A control system based on field programmable gate array for papermaking sewage treatment

International Nuclear Information System (INIS)

Zhang, Zi Sheng; Xie, Chang; Xiong, Yan Qing; Liu, Zhi Qiang; Li, Qing

2013-01-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

All optical programmable logic array (PLA)

Science.gov (United States)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Configuration and debug of field programmable gate arrays using MATLAB[reg)/SIMULINK[reg

International Nuclear Information System (INIS)

Grout, I; Ryan, J; O'Shea, T

2005-01-01

Increasingly, the need to seamlessly link high-level behavioural descriptions of electronic hardware for modelling and simulation purposes to the final application hardware highlights the gap between the high-level behavioural descriptions of the required circuit functionality (considering here digital logic) in commonly used mathematical modelling tools, and the hardware description languages such as VHDL and Verilog-HDL. In this paper, the linking of a MATLAB[reg] model for digital algorithm for implementation on a programmable logic device for design synthesis from the MATLAB[reg] model into VHDL is discussed. This VHDL model is itself synthesised and downloaded to the target Field Programmable Gate Array, for normal operation and also for design debug purposes. To demonstrate this, a circuit architecture mapped from a SIMULINK[reg] model is presented. The rationale is for a seamless interface between the initial algorithm development and the target hardware, enabling the hardware to be debugged and compared to the simulated model from a single interface for use with by a non-expert in the programmable logic and hardware description language use

Development of measurement system for radiation effect on static random access memory based field programmable gate array

International Nuclear Information System (INIS)

Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

2009-01-01

Based on the detailed investigation in field programmable gate array(FPGA) radiation effects theory, a measurement system for radiation effects on static random access memory(SRAM)-based FPGA was developed. The testing principle of internal memory, function and power current was introduced. The hardware and software implement means of system were presented. Some important parameters for radiation effects on SRAM-based FPGA, such as configuration RAM upset section, block RAM upset section, function fault section and single event latchup section can be gained with this system. The transmission distance of the system can be over 50 m and the maximum number of tested gates can reach one million. (authors)

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

Science.gov (United States)

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Stephen Brown

1996-01-01

Full Text Available This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

International Nuclear Information System (INIS)

Hu, Kun; Wang, Xu; Li, Feng; Jin, Ge; Lu, Houbing; Liang, Futian

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability

The impact of software and CAE tools on SEU in field programmable gate arrays

International Nuclear Information System (INIS)

Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

1999-01-01

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

2016-05-15

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Science.gov (United States)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Field-programmable gate array based controller for multi spot light-addressable potentiometric sensors with integrated signal correction mode

Energy Technology Data Exchange (ETDEWEB)

Werner, Carl Frederik; Schusser, Sebastian; Spelthahn, Heiko [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany); Wagner, Torsten; Yoshinobu, Tatsuo [Tohoku University, Department of Electronic Engineering, 6-6-05 Aramaki Aza Aoba, Aoba-ku, Sendai, Miyagi 980-8579 (Japan); Schoening, Michael J., E-mail: schoening@fh-aachen.de [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany)

2011-11-01

Highlights: > Flexible up-scalable design of a light-addressable potentiometric sensor set-up. > Utilisation of a field-programmable gate array to address LAPS measurement spots. > Measurements in amplitude-mode and phase-mode for different pH solutions. > Amplitude, phase and frequency behaviour of LAPS for single and multiple light stimulus. > Signal calibration method by brightness control to compensated systematic errors. - Abstract: A light-addressable potentiometric sensor (LAPS) can measure the concentration of one or several analytes at the sensor surface simultaneously in a spatially resolved manner. A modulated light pointer stimulates the semiconductor structure at the area of interest and a responding photocurrent can be read out. By simultaneous stimulation of several areas with light pointers of different modulation frequencies, the read out can be performed at the same time. With the new proposed controller electronic based on a field-programmable gate array (FPGA), it is possible to control the modulation frequencies, phase shifts, and light brightness of multiple light pointers independently and simultaneously. Thus, it is possible to investigate the frequency response of the sensor, and to examine the analyte concentration by the determination of the surface potential with the help of current/voltage curves and phase/voltage curves. Additionally, the ability to individually change the light intensities of each light pointer is used to perform signal correction.

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

Field programmable gate array reliability analysis using the dynamic flow graph methodology

Energy Technology Data Exchange (ETDEWEB)

McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

2016-10-15

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Design and Implementation of Video Shot Detection on Field Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Jharna Majumdar

2012-09-01

Full Text Available Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays.

CMOS gate array characterization procedures

Science.gov (United States)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants

International Nuclear Information System (INIS)

2016-01-01

Field programmable gate arrays (FPGAs) are gaining increased attention worldwide for application in nuclear power plant (NPP) instrumentation and control (I&C) systems, particularly for safety and safety related applications, but also for non-safety ones. NPP operators and equipment suppliers see potential advantages of FPGA based digital I&C systems as compared to microprocessor based applications. This is because FPGA based systems can be made simpler, more testable and less reliant on complex software (e.g. operating systems), and are easier to qualify for safety and safety related applications. This publication results from IAEA consultancy meetings covering the various aspects, including design, qualification, implementation, licensing, and operation, of FPGA based I&C systems in NPPs

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Science.gov (United States)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Field programmable gate array based reconfigurable scanning probe/optical microscope.

Science.gov (United States)

Nowak, Derek B; Lawrence, A J; Dzegede, Zechariah K; Hiester, Justin C; Kim, Cliff; Sánchez, Erik J

2011-10-01

The increasing popularity of nanometrology and nanospectroscopy has pushed researchers to develop complex new analytical systems. This paper describes the development of a platform on which to build a microscopy tool that will allow for flexibility of customization to suit research needs. The novelty of the described system lies in its versatility of capabilities. So far, one version of this microscope has allowed for successful near-field and far-field fluorescence imaging with single molecule detection sensitivity. This system is easily adapted for reflection, polarization (Kerr magneto-optical (MO)), Raman, super-resolution techniques, and other novel scanning probe imaging and spectroscopic designs. While collecting a variety of forms of optical images, the system can simultaneously monitor topographic information of a sample with an integrated tuning fork based shear force system. The instrument has the ability to image at room temperature and atmospheric pressure or under liquid. The core of the design is a field programmable gate array (FPGA) data acquisition card and a single, low cost computer to control the microscope with analog control circuitry using off-the-shelf available components. A detailed description of electronics, mechanical requirements, and software algorithms as well as examples of some different forms of the microscope developed so far are discussed.

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

Energy Technology Data Exchange (ETDEWEB)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Katori, Hidetoshi [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656 (Japan); Department of Applied Physics, Graduate School of Engineering, The University of Tokyo, Bunkyo-ku, Tokyo 113-8656 (Japan)

2015-11-15

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

Science.gov (United States)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

International Nuclear Information System (INIS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-01-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

CERN Document Server

Sivasubramaniyan, Sriram

Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

Science.gov (United States)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Science.gov (United States)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A new data acquisition and imaging system for nuclear microscopy based on a Field Programmable Gate Array card

International Nuclear Information System (INIS)

Bettiol, A.A.; Udalagama, C.; Watt, F.

2009-01-01

The introduction of the new Field Programmable Gate Array (FPGA) cards by National Instruments has made it possible for the first time to develop reconfigurable custom data acquisition hardware easily with the LabVIEW programming environment. Data acquisition issues such as precise timing for scanning and operating system latencies can now be easily overcome using this new technology because the data acquisition software is embedded in the FPGA chip on the card. In this paper we present the first results of the new data acquisition system developed at the Centre for Ion Beam Applications (CIBA), National University of Singapore using the new National Instruments cards in conjunction with rack mountable Wilkinson type ADCs.

Design of a Tritium-in-air-monitor using field programmable gate arrays

International Nuclear Information System (INIS)

McNelles, Phillip; Lu, Lixuan

2015-01-01

Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

Development and simulation of soft morphological operators for a field programmable gate array

Science.gov (United States)

Tickle, Andrew J.; Harvey, Paul K.; Smith, Jeremy S.; Wu, Q. Henry

2013-04-01

In image processing applications, soft mathematical morphology (MM) can be employed for both binary and grayscale systems and is derived from set theory. Soft MM techniques have improved behavior over standard morphological operations in noisy environments, as they can preserve small details within an image. This makes them suitable for use in image processing applications on portable field programmable gate arrays for tasks such as robotics and security. We explain how the systems were developed using Altera's DSP Builder in order to provide optimized code for the many different devices currently on the market. Also included is how the circuits can be inserted and combined with previously developed work in order to increase their functionality. The testing procedures involved loading different images into these systems and analyzing the outputs against MATLAB-generated validation images. A set of soft morphological operations are described, which can then be applied to various tasks and easily modified in size via altering the line buffer settings inside the system to accommodate a range of image attributes ranging from image sizes such as 320×240 pixels for basic webcam imagery up to high quality 4000×4000 pixel images for military applications.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Xu Zhouxiang; Zhang Xian; Huang Kaikai; Lu Xuanhui [Physics Department, Zhejiang University, Hangzhou, 310027 (China)

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

Energy Technology Data Exchange (ETDEWEB)

O' Gorman, T.; Gibson, K. J.; Snape, J. A. [York Plasma Institute, Department of Physics, University of York, York YO10 5DD (United Kingdom); Naylor, G.; Huang, B.; McArdle, G. J.; Scannell, R.; Shibaev, S.; Thomas-Davies, N. [EURATOM/CCFE Fusion Association, Culham Science Centre, Oxfordshire OX14 3DB (United Kingdom)

2012-10-15

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate trigger from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.

Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

Energy Technology Data Exchange (ETDEWEB)

Learn, Mark Walter

2012-01-01

The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

Field programmable gate array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

DEFF Research Database (Denmark)

Thrane, Lars; Larsen, Henning Engelbrecht; Norozi, Kambiz

2009-01-01

efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation......We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows...

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA; Desenvolvimento de sistema de protecao para reator nuclear de pesquisa baseado em Field Programmable Gate Array - FPGA

Energy Technology Data Exchange (ETDEWEB)

Martins, Roque Hudson da Silva

2016-07-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

Energy Technology Data Exchange (ETDEWEB)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars [Solid State Physics, Nanometer Structure Consortium, Lund University, Box 118, S-221 00 Lund (Sweden)

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Development of field programmable gate array-based reactor trip functions using systems engineering approach

Energy Technology Data Exchange (ETDEWEB)

Jung, Jae Cheon; Ahmed, Ibrahim [Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

2016-08-15

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

Design of acoustic logging signal source of imitation based on field programmable gate array

Science.gov (United States)

Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

2014-08-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

Science.gov (United States)

Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

2017-01-01

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

Science.gov (United States)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Directory of Open Access Journals (Sweden)

Ion Stiharu

2010-08-01

Full Text Available Computer numerically controlled (CNC machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA-based sensor node.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Science.gov (United States)

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Science.gov (United States)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Nolida Yussup; Maslina Mohd Ibrahim; Lojius Lombigit; Nur Aira Abdul Rahman; Muhammad Rawi Mohamed Zin

2013-01-01

Full-text: Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed. (author)

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-01-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed

Use of Field Programmable Gate Array Technology in Future Space Avionics

Science.gov (United States)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Development of multi-channel gated integrator and PXI-DAQ system for nuclear detector arrays

International Nuclear Information System (INIS)

Kong Jie; Su Hong; Chen Zhiqiang; Dong Chengfu; Qian Yi; Gao Shanshan; Zhou Chaoyang; Lu Wan; Ye Ruiping; Ma Junbing

2010-01-01

A multi-channel gated integrator and PXI based data acquisition system have been developed for nuclear detector arrays with hundreds of detector units. The multi-channel gated integrator can be controlled by a programmable GI controller. The PXI-DAQ system consists of NI PXI-1033 chassis with several PXI-DAQ cards. The system software has a user-friendly GUI which is written in C language using LabWindows/CVI under Windows XP operating system. The performance of the PXI-DAQ system is very reliable and capable of handling event rate up to 40 kHz.

Design of acoustic logging signal source of imitation based on field programmable gate array

International Nuclear Information System (INIS)

Zhang, K; Ju, X D; Lu, J Q; Men, B Y

2014-01-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

SWNT array resonant gate MOS transistor.

Science.gov (United States)

Arun, A; Campidelli, S; Filoramo, A; Derycke, V; Salet, P; Ionescu, A M; Goffman, M F

2011-02-04

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

SWNT array resonant gate MOS transistor

International Nuclear Information System (INIS)

Arun, A; Salet, P; Ionescu, A M; Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F

2011-01-01

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

International Nuclear Information System (INIS)

Chen, Yuan-Ho

2017-01-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

Energy Technology Data Exchange (ETDEWEB)

Shan, Jaffry Syed [Hamdard University, Karachi (Pakistan); Abbas, Syed Haider; Lee, Jung Ryul [Dept. of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Kang, Dong Hoon [Advanced Materials Research Team, Korea Railroad Research Institute, Uiwang (Korea, Republic of)

2015-12-15

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm{sup 2} with 0.5 mm interval) to 87.5% (scanning of 200x200mm{sup 2} with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

International Nuclear Information System (INIS)

Shan, Jaffry Syed; Abbas, Syed Haider; Lee, Jung Ryul; Kang, Dong Hoon

2015-01-01

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm 2 with 0.5 mm interval) to 87.5% (scanning of 200x200mm 2 with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

Energy Technology Data Exchange (ETDEWEB)

Chen, Yuan-Ho, E-mail: chenyh@mail.cgu.edu.tw [Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Department of Radiation Oncology, Chang Gung Memorial Hospital, Tao-Yuan 333, Taiwan (China); Center for Reliability Sciences and Technologies, Chang Gung University, Tao-Yuan 333, Taiwan (China)

2017-05-11

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA

International Nuclear Information System (INIS)

Martins, Roque Hudson da Silva

2016-01-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

Science.gov (United States)

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

SWNT array resonant gate MOS transistor

Energy Technology Data Exchange (ETDEWEB)

Arun, A; Salet, P; Ionescu, A M [NanoLab, Ecole Polytechnique Federale de Lausanne, CH-1015, Lausanne (Switzerland); Campidelli, S; Filoramo, A; Derycke, V; Goffman, M F, E-mail: marcelo.goffman@cea.fr [Laboratoire d' Electronique Moleculaire, SPEC (CNRS URA 2454), IRAMIS, CEA, Gif-sur-Yvette (France)

2011-02-04

We show that thin horizontal arrays of single wall carbon nanotubes (SWNTs) suspended above the channel of silicon MOSFETs can be used as vibrating gate electrodes. This new class of nano-electromechanical system (NEMS) combines the unique mechanical and electronic properties of SWNTs with an integrated silicon-based motion detection. Its electrical response exhibits a clear signature of the mechanical resonance of SWNT arrays (120-150 MHz) showing that these thin horizontal arrays behave as a cohesive, rigid and elastic body membrane with a Young's modulus in the order of 1-10 GPa and ultra-low mass. The resonant frequency can be tuned by the gate voltage and its dependence is well understood within the continuum mechanics framework.

Compensated readout for high-density MOS-gated memristor crossbar array

KAUST Repository

Zidan, Mohammed A.

2015-01-01

Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.

Theory and implementation of a very high throughput true random number generator in field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong; Xu, Chao [Department of Modern Physics, University of Science and Technology of China, Hefei 230026 (China)

2016-04-15

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

Science.gov (United States)

Kyrkou, Christos; Theocharides, Theocharis

2016-07-01

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

Isotropic gates and large gamma detector arrays versus angular distributions

International Nuclear Information System (INIS)

Iacob, V.E.; Duchene, G.

1997-01-01

Angular information extracted from in-beam γ ray measurements are of great importance for γ ray multipolarity and nuclear spin assignments. In our days large Ge detector arrays became available allowing the measurements of extremely weak γ rays in almost 4π sr solid angle (e.g., EUROGAM detector array). Given the high detector efficiency it is common for the mean suppressed coincidence multiplicity to reach values as high as 4 to 6. Thus, it is possible to gate on particular γ rays in order to enhance the relative statistics of a definite reaction channel and/or a definite decaying path in the level scheme of the selected residual nucleus. As compared to angular correlations, the conditioned angular distribution spectra exhibit larger statistics because in the latter the gate-setting γ ray may be observed by all the detectors in the array, relaxing somehow the geometrical restrictions of the angular correlations. Since the in-beam γ ray emission is anisotropic one could inquire that gate setting as mentioned above, based on anisotropic γ ray which would perturb the angular distributions in the unfolded events. As our work proved, there is no reason to worry about this if the energy gate runs over the whole solid angle in an ideal 4π sr detector, i.e., if the gate is isotropic. In real quasi 4π sr detector arrays the corresponding quasi isotropic gate preserves the angular properties of the unfolded data, too. However extraction of precise angular distribution coefficient especially a 4 , requires the consideration of the deviation of the quasi isotropic gate relative to the (ideal) isotropic gate

Fringe pattern demodulation using the one-dimensional continuous wavelet transform: field-programmable gate array implementation.

Science.gov (United States)

Abid, Abdulbasit

2013-03-01

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation

Directory of Open Access Journals (Sweden)

Arati M. Dixit

2013-01-01

Full Text Available The real-time nondestructive testing (NDT for crack detection and impact source identification (CDISI has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL. The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

Developing a gate-array capability at a research and development laboratory

Science.gov (United States)

Balch, J. W.; Current, K. W.; Magnuson, W. G., Jr.; Pocha, M. D.

1983-03-01

Experiences in developing a gate array capability for low volume applications in a research and development (R and D) laboratory are described. By purchasing unfinished wafers and doing the customization steps in-house. Turnaround time was shortened to as little as one week and the direct costs reduced to as low as $5K per design. Designs generally require fast turnaround (a few weeks to a few months) and very low volumes (1 to 25). Design costs must be kept at a minimum. After reviewing available commercial gate array design and fabrication services, it was determined that objectives would best be met by using existing internal integrated circuit fabrication facilities, the COMPUTERVISION interactive graphics layout system, and extensive computational capabilities. The reasons and the approach taken for; selection for a particular gate array wafer, adapting a particular logic simulation program, and how layout aids were enhanced are discussed. Testing of the customized chips is described. The content, schedule, and results of the internal gate array course recently completed are discussed. Finally, problem areas and near term plans are presented.

Gate protective device for SOS array

Science.gov (United States)

Meyer, J. E., Jr.; Scott, J. H.

1972-01-01

Protective gate device consisting of alternating heavily doped n(+) and p(+) diffusions eliminates breakdown voltages in silicon oxide on sapphire arrays caused by electrostatic discharge from person or equipment. Diffusions are easily produced during normal double epitaxial processing. Devices with nine layers had 27-volt breakdown.

Failure mode taxonomy for assessing the reliability of Field Programmable Gate Array based Instrumentation and Control systems

International Nuclear Information System (INIS)

McNelles, Phillip; Zeng, Zhao Chang; Renganathan, Guna; Chirila, Marius; Lu, Lixuan

2017-01-01

Highlights: • The use FPGAs in I&C systems in Nuclear Power Plants is an important issue (IAEA). • OECD-NEA published a failure mode taxonomy for software-based digital I&C systems. • This paper extends the OECD-NEA taxonomy to model FPGA-based systems. • FPGA failure modes, failure effects, uncovering methods are categorized/described. • Provides an example of modelling an FPGA-Based RTS/ESFAS using the FPGA taxonomy. - Abstract: Field Programmable Gate Arrays (FPGAs) are a form of programmable digital hardware configured to perform digital logic functions. This configuration (programming) is performed using Hardware Description Language (HDL), making FPGAs a form of HDL Programmed Device (HPD). In the nuclear field, FPGAs have seen use in upgrades and replacements of obsolete Instrumentation and Control (I&C) systems. This paper expands upon previous work that resulted in extensive FPGA failure mode data, to allow for the application of the OECD-NEA failure modes taxonomy. The OECD-NEA taxonomy presented a method to model digital (software-based) I&C systems, based on the hardware and software failure modes, failure uncovering effects and levels of abstraction, using a Reactor Trip System/Engineering Safety Feature Actuation System (RTS/ESFAS) as an example system. To create the FPGA taxonomy, this paper presents an additional “sub-component” level of abstraction, to demonstrate the effect of the FPGA failure modes and failure categories on an FPGA-based system. The proposed FPGA taxonomy is based on the FPGA failure modes, failure categories, failure effects and uncovering situations. The FPGA taxonomy is applied to the RTS/ESFAS test system, to demonstrate the effects of the anticipated FPGA failure modes on a digital I&C system, and to provide a modelling example for this proposed taxonomy.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

Science.gov (United States)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

International Nuclear Information System (INIS)

Szplet, R; Kalisz, J; Jachna, Z

2009-01-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second

Field programmable gate array based hardware implementation of a gradient filter for edge detection in colour images with subpixel precision

International Nuclear Information System (INIS)

Schellhorn, M; Rosenberger, M; Correns, M; Blau, M; Goepfert, A; Rueckwardt, M; Linss, G

2010-01-01

Within the field of industrial image processing the use of colour cameras becomes ever more common. Increasingly the established black and white cameras are replaced by economical single-chip colour cameras with Bayer pattern. The use of the additional colour information is particularly important for recognition or inspection. Become interesting however also for the geometric metrology, if measuring tasks can be solved more robust or more exactly. However only few suitable algorithms are available, in order to detect edges with the necessary precision. All attempts require however additional computation expenditure. On the basis of a new filter for edge detection in colour images with subpixel precision, the implementation on a pre-processing hardware platform is presented. Hardware implemented filters offer the advantage that they can be used easily with existing measuring software, since after the filtering a single channel image is present, which unites the information of all colour channels. Advanced field programmable gate arrays represent an ideal platform for the parallel processing of multiple channels. The effective implementation presupposes however a high programming expenditure. On the example of the colour filter implementation, arising problems are analyzed and the chosen solution method is presented.

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

International Nuclear Information System (INIS)

Azarbayejani, M; Jalalpour, M; Reda Taha, M M; El-Osery, A I

2011-01-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide

Field application of smart SHM using field programmable gate array technology to monitor an RC bridge in New Mexico

Science.gov (United States)

Azarbayejani, M.; Jalalpour, M.; El-Osery, A. I.; Reda Taha, M. M.

2011-08-01

In this paper, an innovative field application of a structural health monitoring (SHM) system using field programmable gate array (FPGA) technology and wireless communication is presented. The new SHM system was installed to monitor a reinforced concrete (RC) bridge on Interstate 40 (I-40) in Tucumcari, New Mexico. This newly installed system allows continuous remote monitoring of this bridge using solar power. Details of the SHM component design and installation are discussed. The integration of FPGA and solar power technologies make it possible to remotely monitor infrastructure with limited access to power. Furthermore, the use of FPGA technology enables smart monitoring where data communication takes place on-need (when damage warning signs are met) and on-demand for periodic monitoring of the bridge. Such a system enables a significant cut in communication cost and power demands which are two challenges during SHM operation. Finally, a three-dimensional finite element (FE) model of the bridge was developed and calibrated using a static loading field test. This model is then used for simulating damage occurrence on the bridge. Using the proposed automation process for SHM will reduce human intervention significantly and can save millions of dollars currently spent on prescheduled inspection of critical infrastructure worldwide.

Programmable architecture for quantum computing

NARCIS (Netherlands)

Chen, J.; Wang, L.; Charbon, E.; Wang, B.

2013-01-01

A programmable architecture called “quantum FPGA (field-programmable gate array)” (QFPGA) is presented for quantum computing, which is a hybrid model combining the advantages of the qubus system and the measurement-based quantum computation. There are two kinds of buses in QFPGA, the local bus and

Increasing feasibility of the field-programmable gate array implementation of an iterative image registration using a kernel-warping algorithm

Science.gov (United States)

Nguyen, An Hung; Guillemette, Thomas; Lambert, Andrew J.; Pickering, Mark R.; Garratt, Matthew A.

2017-09-01

Image registration is a fundamental image processing technique. It is used to spatially align two or more images that have been captured at different times, from different sensors, or from different viewpoints. There have been many algorithms proposed for this task. The most common of these being the well-known Lucas-Kanade (LK) and Horn-Schunck approaches. However, the main limitation of these approaches is the computational complexity required to implement the large number of iterations necessary for successful alignment of the images. Previously, a multi-pass image interpolation algorithm (MP-I2A) was developed to considerably reduce the number of iterations required for successful registration compared with the LK algorithm. This paper develops a kernel-warping algorithm (KWA), a modified version of the MP-I2A, which requires fewer iterations to successfully register two images and less memory space for the field-programmable gate array (FPGA) implementation than the MP-I2A. These reductions increase feasibility of the implementation of the proposed algorithm on FPGAs with very limited memory space and other hardware resources. A two-FPGA system rather than single FPGA system is successfully developed to implement the KWA in order to compensate insufficiency of hardware resources supported by one FPGA, and increase parallel processing ability and scalability of the system.

Programmable cellular arrays. Faults testing and correcting in cellular arrays

International Nuclear Information System (INIS)

Cercel, L.

1978-03-01

A review of some recent researches about programmable cellular arrays in computing and digital processing of information systems is presented, and includes both combinational and sequential arrays, with full arbitrary behaviour, or which can realize better implementations of specialized blocks as: arithmetic units, counters, comparators, control systems, memory blocks, etc. Also, the paper presents applications of cellular arrays in microprogramming, in implementing of a specialized computer for matrix operations, in modeling of universal computing systems. The last section deals with problems of fault testing and correcting in cellular arrays. (author)

Solar cell array for driving MOS type FET gate. MOS gata EFT gate kudoyo taiyo denchi array

Energy Technology Data Exchange (ETDEWEB)

Murakami, S; Yoshida, K; Yoshiki, T; Yamaguchi, Y; Nakayama, T; Owada, Y

1990-03-12

There has been a semiconductor relay utilizing MOS type FET (field effect transistor). Concerning the solar cells used for a semiconductor relay, it is required to separate the cells by forming insulating oxide films first and to form semiconductor layers by using many mask patterns, since a crystal semiconductor is used. Thereby its manufacturing process becomes complicated and laminification as well as thin film formation are difficult, In view of the above, this invention proposes a solar cell array for driving a MOS type FET gate consisting of amorphous silicon semiconductor cells, which are used for a semiconductor relay with solar cells generating electromotive power by the light of a light emitting diode and a MOS type FET that the power output of the above solar cells is supplied to its gate, and which are connected in series with many steps. 9 figs.

Image processing with cellular nonlinear networks implemented on field-programmable gate arrays for real-time applications in nuclear fusion

International Nuclear Information System (INIS)

Palazzo, S.; Vagliasindi, G.; Arena, P.; Murari, A.; Mazon, D.; De Maack, A.

2010-01-01

In the past years cameras have become increasingly common tools in scientific applications. They are now quite systematically used in magnetic confinement fusion, to the point that infrared imaging is starting to be used systematically for real-time machine protection in major devices. However, in order to guarantee that the control system can always react rapidly in case of critical situations, the time required for the processing of the images must be as predictable as possible. The approach described in this paper combines the new computational paradigm of cellular nonlinear networks (CNNs) with field-programmable gate arrays and has been tested in an application for the detection of hot spots on the plasma facing components in JET. The developed system is able to perform real-time hot spot recognition, by processing the image stream captured by JET wide angle infrared camera, with the guarantee that computational time is constant and deterministic. The statistical results obtained from a quite extensive set of examples show that this solution approximates very well an ad hoc serial software algorithm, with no false or missed alarms and an almost perfect overlapping of alarm intervals. The computational time can be reduced to a millisecond time scale for 8 bit 496x560-sized images. Moreover, in our implementation, the computational time, besides being deterministic, is practically independent of the number of iterations performed by the CNN - unlike software CNN implementations.

Innovative Columnar Type of Grid Array SJ BIST HALT Method, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop will develop a superior method for testing and qualifying columnar type of grid arrays such as field programmable gate arrays (FPGAs) packaged in column...

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

Energy Technology Data Exchange (ETDEWEB)

Ahmed, Ibrahim [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of); Jung, Jaecheon, E-mail: jcjung@kings.ac.kr [Department of Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, 658-91 Haemaji-ro, Seosang-myeon, Ulju-gun, Ulsan 45014 (Korea, Republic of); Heo, Gyunyoung [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of)

2017-06-15

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jaecheon; Heo, Gyunyoung

2017-01-01

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

Science.gov (United States)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

Science.gov (United States)

Berger, Andrew J; Page, Michael R; Jacob, Jan; Young, Justin R; Lewis, Jim; Wenzel, Lothar; Bhallamudi, Vidya P; Johnston-Halperin, Ezekiel; Pelekhov, Denis V; Hammel, P Chris

2014-12-01

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

Development of field programmable gate array–based encryption module to mitigate man-in-the-middle attack for nuclear power plant data communication network

Directory of Open Access Journals (Sweden)

Mohamed Abdallah Elakrat

2018-06-01

Full Text Available This article presents a security module based on a field programmable gate array (FPGA to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA. Keywords: AES-128, Cyber Security, Encryption, Field Programmable Gate Array, I&C

Isotropic gates in large gamma detector arrays versus angular distributions

International Nuclear Information System (INIS)

Iacob, V.E.; Duchene, G.

1997-01-01

The quality of the angular distribution information extracted from high-fold gamma-gamma coincidence events is analyzed. It is shown that a correct quasi-isotropic gate setting, available at the modern large gamma-ray detector arrays, essentially preserves the quality of the angular information. (orig.)

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

Science.gov (United States)

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Energy Technology Data Exchange (ETDEWEB)

Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

2013-12-23

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

Programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-04-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

A programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-01-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Photon-Counting Arrays for Time-Resolved Imaging

Directory of Open Access Journals (Sweden)

I. Michel Antolovic

2016-06-01

Full Text Available The paper presents a camera comprising 512 × 128 pixels capable of single-photon detection and gating with a maximum frame rate of 156 kfps. The photon capture is performed through a gated single-photon avalanche diode that generates a digital pulse upon photon detection and through a digital one-bit counter. Gray levels are obtained through multiple counting and accumulation, while time-resolved imaging is achieved through a 4-ns gating window controlled with subnanosecond accuracy by a field-programmable gate array. The sensor, which is equipped with microlenses to enhance its effective fill factor, was electro-optically characterized in terms of sensitivity and uniformity. Several examples of capture of fast events are shown to demonstrate the suitability of the approach.

A prototype of programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Dell'Orso, M.

1999-01-01

The authors present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into Field Programmable Gate Arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows them to keep up smoothly with technology improvements. A 64 PAM array has been assembled on a prototype VME board and fully tested up to 30 MHz

Physiologically gated microbeam radiation using a field emission x-ray source array

Energy Technology Data Exchange (ETDEWEB)

Chtcheprov, Pavel, E-mail: PavelC@unc.edu, E-mail: zhou@email.unc.edu [Department of Biomedical Engineering, University of North Carolina, 152 MacNider Hall, Campus Box 7575, Chapel Hill, North Carolina 27599 (United States); Burk, Laurel; Inscoe, Christina; Ger, Rachel; Hadsell, Michael; Lu, Jianping [Department of Physics and Astronomy, University of North Carolina, Phillips Hall, CB #3255, 120 East Cameron Avenue, Chapel Hill, North Carolina 27599 (United States); Yuan, Hong [Department of Radiology, University of North Carolina, 2006 Old Clinic, CB #7510, Chapel Hill, North Carolina 27599 (United States); Zhang, Lei [Department of Applied Physical Sciences, University of North Carolina, Chapman Hall, CB#3216, Chapel Hill, North Carolina 27599 (United States); Chang, Sha [Department of Radiation Oncology, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 and UNC Lineberger Comprehensive Cancer Center, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 (United States); Zhou, Otto, E-mail: PavelC@unc.edu, E-mail: zhou@email.unc.edu [Department of Physics and Astronomy, University of North Carolina, Phillips Hall, CB #3255, 120 East Cameron Avenue, Chapel Hill, North Carolina 27599 and UNC Lineberger Comprehensive Cancer Center, University of North Carolina, 101 Manning Drive, Chapel Hill, North Carolina 27514 (United States)

2014-08-15

Purpose: Microbeam radiation therapy (MRT) uses narrow planes of high dose radiation beams to treat cancerous tumors. This experimental therapy method based on synchrotron radiation has been shown to spare normal tissue at up to 1000 Gy of peak entrance dose while still being effective in tumor eradication and extending the lifetime of tumor-bearing small animal models. Motion during treatment can lead to significant movement of microbeam positions resulting in broader beam width and lower peak to valley dose ratio (PVDR), which reduces the effectiveness of MRT. Recently, the authors have demonstrated the feasibility of generating microbeam radiation for small animal treatment using a carbon nanotube (CNT) x-ray source array. The purpose of this study is to incorporate physiological gating to the CNT microbeam irradiator to minimize motion-induced microbeam blurring. Methods: The CNT field emission x-ray source array with a narrow line focal track was operated at 160 kVp. The x-ray radiation was collimated to a single 280 μm wide microbeam at entrance. The microbeam beam pattern was recorded using EBT2 Gafchromic{sup ©} films. For the feasibility study, a strip of EBT2 film was attached to an oscillating mechanical phantom mimicking mouse chest respiratory motion. The servo arm was put against a pressure sensor to monitor the motion. The film was irradiated with three microbeams under gated and nongated conditions and the full width at half maximums and PVDRs were compared. An in vivo study was also performed with adult male athymic mice. The liver was chosen as the target organ for proof of concept due to its large motion during respiration compared to other organs. The mouse was immobilized in a specialized mouse bed and anesthetized using isoflurane. A pressure sensor was attached to a mouse's chest to monitor its respiration. The output signal triggered the electron extraction voltage of the field emission source such that x-ray was generated only

Direct protein detection with a nano-interdigitated array gate MOSFET.

Science.gov (United States)

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

A programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Donati, S.; Galeotti, S.; Giannetti, P.; Morsani, F.; Passuello, D.; Spinella, F.; Cerri, A.; Punzi, G.; Ristori, L.; Dell'Orso, M.; Meschi, E.; Leger, A.; Speer, T.; Wu, X.

1998-01-01

We present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into field programmable gate arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows to keep up smoothly with technology improvements. (orig.)

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Science.gov (United States)

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

Directory of Open Access Journals (Sweden)

Santiago T. Pérez Suárez

2013-12-01

Full Text Available This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

CERN Document Server

Bonacini, Sandro; Kloukinas, Kostas

2007-01-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

Science.gov (United States)

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

A high performance gate drive for large gate turn off thyristors

Energy Technology Data Exchange (ETDEWEB)

Szilagyi, C.P.

1993-01-01

Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

The Bill & Melinda Gates Foundation's grant-making programme for global health.

Science.gov (United States)

McCoy, David; Kembhavi, Gayatri; Patel, Jinesh; Luintel, Akish

2009-05-09

The Bill & Melinda Gates Foundation is a major contributor to global health; its influence on international health policy and the design of global health programmes and initiatives is profound. Although the foundation's contribution to global health generally receives acclaim, fairly little is known about its grant-making programme. We undertook an analysis of 1094 global health grants awarded between January, 1998, and December, 2007. We found that the total value of these grants was US$8.95 billion, of which $5.82 billion (65%) was shared by only 20 organisations. Nevertheless, a wide range of global health organisations, such as WHO, the GAVI Alliance, the World Bank, the Global Fund to Fight AIDS, Tuberculosis and Malaria, prominent universities, and non-governmental organisations received grants. $3.62 billion (40% of all funding) was given to supranational organisations. Of the remaining amount, 82% went to recipients based in the USA. Just over a third ($3.27 billion) of funding was allocated to research and development (mainly for vaccines and microbicides), or to basic science research. The findings of this report raise several questions about the foundation's global health grant-making programme, which needs further research and assessment.

Universal programmable quantum circuit schemes to emulate an operator

Energy Technology Data Exchange (ETDEWEB)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)

2012-12-21

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Universal programmable quantum circuit schemes to emulate an operator

International Nuclear Information System (INIS)

Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre

2012-01-01

Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.

Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array; Modelagem de funcoes criticas de reatores nucleares utilizando Fild Programmable Gate Array

Energy Technology Data Exchange (ETDEWEB)

Teixeira, Pamela Iara Nolasco

2016-07-01

This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

CERN Document Server

Silvestri, M; Gerardin, Simone; Faccio, Federico; Paccagnella, Alessandro

2010-01-01

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO2), and practically no change for 100 Mrad(SiO2) irradiation, dose of interest for the future super large hadron collider (SLHC).

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

Science.gov (United States)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Design Principles of A Sigma-delta Flux-gate Magnetometer

Science.gov (United States)

Magnes, W.; Valavanoglou, A.; Pierce, D.; Frank, A.; Schwingenschuh, K.

A state-of-the-art flux-gate magnetometer is characterised by magnetic field resolution of several pT in a wide frequency range, low power consumption, low weight and high robustness. Therefore, flux-gate magnetometers are frequently used for ground-based Earth's field observation as well as for measurements aboard scientific space missions. But both traditional analogue and recently developed digital flux-gate magnetometers need low power and high-resolution analogue-to-digital converters for signal quan- tization. The disadvantage of such converters is the low radiation hardness. This fact has led to the idea of combining a traditional analogue flux-gate regulation circuit with that of a discretely realized sigma-delta converter in order to get a radiation hard and further miniaturized magnetometer. The name sigma-delta converter is derived from putting an integrator in front of a 1-bit delta modulator which forms the sigma-delta loop. It is followed by a digital decimation filter realized in a field-programmable gate array (FPGA). The flux-gate regulation and the sigma-delta loop are quite similar in the way of realizing the integrator and feedback circuit, which makes it easy to com- bine these two systems. The presented talk deals with the design principles and the results of a first bread board model.

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

Science.gov (United States)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Biological applications of an LCoS-BASED PROGRAMMABLE ARRAY MICROSCOPE (PAM)

NARCIS (Netherlands)

Hagen, G.M.; Caarls, W.; Thomas, M.; Hill, A.; Lidke, K.A.; Rieger, B.; Fritsch, C.; Van Geest, B.; Jovin, T.M.; Arndt-Jovin, D.J.

2007-01-01

We report on a new generation, commercial prototype of a programmable array optical sectioning fluorescence microscope (PAM) for rapid, light efficient 3D imaging of living specimens. The stand-alone module, including light source(s) and detector(s), features an innovative optical design and a

Mechanical design of SST-GATE, a dual-mirror telescope for the Cherenkov Telescope Array

Science.gov (United States)

Dournaux, Jean-Laurent; Huet, Jean-Michel; Amans, Jean-Philippe; Dumas, Delphine; Laporte, Philippe; Sol, Hélène; Blake, Simon

2014-07-01

The Cherenkov Telescope Array (CTA) project aims to create the next generation Very High Energy (VHE) gamma-ray telescope array. It will be devoted to the observation of gamma rays over a wide band of energy, from a few tens of GeV to more than 100 TeV. Two sites are foreseen to view the whole sky where about 100 telescopes, composed of three different classes, related to the specific energy region to be investigated, will be installed. Among these, the Small Size class of Telescopes, SSTs, are devoted to the highest energy region, to beyond 100 TeV. Due to the large number of SSTs, their unit cost is an important parameter. At the Observatoire de Paris, we have designed a prototype of a Small Size Telescope named SST-GATE, based on the dual-mirror Schwarzschild-Couder optical formula, which has never before been implemented in the design of a telescope. Over the last two years, we developed a mechanical design for SST-GATE from the optical and preliminary mechanical designs made by the University of Durham. The integration of this telescope is currently in progress. Since the early stages of mechanical design of SST-GATE, finite element method has been used employing shape and topology optimization techniques to help design several elements of the telescope. This allowed optimization of the mechanical stiffness/mass ratio, leading to a lightweight and less expensive mechanical structure. These techniques and the resulting mechanical design are detailed in this paper. We will also describe the finite element analyses carried out to calculate the mechanical deformations and the stresses in the structure under observing and survival conditions.

Experimental investigation of localized stress-induced leakage current distribution in gate dielectrics using array test circuit

Science.gov (United States)

Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi

2018-04-01

Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.

FPGAs for software programmers

CERN Document Server

Hannig, Frank; Ziener, Daniel

2016-01-01

This book makes powerful Field Programmable Gate Array (FPGA) and reconfigurable technology accessible to software engineers by covering different state-of-the-art high-level synthesis approaches (e.g., OpenCL and several C-to-gates compilers). It introduces FPGA technology, its programming model, and how various applications can be implemented on FPGAs without going through low-level hardware design phases. Readers will get a realistic sense for problems that are suited for FPGAs and how to implement them from a software designer’s point of view. The authors demonstrate that FPGAs and their programming model reflect the needs of stream processing problems much better than traditional CPU or GPU architectures, making them well-suited for a wide variety of systems, from embedded systems performing sensor processing to large setups for Big Data number crunching. This book serves as an invaluable tool for software designers and FPGA design engineers who are interested in high design productivity through behavi...

A FPGA-based signal processing unit for a GEM array detector

International Nuclear Information System (INIS)

Yen, W.W.; Chou, H.P.

2013-06-01

in the present study, a signal processing unit for a GEM one-dimensional array detector is presented to measure the trajectory of photoelectrons produced by cosmic X-rays. The present GEM array detector system has 16 signal channels. The front-end unit provides timing signals from trigger units and energy signals from charge sensitive amplifies. The prototype of the processing unit is implemented using commercial field programmable gate array circuit boards. The FPGA based system is linked to a personal computer for testing and data analysis. Tests using simulated signals indicated that the FPGA-based signal processing unit has a good linearity and is flexible for parameter adjustment for various experimental conditions (authors)

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

The Advanced Gamma-ray Imaging System (AGIS): Real Time Stereoscopic Array Trigger

Science.gov (United States)

Byrum, K.; Anderson, J.; Buckley, J.; Cundiff, T.; Dawson, J.; Drake, G.; Duke, C.; Haberichter, B.; Krawzcynski, H.; Krennrich, F.; Madhavan, A.; Schroedter, M.; Smith, A.

2009-05-01

Future large arrays of Imaging Atmospheric Cherenkov telescopes (IACTs) such as AGIS and CTA are conceived to comprise of 50 - 100 individual telescopes each having a camera with 10**3 to 10**4 pixels. To maximize the capabilities of such IACT arrays with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We describe the design of a stereoscopic array trigger that calculates image parameters and then correlates them across a subset of telescopes. Fast Field Programmable Gate Array technology allows to use lookup tables at the array trigger level to form a real-time pattern recognition trigger tht capitalizes on the multiple view points of the shower at different shower core distances. A proof of principle system is currently under construction. It is based on 400 MHz FPGAs and the goal is for camera trigger rates of up to 10 MHz and a tunable cosmic-ray background suppression at the array level.

Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

Directory of Open Access Journals (Sweden)

Pankiewicz Bogdan

2017-03-01

Full Text Available In this paper a programmable input mode instrumentation amplifier (IA utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA, which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC. IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

National Research Council Canada - National Science Library

Mumbru, Jose

2004-01-01

... holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors and logic circuitry can better utilize the high parallelism inherent in holographic modules...

High-throughput gated photon counter with two detection windows programmable down to 70 ps width

Energy Technology Data Exchange (ETDEWEB)

Boso, Gianluca; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Zappa, Franco [Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Mora, Alberto Dalla [Dipartimento di Fisica, Politecnico di Milano, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy)

2014-01-15

We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer.

High-throughput gated photon counter with two detection windows programmable down to 70 ps width

International Nuclear Information System (INIS)

Boso, Gianluca; Tosi, Alberto; Zappa, Franco; Mora, Alberto Dalla

2014-01-01

We present the design and characterization of a high-throughput gated photon counter able to count electrical pulses occurring within two well-defined and programmable detection windows. We extensively characterized and validated this instrument up to 100 Mcounts/s and with detection window width down to 70 ps. This instrument is suitable for many applications and proves to be a cost-effective and compact alternative to time-correlated single-photon counting equipment, thanks to its easy configurability, user-friendly interface, and fully adjustable settings via a Universal Serial Bus (USB) link to a remote computer

The Advanced Gamma-ray Imaging System (AGIS): Topological Array Trigger

Science.gov (United States)

Smith, Andrew W.

2010-03-01

AGIS is a concept for the next-generation ground-based gamma-ray observatory. It will be an array of 36 imaging atmospheric Cherenkov telescopes (IACTs) sensitive in the energy range from 50 GeV to 200 TeV. The required improvements in sensitivity, angular resolution, and reliability of operation relative to the present generation instruments imposes demanding technological and cost requirements on the design of the telescopes and on the triggering and readout systems for AGIS. To maximize the capabilities of large arrays of IACTs with a low energy threshold, a wide field of view and a low background rate, a sophisticated array trigger is required. We outline the status of the development of a stereoscopic array trigger that calculates image parameters and correlates them across a subset of telescopes. Field Programmable Gate Arrays (FPGAs) implement the real-time pattern recognition to suppress cosmic rays and night-sky background events. A proof of principle system is being developed to run at camera trigger rates up to 10MHz and array-level rates up to 10kHz.

Modelling of critical functions of nuclear reactors using Fild Programmable Gate Array

International Nuclear Information System (INIS)

Teixeira, Pamela Iara Nolasco

2016-01-01

This paper proposes the development of a method using FPGA for critical security functions of a nuclear reactor. It was implemented two critical safety functions in VHDL, which is a way to describe, through a program, the behavior of a circuit or digital component. Two critical security functions, FCS Core Cooling, responsible for cooling the reactor core in the charts of the plant and also in the event of accidents involving loss of coolant and FCS Heat Transfer, responsible for cooling the reactor core in the event an accident with loss of coolant were implemented. In this Dissertation it was chosen the use of FPGA, because - due to the effects of aging, obsolescence issues, environmental degradation and mechanical failures - nuclear power plants need to replace their older systems by new ones based on digital technology. The technologies obtained using a system described in hardware language can be implemented in a programmable device, having the advantage of changing the code at any time. (author)

Tests of the gated mode for Belle II pixel detector

Energy Technology Data Exchange (ETDEWEB)

Prinker, Eduard [Max-Planck-Institute for Physics, Munich (Germany); Collaboration: Belle II-Collaboration

2015-07-01

DEPFET pixel detectors offer intrinsic amplification and very high signal to noise ratio. They form an integral building block for the vertex detector system of the Belle II experiment, which will start data taking in the year 2017 at the SuperKEKB Collider in Japan. A special Test board (Hybrid4) is used, which contains a small version of the DEPFET sensor with a read-out (DCD) and a steering chip (Switcher) attached, both controlled by a field-programmable gate array (FPGA) as the central interface to the computer. In order to keep the luminosity of the collider constant over time, the particle bunch currents have to be topped off by injecting additional bunches at a rate of 50 Hz. The particles in the daughter bunches produce a high rate of background (noisy bunches) for a short period of time, saturating the occupancy of the sensor. Operating the DEPFET sensor in a Gated Mode allows preserving the signals from collisions of normal bunches while protecting the pixels from background signals of the passing noisy bunches. An overview of the Gated Mode and first results is presented.

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS

International Nuclear Information System (INIS)

Bonacini, S.

2007-11-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 μm CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to ∼ 25 k gates, in 0.13 μm CMOS. The irradiation test results obtained in the CMOS 0.25 μm technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm 2 *MeV/mg, which make it suitable for the target environment. The CMOS 0.13 μm circuit has showed robustness to an LET of 37.4 cm 2 *MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design

Graphical Environment Tools for Application to Gamma-Ray Energy Tracking Arrays

Energy Technology Data Exchange (ETDEWEB)

Todd, Richard A. [RIS Corp.; Radford, David C. [ORNL Physics Div.

2013-12-30

Highly segmented, position-sensitive germanium detector systems are being developed for nuclear physics research where traditional electronic signal processing with mixed analog and digital function blocks would be enormously complex and costly. Future systems will be constructed using pipelined processing of high-speed digitized signals as is done in the telecommunications industry. Techniques which provide rapid algorithm and system development for future systems are desirable. This project has used digital signal processing concepts and existing graphical system design tools to develop a set of re-usable modular functions and libraries targeted for the nuclear physics community. Researchers working with complex nuclear detector arrays such as the Gamma-Ray Energy Tracking Array (GRETA) have been able to construct advanced data processing algorithms for implementation in field programmable gate arrays (FPGAs) through application of these library functions using intuitive graphical interfaces.

Dependable Design Flow for Protection Systems using Programmable Logic Devices

CERN Document Server

Kwiatkowski, M

2011-01-01

Programmable Logic Devices (PLD) such as Field Programmable Gate Arrays (FPGA) are becoming more prevalent in protection and safety-related electronic systems. When employing such programmable logic devices, extra care and attention needs to be taken. The final synthesis result, used to generate the bit-stream to program the device, must be shown to meet the design’s requirements. This paper describes how to maximize confidence using techniques such as Formal Methods, exhaustive Hardware Description Language (HDL) code simulation and hardware testing. An example is given for one of the critical functions of the Safe Machine Parameters (SMP) system, used in the protection of the Large Hadron Collider (LHC) at CERN. CERN is also working towards an adaptation of the IEC- 61508 lifecycle designed for Machine Protection Systems (MPS), and the High Energy Physics environment, implementation of a protection function in FPGA code is only one small step of this lifecycle. The ultimate aim of this project is to cre...

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

High Performance Systolic Array Core Architecture Design for DNA Sequencer

Directory of Open Access Journals (Sweden)

Saiful Nurdin Dayana

2018-01-01

Full Text Available This paper presents a high performance systolic array (SA core architecture design for Deoxyribonucleic Acid (DNA sequencer. The core implements the affine gap penalty score Smith-Waterman (SW algorithm. This time-consuming local alignment algorithm guarantees optimal alignment between DNA sequences, but it requires quadratic computation time when performed on standard desktop computers. The use of linear SA decreases the time complexity from quadratic to linear. In addition, with the exponential growth of DNA databases, the SA architecture is used to overcome the timing issue. In this work, the SW algorithm has been captured using Verilog Hardware Description Language (HDL and simulated using Xilinx ISIM simulator. The proposed design has been implemented in Xilinx Virtex -6 Field Programmable Gate Array (FPGA and improved in the core area by 90% reduction.

A Sea-of-Gates Style FPGA Placement Algorithm

Directory of Open Access Journals (Sweden)

Kalapi Roy

1996-01-01

Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

On photonic controlled phase gates

International Nuclear Information System (INIS)

Kieling, K; Eisert, J; O'Brien, J L

2010-01-01

As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

Improved sensing characteristics of dual-gate transistor sensor using silicon nanowire arrays defined by nanoimprint lithography

Science.gov (United States)

Lim, Cheol-Min; Lee, In-Kyu; Lee, Ki Joong; Oh, Young Kyoung; Shin, Yong-Beom; Cho, Won-Ju

2017-12-01

This work describes the construction of a sensitive, stable, and label-free sensor based on a dual-gate field-effect transistor (DG FET), in which uniformly distributed and size-controlled silicon nanowire (SiNW) arrays by nanoimprint lithography act as conductor channels. Compared to previous DG FETs with a planar-type silicon channel layer, the constructed SiNW DG FETs exhibited superior electrical properties including a higher capacitive-coupling ratio of 18.0 and a lower off-state leakage current under high-temperature stress. In addition, while the conventional planar single-gate (SG) FET- and planar DG FET-based pH sensors showed the sensitivities of 56.7 mV/pH and 439.3 mV/pH, respectively, the SiNW DG FET-based pH sensors showed not only a higher sensitivity of 984.1 mV/pH, but also a lower drift rate of 0.8% for pH-sensitivity. This demonstrates that the SiNW DG FETs simultaneously achieve high sensitivity and stability, with significant potential for future biosensing applications.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

A synchronous serial bus for multidimensional array acoustic logging tool

Science.gov (United States)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS

Energy Technology Data Exchange (ETDEWEB)

Aunet, Snorre

2002-06-01

This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.

COHERENTLY DEDISPERSED GATED IMAGING OF MILLISECOND PULSARS

International Nuclear Information System (INIS)

Roy, Jayanta; Bhattacharyya, Bhaswati

2013-01-01

Motivated by the need for rapid localization of newly discovered faint millisecond pulsars (MSPs), we have developed a coherently dedispersed gating correlator. This gating correlator accounts for the orbital motions of MSPs in binaries while folding the visibilities with a best-fit topocentric rotational model derived from a periodicity search in a simultaneously generated beamformer output. Unique applications of the gating correlator for sensitive interferometric studies of MSPs are illustrated using the Giant Metrewave Radio Telescope (GMRT) interferometric array. We could unambiguously localize five newly discovered Fermi MSPs in the on-off gated image plane with an accuracy of ±1''. Immediate knowledge of such a precise position enables the use of sensitive coherent beams of array telescopes for follow-up timing observations which substantially reduces the use of telescope time (∼20× for the GMRT). In addition, a precise a priori astrometric position reduces the effect of large covariances in the timing fit (with discovery position, pulsar period derivative, and an unknown binary model), which in-turn accelerates the convergence to the initial timing model. For example, while fitting with the precise a priori position (±1''), the timing model converges in about 100 days, accounting for the effect of covariance between the position and pulsar period derivative. Moreover, such accurate positions allow for rapid identification of pulsar counterparts at other wave bands. We also report a new methodology of in-beam phase calibration using the on-off gated image of the target pulsar, which provides optimal sensitivity of the coherent array removing possible temporal and spacial decoherences.

COHERENTLY DEDISPERSED GATED IMAGING OF MILLISECOND PULSARS

Energy Technology Data Exchange (ETDEWEB)

Roy, Jayanta; Bhattacharyya, Bhaswati [National Centre for Radio Astrophysics, Pune 411007 (India)

2013-03-10

Motivated by the need for rapid localization of newly discovered faint millisecond pulsars (MSPs), we have developed a coherently dedispersed gating correlator. This gating correlator accounts for the orbital motions of MSPs in binaries while folding the visibilities with a best-fit topocentric rotational model derived from a periodicity search in a simultaneously generated beamformer output. Unique applications of the gating correlator for sensitive interferometric studies of MSPs are illustrated using the Giant Metrewave Radio Telescope (GMRT) interferometric array. We could unambiguously localize five newly discovered Fermi MSPs in the on-off gated image plane with an accuracy of {+-}1''. Immediate knowledge of such a precise position enables the use of sensitive coherent beams of array telescopes for follow-up timing observations which substantially reduces the use of telescope time ({approx}20 Multiplication-Sign for the GMRT). In addition, a precise a priori astrometric position reduces the effect of large covariances in the timing fit (with discovery position, pulsar period derivative, and an unknown binary model), which in-turn accelerates the convergence to the initial timing model. For example, while fitting with the precise a priori position ({+-}1''), the timing model converges in about 100 days, accounting for the effect of covariance between the position and pulsar period derivative. Moreover, such accurate positions allow for rapid identification of pulsar counterparts at other wave bands. We also report a new methodology of in-beam phase calibration using the on-off gated image of the target pulsar, which provides optimal sensitivity of the coherent array removing possible temporal and spacial decoherences.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

Science.gov (United States)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Evaluation of delivered monitor unit accuracy of gated step-and-shoot IMRT using a two-dimensional detector array

Energy Technology Data Exchange (ETDEWEB)

Cheong, Kwang-Ho; Kang, Sei-Kwon; Lee, MeYeon; Kim, Su SSan; Park, SoAh; Hwang, Tae-Jin; Kim, Kyoung Ju; Oh, Do Hoon; Bae, Hoonsik; Suh, Tae-Suk [Department of Radiation Oncology, Hallym University College of Medicine, Seoul, 431070 (Korea, Republic of) and Department of Biomedical Engineering, College of Medicine, Catholic University of Korea, Seoul 137701 (Korea, Republic of); Department of Radiation Oncology, Hallym University College of Medicine, Seoul 431070 (Korea, Republic of); Department of Biomedical Engineering, College of Medicine, Catholic University of Korea, Seoul 137701 (Korea, Republic of)

2010-03-15

Purpose: To overcome the problem of organ motion in intensity-modulated radiation therapy (IMRT), gated IMRT is often used for the treatment of lung cancer. In this study, the authors investigated the accuracy of the delivered monitor units (MUs) from each segment during gated IMRT using a two-dimensional detector array for user-specific verification purpose. Methods: The authors planned a 6 MV photon, seven-port step-and-shoot lung IMRT delivery. The respiration signals for gated IMRT delivery were obtained from the one-dimensional moving phantom using the real-time position management (RPM) system (Varian Medical Systems, Palo Alto, CA). The beams were delivered using a Clinac iX (Varian Medical Systems, Palo Alto, CA) with the Millennium 120 MLC. The MatriXX (IBA Dosimetry GmbH, Germany) was validated through consistency and reproducibility tests as well as comparison with measurements from a Farmer-type ion chamber. The authors delivered beams with varying dose rates and duty cycles and analyzed the MatriXX data to evaluate MU delivery accuracy. Results: There was quite good agreement between the planned segment MUs and the MUs computed from the MatriXX within {+-}2% error. The beam-on times computed from the MatriXX data were almost identical for all cases, and they matched well with the RPM beam-on and beam-off signals. A slight difference was observed between them, but it was less than 40 ms. The gated IMRT delivery demonstrated an MU delivery accuracy that was equivalent to ungated IMRT, and the delivered MUs with a gating signal agreed with the planned MUs within {+-}0.5 MU regardless of dose rate and duty cycle. Conclusions: The authors can conclude that gated IMRT is able to deliver an accurate dose to a patient during a procedure. The authors believe that the methodology and results can be transferred to other vendors' devices, particularly those that do not provide MLC log data for a verification purpose.

Cardiac gated ventilation

International Nuclear Information System (INIS)

Hanson, C.W. III; Hoffman, E.A.

1995-01-01

There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

Energy Technology Data Exchange (ETDEWEB)

Xie, X; Cao, D; Housley, D; Mehta, V; Shepard, D [Swedish Cancer Institute, Seattle, WA (United States)

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-moving platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.

Dual-gated volumetric modulated arc therapy

International Nuclear Information System (INIS)

Fahimian, Benjamin; Wu, Junqing; Wu, Huanmei; Geneser, Sarah; Xing, Lei

2014-01-01

Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging radiation therapy modality for treatment of tumors affected by respiratory motion. However, gating significantly prolongs the treatment time, as delivery is only activated during a single respiratory phase. To enhance the efficiency of gated VMAT delivery, a novel dual-gated VMAT (DG-VMAT) technique, in which delivery is executed at both exhale and inhale phases in a given arc rotation, is developed and experimentally evaluated. Arc delivery at two phases is realized by sequentially interleaving control points consisting of MUs, MLC sequences, and angles of VMAT plans generated at the exhale and inhale phases. Dual-gated delivery is initiated when a respiration gating signal enters the exhale window; when the exhale delivery concludes, the beam turns off and the gantry rolls back to the starting position for the inhale window. The process is then repeated until both inhale and exhale arcs are fully delivered. DG-VMAT plan delivery accuracy was assessed using a pinpoint chamber and diode array phantom undergoing programmed motion. DG-VMAT delivery was experimentally implemented through custom XML scripting in Varian’s TrueBeam™ STx Developer Mode. Relative to single gated delivery at exhale, the treatment time was improved by 95.5% for a sinusoidal breathing pattern. The pinpoint chamber dose measurement agreed with the calculated dose within 0.7%. For the DG-VMAT delivery, 97.5% of the diode array measurements passed the 3%/3 mm gamma criterion. The feasibility of DG-VMAT delivery scheme has been experimentally demonstrated for the first time. By leveraging the stability and natural pauses that occur at end-inspiration and end-exhalation, DG-VMAT provides a practical method for enhancing gated delivery efficiency by up to a factor of two

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

Science.gov (United States)

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Investigation of Electromagnetic Signatures of a FPGA Using an APREL EM-ISIGHT System

Science.gov (United States)

2015-12-01

shelf (COTS) field- programmable gate array (FPGA) at the optimized factor levels established from the DOE and varying the programmed signal. This...signature using APREL’s EM-ISight automated system is hypothesized to be a novel way to accomplish this task. Research Questions The research...a field programmable gate array (FPGA) is the circuit board utilized for testing the inherent electromagnetic signature. Every device produces an

Gated field-emitter cathodes for high-power microwave applications

International Nuclear Information System (INIS)

Barasch, E.F.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.; McIntyre, P.M.; Pang, Y.; Smith, D.D.; Trost, H.J.

1992-01-01

Gated field-emitter cathodes have been fabricated on silicon wafers. Two fabrication approaches have been employed: a knife-edge array and a porous silicon structure. The knife-edge array consists of a pattern of knife-edges, sharpened to ∼200 A radius, configured with an insulated metal gate structure at a gap of ∼500 A. The porous silicon cathode consists of an insulating porous layer, containing pores of ∼50 A diameter, densely spaced in the native silicon, biased for field emission by a thin gate metallization on the surface. Emission current density of 20 A/cm 2 has been obtained with only 10 V bias. Fabrication processes and test results are presented. (Author) 4 figs., tab., 12 refs

Regulatory issues on using programmable logic device in nuclear power plants

International Nuclear Information System (INIS)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H.

2012-01-01

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards

Regulatory issues on using programmable logic device in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

2012-10-15

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards.

High-speed two-frame gated camera for parameters measurement of Dragon-Ⅰ LIA

International Nuclear Information System (INIS)

Jiang Xiaoguo; Wang Yuan; Zhang Kaizhi; Shi Jinshui; Deng Jianjun; Li Jin

2012-01-01

The time-resolved measurement system which can work at very high speed is necessary in electron beam parameter diagnosis for Dragon-Ⅰ linear induction accelerator (LIA). A two-frame gated camera system has been developed and put into operation. The camera system adopts the optical principle of splitting the imaging light beam into two parts in the imaging space of a lens with long focus length. It includes lens coupled gated image intensifier, CCD camera, high speed shutter trigger device based on large scale field programmable gate array. The minimum exposure time for each image is about 3 ns, and the interval time between two images can be adjusted with a step of about 0.5 ns. The exposure time and the interval time can be independently adjusted and can reach about 1 s. The camera system features good linearity, good response uniformity, equivalent background illumination (EBI) as low as about 5 electrons per pixel per second, large adjustment range of sensitivity, and excel- lent flexibility and adaptability in applications. The camera system can capture two frame images at one time with the image size of 1024 x 1024. It meets the requirements of measurement for Dragon-Ⅰ LIA. (authors)

Implementation of a two-qubit controlled-rotation gate based on unconventional geometric phase with a constant gating time

International Nuclear Information System (INIS)

Yabu-uti, B.F.C.; Roversi, J.A.

2011-01-01

We propose an alternative scheme to implement a two-qubit controlled-R (rotation) gate in the hybrid atom-CCA (coupled cavities array) system. Our scheme results in a constant gating time and, with an adjustable qubit-bus coupling (atom-resonator), one can specify a particular rotation R on the target qubit. We believe that this proposal may open promising perspectives for networking quantum information processors and implementing distributed and scalable quantum computation. -- Highlights: → We propose an alternative two-qubit controlled-rotation gate implementation. → Our gate is realized in a constant gating time for any rotation. → A particular rotation on the target qubit can be specified by an adjustable qubit-bus coupling. → Our proposal may open promising perspectives for implementing distributed and scalable quantum computation.

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

Science.gov (United States)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

Scaling Trapped Ion Quantum Computers Using Fast Gates and Microtraps

Science.gov (United States)

Ratcliffe, Alexander K.; Taylor, Richard L.; Hope, Joseph J.; Carvalho, André R. R.

2018-06-01

Most attempts to produce a scalable quantum information processing platform based on ion traps have focused on the shuttling of ions in segmented traps. We show that an architecture based on an array of microtraps with fast gates will outperform architectures based on ion shuttling. This system requires higher power lasers but does not require the manipulation of potentials or shuttling of ions. This improves optical access, reduces the complexity of the trap, and reduces the number of conductive surfaces close to the ions. The use of fast gates also removes limitations on the gate time. Error rates of 10-5 are shown to be possible with 250 mW laser power and a trap separation of 100 μ m . The performance of the gates is shown to be robust to the limitations in the laser repetition rate and the presence of many ions in the trap array.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

Science.gov (United States)

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

Directory of Open Access Journals (Sweden)

Sungho Kang

1996-01-01

Full Text Available In order to reduce cost and to achieve high speed a new hardware accelerator for fault simulation has been designed. The architecture of the new accelerator is based on a reconfigurabl mesh type processing element (PE array. Circuit elements at the same topological level are simulated concurrently, as in a pipelined process. A new parallel simulation algorithm expands all of the gates to two input gates in order to limit the number of faults to two at each gate, so that the faults can be distributed uniformly throughout the PE array. The PE array reconfiguration operation provides a simulation speed advantage by maximizing the use of each PE cell.

Design and analysis of a dual mode CMOS field programmable analog array

International Nuclear Information System (INIS)

Cheng Xiaoyan; Yang Haigang; Yin Tao; Wu Qisong; Zhang Hongfeng; Liu Fei

2014-01-01

This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. (semiconductor integrated circuits)

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

Science.gov (United States)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

Multiplexed charge-locking device for large arrays of quantum devices

Energy Technology Data Exchange (ETDEWEB)

Puddy, R. K., E-mail: rkp27@cam.ac.uk; Smith, L. W; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Smith, C. G. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom); Al-Taie, H.; Kelly, M. J. [Cavendish Laboratory, University of Cambridge, Cambridge CB3 0HE (United Kingdom); Centre for Advanced Photonics and Electronics, Electrical Engineering Division, Department of Engineering, 9 J. J. Thomson Avenue, University of Cambridge, Cambridge CB3 0FA (United Kingdom); Pepper, M. [Department of Electronic and Electrical Engineering, University College London, WC1E 7JE (United Kingdom)

2015-10-05

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Final Report

Energy Technology Data Exchange (ETDEWEB)

Britton, Jr., Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Bobrek, Miljko [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

2015-12-01

As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios where human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments due the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is the final report of the activities involving the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. We present a detailed functional block diagram of the proposed data acquisition system, the thought process leading to technical decisions, the implemented system, and the tested results from the systems. This system will be capable of monitoring at least three parameters of importance to nuclear reactor monitoring: temperature, radiation level, and pressure.

DBPM signal processing with field programmable gate arrays

International Nuclear Information System (INIS)

Lai Longwei; Yi Xing; Zhang Ning; Yang Guisen; Wang Baopeng; Xiong Yun; Leng Yongbin; Yan Yingbing

2011-01-01

DBPM system performance is determined by the design and implementation of beam position signal processing algorithm. In order to develop the system, a beam position signal processing algorithm is implemented on FPGA. The hardware is a PMC board ICS-1554A-002 (GE Corp.) with FPGA chip XC5VSX95T. This paper adopts quadrature frequency mixing to down convert high frequency signal to base. Different from conventional method, the mixing is implemented by CORDIC algorithm. The algorithm theory and implementation details are discussed in this paper. As the board contains no front end gain controller, this paper introduces a published patent-pending technique that has been adopted to realize the function in digital logic. The whole design is implemented with VHDL language. An on-line evaluation has been carried on SSRF (Shanghai Synchrotron Radiation Facility)storage ring. Results indicate that the system turn-by-turn data can measure the real beam movement accurately,and system resolution is 1.1μm. (authors)

The FPGA Pixel Array Detector

International Nuclear Information System (INIS)

Hromalik, Marianne S.; Green, Katherine S.; Philipp, Hugh T.; Tate, Mark W.; Gruner, Sol M.

2013-01-01

A proposed design for a reconfigurable x-ray Pixel Array Detector (PAD) is described. It operates by integrating a high-end commercial field programmable gate array (FPGA) into a 3-layer device along with a high-resistivity diode detection layer and a custom, application-specific integrated circuit (ASIC) layer. The ASIC layer contains an energy-discriminating photon-counting front end with photon hits streamed directly to the FPGA via a massively parallel, high-speed data connection. FPGA resources can be allocated to perform user defined tasks on the pixel data streams, including the implementation of a direct time autocorrelation function (ACF) with time resolution down to 100 ns. Using the FPGA at the front end to calculate the ACF reduces the required data transfer rate by several orders of magnitude when compared to a fast framing detector. The FPGA-ASIC high-speed interface, as well as the in-FPGA implementation of a real-time ACF for x-ray photon correlation spectroscopy experiments has been designed and simulated. A 16×16 pixel prototype of the ASIC has been fabricated and is being tested. -- Highlights: ► We describe the novelty and need for the FPGA Pixel Array Detector. ► We describe the specifications and design of the Diode, ASIC and FPGA layers. ► We highlight the Autocorrelation Function (ACF) for speckle as an example application. ► Simulated FPGA output calculates the ACF for different input bitstreams to 100 ns. ► Reduced data transfer rate by 640× and sped up real-time ACF by 100× other methods.

Field-Programmable Logic Devices with Optical Input Output

Science.gov (United States)

Szymanski, Ted H.; Saint-Laurent, Martin; Tyan, Victor; Au, Albert; Supmonchai, Boonchuay

2000-02-01

A field-programmable logic device (FPLD) with optical I O is described. FPLD s with optical I O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA s) on a 2 mm 2 mm die. The devices were fabricated through the Lucent Technologies Advanced Research Projects Agency Consortium for Optical and Optoelectronic Technologies in Computing (Lucent ARPA COOP) workshop by use of 0.5- m complementary metal-oxide semiconductor self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 4 crossbar switches, which can realize more than 190 10 6 unique programmable input output permutations. The same device scaled to a 2 cm 2 cm substrate could support as many as 4000 optical I O and 1 Tbit s of optical I O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

Science.gov (United States)

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Operating scheme for the light-emitting diode array of a volumetric display that exhibits multiple full-color dynamic images

Science.gov (United States)

Hirayama, Ryuji; Shiraki, Atsushi; Nakayama, Hirotaka; Kakue, Takashi; Shimobaba, Tomoyoshi; Ito, Tomoyoshi

2017-07-01

We designed and developed a control circuit for a three-dimensional (3-D) light-emitting diode (LED) array to be used in volumetric displays exhibiting full-color dynamic 3-D images. The circuit was implemented on a field-programmable gate array; therefore, pulse-width modulation, which requires high-speed processing, could be operated in real time. We experimentally evaluated the developed system by measuring the luminance of an LED with varying input and confirmed that the system works appropriately. In addition, we demonstrated that the volumetric display exhibits different full-color dynamic two-dimensional images in two orthogonal directions. Each of the exhibited images could be obtained only from the prescribed viewpoint. Such directional characteristics of the system are beneficial for applications, including digital signage, security systems, art, and amusement.

Characteristics of dual-gate thin-film transistors for applications in digital radiology

International Nuclear Information System (INIS)

Waechter, D.; Huang, Z.; Zhao, W.; Blevis, I.; Rowlands, J.A.

1996-01-01

A large-area flat-panel detector for digital radiology is being developed. The detector uses an array of dual-gate thin-film transistors (TFTs) to read out X-ray-generated charge produced in an amorphous selenium (a-Se) layer. The TFTs use CdSe as the semiconductor and use the bottom gate for row selection. The top gate can be divided into a 'deliberate' gate, covering most of the channel length, and small 'parasitic' gates that consist of: overlap of source or drain metal over the top-gate oxide; and gap regions in the metal that are covered only by the a-Se. In this paper we present the properties of dual-gate TFTs and examine the effect of both the deliberate and parasitic gates on the detector operation. Various options for controlling the top-gate potential are analyzed and discussed. (author)

New efficient five-input majority gate for quantum-dot cellular automata

International Nuclear Information System (INIS)

Farazkish, Razieh; Navi, Keivan

2012-01-01

A novel fault-tolerant five-input majority gate for quantum-dot cellular automata is presented. Quantum-dot cellular automata (QCA) is an emerging technology which is considered to be presented in future computers. Two principle logic elements in QCA are “majority gate” and “inverter.” In this paper, we propose a new approach to the design of fault-tolerant five-input majority gate by considering two-dimensional arrays of QCA cells. We analyze fault tolerance properties of such block five-input majority gate in terms of misalignment, missing, and dislocation cells. Some physical proofs are used for verifying five-input majority gate circuit layout and functionality. Our results clearly demonstrate that the redundant version of the block five-input majority gate is more robust than the standard style for this gate.

Array-level stability enhancement of 50 nm AlxOy ReRAM

Science.gov (United States)

Iwasaki, Tomoko Ogura; Ning, Sheyang; Yamazawa, Hiroki; Takeuchi, Ken

2015-12-01

ReRAM's low voltage and low current programmability are attractive features to solve the scaling issues of conventional floating gate Flash. However, read instability in ReRAM is a critical issue, due to random telegraph noise (RTN), sensitivity to disturb and retention. In this work, the array-level characteristics of read stability in 50 nm AlxOy ReRAM are investigated and a circuit technique to improve stability is proposed and evaluated. First, in order to quantitatively assess memory cell stability, a method of stability characterization is defined. Next, based on this methodology, a proposal to improve read stability, called ;stability check loop; is evaluated. The stability check loop is a stability verification procedure, by which, instability improvement of 7×, and read error rate improvement of 40% are obtained.

Gated x-ray detector for the National Ignition Facility

International Nuclear Information System (INIS)

Oertel, John A.; Aragonez, Robert; Archuleta, Tom; Barnes, Cris; Casper, Larry; Fatherley, Valerie; Heinrichs, Todd; King, Robert; Landers, Doug; Lopez, Frank; Sanchez, Phillip; Sandoval, George; Schrank, Lou; Walsh, Peter; Bell, Perry; Brown, Matt; Costa, Robert; Holder, Joe; Montelongo, Sam; Pederson, Neal

2006-01-01

Two new gated x-ray imaging cameras have recently been designed, constructed, and delivered to the National Ignition Facility in Livermore, CA. These gated x-Ray detectors are each designed to fit within an aluminum airbox with a large capacity cooling plane and are fitted with an array of environmental housekeeping sensors. These instruments are significantly different from earlier generations of gated x-ray images due, in part, to an innovative impedance matching scheme, advanced phosphor screens, pulsed phosphor circuits, precision assembly fixturing, unique system monitoring, and complete remote computer control. Preliminary characterization has shown repeatable uniformity between imaging strips, improved spatial resolution, and no detectable impedance reflections

Terahertz modulation based on surface plasmon resonance by self-gated graphene

Science.gov (United States)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Directory of Open Access Journals (Sweden)

Chao Chen

2014-01-01

Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

GateKeeper: a new hardware architecture for accelerating pre-alignment in DNA short read mapping.

Science.gov (United States)

Alser, Mohammed; Hassan, Hasan; Xin, Hongyi; Ergin, Oguz; Mutlu, Onur; Alkan, Can

2017-11-01

High throughput DNA sequencing (HTS) technologies generate an excessive number of small DNA segments -called short reads- that cause significant computational burden. To analyze the entire genome, each of the billions of short reads must be mapped to a reference genome based on the similarity between a read and 'candidate' locations in that reference genome. The similarity measurement, called alignment, formulated as an approximate string matching problem, is the computational bottleneck because: (i) it is implemented using quadratic-time dynamic programming algorithms and (ii) the majority of candidate locations in the reference genome do not align with a given read due to high dissimilarity. Calculating the alignment of such incorrect candidate locations consumes an overwhelming majority of a modern read mapper's execution time. Therefore, it is crucial to develop a fast and effective filter that can detect incorrect candidate locations and eliminate them before invoking computationally costly alignment algorithms. We propose GateKeeper, a new hardware accelerator that functions as a pre-alignment step that quickly filters out most incorrect candidate locations. GateKeeper is the first design to accelerate pre-alignment using Field-Programmable Gate Arrays (FPGAs), which can perform pre-alignment much faster than software. When implemented on a single FPGA chip, GateKeeper maintains high accuracy (on average >96%) while providing, on average, 90-fold and 130-fold speedup over the state-of-the-art software pre-alignment techniques, Adjacency Filter and Shifted Hamming Distance (SHD), respectively. The addition of GateKeeper as a pre-alignment step can reduce the verification time of the mrFAST mapper by a factor of 10. https://github.com/BilkentCompGen/GateKeeper. mohammedalser@bilkent.edu.tr or onur.mutlu@inf.ethz.ch or calkan@cs.bilkent.edu.tr. Supplementary data are available at Bioinformatics online. © The Author (2017). Published by Oxford University Press

Programmable logic controller performance enhancement by field programmable gate array based design.

Science.gov (United States)

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Magnetomicrofluidics Circuits for Organizing Bioparticle Arrays

Science.gov (United States)

Abedini-Nassab, Roozbeh

Single-cell analysis (SCA) tools have important applications in the analysis of phenotypic heterogeneity, which is difficult or impossible to analyze in bulk cell culture or patient samples. SCA tools thus have a myriad of applications ranging from better credentialing of drug therapies to the analysis of rare latent cells harboring HIV infection or in Cancer. However, existing SCA systems usually lack the required combination of programmability, flexibility, and scalability necessary to enable the study of cell behaviors and cell-cell interactions at the scales sufficient to analyze extremely rare events. To advance the field, I have developed a novel, programmable, and massively-parallel SCA tool which is based on the principles of computer circuits. By integrating these magnetic circuits with microfluidics channels, I developed a platform that can organize a large number of single particles into an array in a controlled manner. My magnetophoretic circuits use passive elements constructed in patterned magnetic thin films to move cells along programmed tracks with an external rotating magnetic field. Cell motion along these tracks is analogous to the motion of charges in an electrical conductor, following a rule similar to Ohm's law. I have also developed asymmetric conductors, similar to electrical diodes, and storage sites for cells that behave similarly to electrical capacitors. I have also developed magnetophoretic circuits which use an overlaid pattern of microwires to switch single cells between different tracks. This switching mechanism, analogous to the operation of electronic transistors, is achieved by establishing a semiconducting gap in the magnetic pattern which can be changed from an insulating state to a conducting state by application of electrical current to an overlaid electrode. I performed an extensive study on the operation of transistors to optimize their geometry and minimize the required gate currents. By combining these elements into

'kids in parks' programme to the professional development of teachers

African Journals Online (AJOL)

This article considers the possible contribution of the 'kids in parks' programme offered at Golden Gate Highlands National Park to the professional development of teachers. Focus group interviews were held with teachers who participated in the programme, and an interview with open-ended questions was held with a ...

Physical Fault Injection and Monitoring Methods for Programmable Devices

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00510096; Ferencei, Jozef

A method of detecting faults for evaluating the fault cross section of any field programmable gate array (FPGA) was developed and is described in the thesis. The incidence of single event effects in FPGAs was studied for different probe particles (proton, neutron, gamma) using this method. The existing accelerator infrastructure of the Nuclear Physics Institute in Rez was supplemented by more sensitive beam monitoring system to ensure that the tests are done under well defined beam conditions. The bit cross section of single event effects was measured for different types of configuration memories, clock signal phase and beam energies and intensities. The extended infrastructure served also for radiation testing of components which are planned to be used in the new Inner Tracking System (ITS) detector of the ALICE experiment and for selecting optimal fault mitigation techniques used for securing the design of the FPGA-based ITS readout unit against faults induced by ionizing radiation.

Microwave metamaterials—from passive to digital and programmable controls of electromagnetic waves

Science.gov (United States)

Cui, Tie Jun

2017-08-01

functions. We realised that when the digital state of a coding unit is controlled by a field programmable gate array, the programmable metamaterial, which is capable of manipulating electromagnetic waves in real time, can generate many different functions.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Laser-assisted electron emission from gated field-emitters

CERN Document Server

Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A

2002-01-01

Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...

Hybrid ECG-gated versus non-gated 512-slice CT angiography of the aorta and coronary artery: image quality and effect of a motion correction algorithm.

Science.gov (United States)

Lee, Ji Won; Kim, Chang Won; Lee, Geewon; Lee, Han Cheol; Kim, Sang-Pil; Choi, Bum Sung; Jeong, Yeon Joo

2018-02-01

Background Using the hybrid electrocardiogram (ECG)-gated computed tomography (CT) technique, assessment of entire aorta, coronary arteries, and aortic valve can be possible using single-bolus contrast administration within a single acquisition. Purpose To compare the image quality of hybrid ECG-gated and non-gated CT angiography of the aorta and evaluate the effect of a motion correction algorithm (MCA) on coronary artery image quality in a hybrid ECG-gated aorta CT group. Material and Methods In total, 104 patients (76 men; mean age = 65.8 years) prospectively randomized into two groups (Group 1 = hybrid ECG-gated CT; Group 2 = non-gated CT) underwent wide-detector array aorta CT. Image quality, assessed using a four-point scale, was compared between the groups. Coronary artery image quality was compared between the conventional reconstruction and motion correction reconstruction subgroups in Group 1. Results Group 1 showed significant advantages over Group 2 in aortic wall, cardiac chamber, aortic valve, coronary ostia, and main coronary arteries image quality (all P ECG-gated CT significantly improved the heart and aortic wall image quality and the MCA can further improve the image quality and interpretability of coronary arteries.

The Gates Malaria Partnership: a consortium approach to malaria research and capacity development.

Science.gov (United States)

Greenwood, Brian; Bhasin, Amit; Targett, Geoffrey

2012-05-01

Recently, there has been a major increase in financial support for malaria control. Most of these funds have, appropriately, been spent on the tools needed for effective prevention and treatment of malaria such as insecticide-treated bed nets, indoor residual spraying and artemisinin combination therapy. There has been less investment in the training of the scientists from malaria-endemic countries needed to support these large and increasingly complex malaria control programmes, especially in Africa. In 2000, with support from the Bill & Melinda Gates Foundation, the Gates Malaria Partnership was established to support postgraduate training of African scientists wishing to pursue a career in malaria research. The programme had three research capacity development components: a PhD fellowship programme, a postdoctoral fellowship programme and a laboratory infrastructure programme. During an 8-year period, 36 African PhD students and six postdoctoral fellows were supported, and two research laboratories were built in Tanzania. Some of the lessons learnt during this project--such as the need to improve PhD supervision in African universities and to provide better support for postdoctoral fellows--are now being applied to a successor malaria research capacity development programme, the Malaria Capacity Development Consortium, and may be of interest to other groups involved in improving postgraduate training in health sciences in African universities. © 2012 Blackwell Publishing Ltd.

Time-Reversal MUSIC Imaging with Time-Domain Gating Technique

Science.gov (United States)

Choi, Heedong; Ogawa, Yasutaka; Nishimura, Toshihiko; Ohgane, Takeo

A time-reversal (TR) approach with multiple signal classification (MUSIC) provides super-resolution for detection and localization using multistatic data collected from an array antenna system. The theory of TR-MUSIC assumes that the number of antenna elements is greater than that of scatterers (targets). Furthermore, it requires many sets of frequency-domain data (snapshots) in seriously noisy environments. Unfortunately, these conditions are not practical for real environments due to the restriction of a reasonable antenna structure as well as limited measurement time. We propose an approach that treats both noise reduction and relaxation of the transceiver restriction by using a time-domain gating technique accompanied with the Fourier transform before applying the TR-MUSIC imaging algorithm. Instead of utilizing the conventional multistatic data matrix (MDM), we employ a modified MDM obtained from the gating technique. The resulting imaging functions yield more reliable images with only a few snapshots regardless of the limitation of the antenna arrays.

Engineering integrated photonics for heralded quantum gates

Science.gov (United States)

Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.

2016-06-01

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Engineering integrated photonics for heralded quantum gates.

Science.gov (United States)

Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J

2016-06-10

Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.

Optical programmable metamaterials

Science.gov (United States)

Gong, Cheng; Zhang, Nan; Dai, Zijie; Liu, Weiwei

2018-02-01

We suggest and demonstrate the concept of optical programmable metamaterials which can configure the device's electromagnetic parameters by the programmable optical stimuli. In such metamaterials, the optical stimuli produced by a FPGA controlled light emitting diode array can switch or combine the resonance modes which are coupled in. As an example, an optical programmable metamaterial terahertz absorber is proposed. Each cell of the absorber integrates four meta-rings (asymmetric 1/4 rings) with photo-resistors connecting the critical gaps. The principle and design of the metamaterials are illustrated and the simulation results demonstrate the functionalities for programming the metamaterial absorber to change its bandwidth and resonance frequency.

Designing for Reuse of Configurable Logic

National Research Council Canada - National Science Library

Elm, Joseph P

2005-01-01

Field-programmable gate arrays (FPGAs) offer electronic systems designers the opportunity to reduce development cost, reduce time-to-market, increase system performance, and improve system adaptability...

Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

CERN Document Server

Kwiatkowski, Maciej; Todd, Benjamin

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and ...

Methods for the application of programmable logic devices in electronic protection systems for high energy particle accelerators

CERN Document Server

Kwiatkowski, M

2014-01-01

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable rmware implementation and to use that method to implement a new rmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis [1]. For that reason the reliable SMP hardware was preserved unchanged. The rst version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP rmware was objectionable. There were new requirements and therefore the SMP speci cation was extended. On that occasion it was decided that the existing SMP rmware will not be continued and that it...

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

Science.gov (United States)

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

Dynamic Reconfiguration Of FPGA Nodes In A Distributed Computing System: A Preliminary Investigation

National Research Council Canada - National Science Library

Nixon, Patrick

2002-01-01

This report results from a contract tasking Trinity College, Dublin to investigate a specialized portion of a heterogeneous information system, specifically, Field Programmable Gate Array (FPGA)-based nodes...

Operational method of a ferroelectric (Fe)-NAND flash memory array

International Nuclear Information System (INIS)

Wang, Shouyu; Takahashi, Mitue; Li, Qiu-Hong; Sakai, Shigeki; Takeuchi, Ken

2009-01-01

Operations of arrayed ferroelectric (Fe)-NAND flash memory cells: erase, program and read were demonstrated for the first time using a small cell array of four word lines by two NAND strings. The memory cells and select-gate transistors were all n-channel Pt/SrBi 2 Ta 2 O 9 /Hf-Al-O/Si ferroelectric-gate field effect transistors. The erase was performed by applying 10 µs wide 7 V pulses to n- and p-wells. The program was performed by applying 10 µs wide 7 V pulses to selected word lines. Accumulated read currents of 51 programmed patterns in the Fe-NAND flash memory cell array successfully showed distribution of the two distinguishable '0' and '1' states. The margin between the two states became wider by applying a verification technique in programming a cell out of the eight. Retention times of bit-line currents were obtained over 33 h for both the '0' and '1' states in a program pattern

Reconfigurable Environmentally Aware Computing Technology for Earth Observing Systems (7284-060), Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Over the past decade, many research groups have developed reconfigurable computing systems built from Field Programmable Gate Arrays (FPGAs) for on-board processing...

Radiation-Tolerant Reprogrammable FPGA for Digital Signal Processing Circuits, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Field Programmable Gate Arrays are a widely used technology; however, they are generally limited in reprogrammability. Radiation hard, low power and high density...

Column Grid Array Rework for High Reliability

Science.gov (United States)

Mehta, Atul C.; Bodie, Charles C.

2008-01-01

Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.

Universal Quantum Computing with Measurement-Induced Continuous-Variable Gate Sequence in a Loop-Based Architecture.

Science.gov (United States)

Takeda, Shuntaro; Furusawa, Akira

2017-09-22

We propose a scalable scheme for optical quantum computing using measurement-induced continuous-variable quantum gates in a loop-based architecture. Here, time-bin-encoded quantum information in a single spatial mode is deterministically processed in a nested loop by an electrically programmable gate sequence. This architecture can process any input state and an arbitrary number of modes with almost minimum resources, and offers a universal gate set for both qubits and continuous variables. Furthermore, quantum computing can be performed fault tolerantly by a known scheme for encoding a qubit in an infinite-dimensional Hilbert space of a single light mode.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

Science.gov (United States)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Rad-Hard and ULP FPGA with "Full" Functionality, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

Digital acquisition and wavelength control of seed laser for space-based Lidar applications, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — This SBIR Phase I proposes to establish the feasibility of using a space qualifiable Field Programmable Gate Array (FPGA) based digital controller to autonomously...

Dose verification for respiratory-gated volumetric modulated arc therapy

Energy Technology Data Exchange (ETDEWEB)

Qian Jianguo; Xing Lei; Liu Wu; Luxton, Gary, E-mail: gluxton@stanford.edu [Department of Radiation Oncology, Stanford University School of Medicine, Stanford, CA 94305 (United States)

2011-08-07

A novel commercial medical linac system (TrueBeam(TM), Varian Medical Systems, Palo Alto, CA) allows respiratory-gated volumetric modulated arc therapy (VMAT), a new modality for treating moving tumors with high precision and improved accuracy by allowing for regular motion associated with a patient's breathing during VMAT delivery. The purpose of this work is to adapt a previously-developed dose reconstruction technique to evaluate the fidelity of VMAT treatment during gated delivery under clinic-relevant periodic motion related to patient breathing. A Varian TrueBeam system was used in this study. VMAT plans were created for three patients with lung or pancreas tumors. Conventional 6 and 15 MV beams with flattening filter and high-dose-rate 10 MV beams with no flattening filter were used in these plans. Each patient plan was delivered to a phantom first without gating and then with gating for three simulated respiratory periods (3, 4.5 and 6 s). Using the adapted log-file-based dose reconstruction procedure supplemented with ion chamber array (Seven29(TM), PTW, Freiburg, Germany) measurements, the delivered dose was used to evaluate the fidelity of gated VMAT delivery. Comparison of Seven29 measurements with and without gating showed good agreement with gamma-index passing rates above 99% for 1%/1 mm dose accuracy/distance-to-agreement criteria. With original plans as reference, gamma-index passing rates were 100% for the reconstituted plans (1%/1 mm criteria) and 93.5-100% for gated Seven29 measurements (3%/3 mm criteria). In the presence of leaf error deliberately introduced into the gated delivery of a pancreas patient plan, both dose reconstruction and Seven29 measurement consistently indicated substantial dosimetric differences from the original plan. In summary, a dose reconstruction procedure was demonstrated for evaluating the accuracy of respiratory-gated VMAT delivery. This technique showed that under clinical operation, the TrueBeam system

Virtual Field Programmable Gate Array Triple Modular Redundant Cell Design

National Research Council Canada - National Science Library

Marty, Barbara

2004-01-01

.... A hardened microcontroller manages the configurations of each of the three FPGAs and monitors upset statistics. Advanced packaging is used to form a component that seems similar in form to the single FPGAs that the concept intends to replace.

Nano/CMOS architectures using a field-programmable nanowire interconnect

International Nuclear Information System (INIS)

Snider, Gregory S; Williams, R Stanley

2007-01-01

A field-programmable nanowire interconnect (FPNI) enables a family of hybrid nano/CMOS circuit architectures that generalizes the CMOL (CMOS/molecular hybrid) approach proposed by Strukov and Likharev, allowing for simpler fabrication, more conservative process parameters, and greater flexibility in the choice of nanoscale devices. The FPNI improves on a field-programmable gate array (FPGA) architecture by lifting the configuration bit and associated components out of the semiconductor plane and replacing them in the interconnect with nonvolatile switches, which decreases both the area and power consumption of the circuit. This is an example of a more comprehensive strategy for improving the efficiency of existing semiconductor technology: placing a level of intelligence and configurability in the interconnect can have a profound effect on integrated circuit performance, and can be used to significantly extend Moore's law without having to shrink the transistors. Compilation of standard benchmark circuits onto FPNI chip models shows reduced area (8 x to 25 x), reduced power, slightly lower clock speeds, and high defect tolerance-an FPNI chip with 20% defective junctions and 20% broken nanowires has an effective yield of 75% with no significant slowdown along the critical path, compared to a defect-free chip. Simulations show that the density and power improvements continue as both CMOS and nano fabrication parameters scale down, although the maximum clock rate decreases due to the high resistance of very small (<10 nm) metallic nanowires

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

SpaceVPX Switch-Controller, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Crossfield Technology proposes a SpaceVPX (VITA 78) Switch-Controller Module implemented in a state-of-the-art Field Programmable Gate Array (FPGA) System on Chip...

Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

National Research Council Canada - National Science Library

Bardouleau, Graham; Kulp, James

2005-01-01

In recent years the size and capabilities of field-programmable gate array (FPGA) devices have increased to a point where they can be deployed as adjunct processing elements within a multicomputer environment...

A programmable artificial retina

International Nuclear Information System (INIS)

Bernard, T.M.; Zavidovique, B.Y.; Devos, F.J.

1993-01-01

An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to 3 b, the authors have demonstrated both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semi-static shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as 6 global clock signals. The successful design, integration, and test of such a 65x76 Boolean retina on a 50-mm 2 CMOS 2-μm circuit are presented

Cryogenic on-chip multiplexer for the study of quantum transport in 256 split-gate devices

International Nuclear Information System (INIS)

Al-Taie, H.; Kelly, M. J.; Smith, L. W.; Xu, B.; Griffiths, J. P.; Beere, H. E.; Jones, G. A. C.; Ritchie, D. A.; Smith, C. G.; See, P.

2013-01-01

We present a multiplexing scheme for the measurement of large numbers of mesoscopic devices in cryogenic systems. The multiplexer is used to contact an array of 256 split gates on a GaAs/AlGaAs heterostructure, in which each split gate can be measured individually. The low-temperature conductance of split-gate devices is governed by quantum mechanics, leading to the appearance of conductance plateaux at intervals of 2e 2 /h. A fabrication-limited yield of 94% is achieved for the array, and a “quantum yield” is also defined, to account for disorder affecting the quantum behaviour of the devices. The quantum yield rose from 55% to 86% after illuminating the sample, explained by the corresponding increase in carrier density and mobility of the two-dimensional electron gas. The multiplexer is a scalable architecture, and can be extended to other forms of mesoscopic devices. It overcomes previous limits on the number of devices that can be fabricated on a single chip due to the number of electrical contacts available, without the need to alter existing experimental set ups

A 1T Dynamic Random Access Memory Cell Based on Gated Thyristor with Surrounding Gate Structure for High Scalability.

Science.gov (United States)

Kim, Hyungjin; Kim, Sihyun; Kim, Hyun-Min; Lee, Kitae; Kim, Sangwan; Pak, Byung-Gook

2018-09-01

In this study, we investigate a one-transistor (1T) dynamic random access memory (DRAM) cell based on a gated-thyristor device utilizing voltage-driven bistability to enable high-speed operations. The structural feature of the surrounding gate using a sidewall provides high scalability with regard to constructing an array architecture of the proposed devices. In addition, the operation mechanism, I-V characteristics, DRAM operations, and bias dependence are analyzed using a commercial device simulator. Unlike conventional 1T DRAM cells utilizing the floating body effect, excess carriers which are required to be stored to make two different states are not generated but injected from the n+ cathode region, giving the device high-speed operation capabilities. The findings here indicate that the proposed DRAM cell offers distinct advantages in terms of scalability and high-speed operations.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

Science.gov (United States)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Nucleic acid programmable protein array a just-in-time multiplexed protein expression and purification platform.

Science.gov (United States)

Qiu, Ji; LaBaer, Joshua

2011-01-01

Systematic study of proteins requires the availability of thousands of proteins in functional format. However, traditional recombinant protein expression and purification methods have many drawbacks for such study at the proteome level. We have developed an innovative in situ protein expression and capture system, namely NAPPA (nucleic acid programmable protein array), where C-terminal tagged proteins are expressed using an in vitro expression system and efficiently captured/purified by antitag antibodies coprinted at each spot. The NAPPA technology presented in this chapter enable researchers to produce and display fresh proteins just in time in a multiplexed high-throughput fashion and utilize them for various downstream biochemical researches of interest. This platform could revolutionize the field of functional proteomics with it ability to produce thousands of spatially separated proteins in high density with narrow dynamic rand of protein concentrations, reproducibly and functionally. Copyright © 2011 Elsevier Inc. All rights reserved.

High-Performance Linear Algebra Processor using FPGA

National Research Council Canada - National Science Library

Johnson, J

2004-01-01

With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS and LHC Transverse Dampers

CERN Document Server

Rossi, V

2002-01-01

In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in t...

Final Report and Documentation for the PLD11 Multipurpose Programmable Logic VME Board Design

International Nuclear Information System (INIS)

Hutchinson, Robert L.; Pierson, Lyndon G.; Robertson, Perry J.; Tarman, Thomas D.; Witzke, Edward L.

1999-01-01

The PLD11 board is a 9U VME board containing 11 Altera 10K100 Programmable Logic Devices, controlled impedance clock tree, VME interface, programming inteface, 0C3 (155 Mbps) interface and serial port. The 11 Altera 10K100 Programmable Logic Devices arranged to provide four 96 bit wide buses for a total of 384 parallel digital data lines in and out of the board that can operate up to 100 Mhz for a aggrigate throughput of 38.4 Gpbs. The 14.44'' X 15.75'' board has over 1.1 million programmable gates that can be programmed through a serial interace. The board contains a clock reference and 50 ohm clock distribution tree that can drive each of the eleven 10K100 devices with two critically timed clock references. Five external clock references can be used to drive five additional PLD 11 boards for a total of six boards operating all from the same synchronous clock reference. A system of six boards provides just under 7 million programmable gates

An electronically controlled automatic security access gate

Directory of Open Access Journals (Sweden)

Jonathan A. ENOKELA

2014-11-01

Full Text Available The security challenges being encountered in many places require electronic means of controlling access to communities, recreational centres, offices, and homes. The electronically controlled automated security access gate being proposed in this work helps to prevent an unwanted access to controlled environments. This is achieved mainly through the use of a Radio Frequency (RF transmitter-receiver pair. In the design a microcontroller is programmed to decode a given sequence of keys that is entered on a keypad and commands a transmitter module to send out this code as signal at a given radio frequency. Upon reception of this RF signal by the receiver module, another microcontroller activates a driver circuitry to operate the gate automatically. The codes for the microcontrollers were written in C language and were debugged and compiled using the KEIL Micro vision 4 integrated development environment. The resultant Hex files were programmed into the memories of the microcontrollers with the aid of a universal programmer. Software simulation was carried out using the Proteus Virtual System Modeling (VSM version 7.7. A scaled-down prototype of the system was built and tested. The electronically controlled automated security access gate can be useful in providing security for homes, organizations, and automobile terminals. The four-character password required to operate the gate gives the system an increased level of security. Due to its standalone nature of operation the system is cheaper to maintain in comparison with a manually operated type.

In situ synthesis of protein arrays.

Science.gov (United States)

He, Mingyue; Stoevesandt, Oda; Taussig, Michael J

2008-02-01

In situ or on-chip protein array methods use cell free expression systems to produce proteins directly onto an immobilising surface from co-distributed or pre-arrayed DNA or RNA, enabling protein arrays to be created on demand. These methods address three issues in protein array technology: (i) efficient protein expression and availability, (ii) functional protein immobilisation and purification in a single step and (iii) protein on-chip stability over time. By simultaneously expressing and immobilising many proteins in parallel on the chip surface, the laborious and often costly processes of DNA cloning, expression and separate protein purification are avoided. Recently employed methods reviewed are PISA (protein in situ array) and NAPPA (nucleic acid programmable protein array) from DNA and puromycin-mediated immobilisation from mRNA.

FPGA fabric specific optimization for RLT design

International Nuclear Information System (INIS)

Perwaiz, A.; Khan, S.A.

2010-01-01

This paper proposes a technique custom to the optimization requirements suited for a particular family of Field Programmable Gate Arrays (FPGAs). As FPGAs have introduced re configurable black boxes there is a need to perform optimization across FPGAs slice fabric in order to achieve optimum performance. Though the Register Transfer Level (RTL) Hardware Descriptive Language (HDL) code should be technology independent but in many design instances it is imperative to understand the target technology especially once the target device embeds dedicated arithmetic blocks. No matter what the degree of optimization of the algorithm is, the configuration of target device plays an important role as far as the device utilization and path delays are concerned Index Terms: Field Programmable Gate Arrays (FPGA), Compression Tree, Bit Width Reduction, Look Ahead Pipelining. (author)

Efficient processing of two-dimensional arrays with C or C++

Science.gov (United States)

Donato, David I.

2017-07-20

Because fast and efficient serial processing of raster-graphic images and other two-dimensional arrays is a requirement in land-change modeling and other applications, the effects of 10 factors on the runtimes for processing two-dimensional arrays with C and C++ are evaluated in a comparative factorial study. This study’s factors include the choice among three C or C++ source-code techniques for array processing; the choice of Microsoft Windows 7 or a Linux operating system; the choice of 4-byte or 8-byte array elements and indexes; and the choice of 32-bit or 64-bit memory addressing. This study demonstrates how programmer choices can reduce runtimes by 75 percent or more, even after compiler optimizations. Ten points of practical advice for faster processing of two-dimensional arrays are offered to C and C++ programmers. Further study and the development of a C and C++ software test suite are recommended.Key words: array processing, C, C++, compiler, computational speed, land-change modeling, raster-graphic image, two-dimensional array, software efficiency

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Pramana – Journal of Physics | Indian Academy of Sciences

Indian Academy of Sciences (India)

A new 4D chaotic system with hidden attractor and its engineering applications: Analog circuit design and field programmable gate array implementation .... On synchronisation of a class of complex chaotic systems with complex unknown ...

High-frequency self-aligned graphene transistors with transferred gate stacks

Science.gov (United States)

Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

2012-01-01

Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

Block QCA Fault-Tolerant Logic Gates

Science.gov (United States)

Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

2003-01-01

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA

100-nm gate lithography for double-gate transistors

Science.gov (United States)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Science.gov (United States)

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

Science.gov (United States)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Gating-ML: XML-based gating descriptions in flow cytometry.

Science.gov (United States)

Spidlen, Josef; Leif, Robert C; Moore, Wayne; Roederer, Mario; Brinkman, Ryan R

2008-12-01

The lack of software interoperability with respect to gating due to lack of a standardized mechanism for data exchange has traditionally been a bottleneck, preventing reproducibility of flow cytometry (FCM) data analysis and the usage of multiple analytical tools. To facilitate interoperability among FCM data analysis tools, members of the International Society for the Advancement of Cytometry (ISAC) Data Standards Task Force (DSTF) have developed an XML-based mechanism to formally describe gates (Gating-ML). Gating-ML, an open specification for encoding gating, data transformations and compensation, has been adopted by the ISAC DSTF as a Candidate Recommendation. Gating-ML can facilitate exchange of gating descriptions the same way that FCS facilitated for exchange of raw FCM data. Its adoption will open new collaborative opportunities as well as possibilities for advanced analyses and methods development. The ISAC DSTF is satisfied that the standard addresses the requirements for a gating exchange standard.

Gates, GAVI, the glorious global funds and more: all you ever wanted to know.

Science.gov (United States)

Nossal, Gustav J V

2003-02-01

Global immunization programmes have achieved some remarkable successes. In 1977, Frank Fenner's Commission declared smallpox to have been eradicated by an 11-year-long intensive campaign. The Expanded Programme on Immunization encompassed six important childhood vaccines and reached over three-quarters of the world's children. Polio eradication has gone remarkably well, with only 10 out of 200 countries reporting residual cases. But amidst all the good news, there is also bad news. Coverage is variable; infrastructure is crumbling; and newer vaccines are not being incorporated in many country programmes. The Bill and Melinda Gates Foundation has introduced a new dynamic here. From their initial gift of $100 million in December 1998, their commitment to date is US$1.5 billion - and rising. At the centre is a Global Children's Vaccine Fund which permitted the launch, in January 2000, of the Global Alliance for Vaccines and Immunization. This is targeted to the 74 poorest countries of the world and is designed to improve vaccination infrastructure, to purchase newer vaccines and to support research and development. Even before we know how successful this programme will be, it has had its imitators. The Global Fund to Fight AIDS, TB and Malaria borrowed many concepts from GAVI. The Global Alliance for Improved Nutrition announced in May 2002 does so as well, and is heavily supported by Gates. Highly effective parasite control programmes antedate all this but will be much strengthened. However, we still face a sizeable budgetary gap both for research and for bringing the best advances to all people who need them.

A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

Science.gov (United States)

Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

2016-06-28

Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

New Developments in Error Detection and Correction Strategies for Critical Applications

Science.gov (United States)

Berg, Melanie; Label, Ken

2017-01-01

The presentation will cover a variety of mitigation strategies that were developed for critical applications. An emphasis is placed on strengths and weaknesses per mitigation technique as it pertains to different Field programmable gate array (FPGA) device types.

Flexible, fpga-based electronics for modular robots

DEFF Research Database (Denmark)

Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

2008-01-01

In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... the FPGA and therefore integrate task-specific electronics without physically changing the electronics or we can reconfigure the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...

A Time Domain Reflectometer with 100 ps precision implemented in a cost-effective FPGA for the test of the KLOE-2 Inner Tracker readout anodes

Energy Technology Data Exchange (ETDEWEB)

Bencivenni, G. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Czerwinski, E. [Institute of Physics, Jagiellonian University, Krakow (Poland); De Lucia, E. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); De Robertis, G. [INFN Sezione di Bari, Bari (Italy); Domenici, D. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Erriquez, O. [INFN Sezione di Bari, Bari (Italy); Dipartimento di Fisica, Università degli Studi di Bari, Bari (Italy); Fanizzi, G., E-mail: Giampiero.Fanizzi@ba.infn.it [INFN Sezione di Bari, Bari (Italy); Dipartimento di Fisica, Università degli Studi di Bari, Bari (Italy); Felici, G. [Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Liuzzi, R.; Loddo, F.; Mongelli, M. [INFN Sezione di Bari, Bari (Italy); Morello, G. [INFN gruppo collegato di Cosenza, Cosenza (Italy); Laboratori Nazionali di Frascati dell' INFN, Frascati (Italy); Ranieri, A.; Valentino, V. [INFN Sezione di Bari, Bari (Italy)

2013-01-11

A Time Domain Reflectometer implemented in a single cost-effective Field Programmable Gate Array device is shown to achieve a precision around 100 ps. The Time to Digital Converter section of the device is based on a tapped delay line followed by an encoder and shows both Differential and Integral Non-Linearity below one least significant bit. The same Field Programmable Gate Array houses an 8051 8-bits microprocessor, for the control of the pulse signals generation, the acquisition and the first treatment of raw data. Principles of operation, architecture, performance and preliminary trials on the prototype are presented in this paper. As an example of possible application, the proposed circuit has been usefully used to perform the quality control of the micro-strip anodic planes of the Gas Electron Multiplier Inner Tracker of the KLOE-2 experiment.

VHDL, FPGA and the master trigger controller of BES

International Nuclear Information System (INIS)

Guo Yanan; Wang Jufang; Zhao Dixin

1996-01-01

A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing

International Nuclear Information System (INIS)

Potluri, U S; Madanayake, A; Rajapaksha, N; Cintra, R J; Bayer, F M

2012-01-01

Multi-beamforming is an important requirement for broadband space imaging applications based on dense aperture arrays (AAs). Usually, the discrete Fourier transform is the transform of choice for AA electromagnetic imaging. Here, the discrete cosine transform (DCT) is proposed as an alternative, enabling the use of emerging fast algorithms that offer greatly reduced complexity in digital arithmetic circuits. We propose two novel high-speed digital architectures for recently proposed fast algorithms (Bouguezel, Ahmad and Swamy 2008 Electron. Lett. 44 1249–50) (BAS-2008) and (Cintra and Bayer 2011 IEEE Signal Process. Lett. 18 579–82) (CB-2011) that provide good approximations to the DCT at zero multiplicative complexity. Further, we propose a novel DCT approximation having zero multiplicative complexity that is shown to be better for multi-beamforming AAs when compared to BAS-2008 and CB-2011. The far-field array pattern of ideal DCT, BAS-2008, CB-2011 and proposed approximation are investigated with error analysis. Extensive hardware realizations, implementation details and performance metrics are provided for synchronous field programmable gate array (FPGA) technology from Xilinx. The resource consumption and speed metrics of BAS-2008, CB-2011 and the proposed approximation are investigated as functions of system word size. The 8-bit versions are mapped to emerging asynchronous FPGAs leading to significantly increased real-time throughput with clock rates at up to 925.6 MHz implying the fastest DCT approximations using reconfigurable logic devices in the literature. (paper)

Logical Qubit in a Linear Array of Semiconductor Quantum Dots

Directory of Open Access Journals (Sweden)

Cody Jones

2018-06-01

Full Text Available We design a logical qubit consisting of a linear array of quantum dots, we analyze error correction for this linear architecture, and we propose a sequence of experiments to demonstrate components of the logical qubit on near-term devices. To avoid the difficulty of fully controlling a two-dimensional array of dots, we adapt spin control and error correction to a one-dimensional line of silicon quantum dots. Control speed and efficiency are maintained via a scheme in which electron spin states are controlled globally using broadband microwave pulses for magnetic resonance, while two-qubit gates are provided by local electrical control of the exchange interaction between neighboring dots. Error correction with two-, three-, and four-qubit codes is adapted to a linear chain of qubits with nearest-neighbor gates. We estimate an error correction threshold of 10^{-4}. Furthermore, we describe a sequence of experiments to validate the methods on near-term devices starting from four coupled dots.

Reconfigurable digital receiver design and application for instantaneous polarimetric measurement

NARCIS (Netherlands)

Wang, Z.; Krasnov, O.A.; Babur, G.P.; Ligthart, L.P.; Van der Zwan, F.

2011-01-01

This paper presents the development of a reconfigurable receiver to undertake challenging signal processing tasks for a novel polarimetric radar system. The field-programmable gate arrays (FPGAs)-based digital receiver samples incoming signals at intermediate frequency (IF) and processes signals

Browse Title Index

African Journals Online (AJOL)

Items 51 - 100 of 546 ... Vol 9, No 1 (2011), Application of Field programmable Gate Array to ... Vol 5, No 1 (2007), Barriers To Choice Of Women Occupation In ... Road Transport – Study Of Gibraltar Engineering Company, Aba, Nigeria, Abstract.

Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

DEFF Research Database (Denmark)

Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

2012-01-01

Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...

Implementation of fractional order integrator/differentiator on field programmable gate array

OpenAIRE

K.P.S. Rana; V. Kumar; N. Mittra; N. Pramanik

2016-01-01

Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus. For the past two decades, applications of fractional order calculus, in system modeling, control and signal processing, have grown rapidly. This paper presents a systematic procedure for hardware implementation of the basic operators of fractio...

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

Science.gov (United States)

2008-07-01

Cruickshank, J. E. Gaffney and R. D. Melbourne, Australia : ACM, 1992. Proceedings of the 14th International Conference on Software Engineering. pp. 327-337... Ridge Compiler Collection Stone Ridge Technology 48 A.3 FPGA Architecture Survey Company Niche 3P plus 1 Technology Coarse-grain configurable IP

Development and applications of a computer-aided phased array assembly for ultrasonic testing

International Nuclear Information System (INIS)

Schenk, G.; Montag, H.J.; Wuestenberg, H.; Erhard, A.

1985-01-01

The use of modern electronic equipment for programmable signal delay increasingly allows transit-time controlled phased arrays to be applied in non-destructive, ultrasonic materials testing. A phased-array assembly is described permitting fast variation of incident angle of acoustic wave and of sonic beam focus, together with numerical evaluation of measured data. Phased arrays can be optimized by adding programmable electronic equipment so that the quality of conventional designs can be achieved. Applications of the new technical improvement are explained, referring to stress corrosion cracking, turbine testing, echo tomography of welded joints. (orig./HP) [de

Unusual Voltage-Gated Sodium Currents as Targets for Pain.

Science.gov (United States)

Barbosa, C; Cummins, T R

2016-01-01

Pain is a serious health problem that impacts the lives of many individuals. Hyperexcitability of peripheral sensory neurons contributes to both acute and chronic pain syndromes. Because voltage-gated sodium currents are crucial to the transmission of electrical signals in peripheral sensory neurons, the channels that underlie these currents are attractive targets for pain therapeutics. Sodium currents and channels in peripheral sensory neurons are complex. Multiple-channel isoforms contribute to the macroscopic currents in nociceptive sensory neurons. These different isoforms exhibit substantial variations in their kinetics and pharmacology. Furthermore, sodium current complexity is enhanced by an array of interacting proteins that can substantially modify the properties of voltage-gated sodium channels. Resurgent sodium currents, atypical currents that can enhance recovery from inactivation and neuronal firing, are increasingly being recognized as playing potentially important roles in sensory neuron hyperexcitability and pain sensations. Here we discuss unusual sodium channels and currents that have been identified in nociceptive sensory neurons, describe what is known about the molecular determinants of the complex sodium currents in these neurons. Finally, we provide an overview of therapeutic strategies to target voltage-gated sodium currents in nociceptive neurons. Copyright © 2016 Elsevier Inc. All rights reserved.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

Science.gov (United States)

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

Many-body strategies for multiqubit gates: Quantum control through Krawtchouk-chain dynamics

Science.gov (United States)

Groenland, Koen; Schoutens, Kareljan

2018-04-01

We propose a strategy for engineering multiqubit quantum gates. As a first step, it employs an eigengate to map states in the computational basis to eigenstates of a suitable many-body Hamiltonian. The second step employs resonant driving to enforce a transition between a single pair of eigenstates, leaving all others unchanged. The procedure is completed by mapping back to the computational basis. We demonstrate the strategy for the case of a linear array with an even number N of qubits, with specific X X +Y Y couplings between nearest neighbors. For this so-called Krawtchouk chain, a two-body driving term leads to the iSWAPN gate, which we numerically test for N =4 and 6.

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

A novel optical gating method for laser gated imaging

Science.gov (United States)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

Improvement of high-fold gamma-ray data processing: the spherical gate method

CERN Document Server

Theisen, C; Stezowski, O; Vivien, J P

1999-01-01

A new method for optimizing the processing of events from a highly efficient large array gamma-ray detector is described in this article. The spherical gates technique, developed to project high-fold events, consists of optimizing n-dimensional gate shape as a function of peak width and shape of each detector. Formulas in closed form are proposed for determining the projected statistics from coincidence fold and peak shape and for estimating the increased quality of projected spectra. This procedure has been tested on high-fold, high statistics data sets including superdeformed cascades. Compared to the classical 'square-gate' technique, better peak-to-background ratios as well as a reduction in fluctuations are observed. A quality parameter is defined to characterize the optimal parameter set. This method leads roughly to a gain in spectral quality equivalent of one fold. It is also shown that the efficiency of the method increases with coincidence fold. This should be particularly suited for future higher-f...

Time-area efficient multiplier-free recursive filter architectures for FPGA implementation

DEFF Research Database (Denmark)

Shajaan, Mohammad; Sørensen, John Aasted

1996-01-01

Simultaneous design of multiplier-free recursive filters (IIR filters) and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The hardware design methodology leads to high performance recursive filters with sampling frequencies in the interval 15-21 MHz (...

Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms

Directory of Open Access Journals (Sweden)

He Chen

2011-12-01

Full Text Available This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT suitable for electronic warfare (EW applications. When implementing the FFT algorithm on field-programmable gate array (FPGA platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA, fast Fourier transform (FFT, large point reconfigured, signal processing system.

Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy

International Nuclear Information System (INIS)

Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki

2011-01-01

Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.

Design and implementation of a radiation hardened silicon on sapphire (SOS) embedded signal conditioning unit controller (SCUC) for the RAPID instrument on the Cluster satellites

International Nuclear Information System (INIS)

Ersland, L.

1992-07-01

The Cluster mission consistens of four spacecrafts equipped with instruments capable of making comprehensive measurements of plasma particles and electromagnetic fields. The RAPID (Research with Adaptive Particle Imaging Detectors) spectrometer is one of many instruments on board the Cluster satellites. It is designed for fast analysis of energetic electrons and ions with a complete coverage of the unit sphere in phase space. This thesis describes the development and testing of an embedded controller for the Spectroscopic Camera for Electrons, Neutral and Ion Compositions (SCENIC), which is a part of the RAPID instrument. The design is implemented in two different CMOS circuit technologies, namely Actel's Field Programmable Gate Arrays and GEC Plessey's CMOS Silicon On Sapphire (SOS) gate array. The prototypes of the SOS gate array have been verified and characterized. This includes measurements of DC and AC parameters under different conditions, including total dose of gamma irradiation. 42 refs., 92 figs., 44 tabs

[A capillary blood flow velocity detection system based on linear array charge-coupled devices].

Science.gov (United States)

Zhou, Houming; Wang, Ruofeng; Dang, Qi; Yang, Li; Wang, Xiang

2017-12-01

In order to detect the flow characteristics of blood samples in the capillary, this paper introduces a blood flow velocity measurement system based on field-programmable gate array (FPGA), linear charge-coupled devices (CCD) and personal computer (PC) software structure. Based on the analysis of the TCD1703C and AD9826 device data sheets, Verilog HDL hardware description language was used to design and simulate the driver. Image signal acquisition and the extraction of the real-time edge information of the blood sample were carried out synchronously in the FPGA. Then a series of discrete displacement were performed in a differential operation to scan each of the blood samples displacement, so that the sample flow rate could be obtained. Finally, the feasibility of the blood flow velocity detection system was verified by simulation and debugging. After drawing the flow velocity curve and analyzing the velocity characteristics, the significance of measuring blood flow velocity is analyzed. The results show that the measurement of the system is less time-consuming and less complex than other flow rate monitoring schemes.

Empirical Verification of Fault Models for FPGAs Operating in the Subcritical Voltage Region

DEFF Research Database (Denmark)

Birklykke, Alex Aaen; Koch, Peter; Prasad, Ramjee

2013-01-01

We present a rigorous empirical study of the bit-level error behavior of field programmable gate arrays operating in the subcricital voltage region. This region is of significant interest as voltage-scaling under normal circumstances is halted by the first occurrence of errors. However, accurate...

High speed numerical integration algorithm using FPGA | Razak ...

African Journals Online (AJOL)

Conventionally, numerical integration algorithm is executed in software and time consuming to accomplish. Field Programmable Gate Arrays (FPGAs) can be used as a much faster, very efficient and reliable alternative to implement the numerical integration algorithm. This paper proposed a hardware implementation of four ...

Consideration of the accuracy by variation of respiration in real-time position management respiratory gating system

International Nuclear Information System (INIS)

Na, Jun Young; Kang, Tae Young; Beak, Geum Mun; Kwon, Gyeong Tae

2013-01-01

Respiratory Gated Radiation Therapy (RGRT) has been carried out using RPM (Real-time Position Management) Respiratory Gating System (version 1.7.5, varian, USA) in Asan Medical Center. This study was to analyze and evaluate the accuracy of Respiratory Gated Radiation Therapy (RGRT) according to variation of respiration. Making variation of respiration using Motion Phantom:QUASAR Programmable Respiratory Motion Phantom (Moudus Medical Device Inc. CANADA) able to adjust respiration pattern randomly was varying period, amplitude and baseline by analyze 50 patient's respiration of lung and liver cancer. One of the variations of respiration is baseline shift gradually downward per 0.01 cm, 0.03 cm, 0.05 cm. The other variation of respiration is baseline shift accidently downward per 0.2 cm, 0.4 cm, 0.6 cm, 0.8 cm. Experiments were performed in the same way that is used RPM Respiratory Gating System (phase gating, usually 30-70% gating) in Asan Medical Center. It was all exposed radiation under one of the conditions of baseline shift gradually downward per 0.01 cm, 0.03 cm, 0.05 cm. Under the other condition of baseline shift accidently downward per 0.2 cm, 0.4 cm, 0.6 cm, 0.8 cm equally radiation was exposed. The variations of baseline shifts didn't accurately reflect on phase gating in RPM Respiratory Gating System. This inexactitude makes serious uncertainty in Respiratory Gated Radiation Therapy. So, Must be stabilized breathing of patient before conducting Respiratory Gated Radiation Therapy. also must be monitored breathing of patient in the middle of treatment. If you observe considerable changes of breathing when conducting Respiratory Gated Radiation Therapy. Stopping treatment immediately and then must be need to recheck treatment site using fluoroscopy. If patient's respiration rechecked using fluoroscopy restabilize, it is possible to restart Respiratory Gated Radiation Therapy

System Realization of Broad Band Digital Beam Forming for Digital Array Radar

Directory of Open Access Journals (Sweden)

Wang Feng

2013-09-01

Full Text Available Broad band Digital Beam Forming (DBF is the key technique for the realization of Digital Array Radar (DAR. We propose the method of combination realization of the channel equalization and DBF time delay filter function by using adaptive Sample Matrix Inversion algorithm. The broad band DBF function is realized on a new DBF module based on parallel fiber optic engines and Field Program Gate Array (FPGA. Good performance is achieved when it is used to some radar products.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Science.gov (United States)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Report 3

Energy Technology Data Exchange (ETDEWEB)

Britton, Jr, Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Shelton, Jacob H. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

2015-03-01

As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios when human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments because of the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is a report of the activities involving Task 3 of the Nuclear Energy Enabling Technologies (NEET) 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays [1]. Evaluation of the performance of the system for both pre- and post-irradiation as well as operation at elevated temperature will be performed. Detailed performance of the system will be documented to ensure the design meets requirements prior to any extended evaluation. A suite of tests will be developed which will allow evaluation before and after irradiation and during temperature. Selection of the radiation exposure facilities will be determined in the early phase of the project. Radiation exposure will consist of total integrated dose (TID) up to 200 kRad or above with several intermediate doses during test. Dose rates will be in various ranges determined by the facility that will be used with a target of 30 kRad/hr. Many samples of the pre-commercial devices to be used will have been tested in previous projects to doses of at least 300 kRad and temperatures up to 125C. The complete systems will therefore be tested for performance at intermediate doses. Extended temperature testing will be performed up to the limit of the commercial sensors. The test suite performed at each test point will consist of operational testing of the three basic

Linear-optical programmable quantum router

Czech Academy of Sciences Publication Activity Database

Lemr, K.; Černoch, Antonín

2013-01-01

Roč. 300, JUL (2013), s. 282-285 ISSN 0030-4018 R&D Projects: GA ČR GAP205/12/0382 Institutional research plan: CEZ:AV0Z10100522 Keywords : quantum router * quantum information processing * photon pairs * quantum communications * programmable phase gate Subject RIV: BH - Optics, Masers, Lasers Impact factor: 1.542, year: 2013 http://ac.els-cdn.com/S0030401813002563/1-s2.0-S0030401813002563-main.pdf?_tid=d1f7d17a-66e9-11e3-aa5e-00000aab0f6c&acdnat=1387264198_99aef4d40cf81f69

Ionizing radiation effects on floating gates

International Nuclear Information System (INIS)

Cellere, G.; Paccagnella, A.; Visconti, A.; Bonanomi, M.

2004-01-01

Floating gate (FG) memories, and in particular Flash, are the dominant among modern nonvolatile memory technologies. Their performance under ionizing radiation was traditionally studied for the use in space, but has become of general interest in recent years. We are showing results on the charge loss from programmed FG arrays after 10 keV x-rays exposure. Exposure to ionizing radiation results in progressive discharge of the FG. More advanced devices, featuring smaller FG, are less sensitive to ionizing radiation that older ones. The reason is identified in the photoemission of electrons from FG, since at high doses it dominates over charge loss deriving from electron/hole pairs generation in the oxides

A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

KAUST Repository

Tella, Sherif Adekunle

2018-04-30

Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

KAUST Repository

Tella, Sherif Adekunle; Alcheikh, Nouha; Younis, Mohammad I.

2018-01-01

Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

Biological applications of an LCoS-based programmable array microscope (PAM)

Science.gov (United States)

Hagen, Guy M.; Caarls, Wouter; Thomas, Martin; Hill, Andrew; Lidke, Keith A.; Rieger, Bernd; Fritsch, Cornelia; van Geest, Bert; Jovin, Thomas M.; Arndt-Jovin, Donna J.

2007-02-01

We report on a new generation, commercial prototype of a programmable array optical sectioning fluorescence microscope (PAM) for rapid, light efficient 3D imaging of living specimens. The stand-alone module, including light source(s) and detector(s), features an innovative optical design and a ferroelectric liquid-crystal-on-silicon (LCoS) spatial light modulator (SLM) instead of the DMD used in the original PAM design. The LCoS PAM (developed in collaboration with Cairn Research, Ltd.) can be attached to a port of a(ny) unmodified fluorescence microscope. The prototype system currently operated at the Max Planck Institute incorporates a 6-position high-intensity LED illuminator, modulated laser and lamp light sources, and an Andor iXon emCCD camera. The module is mounted on an Olympus IX71 inverted microscope with 60-150X objectives with a Prior Scientific x,y, and z high resolution scanning stages. Further enhancements recently include: (i) point- and line-wise spectral resolution and (ii) lifetime imaging (FLIM) in the frequency domain. Multiphoton operation and other nonlinear techniques should be feasible. The capabilities of the PAM are illustrated by several examples demonstrating single molecule as well as lifetime imaging in live cells, and the unique capability to perform photoconversion with arbitrary patterns and high spatial resolution. Using quantum dot coupled ligands we show real-time binding and subsequent trafficking of individual ligand-growth factor receptor complexes on and in live cells with a temporal resolution and sensitivity exceeding those of conventional CLSM systems. The combined use of a blue laser and parallel LED or visible laser sources permits photoactivation and rapid kinetic analysis of cellular processes probed by photoswitchable visible fluorescent proteins such as DRONPA.

Real-Time Plasma Control Tools for Advanced Tokamak Operation

International Nuclear Information System (INIS)

Varandas, C. A. F.; Sousa, J.; Rodrigues, A. P.; Carvalho, B. B.; Fernandes, H.; Batista, A. J.; Cruz, N.; Combo, A.; Pereira, R. C.

2006-01-01

Real-time control will play an important role in the operation and scientific exploitation of the new generation fusion devices. This paper summarizes the real-time systems and diagnostics developed by the Portuguese Fusion Euratom Association based on digital signal processors and field programmable gate arrays

Time-area efficient multiplier-free filter architectures for FPGA implementation

DEFF Research Database (Denmark)

Shajaan, Mohammad; Nielsen, Karsten; Sørensen, John Aasted

1995-01-01

Simultaneous design of multiplier-free filters and their hardware implementation in Xilinx field programmable gate array (XC4000) is presented. The filter synthesis method is a new approach based on cascade coupling of low order sections. The complexity of the design algorithm is 𝒪 (filter o...

The oxidized porous silicon field emission array

International Nuclear Information System (INIS)

Smith, D.D.; Demroff, H.P.; Elliott, T.S.; Kasprowicz, T.B.; Lee, B.; Mazumdar, T.K.; McIntyre, P.M.; Pang, Y.; Trost, H.J.

1993-01-01

The goal of developing a highly efficient microwave power source has led the authors to investigate new methods of electron field emission. One method presently under consideration involves the use of oxidized porous silicon thin films. The authors have used this technology to fabricate the first working field emission arrays from this substance. This approach reduces the diameter of an individual emitter to the nanometer scale. Tests of the first samples are encouraging, with extracted electron currents to nearly 1 mA resulting from less than 20 V of pulsed DC gate voltage. Modulated emission at 5 MHz was also observed. Developments of a full-scale emission array capable of delivering an electron beam at 18 GHz of minimum density 100 A/cm 2 is in progress

Ryanodine receptor gating controls generation of diastolic calcium waves in cardiac myocytes

Science.gov (United States)

Petrovič, Pavol; Valent, Ivan; Cocherová, Elena; Pavelková, Jana

2015-01-01

The role of cardiac ryanodine receptor (RyR) gating in the initiation and propagation of calcium waves was investigated using a mathematical model comprising a stochastic description of RyR gating and a deterministic description of calcium diffusion and sequestration. We used a one-dimensional array of equidistantly spaced RyR clusters, representing the confocal scanning line, to simulate the formation of calcium sparks. Our model provided an excellent description of the calcium dependence of the frequency of diastolic calcium sparks and of the increased tendency for the production of calcium waves after a decrease in cytosolic calcium buffering. We developed a hypothesis relating changes in the propensity to form calcium waves to changes of RyR gating and tested it by simulation. With a realistic RyR gating model, increased ability of RyR to be activated by Ca2+ strongly increased the propensity for generation of calcium waves at low (0.05–0.1-µM) calcium concentrations but only slightly at high (0.2–0.4-µM) calcium concentrations. Changes in RyR gating altered calcium wave formation by changing the calcium sensitivity of spontaneous calcium spark activation and/or the average number of open RyRs in spontaneous calcium sparks. Gating changes that did not affect RyR activation by Ca2+ had only a weak effect on the propensity to form calcium waves, even if they strongly increased calcium spark frequency. Calcium waves induced by modulating the properties of the RyR activation site could be suppressed by inhibiting the spontaneous opening of the RyR. These data can explain the increased tendency for production of calcium waves under conditions when RyR gating is altered in cardiac diseases. PMID:26009544

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

International Nuclear Information System (INIS)

Che, Yongli; Zhang, Yating; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

2016-01-01

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV th  ∼ 15 V) and a long retention time (>10 5  s). The magnitude of ΔV th depended on both P/E voltages and the bias voltage (V DS ): ΔV th was a cubic function to V P/E and linearly depended on V DS . Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

Real-time heterogeneous video transcoding for low-power applications

CERN Document Server

Elarabi, Tarek; Bayoumi, Magdy

2014-01-01

This book introduces a novel transcoding algorithm for real time video applications, designed to overcome inter-operability problems between MPEG-2 to H.264/AVC. The new algorithm achieves 92.8% reduction in the transcoding run time at a price of an acceptable Peak Signal-to-Noise Ratio (PSNR) degradation, enabling readers to use it for real time video applications. The algorithm described is evaluated through simulation and experimental results. In addition, the authors present a hardware implementation of the new algorithm using Field Programmable Gate Array (FPGA) and Application-specific standard products (ASIC).   • Describes a novel transcoding algorithm for real time video applications, designed to overcome inter-operability problems between H.264/AVC to MPEG-2; • Implements algorithm presented using Field Programmable Gate Array (FPGA) and Application-specific Integrated Circuit (ASIC); • Demonstrates the solution to real problems, with verification through simulation and experimental result...

Pulling the trigger on LHC electronics

CERN Document Server

CERN. Geneva

2001-01-01

The conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology. The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector perform...

Implementation of FPGA-Based Diverse Protection System

International Nuclear Information System (INIS)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

2015-01-01

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

Implementation of FPGA-Based Diverse Protection System

Energy Technology Data Exchange (ETDEWEB)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

2015-10-15

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

Size dependence in tunneling spectra of PbSe quantum-dot arrays.

Science.gov (United States)

Ou, Y C; Cheng, S F; Jian, W B

2009-07-15

Interdot Coulomb interactions and collective Coulomb blockade were theoretically argued to be a newly important topic, and experimentally identified in semiconductor quantum dots, formed in the gate confined two-dimensional electron gas system. Developments of cluster science and colloidal synthesis accelerated the studies of electron transport in colloidal nanocrystal or quantum-dot solids. To study the interdot coupling, various sizes of two-dimensional arrays of colloidal PbSe quantum dots are self-assembled on flat gold surfaces for scanning tunneling microscopy and scanning tunneling spectroscopy measurements at both room and liquid-nitrogen temperatures. The tip-to-array, array-to-substrate, and interdot capacitances are evaluated and the tunneling spectra of quantum-dot arrays are analyzed by the theory of collective Coulomb blockade. The current-voltage of PbSe quantum-dot arrays conforms properly to a scaling power law function. In this study, the dependence of tunneling spectra on the sizes (numbers of quantum dots) of arrays is reported and the capacitive coupling between quantum dots in the arrays is explored.

Methodology for Assessing the Degree of Internationalization of Business Academic Study Programmes

OpenAIRE

Dan-Cristian Dabija; Cătălin Postelnicu; Nicolae Al. Pop

2014-01-01

The purpose of this paper is to develop a methodology for assessing the degree of internationalization of undergraduate, Master’s and doctoral business programmes with the aid of complex indicators designed to capture the vast array of characteristics displayed by these programmes and contribute to their promotion in the international academic competition. The methodology should include both general indicators applicable to any study programme and some indicators that are specifically develop...

Linear gate

International Nuclear Information System (INIS)

Suwono.

1978-01-01

A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

OpenAIRE

Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.

2001-01-01

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interco...

A high-resolution programmable Vernier delay generator based on carry chains in FPGA.

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20  ° C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

Science.gov (United States)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Development of a Crosstalk Suppression Algorithm for KID Readout

Science.gov (United States)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

Auto and hetero-associative memory using a 2-D optical logic gate

Science.gov (United States)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

New gate opening hours

CERN Multimedia

GS Department

2009-01-01

Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

Predictive digital peak current mode controller for DC-DC converters capable of operating over the full 0-100% duty cycle range

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2017-01-01

) and discontinuous conduction mode (DCM) and supports high switching frequencies even with low cost A/D converters. The proposed controller is implemented in a Field Programmable Gate Array (FPGA) to control a 450 W buck converter and the experimental results verify the controller's capability to operate in the full...

Real-time gigabit DMT transmission over plastic optical fibre

NARCIS (Netherlands)

Lee, S.C.J.; Breyer, F.; Cárdenas, D.; Randel, S.; Koonen, A.M.J.

2009-01-01

For the first time, a real-time 1.25 Gbit/s discrete multitone (DMT) transmitter implemented in a field-programmable gate array is demonstrated for use in low-cost, standard 1 mm step-index plastic optical fibre applications based on a commercial resonant-cavity LED and a large-diameter

FPGA Based Efficient Design of Traffic Light Controller using Frequency Scaling for Family of HSTL

DEFF Research Database (Denmark)

Sharma, Shivani; Khan, Sadiq; Das, Bhagwan

2016-01-01

utilizes least amount of power and is well tested in hardware using Xilinx Virtex6 Field Programmable gate array. FPGA designs are not only cheaper than ASIC designs but have many positive features like speed and performance. So the factors that contribute to power consumption for family of HSTL...

FPGA Implementation of Decimal Processors for Hardware Acceleration

DEFF Research Database (Denmark)

Borup, Nicolas; Dindorp, Jonas; Nannarelli, Alberto

2011-01-01

Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial trans...... execution on the CPU of the hosting computer....

Modified impedance source inverter for power conditioning system

Indian Academy of Sciences (India)

DC link voltage boost, reduced total harmonic distortion of output current and voltage, better voltage gain and wide range of output voltage controlcan be achieved easily with improved power quality. Experimental set-up of the modified impedance source inverter with Field Programmable Gate Array (FPGA) controller has ...

ISAC's Gating-ML 2.0 data exchange standard for gating description.

Science.gov (United States)

Spidlen, Josef; Moore, Wayne; Brinkman, Ryan R

2015-07-01

The lack of software interoperability with respect to gating has traditionally been a bottleneck preventing the use of multiple analytical tools and reproducibility of flow cytometry data analysis by independent parties. To address this issue, ISAC developed Gating-ML, a computer file format to encode and interchange gates. Gating-ML 1.5 was adopted and published as an ISAC Candidate Recommendation in 2008. Feedback during the probationary period from implementors, including major commercial software companies, instrument vendors, and the wider community, has led to a streamlined Gating-ML 2.0. Gating-ML has been significantly simplified and therefore easier to support by software tools. To aid developers, free, open source reference implementations, compliance tests, and detailed examples are provided to stimulate further commercial adoption. ISAC has approved Gating-ML as a standard ready for deployment in the public domain and encourages its support within the community as it is at a mature stage of development having undergone extensive review and testing, under both theoretical and practical conditions. © 2015 International Society for Advancement of Cytometry.

Determination of prospective displacement-based gate threshold for respiratory-gated radiation delivery from retrospective phase-based gate threshold selected at 4D CT simulation

International Nuclear Information System (INIS)

Vedam, S.; Archambault, L.; Starkschall, G.; Mohan, R.; Beddar, S.

2007-01-01

Four-dimensional (4D) computed tomography (CT) imaging has found increasing importance in the localization of tumor and surrounding normal structures throughout the respiratory cycle. Based on such tumor motion information, it is possible to identify the appropriate phase interval for respiratory gated treatment planning and delivery. Such a gating phase interval is determined retrospectively based on tumor motion from internal tumor displacement. However, respiratory-gated treatment is delivered prospectively based on motion determined predominantly from an external monitor. Therefore, the simulation gate threshold determined from the retrospective phase interval selected for gating at 4D CT simulation may not correspond to the delivery gate threshold that is determined from the prospective external monitor displacement at treatment delivery. The purpose of the present work is to establish a relationship between the thresholds for respiratory gating determined at CT simulation and treatment delivery, respectively. One hundred fifty external respiratory motion traces, from 90 patients, with and without audio-visual biofeedback, are analyzed. Two respiratory phase intervals, 40%-60% and 30%-70%, are chosen for respiratory gating from the 4D CT-derived tumor motion trajectory. From residual tumor displacements within each such gating phase interval, a simulation gate threshold is defined based on (a) the average and (b) the maximum respiratory displacement within the phase interval. The duty cycle for prospective gated delivery is estimated from the proportion of external monitor displacement data points within both the selected phase interval and the simulation gate threshold. The delivery gate threshold is then determined iteratively to match the above determined duty cycle. The magnitude of the difference between such gate thresholds determined at simulation and treatment delivery is quantified in each case. Phantom motion tests yielded coincidence of simulation

A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

Science.gov (United States)

Männer, R.

1989-12-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8 x 8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology.

A programmable systolic array correlator as a trigger processor for electron pairs in RICH (ring image Cherenkov) counters

International Nuclear Information System (INIS)

Maenner, R.

1989-01-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128x128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8x8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology. (orig.)

An innovative telescope control system architecture for SST-GATE telescopes at the CTA Observatory

Science.gov (United States)

Fasola, Gilles; Mignot, Shan; Laporte, Philippe; Abchiche, Abdel; Buchholtz, Gilles; Jégouzo, Isabelle

2014-07-01

SST-GATE (Small Size Telescope - GAmma-ray Telescope Elements) is a 4-metre telescope designed as a prototype for the Small Size Telescopes (SST) of the Cherenkov Telescope Array (CTA), a major facility for the very high energy gamma-ray astronomy of the next three decades. In this 100-telescope array there will be 70 SSTs, involving a design with an industrial view aiming at long-term service, low maintenance effort and reduced costs. More than a prototype, SST-GATE is also a fully functional telescope that shall be usable by scientists and students at the Observatoire de Meudon for 30 years. The Telescope Control System (TCS) is designed to work either as an element of a large array driven by an array controller or in a stand-alone mode with a remote workstation. Hence it is built to be autonomous with versatile interfacing; as an example, pointing and tracking —the main functions of the telescope— are managed onboard, including astronomical transformations, geometrical transformations (e.g. telescope bending model) and drive control. The core hardware is a CompactRIO (cRIO) featuring a real-time operating system and an FPGA. In this paper, we present an overview of the current status of the TCS. We especially focus on three items: the pointing computation implemented in the FPGA of the cRIO —using CORDIC algorithms— since it enables an optimisation of the hardware resources; data flow management based on OPCUA with its specific implementation on the cRIO; and the use of an EtherCAT field-bus for its ability to provide real-time data exchanges with the sensors and actuators distributed throughout the telescope.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

Science.gov (United States)

2011-12-01

Decimation in Frequency DIT Decimation in Time DSP Digital Signal Processing DTFT Discrete Time Fourier Transform EDIF Electronic Data Interchange...standard electronic data interchange format ( EDIF ), compilation directly to bitstream for direct implementation on an FPGA, and hardware cosimulation

The design of RFID convey or belt gate systems using an antenna control unit.

Science.gov (United States)

Park, Chong Ryol; Lee, Seung Joon; Eom, Ki Hwan

2011-01-01

This paper proposes an efficient management system utilizing a Radio Frequency Identification (RFID) antenna control unit which is moving along with the path of boxes of materials on the conveyor belt by manipulating a motor. The proposed antenna control unit, which is driven by a motor and is located on top of the gate, has an array structure of two antennas with parallel connection. The array structure helps improve the directivity of antenna beam pattern and the readable RFID distance due to its configuration. In the experiments, as the control unit follows moving materials, the reading time has been improved by almost three-fold compared to an RFID system employing conventional fixed antennas. The proposed system also has a recognition rate of over 99% without additional antennas for detecting the sides of a box of materials. The recognition rate meets the conditions recommended by the Electronic Product Code glbal network (EPC)global for commercializing the system, with three antennas at a 20 dBm power of reader and a conveyor belt speed of 3.17 m/s. This will enable a host of new RFID conveyor belt gate systems with increased performance.

The Design of RFID Conveyor Belt Gate Systems Using an Antenna Control Unit

Directory of Open Access Journals (Sweden)

Ki Hwan Eom

2011-09-01

Full Text Available This paper proposes an efficient management system utilizing a Radio Frequency Identification (RFID antenna control unit which is moving along with the path of boxes of materials on the conveyor belt by manipulating a motor. The proposed antenna control unit, which is driven by a motor and is located on top of the gate, has an array structure of two antennas with parallel connection. The array structure helps improve the directivity of antenna beam pattern and the readable RFID distance due to its configuration. In the experiments, as the control unit follows moving materials, the reading time has been improved by almost three-fold compared to an RFID system employing conventional fixed antennas. The proposed system also has a recognition rate of over 99% without additional antennas for detecting the sides of a box of materials. The recognition rate meets the conditions recommended by the Electronic Product Code glbal network (EPCglobal for commercializing the system, with three antennas at a 20 dBm power of reader and a conveyor belt speed of 3.17 m/s. This will enable a host of new RFID conveyor belt gate systems with increased performance.

Embedded SoPC Design with Nios II Processor and Verilog Examples

CERN Document Server

Chu, Pong P

2012-01-01

Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction

CERN Document Server

Scherl, Holger

2011-01-01

Holger Scherl introduces the reader to the reconstruction problem in computed tomography and its major scientific challenges that range from computational efficiency to the fulfillment of Tuy's sufficiency condition. The assessed hardware architectures include multi- and many-core systems, cell broadband engine architecture, graphics processing units, and field programmable gate arrays.

System-on-chip implementation of embedded real-time simulator for modular multilevel converters

DEFF Research Database (Denmark)

Ricco, Mattia; Gheorghe, Marius-Radu; Máthé, Lászlo

2017-01-01

. For these reasons, a Xilinx Zynq SoC platform is adopted; this device provides two hard-processors along with the programmable gate array. In this work, the MMC plant model and the MMC controller are implemented in the two available microcontrollers, whereas, all the modulators and interfaces can be implemented...

Assessing psychosocial correlates of parental safety behaviour using Protection Motivation Theory: stair gate presence and use among parents of toddlers.

Science.gov (United States)

Beirens, T M J; Brug, J; van Beeck, E F; Dekker, R; den Hertog, P; Raat, H

2008-08-01

Unintentional injury due to falls is one of the main reasons for hospitalization among children 0-4 years of age. The goal of this study was to assess the psychosocial correlates of parental safety behaviours to prevent falls from a staircase due to the lack of or the lack of adequate use of a stair gate. Data were collected from a cross-sectional survey using self-administered questionnaires mailed to a population sample of 2470 parents with toddlers. Associations between self-reported habits on the presence and use of stair gates and family and psychosocial factors were analysed, using descriptive statistics and multiple regression models, based on Protection Motivation Theory. The presence of stair gates was associated with family situation, perceived vulnerability, response efficacy, social norms and descriptive norms. The use of stair gates was associated with family situation, response efficacy, self-efficacy and perceived advantages of safe behaviour. The full model explained 32 and 24% of the variance in the presence of stair gates and the use of stair gates, respectively, indicating a large and medium effect size. Programmes promoting the presence and adequate use of stair gates should address the family situation, personal cognitive factors as well as social factors.

Field Emitter Arrays for a Free Electron Laser Application

CERN Document Server

Shing-Bruce-Li, Kevin; Ganter, Romain; Gobrecht, Jens; Raguin, Jean Yves; Rivkin, Leonid; Wrulich, Albin F

2004-01-01

The development of a new electron gun with the lowest possible emittance would help reducing the total length and cost of a free electron laser. Field emitter arrays (FEAs) are an attractive technology for electron sources of ultra high brightness. Indeed, several thousands of microscopic tips can be deposited on a 1 mm diameter area. Electrons are then extracted by applying voltage to a first grid layer close to the tip apexes, the so called gate layer, and focused by a second grid layer one micrometer above the tips. The typical aperture diameter of the gate and the focusing layer is in the range of one micrometer. One challenge for such cathodes is to produce peak currents in the ampere range since the usual applications of FEAs require less than milliampere. Encouraging peak current performances have been obtained by applying voltage pulses at low frequency between gate and tips. In this paper we report on different tip materials available on the market: diamond FEAs from Extreme Devices Inc., ZrC single ...

Gate current for p+-poly PMOS devices under gate injection conditions

NARCIS (Netherlands)

Hof, A.J.; Holleman, J.; Woerlee, P.H.

2001-01-01

In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the

T-gate aligned nanotube radio frequency transistors and circuits with superior performance.

Science.gov (United States)

Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu

2013-05-28

In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.

Prospects for quantum computing with an array of ultracold polar paramagnetic molecules.

Science.gov (United States)

Karra, Mallikarjun; Sharma, Ketan; Friedrich, Bretislav; Kais, Sabre; Herschbach, Dudley

2016-03-07

Arrays of trapped ultracold molecules represent a promising platform for implementing a universal quantum computer. DeMille [Phys. Rev. Lett. 88, 067901 (2002)] has detailed a prototype design based on Stark states of polar (1)Σ molecules as qubits. Herein, we consider an array of polar (2)Σ molecules which are, in addition, inherently paramagnetic and whose Hund's case (b) free-rotor pair-eigenstates are Bell states. We show that by subjecting the array to combinations of concurrent homogeneous and inhomogeneous electric and magnetic fields, the entanglement of the array's Stark and Zeeman states can be tuned and the qubit sites addressed. Two schemes for implementing an optically controlled CNOT gate are proposed and their feasibility discussed in the face of the broadening of spectral lines due to dipole-dipole coupling and the inhomogeneity of the electric and magnetic fields.

Multiple Independent Gate FETs: How Many Gates Do We Need?

OpenAIRE

Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

2015-01-01

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

Full-frame, programmable hyperspectral imager

Science.gov (United States)

Love, Steven P.; Graff, David L.

2017-07-25

A programmable, many-band spectral imager based on addressable spatial light modulators (ASLMs), such as micro-mirror-, micro-shutter- or liquid-crystal arrays, is described. Capable of collecting at once, without scanning, a complete two-dimensional spatial image with ASLM spectral processing applied simultaneously to the entire image, the invention employs optical assemblies wherein light from all image points is forced to impinge at the same angle onto the dispersing element, eliminating interplay between spatial position and wavelength. This is achieved, as examples, using telecentric optics to image light at the required constant angle, or with micro-optical array structures, such as micro-lens- or capillary arrays, that aim the light on a pixel-by-pixel basis. Light of a given wavelength then emerges from the disperser at the same angle for all image points, is collected at a unique location for simultaneous manipulation by the ASLM, then recombined with other wavelengths to form a final spectrally-processed image.

Neuron array with plastic synapses and programmable dendrites.

Science.gov (United States)

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Getting more out of biomedical documents with GATE's full lifecycle open source text analytics.

Science.gov (United States)

Cunningham, Hamish; Tablan, Valentin; Roberts, Angus; Bontcheva, Kalina

2013-01-01

This software article describes the GATE family of open source text analysis tools and processes. GATE is one of the most widely used systems of its type with yearly download rates of tens of thousands and many active users in both academic and industrial contexts. In this paper we report three examples of GATE-based systems operating in the life sciences and in medicine. First, in genome-wide association studies which have contributed to discovery of a head and neck cancer mutation association. Second, medical records analysis which has significantly increased the statistical power of treatment/outcome models in the UK's largest psychiatric patient cohort. Third, richer constructs in drug-related searching. We also explore the ways in which the GATE family supports the various stages of the lifecycle present in our examples. We conclude that the deployment of text mining for document abstraction or rich search and navigation is best thought of as a process, and that with the right computational tools and data collection strategies this process can be made defined and repeatable. The GATE research programme is now 20 years old and has grown from its roots as a specialist development tool for text processing to become a rather comprehensive ecosystem, bringing together software developers, language engineers and research staff from diverse fields. GATE now has a strong claim to cover a uniquely wide range of the lifecycle of text analysis systems. It forms a focal point for the integration and reuse of advances that have been made by many people (the majority outside of the authors' own group) who work in text processing for biomedicine and other areas. GATE is available online under GNU open source licences and runs on all major operating systems. Support is available from an active user and developer community and also on a commercial basis.

Getting more out of biomedical documents with GATE's full lifecycle open source text analytics.

Directory of Open Access Journals (Sweden)

Hamish Cunningham

Full Text Available This software article describes the GATE family of open source text analysis tools and processes. GATE is one of the most widely used systems of its type with yearly download rates of tens of thousands and many active users in both academic and industrial contexts. In this paper we report three examples of GATE-based systems operating in the life sciences and in medicine. First, in genome-wide association studies which have contributed to discovery of a head and neck cancer mutation association. Second, medical records analysis which has significantly increased the statistical power of treatment/outcome models in the UK's largest psychiatric patient cohort. Third, richer constructs in drug-related searching. We also explore the ways in which the GATE family supports the various stages of the lifecycle present in our examples. We conclude that the deployment of text mining for document abstraction or rich search and navigation is best thought of as a process, and that with the right computational tools and data collection strategies this process can be made defined and repeatable. The GATE research programme is now 20 years old and has grown from its roots as a specialist development tool for text processing to become a rather comprehensive ecosystem, bringing together software developers, language engineers and research staff from diverse fields. GATE now has a strong claim to cover a uniquely wide range of the lifecycle of text analysis systems. It forms a focal point for the integration and reuse of advances that have been made by many people (the majority outside of the authors' own group who work in text processing for biomedicine and other areas. GATE is available online under GNU open source licences and runs on all major operating systems. Support is available from an active user and developer community and also on a commercial basis.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

Science.gov (United States)

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

Energy Technology Data Exchange (ETDEWEB)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); Cao, Xiaolong [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590 (China); Dai, Haitao [Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology, School of Science, Tianjin University, Tianjin 300072 (China); Yang, Junbo [Center of Material Science, National University of Defense Technology, Changsha 410073 (China)

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

Science.gov (United States)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

Science.gov (United States)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

The Bill and Melinda Gates Foundation: pushing the boundaries of what is possible in public health - perspectives and challenges to the global community

CERN Multimedia

CERN. Geneva

2008-01-01

Introduction: In July 2008, Bill Gates will transition out of a day-to-day role at Microsoft, to spend more time on his philanthropic work with the Bill and Melinda Gates Foundation. As the world’s largest philanthropic organization, the Gates Foundation has set ambitious goals to tackle some of the world’s worst diseases. In this talk, Julie Jacobson will outline some of the objectives of the Gates Foundation and how it is impacting public health and challenging the global community. Speaker Bio: As Senior Programme Officer at the Bill and Melinda Gates Foundation, Julie Jacobson currently supports grants working toward the control of neglected tropical diseases and works with the development and implementation of new vaccines in the infectious disease group of Global Health. Previously Dr. Jacobson was Scientific Director of Immunization Solutions and Director of Japanese encephalitis (JE) project at PATH, an international non-profit organization. As director of the JE project, she managed a US$35 ...

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack

Directory of Open Access Journals (Sweden)

Shi-Bing Qian

2015-12-01

Full Text Available Amorphous indium-gallium-zinc oxide (a-IGZO thin-film transistor (TFT memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack under a maximal processing temperature of 300 oC. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 103 P/E cycles, and a memory window of 1.1 V was retained after 105 s retention time.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

Science.gov (United States)

Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

2015-09-01

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Dynamic array of dark optical traps

DEFF Research Database (Denmark)

Daria, V.R.; Rodrigo, P.J.; Glückstad, J.

2004-01-01

A dynamic array of dark optical traps is generated for simultaneous trapping and arbitrary manipulation of multiple low-index microstructures. The dynamic intensity patterns forming the dark optical trap arrays are generated using a nearly loss-less phase-to-intensity conversion of a phase......-encoded coherent light source. Two-dimensional input phase distributions corresponding to the trapping patterns are encoded using a computer-programmable spatial light modulator, enabling each trap to be shaped and moved arbitrarily within the plane of observation. We demonstrate the generation of multiple dark...... optical traps for simultaneous manipulation of hollow "air-filled" glass microspheres suspended in an aqueous medium. (C) 2004 American Institute of Physics....

Coulomb blockade threshold in finite one-dimensional arrays of small tunnel junctions

International Nuclear Information System (INIS)

Lien, Nguyen V.; Dat, Nguyen T.; Nam, Nguyen H.

2001-11-01

The current-voltage characteristics of one-dimensional tunnel junction arrays are simulated using the semiclassical and full capacitance matrix description. The threshold voltage V th of the Coulomb blockade (CB) is evaluated and analyzed in detail as a function of the gate capacitance C 0 , the array length N, the temperature, and the degree of disorder. The disordered effect is found to be essential, while the long range interaction included in the full capacitance matrix calculations, when decreasing V th , weakly affects the qualitative behaviour of the CB for the V th (C 0 ) - and the V th (N)-dependences. (author)

Design of Circularly-Polarised, Crossed Drooping Dipole, Phased Array Antenna Using Genetic Algorithm Optimisation

DEFF Research Database (Denmark)

Larsen, Niels Vesterdal

2007-01-01

A printed drooping dipole array is designed and constructed. The design is based on a genetic algorithm optimisation procedure used in conjunction with the software programme AWAS. By optimising the array G/T for specific combinations of scan angles and frequencies an optimum design is obtained...

Respiratory gating in positron emission tomography: A quantitative comparison of different gating schemes

International Nuclear Information System (INIS)

Dawood, Mohammad; Buether, Florian; Lang, Norbert; Schober, Otmar; Schaefers, Klaus P

2007-01-01

Respiratory gating is used for reducing the effects of breathing motion in a wide range of applications from radiotherapy treatment to diagnostical imaging. Different methods are feasible for respiratory gating. In this study seven gating methods were developed and tested on positron emission tomography (PET) listmode data. The results of seven patient studies were compared quantitatively with respect to motion and noise. (1) Equal and (2) variable time-based gating methods use only the time information of the breathing cycle to define respiratory gates. (3) Equal and (4) variable amplitude-based gating approaches utilize the amplitude of the respiratory signal. (5) Cycle-based amplitude gating is a combination of time and amplitude-based techniques. A baseline correction was applied to methods (3) and (4) resulting in two new approaches: Baseline corrected (6) equal and (7) variable amplitude-based gating. Listmode PET data from seven patients were acquired together with a respiratory signal. Images were reconstructed applying the seven gating methods. Two parameters were used to quantify the results: Motion was measured as the displacement of the heart due to respiration and noise was defined as the standard deviation of pixel intensities in a background region. The amplitude-based approaches (3) and (4) were superior to the time-based methods (1) and (2). The improvement in capturing the motion was more than 30% (up to 130%) in all subjects. The variable time (2) and amplitude (4) methods had a more uniform noise distribution among all respiratory gates compared to equal time (1) and amplitude (3) methods. Baseline correction did not improve the results. Out of seven different respiratory gating approaches, the variable amplitude method (4) captures the respiratory motion best while keeping a constant noise level among all respiratory phases

A gate drive circuit for gate-turn-off (GTO) devices in series stack

International Nuclear Information System (INIS)

Despe, O.

1999-01-01

A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

Science.gov (United States)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Efficient Implementation of Nested-Loop Multimedia Algorithms

Directory of Open Access Journals (Sweden)

Kittitornkun Surin

2001-01-01

Full Text Available A novel dependence graph representation called the multiple-order dependence graph for nested-loop formulated multimedia signal processing algorithms is proposed. It allows a concise representation of an entire family of dependence graphs. This powerful representation facilitates the development of innovative implementation approach for nested-loop formulated multimedia algorithms such as motion estimation, matrix-matrix product, 2D linear transform, and others. In particular, algebraic linear mapping (assignment and scheduling methodology can be applied to implement such algorithms on an array of simple-processing elements. The feasibility of this new approach is demonstrated in three major target architectures: application-specific integrated circuit (ASIC, field programmable gate array (FPGA, and a programmable clustered VLIW processor.

A high-speed bioelectrical impedance spectroscopy system based on the digital auto-balancing bridge method

International Nuclear Information System (INIS)

Li, Nan; Xu, Hui; Zhou, Zhou; Wang, Wei; Qiao, Guofeng; Li, David D-U

2013-01-01

A novel bioelectrical impedance spectroscopy system based on the digital auto-balancing bridge method improved from the conventional analogue auto-balancing method is presented for bioelectrical impedance measurements. The hardware of the proposed system consists of a reference source, a null detector, a variable source, a field programmable gate array, a clock generator, a flash and a USB controller. Software implemented in the field programmable gate array includes three major blocks: clock management, peripheral control and digital signal processing. The principle and realization of the least-mean-squares-based digital auto-balancing algorithm is introduced in detail. The performances of our system were examined by comparing with a commercial impedance analyzer. The results reveal that the proposed system has high speed (less than 3.5 ms per measurement) and high accuracy in the frequency range of 1 kHz–10 MHz. Compared with the commercial instrument based on the traditional analogue auto-balancing method, our system shows advantages in measurement speed, compactness and flexibility, making it suitable for various bioelectrical impedance measurement applications. (paper)

High-performance computing for airborne applications

International Nuclear Information System (INIS)

Quinn, Heather M.; Manuzatto, Andrea; Fairbanks, Tom; Dallmann, Nicholas; Desgeorges, Rose

2010-01-01

Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even though the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.

A high performance cost-effective digital complex correlator for an X-band polarimetry survey.

Science.gov (United States)

Bergano, Miguel; Rocha, Armando; Cupido, Luís; Barbosa, Domingos; Villela, Thyrso; Boas, José Vilas; Rocha, Graça; Smoot, George F

2016-01-01

The detailed knowledge of the Milky Way radio emission is important to characterize galactic foregrounds masking extragalactic and cosmological signals. The update of the global sky models describing radio emissions over a very large spectral band requires high sensitivity experiments capable of observing large sky areas with long integration times. Here, we present the design of a new 10 GHz (X-band) polarimeter digital back-end to map the polarization components of the galactic synchrotron radiation field of the Northern Hemisphere sky. The design follows the digital processing trends in radio astronomy and implements a large bandwidth (1 GHz) digital complex cross-correlator to extract the Stokes parameters of the incoming synchrotron radiation field. The hardware constraints cover the implemented VLSI hardware description language code and the preliminary results. The implementation is based on the simultaneous digitized acquisition of the Cartesian components of the two linear receiver polarization channels. The design strategy involves a double data rate acquisition of the ADC interleaved parallel bus, and field programmable gate array device programming at the register transfer mode. The digital core of the back-end is capable of processing 32 Gbps and is built around an Altera field programmable gate array clocked at 250 MHz, 1 GSps analog to digital converters and a clock generator. The control of the field programmable gate array internal signal delays and a convenient use of its phase locked loops provide the timing requirements to achieve the target bandwidths and sensitivity. This solution is convenient for radio astronomy experiments requiring large bandwidth, high functionality, high volume availability and low cost. Of particular interest, this correlator was developed for the Galactic Emission Mapping project and is suitable for large sky area polarization continuum surveys. The solutions may also be adapted to be used at signal processing

Experimental study on gamma irradiation effects of floating gate ROMs The ROM is stated for Read-only Memory

CERN Document Server

He Chao Hui; Chen Xiao Hua; Wang Yan Ping; Peng Hong Lun

2002-01-01

Experimental results of gamma irradiation effects are given for Floating gate ROMs. There is an accumulated dose threshold. Errors occur when accumulated dose is above the threshold, no error occurs when below the threshold. The errors go up with the increase of the accumulated dose. Errors occur in devices that are measured during irradiation and irradiated in power on, moreover, new data cannot be written in these devices with programmer. However, under more accumulated dose, there is no error in devices in power off mode and new data can be written in these devices with programmer

Design and implementation of the NaI(Tl)/CsI(Na) detectors output signal generator

Science.gov (United States)

Zhou, Xu; Liu, Cong-Zhan; Zhao, Jian-Ling; Zhang, Fei; Zhang, Yi-Fei; Li, Zheng-Wei; Zhang, Shuo; Li, Xu-Fang; Lu, Xue-Feng; Xu, Zhen-Ling; Lu, Fang-Jun

2014-02-01

We designed and implemented a signal generator that can simulate the output of the NaI(Tl)/CsI(Na) detectors' pre-amplifier onboard the Hard X-ray Modulation Telescope (HXMT). Using the development of the FPGA (Field Programmable Gate Array) with VHDL language and adding a random constituent, we have finally produced the double exponential random pulse signal generator. The statistical distribution of the signal amplitude is programmable. The occurrence time intervals of the adjacent signals contain negative exponential distribution statistically.

Microlens array processor with programmable weight mask and direct optical input

Science.gov (United States)

Schmid, Volker R.; Lueder, Ernst H.; Bader, Gerhard; Maier, Gert; Siegordner, Jochen

1999-03-01

We present an optical feature extraction system with a microlens array processor. The system is suitable for online implementation of a variety of transforms such as the Walsh transform and DCT. Operating with incoherent light, our processor accepts direct optical input. Employing a sandwich- like architecture, we obtain a very compact design of the optical system. The key elements of the microlens array processor are a square array of 15 X 15 spherical microlenses on acrylic substrate and a spatial light modulator as transmissive mask. The light distribution behind the mask is imaged onto the pixels of a customized a-Si image sensor with adjustable gain. We obtain one output sample for each microlens image and its corresponding weight mask area as summation of the transmitted intensity within one sensor pixel. The resulting architecture is very compact and robust like a conventional camera lens while incorporating a high degree of parallelism. We successfully demonstrate a Walsh transform into the spatial frequency domain as well as the implementation of a discrete cosine transform with digitized gray values. We provide results showing the transformation performance for both synthetic image patterns and images of natural texture samples. The extracted frequency features are suitable for neural classification of the input image. Other transforms and correlations can be implemented in real-time allowing adaptive optical signal processing.

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

Directory of Open Access Journals (Sweden)

Jong-Ryul Yang

2016-03-01

Full Text Available A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Study on Oscillations during Short Circuit of MW-Scale IGBT Power Modules by Means of a 6-kA/1.1-kV Nondestructive Testing System

DEFF Research Database (Denmark)

Wu, Rui; Diaz Reigosa, Paula; Iannuzzo, Francesco

2015-01-01

This paper uses a 6-kA/1.1-kV nondestructive testing system for the analysis of the short-circuit behavior of insulated-gate bipolar transistor (IGBT) power modules. A field-programmable gate array enables the definition of control signals to an accuracy of 10 ns. Multiple 1.7-kV/1-kA IGBT power...... modules displayed severe divergent oscillations, which were subsequently characterized. Experimental tests indicate that nonnegligible circuit stray inductance plays an important role in the divergent oscillations. In addition, the temperature dependence of the transconductance is proposed as an important...

Memory, microprocessor, and ASIC

CERN Document Server

Chen, Wai-Kai

2003-01-01

System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

Simple method for assembly of CRISPR synergistic activation mediator gRNA expression array.

Science.gov (United States)

Vad-Nielsen, Johan; Nielsen, Anders Lade; Luo, Yonglun

2018-05-20

When studying complex interconnected regulatory networks, effective methods for simultaneously manipulating multiple genes expression are paramount. Previously, we have developed a simple method for generation of an all-in-one CRISPR gRNA expression array. We here present a Golden Gate Assembly-based system of synergistic activation mediator (SAM) compatible CRISPR/dCas9 gRNA expression array for the simultaneous activation of multiple genes. Using this system, we demonstrated the simultaneous activation of the transcription factors, TWIST, SNAIL, SLUG, and ZEB1 a human breast cancer cell line. Copyright © 2018 Elsevier B.V. All rights reserved.

Expert Oracle GoldenGate

CERN Document Server

Prusinski, Ben; Chung, Richard

2011-01-01

Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica

MO-F-CAMPUS-J-02: Commissioning of Radiofrequency Tracking for Gated SBRT of the Liver Using Novel Motion System

International Nuclear Information System (INIS)

James, J; Cetnar, A; Nguyen, V; Wang, B

2015-01-01

Purpose: Tracking soft tissue targets has recently been approved as a new application of the Calypso radiofrequency tracking system allowing for gated treatment of the liver based on the motion of the target volume itself. As part of the commissioning process, an end-to-end test was performed using a 3D diode array and 6D motion platform to verify the dosimetric accuracy and establish the workflow of gated SBRT treatment of the liver using Calypso. Methods: A 4DCT scan of the ScandiDos Delta4 phantom was acquired using the HexaMotion motion platform to simulate realistic breathing motion. A VMAT plan was optimized on the end of inspiration phase of the 4DCT scan and delivered to the Delta4 phantom using the Varian TrueBeam. The treatment beam was gated by Calypso to deliver dose at the end of inspiration. The expected dose was compared to the delivered dose using gamma analysis. In addition, gating limits were investigated to determine how large the gating range can be while still maintaining dosimetric accuracy. Results: The 3%/3mm and 2%/2mm gamma pass rate for the gated treatment delivery was 100% and 98.4%, respectively. When increasing the gating limits beyond the known extent of planned motion from the 4DCT, the gamma pass rates decreased as expected. The 3%/3mm gamma pass rate for a 1, 2, and 3mm increase in gating limits were measured to be 96.0%, 92.7%, and 78.8%, respectively. Conclusion: Radiofrequency tracking was shown to be an effective way to provide gated SBRT treatment of the liver. Baseline gating limits should be determined by measuring the extent of target motion during the respiratory phases used for planning. We recommend adding 1mm to the baseline limits to provide the proper balance between treatment efficiency and dosimetric accuracy

Dynamic monitoring of transmembrane potential changes: a study of ion channels using an electrical double layer-gated FET biosensor.

Science.gov (United States)

Pulikkathodi, Anil Kumar; Sarangadharan, Indu; Chen, Yi-Hong; Lee, Geng-Yen; Chyi, Jen-Inn; Lee, Gwo-Bin; Wang, Yu-Lin

2018-03-27

In this research, we have designed, fabricated and characterized an electrical double layer (EDL)-gated AlGaN/GaN high electron mobility transistor (HEMT) biosensor array to study the transmembrane potential changes of cells. The sensor array platform is designed to detect and count circulating tumor cells (CTCs) of colorectal cancer (CRC) and investigate cellular bioelectric signals. Using the EDL FET biosensor platform, cellular responses can be studied in physiological salt concentrations, thereby eliminating complex automation. Upon investigation, we discovered that our sensor response follows the transmembrane potential changes of captured cells. Our whole cell sensor platform can be used to monitor the dynamic changes in the membrane potential of cells. The effects of continuously changing electrolyte ion concentrations and ion channel blocking using cadmium are investigated. This methodology has the potential to be used as an electrophysiological probe for studying ion channel gating and the interaction of biomolecules in cells. The sensor can also be a point-of-care diagnostic tool for rapid screening of diseases.

Design and implementation of the NaI(Tl)/CsI(Na) detectors output signal generator

International Nuclear Information System (INIS)

Zhou Xu; Liu Congzhan; Zhao Jianling

2014-01-01

We designed and implemented a signal generator that can simulate the output of the NaI(Tl)/CsI(Na) detectors' pre-amplifier onboard the Hard X-ray Modulation Telescope (HXMT). Using the development of the FPGA (Field Programmable Gate Array) with VHDL language and adding a random constituent, we have finally produced the double exponential random pulse signal generator. The statistical distribution of the signal amplitude is programmable. The occurrence time intervals of the adjacent signals contain negative exponential distribution statistically. (authors)

A Compute Environment of ABC95 Array Computer Based on Multi-FPGA Chip

Institute of Scientific and Technical Information of China (English)

无

2000-01-01

ABC95 array computer is a multi-function network's computer based on FPGA technology, The multi-function network supports processors conflict-free access data from memory and supports processors access data from processors based on enhanced MESH network.ABC95 instruction's system includes control instructions, scalar instructions, vectors instructions.Mostly net-work instructions are introduced.A programming environment of ABC95 array computer assemble language is designed.A programming environment of ABC95 array computer for VC++ is advanced.It includes load function of ABC95 array computer program and data, store function, run function and so on.Specially, The data type of ABC95 array computer conflict-free access is defined.The results show that these technologies can develop programmer of ABC95 array computer effectively.

GATE V6: a major enhancement of the GATE simulation platform enabling modelling of CT and radiotherapy

Energy Technology Data Exchange (ETDEWEB)

Jan, S; Becheva, E [DSV/I2BM/SHFJ, Commissariat a l' Energie Atomique, Orsay (France); Benoit, D; Rehfeld, N; Stute, S; Buvat, I [IMNC-UMR 8165 CNRS-Paris 7 and Paris 11 Universities, 15 rue Georges Clemenceau, 91406 Orsay Cedex (France); Carlier, T [INSERM U892-Cancer Research Center, University of Nantes, Nantes (France); Cassol, F; Morel, C [Centre de physique des particules de Marseille, CNRS-IN2P3 and Universite de la Mediterranee, Aix-Marseille II, 163, avenue de Luminy, 13288 Marseille Cedex 09 (France); Descourt, P; Visvikis, D [INSERM, U650, Laboratoire du Traitement de l' Information Medicale (LaTIM), CHU Morvan, Brest (France); Frisson, T; Grevillot, L; Guigues, L; Sarrut, D; Zahra, N [Universite de Lyon, CREATIS, CNRS UMR5220, Inserm U630, INSA-Lyon, Universite Lyon 1, Centre Leon Berard (France); Maigne, L; Perrot, Y [Laboratoire de Physique Corpusculaire, 24 Avenue des Landais, 63177 Aubiere Cedex (France); Schaart, D R [Delft University of Technology, Radiation Detection and Medical Imaging, Mekelweg 15, 2629 JB Delft (Netherlands); Pietrzyk, U, E-mail: buvat@imnc.in2p3.fr [Reseach Center Juelich, Institute of Neurosciences and Medicine and Department of Physics, University of Wuppertal (Germany)

2011-02-21

GATE (Geant4 Application for Emission Tomography) is a Monte Carlo simulation platform developed by the OpenGATE collaboration since 2001 and first publicly released in 2004. Dedicated to the modelling of planar scintigraphy, single photon emission computed tomography (SPECT) and positron emission tomography (PET) acquisitions, this platform is widely used to assist PET and SPECT research. A recent extension of this platform, released by the OpenGATE collaboration as GATE V6, now also enables modelling of x-ray computed tomography and radiation therapy experiments. This paper presents an overview of the main additions and improvements implemented in GATE since the publication of the initial GATE paper (Jan et al 2004 Phys. Med. Biol. 49 4543-61). This includes new models available in GATE to simulate optical and hadronic processes, novelties in modelling tracer, organ or detector motion, new options for speeding up GATE simulations, examples illustrating the use of GATE V6 in radiotherapy applications and CT simulations, and preliminary results regarding the validation of GATE V6 for radiation therapy applications. Upon completion of extensive validation studies, GATE is expected to become a valuable tool for simulations involving both radiotherapy and imaging.

A programmable CCD driver circuit for multiphase CCD operation

International Nuclear Information System (INIS)

Ewin, A.J.; Reed, K.V.

1989-01-01

A programmable CCD driver circuit was designed to drive CCD's in multiphased modes. The purpose of the drive electronics was to operate developmental CCD imaging arrays for NASA's Moderate Resolution Imaging Spectrometer - Tiltable (MODIS-T). Five prototype arrays were designed. Valid's Graphics Editor (GED) was used to design the driver. With this driver design, any of the five arrays can be readout. Designing the driver with GED allowed functional simulation, timing verification, and certain packaging analyses to be done on the design before fabrication. The driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400 Kpixels/sec. Timing and packaging parameters were verified. the design uses 54 TTL component chips

Development of a prototype PET scanner with depth-of-interaction measurement using solid-state photomultiplier arrays and parallel readout electronics.

Science.gov (United States)

Shao, Yiping; Sun, Xishan; Lan, Kejian A; Bircher, Chad; Lou, Kai; Deng, Zhi

2014-03-07

In this study, we developed a prototype animal PET by applying several novel technologies to use solid-state photomultiplier (SSPM) arrays to measure the depth of interaction (DOI) and improve imaging performance. Each PET detector has an 8 × 8 array of about 1.9 × 1.9 × 30.0 mm(3) lutetium-yttrium-oxyorthosilicate scintillators, with each end optically connected to an SSPM array (16 channels in a 4 × 4 matrix) through a light guide to enable continuous DOI measurement. Each SSPM has an active area of about 3 × 3 mm(2), and its output is read by a custom-developed application-specific integrated circuit to directly convert analogue signals to digital timing pulses that encode the interaction information. These pulses are transferred to and are decoded by a field-programmable gate array-based time-to-digital convertor for coincident event selection and data acquisition. The independent readout of each SSPM and the parallel signal process can significantly improve the signal-to-noise ratio and enable the use of flexible algorithms for different data processes. The prototype PET consists of two rotating detector panels on a portable gantry with four detectors in each panel to provide 16 mm axial and variable transaxial field-of-view (FOV) sizes. List-mode ordered subset expectation maximization image reconstruction was implemented. The measured mean energy, coincidence timing and DOI resolution for a crystal were about 17.6%, 2.8 ns and 5.6 mm, respectively. The measured transaxial resolutions at the center of the FOV were 2.0 mm and 2.3 mm for images reconstructed with and without DOI, respectively. In addition, the resolutions across the FOV with DOI were substantially better than those without DOI. The quality of PET images of both a hot-rod phantom and mouse acquired with DOI was much higher than that of images obtained without DOI. This study demonstrates that SSPM arrays and advanced readout/processing electronics can be used to develop a practical DOI

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

International Nuclear Information System (INIS)

Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.

2016-01-01

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p"+-p-p"+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10"5. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.

Coupled quantum electrodynamics in photonic crystal cavities towards controlled phase gate operations

International Nuclear Information System (INIS)

Xiao, Y-F; Gao, J; McMillan, J F; Yang, X; Wong, C W; Zou, X-B; Chen, Y-L; Han, Z-F; Guo, G-C

2008-01-01

In this paper, a scalable photonic crystal cavity array, in which single embedded quantum dots (QDs) are coherently interacting, is studied theoretically. Firstly, we examine the spectral character and optical delay brought about by the coupled cavities interacting with single QDs, in an optical analogue to electromagnetically induced transparency. Secondly, we then examine the usability of this coupled QD-cavity system for quantum phase gate operation and our numerical examples suggest that a two-qubit system with fidelity above 0.99 and photon loss below 0.04 is possible.

Philanthropy and the nation-state in global health: The Gates Foundation in India.

Science.gov (United States)

Mahajan, Manjari

2017-12-15

In recent years, philanthropic actors such as the Gates Foundation have been understood as commanding sweeping influence in global health. They have been associated with the outsourcing of public health services, shifting of policy priorities, and the eventual sidelining of national governments. This article makes a different argument about the impact of global philanthropic actors. It focuses on the work of the Gates Foundation in India over the last decade and a half, tracing how the foundation initially circumvented the national government but then moved on to a discourse of partnership. Ironically, after an early discounting of the role of the government, the foundation later sought to transition its programmes to the state. The foundation's evolving trajectory reflects its experiences on the ground and also the difficulties of realising its original ambitions. While the foundation's work in India is marked by ebbs and flows, the state's institutions remain constant. The article argues that there is not always a straightforward marginalisation of the government vis-à-vis global philanthropic actors. Actors such as the Gates Foundation, perceived as enormously powerful in global health institutions in Geneva and New York, may have a far more qualified impact in large developing countries such as India.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Measurement of time delays in gated radiotherapy for realistic respiratory motions

International Nuclear Information System (INIS)

Chugh, Brige P.; Quirk, Sarah; Conroy, Leigh; Smith, Wendy L.

2014-01-01

Purpose: Gated radiotherapy is used to reduce internal motion margins, escalate target dose, and limit normal tissue dose; however, its temporal accuracy is limited. Beam-on and beam-off time delays can lead to treatment inefficiencies and/or geographic misses; therefore, AAPM Task Group 142 recommends verifying the temporal accuracy of gating systems. Many groups use sinusoidal phantom motion for this, under the tacit assumption that use of sinusoidal motion for determining time delays produces negligible error. The authors test this assumption by measuring gating time delays for several realistic motion shapes with increasing degrees of irregularity. Methods: Time delays were measured on a linear accelerator with a real-time position management system (Varian TrueBeam with RPM system version 1.7.5) for seven motion shapes: regular sinusoidal; regular realistic-shape; large (40%) and small (10%) variations in amplitude; large (40%) variations in period; small (10%) variations in both amplitude and period; and baseline drift (30%). Film streaks of radiation exposure were generated for each motion shape using a programmable motion phantom. Beam-on and beam-off time delays were determined from the difference between the expected and observed streak length. Results: For the system investigated, all sine, regular realistic-shape, and slightly irregular amplitude variation motions had beam-off and beam-on time delays within the AAPM recommended limit of less than 100 ms. In phase-based gating, even small variations in period resulted in some time delays greater than 100 ms. Considerable time delays over 1 s were observed with highly irregular motion. Conclusions: Sinusoidal motion shapes can be considered a reasonable approximation to the more complex and slightly irregular shapes of realistic motion. When using phase-based gating with predictive filters even small variations in period can result in time delays over 100 ms. Clinical use of these systems for patients

Measurement of time delays in gated radiotherapy for realistic respiratory motions

Energy Technology Data Exchange (ETDEWEB)

Chugh, Brige P.; Quirk, Sarah; Conroy, Leigh; Smith, Wendy L., E-mail: Wendy.Smith@albertahealthservices.ca [Department of Medical Physics, Tom Baker Cancer Centre, Calgary, Alberta T2N 4N2 (Canada)

2014-09-15

Purpose: Gated radiotherapy is used to reduce internal motion margins, escalate target dose, and limit normal tissue dose; however, its temporal accuracy is limited. Beam-on and beam-off time delays can lead to treatment inefficiencies and/or geographic misses; therefore, AAPM Task Group 142 recommends verifying the temporal accuracy of gating systems. Many groups use sinusoidal phantom motion for this, under the tacit assumption that use of sinusoidal motion for determining time delays produces negligible error. The authors test this assumption by measuring gating time delays for several realistic motion shapes with increasing degrees of irregularity. Methods: Time delays were measured on a linear accelerator with a real-time position management system (Varian TrueBeam with RPM system version 1.7.5) for seven motion shapes: regular sinusoidal; regular realistic-shape; large (40%) and small (10%) variations in amplitude; large (40%) variations in period; small (10%) variations in both amplitude and period; and baseline drift (30%). Film streaks of radiation exposure were generated for each motion shape using a programmable motion phantom. Beam-on and beam-off time delays were determined from the difference between the expected and observed streak length. Results: For the system investigated, all sine, regular realistic-shape, and slightly irregular amplitude variation motions had beam-off and beam-on time delays within the AAPM recommended limit of less than 100 ms. In phase-based gating, even small variations in period resulted in some time delays greater than 100 ms. Considerable time delays over 1 s were observed with highly irregular motion. Conclusions: Sinusoidal motion shapes can be considered a reasonable approximation to the more complex and slightly irregular shapes of realistic motion. When using phase-based gating with predictive filters even small variations in period can result in time delays over 100 ms. Clinical use of these systems for patients

A modular and programmable development platform for capsule endoscopy system.

Science.gov (United States)

Khan, Tareq Hasan; Shrestha, Ravi; Wahid, Khan A

2014-06-01

The state-of-the-art capsule endoscopy (CE) technology offers painless examination for the patients and the ability to examine the interior of the gastrointestinal tract by a noninvasive procedure for the gastroenterologists. In this work, a modular and flexible CE development system platform consisting of a miniature field programmable gate array (FPGA) based electronic capsule, a microcontroller based portable data recorder unit and computer software is designed and developed. Due to the flexible and reprogrammable nature of the system, various image processing and compression algorithms can be tested in the design without requiring any hardware change. The designed capsule prototype supports various imaging modes including white light imaging (WLI) and narrow band imaging (NBI), and communicates with the data recorder in full duplex fashion, which enables configuring the image size and imaging mode in real time during examination. A low complexity image compressor based on a novel color-space is implemented inside the capsule to reduce the amount of RF transmission data. The data recorder contains graphical LCD for real time image viewing and SD cards for storing image data. Data can be uploaded to a computer or Smartphone by SD card, USB interface or by wireless Bluetooth link. Computer software is developed that decompresses and reconstructs images. The fabricated capsule PCBs have a diameter of 16 mm. An ex-vivo animal testing has also been conducted to validate the results.

A Secure and Reliable High-Performance Field Programmable Gate Array for Information Processing

Science.gov (United States)

2012-03-01

receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select an input port. The input...dual of a merge. It receives a data token from its control input (shown as a horizontal arrow above). The value of this data token is used to select...Transactions on Computer-Aided Design of Intergrated Circuits and Systems, Vol. 26, No. 2, February 2007. [12] Cadence Design Systems, “Clock Domain

CCD and IR array controllers

Science.gov (United States)

Leach, Robert W.; Low, Frank J.

2000-08-01

A family of controllers has bene developed that is powerful and flexible enough to operate a wide range of CCD and IR focal plane arrays in a variety of ground-based applications. These include fast readout of small CCD and IR arrays for adaptive optics applications, slow readout of large CCD and IR mosaics, and single CCD and IR array operation at low background/low noise regimes as well as high background/high speed regimes. The CCD and IR controllers have a common digital core based on user- programmable digital signal processors that are used to generate the array clocking and signal processing signals customized for each application. A fiber optic link passes image data and commands to VME or PCI interface boards resident in a host computer to the controller. CCD signal processing is done with a dual slope integrator operating at speeds of up to one Megapixel per second per channel. Signal processing of IR arrays is done either with a dual channel video processor or a four channel video processor that has built-in image memory and a coadder to 32-bit precision for operating high background arrays. Recent developments underway include the implementation of a fast fiber optic data link operating at a speed of 12.5 Megapixels per second for fast image transfer from the controller to the host computer, and supporting image acquisition software and device drivers for the PCI interface board for the Sun Solaris, Linux and Windows 2000 operating systems.

New opening hours of the gates

CERN Multimedia

GS Department

2009-01-01

Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

Single-flux-quantum logic circuits exploiting collision-based fusion gates

International Nuclear Information System (INIS)

Asai, T.; Yamada, K.; Amemiya, Y.

2008-01-01

We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock

Optical XOR gate

Science.gov (United States)

Vawter, G. Allen

2013-11-12

An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

Intrinsic respiratory gating in small-animal CT

International Nuclear Information System (INIS)

Bartling, Soenke H.; Dinkel, Julien; Kauczor, Hans-Ulrich; Stiller, Wolfram; Semmler, Wolfhard; Grasruck, Michael; Madisch, Ijad; Gupta, Rajiv; Kiessling, Fabian

2008-01-01

Gating in small-animal CT imaging can compensate artefacts caused by physiological motion during scanning. However, all published gating approaches for small animals rely on additional hardware to derive the gating signals. In contrast, in this study a novel method of intrinsic respiratory gating of rodents was developed and tested for mice (n=5), rats (n=5) and rabbits (n=2) in a flat-panel cone-beam CT system. In a consensus read image quality was compared with that of non-gated and retrospective extrinsically gated scans performed using a pneumatic cushion. In comparison to non-gated images, image quality improved significantly using intrinsic and extrinsic gating. Delineation of diaphragm and lung structure improved in all animals. Image quality of intrinsically gated CT was judged to be equivalent to extrinsically gated ones. Additionally 4D datasets were calculated using both gating methods. Values for expiratory, inspiratory and tidal lung volumes determined with the two gating methods were comparable and correlated well with values known from the literature. We could show that intrinsic respiratory gating in rodents makes additional gating hardware and preparatory efforts superfluous. This method improves image quality and allows derivation of functional data. Therefore it bears the potential to find wide applications in small-animal CT imaging. (orig.)

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Rad-Hard Structured ASIC Body of Knowledge

Science.gov (United States)

Heidecker, Jason

2013-01-01

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

Science.gov (United States)

Berg, Melanie; LaBel, Kenneth; Campola, Michael; Xapsos, Michael

2017-01-01

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

Final Report, Center for Programming Models for Scalable Parallel Computing: Co-Array Fortran, Grant Number DE-FC02-01ER25505

Energy Technology Data Exchange (ETDEWEB)

Robert W. Numrich

2008-04-22

The major accomplishment of this project is the production of CafLib, an 'object-oriented' parallel numerical library written in Co-Array Fortran. CafLib contains distributed objects such as block vectors and block matrices along with procedures, attached to each object, that perform basic linear algebra operations such as matrix multiplication, matrix transpose and LU decomposition. It also contains constructors and destructors for each object that hide the details of data decomposition from the programmer, and it contains collective operations that allow the programmer to calculate global reductions, such as global sums, global minima and global maxima, as well as vector and matrix norms of several kinds. CafLib is designed to be extensible in such a way that programmers can define distributed grid and field objects, based on vector and matrix objects from the library, for finite difference algorithms to solve partial differential equations. A very important extra benefit that resulted from the project is the inclusion of the co-array programming model in the next Fortran standard called Fortran 2008. It is the first parallel programming model ever included as a standard part of the language. Co-arrays will be a supported feature in all Fortran compilers, and the portability provided by standardization will encourage a large number of programmers to adopt it for new parallel application development. The combination of object-oriented programming in Fortran 2003 with co-arrays in Fortran 2008 provides a very powerful programming model for high-performance scientific computing. Additional benefits from the project, beyond the original goal, include a programto provide access to the co-array model through access to the Cray compiler as a resource for teaching and research. Several academics, for the first time, included the co-array model as a topic in their courses on parallel computing. A separate collaborative project with LANL and PNNL showed how to

Astroparticle physics: the new ASPERA-2 programme

CERN Multimedia

2009-01-01

On 7 July the ASPERA-2 programme funded by the European Commission was officially launched in Hamburg with the goal of creating a sustainable structure for the coordination of astroparticle physics in Europe. CERN, which is a participant in the programme, could play an important role in this respect. Artist’s impression of the CTA (Cherenkov Telescope Array). The CTA is one of the "Magnificent Seven", the seven large astroparticle physics infrastructures planned for the coming years. It is the next-generation facility destined to succeed the H.E.S.S. telescope in Namibia and the MAGIC telescope in the Canary Islands. (Credit ASPERA/G.Toma/A.Saftoiu). Following the success of ASPERA-1, the European network for astroparticle physics (see box), funding agency representatives gathered in Hamburg on 7 July 2009 for the official launch of ASPERA-2, a new three-year programme funded by the European Commission. Today the strategic roles of ...

Dynamic Adaptive Neural Network Arrays: A Neuromorphic Architecture

Energy Technology Data Exchange (ETDEWEB)

Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

2015-01-01

Dynamic Adaptive Neural Network Array (DANNA) is a neuromorphic hardware implementation. It differs from most other neuromorphic projects in that it allows for programmability of structure, and it is trained or designed using evolutionary optimization. This paper describes the DANNA structure, how DANNA is trained using evolutionary optimization, and an application of DANNA to a very simple classification task.

The cost of respiration-gated radiotherapy in the framework of a clinical research programme -STIC-

International Nuclear Information System (INIS)

Remonnay, R.; Morelle, M.; Carrere, M.O.; Giraud, P.

2009-01-01

Purpose. Our study aims to evaluate the impact of the implementation of respiratory gating (R.G.) on the production cost of radiotherapy, as compared to conformational radiotherapy without R.G. (comparator) in patients with lung or breast cancers. Issues surrounding reimbursement were also explored. Materials and methods: A prospective, multicenter, non-randomized study was conducted in the framework of a project entitled 'Support Program for Costly Diagnostic and Therapeutic Innovations'. Of the 20 hospitals involved in the clinical study, eight reference centers participated to the medico-economic study evaluating the costs of staff and equipment, as well as the costs of maintenance and consumables. Results: Three hundred and sixty-five patients were enrolled over two years in the economic study, corresponding to 197 radiotherapy treatments without R.G. and 168 with R.G.. Patients treated during the learning phase (n = 27) were excluded from the comparison with the control group. The use of R.G. in routine practice induced a cost increase of respectively 1256 and 996 Euros per treatment for lung and breast cancer patients treated with breath-hold techniques, versus 1807 and 1510 Euros for lung and breast cancer patients treated with synchronized gating techniques. Over costs were mainly due to extra working time of medical staff and medical technicians and to extra use of equipment during treatment sessions. Conclusion: The results of the full cost estimation suggested that medical reimbursements largely underestimate the costs related to innovation. (authors)

Signatures of Mechanosensitive Gating.

Science.gov (United States)

Morris, Richard G

2017-01-10

The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Quantum gate decomposition algorithms.

Energy Technology Data Exchange (ETDEWEB)

Slepoy, Alexander

2006-07-01

Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures

Directory of Open Access Journals (Sweden)

Evgeny Pikhay

2017-07-01

Full Text Available In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested.

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

International Nuclear Information System (INIS)

Miura, Atsushi; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi; Tsukamoto, Rikako; Yoshii, Shigeo

2008-01-01

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co 3 O 4 ) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented

Fully transparent conformal organic thin-film transistor array and its application as LED front driving.

Science.gov (United States)

Cui, Nan; Ren, Hang; Tang, Qingxin; Zhao, Xiaoli; Tong, Yanhong; Hu, Wenping; Liu, Yichun

2018-02-22

A fully transparent conformal organic thin-film field-effect transistor array is demonstrated based on a photolithography-compatible ultrathin metallic grid gate electrode and a solution-processed C 8 -BTBT film. The resulting organic field-effect transistor array exhibits a high optical transparency of >80% over the visible spectrum, mobility up to 2 cm 2 V -1 s -1 , on/off ratio of 10 5 -10 6 , switching current of >0.1 mA, and excellent light stability. The transparent conformal transistor array is demonstrated to adhere well to flat and curved LEDs as front driving. These results present promising applications of the solution-processed wide-bandgap organic semiconductor thin films in future large-scale transparent conformal active-matrix displays.

Nitrogen incorporated ultrananocrystalline diamond based field emitter array for a flat-panel x-ray source

International Nuclear Information System (INIS)

Posada, Chrystian M.; Grant, Edwin J.; Lee, Hyoung K.; Castaño, Carlos H.; Divan, Ralu; Sumant, Anirudha V.; Rosenmann, Daniel; Stan, Liliana

2014-01-01

A field emission based flat-panel transmission x-ray source is being developed as an alternative for medical and industrial imaging. A field emitter array (FEA) prototype based on nitrogen incorporated ultrananocrystalline diamond film has been fabricated to be used as the electron source of this flat panel x-ray source. The FEA prototype was developed using conventional microfabrication techniques. The field emission characteristics of the FEA prototype were evaluated. Results indicated that emission current densities of the order of 6 mA/cm 2 could be obtained at electric fields as low as 10 V/μm to 20 V/μm. During the prototype microfabrication process, issues such as delamination of the extraction gate and poor etching of the SiO 2 insulating layer located between the emitters and the extraction layer were encountered. Consequently, alternative FEA designs were investigated. Experimental and simulation data from the first FEA prototype were compared and the results were used to evaluate the performance of alternative single and double gate designs that would yield better field emission characteristics compared to the first FEA prototype. The best simulation results are obtained for the double gate FEA design, when the diameter of the collimator gate is around 2.6 times the diameter of the extraction gate

SU-F-T-514: Evaluation of the Accuracy of Free-Breathing and Deep Inspiration Breath-Hold Gated Beam Delivery Using An Elekta Linac

International Nuclear Information System (INIS)

Jermoumi, M; Cao, D; Housley, D; Shepard, D; Xie, R

2016-01-01

Purpose: In this study, we evaluated the performance of an Elekta linac in the delivery of gated radiotherapy. We examined whether the use of either a short gating window or a long beam hold impacts the accuracy of the delivery Methods: The performance of an Elekta linac in the delivery of gated radiotherapy was assessed using a 20cmX 20cm open field with the radiation delivered using a range of beam-on and beam-off time periods. Two SBRT plans were used to examine the accuracy of gated beam delivery for clinical treatment plans. For the SBRT cases, tests were performed for both free-breathing based gating and for gated delivery with a simulated breath-hold. A MatriXX 2D ion chamber array was used for data collection, and the gating accuracy was evaluated using gamma score. Results: For the 20cmX20cm open field, the gated beam delivery agreed closely with the non-gated delivery results. Discrepancies in the agreement, however, began to appear with a 5-to-1 ratio of the beam-off to beam-on. For these tight gating windows, each beam-on segment delivered a small number of monitor units. This finding was confirmed with dose distribution analysis from the delivery of the two VMAT plans where the gamma score(±1%,2%/1mm) showed passing rates in the range of 95% to 100% for gating windows of 25%, 38%, 50%, 63%, 75%, and 83%. Using a simulated sinusoidal breathing signal with a 4 second period, the gamma score of freebreathing gating and breath-hold gating deliveries were measured in the range of 95.7% to 100%. Conclusion: The results demonstrate that Elekta linacs can be used to accurately deliver respiratory gated treatments for both free-breathing and breath-hold patients. The accuracy of beams delivered in a gated delivery mode at low small MU proved higher than similar deliveries performed in a non-gated (manually interrupted) fashion.

SU-F-T-514: Evaluation of the Accuracy of Free-Breathing and Deep Inspiration Breath-Hold Gated Beam Delivery Using An Elekta Linac

Energy Technology Data Exchange (ETDEWEB)

Jermoumi, M; Cao, D; Housley, D; Shepard, D [Department of Radiation Oncology, Swedish Cancer Institute, Seattle, WA (United States); Xie, R [Ironwood Cancer and Research Centers, Chandler, AZ (United States)

2016-06-15

Purpose: In this study, we evaluated the performance of an Elekta linac in the delivery of gated radiotherapy. We examined whether the use of either a short gating window or a long beam hold impacts the accuracy of the delivery Methods: The performance of an Elekta linac in the delivery of gated radiotherapy was assessed using a 20cmX 20cm open field with the radiation delivered using a range of beam-on and beam-off time periods. Two SBRT plans were used to examine the accuracy of gated beam delivery for clinical treatment plans. For the SBRT cases, tests were performed for both free-breathing based gating and for gated delivery with a simulated breath-hold. A MatriXX 2D ion chamber array was used for data collection, and the gating accuracy was evaluated using gamma score. Results: For the 20cmX20cm open field, the gated beam delivery agreed closely with the non-gated delivery results. Discrepancies in the agreement, however, began to appear with a 5-to-1 ratio of the beam-off to beam-on. For these tight gating windows, each beam-on segment delivered a small number of monitor units. This finding was confirmed with dose distribution analysis from the delivery of the two VMAT plans where the gamma score(±1%,2%/1mm) showed passing rates in the range of 95% to 100% for gating windows of 25%, 38%, 50%, 63%, 75%, and 83%. Using a simulated sinusoidal breathing signal with a 4 second period, the gamma score of freebreathing gating and breath-hold gating deliveries were measured in the range of 95.7% to 100%. Conclusion: The results demonstrate that Elekta linacs can be used to accurately deliver respiratory gated treatments for both free-breathing and breath-hold patients. The accuracy of beams delivered in a gated delivery mode at low small MU proved higher than similar deliveries performed in a non-gated (manually interrupted) fashion.

Self-gated fat-suppressed cardiac cine MRI.

Science.gov (United States)

Ingle, R Reeve; Santos, Juan M; Overall, William R; McConnell, Michael V; Hu, Bob S; Nishimura, Dwight G

2015-05-01

To develop a self-gated alternating repetition time balanced steady-state free precession (ATR-SSFP) pulse sequence for fat-suppressed cardiac cine imaging. Cardiac gating is computed retrospectively using acquired magnetic resonance self-gating data, enabling cine imaging without the need for electrocardiogram (ECG) gating. Modification of the slice-select rephasing gradients of an ATR-SSFP sequence enables the acquisition of a one-dimensional self-gating readout during the unused short repetition time (TR). Self-gating readouts are acquired during every TR of segmented, breath-held cardiac scans. A template-matching algorithm is designed to compute cardiac trigger points from the self-gating signals, and these trigger points are used for retrospective cine reconstruction. The proposed approach is compared with ECG-gated ATR-SSFP and balanced steady-state free precession in 10 volunteers and five patients. The difference of ECG and self-gating trigger times has a variability of 13 ± 11 ms (mean ± SD). Qualitative reviewer scoring and ranking indicate no statistically significant differences (P > 0.05) between self-gated and ECG-gated ATR-SSFP images. Quantitative blood-myocardial border sharpness is not significantly different among self-gated ATR-SSFP ( 0.61±0.15 mm -1), ECG-gated ATR-SSFP ( 0.61±0.15 mm -1), or conventional ECG-gated balanced steady-state free precession cine MRI ( 0.59±0.15 mm -1). The proposed self-gated ATR-SSFP sequence enables fat-suppressed cardiac cine imaging at 1.5 T without the need for ECG gating and without decreasing the imaging efficiency of ATR-SSFP. © 2014 Wiley Periodicals, Inc.

Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

Energy Technology Data Exchange (ETDEWEB)

Zhang, X.; Wan, C.H., E-mail: wancaihua@iphy.ac.cn; Yuan, Z.H.; Fang, C.; Kong, W.J.; Wu, H.; Zhang, Q.T.; Tao, B.S.; Han, X.F., E-mail: xfhan@iphy.ac.cn

2017-04-15

Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices. - Highlights: • Experimental demonstration of spin logic cell based on spin Hall effect. • Five logic functions are realized in a single logic cell. • The logic cell is reprogrammable. • Information in the cell is symmetry-protected. • The logic cell can be easily expanded to logic gate array.

Autonomous Magnetic Microrobots by Navigating Gates for Multiple Biomolecules Delivery.

Science.gov (United States)

Hu, Xinghao; Lim, Byeonghwa; Torati, Sri Ramulu; Ding, Junjia; Novosad, Valentine; Im, Mi-Young; Reddy, Venu; Kim, Kunwoo; Jung, Eunjoo; Shawl, Asif Iqbal; Kim, Eunjoo; Kim, CheolGi

2018-05-08

The precise delivery of biofunctionalized matters is of great interest from the fundamental and applied viewpoints. In spite of significant progress achieved during the last decade, a parallel and automated isolation and manipulation of rare analyte, and their simultaneous on-chip separation and trapping, still remain challenging. Here, a universal micromagnet junction for self-navigating gates of microrobotic particles to deliver the biomolecules to specific sites using a remote magnetic field is described. In the proposed concept, the nonmagnetic gap between the lithographically defined donor and acceptor micromagnets creates a crucial energy barrier to restrict particle gating. It is shown that by carefully designing the geometry of the junctions, it becomes possible to deliver multiple protein-functionalized carriers in high resolution, as well as MCF-7 and THP-1 cells from the mixture, with high fidelity and trap them in individual apartments. Integration of such junctions with magnetophoretic circuitry elements could lead to novel platforms without retrieving for the synchronous digital manipulation of particles/biomolecules in microfluidic multiplex arrays for next-generation biochips. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

International Nuclear Information System (INIS)

Bloomfield, P.

1992-01-01

The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

Rapid wide-field Mueller matrix polarimetry imaging based on four photoelastic modulators with no moving parts.

Science.gov (United States)

Alali, Sanaz; Gribble, Adam; Vitkin, I Alex

2016-03-01

A new polarimetry method is demonstrated to image the entire Mueller matrix of a turbid sample using four photoelastic modulators (PEMs) and a charge coupled device (CCD) camera, with no moving parts. Accurate wide-field imaging is enabled with a field-programmable gate array (FPGA) optical gating technique and an evolutionary algorithm (EA) that optimizes imaging times. This technique accurately and rapidly measured the Mueller matrices of air, polarization elements, and turbid phantoms. The system should prove advantageous for Mueller matrix analysis of turbid samples (e.g., biological tissues) over large fields of view, in less than a second.

Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

Directory of Open Access Journals (Sweden)

Alisson C. D. de Souza

2014-09-01

Full Text Available This paper proposes a parallel fixed point radial basis function (RBF artificial neural network (ANN, implemented in a field programmable gate array (FPGA trained online with a least mean square (LMS algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx, with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

New methods for trigger electronics development

Energy Technology Data Exchange (ETDEWEB)

Cleland, W.E.; Stern, E.G. [Univ. of Pittsburgh, PA (United States)

1991-12-31

The large and complex nature of RHIC experiments and the tight time schedule for their construction requires that new techniques for designing the electronics should be employed. This is particularly true of the trigger and data acquisition electronics which has to be ready for turn-on of the experiment. We describe the use of the Workview package from VIEWlogic Inc. for design, simulation, and verification of a flash ADC readout system. We also show how field-programmable gate arrays such as the Xilinx 4000 might be employed to construct or prototype circuits with a large number of gates while preserving flexibility.

Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

International Nuclear Information System (INIS)

Datta, Deepanjan; Ganguly, Samiran; Dasgupta, S

2007-01-01

Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p + poly-n + poly-p + poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime

Visualization of neonatal coronary arteries on multidetector row CT: ECG-gated versus non-ECG-gated technique

International Nuclear Information System (INIS)

Tsai, I.C.; Lee, Tain; Chen, Min-Chi; Fu, Yun-Ching; Jan, Sheng-Lin; Wang, Chung-Chi; Chang, Yen

2007-01-01

Multidetector CT (MDCT) seems to be a promising tool for detection of neonatal coronary arteries, but whether the ECG-gated or non-ECG-gated technique should be used has not been established. To compare the detection rate and image quality of neonatal coronary arteries on MDCT using ECG-gated and non-ECG-gated techniques. Twelve neonates with complex congenital heart disease were included. The CT scan was acquired using an ECG-gated technique, and the most quiescent phase of the RR interval was selected to represent the ECG-gated images. The raw data were then reconstructed without the ECG signal to obtain non-ECG-gated images. The detection rate and image quality of nine coronary artery segments in the two sets of images were then compared. A two-tailed paired t test was used with P values <0.05 considered as statistically significant. In all coronary segments the ECG-gated technique had a better detection rate and produced images of better quality. The difference between the two techniques ranged from 25% in the left main coronary artery to 100% in the distal right coronary artery. For neonates referred for MDCT, if evaluation of coronary artery anatomy is important for the clinical management or surgical planning, the ECG-gated technique should be used because it can reliably detect the coronary arteries. (orig.)

Ferritin-Templated Quantum-Dots for Quantum Logic Gates

Science.gov (United States)

Choi, Sang H.; Kim, Jae-Woo; Chu, Sang-Hyon; Park, Yeonjoon; King, Glen C.; Lillehei, Peter T.; Kim, Seon-Jeong; Elliott, James R.

2005-01-01

Quantum logic gates (QLGs) or other logic systems are based on quantum-dots (QD) with a stringent requirement of size uniformity. The QD are widely known building units for QLGs. The size control of QD is a critical issue in quantum-dot fabrication. The work presented here offers a new method to develop quantum-dots using a bio-template, called ferritin, that ensures QD production in uniform size of nano-scale proportion. The bio-template for uniform yield of QD is based on a ferritin protein that allows reconstitution of core material through the reduction and chelation processes. One of the biggest challenges for developing QLG is the requirement of ordered and uniform size of QD for arrays on a substrate with nanometer precision. The QD development by bio-template includes the electrochemical/chemical reconsitution of ferritins with different core materials, such as iron, cobalt, manganese, platinum, and nickel. The other bio-template method used in our laboratory is dendrimers, precisely defined chemical structures. With ferritin-templated QD, we fabricated the heptagonshaped patterned array via direct nano manipulation of the ferritin molecules with a tip of atomic force microscope (AFM). We also designed various nanofabrication methods of QD arrays using a wide range manipulation techniques. The precise control of the ferritin-templated QD for a patterned arrangement are offered by various methods, such as a site-specific immobilization of thiolated ferritins through local oxidation using the AFM tip, ferritin arrays induced by gold nanoparticle manipulation, thiolated ferritin positioning by shaving method, etc. In the signal measurements, the current-voltage curve is obtained by measuring the current through the ferritin, between the tip and the substrate for potential sweeping or at constant potential. The measured resistance near zero bias was 1.8 teraohm for single holoferritin and 5.7 teraohm for single apoferritin, respectively.

Array TDEM survey at the Yufuin fault; Yufuin danso ni okeru array shiki TDEM tansa

Energy Technology Data Exchange (ETDEWEB)

Mogi, T [Kyushu University, Fukuoka (Japan). Faculty of Engineering; Tanaka, Y; Fukuda, Y [Kyoto University, Kyoto (Japan). Faculty of Science; Jomori, N [Chiba Electric Research Institute Co., Chiba (Japan)

1996-10-01

The array arrangement of receivers was studied to improve the resolution of LOTEM (long offset transient electromagnetics) survey. To eliminate the effect of underground structure from a source to a receiving point, continuous array arrangement from a source site is desirable. The survey at the Yufuin fault was carried out by arranging TEM receivers at intervals of 100m from the source. Since the synchronization between transmitting and receiving points by high-precision clock is essential, an amplifier for a flux gate magnetometer capable of measuring at four points at the same time was used. In the south plateau of the Yufuin basin, a relatively high resistivity stratum more than several tens ohm m exists at depth less than several hundreds meter, and a low resistivity stratum less than 10 ohm m exists under that. Those boundary depth increases toward the north up to 950m, and the depth subsequently decreases toward the north until the low resistivity stratum disappears. In addition, the uniform stratum of 1000m deep continues toward the north. Such precise resistivity structure around the fault was obtained by dense arrangement of measuring points. 4 refs., 7 figs.

Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

Energy Technology Data Exchange (ETDEWEB)

Datta, Deepanjan [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 (United States); Ganguly, Samiran [Department of Electronics Engineering, Indian School of Mines, Dhanbad-826004 (India); Dasgupta, S [Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee-247667 (India)

2007-05-30

Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p{sup +} poly-n{sup +} poly-p{sup +} poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.

Sliding-gate valve for use with abrasive materials

Science.gov (United States)

Ayers, Jr., William J.; Carter, Charles R.; Griffith, Richard A.; Loomis, Richard B.; Notestein, John E.

1985-01-01

The invention is a flow and pressure-sealing valve for use with abrasive solids. The valve embodies special features which provide for long, reliable operating lifetimes in solids-handling service. The valve includes upper and lower transversely slidable gates, contained in separate chambers. The upper gate provides a solids-flow control function, whereas the lower gate provides a pressure-sealing function. The lower gate is supported by means for (a) lifting that gate into sealing engagement with its seat when the gate is in its open and closed positions and (b) lowering the gate out of contact with its seat to permit abrasion-free transit of the gate between its open and closed positions. When closed, the upper gate isolates the lower gate from the solids. Because of this shielding action, the sealing surface of the lower gate is not exposed to solids during transit or when it is being lifted or lowered. The chamber containing the lower gate normally is pressurized slightly, and a sweep gas is directed inwardly across the lower-gate sealing surface during the vertical translation of the gate.

Photon-gated spin transistor

OpenAIRE

Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

2017-01-01

Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

Javascript Library for Developing Interactive Micro-Level Animations for Teaching and Learning Algorithms on One-Dimensional Arrays

Science.gov (United States)

Végh, Ladislav

2016-01-01

The first data structure that first-year undergraduate students learn during the programming and algorithms courses is the one-dimensional array. For novice programmers, it might be hard to understand different algorithms on arrays (e.g. searching, mirroring, sorting algorithms), because the algorithms dynamically change the values of elements. In…

Reversible logic gates on Physarum Polycephalum

International Nuclear Information System (INIS)

Schumann, Andrew

2015-01-01

In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

SU-E-T-403: Evaluation of the Beam Performance of a Varian TrueBeam Linear Accelerator Under External Device-Based Gated Delivery Conditions

International Nuclear Information System (INIS)

Kobulnicky, K; Pawlak, D; Purwar, A

2015-01-01

Purpose: To examine the beam performance of a Varian TrueBeam linear accelerator under external device-based gated delivery conditions. Methods: Six gating cycles were used to evaluate the gating performance of a standard production TrueBeam system that was not specially tuned in any way. The system was equipped with a factory installed external gating interface (EXGI). An in-house EXGI tester box was used to simulate the input gating signals. The gating cycles were selected based on long beam-on and short beam-off times, short beam-on and long beam-off times, or equal beam on and off times to check linac performance. The beam latencies were measured as the time difference between the logic high gating signal and the first or last target pulses with an oscilloscope. Tissue-Phantom Ratio, beam flatness, and dose distributions from 5 different plans were measured using the 6 different gating durations and the un-gated irradiation. A PTW 729 2-D array was used to compare 5 plans versus the un-gated delivery with a 1%/1mm gamma index passing criteria. Results: The beam latencies of the linac were based off of 20 samples for beam-on and beam-off, for each gating cycle. The average beam-on delays were measured to be between 57 and 66msec, with a maximum of 88 msec. The beam off latencies averaged between 19 and 26msec, with a maximum of 48 msec. TPR20,10 measurements showed beam energy stability within 0.5% of the un-gated delivery. Beam flatness was better than 2.5% for all gated cycles. All but two deliveries, the open field with 4 seconds on, 1 second off, and a five field IMRT plan with 0.5 seconds on, 2.5 seconds off, had >90% passing rate. Conclusion: TrueBeam demonstrates excellent beam stability with minimal beam latencies under external device-based gated operations. Dosimetric measurements show minimal variation in beam energy, flatness, and plan delivery. Authors are employees of Varian Medical Systems, Inc

SU-E-T-403: Evaluation of the Beam Performance of a Varian TrueBeam Linear Accelerator Under External Device-Based Gated Delivery Conditions

Energy Technology Data Exchange (ETDEWEB)

Kobulnicky, K; Pawlak, D; Purwar, A [Varian Medical Systems, Inc., Palo Alto, CA (United States)

2015-06-15

Purpose: To examine the beam performance of a Varian TrueBeam linear accelerator under external device-based gated delivery conditions. Methods: Six gating cycles were used to evaluate the gating performance of a standard production TrueBeam system that was not specially tuned in any way. The system was equipped with a factory installed external gating interface (EXGI). An in-house EXGI tester box was used to simulate the input gating signals. The gating cycles were selected based on long beam-on and short beam-off times, short beam-on and long beam-off times, or equal beam on and off times to check linac performance. The beam latencies were measured as the time difference between the logic high gating signal and the first or last target pulses with an oscilloscope. Tissue-Phantom Ratio, beam flatness, and dose distributions from 5 different plans were measured using the 6 different gating durations and the un-gated irradiation. A PTW 729 2-D array was used to compare 5 plans versus the un-gated delivery with a 1%/1mm gamma index passing criteria. Results: The beam latencies of the linac were based off of 20 samples for beam-on and beam-off, for each gating cycle. The average beam-on delays were measured to be between 57 and 66msec, with a maximum of 88 msec. The beam off latencies averaged between 19 and 26msec, with a maximum of 48 msec. TPR20,10 measurements showed beam energy stability within 0.5% of the un-gated delivery. Beam flatness was better than 2.5% for all gated cycles. All but two deliveries, the open field with 4 seconds on, 1 second off, and a five field IMRT plan with 0.5 seconds on, 2.5 seconds off, had >90% passing rate. Conclusion: TrueBeam demonstrates excellent beam stability with minimal beam latencies under external device-based gated operations. Dosimetric measurements show minimal variation in beam energy, flatness, and plan delivery. Authors are employees of Varian Medical Systems, Inc.

Digitally programmable microfluidic automaton for multiscale combinatorial mixing and sample processing†

Science.gov (United States)

Jensen, Erik C.; Stockton, Amanda M.; Chiesl, Thomas N.; Kim, Jungkyu; Bera, Abhisek; Mathies, Richard A.

2013-01-01

A digitally programmable microfluidic Automaton consisting of a 2-dimensional array of pneumatically actuated microvalves is programmed to perform new multiscale mixing and sample processing operations. Large (µL-scale) volume processing operations are enabled by precise metering of multiple reagents within individual nL-scale valves followed by serial repetitive transfer to programmed locations in the array. A novel process exploiting new combining valve concepts is developed for continuous rapid and complete mixing of reagents in less than 800 ms. Mixing, transfer, storage, and rinsing operations are implemented combinatorially to achieve complex assay automation protocols. The practical utility of this technology is demonstrated by performing automated serial dilution for quantitative analysis as well as the first demonstration of on-chip fluorescent derivatization of biomarker targets (carboxylic acids) for microchip capillary electrophoresis on the Mars Organic Analyzer. A language is developed to describe how unit operations are combined to form a microfluidic program. Finally, this technology is used to develop a novel microfluidic 6-sample processor for combinatorial mixing of large sets (>26 unique combinations) of reagents. The digitally programmable microfluidic Automaton is a versatile programmable sample processor for a wide range of process volumes, for multiple samples, and for different types of analyses. PMID:23172232

Stanford, Duke, Rice,... and Gates?

Science.gov (United States)

Carey, Kevin

2009-01-01

This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

Effects Of Local Oscillator Errors On Digital Beamforming

Science.gov (United States)

2016-03-01

processor EF element factor EW electronic warfare FFM flicker frequency modulation FOV field-of-view FPGA field-programmable gate array FPM flicker...frequencies and also more difficult to measure [15]. 2. Flicker frequency modulation The source for flicker frequency modulation ( FFM ) is attributed to...a physical resonance mechanism of an oscillator or issues controlling electronic components. Some oscillators might not show FFM noise, which might

FPGA Based Acceleration of Decimal Operations

DEFF Research Database (Denmark)

Nannarelli, Alberto

2011-01-01

Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show...... an advanced input/output interface, can achieve a speed-up of about 10 over its execution on the CPU of the hosting computer....

Performance evaluation of coherent Ising machines against classical neural networks

Science.gov (United States)

Haribara, Yoshitaka; Ishikawa, Hitoshi; Utsunomiya, Shoko; Aihara, Kazuyuki; Yamamoto, Yoshihisa

2017-12-01

The coherent Ising machine is expected to find a near-optimal solution in various combinatorial optimization problems, which has been experimentally confirmed with optical parametric oscillators and a field programmable gate array circuit. The similar mathematical models were proposed three decades ago by Hopfield et al in the context of classical neural networks. In this article, we compare the computational performance of both models.

Benchmarking gate-based quantum computers

Science.gov (United States)

Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans

2017-11-01

With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.

Motion Correction using Coil Arrays (MOCCA) for Free-Breathing Cardiac Cine MRI

Science.gov (United States)

Hu, Peng; Hong, Susie; Moghari, Mehdi H.; Goddu, Beth; Goepfert, Lois; Kissinger, Kraig V.; Hauser, Thomas H.; Manning, Warren J; Nezafat, Reza

2014-01-01

In this study, we present a motion compensation technique based on coil arrays (MOCCA) and evaluate its application in free-breathing respiratory self-gated cine MRI. MOCCA takes advantages of the fact that motion-induced changes in k-space signal are modulated by individual coil sensitivity profiles. In the proposed implementation of MOCCA self-gating for free-breathing cine MRI, the k-space center line is acquired at the beginning of each k-space segment for each cardiac cycle with 4 repetitions. For each k-space segment, the k-space center line acquired immediately before was used to select one of the 4 acquired repetitions to be included in the final self-gated cine image by calculating the cross-correlation between the k-space center line with a reference line. The proposed method was tested on a cohort of healthy adult subjects for subjective image quality and objective blood-myocardium border sharpness. The method was also tested on a cohort of patients to compare the left and right ventricular volumes and ejection fraction measurements with that of standard breath-hold cine MRI. Our data indicate that the proposed MOCCA method provides significantly improved image quality and sharpness compared to free-breathing cine without respiratory self-gating, and provides similar volume measurements compared with breath-hold cine MRI. PMID:21773986

Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

Energy Technology Data Exchange (ETDEWEB)

Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun; Ding, Shi-Jin, E-mail: sjding@fudan.edu.cn [State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 (China)

2015-12-15

Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.

Reliability evaluation programmable logic devices

International Nuclear Information System (INIS)

Srivani, L.; Murali, N.; Thirugnana Murthy, D.; Satya Murty, S.A.V.

2014-01-01

Programmable Logic Devices (PLD) are widely used as basic building modules in high integrity systems, considering their robust features such as gate density, performance, speed etc. PLDs are used to implement digital design such as bus interface logic, control logic, sequencing logic, glue logic etc. Due to semiconductor evolution, new PLDs with state-of-the-art features are arriving to the market. Since these devices are reliable as per the manufacturer's specification, they were used in the design of safety systems. But due to their reduced market life, the availability of performance data is limited. So evaluating the PLD before deploying in a safety system is very important. This paper presents a survey on the use of PLDs in the nuclear domain and the steps involved in the evaluation of PLD using Quantitative Accelerated Life Testing. (author)

Programmable trigger for electron pairs in ring image Cherenkov counters

International Nuclear Information System (INIS)

Glab, J.; Baur, R.; Manner, R.

1990-01-01

This paper describes a programmable trigger processor for the recognition of Cherenkov rings in a RICH counter. It identifies open electron pairs and suppresses close conversion and Dalitz pairs within 20 μs. More generally, the system can be used for correlating pixel images with pattern masks in order to locate all relatively well defined patterns of a certain type. The trigger processor consists of a systolic processor array of 160 x 176, i.e., 28,160 identical processing elements (PEs) that filter out open electron pairs, and a pseudo adder array that determines whether there was at least one such pair. The processor array is assembled of 20 x 22 VLSI chips containing 8 x 8 PEs each. The semi-custom chip has been developed in 2 μ CMOS standard cell technology

Gate Engineering in SOI LDMOS for Device Reliability

Directory of Open Access Journals (Sweden)

Aanand

2016-01-01

Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

Energy Technology Data Exchange (ETDEWEB)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr [Advanced Display Research Center and Department of Information Display, Kyung Hee University, Seoul 02447 (Korea, Republic of)

2016-07-15

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of In metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.

GATE: Improving the computational efficiency

International Nuclear Information System (INIS)

Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.

2006-01-01

GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable

Dual-gated cardiac PET-clinical feasibility study

Energy Technology Data Exchange (ETDEWEB)

Teraes, Mika; Kokki, Tommi; Noponen, Tommi; Hoppela, Erika; Sipilae, Hannu T.; Knuuti, Juhani [Turku PET Centre, PO BOX 52, Turku (Finland); Durand-Schaefer, Nicolas [General Electric Medical Systems, Buc (France); Pietilae, Mikko [Turku University Hospital, Department of Internal Medicine, Turku (Finland); Kiss, Jan [Turku University Hospital, Department of Surgery, Turku (Finland)

2010-03-15

Both respiratory and cardiac motions reduce image quality in myocardial imaging. For accurate imaging of small structures such as vulnerable coronary plaques, simultaneous cardiac and respiratory gating is warranted. This study tests the feasibility of a recently developed robust method for cardiac-respiratory gating. List-mode data with triggers from respiratory and cardiac cycles are rearranged into dual-gated segments and reconstructed with standard algorithms of a commercial PET/CT scanner. Cardiac gates were defined as three fixed phases and one variable diastolic phase. Chest motion was measured with a respiratory gating device and post-processed to determine gates. Preservation of quantification in dual-gated images was tested with an IEC whole-body phantom. Minipig and human studies were performed to evaluate the feasibility of the method. In minipig studies, a coronary catheter with radioactive tip was guided in coronary artery for in vivo and ex vivo acquisitions. Dual gating in humans with suspected cardiac disorders was performed using 18-F-FDG as a tracer. The method was found feasible for in vivo imaging and the radioactive catheter tip was better resolved in gated images. In human studies, the dual gating was found feasible and easy for clinical routine. Maximal movement of myocardial surface in cranio-caudal direction was over 20 mm. The shape of myocardium was clearly different between the gates and papillary muscles become more visible in diastolic images. The first clinical experiences using robust cardiac-respiratory dual gating are encouraging. Further testing in larger clinical populations using tracers designed especially for plaque imaging is warranted. (orig.)

Dual-gated cardiac PET-clinical feasibility study

International Nuclear Information System (INIS)

Teraes, Mika; Kokki, Tommi; Noponen, Tommi; Hoppela, Erika; Sipilae, Hannu T.; Knuuti, Juhani; Durand-Schaefer, Nicolas; Pietilae, Mikko; Kiss, Jan

2010-01-01

Both respiratory and cardiac motions reduce image quality in myocardial imaging. For accurate imaging of small structures such as vulnerable coronary plaques, simultaneous cardiac and respiratory gating is warranted. This study tests the feasibility of a recently developed robust method for cardiac-respiratory gating. List-mode data with triggers from respiratory and cardiac cycles are rearranged into dual-gated segments and reconstructed with standard algorithms of a commercial PET/CT scanner. Cardiac gates were defined as three fixed phases and one variable diastolic phase. Chest motion was measured with a respiratory gating device and post-processed to determine gates. Preservation of quantification in dual-gated images was tested with an IEC whole-body phantom. Minipig and human studies were performed to evaluate the feasibility of the method. In minipig studies, a coronary catheter with radioactive tip was guided in coronary artery for in vivo and ex vivo acquisitions. Dual gating in humans with suspected cardiac disorders was performed using 18-F-FDG as a tracer. The method was found feasible for in vivo imaging and the radioactive catheter tip was better resolved in gated images. In human studies, the dual gating was found feasible and easy for clinical routine. Maximal movement of myocardial surface in cranio-caudal direction was over 20 mm. The shape of myocardium was clearly different between the gates and papillary muscles become more visible in diastolic images. The first clinical experiences using robust cardiac-respiratory dual gating are encouraging. Further testing in larger clinical populations using tracers designed especially for plaque imaging is warranted. (orig.)

Demonstration of a Quantum Nondemolition Sum Gate

DEFF Research Database (Denmark)

Yoshikawa, J.; Miwa, Y.; Huck, Alexander

2008-01-01

The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...

Validation of the GATE Monte Carlo simulation platform for modelling a CsI(Tl) scintillation camera dedicated to small-animal imaging

International Nuclear Information System (INIS)

Lazaro, D; Buvat, I; Loudos, G; Strul, D; Santin, G; Giokaris, N; Donnarieix, D; Maigne, L; Spanoudaki, V; Styliaris, S; Staelens, S; Breton, V

2004-01-01

Monte Carlo simulations are increasingly used in scintigraphic imaging to model imaging systems and to develop and assess tomographic reconstruction algorithms and correction methods for improved image quantitation. GATE (GEANT4 application for tomographic emission) is a new Monte Carlo simulation platform based on GEANT4 dedicated to nuclear imaging applications. This paper describes the GATE simulation of a prototype of scintillation camera dedicated to small-animal imaging and consisting of a CsI(Tl) crystal array coupled to a position-sensitive photomultiplier tube. The relevance of GATE to model the camera prototype was assessed by comparing simulated 99m Tc point spread functions, energy spectra, sensitivities, scatter fractions and image of a capillary phantom with the corresponding experimental measurements. Results showed an excellent agreement between simulated and experimental data: experimental spatial resolutions were predicted with an error less than 100 μm. The difference between experimental and simulated system sensitivities for different source-to-collimator distances was within 2%. Simulated and experimental scatter fractions in a [98-82 keV] energy window differed by less than 2% for sources located in water. Simulated and experimental energy spectra agreed very well between 40 and 180 keV. These results demonstrate the ability and flexibility of GATE for simulating original detector designs. The main weakness of GATE concerns the long computation time it requires: this issue is currently under investigation by the GEANT4 and the GATE collaborations

Development of FPGA-Based Control Board

Energy Technology Data Exchange (ETDEWEB)

Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

2009-10-15

It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

Digitally Programmable High-Q Voltage Mode Universal Filter

Directory of Open Access Journals (Sweden)

D. Singh

2013-12-01

Full Text Available A new low-voltage low-power CMOS current feedback amplifier (CFA is presented in this paper. This is used to realize a novel digitally programmable CFA (DPCFA using transistor arrays and MOS switches. The proposed realizations nearly allow rail-to-rail swing capability at all the ports. Class-AB output stage ensures low power dissipation and high current drive capability. The proposed CFA/ DPCFA operates at supply voltage of ±0.75 V and exhibits bandwidth better than 95 MHz. An application of the DPCFA to realize a novel voltage mode high-Q digitally programmable universal filter (UF is given. Performances of all the proposed circuits are verified by PSPICE simulation using TSMC 0.25μm technology parameters.

Multi-gated field emitters for a micro-column

International Nuclear Information System (INIS)

Mimura, Hidenori; Kioke, Akifumi; Aoki, Toru; Neo, Yoichiro; Yoshida, Tomoya; Nagao, Masayoshi

2011-01-01

We have developed a multi-gated field emitter (FE) such as a quadruple-gated FE with a three-stacked electrode lens and a quintuple-gated FE with a four-stacked electrode lens. Both the FEs can focus the electron beam. However, the quintuple-gated FE has a stronger electron convergence than the quadruple-gated FE, and a beam crossover is clearly observed for the quintuple-gated FE.

Picosecond time-resolved laser pump/X-ray probe experiments using a gated single-photon-counting area detector

DEFF Research Database (Denmark)

Ejdrup, T.; Lemke, H.T.; Haldrup, Martin Kristoffer

2009-01-01

The recent developments in X-ray detectors have opened new possibilities in the area of time-resolved pump/probe X-ray experiments; this article presents the novel use of a PILATUS detector to achieve X-ray pulse duration limited time-resolution at the Advanced Photon Source (APS), USA...... limited time-resolution of 60 ps using the gated PILATUS detector. This is the first demonstration of X-ray pulse duration limited data recorded using an area detector without the use of a mechanical chopper array at the beamline........ The capability of the gated PILATUS detector to selectively detect the signal from a given X-ray pulse in 24 bunch mode at the APS storage ring is demonstrated. A test experiment performed on polycrystalline organic thin films of [alpha]-perylene illustrates the possibility of reaching an X-ray pulse duration...

An evaluation of gating window size, delivery method, and composite field dosimetry of respiratory-gated IMRT

International Nuclear Information System (INIS)

Hugo, Geoffrey D.; Agazaryan, Nzhde; Solberg, Timothy D.

2002-01-01

A respiratory gating system has been developed based on a commercial patient positioning system. The purpose of this study is to investigate the ability of the gating system to reproduce normal, nongated IMRT operation and to quantify the errors produced by delivering a nongated IMRT treatment onto a moving target. A moving phantom capable of simultaneous two-dimensional motion was built, and an analytical liver motion function was used to drive the phantom. Studies were performed to assess the effect of gating window size and choice of delivery method (segmented and dynamic multileaf collimation). Additionally, two multiple field IMRT cases were delivered to quantify the error in gated and nongated IMRT with motion. Dosimetric error between nonmoving and moving deliveries is related to gating window size. By reducing the window size, the error can be reduced. Delivery error can be reduced for both dynamic and segmented delivery with gating. For the implementation of dynamic IMRT delivery in this study, dynamic delivery was found to generate larger delivery errors than segmented delivery in most cases studied. For multiple field IMRT delivery, the largest errors were generated in regions where high field modulation was present parallel to the axis of motion. Gating was found to reduce these large errors to clinically acceptable levels

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

Science.gov (United States)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Array of organic thin film transistors integrated with organic light emitting diodes on a plastic substrate

International Nuclear Information System (INIS)

Ryu, Gi-Seong; Choe, Ki-Beom; Song, Chung-Kun

2006-01-01

In order to demonstrate the possible application of an organic thin film transistor (OTFT) to a flexible active matrix organic light emitting diode (OLED) an array of 64 x 64 pixels was fabricated on a 4-in. size poly-ethylene-terephehalate substrate. Each pixel was composed of one OTFT integrated with one OLED. OTFTs successfully drove OLEDs by varying current in a wide range and some images were displayed on the array by emitting green light. The OTFTs used poly(4-vinylphenol) for the gate and pentacene for the semiconductor taking account compatibility with the PET substrate. The average mobility in the array was 0.2 cm 2 /V.s, which was reduced from 1.0 cm 2 /V.s in a single OTFT, and its variation over the entire substrate was 10%

EUROGAM: A high efficiency escape suppressed spectrometer array

Energy Technology Data Exchange (ETDEWEB)

Nolan, P J [Liverpool Univ. (United Kingdom). Oliver Lodge Lab.

1992-08-01

EUROGAM is a UK-France collaboration to develop and build a high efficiency escape suppressed spectrometer array. The project has involved the development of both germanium (Ge) and bismuth germanate (BGO) detectors to produce crystals which are both bigger and have a more complex geometry. As a major investment for the future, the collaboration has developed a new electronics and data acquisition system based on the VXI and VME standards. The array will start its experimental programme in mid 1992 at the Nuclear Structure Facility at Daresbury, U.K. At this stage it will have a total photopeak efficiency (for 1.33 MeV gamma-rays) of {approx} 4.5%. This will give an improvement in sensitivity (relative to presently operating arrays) of a factor of about 10. When EUROGAM moves to France in mid 1993 its photopeak efficiency will have increased to about 8.5% which will result in an increase in sensitivity of a further factor of about 10. In this article I will concentrate on the array which will operate at Daresbury in 1992 and only briefly cover the developments which will take place for the full array before it is used in France in 1993. (author). 13 refs., 2 tabs., 10 figs.

EUROGAM: A high efficiency escape suppressed spectrometer array

International Nuclear Information System (INIS)

Nolan, P.J.

1992-01-01

EUROGAM is a UK-France collaboration to develop and build a high efficiency escape suppressed spectrometer array. The project has involved the development of both germanium (Ge) and bismuth germanate (BGO) detectors to produce crystals which are both bigger and have a more complex geometry. As a major investment for the future, the collaboration has developed a new electronics and data acquisition system based on the VXI and VME standards. The array will start its experimental programme in mid 1992 at the Nuclear Structure Facility at Daresbury, U.K. At this stage it will have a total photopeak efficiency (for 1.33 MeV gamma-rays) of ∼ 4.5%. This will give an improvement in sensitivity (relative to presently operating arrays) of a factor of about 10. When EUROGAM moves to France in mid 1993 its photopeak efficiency will have increased to about 8.5% which will result in an increase in sensitivity of a further factor of about 10. In this article I will concentrate on the array which will operate at Daresbury in 1992 and only briefly cover the developments which will take place for the full array before it is used in France in 1993. (author). 13 refs., 2 tabs., 10 figs

Design of digital logic control for accelerator magnet power supply

International Nuclear Information System (INIS)

Long Fengli; Hu Wei; Cheng Jian

2008-01-01

For the accelerator magnet power supply, usually the Programmable Logic Controller (PLC) is used to server as the controller for logic protection and control. Along with the development of modern accelerator technology, it is a trend to use fully-digital control to the magnet power supply. It is possible to integrate the logic control part into the digital control component of the power supply, for example, the Field Programmable Gate Array (FPGA). The paper introduces to different methods which are designed for the logic protection and control for accelerator magnet power supplies with the FPGA as the control component. (authors)

Hardware and Software Integration in Project Development of Automated Controller System Using LABVIEW FPGA

International Nuclear Information System (INIS)

Mohd Khairulezwan Abd Manan; Mohd Sabri Minhat; Izhar Abu Hussin

2014-01-01

The Field-Programmable Gate Array (FPGA) is a semiconductor device that can be programmed after manufacturing. Instead of being restricted to any predetermined hardware function, an FPGA allows user to program product features and functions, adapt to new standards, and reconfigure hardware for specific applications even after the product has been installed in the field, hence the name field-programmable. This project developed a control system using LabVIEW FPGA. LabVIEW FPGA is easier where it is programmed by using drag and drop icon. Then it will be integrated with the hardware input and output. (author)

Double optical gating

Science.gov (United States)

Gilbertson, Steve

The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.

Solution-processed single-wall carbon nanotube transistor arrays for wearable display backplanes

Directory of Open Access Journals (Sweden)

Byeong-Cheol Kang

2018-01-01

Full Text Available In this paper, we demonstrate solution-processed single-wall carbon nanotube thin-film transistor (SWCNT-TFT arrays with polymeric gate dielectrics on the polymeric substrates for wearable display backplanes, which can be directly attached to the human body. The optimized SWCNT-TFTs without any buffer layer on flexible substrates exhibit a linear field-effect mobility of 1.5cm2/V-s and a threshold voltage of around 0V. The statistical plot of the key device metrics extracted from 35 SWCNT-TFTs which were fabricated in different batches at different times conclusively support that we successfully demonstrated high-performance solution-processed SWCNT-TFT arrays which demand excellent uniformity in the device performance. We also investigate the operational stability of wearable SWCNT-TFT arrays against an applied strain of up to 40%, which is the essential for a harsh degree of strain on human body. We believe that the demonstration of flexible SWCNT-TFT arrays which were fabricated by all solution-process except the deposition of metal electrodes at process temperature below 130oC can open up new routes for wearable display backplanes.

Multi detector computed tomography (MDCT) of the aortic root; ECG-gated verses non-ECG-gated examinations

International Nuclear Information System (INIS)

Kristiansen, Joanna; Guenther, Anne; Aalokken, Trond Mogens; Andersen, Rune

2011-01-01

Purpose: Motion artifacts may degrade a conventional CT examination of the ascending aorta and hinder accurate diagnosis. We quantitatively compared retrospectively electrocardiographic (ECG) -gated multi detector computed tomography (MDCT) with non-ECG-gated MDCT in order to demonstrate whether or not one of the methods should be preferred. Method: The study included seventeen patients with surgically reconstructed aortic root and reimplanted coronary arteries. All patients had undergone both non-gated MDCT and retrospectively ECG-gated MDCT employing a stringently modulated tube current with single phase image reconstruction. The incidence of motion artifacts in the left main coronary artery (LM), proximal right coronary artery (RCA), and aortic root and ascending aorta were rated using a four point scale. The effective dose for each scan was calculated and normalized to a 15 cm scan length. Statistical analysis of motion artifacts and radiation dose was performed using Wilcoxon matched pairs signed rank sum test. Results: A significant reduction in motion artifacts was found in all three vessels in images from the retrospectively ECG-gated scans (LM: P = 0.005, RCA: P = 0.015, aorta: P = 0.003). The mean normalized effective radiation dose was 3.69 mSv (±1.03) for the non-ECG-gated scans and 16.37 mSv (±2.53) for the ECG-gated scans. Conclusion: Retrospective ECG-gating with single phase reconstruction significantly reduces the incidence of motion artifacts in the aortic root and the proximal portion of the coronary arteries but at the expense of a fourfold increase in radiation dose.

FPGA Vision Data Architecture

Science.gov (United States)

Morfopoulos, Arin C.; Pham, Thang D.

2013-01-01

JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

Event Pre Processor for the CZT Detector on MIRAX

International Nuclear Information System (INIS)

Kendziorra, Eckhard; Schanz, Thomas; Distratis, Giuseppe; Suchy, Slawomir

2006-01-01

We describe the Event Pre Processor (EPP) for the Hard X-ray Imager (HXI) on MIRAX. The EPP provides on board data reduction and event filtering for the HXI Cadmium Zinc Telluride strip detector. Emphasis is placed upon the EPP requirements, its implementation as VHDL design in a Field Programmable Gate Array (FPGA), and the description of a test environment for both the VHDL code and the FPGA hardware

Dessign and Implementation of Hardened Reconfiguration Controller for Self-Healing Systems on SRAM-Based FPGAs

OpenAIRE

DERAKHSHAN, NASER

2013-01-01

As digital systems become large and complex, their dependability is getting more important, particularly in mission-critical and safety‐critical applications. Among various available platforms for implementing a digital system, SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly adopted in embedded systems due to their flexibility in achieving multiple requirements such as low cost, high performance, and fast turnaround time compared to Fixed Application Specific Integrated Cir...

Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

DEFF Research Database (Denmark)

Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

2012-01-01

This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

Implementation and Testing of the JANUS Standard with SSC Pacific’s Software-Defined Acoustic Modem

Science.gov (United States)

2017-10-01

JANUS limit) was typed from the keyboard by the user. Next, the transmitter bash script was run and the user typed the ASCII text of choice, or the...FDECO Forward Deployed Energy and Communications Outpost CONOPS concept of operation DSP digital signal processor FPGA field programmable gate array...deployed by U.S. and international military and civilian organizations have for decades operated without any type of widely adopted standards or

Signal compression in radar using FPGA

OpenAIRE

Escamilla Hemández, Enrique; Kravchenko, Víctor; Ponomaryov, Volodymyr; Duchen Sánchez, Gonzalo; Hernández Sánchez, David

2010-01-01

We present the hardware implementation of radar real time processing procedures using a simple, fast technique based on FPGA (Field Programmable Gate Array) architecture. This processing includes different window procedures during pulse compression in synthetic aperture radar (SAR). The radar signal compression processing is realized using matched filter, and classical and novel window functions, where we focus on better solution for minimum values of sidelobes. The proposed architecture expl...

High-Bandwidth Tactical-Network Data Analysis in a High-Performance-Computing (HPC) Environment: Packet-Level Analysis

Science.gov (United States)

2015-09-01

individual fragments using the hash-based method. In general, fragments 6 appear in order and relatively close to each other in the file. A fragment...data product derived from the data model is shown in Fig. 5, a Google Earth12 Keyhole Markup Language (KML) file. This product includes aggregate...System BLOb binary large object FPGA field-programmable gate array HPC high-performance computing IP Internet Protocol KML Keyhole Markup Language

Optimizing Gas Generator Efficiency in a Forward Operating Base Using an Energy Management System

Science.gov (United States)

2013-06-01

Bus Battery Chargers Routers Security Systems Laptops Radios Flat Panel Displays LED Lighting Fluorescent Lighting "Generator 2" 15kW Non...custom printed circuit board (PCB), field- programmable gate array (FPGA) development board and signal processing board. The battery pack is visible...source selection decisions are based upon system states such as load demand, generator capacity, and battery bank SoC. A simple RC circuit was used to

Algorithmic strategies for FPGA-based vision

OpenAIRE

Lim, Yoong Kang

2016-01-01

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms...

The Fermilab Advanced Computer Program multi-array processor system (ACPMAPS): A site oriented supercomputer for theoretical physics

International Nuclear Information System (INIS)

Nash, T.; Areti, H.; Atac, R.

1988-08-01

The ACP Multi-Array Processor System (ACPMAPS) is a highly cost effective, local memory parallel computer designed for floating point intensive grid based problems. The processing nodes of the system are single board array processors based on the FORTRAN and C programmable Weitek XL chip set. The nodes are connected by a network of very high bandwidth 16 port crossbar switches. The architecture is designed to achieve the highest possible cost effectiveness while maintaining a high level of programmability. The primary application of the machine at Fermilab will be lattice gauge theory. The hardware is supported by a transparent site oriented software system called CANOPY which shields theorist users from the underlying node structure. 4 refs., 2 figs

Zero deadtime spectroscopy without full charge collection

International Nuclear Information System (INIS)

Odell, D.M.C.; Bushart, B.S.; Harpring, L.J.; Moore, F.S.; Riley, T.N.

1998-01-01

The Savannah River Technology Center has built a remote gamma monitoring instrument which employs data sampling techniques rather than full charge collection to perform energy spectroscopy without instrument dead time. The raw, unamplified anode output of a photomultiplier tube is directly coupled to the instrument to generate many digital samples during the charge collection process, so that all pulse processing is done in the digital domain. The primary components are a free-running, 32 MSPS, 10-bit A/D, a field programmable gate array, FIFO buffers, and a digital signal processor (DSP). Algorithms for pulse integration, pile-up rejection, and other shape based criteria are being developed in DSP code for migration into the gate array. Spectra taken with a two inch Na(I) detector have been obtained at rates as high as 59,000 counts per second without dead time with peak resolution at 662 KeV measuring 7.3%

Double-gated spectral snapshots for biomolecular fluorescence

International Nuclear Information System (INIS)

Nakamura, Ryosuke; Hamada, Norio; Ichida, Hideki; Tokunaga, Fumio; Kanematsu, Yasuo

2007-01-01

A versatile method to take femtosecond spectral snapshots of fluorescence has been developed based on a double gating technique in the combination of an optical Kerr gate and an image intensifier as an electrically driven gate set in front of a charge-coupled device detector. The application of a conventional optical-Kerr-gate method is limited to molecules with the short fluorescence lifetime up to a few hundred picoseconds, because long-lifetime fluorescence itself behaves as a source of the background signal due to insufficiency of the extinction ratio of polarizers employed for the Kerr gate. By using the image intensifier with the gate time of 200 ps, we have successfully suppressed the background signal and overcome the application limit of optical-Kerr-gate method. The system performance has been demonstrated by measuring time-resolved fluorescence spectra for laser dye solution and the riboflavin solution as a typical sample of biomolecule

Radio frequency interference noise reduction using a field programmable gate array for SQUID applications

International Nuclear Information System (INIS)

Sakuta, K; Narita, Y; Itozaki, H

2007-01-01

It is important to remove large environmental noise in superconducting quantum interference device (SQUID) measurement without magnetic shielding. Active noise control (ANC) is one of the effective methods to reduce environmental noise. Recently, SQUIDs have been used in various applications at high frequencies, such as nuclear quadrupole resonance (NQR). The NQR frequency from explosives is in the range 0.5-5 MHz. In this case, an NQR sensor is exposed to AM radio frequency interference (RFI). The feasibility of the ANC system for RFI that used digital signal processing was studied. Our investigation showed that this digital ANC system can be applied to SQUID measurements for RFI suppression

Field Programmable Gate Array Based Parallel Strapdown Algorithm Design for Strapdown Inertial Navigation Systems

Directory of Open Access Journals (Sweden)

Long-Hua Ma

2011-08-01

Full Text Available A new generalized optimum strapdown algorithm with coning and sculling compensation is presented, in which the position, velocity and attitude updating operations are carried out based on the single-speed structure in which all computations are executed at a single updating rate that is sufficiently high to accurately account for high frequency angular rate and acceleration rectification effects. Different from existing algorithms, the updating rates of the coning and sculling compensations are unrelated with the number of the gyro incremental angle samples and the number of the accelerometer incremental velocity samples. When the output sampling rate of inertial sensors remains constant, this algorithm allows increasing the updating rate of the coning and sculling compensation, yet with more numbers of gyro incremental angle and accelerometer incremental velocity in order to improve the accuracy of system. Then, in order to implement the new strapdown algorithm in a single FPGA chip, the parallelization of the algorithm is designed and its computational complexity is analyzed. The performance of the proposed parallel strapdown algorithm is tested on the Xilinx ISE 12.3 software platform and the FPGA device XC6VLX550T hardware platform on the basis of some fighter data. It is shown that this parallel strapdown algorithm on the FPGA platform can greatly decrease the execution time of algorithm to meet the real-time and high precision requirements of system on the high dynamic environment, relative to the existing implemented on the DSP platform.

Hardware, Software and Data Analysis Techniques for SRAM-based Field Programmable Gate Array Circuits

National Research Council Canada - National Science Library

Hockenberry, Eugene B

2008-01-01

The main objective of this research is to accomplish two objectives; first, develop a robust test methodology to successfully allow researchers to isolate errors occurring in SRAM-based FPGAs and other memory devices...

Voltage-Gated Potassium Channels: A Structural Examination of Selectivity and Gating

Science.gov (United States)

Kim, Dorothy M.; Nimigean, Crina M.

2016-01-01

Voltage-gated potassium channels play a fundamental role in the generation and propagation of the action potential. The discovery of these channels began with predictions made by early pioneers, and has culminated in their extensive functional and structural characterization by electrophysiological, spectroscopic, and crystallographic studies. With the aid of a variety of crystal structures of these channels, a highly detailed picture emerges of how the voltage-sensing domain reports changes in the membrane electric field and couples this to conformational changes in the activation gate. In addition, high-resolution structural and functional studies of K+ channel pores, such as KcsA and MthK, offer a comprehensive picture on how selectivity is achieved in K+ channels. Here, we illustrate the remarkable features of voltage-gated potassium channels and explain the mechanisms used by these machines with experimental data. PMID:27141052

Audio-visual biofeedback for respiratory-gated radiotherapy: Impact of audio instruction and audio-visual biofeedback on respiratory-gated radiotherapy

International Nuclear Information System (INIS)

George, Rohini; Chung, Theodore D.; Vedam, Sastry S.; Ramakrishnan, Viswanathan; Mohan, Radhe; Weiss, Elisabeth; Keall, Paul J.

2006-01-01

Purpose: Respiratory gating is a commercially available technology for reducing the deleterious effects of motion during imaging and treatment. The efficacy of gating is dependent on the reproducibility within and between respiratory cycles during imaging and treatment. The aim of this study was to determine whether audio-visual biofeedback can improve respiratory reproducibility by decreasing residual motion and therefore increasing the accuracy of gated radiotherapy. Methods and Materials: A total of 331 respiratory traces were collected from 24 lung cancer patients. The protocol consisted of five breathing training sessions spaced about a week apart. Within each session the patients initially breathed without any instruction (free breathing), with audio instructions and with audio-visual biofeedback. Residual motion was quantified by the standard deviation of the respiratory signal within the gating window. Results: Audio-visual biofeedback significantly reduced residual motion compared with free breathing and audio instruction. Displacement-based gating has lower residual motion than phase-based gating. Little reduction in residual motion was found for duty cycles less than 30%; for duty cycles above 50% there was a sharp increase in residual motion. Conclusions: The efficiency and reproducibility of gating can be improved by: incorporating audio-visual biofeedback, using a 30-50% duty cycle, gating during exhalation, and using displacement-based gating

Image quality in non-gated versus gated reconstruction of tongue motion using magnetic resonance imaging: a comparison using automated image processing

Energy Technology Data Exchange (ETDEWEB)

Alvey, Christopher; Orphanidou, C.; Coleman, J.; McIntyre, A.; Golding, S.; Kochanski, G. [University of Oxford, Oxford (United Kingdom)

2008-11-15

The use of gated or ECG triggered MR is a well-established technique and developments in coil technology have enabled this approach to be applied to areas other than the heart. However, the image quality of gated (ECG or cine) versus non-gated or real-time has not been extensively evaluated in the mouth. We evaluate two image sequences by developing an automatic image processing technique which compares how well the image represents known anatomy. Four subjects practised experimental poly-syllabic sentences prior to MR scanning. Using a 1.5 T MR unit, we acquired comparable gated (using an artificial trigger) and non-gated sagittal images during speech. We then used an image processing algorithm to model the image grey along lines that cross the airway. Each line involved an eight parameter non-linear equation to model of proton densities, edges, and dimensions. Gated and non-gated images show similar spatial resolution, with non-gated images being slightly sharper (10% better resolution, less than 1 pixel). However, the gated sequences generated images of substantially lower inherent noise, and substantially better discrimination between air and tissue. Additionally, the gated sequences demonstrate a very much greater temporal resolution. Overall, image quality is better with gated imaging techniques, especially given their superior temporal resolution. Gated techniques are limited by the repeatability of the motions involved, and we have shown that speech to a metronome can be sufficiently repeatable to allow high-quality gated magnetic resonance imaging images. We suggest that gated sequences may be useful for evaluating other types of repetitive movement involving the joints and limb motions. (orig.)

Image quality in non-gated versus gated reconstruction of tongue motion using magnetic resonance imaging: a comparison using automated image processing

International Nuclear Information System (INIS)

Alvey, Christopher; Orphanidou, C.; Coleman, J.; McIntyre, A.; Golding, S.; Kochanski, G.

2008-01-01

The use of gated or ECG triggered MR is a well-established technique and developments in coil technology have enabled this approach to be applied to areas other than the heart. However, the image quality of gated (ECG or cine) versus non-gated or real-time has not been extensively evaluated in the mouth. We evaluate two image sequences by developing an automatic image processing technique which compares how well the image represents known anatomy. Four subjects practised experimental poly-syllabic sentences prior to MR scanning. Using a 1.5 T MR unit, we acquired comparable gated (using an artificial trigger) and non-gated sagittal images during speech. We then used an image processing algorithm to model the image grey along lines that cross the airway. Each line involved an eight parameter non-linear equation to model of proton densities, edges, and dimensions. Gated and non-gated images show similar spatial resolution, with non-gated images being slightly sharper (10% better resolution, less than 1 pixel). However, the gated sequences generated images of substantially lower inherent noise, and substantially better discrimination between air and tissue. Additionally, the gated sequences demonstrate a very much greater temporal resolution. Overall, image quality is better with gated imaging techniques, especially given their superior temporal resolution. Gated techniques are limited by the repeatability of the motions involved, and we have shown that speech to a metronome can be sufficiently repeatable to allow high-quality gated magnetic resonance imaging images. We suggest that gated sequences may be useful for evaluating other types of repetitive movement involving the joints and limb motions. (orig.)

Rapid gated Thallium-201 perfusion SPECT - clinically feasible?

International Nuclear Information System (INIS)

Wadhwa, S.S.; Mansberg, R.; Fernandes, V.B.; Wilkinson, D.; Abatti, D.

1998-01-01

Full text: Standard dose energy window optimised Thallium-201 (Tl-201) SPECT has about half the counts of a standard dose from Technetium-99m Sestamibi (Tc99m-Mibi) gated perfusion SPECT. This study investigates the clinical feasibility of rapid energy window optimised Tl-201 gated perfusion SPECT (gated-TI) and compares quantitative left ventricular ejection fraction (LVEF) and visually assessed image quality for wall motion and thickening to analogous values obtained from Tc99m-Mibi gated perfusion SPECT (gated - mibi). Methods: We studied 60 patients with a rest gated Tl-201 SPECT (100 MBq, 77KeV peak, 34% window, 20 sec/projection) followed by a post stress gated Sestamibi SPECT (1GBq, 140KeV, 20% window, 20 sec/projection) separate dual isotope protocol. LVEF quantitation was performed using commercially available software (SPECTEF, General Electric). Visual grading of image quality for wall thickening and motion was performed using a three-point scale (excellent, good and poor). Results: LVEF for gated Tl-201 SPECT was 59.6 ± 12.0% (Mean ± SD). LVEF for gated Sestamibi SPECT was 60.4 ±11.4% (Mean ± SD). These were not significantly different (P=0.27, T-Test). There was good correlation (r=0.9) between gated-TI and gated-mibi LVEF values. The quality of gated-Tl images was ranked as excellent, good and poor in 12, 50 and 38% of the patients respectively. Image quality was better in gated-mibi SPECT, with ratings of 12, 62 and 26% respectively. Conclusion: Rapid gated Thallium-201 acquisition with energy window optimisation can be effectively performed on majority of patients and offers the opportunity to assess not only myocardial perfusion and function, as with Technetium based agents, but also viability using a single day one isotope protocol

High-fidelity gates in quantum dot spin qubits.

Science.gov (United States)

Koh, Teck Seng; Coppersmith, S N; Friesen, Mark

2013-12-03

Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet-triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning [Symbol: see text], which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an f(opt)(g) that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound f(max) that is specific to the qubit-gate combination. We show that similar gate fidelities (~99:5%) should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins.

Research on range-gated laser active imaging seeker

Science.gov (United States)

You, Mu; Wang, PengHui; Tan, DongJie

2013-09-01

Compared with other imaging methods such as millimeter wave imaging, infrared imaging and visible light imaging, laser imaging provides both a 2-D array of reflected intensity data as well as 2-D array of range data, which is the most important data for use in autonomous target acquisition .In terms of application, it can be widely used in military fields such as radar, guidance and fuse. In this paper, we present a laser active imaging seeker system based on range-gated laser transmitter and sensor technology .The seeker system presented here consist of two important part, one is laser image system, which uses a negative lens to diverge the light from a pulse laser to flood illuminate a target, return light is collected by a camera lens, each laser pulse triggers the camera delay and shutter. The other is stabilization gimbals, which is designed to be a rotatable structure both in azimuth and elevation angles. The laser image system consists of transmitter and receiver. The transmitter is based on diode pumped solid-state lasers that are passively Q-switched at 532nm wavelength. A visible wavelength was chosen because the receiver uses a Gen III image intensifier tube with a spectral sensitivity limited to wavelengths less than 900nm.The receiver is image intensifier tube's micro channel plate coupled into high sensitivity charge coupled device camera. The image has been taken at range over one kilometer and can be taken at much longer range in better weather. Image frame frequency can be changed according to requirement of guidance with modifiable range gate, The instantaneous field of views of the system was found to be 2×2 deg. Since completion of system integration, the seeker system has gone through a series of tests both in the lab and in the outdoor field. Two different kinds of buildings have been chosen as target, which is located at range from 200m up to 1000m.To simulate dynamic process of range change between missile and target, the seeker system has

Retrospectively ECG-gated multi-detector row CT of the chest: does ECG-gating improve three-dimensional visualization of the bronchial tree?

International Nuclear Information System (INIS)

Schertler, T.; Wildermuth, S.; Willmann, J.K.; Crook, D.W.; Marincek, B.; Boehm, T.

2004-01-01

Purpose: To determine the impact of retrospectively ECG-gated multi-detector row CT (MDCT) on three-dimensional (3D) visualization of the bronchial tree and virtual bronchoscopy (VB) as compared to non-ECG-gated data acquisition. Materials and Methods: Contrast-enhanced retrospectively ECG-gated and non-ECG-gated MDCT of the chest was performed in 25 consecutive patients referred for assessment of coronary artery bypass grafts and pathology of the ascending aorta. ECG-gated MDCT data were reconstructed in diastole using an absolute reverse delay of -400 msec in all patients. In 10 patients additional reconstructions at -200 msec, -300 msec, and -500 msec prior to the R-wave were performed. Shaded surface display (SSD) and virtual bronchoscopy (VB) for visualization of the bronchial segments was performed with ECG-gated and non-ECG-gated MDCT data. The visualization of the bronchial tree underwent blinded scoring. Effective radiation dose and signal-to-noise ratio (SNR) for both techniques were compared. Results: There was no significant difference in visualizing single bronchial segments using ECG-gated compared to non-ECG-gated MDCT data. However, the total sum of scores for all bronchial segments visualized with non-ECG-gated MDCT was significantly higher compared to ECG-gated MDCT (P [de

Gated frequency-resolved optical imaging with an optical parametric amplifier for medical applications

Energy Technology Data Exchange (ETDEWEB)

Cameron, S.M.; Bliss, D.E.

1997-02-01

Implementation of optical imagery in a diffuse inhomogeneous medium such as biological tissue requires an understanding of photon migration and multiple scattering processes which act to randomize pathlength and degrade image quality. The nature of transmitted light from soft tissue ranges from the quasi-coherent properties of the minimally scattered component to the random incoherent light of the diffuse component. Recent experimental approaches have emphasized dynamic path-sensitive imaging measurements with either ultrashort laser pulses (ballistic photons) or amplitude modulated laser light launched into tissue (photon density waves) to increase image resolution and transmissive penetration depth. Ballistic imaging seeks to compensate for these {open_quotes}fog-like{close_quotes} effects by temporally isolating the weak early-arriving image-bearing component from the diffusely scattered background using a subpicosecond optical gate superimposed on the transmitted photon time-of-flight distribution. The authors have developed a broadly wavelength tunable (470 nm -2.4 {mu}m), ultrashort amplifying optical gate for transillumination spectral imaging based on optical parametric amplification in a nonlinear crystal. The time-gated image amplification process exhibits low noise and high sensitivity, with gains greater than 104 achievable for low light levels. We report preliminary benchmark experiments in which this system was used to reconstruct, spectrally upcovert, and enhance near-infrared two-dimensional images with feature sizes of 65 {mu}m/mm{sup 2} in background optical attenuations exceeding 10{sup 12}. Phase images of test objects exhibiting both absorptive contrast and diffuse scatter were acquired using a self-referencing Shack-Hartmann wavefront sensor in combination with short-pulse quasi-ballistic gating. The sensor employed a lenslet array based on binary optics technology and was sensitive to optical path distortions approaching {lambda}/100.

Gate errors in solid-state quantum-computer architectures

International Nuclear Information System (INIS)

Hu Xuedong; Das Sarma, S.

2002-01-01

We theoretically consider possible errors in solid-state quantum computation due to the interplay of the complex solid-state environment and gate imperfections. In particular, we study two examples of gate operations in the opposite ends of the gate speed spectrum, an adiabatic gate operation in electron-spin-based quantum dot quantum computation and a sudden gate operation in Cooper-pair-box superconducting quantum computation. We evaluate quantitatively the nonadiabatic operation of a two-qubit gate in a two-electron double quantum dot. We also analyze the nonsudden pulse gate in a Cooper-pair-box-based quantum-computer model. In both cases our numerical results show strong influences of the higher excited states of the system on the gate operation, clearly demonstrating the importance of a detailed understanding of the relevant Hilbert-space structure on the quantum-computer operations

Edge-on gating effect in molecular wires.

Science.gov (United States)

Lo, Wai-Yip; Bi, Wuguo; Li, Lianwei; Jung, In Hwan; Yu, Luping

2015-02-11

This work demonstrates edge-on chemical gating effect in molecular wires utilizing the pyridinoparacyclophane (PC) moiety as the gate. Different substituents with varied electronic demands are attached to the gate to simulate the effect of varying gating voltages similar to that in field-effect transistor (FET). It was observed that the orbital energy level and charge carrier's tunneling barriers can be tuned by changing the gating group from strong electron acceptors to strong electron donors. The single molecule conductance and current-voltage characteristics of this molecular system are truly similar to those expected for an actual single molecular transistor.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

Opening of the New Gate E - Final Closure of Gate C - New azur «B» type cern access card

CERN Multimedia

Relations with the Host States Service

2004-01-01

Gate E ("Charles de Gaulle Gate") to the Meyrin Site will be open, for those entitled to use it, from 1 November 2004. The opening of this Gate should contribute to relieving congestion not only on the Prévessin - RN84 and Meyrin Route border crossings but also at Gates A and B. As a result, Gate C will be closed indefinitely from 1 November 2004. Providing a direct link between the Meyrin Site and the French territory beyond the fenced part of the CERN site, Gate E is the subject of international agreements between CERN, Switzerland and France, on the basis of which the Director-General has issued the "Rules for the Use of Gate E", (document CERN/DSU-RH/12222 of 27 October 2004; see also the latest news in "publications" at http://www.cern.ch/relations/). The main provisions of these Rules are as follows: Gate E is open from Monday to Friday, except on official CERN holidays, from 7.30 a.m. to 9.30 a.m. for access into the site, and from 4.30 p.m. to 6.30 p.m. for passage out of the site. Persons are aut...

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

Science.gov (United States)

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

Science.gov (United States)

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Chip-by-chip configurable interconnection using digital printing techniques

International Nuclear Information System (INIS)

Mashayekhi, Mohammad; Carrabina, Jordi; Winchester, Lee; Laurila, Mika-Matti; Mäntysalo, Matti; Ogier, Simon; Terés, Lluís

2017-01-01

Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results. (paper)

Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

KAUST Repository

Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

2010-01-01

Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

KAUST Repository

Hussain, Muhammad Mustafa

2010-03-01

Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

Implementation of floating gate MOSFET in inverter for threshold voltage tunability

Directory of Open Access Journals (Sweden)

Musa F.A.S.

2017-01-01

Full Text Available This paper presents the ability of floating gate MOSFET (FGMOS threshold voltage to be programmed or tuned which is exploited to improve the performance of electronic circuit design. This special characteristic owns by FGMOS is definitely contributes towards low voltage and low power circuit design. The comparison of threshold voltage between FGMOS and conventional NMOS is done in order to prove that FGMOS is able to produce a lower threshold voltage compared to conventional NMOS. In addition, in this paper, an implementation of FGMOS into inverter circuit is also done to show the programmability of FGMOS threshold voltage. The operations of the inverter circuits are verified using Sypnopsys simulation in 0.1μm CMOS technology with supply voltage of 1.8V.

Protected gates for topological quantum field theories

International Nuclear Information System (INIS)

Beverland, Michael E.; Pastawski, Fernando; Preskill, John; Buerschaper, Oliver; Koenig, Robert; Sijher, Sumit

2016-01-01

We study restrictions on locality-preserving unitary logical gates for topological quantum codes in two spatial dimensions. A locality-preserving operation is one which maps local operators to local operators — for example, a constant-depth quantum circuit of geometrically local gates, or evolution for a constant time governed by a geometrically local bounded-strength Hamiltonian. Locality-preserving logical gates of topological codes are intrinsically fault tolerant because spatially localized errors remain localized, and hence sufficiently dilute errors remain correctable. By invoking general properties of two-dimensional topological field theories, we find that the locality-preserving logical gates are severely limited for codes which admit non-abelian anyons, in particular, there are no locality-preserving logical gates on the torus or the sphere with M punctures if the braiding of anyons is computationally universal. Furthermore, for Ising anyons on the M-punctured sphere, locality-preserving gates must be elements of the logical Pauli group. We derive these results by relating logical gates of a topological code to automorphisms of the Verlinde algebra of the corresponding anyon model, and by requiring the logical gates to be compatible with basis changes in the logical Hilbert space arising from local F-moves and the mapping class group

Latest design of gate valves

Energy Technology Data Exchange (ETDEWEB)

Kurzhofer, U.; Stolte, J.; Weyand, M.

1996-12-01

Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.