Regulatory issues on using programmable logic device in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Park, G. Y.; Yu, Y. J.; Kim, H. T.; Kwon, Y. I.; Park, H. S.; Jeong, C. H. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

2012-10-15

For replacing obsolete analog equipment in nuclear power plant, the Programmable Logic Devices (PLDs) using Hardware Description Language (HDL) have been widely adopted in digitalized Instrumentation and Control (I and C) systems because of its flexibility. For safety reviews on Nuclear Power Plants (NPPs,) qualifying digitalized safety I and C system using PLDs is an important issue. As an effort to provide regulatory position on using PLDs in safety I and C system, there is a research project to provide the regulatory positions against emerging issues involved with digitalisation of I and C system including using PLDs. Therefore, this paper addresses the important considerations for using PLDs in safety I and C systems such as diversity, independence and qualification, etc. In this point, this study focuses on technical reports for Field Programmable Gate Array (FPGA) from EPRI,. U.S. NRC, and relevant technical standards.

Field programmable gate array reliability analysis using the dynamic flow graph methodology

Energy Technology Data Exchange (ETDEWEB)

McNelles, Phillip; Lu, Lixuan [Faculty of Energy Systems and Nuclear Science, University of Ontario Institute of Technology (UOIT), Ontario (Canada)

2016-10-15

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the 'IEEE 1164 standard', registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

International Nuclear Information System (INIS)

Lashin, A. V.; Kozyrev, A. V.

2015-01-01

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

Flexible programmable logic module

Science.gov (United States)

Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

2001-01-01

The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

Universal programmable logic gate and routing method

Science.gov (United States)

Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Implementation of BES-III TOF trigger system in programmable logic devices

International Nuclear Information System (INIS)

Zheng Wei; Liu Shubin; Liu Xuzong; An Qi

2009-01-01

The TOF trigger sub-system on the upgrading Beijing Spectrometer is designed to receive 368 bits fast hit signals from the front end electronics module to yield 7 bits trigger information according to the physical requirement. It sends the processed real time trigger information to the Global-Trigger-Logic to generate the primal trigger signal L1, and sends processed 136 bits real time position information to the Track-Match-Logic to calculate the particle flight tracks. The sub-system also packages the valid events for the DAQ system to read out. Following the reconfigurable concept, a large number of programmable logic devices are employed to increase the flexibility and reliability of the system, and decrease the complexity and the space requirement of PCB layout. This paper describes the implementation of the kernel trigger logic in a programmable logic device. (authors)

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Implementation of programmable logic controller for proposed new instrumentation and control system of RTP

International Nuclear Information System (INIS)

Mohd Khairulezwan Abdul Manan; Mohd Idris Taib; Mohd Dzul Aiman Aslan

2010-01-01

Reactor Monitoring System is one of very important part of Reactor Instrumentation and Control system. Current monitoring system is using analog system whereby all circuits are discrete circuit and all displays and indicators are not digitalized. The proposed new system will use using a Commercial Off-The-Shelf, state of the art, Supervisory Control and Data Acquisition system such as Programmable Logic Controller as well as Computer System. The implementations of Programmable Logic Controller are used for Data Acquisition System and as a sub-system for Computer System where all the activities involved are stored for operation record and report as well as use for research purposes. Programmable Logic Controller receives galvanised or optically isolated signal from Reactor Protection System. Programmable Logic Controller also receives signal from other parameters as a digital and analog input related to reactor system. (author)

Development of Single-Event Upset hardened programmable logic devices in deep submicron CMOS; Developpement de circuits logiques programmables resistants aux aleas logiques en technologie CMOS submicrometrique

Energy Technology Data Exchange (ETDEWEB)

Bonacini, S

2007-11-15

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust (Single Event Upset) programmable components for application in high energy physics experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 {mu}m CMOS technology. The FPGA under development is a 32*32 logic block array, equivalent to {approx} 25 k gates, in 0.13 {mu}m CMOS. The irradiation test results obtained in the CMOS 0.25 {mu}m technology demonstrate good robustness of the circuit up to an LET (Linear Energy Transfer) of 79.6 cm{sup 2}*MeV/mg, which make it suitable for the target environment. The CMOS 0.13 {mu}m circuit has showed robustness to an LET of 37.4 cm{sup 2}*MeV/mg in the static test mode and has increased sensitivity in the dynamic test mode. This work focused also on the research for an SEU-robust register in both the mentioned technologies. The SEU-robust register is employed as a user data flip-flop in the FPGA and PLD designs and as a configuration cell as well in the FPGA design.

Design of digital logic control for accelerator magnet power supply

International Nuclear Information System (INIS)

Long Fengli; Hu Wei; Cheng Jian

2008-01-01

For the accelerator magnet power supply, usually the Programmable Logic Controller (PLC) is used to server as the controller for logic protection and control. Along with the development of modern accelerator technology, it is a trend to use fully-digital control to the magnet power supply. It is possible to integrate the logic control part into the digital control component of the power supply, for example, the Field Programmable Gate Array (FPGA). The paper introduces to different methods which are designed for the logic protection and control for accelerator magnet power supplies with the FPGA as the control component. (authors)

Programmable logic control applied to a coal preparation plant complex

Energy Technology Data Exchange (ETDEWEB)

Krahenbil, L W

1979-02-01

The programmable Logic Controller (PLC), at its present stage of evolution, is now considered as a mature control system. The PLC combines the solid-state reliability of hard-wired logic and computer control systems with the simplicity of a relay ladder logic. Relay symbolic programming through a function-oriented keyboard provides a means which plant personnel can easily become accoustomed to work with. In a large coal facility, it is shown that the control engineer can provide improved control flexibility with the advanced capabilities of the PLC.

Fully digital routing logic for single-photon avalanche diode arrays in highly efficient time-resolved imaging

Science.gov (United States)

Cominelli, Alessandro; Acconcia, Giulia; Ghioni, Massimo; Rech, Ivan

2018-03-01

Time-correlated single-photon counting (TCSPC) is a powerful optical technique, which permits recording fast luminous signals with picosecond precision. Unfortunately, given its repetitive nature, TCSPC is recognized as a relatively slow technique, especially when a large time-resolved image has to be recorded. In recent years, there has been a fast trend toward the development of TCPSC imagers. Unfortunately, present systems still suffer from a trade-off between number of channels and performance. Even worse, the overall measurement speed is still limited well below the saturation of the transfer bandwidth toward the external processor. We present a routing algorithm that enables a smart connection between a 32×32 detector array and five shared high-performance converters able to provide an overall conversion rate up to 10 Gbit/s. The proposed solution exploits a fully digital logic circuit distributed in a tree structure to limit the number and length of interconnections, which is a major issue in densely integrated circuits. The behavior of the logic has been validated by means of a field-programmable gate array, while a fully integrated prototype has been designed in 180-nm technology and analyzed by means of postlayout simulations.

Programming Programmable Logic Controller. High-Technology Training Module.

Science.gov (United States)

Lipsky, Kevin

This training module on programming programmable logic controllers (PLC) is part of the memory structure and programming unit used in a packaging systems equipment control course. In the course, students assemble, install, maintain, and repair industrial machinery used in industry. The module contains description, objectives, content outline,…

Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

Energy Technology Data Exchange (ETDEWEB)

Zhang, X.; Wan, C.H., E-mail: wancaihua@iphy.ac.cn; Yuan, Z.H.; Fang, C.; Kong, W.J.; Wu, H.; Zhang, Q.T.; Tao, B.S.; Han, X.F., E-mail: xfhan@iphy.ac.cn

2017-04-15

Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices. - Highlights: • Experimental demonstration of spin logic cell based on spin Hall effect. • Five logic functions are realized in a single logic cell. • The logic cell is reprogrammable. • Information in the cell is symmetry-protected. • The logic cell can be easily expanded to logic gate array.

Programmable cellular arrays. Faults testing and correcting in cellular arrays

International Nuclear Information System (INIS)

Cercel, L.

1978-03-01

A review of some recent researches about programmable cellular arrays in computing and digital processing of information systems is presented, and includes both combinational and sequential arrays, with full arbitrary behaviour, or which can realize better implementations of specialized blocks as: arithmetic units, counters, comparators, control systems, memory blocks, etc. Also, the paper presents applications of cellular arrays in microprogramming, in implementing of a specialized computer for matrix operations, in modeling of universal computing systems. The last section deals with problems of fault testing and correcting in cellular arrays. (author)

Life Cycle V and V Process for Hardware Description Language Programs of Programmable Logic Device-based Instrumentation and Control Systems

International Nuclear Information System (INIS)

Cha, K. H.; Lee, D. Y.

2010-01-01

Programmable Logic Device (PLD), especially Complex PLD (CPLD) or Field Programmable Logic Array (FPGA), has been growing in interest in nuclear Instrumentation and Control (I and C) applications. PLD has been applied to replace an obsolete analog device or old-fashioned microprocessor, or to develop digital controller, subsystem or overall system on hardware aspects. This is the main reason why the PLD-based I and C design provides higher flexibility than the analog-based one, and the PLD-based I and C systems shows better real-time performance than the processor-based I and C systems. Due to the development of the PLD-based I and C systems, their nuclear qualification has been issued in the nuclear industry. Verification and Validation (V and V) is one of necessary qualification activities when a Hardware Description Language (HDL) is used to implement functions of the PLD-based I and C systems. The life cycle V and V process, described in this paper, has been defined as satisfying the nuclear V and V requirements, and it has been applied to verify Correctness, Completeness, and Consistency (3C) among design outputs in a safety-grade programmable logic controller and a safety-critical data communication system. Especially, software engineering techniques such as the Fagan Inspection, formal verification, simulated verification and automated testing have been defined for the life cycle V and V tasks of behavioral, structural, and physical design in VHDL

Programmable logic controllers in Heavy Water Project, Manuguru (Paper No. 3.4)

International Nuclear Information System (INIS)

Gupta, S.C.; Bhaskar, R.; Maiti, A.; Venkatesu, G.; Satish, P.; Goel, R.K.

1992-01-01

Enhancement to plant operational flexibility has been achieved in Heavy Water Project, Manuguru by installing programmable logic controllers for its control equipment. The earlier sulfide based Heavy Water Plant, Kota is using relay logic and diode based program-matrix for binary controls. Performance improvement and advantages of PLC and experience in its operation are described. (author). 3 refs

Integrated plant automation using programmable logic controllers

International Nuclear Information System (INIS)

Qureshi, S.A.

2002-01-01

In the world of automation the Programmable Logic Controller (PLC) has became for control. It now not only replaces the earlier relay logic controls but also has taken over many additional control functions. Initially the PLC was used to replace relay logic, but is ever-increasing range of functions means that it is found in many and more complex applications. As the structure of the PLC is based on the same principles as those employed in computer architecture, it is capable of performance not only relay switching tasks, but also other applications such as counting, calculating, comparing and the processing of analogue signals. Due to the simplicity of entering and modifying the programmed instructions to suit the requirements of the process under control, the PLC is truly a versatile and flexible device that can be employed easily and efficiently to repeatedly control tasks that vary in nature and complexes. A photograph of the Siemens S-5 95U. To illustrate the advantage of using a PLC over a traditional relay logic system, consider a control system with 20 input/output points. This assembly could comprise 60-80 relays, some counter/timers and a great deal of wiring. This assembly would be cumbersome with a power consumption of 30-40VA. A considerable time would be required to design, test and commission the assembly and once it is in full working order any desired modification, even of minor nature, could require major hardware changes. (author)

Universal Programmable Logic Controller Software

International Nuclear Information System (INIS)

Mohd Arif Hamzah; Azhar Shamsudin; Fadil Ismail; Muhammad Nor Atan; Anwar Abdul Rahman

2013-01-01

Programmable Logic Controller (PLC) is an electronic hardware which is widely used in manufacturing or processing industries. It is also serve as the main control system hardware to run the production and manufacturing process. There are more than ten (10) well known company producing PLC hardware, with their own specialties, including the method of programming and language used. Malaysia Nuclear Agency have various plant and equipment, runs and control by PLC, such as Mintex Sinagama Plant, Alurtron Plant, and few laboratory equipment. Since all the equipment and plant are equipped with various brand or different manufacture of PLC, it creates difficulties to the supporting staff to master the control program. The same problems occur for new application of this hardware, since there no policies to purchase only one specific brand of PLC. (author)

The impact of software and CAE tools on SEU in field programmable gate arrays

International Nuclear Information System (INIS)

Katz, R.; Wang, J.; McCollum, J.; Cronquist, B.

1999-01-01

Field programmable gate array (FPGA) devices, heavily used in spacecraft electronics, have grown substantially in size over the past few years, causing designers to work at a higher conceptual level, with computer aided engineering (CAE) tools synthesizing and optimizing the logic from a description. It is shown that the use of commercial-off-the-shelf (COTS) CAE tools can produce unreliable circuit designs when the device is used in a radiation environment and a flip-flop is upset. At a lower level, software can be used to improve the SEU performance of a flip-flop, exploiting the configurable nature of FPGA technology and on-chip delay, parasitic resistive, and capacitive circuit elements

Logical Qubit in a Linear Array of Semiconductor Quantum Dots

Directory of Open Access Journals (Sweden)

Cody Jones

2018-06-01

Full Text Available We design a logical qubit consisting of a linear array of quantum dots, we analyze error correction for this linear architecture, and we propose a sequence of experiments to demonstrate components of the logical qubit on near-term devices. To avoid the difficulty of fully controlling a two-dimensional array of dots, we adapt spin control and error correction to a one-dimensional line of silicon quantum dots. Control speed and efficiency are maintained via a scheme in which electron spin states are controlled globally using broadband microwave pulses for magnetic resonance, while two-qubit gates are provided by local electrical control of the exchange interaction between neighboring dots. Error correction with two-, three-, and four-qubit codes is adapted to a linear chain of qubits with nearest-neighbor gates. We estimate an error correction threshold of 10^{-4}. Furthermore, we describe a sequence of experiments to validate the methods on near-term devices starting from four coupled dots.

Programmable logic controller performance enhancement by field programmable gate array based design.

Science.gov (United States)

Patel, Dhruv; Bhatt, Jignesh; Trivedi, Sanjay

2015-01-01

PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx's Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported. Copyright © 2014 ISA. Published by Elsevier Ltd. All rights reserved.

Application of programmable logic controller in nuclear experiments

International Nuclear Information System (INIS)

Ponikvar, D.

1991-09-01

The applicability of programmable logic controller (PLC) in nuclear experiments was studied on an example that simulated the monitoring and control of an ion beam in an accelerator. Using infrared and laser light, a comparison was made between the complexity and suitability of PLC compared to a setup using a personal computer. The experiments are described in detail. The routines for registration of signals from appropriate sensors and for control of the stepper monitor were written in quick BASIC. (author). 5 figs

Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms

Energy Technology Data Exchange (ETDEWEB)

Pruttivarasin, Thaned, E-mail: thaned.pruttivarasin@riken.jp [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Katori, Hidetoshi [Quantum Metrology Laboratory, RIKEN, Wako-shi, Saitama 351-0198 (Japan); Innovative Space-Time Project, ERATO, JST, Bunkyo-ku, Tokyo 113-8656 (Japan); Department of Applied Physics, Graduate School of Engineering, The University of Tokyo, Bunkyo-ku, Tokyo 113-8656 (Japan)

2015-11-15

We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 transistor-transistor logic (TTL) channels with a timing resolution of 40 ns and contains a built-in 100 MHz frequency counter for counting electrical pulses from a photo-multiplier tube. There are 16 independent direct-digital-synthesizers RF sources with fast (rise-time of ∼60 ns) amplitude switching and sub-mHz frequency tuning from 0 to 800 MHz.

The Programmable Logic Controller and its application in nuclear reactor systems

International Nuclear Information System (INIS)

Palomar, J.; Wyman, R.

1993-09-01

This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out

The Programmable Logic Controller and its application in nuclear reactor systems

Energy Technology Data Exchange (ETDEWEB)

Palomar, J.; Wyman, R. [Lawrence Livermore National Lab., CA (United States)

1993-09-01

This document provides recommendations to guide reviewers in the application of Programmable Logic Controllers (PLCS) to the control, monitoring and protection of nuclear reactors. The first topics addressed are system-level design issues, specifically including safety. The document then discusses concerns about the PLC manufacturing organization and the protection system engineering organization. Supplementing this document are two appendices. Appendix A summarizes PLC characteristics. Specifically addressed are those characteristics that make the PLC more suitable for emergency shutdown systems than other electrical/electronic-based systems, as well as characteristics that improve reliability of a system. Also covered are PLC characteristics that may create an unsafe operating environment. Appendix B provides an overview of the use of programmable logic controllers in emergency shutdown systems. The intent is to familiarize the reader with the design, development, test, and maintenance phases of applying a PLC to an ESD system. Each phase is described in detail and information pertinent to the application of a PLC is pointed out.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

International Nuclear Information System (INIS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-01-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Roles of programmable logic controllers in fuel reprocessing plants

International Nuclear Information System (INIS)

Mishra, Hrishikesh; Balakrishnan, V.P.; Pandya, G.J.

1999-01-01

Fuel charging facility is another application of Programmable Logic Controllers (PLC) in fuel reprocessing plants, that involves automatic operation of fuel cask dolly, charging motor, pneumatic doors, clutches, clamps, stepper motors and rod pushers in a pre-determined sequence. Block diagram of ACF system is given for underlining the scope of control and interlocks requirements involved for automation of the fuel charging system has been provided for the purpose at KARP Plant, Kalpakkam

Final Report and Documentation for the PLD11 Multipurpose Programmable Logic VME Board Design

International Nuclear Information System (INIS)

Hutchinson, Robert L.; Pierson, Lyndon G.; Robertson, Perry J.; Tarman, Thomas D.; Witzke, Edward L.

1999-01-01

The PLD11 board is a 9U VME board containing 11 Altera 10K100 Programmable Logic Devices, controlled impedance clock tree, VME interface, programming inteface, 0C3 (155 Mbps) interface and serial port. The 11 Altera 10K100 Programmable Logic Devices arranged to provide four 96 bit wide buses for a total of 384 parallel digital data lines in and out of the board that can operate up to 100 Mhz for a aggrigate throughput of 38.4 Gpbs. The 14.44'' X 15.75'' board has over 1.1 million programmable gates that can be programmed through a serial interace. The board contains a clock reference and 50 ohm clock distribution tree that can drive each of the eleven 10K100 devices with two critically timed clock references. Five external clock references can be used to drive five additional PLD 11 boards for a total of six boards operating all from the same synchronous clock reference. A system of six boards provides just under 7 million programmable gates

Technologies for faults diagnosis of FPGA logic blocks

Directory of Open Access Journals (Sweden)

C. U. Ngene

2012-08-01

Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

A new fast and programmable trigger logic

International Nuclear Information System (INIS)

Fucci, A.; Amendolia, S.R.; Bertolucci, E.; Bottigli, U.; Bradaschia, C.; Foa, L.; Giazotto, A.; Giorgi, M.; Givoletti, M.; Lucardesi, P.; Menzione, A.; Passuello, D.; Quaglia, M.; Ristori, L.; Rolandi, L.; Salvadori, P.; Scribano, A.; Stanga, R.; Stefanini, A.; Vincelli, M.L.

1977-01-01

The NA1 (FRAMM) experiment, under construction for the CERN-SPS North Area, deals with more than 1000 counter signals which have to be combined together in order to build sophisticated and highly selective triggers. These requirements have led to the development of a low cost, combinatorial, fast electronics which can replace, in an advantageous way the standard NIM electronics at the trigger level. The essential performances of the basic circuit are: 1) programmability of any desired logical expression; 2) trigger time independent of the chosen expression; 3) reduced cost and compactness due to the use of commercial RAMs, PROMs, and PLAs; 4) short delay, less than 20 ns, between input and output pulses. (Auth.)

A multi-channel scaler designed with programmable logic device

International Nuclear Information System (INIS)

Sun Yongjie; Li Cheng; Xing Tao; Zhang Junjie

2004-01-01

This scaler used programmable logic device is a design for the electronics of telescope system of the beam. The scaler can scale 30 ECL inputs at the same time. With the EPP (Enhanced Parallel Port) modes of the Parallel Port, the transmitted rate of data is 2 MB/s. This scaler can be used in the position system of MWPC (Multi-Wires Proportional Chamber). Tested with particles of 5 x 10 3 /s, the scaler gives a credible and stable result. (authors)

Introducing Programmable Logic to Undergraduate Engineering Students in a Digital Electronics Course

Science.gov (United States)

Todorovich, E.; Marone, J. A.; Vazquez, M.

2012-01-01

Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some…

Performance Testing Methodology for Safety-Critical Programmable Logic Controller

International Nuclear Information System (INIS)

Kim, Chang Ho; Oh, Do Young; Kim, Ji Hyeon; Kim, Sung Ho; Sohn, Se Do

2009-01-01

The Programmable Logic Controller (PLC) for use in Nuclear Power Plant safety-related applications is being developed and tested first time in Korea. This safety-related PLC is being developed with requirements of regulatory guideline and industry standards for safety system. To test that the quality of the developed PLC is sufficient to be used in safety critical system, document review and various product testings were performed over the development documents for S/W, H/W, and V/V. This paper provides the performance testing methodology and its effectiveness for PLC platform conducted by KOPEC

Fuzzy Logic Controller Design for Intelligent Robots

Directory of Open Access Journals (Sweden)

Ching-Han Chen

2017-01-01

Full Text Available This paper presents a fuzzy logic controller by which a robot can imitate biological behaviors such as avoiding obstacles or following walls. The proposed structure is implemented by integrating multiple ultrasonic sensors into a robot to collect data from a real-world environment. The decisions that govern the robot’s behavior and autopilot navigation are driven by a field programmable gate array- (FPGA- based fuzzy logic controller. The validity of the proposed controller was demonstrated by simulating three real-world scenarios to test the bionic behavior of a custom-built robot. The results revealed satisfactorily intelligent performance of the proposed fuzzy logic controller. The controller enabled the robot to demonstrate intelligent behaviors in complex environments. Furthermore, the robot’s bionic functions satisfied its design objectives.

Programmable Logic Controllers for Systems of Automatic of the Level Crossing

Directory of Open Access Journals (Sweden)

Mieczyslaw Kornaszewski

2006-01-01

Full Text Available The railway crossings are vulnerable to incidence of high number of accidents often deadly. In order to face this problem, the modern systems of automatic of the level crossing have been introduced. These systems are based on Programmable Logic Controllers, which allow the designers to exploit self-control mechanisms, events acquiring, technical diagnostic which in turn enable remote control and acquisition of faults.

A Project-Based Learning Approach to Programmable Logic Design and Computer Architecture

Science.gov (United States)

Kellett, C. M.

2012-01-01

This paper describes a course in programmable logic design and computer architecture as it is taught at the University of Newcastle, Australia. The course is designed around a major design project and has two supplemental assessment tasks that are also described. The context of the Computer Engineering degree program within which the course is…

Management of Industrial Processes with Programmable Logic Controller

Directory of Open Access Journals (Sweden)

Marius Tufoi

2009-10-01

Full Text Available In a modern economy, automation (the control is primarily to raise the competitiveness of a product, either directly through price or quality, or indirectly through the improvement of working conditions of staff productive. The control of industrial processes involves the management of dynamic systems that have continuous states. These systems are described by differential equations and, in general, analog inputs and outputs. Management of these systems is achieved, in general, with classical automation, by automation or with analog computers which contains modules with input / output analog performance. If states, inputs and outputs of a system can be modeled using binary variables, then these systems can be driven with Programmable Logic Controller.

A Complementary Resistive Switch-based Crossbar Array Adder

OpenAIRE

Siemon, A.; Menzel, S.; Waser, R.; Linn, E.

2014-01-01

Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to...

Complex programmable logic device based alarm sequencer for nuclear power plants

International Nuclear Information System (INIS)

Khedkar, Ravindra; Solomon, J. Selva; KrishnaKumar, B.

2001-01-01

Complex Programmable Logic Device based Alarm Sequencer is an instrument, which detects alarms, memorizes them and displays the sequences of occurrence of alarms. It caters to sixteen alarm signals and distinguishes the sequence among any two alarms with a time resolution of 1 ms. The system described has been designed for continuous operation in process plants, nuclear power plants etc. The system has been tested and found to be working satisfactorily. (author)

Emergency Diesel: Safety-related instrumentation and control with programmable logic controllers

International Nuclear Information System (INIS)

Breidenich, G.; Luedtke, M.

2004-01-01

This report presents a new concept for the design of emergency diesel equipment protection circuits as a part of the safety related instrumentation in the nuclear power plant Biblis, units A and B. The concept was implemented with state of the art SIMATIC S7/316 programmable logic controllers (PLCs) and can be adapted to any system with high availability requirements (e.g. power plant turbines, aircraft engines, mining pumps etc). (orig.)

Stealth low-level manipulation of programmable logic controllers I/O by pin control exploitation

NARCIS (Netherlands)

Abbasi, A.; Hashemi, M.; Zambon, E.; Etalle, S.; Havarneanu, G.; Setola, R.; Nassopoulos, H.; Wolthusen, S.

2016-01-01

Input/OutputisthemechanismthroughwhichProgrammable Logic Controllers (PLCs) interact with and control the outside world. Particularly when employed in critical infrastructures, the I/O of PLCs has to be both reliable and secure. PLCs I/O like other embedded devices are controlled by a pin based

Application of complex programmable logic devices in memory radiation effects test system

International Nuclear Information System (INIS)

Li Yonghong; He Chaohui; Yang Hailiang; He Baoping

2005-01-01

The application of the complex programmable logic device (CPLD) in electronics is emphatically discussed. The method of using software MAX + plus II and CPLD are introduced. A new test system for memory radiation effects is established by using CPLD devices-EPM7128C84-15. The old test system's function are realized and, moreover, a number of small scale integrated circuits are reduced and the test system's reliability is improved. (authors)

Development of RPS trip logic based on PLD technology

International Nuclear Information System (INIS)

Choi, Jong Gyun; Lee, Dong Young

2012-01-01

The majority of instrumentation and control (I and C) systems in today's nuclear power plants (NPPs) are based on analog technology. Thus, most existing I and C systems now face obsolescence problems. Existing NPPs have difficulty in repairing and replacing devices and boards during maintenance because manufacturers no longer produce the analog devices and boards used in the implemented I and C systems. Therefore, existing NPPs are replacing the obsolete analog I and C systems with advanced digital systems. New NPPs are also adopting digital I and C systems because the economic efficiencies and usability of the systems are higher than the analog I and C systems. Digital I and C systems are based on two technologies: a microprocessor based system in which software programs manage the required functions and a programmable logic device (PLD) based system in which programmable logic devices, such as field programmable gate arrays, manage the required functions. PLD based systems provide higher levels of performance compared with microprocessor based systems because PLD systems can process the data in parallel while microprocessor based systems process the data sequentially. In this research, a bistable trip logic in a reactor protection system (RPS) was developed using very high speed integrated circuits hardware description language (VHDL), which is a hardware description language used in electronic design to describe the behavior of the digital system. Functional verifications were also performed in order to verify that the bistable trip logic was designed correctly and satisfied the required specifications. For the functional verification, a random testing technique was adopted to generate test inputs for the bistable trip logic.

Ghost in the PLC: stealth on-the-fly manipulation of programmable logic controllers’ I/O

NARCIS (Netherlands)

Abbasi, Ali

2016-01-01

Programmable Logic Controllers (PLCs) are a family of embedded devices used for physical process control. Similar to other embedded devices, PLCs are vulnerable to cyber attacks. Because they are used to control the physical processes of critical infrastructures, compromised PLCs constitute a

Programmable logic controller based synchronous motor excitation system

Directory of Open Access Journals (Sweden)

Janda Žarko

2011-01-01

Full Text Available This paper presents a 3.5 MW synchronous motor excitation system reconstruction. In the proposed solution programmable logic controller is used to control motor, which drives the turbo compressor. Comparing to some other solutions that are used in similar situations, the proposed solution is superior due to its flexibility and usage of mass-production hardware. Moreover, the implementation of PLC enables easy integration of the excitation system with the other technological processes in the plant as well as in the voltage regulation of 'smart grid' system. Also, implementation of various optimization algorithms can be done comfortably and it does not require additional investment in hardware. Some experimental results that depict excitation current during motor start-up, as well as, measured static characteristics of the motor, were presented.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Science.gov (United States)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment

Programmable - logic equipment for ultrasound periodic inspections of reactor pressure vessels

International Nuclear Information System (INIS)

Haniger, L.

1980-01-01

Two alternatives are presented of programmable logic corresponding to the 2nd generation of the apparatus for performing periodic ultrasonic inspections of power reactor pressure vessels and a solution is outlined of inspecting the circumferential weld on the pressure vessel head. The apparatus will allow using any measuring head taken into consideration for operational inspection. Command words are taken from a punched type reader. Czechoslovak made RAM memories are used. The algorithm of instrument function is supposed to be controlled by a microprocessor as soon as necessary preconditions for this technology are created in Czechoslovakia

Application of Field programmable Gate Array to Digital Signal ...

African Journals Online (AJOL)

Journal of Research in National Development ... This work shows how one parallel technology Field Programmable Gate Array (FPGA) can be applied to digital signal processing problem to increase computational speed. ... In this research work FPGA typically exploits parallelism because FPGA is a parallel device. With the ...

G(sup 4)FET Implementations of Some Logic Circuits

Science.gov (United States)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration

Reliability concerns with logical constants in Xilinx FPGA designs

Energy Technology Data Exchange (ETDEWEB)

Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul [Los Alamos National Laboratory; Morgan, Keith [Los Alamos National Laboratory; Ostler, Patrick [Los Alamos National Laboratory; Allen, Greg [JPL; Swift, Gary [XILINX; Tseng, Chen W [XILINX

2009-01-01

In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.

A Soft Computing Approach to Crack Detection and Impact Source Identification with Field-Programmable Gate Array Implementation

Directory of Open Access Journals (Sweden)

Arati M. Dixit

2013-01-01

Full Text Available The real-time nondestructive testing (NDT for crack detection and impact source identification (CDISI has attracted the researchers from diverse areas. This is apparent from the current work in the literature. CDISI has usually been performed by visual assessment of waveforms generated by a standard data acquisition system. In this paper we suggest an automation of CDISI for metal armor plates using a soft computing approach by developing a fuzzy inference system to effectively deal with this problem. It is also advantageous to develop a chip that can contribute towards real time CDISI. The objective of this paper is to report on efforts to develop an automated CDISI procedure and to formulate a technique such that the proposed method can be easily implemented on a chip. The CDISI fuzzy inference system is developed using MATLAB’s fuzzy logic toolbox. A VLSI circuit for CDISI is developed on basis of fuzzy logic model using Verilog, a hardware description language (HDL. The Xilinx ISE WebPACK9.1i is used for design, synthesis, implementation, and verification. The CDISI field-programmable gate array (FPGA implementation is done using Xilinx’s Spartan 3 FPGA. SynaptiCAD’s Verilog Simulators—VeriLogger PRO and ModelSim—are used as the software simulation and debug environment.

Développement de circuits logiques programmables résistants aux alas logiques en technologie CMOS submicrométrique

CERN Document Server

Bonacini, Sandro; Kloukinas, Kostas

2007-01-01

The electronics associated to the particle detectors of the Large Hadron Collider (LHC), under construction at CERN, will operate in a very harsh radiation environment. Most of the microelectronics components developed for the first generation of LHC experiments have been designed with very precise experiment-specific goals and are hardly adaptable to other applications. Commercial Off-The-Shelf (COTS) components cannot be used in the vicinity of particle collision due to their poor radiation tolerance. This thesis is a contribution to the effort to cover the need for radiation-tolerant SEU-robust programmable components for application in High Energy Physics (HEP) experiments. Two components are under development: a Programmable Logic Device (PLD) and a Field-Programmable Gate Array (FPGA). The PLD is a fuse-based, 10-input, 8-I/O general architecture device in 0.25 micron CMOS technology. The FPGA under development is instead a 32x32 logic block array, equivalent to ~25k gates, in 0.13 micron CMOS. This wor...

Design and FPGA-implementation of an improved adaptive fuzzy logic controller for DC motor speed control

Directory of Open Access Journals (Sweden)

E.A. Ramadan

2014-09-01

Full Text Available This paper presents an improved adaptive fuzzy logic speed controller for a DC motor, based on field programmable gate array (FPGA hardware implementation. The developed controller includes an adaptive fuzzy logic control (AFLC algorithm, which is designed and verified with a nonlinear model of DC motor. Then, it has been synthesised, functionally verified and implemented using Xilinx Integrated Software Environment (ISE and Spartan-3E FPGA. The performance of this controller has been successfully validated with good tracking results under different operating conditions.

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

Science.gov (United States)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

Project W-058 monitor and control system logic

International Nuclear Information System (INIS)

ROBERTS, J.B.

1999-01-01

This supporting document contains the printout of the control logic for the Project W-058 Monitor and Control System, as developed by Programmable Control Services, Inc. The logic is arranged in five appendices, one for each programmable logic controller console

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Nolida Yussup; Maslina Mohd Ibrahim; Lojius Lombigit; Nur Aira Abdul Rahman; Muhammad Rawi Mohamed Zin

2013-01-01

Full-text: Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed. (author)

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

International Nuclear Information System (INIS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-01-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed

Design of a Tritium-in-air-monitor using field programmable gate arrays

International Nuclear Information System (INIS)

McNelles, Phillip; Lu, Lixuan

2015-01-01

Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

Project-Based Learning in Programmable Logic Controller

Science.gov (United States)

Seke, F. R.; Sumilat, J. M.; Kembuan, D. R. E.; Kewas, J. C.; Muchtar, H.; Ibrahim, N.

2018-02-01

Project-based learning is a learning method that uses project activities as the core of learning and requires student creativity in completing the project. The aims of this study is to investigate the influence of project-based learning methods on students with a high level of creativity in learning the Programmable Logic Controller (PLC). This study used experimental methods with experimental class and control class consisting of 24 students, with 12 students of high creativity and 12 students of low creativity. The application of project-based learning methods into the PLC courses combined with the level of student creativity enables the students to be directly involved in the work of the PLC project which gives them experience in utilizing PLCs for the benefit of the industry. Therefore, it’s concluded that project-based learning method is one of the superior learning methods to apply on highly creative students to PLC courses. This method can be used as an effort to improve student learning outcomes and student creativity as well as to educate prospective teachers to become reliable educators in theory and practice which will be tasked to create qualified human resources candidates in order to meet future industry needs.

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA; Desenvolvimento de sistema de protecao para reator nuclear de pesquisa baseado em Field Programmable Gate Array - FPGA

Energy Technology Data Exchange (ETDEWEB)

Martins, Roque Hudson da Silva

2016-07-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

A Modular Approach to Arithmetic and Logic Unit Design on a Reconfigurable Hardware Platform for Educational Purpose

Science.gov (United States)

Oztekin, Halit; Temurtas, Feyzullah; Gulbag, Ali

The Arithmetic and Logic Unit (ALU) design is one of the important topics in Computer Architecture and Organization course in Computer and Electrical Engineering departments. There are ALU designs that have non-modular nature to be used as an educational tool. As the programmable logic technology has developed rapidly, it is feasible that ALU design based on Field Programmable Gate Array (FPGA) is implemented in this course. In this paper, we have adopted the modular approach to ALU design based on FPGA. All the modules in the ALU design are realized using schematic structure on Altera's Cyclone II Development board. Under this model, the ALU content is divided into four distinct modules. These are arithmetic unit except for multiplication and division operations, logic unit, multiplication unit and division unit. User can easily design any size of ALU unit since this approach has the modular nature. Then, this approach was applied to microcomputer architecture design named BZK.SAU.FPGA10.0 instead of the current ALU unit.

Introduction to embedded system design using field programmable gate arrays

CERN Document Server

Dubey, Rahul

2009-01-01

Offers information on the use of field programmable gate arrays (FPGAs) in the design of embedded systems. This text considers a hypothetical robot controller as an embedded application and weaves around it related concepts of FPGA-based digital design. It is suitable for both students and designers who have worked with microprocessors.

Saltwell PIC Skid Programmable Logic Controller (PLC) Software Configuration Management Plan

International Nuclear Information System (INIS)

KOCH, M.R.

1999-01-01

This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell PIC Skids as required by LMH-PRO-309/Rev. 0, Computer Software Quality Assurance, Section 2.6, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell PIC Skid Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell PIC Skid PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

Local and Remote Laboratory User Experimentation Access using Digital Programmable Logic

Directory of Open Access Journals (Sweden)

Ian A Grout

2005-06-01

Full Text Available This paper will discuss the structure and operation of a programmable logic based experimentation arrangement that is suitable for both local and remote teaching and learning scenarios targeting electronic and microelectronic circuit design and test principles. With this experimentation arrangement, the ability to provide both local and Internet based “remote” access for the student and the teacher can provide a number of advantages where physical laboratory accessibility is limited and/or the learning experience must be undertaken with one or more of the parties remotely based. The paper concentrates on the design and example use of a system developed within the University of Limerick.

A synchronous serial bus for multidimensional array acoustic logging tool

Science.gov (United States)

Men, Baiyong; Ju, Xiaodong; Lu, Junqiang; Qiao, Wenxiao

2016-12-01

In high-temperature and spatial borehole applications, a distributed structure is employed in a multidimensional array acoustic logging tool (MDALT) based on a phased array technique for electronic systems. However, new challenges, such as synchronous multichannel data acquisition, multinode real-time control and bulk data transmission in a limited interval, have emerged. To address these challenges, we developed a synchronous serial bus (SSB) in this study. SSB works in a half-duplex mode via a master-slave architecture. It also consists of a single master, several slaves, a differential clock line and a differential data line. The clock line is simplex, whereas the data line is half-duplex and synchronous to the clock line. A reliable communication between the master and the slaves with real-time adjustment of synchronisation is achieved by rationally designing the frame format and protocol of communication and by introducing a scramble code and a Hamming error-correcting code. The control logic of the master and the slaves is realized in field programmable gate array (FPGA) or complex programmable logic device (CPLD). The clock speed of SSB is 10 MHz, the effective data rate of the bulk data transmission is over 99%, and the synchronous errors amongst the slaves are less than 10 ns. Room-temperature test, high-temperature test (175 °C) and field test demonstrate that the proposed SSB is qualified for MDALT.

Biological applications of an LCoS-BASED PROGRAMMABLE ARRAY MICROSCOPE (PAM)

NARCIS (Netherlands)

Hagen, G.M.; Caarls, W.; Thomas, M.; Hill, A.; Lidke, K.A.; Rieger, B.; Fritsch, C.; Van Geest, B.; Jovin, T.M.; Arndt-Jovin, D.J.

2007-01-01

We report on a new generation, commercial prototype of a programmable array optical sectioning fluorescence microscope (PAM) for rapid, light efficient 3D imaging of living specimens. The stand-alone module, including light source(s) and detector(s), features an innovative optical design and a

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

National Research Council Canada - National Science Library

O'Connor, Joseph E

2008-01-01

...) continuously develops new design and education resources for students. One area of focus for students in the Power Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA...

A test system and supervisory control and data acquisition application with programmable logic controller for thermoelectric generators

International Nuclear Information System (INIS)

Ahiska, Rasit; Mamur, Hayati

2012-01-01

Highlights: ► A new TEG test measurement system with the PLC has been carried out. ► A new SCADA program has been written and tested for the test measurement system. ► An operator panel has been used for monitoring to the instant TEG data. ► All of the measurement data of TEG have been aggregated in the system. - Abstract: In this study, a new test measurement system and supervisory control and data acquisition application with programmable logic controller has been carried out to be enable the collection of the data of thermoelectric generator for the usage of thermoelectric modules as thermoelectric generator. During the production of the electric energy from the thermoelectric generator, the temperatures of the surfaces of the thermoelectric generator, current–voltage values obtained from output of the thermoelectric generator, hot and cold flows have been measured by the newly established system instantly. All these data have been monitored continuously from the computer and recorded by a supervisory control and data acquisition program. At the same time, in environments where there was no computer, an operator panel with the ability to communicate with the programmable logic controller has been added for the monitoring of the instant thermoelectric generator data. All of the measurement data of the thermoelectric generator have been aggregated in the new test measurement and supervisory control and data acquisition system. The setup test measurement system has been implemented on the thermoelectric generator system with about 10 W. Thermoelectric generators, Altec-GM-1 brand-coded have been examined by the new proposed test measurement system and the values of maximum power and thermoelectric generator efficiency were calculated by the programmable logic controller. When the obtained results were compared with the datasheets, the relative error for the maximum power was around 4% and the value for efficiency was below 3%.

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

Energy Technology Data Exchange (ETDEWEB)

Ahmed, Ibrahim [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of); Jung, Jaecheon, E-mail: jcjung@kings.ac.kr [Department of Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, 658-91 Haemaji-ro, Seosang-myeon, Ulju-gun, Ulsan 45014 (Korea, Republic of); Heo, Gyunyoung [Department of Nuclear Engineering, Kyung Hee University, 1732 Deogyeong-daero, Giheung-gu, Yongin-si, Gyeonggi-do 17104 (Korea, Republic of)

2017-06-15

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Design verification enhancement of field programmable gate array-based safety-critical I&C system of nuclear power plant

International Nuclear Information System (INIS)

Ahmed, Ibrahim; Jung, Jaecheon; Heo, Gyunyoung

2017-01-01

Highlights: • An enhanced, systematic and integrated design verification approach is proposed for V&V of FPGA-based I&C system of NPP. • RPS bistable fixed setpoint trip algorithm is designed, analyzed, verified and discussed using the proposed approaches. • The application of integrated verification approach simultaneously verified the entire design modules. • The applicability of the proposed V&V facilitated the design verification processes. - Abstract: Safety-critical instrumentation and control (I&C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. However, safety analysis for FPGA-based I&C systems, and verification and validation (V&V) assessments still remain important issues to be resolved, which are now become a global research point of interests. In this work, we proposed a systematic design and verification strategies from start to ready-to-use in form of model-based approaches for FPGA-based reactor protection system (RPS) that can lead to the enhancement of the design verification and validation processes. The proposed methodology stages are requirement analysis, enhanced functional flow block diagram (EFFBD) models, finite state machine with data path (FSMD) models, hardware description language (HDL) code development, and design verifications. The design verification stage includes unit test – Very high speed integrated circuit Hardware Description Language (VHDL) test and modified condition decision coverage (MC/DC) test, module test – MATLAB/Simulink Co-simulation test, and integration test – FPGA hardware test beds. To prove the adequacy of the proposed

Reprogrammable logic in memristive crossbar for in-memory computing

Science.gov (United States)

Cheng, Long; Zhang, Mei-Yun; Li, Yi; Zhou, Ya-Xiong; Wang, Zhuo-Rui; Hu, Si-Yu; Long, Shi-Bing; Liu, Ming; Miao, Xiang-Shui

2017-12-01

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

Real-time object tracking system based on field-programmable gate array and convolution neural network

Directory of Open Access Journals (Sweden)

Congyi Lyu

2016-12-01

Full Text Available Vision-based object tracking has lots of applications in robotics, like surveillance, navigation, motion capturing, and so on. However, the existing object tracking systems still suffer from the challenging problem of high computation consumption in the image processing algorithms. The problem can prevent current systems from being used in many robotic applications which have limitations of payload and power, for example, micro air vehicles. In these applications, the central processing unit- or graphics processing unit-based computers are not good choices due to the high weight and power consumption. To address the problem, this article proposed a real-time object tracking system based on field-programmable gate array, convolution neural network, and visual servo technology. The time-consuming image processing algorithms, such as distortion correction, color space convertor, and Sobel edge, Harris corner features detector, and convolution neural network were redesigned using the programmable gates in field-programmable gate array. Based on the field-programmable gate array-based image processing, an image-based visual servo controller was designed to drive a two degree of freedom manipulator to track the target in real time. Finally, experiments on the proposed system were performed to illustrate the effectiveness of the real-time object tracking system.

Programmable logic controller (PLC) for safety systems of nuclear plants

International Nuclear Information System (INIS)

Sen, S.K.; Karmakar, G.; Joseph, Jose; Patil, R.K.

2002-01-01

Full text: A programmable logic controller (PLC) has been developed by RCnD, BARC for use in the safety critical systems in nuclear power plants. This PLC uses qualified hardware developed in RCnD for use in NPP. The programming software conforms to IEC-61131 part 3. The application programming is done on function block diagram (FBD) editor and the FBD is automatically converted into code in high level language (C / C++). This feature makes the application easily decipherable and therefore easily subjected to reviews and other validation techniques. The key to make quality software for use in nuclear systems is to enforce various standards in the design and development of the software, something, which is not possible to do with a commercially available PLC. This PLC with its software completely transparent lends itself to rigorous verification and validation easily

Molecular implementation of simple logic programs.

Science.gov (United States)

Ran, Tom; Kaplan, Shai; Shapiro, Ehud

2009-10-01

Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

Developing and Optimising the Use of Logic Models in Systematic Reviews: Exploring Practice and Good Practice in the Use of Programme Theory in Reviews.

Science.gov (United States)

Kneale, Dylan; Thomas, James; Harris, Katherine

2015-01-01

Logic models are becoming an increasingly common feature of systematic reviews, as is the use of programme theory more generally in systematic reviewing. Logic models offer a framework to help reviewers to 'think' conceptually at various points during the review, and can be a useful tool in defining study inclusion and exclusion criteria, guiding the search strategy, identifying relevant outcomes, identifying mediating and moderating factors, and communicating review findings. In this paper we critique the use of logic models in systematic reviews and protocols drawn from two databases representing reviews of health interventions and international development interventions. Programme theory featured only in a minority of the reviews and protocols included. Despite drawing from different disciplinary traditions, reviews and protocols from both sources shared several limitations in their use of logic models and theories of change, and these were used almost unanimously to solely depict pictorially the way in which the intervention worked. Logic models and theories of change were consequently rarely used to communicate the findings of the review. Logic models have the potential to be an aid integral throughout the systematic reviewing process. The absence of good practice around their use and development may be one reason for the apparent limited utility of logic models in many existing systematic reviews. These concerns are addressed in the second half of this paper, where we offer a set of principles in the use of logic models and an example of how we constructed a logic model for a review of school-based asthma interventions.

Development of a protection system for research reactor based in Field Programmable Gate Array - FPGA

International Nuclear Information System (INIS)

Martins, Roque Hudson da Silva

2016-01-01

This study presents a implementation purpose of a protection system for research nuclear reactors by using a programed device FPGA (Field Programmable Gate Array). As well as logic protection method involved on an automatic shutdown (TRIP) of a reactor, that ensure the security on such systems. These new control and operation mechanics are developed to guarantee that the security limits of a power plant are not exceeded, these mechanics can work isolated or in groups to safe guard the security levels. For this implementation to be completed, there will be presented the main aspects and concepts referred to protection systems, mostly about research nuclear reactors, with some applications terms exposed. The system proposed at this paper was developed following the VHDL (Very High Speed Integrated Circuits) hardware describing language, and the Modelsim software from Altera Software to program the automatic turning off routines, and hypothetical simulations for such. The results show that for every software application for supporting nuclear reactors, like security devices, they have to meet the IEC 60880 criteria. This paper have great importance, seeing that nuclear reactor security systems, are a basic element for ensure the reactor security. (author)

Programmable logic controller optical fibre sensor interface module

Science.gov (United States)

Allwood, Gary; Wild, Graham; Hinckley, Steven

2011-12-01

Most automated industrial processes use Distributed Control Systems (DCSs) or Programmable Logic Controllers (PLCs) for automated control. PLCs tend to be more common as they have much of the functionality of DCSs, although they are generally cheaper to install and maintain. PLCs in conjunction with a human machine interface form the basis of Supervisory Control And Data Acquisition (SCADA) systems, combined with communication infrastructure and Remote Terminal Units (RTUs). RTU's basically convert different sensor measurands in to digital data that is sent back to the PLC or supervisory system. Optical fibre sensors are becoming more common in industrial processes because of their many advantageous properties. Being small, lightweight, highly sensitive, and immune to electromagnetic interference, means they are an ideal solution for a variety of diverse sensing applications. Here, we have developed a PLC Optical Fibre Sensor Interface Module (OFSIM), in which an optical fibre is connected directly to the OFSIM located next to the PLC. The embedded fibre Bragg grating sensors, are highly sensitive and can detect a number of different measurands such as temperature, pressure and strain without the need for a power supply.

General purpose programmable accelerator board

Science.gov (United States)

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

Logic synthesis for FPGA-based finite state machines

CERN Document Server

Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

2016-01-01

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

Special Technology Area Review on Field Programmable Gate Arrays (FPGAs) For Military Applications

National Research Council Canada - National Science Library

2005-01-01

...) on Field Programmable Gate Arrays (FPGAs) for Military Applications on August 3-4, 2004 at the Naval Postgraduate School in Monterey, California to address issues relevant to the use of this technology in military systems...

Analysis and research on Maximum Power Point Tracking of Photovoltaic Array with Fuzzy Logic Control and Three-point Weight Comparison Method

Institute of Scientific and Technical Information of China (English)

LIN; Kuang-Jang; LIN; Chii-Ruey

2010-01-01

The Photovoltaic Array has a best optimal operating point where the array operating can obtain the maximum power.However, the optimal operating point can be compromised by the strength of solar radiation,angle,and by the change of environment and load.Due to the constant changes in these conditions,it has become very difficult to locate the optimal operating point by following a mathematical model.Therefore,this study will focus mostly on the application of Fuzzy Logic Control theory and Three-point Weight Comparison Method in effort to locate the optimal operating point of solar panel and achieve maximum efficiency in power generation. The Three-point Weight Comparison Method is the comparison between the characteristic curves of the voltage of photovoltaic array and output power;it is a rather simple way to track the maximum power.The Fuzzy Logic Control,on the other hand,can be used to solve problems that cannot be effectively dealt with by calculation rules,such as concepts,contemplation, deductive reasoning,and identification.Therefore,this paper uses these two kinds of methods to make simulation successively. The simulation results show that,the Three-point Comparison Method is more effective under the environment with more frequent change of solar radiation;however,the Fuzzy Logic Control has better tacking efficiency under the environment with violent change of solar radiation.

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Science.gov (United States)

Homulle, Harald; Visser, Stefan; Patra, Bishnu; Charbon, Edoardo

2018-01-01

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires and reduced performance of various printed circuit board components commonly employed at room temperature. Extensive characterization of these components shows that the majority of decoupling capacitor types and voltage regulators are not well behaved at cryogenic temperatures, asking for an ad hoc solution to stabilize the FPGA supply voltage, especially for sensitive applications. Therefore, we have designed a firmware that enforces a constant power consumption, so as to stabilize the supply voltage in the interior of the FPGA. The FPGA is powered with a supply at several meters distance, causing significant resistive voltage drop and thus fluctuations on the local supply voltage. To achieve the stabilization, the variation in digital logic speed, which directly corresponds to changes in supply voltage, is constantly measured and corrected for through a tunable oscillator farm, implemented on the FPGA. The impact of the stabilization technique is demonstrated together with a reconfigurable analog-to-digital converter (ADC), completely implemented in the FPGA fabric and operating at 15 K. The ADC performance can be improved by at most 1.5 bits (effective number of bits) thanks to the more stable supply voltage. The method is versatile and robust, enabling seamless porting to other FPGA families and configurations.

System design specification for rotary mode core sample trucks No. 2, 3, and 4 programmable logic controller

International Nuclear Information System (INIS)

Dowell, J.L.; Akers, J.C.

1995-01-01

The system this document describes controls several functions of the Core Sample Truck(s) used to obtain nuclear waste samples from various underground storage tanks at Hanford. The system will monitor the sampling process and provide alarms and other feedback to insure the sampling process is performed within the prescribed operating envelope. The intended audience for this document is anyone associated with rotary or push mode core sampling. This document describes the Alarm and Control logic installed on Rotary Mode Core Sample Trucks (RMCST) number-sign 2, 3, and 4. It is intended to define the particular requirements of the RMCST alarm and control operation (not defined elsewhere) sufficiently for detailed design to implement on a Programmable Logic Controller (PLC)

Logic-programming language enriches design processes

Energy Technology Data Exchange (ETDEWEB)

Kitson, B.; Ow-Wing, K.

1984-03-22

With the emergence of a set of high-level CAD tools for programmable logic devices, designers can translate logic into functional custom devices simply and efficiently. The core of the package is a blockstructured hardware description language called PLPL, for ''programmable-logic programming language.'' The cheif advantage of PLPL lies in its multiple input formats, which permit different design approaches for a variety of design problems. The higher the level of the approach, the closer PLPL will come to directly specifying the desired function. Intermediate steps in the design process can be eliminated, along with the errors that might have been generated during those steps.

Implementation of digital equality comparator circuit on memristive memory crossbar array using material implication logic

Science.gov (United States)

Haron, Adib; Mahdzair, Fazren; Luqman, Anas; Osman, Nazmie; Junid, Syed Abdul Mutalib Al

2018-03-01

One of the most significant constraints of Von Neumann architecture is the limited bandwidth between memory and processor. The cost to move data back and forth between memory and processor is considerably higher than the computation in the processor itself. This architecture significantly impacts the Big Data and data-intensive application such as DNA analysis comparison which spend most of the processing time to move data. Recently, the in-memory processing concept was proposed, which is based on the capability to perform the logic operation on the physical memory structure using a crossbar topology and non-volatile resistive-switching memristor technology. This paper proposes a scheme to map digital equality comparator circuit on memristive memory crossbar array. The 2-bit, 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit of equality comparator circuit are mapped on memristive memory crossbar array by using material implication logic in a sequential and parallel method. The simulation results show that, for the 64-bit word size, the parallel mapping exhibits 2.8× better performance in total execution time than sequential mapping but has a trade-off in terms of energy consumption and area utilization. Meanwhile, the total crossbar area can be reduced by 1.2× for sequential mapping and 1.5× for parallel mapping both by using the overlapping technique.

Saltwell Leak Detector Station Programmable Logic Controller (PLC) Software Configuration Management Plan (SCMP)

International Nuclear Information System (INIS)

WHITE, K.A.

2000-01-01

This document provides the procedures and guidelines necessary for computer software configuration management activities during the operation and maintenance phases of the Saltwell Leak Detector Stations as required by HNF-PRO-309/Rev.1, Computer Software Quality Assurance, Section 2.4, Software Configuration Management. The software configuration management plan (SCMP) integrates technical and administrative controls to establish and maintain technical consistency among requirements, physical configuration, and documentation for the Saltwell Leak Detector Station Programmable Logic Controller (PLC) software during the Hanford application, operations and maintenance. This SCMP establishes the Saltwell Leak Detector Station PLC Software Baseline, status changes to that baseline, and ensures that software meets design and operational requirements and is tested in accordance with their design basis

A study on implementation of dynamic safety system in programmable logic controller for pressurized water reactor

International Nuclear Information System (INIS)

Kim, Ung Soo

1997-02-01

The dynamic safety system (DSS) is a computer based reactor protection system that has dynamic self-testing feature and fail-safe nature inherently. The inherent dynamic self-testing feature and fail-safe design provide a high level of reliability and low spurious trip rate. We can also reduce the time and human efforts to maintain the system by virtue of those features. Therefore, the application of the DSS to PWR has many advantages. The DSS has been applied only to advanced gas-cooled reactor (AGR) in the UK. In order to apply the DSS for PWR, the DSS has to be modified because there exist many differences between PWR and AGR for which the DSS was tested and installed. These differences are trip algorithms, monitored parameters, trip logics, and other conditions. In this study, the DSS algorithm is modified for PWR first. The modified DSS has several new features : 1) The modified DSS tests and processes time-dependent parameters, while the original DSS does not. 2) It has flexibility for handling several types of voting logic but the original DSS handles the only one type of voting - 2 out of 4 coincidence logic. Then, in this study, the modified DSS is implemented in programmable logic controller (PLC) using the ladder logic. Finally, the modified DSS is tested in two ways in this work : 1) The manual test is performed using direct input through the human computer interface (HCI) system. 2) The scenario based test is performed using input from the FISA-2/WS simulator. From the test results, it is shown that the modified DSS operates correctly in all conditions

Use of advanced programmable logic controllers to monitor and control the Elmo Bumpy Torus-proof-of-principle device

International Nuclear Information System (INIS)

Boyd, B.A.

1983-01-01

The Elmo Bumpy Torus - Proof-of-Principle (EBT-P) device is designed with an instrumentation and control system based upon the use of an advanced Programmable Logic Controller (PLC). The modern PLC incorporates many advanced programming features not available in earlier PLC's intended for application to conventional relay logic replacement. The additional power and flexibility of these modern PLC's is especially applicable to an experimental device such as EBT-P which is made up of several complex interrelated subsystems whose operational characteristics will be evolving throughout the lifetime of the device. The rationale for the selection of advanced PLC's for EBT-P and the approach taken to design of the software developed to control EBT-P are the topics addressed in this paper

Greek, Indian and Arabic logic

CERN Document Server

Gabbay, Dov M

2004-01-01

Greek, Indian and Arabic Logic marks the initial appearance of the multi-volume Handbook of the History of Logic. Additional volumes will be published when ready, rather than in strict chronological order. Soon to appear are The Rise of Modern Logic: From Leibniz to Frege. Also in preparation are Logic From Russell to Gödel, Logic and the Modalities in the Twentieth Century, and The Many-Valued and Non-Monotonic Turn in Logic. Further volumes will follow, including Mediaeval and Renaissance Logic and Logic: A History of its Central. In designing the Handbook of the History of Logic, the Editors have taken the view that the history of logic holds more than an antiquarian interest, and that a knowledge of logic's rich and sophisticated development is, in various respects, relevant to the research programmes of the present day. Ancient logic is no exception. The present volume attests to the distant origins of some of modern logic's most important features, such as can be found in the claim by the authors of t...

Introduction to fuzzy logic using Matlab

CERN Document Server

Sivanandam, SN; Deepa, S N

2006-01-01

Fuzzy Logic, at present is a hot topic, among academicians as well various programmers. This book is provided to give a broad, in-depth overview of the field of Fuzzy Logic. The basic principles of Fuzzy Logic are discussed in detail with various solved examples. The different approaches and solutions to the problems given in the book are well balanced and pertinent to the Fuzzy Logic research projects. The applications of Fuzzy Logic are also dealt to make the readers understand the concept of Fuzzy Logic. The solutions to the problems are programmed using MATLAB 6.0 and the simulated results are given. The MATLAB Fuzzy Logic toolbox is provided for easy reference.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

Science.gov (United States)

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Science.gov (United States)

Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley

2009-02-10

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Optical Doppler tomography based on a field programmable gate array

DEFF Research Database (Denmark)

Larsen, Henning Engelbrecht; Nilsson, Ronnie Thorup; Thrane, Lars

2008-01-01

We report the design of and results obtained by using a field programmable gate array (FPGA) to digitally process optical Doppler tomography signals. The processor fits into the analog signal path in an existing optical coherence tomography setup. We demonstrate both Doppler frequency and envelope...... extraction using the Hilbert transform, all in a single FPGA. An FPGA implementation has certain advantages over general purpose digital signal processor (DSP) due to the fact that the processing elements operate in parallel as opposed to the DSP. which is primarily a sequential processor....

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

National Research Council Canada - National Science Library

Mumbru, Jose

2004-01-01

... holograms for these modules. The first chapter makes the case that a direct interface between an optical memory and a chip integrating detectors and logic circuitry can better utilize the high parallelism inherent in holographic modules...

Smart time-pulse coding photoconverters as basic components 2D-array logic devices for advanced neural networks and optical computers

Science.gov (United States)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Michalnichenko, Nikolay N.

2004-04-01

The article deals with a conception of building arithmetic-logic devices (ALD) with a 2D-structure and optical 2D-array inputs-outputs as advanced high-productivity parallel basic operational training modules for realization of basic operation of continuous, neuro-fuzzy, multilevel, threshold and others logics and vector-matrix, vector-tensor procedures in neural networks, that consists in use of time-pulse coding (TPC) architecture and 2D-array smart optoelectronic pulse-width (or pulse-phase) modulators (PWM or PPM) for transformation of input pictures. The input grayscale image is transformed into a group of corresponding short optical pulses or time positions of optical two-level signal swing. We consider optoelectronic implementations of universal (quasi-universal) picture element of two-valued ALD, multi-valued ALD, analog-to-digital converters, multilevel threshold discriminators and we show that 2D-array time-pulse photoconverters are the base elements for these devices. We show simulation results of the time-pulse photoconverters as base components. Considered devices have technical parameters: input optical signals power is 200nW_200μW (if photodiode responsivity is 0.5A/W), conversion time is from tens of microseconds to a millisecond, supply voltage is 1.5_15V, consumption power is from tens of microwatts to a milliwatt, conversion nonlinearity is less than 1%. One cell consists of 2-3 photodiodes and about ten CMOS transistors. This simplicity of the cells allows to carry out their integration in arrays of 32x32, 64x64 elements and more.

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

Science.gov (United States)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Fuzzy logic type 1 and type 2 based on LabVIEW FPGA

CERN Document Server

Ponce-Cruz, Pedro; MacCleery, Brian

2016-01-01

This book is a comprehensive introduction to LabVIEW FPGA™, a package allowing the programming of intelligent digital controllers in field programmable gate arrays (FPGAs) using graphical code. It shows how both potential difficulties with understanding and programming in VHDL and the consequent difficulty and slowness of implementation can be sidestepped. The text includes a clear theoretical explanation of fuzzy logic (type 1 and type 2) with case studies that implement the theory and systematically demonstrate the implementation process. It goes on to describe basic and advanced levels of programming LabVIEW FPGA and show how implementation of fuzzy-logic control in FPGAs improves system responses. A complete toolkit for implementing fuzzy controllers in LabVIEW FPGA has been developed with the book so that readers can generate new fuzzy controllers and deploy them immediately. Problems and their solutions allow readers to practice the techniques and to absorb the theoretical ideas as they arise. Fuzzy L...

PID Neural Network Based Speed Control of Asynchronous Motor Using Programmable Logic Controller

Directory of Open Access Journals (Sweden)

MARABA, V. A.

2011-11-01

Full Text Available This paper deals with the structure and characteristics of PID Neural Network controller for single input and single output systems. PID Neural Network is a new kind of controller that includes the advantages of artificial neural networks and classic PID controller. Functioning of this controller is based on the update of controller parameters according to the value extracted from system output pursuant to the rules of back propagation algorithm used in artificial neural networks. Parameters obtained from the application of PID Neural Network training algorithm on the speed model of the asynchronous motor exhibiting second order linear behavior were used in the real time speed control of the motor. Programmable logic controller (PLC was used as real time controller. The real time control results show that reference speed successfully maintained under various load conditions.

Experience with the use of programmable logic controllers in nuclear safety applications. Final report

International Nuclear Information System (INIS)

Brown, E.M.; Stofko, M.J.

1995-03-01

This report describes the implementation and experience with Programmable Logic Controllers (PLC) for nuclear safety applications. Two applications are described. The first is an Anticipated Transient Without Scram (ATWS) mitigation system provided as a Diverse Auxiliary Feedwater Actuation System (DAFAS). It was implemented at Arizona Public Service's Palo Verde Nuclear Generating Station and has been in commercial operation since early 1992. The second system described is an Emergency Diesel Generator Bus Load Sequencer installed at Florida Power and Light's Turkey Point Nuclear Power Plant. This system was installed as part of an upgrade to the emergency power system in 1988. The experience gained in the design, development, implementation and qualification of these systems will be beneficial to utilities that are considering the utilization of PLCs for their plant applications

Failure mode taxonomy for assessing the reliability of Field Programmable Gate Array based Instrumentation and Control systems

International Nuclear Information System (INIS)

McNelles, Phillip; Zeng, Zhao Chang; Renganathan, Guna; Chirila, Marius; Lu, Lixuan

2017-01-01

Highlights: • The use FPGAs in I&C systems in Nuclear Power Plants is an important issue (IAEA). • OECD-NEA published a failure mode taxonomy for software-based digital I&C systems. • This paper extends the OECD-NEA taxonomy to model FPGA-based systems. • FPGA failure modes, failure effects, uncovering methods are categorized/described. • Provides an example of modelling an FPGA-Based RTS/ESFAS using the FPGA taxonomy. - Abstract: Field Programmable Gate Arrays (FPGAs) are a form of programmable digital hardware configured to perform digital logic functions. This configuration (programming) is performed using Hardware Description Language (HDL), making FPGAs a form of HDL Programmed Device (HPD). In the nuclear field, FPGAs have seen use in upgrades and replacements of obsolete Instrumentation and Control (I&C) systems. This paper expands upon previous work that resulted in extensive FPGA failure mode data, to allow for the application of the OECD-NEA failure modes taxonomy. The OECD-NEA taxonomy presented a method to model digital (software-based) I&C systems, based on the hardware and software failure modes, failure uncovering effects and levels of abstraction, using a Reactor Trip System/Engineering Safety Feature Actuation System (RTS/ESFAS) as an example system. To create the FPGA taxonomy, this paper presents an additional “sub-component” level of abstraction, to demonstrate the effect of the FPGA failure modes and failure categories on an FPGA-based system. The proposed FPGA taxonomy is based on the FPGA failure modes, failure categories, failure effects and uncovering situations. The FPGA taxonomy is applied to the RTS/ESFAS test system, to demonstrate the effects of the anticipated FPGA failure modes on a digital I&C system, and to provide a modelling example for this proposed taxonomy.

Logicism, intuitionism, and formalism

CERN Document Server

Symons, John

2008-01-01

Aims to review the programmes in the foundations of mathematics from the classical period and to assess their possible relevance for contemporary philosophy of mathematics. This work is suitable for researchers and graduate students of philosophy, logic, mathematics and theoretical computer science.

What Else Is Decidable about Integer Arrays?

OpenAIRE

Habermehl, Peter; Iosif, Radu; Vojnar, Tomáš

2008-01-01

International audience; We introduce a new decidable logic for reasoning about infinite arrays of integers. The logic is in the ∃ * ∀ * first-order fragment and allows (1) Presburger constraints on existentially quantified variables, (2) difference constraints as well as periodicity constraints on universally quantified indices, and (3) difference constraints on values. In particular, using our logic, one can express constraints on consecutive elements of arrays (e.g. ∀i. 0 ≤ i < n → a[i + 1]...

Development of a fast time-to-digital converter (TDC) using a programmable gate array

International Nuclear Information System (INIS)

Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

1994-09-01

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

MANUAL LOGIC CONTROLLER (MLC)

OpenAIRE

Claude Ziad Bayeh

2015-01-01

The “Manual Logic Controller” also called MLC, is an electronic circuit invented and designed by the author in 2008, in order to replace the well known PLC (Programmable Logic Controller) in many applications for its advantages and its low cost of fabrication. The function of the MLC is somewhat similar to the well known PLC, but instead of doing it by inserting a written program into the PLC using a computer or specific software inside the PLC, it will be manually programmed in a manner to h...

Modeling and Simulation of a Non-Coherent Frequency Shift Keying Transceiver Using a Field Programmable Gate Array (FPGA)

National Research Council Canada - National Science Library

Voskakis, Konstantinos

2008-01-01

...) receiver-transmitter in a Field Programmable Gate Array (FPGA). After introducing the theory behind the Non- Coherent BFSK demodulation implemented at the receiver, the design of transmitter and receiver is illustrated...

Field programmable gate array-assigned complex-valued computation and its limits

Energy Technology Data Exchange (ETDEWEB)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com [National Instruments, Ganghoferstrasse 70b, 80339 Munich (Germany); Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien (Austria); Zwick, Wolfgang; Klier, Jochen [National Instruments, Ganghoferstrasse 70b, 80339 Munich (Germany); Wenzel, Lothar [National Instruments, 11500 N MOPac Expy, Austin, Texas 78759 (United States); Gröschl, Martin [Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien (Austria)

2014-09-15

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

Science.gov (United States)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Science.gov (United States)

Le, Martin; Zheng, Xin; Katanyoutant, Sunant

2008-01-01

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state

Multiple constant multiplication optimizations for field programmable gate arrays

CERN Document Server

Kumm, Martin

2016-01-01

This work covers field programmable gate array (FPGA)-specific optimizations of circuits computing the multiplication of a variable by several constants, commonly denoted as multiple constant multiplication (MCM). These optimizations focus on low resource usage but high performance. They comprise the use of fast carry-chains in adder-based constant multiplications including ternary (3-input) adders as well as the integration of look-up table-based constant multipliers and embedded multipliers to get the optimal mapping to modern FPGAs. The proposed methods can be used for the efficient implementation of digital filters, discrete transforms and many other circuits in the domain of digital signal processing, communication and image processing. Contents Heuristic and ILP-Based Optimal Solutions for the Pipelined Multiple Constant Multiplication Problem Methods to Integrate Embedded Multipliers, LUT-Based Constant Multipliers and Ternary (3-Input) Adders An Optimized Multiple Constant Multiplication Architecture ...

Using Spare Logic Resources To Create Dynamic Test Points

Science.gov (United States)

Katz, Richard; Kleyner, Igor

2011-01-01

A technique has been devised to enable creation of a dynamic set of test points in an embedded digital electronic system. As a result, electronics contained in an application specific circuit [e.g., gate array, field programmable gate array (FPGA)] can be internally probed, even when contained in a closed housing during all phases of test. In the present technique, the test points are not fixed and limited to a small number; the number of test points can vastly exceed the number of buffers or pins, resulting in a compact footprint. Test points are selected by means of spare logic resources within the ASIC(s) and/or FPGA(s). A register is programmed with a command, which is used to select the signals that are sent off-chip and out of the housing for monitoring by test engineers and external test equipment. The register can be commanded by any suitable means: for example, it could be commanded through a command port that would normally be used in the operation of the system. In the original application of the technique, commanding of the register is performed via a MIL-STD-1553B communication subsystem.

An Undergraduate Survey Course on Asynchronous Sequential Logic, Ladder Logic, and Fuzzy Logic

Science.gov (United States)

Foster, D. L.

2012-01-01

For a basic foundation in computer engineering, universities traditionally teach synchronous sequential circuit design, using discrete gates or field programmable gate arrays, and a microcomputers course that includes basic I/O processing. These courses, though critical, expose students to only a small subset of tools. At co-op schools like…

The application of computer logic design in the trigger system

International Nuclear Information System (INIS)

Zhao Dixin; Ding Huiliang; Gu Jianhui

1996-01-01

The programmable logic devices PLD and FPGA, which are developing steadily recently, can be configured by user. Designers define the logic functions of the circuit and revise these functions when necessary. The application of these devices in the trigger system and development system is introduced

Peptide Logic Circuits Based on Chemoenzymatic Ligation for Programmable Cell Apoptosis.

Science.gov (United States)

Li, Yong; Sun, Sujuan; Fan, Lin; Hu, Shanfang; Huang, Yan; Zhang, Ke; Nie, Zhou; Yao, Shouzhou

2017-11-20

A novel and versatile peptide-based bio-logic system capable of regulating cell function is developed using sortase A (SrtA), a peptide ligation enzyme, as a generic processor. By modular peptide design, we demonstrate that mammalian cells apoptosis can be programmed by peptide-based logic operations, including binary and combination gates (AND, INHIBIT, OR, and AND-INHIBIT), and a complex sequential logic circuit (multi-input keypad lock). Moreover, a proof-of-concept peptide regulatory circuit was developed to analyze the expression profile of cell-secreted protein biomarkers and trigger cancer-cell-specific apoptosis. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Control Systems of Rubber Dryer Machinery Components Using Programmable Logic Control (PLC)

Science.gov (United States)

Hendra; Yulianto, A. S.; Indriani, A.; Hernadewita; Hermiyetti

2018-02-01

Application of programmable logic control (PLC) is widely used on the control systems in the many field engineering such as automotive, aviation, food processing and other industries [1-2]. PLC is simply program to control many automatic activity, easy to use, flexible and others. PLC using the ladder program to solve and regulated the control system component. In previous research, PLC was used for control system of rotary dryer machine. In this paper PLC are used for control system of motion component in the rubber dryer machinery. Component of rubber dryer machine is motors, gearbox, sprocket, heater, drying chamber and bearing. Principle working of rubber dryer machinery is wet rubber moving into the drying chamber by sprocket. Sprocket is driven by motors that conducted by PLC to moving and set of wet rubber on the drying chamber. Drying system uses greenhouse effect by making hanger dryer design in the form of line path. In this paper focused on motion control system motors and sensors drying rubber using PLC. The results show that control system of rubber dryer machinery can work in accordance control input and the time required to dry the rubber.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

Science.gov (United States)

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode

Triggering the GRANDE array

International Nuclear Information System (INIS)

Wilson, C.L.; Bratton, C.B.; Gurr, J.; Kropp, W.; Nelson, M.; Sobel, H.; Svoboda, R.; Yodh, G.; Burnett, T.; Chaloupka, V.; Wilkes, R.J.; Cherry, M.; Ellison, S.B.; Guzik, T.G.; Wefel, J.; Gaidos, J.; Loeffler, F.; Sembroski, G.; Goodman, J.; Haines, T.J.; Kielczewska, D.; Lane, C.; Steinberg, R.; Lieber, M.; Nagle, D.; Potter, M.; Tripp, R.

1990-01-01

A brief description of the Gamma Ray And Neutrino Detector Experiment (GRANDE) is presented. The detector elements and electronics are described. The trigger logic for the array is then examined. The triggers for the Gamma Ray and the Neutrino portions of the array are treated separately. (orig.)

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

Science.gov (United States)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

Real-time field programmable gate array architecture for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2001-01-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

Three-channel phase meters based on the AD8302 and field programmable gate arrays for heterodyne millimeter wave interferometer

Czech Academy of Sciences Publication Activity Database

Varavin, A.V.; Ermak, G.P.; Vasiliev, A.S.; Fateev, A.V.; Varavin, Mykyta; Žáček, František; Zajac, Jaromír

2016-01-01

Roč. 75, č. 11 (2016), s. 1009-1025 ISSN 0040-2508 Institutional support: RVO:61389021 Keywords : AD8302 * Interferometer * Millimeter wave * Phase meter * Programmable gate array * Tokamak Subject RIV: BL - Plasma and Gas Discharge Physics

Simultaneous G-Quadruplex DNA Logic.

Science.gov (United States)

Bader, Antoine; Cockroft, Scott L

2018-04-03

A fundamental principle of digital computer operation is Boolean logic, where inputs and outputs are described by binary integer voltages. Similarly, inputs and outputs may be processed on the molecular level as exemplified by synthetic circuits that exploit the programmability of DNA base-pairing. Unlike modern computers, which execute large numbers of logic gates in parallel, most implementations of molecular logic have been limited to single computing tasks, or sensing applications. This work reports three G-quadruplex-based logic gates that operate simultaneously in a single reaction vessel. The gates respond to unique Boolean DNA inputs by undergoing topological conversion from duplex to G-quadruplex states that were resolved using a thioflavin T dye and gel electrophoresis. The modular, addressable, and label-free approach could be incorporated into DNA-based sensors, or used for resolving and debugging parallel processes in DNA computing applications. © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

step by step process from logic model to case study method as an ...

African Journals Online (AJOL)

Global Journal

Logic models and case study approach to programme evaluation have proven ... in qualitative methodology. There is ... Note: IEHPs= internationally educated health professionals, ... interviews with the programme managers. .... programme assessed to ensure that the IEHPs are ready to face the certification ..... Comparison.

Telescope Array Control System Based on Wireless Touch Screen Platform

Science.gov (United States)

Fu, Xia-nan; Huang, Lei; Wei, Jian-yan

2017-10-01

Ground-based Wide Angle Cameras (GMAC) are the ground-based observational facility for the SVOM (Space Variable Object Monitor) astronomical satellite of Sino-French cooperation, and Mini-GWAC is the pathfinder and supplement of GWAC. In the context of the Mini-GWAC telescope array, this paper introduces the design and implementation of a kind of telescope array control system based on the wireless touch screen platform. We describe the development and implementation of the system in detail in terms of control system principle, system hardware structure, software design, experiment, and test etc. The system uses a touch-control PC which is based on the Windows CE system as the upper computer, while the wireless transceiver module and PLC (Programmable Logic Controller) are taken as the system kernel. It has the advantages of low cost, reliable data transmission, and simple operation. And the control system has been applied to the Mini-GWAC successfully.

"Modeling" Youth Work: Logic Models, Neoliberalism, and Community Praxis

Science.gov (United States)

Carpenter, Sara

2016-01-01

This paper examines the use of logic models in the development of community initiatives within the AmeriCorps program. AmeriCorps is the civilian national service programme in the U.S., operating as a grants programme to local governments and not-for-profit organisations and providing low-cost labour to address pressing issues of social…

A control system based on field programmable gate array for papermaking sewage treatment

International Nuclear Information System (INIS)

Zhang, Zi Sheng; Xie, Chang; Xiong, Yan Qing; Liu, Zhi Qiang; Li, Qing

2013-01-01

A sewage treatment control system is designed to improve the efficiency of papermaking wastewater treatment system. The automation control system is based on Field Programmable Gate Array (FPGA), coded with Very-High-Speed Integrate Circuit Hardware Description Language (VHDL), compiled and simulated with Quartus. In order to ensure the stability of the data used in FPGA, the data is collected through temperature sensors, water level sensor and online PH measurement system. The automatic control system is more sensitive, and both the treatment efficiency and processing power are increased. This work provides a new method for sewage treatment control.

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

Science.gov (United States)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Fuzzy Logic vs. Neutrosophic Logic: Operations Logic

Directory of Open Access Journals (Sweden)

Salah Bouzina

2016-12-01

Full Text Available The goal of this research is first to show how different, thorough, widespread and effective are the operations logic of the neutrosophic logic compared to the fuzzy logic’s operations logical. The second aim is to observe how a fully new logic, the neutrosophic logic, is established starting by changing the previous logical perspective fuzzy logic, and by changing that, we mean changing changing the truth values from the truth and falsity degrees membership in fuzzy logic, to the truth, falsity and indeterminacy degrees membership in neutrosophic logic; and thirdly, to observe that there is no limit to the logical discoveries - we only change the principle, then the system changes completely.

Design and analysis of a dual mode CMOS field programmable analog array

International Nuclear Information System (INIS)

Cheng Xiaoyan; Yang Haigang; Yin Tao; Wu Qisong; Zhang Hongfeng; Liu Fei

2014-01-01

This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%. (semiconductor integrated circuits)

Time-space modal logic for verification of bit-slice circuits

Science.gov (United States)

Hiraishi, Hiromi

1996-03-01

The major goal of this paper is to propose a new modal logic aiming at formal verification of bit-slice circuits. The new logic is called as time-space modal logic and its major feature is that it can handle two transition relations: one for time transition and the other for space transition. As for a verification algorithm, a symbolic model checking algorithm of the new logic is shown. This could be applicable to verification of bit-slice microprocessor of infinite bit width and 1D systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.

CAMAC modular programmable function generator

Energy Technology Data Exchange (ETDEWEB)

Turner, G.W.; Suehiro, S.; Hendricks, R.W.

1980-12-01

A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve.

CAMAC modular programmable function generator

International Nuclear Information System (INIS)

Turner, G.W.; Suehiro, S.; Hendricks, R.W.

1980-12-01

A CAMAC modular programmable function generator has been developed. The device contains a 1024 word by 12-bit memory, a 12-bit digital-to-analog converter with a 600 ns settling time, an 18-bit programmable frequency register, and two programmable trigger output registers. The trigger registers can produce programmed output logic transitions at various (binary) points in the output function curve, and are used to synchronize various other data acquisition devices with the function curve

Reliability analysis of diverse safety logic systems of fast breeder reactor

International Nuclear Information System (INIS)

Ravi Kumar, Bh.; Apte, P.R.; Srivani, L.; Ilango Sambasivan, S.; Swaminathan, P.

2006-01-01

Safety Logic for Fast Breeder Reactor (FBR) is designed to initiate safety action against Design Basis Events. Based on the outputs of various processing circuits, Safety logic system drives the control rods of the shutdown system. So, Safety Logic system is classified as safety critical system. Therefore, reliability analysis has to be performed. This paper discusses the Reliability analysis of Diverse Safety logic systems of FBRs. For this literature survey on safety critical systems, system reliability approach and standards to be followed like IEC-61508 are discussed in detail. For Programmable Logic device based systems, Hardware Description Languages (HDL) are used. So this paper also discusses the Verification and Validation for HDLs. Finally a case study for the Reliability analysis of Safety logic is discussed. (author)

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Final Report

Energy Technology Data Exchange (ETDEWEB)

Britton, Jr., Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Bobrek, Miljko [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

2015-12-01

As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios where human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments due the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is the final report of the activities involving the NEET 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays. We present a detailed functional block diagram of the proposed data acquisition system, the thought process leading to technical decisions, the implemented system, and the tested results from the systems. This system will be capable of monitoring at least three parameters of importance to nuclear reactor monitoring: temperature, radiation level, and pressure.

Reducing pure dephasing of quantum bits by collective encoding in quantum dot arrays

International Nuclear Information System (INIS)

Grodecka, A; Machnikowski, P; Jacak, L

2006-01-01

We show that phonon-induced pure dephasing of an excitonic (charge) quantum bit in a quantum dot (QD) may be reduced by collective encoding of logical qubits in QD arrays. We define the logical qubit on an array of 2, 4 and 8 QDs, connecting the logical 0) state with the presence of excitons in the appropriately chosen half of dots and the logical 1) state with the other half of the dots occupied. We give quantitative estimates of the resulting total error of a single qubit operation for an InAs/GaAs system

PENGEMBANGAN PERANGKAT PEMBELAJARAN MEKATRONIKA BERBASIS KOMPUTER POKOK BAHASAN PROGRAMMABLE LOGIC CONTROLLER BERORIENTASI PADA PEMBELAJARAN LANGSUNG

Directory of Open Access Journals (Sweden)

Wahyu Dwi Kurniawan

2015-02-01

Program Logic Controller is subject that many complaints by students of Department of Mechanical Engineering FT-Unesa. This is due to the lack of learning devices are used so that learning becomes less favorable and become passive. This study aims to develop computer-based learning device mechatronics subject-oriented programmable logic controller directly on student learning Mechanical Engineering Department Unesa FT. This study was conducted in two phases. Phase I, the development of the learning refers to the design of the Model 4D Thiagarajan (1974, Phase II, trial learning in the classroom using a design of one group pretest-posttest design. The findings of the study: (1 an average score of 3.32 learning assessment tools (pretty good, (2 average scores on tests of learning implementation I of 3.59 (good and trials II of 3.70 (both , (3 student learning outcomes of cognitive and psychomotor aspects have achieved individually and classical mastery, (4 students showed a positive response to the stated learning tehadap interested, excited, and motivated to attend lectures mechatronics; activity of the most dominant college students are discussin /practices relevant to teaching and learning that is on trial I is 36.46% and trials II 38.19%. Based on the analysis of data, it can be concluded that the developed learning feasible for use in lectures mechatronics. Implementation of the computer-based learning mechatronics subjects PLC can improve the quality of teaching and learning, as students showed a positive response, implementation category learning and learning outcomes both cognitive and psychomotor aspects of students have achieved mastery individually and classical. Keywords: development, learning, mechatronics, computer, plc

Optically controllable molecular logic circuits

International Nuclear Information System (INIS)

Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun

2015-01-01

Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

Science.gov (United States)

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Multi Channels PWM Controller for Thermoelectric Cooler Using a Programmable Logic Device and Lab-Windows CVI

Directory of Open Access Journals (Sweden)

Eli FLAXER

2008-09-01

Full Text Available We present a complete design of a multi channels PID controller for Thermoelectric Cooler (TEC using a pulse width modulation (PWM technique implemented by a dedicated programmable logic device (PLD programmed by VHDL. The PID control loop is implemented by software written by National Instrument Lab-Windows CVI. Due to the fact that the implementation is by a VHDL and PLD the design is modular, as a result, the circuit is very compact in size and very low cost as compared to any commercial product. In addition, since the control loop is implemented by software running on a personal computer (PC using a C language, it is easy to adjust the controller to various environmental conditions and for a width range of sensors like: a thermo couple (TC, thermistor, resistance temperature detectors (RTD etc. We demonstrate the performance of this circuit as a controller for a small incubator using thermistor as the temperature sensor.

Fuzzy Logic and Intelligent Technologies in Nuclear Science (FLINS)

International Nuclear Information System (INIS)

Da Ruan

2000-01-01

FLINS is the acronym for Fuzzy Logic and Intelligent Technologies in Nuclear Science. In 1994, SCK-CEN launched a programme on FLINS. The first FLINS project dealt with the specific prototyping of fuzzy logic control (FLC) of the BR-1 research reactor. This project focussed on controlling the power level of the BR1 reactor added value of FLC for both safety and economic aspects for a nuclear reactor control operation. Main achievements in 1999 are reported

Methods for the Application of Programmable Logic Devices in Electronic Protection Systems for High Energy Particle Accelerators

CERN Document Server

Kwiatkowski, Maciej; Todd, Benjamin

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable firmware implementation and to use that method to implement a new firmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis. For that reason the reliable SMP hardware was preserved unchanged. The first version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP firmware was objectionable. There were new requirements and therefore the SMP specification was extended. On that occasion it was decided that the existing SMP firmware will not be continued and ...

Methods for the application of programmable logic devices in electronic protection systems for high energy particle accelerators

CERN Document Server

Kwiatkowski, M

2014-01-01

The present thesis was realised within the framework of the Doctoral Student programme at the European Organisation for Nuclear Research CERN, which is situated near Geneva. The aim of this thesis was to develop a method for reliable rmware implementation and to use that method to implement a new rmware for the Safe Machine Parameters (SMP) system. That system relies heavily on the Field Programmable Gate Arrays (FPGA) and it is one of the key machine protection systems of the Large Hadron Collider (LHC). The conception of the SMP hardware originates from the fully tested Beam Interlock System (BIS) being a result of another PhD thesis [1]. For that reason the reliable SMP hardware was preserved unchanged. The rst version of the SMP was ready for the LHC startup in the year 2008. Nevertheless the quality of the SMP rmware was objectionable. There were new requirements and therefore the SMP speci cation was extended. On that occasion it was decided that the existing SMP rmware will not be continued and that it...

Universal file processing program for field programmable integrated circuits

International Nuclear Information System (INIS)

Freytag, D.R.; Nelson, D.J.

1985-01-01

A computer program is presented that translates logic equations into promburner files (or the reverse) for programmable logic devices of various kinds, namely PROMs FPLAs, FPLSs and PALs. The program achieves flexibility through the use of a database containing detailed information about the devices to be programmed. New devices can thus be accommodated through simple extensions of the database. When writing logic equations, the user can define logic combinations of signals as new logic variables for use in subsequent equations. This procedure yields compact and transparent expressions for logic operations, thus reducing the chances for error. A logic simulation program is also provided so that an independent check of the design can be performed at the software level

Logical Reasoning in Middle Childhood: A Study of Piagetian Concrete Operations Stage.

Science.gov (United States)

Hooper, Frank H.; And Others

This 4-year longitudinal study of logical reasoning found complex interrelationships among different cognitive processes of children ages 6 to 15. Piaget's stage theory is discussed in the introduction, with a focus on the concrete operational stage in middle childhood. In the study, a representative array of logical concept tasks and short-term…

Layout and cabling considerations for a large communications antenna array

Science.gov (United States)

Logan, R. T., Jr.

1993-01-01

Layout considerations for a large deep space communications antenna array are discussed. A fractal geometry for the antenna layout is described that provides optimal packing of antenna elements, efficient cable routing, and logical division of the array into identical sub-arrays.

Designing for Reuse of Configurable Logic

National Research Council Canada - National Science Library

Elm, Joseph P

2005-01-01

Field-programmable gate arrays (FPGAs) offer electronic systems designers the opportunity to reduce development cost, reduce time-to-market, increase system performance, and improve system adaptability...

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

Design structure for in-system redundant array repair in integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

Science.gov (United States)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Software V and V methods for a safety - grade programmable logic controller

International Nuclear Information System (INIS)

Jang Yeol Kim; Young Jun Lee; Kyung Ho Cha; Se Woo Cheon; Jang Soo Lee; Kee Choon Kwon

2006-01-01

This paper addresses the Verification and Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety- grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines and procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects. (author)

Integration of spintronic interface for nanomagnetic arrays

Directory of Open Access Journals (Sweden)

Andrew Lyle

2011-12-01

Full Text Available An experimental demonstration utilizing a spintronic input/output (I/O interface for arrays of closely spaced nanomagnets is presented. The free layers of magnetic tunnel junctions (MTJs form dipole coupled nanomagnet arrays which can be applied to different contexts including Magnetic Quantum Cellular Automata (MQCA for logic applications and self-biased devices for field sensing applications. Dipole coupled nanomagnet arrays demonstrate adaptability to a variety of contexts due to the ability for tuning of magnetic response. Spintronics allows individual nanomagnets to be manipulated with spin transfer torque and monitored with magnetoresistance. This facilitates measurement of the magnetic coupling which is important for (yet to be demonstrated data propagation reliability studies. In addition, the same magnetic coupling can be tuned to reduce coercivity for field sensing. Dipole coupled nanomagnet arrays have the potential to be thousands of times more energy efficient than CMOS technology for logic applications, and they also have the potential to form multi-axis field sensors.

Data acquisition and control system with a programmable logic controller (PLC) for a pulsed chemical oxygen-iodine laser

Science.gov (United States)

Yu, Haijun; Li, Guofu; Duo, Liping; Jin, Yuqi; Wang, Jian; Sang, Fengting; Kang, Yuanfu; Li, Liucheng; Wang, Yuanhu; Tang, Shukai; Yu, Hongliang

2015-02-01

A user-friendly data acquisition and control system (DACS) for a pulsed chemical oxygen -iodine laser (PCOIL) has been developed. It is implemented by an industrial control computer，a PLC, and a distributed input/output (I/O) module, as well as the valve and transmitter. The system is capable of handling 200 analogue/digital channels for performing various operations such as on-line acquisition, display, safety measures and control of various valves. These operations are controlled either by control switches configured on a PC while not running or by a pre-determined sequence or timings during the run. The system is capable of real-time acquisition and on-line estimation of important diagnostic parameters for optimization of a PCOIL. The DACS system has been programmed using software programmable logic controller (PLC). Using this DACS, more than 200 runs were given performed successfully.

Reversible arithmetic logic unit for quantum arithmetic

DEFF Research Database (Denmark)

Thomsen, Michael Kirkedal; Glück, Robert; Axelsen, Holger Bock

2010-01-01

This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic...... and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n......-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible...

Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Stephen Brown

1996-01-01

Full Text Available This paper addresses several issues involved for routing in Field-Programmable Gate Arrays (FPGAs that have both horizontal and vertical routing channels, with wire segments of various lengths. Routing is studied by using CAD routing tools to map a set of benchmark circuits into FPGAs, and measuring the effects that various parameters of the CAD tools have on the implementation of the circuits. A two-stage routing strategy of global followed by detailed routing is used, and the effects of both of these CAD stages are discussed, with emphasis on detailed routing. We present a new detailed routing algorithm designed specifically for the types of routing structures found in the most recent generation of FPGAs, and show that the new algorithm achieves significantly better results than previously published FPGA routers with respect to the speed-performance of implemented circuits.

A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

KAUST Repository

Tella, Sherif Adekunle

2018-04-30

Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

A Single MEMS Resonator for Reconfigurable Multifunctional Logic Gates

KAUST Repository

Tella, Sherif Adekunle; Alcheikh, Nouha; Younis, Mohammad I.

2018-01-01

Despite recent efforts toward true electromechanical resonator-based computing, achieving complex logics functions through cascading micro resonators has been deterred by challenges involved in their interconnections and the large required array of resonators. In this work we present a single micro electromechanical resonator with two outputs that enables the realization of multifunctional logic gates as well as other complex logic operations. As examples, we demonstrate the realization of the fundamental 2-bit logic gates of OR, XOR, AND, NOR, and a half adder. The device is based on a compound resonator consisting of a clamped-guided electrostatically actuated arch beam that is attached to another resonant beam from the side, which serves as an additional actuation electrode for the arch. The structure is also provided with an additional electrothermal tuning capability. The logic operations are based on the linear frequency modulations of the arch resonator and side microbeam. The device is compatible with CMOS fabrication process and works at room temperature

Nonlinear dynamics based digital logic and circuits.

Science.gov (United States)

Kia, Behnam; Lindner, John F; Ditto, William L

2015-01-01

We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.

Orientation of a 3D object: implementation with an artificial neural network using a programmable logic device

International Nuclear Information System (INIS)

Carnevale, Federico J.

2010-01-01

Complex information extraction from images is a key skill of intelligent machines, with wide application in automated systems, robotic manipulation and human-computer interaction. However, solving this problem with traditional, geometric or analytical, strategies is extremely difficult. Therefore, an approach based on learning from examples seems to be more appropriate. This thesis addresses the problem of 3D orientation, aiming to estimate the angular coordinates of a known object from an image shot from any direction. We describe a system based on artificial neural networks to solve this problem in real time. The implementation is performed using a programmable logic device. The digital system described in this paper has the ability to estimate two rotational coordinates of a 3D known object, in ranges from -80 0 to 80 0 . The operation speed allows a real time performance at video rate. The system accuracy can be successively increased by increasing the size of the artificial neural network and using a larger number of training examples [es

A Computed River Flow-Based Turbine Controller on a Programmable Logic Controller for Run-Off River Hydroelectric Systems

Directory of Open Access Journals (Sweden)

Razali Jidin

2017-10-01

Full Text Available The main feature of a run-off river hydroelectric system is a small size intake pond that overspills when river flow is more than turbines’ intake. As river flow fluctuates, a large proportion of the potential energy is wasted due to the spillages which can occur when turbines are operated manually. Manual operation is often adopted due to unreliability of water level-based controllers at many remote and unmanned run-off river hydropower plants. In order to overcome these issues, this paper proposes a novel method by developing a controller that derives turbine output set points from computed mass flow rate of rivers that feed the hydroelectric system. The computed flow is derived by summation of pond volume difference with numerical integration of both turbine discharge flows and spillages. This approach of estimating river flow allows the use of existing sensors rather than requiring the installation of new ones. All computations, including the numerical integration, have been realized as ladder logics on a programmable logic controller. The implemented controller manages the dynamic changes in the flow rate of the river better than the old point-level based controller, with the aid of a newly installed water level sensor. The computed mass flow rate of the river also allows the controller to straightforwardly determine the number of turbines to be in service with considerations of turbine efficiencies and auxiliary power conservation.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

International Nuclear Information System (INIS)

Hu, Kun; Wang, Xu; Li, Feng; Jin, Ge; Lu, Houbing; Liang, Futian

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability

The PLC: a logical development

OpenAIRE

Walker, Mark; Bissell, Christopher; Monk, John

2010-01-01

Programmable Logic Controllers (PLCs) have been used to control industrial processes and equipment for over 40 years, having their first commercially recognised application in 1969. Since then there have been enormous changes in the design and application of PLCs, yet developments were evolutionary rather than radical. The flexibility of the PLC does not confine it to industrial use and it has been used for disparate non-industrial control applications . This article reviews the history, deve...

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

2007-12-18

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Method and apparatus for in-system redundant array repair on integrated circuits

Science.gov (United States)

Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

2008-07-29

Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Design for an IO block array in a tile-based FPGA

International Nuclear Information System (INIS)

Ding Guangxin; Chen Lingdou; Liu Zhongli

2009-01-01

A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process. (semiconductor integrated circuits)

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

2016-05-15

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

Logic qualification of FPGA-based safety-related I and C systems

International Nuclear Information System (INIS)

Hayashi, Toshifumi; Oda, Naotaka; Ito, Toshiaki; Miyazaki, Tadashi; Haren, Yasuhiko

2009-01-01

We established a logic qualification method for FPGA-Based I and C safety-related use in Nuclear Power Plants Systems. The FPGA is a programmable logic device and has advantages that the programming is rigorous, simple verifiable, and the technology is stable. However, logic qualification of FPGA had been an issue to be solved when it is used in the safety-related systems, because FPGA is relatively new technology for the nuclear power industry. We employed a software-life cycle approach, because its development process is similar to that of conventional computer-based systems. There are some differences between the FPGA-Based systems and the computer-based systems in the implementation and integration of logic. We examined the FPGA logic implementation and integration process to identify any FPGA-Based system specific hazards. The identified hazards are (1) small logic errors, (2) timing errors, (3) logic synthesis errors, (4) place and route errors, and (5) logic embedding errors. We took the appropriate countermeasures to mitigate these hazards, and employed this logic qualification method in the qualification of the Power Range Monitor System for BWR Power Plants. (author)

Programmable combinational logic trigger system for high energy particle physics experiments

International Nuclear Information System (INIS)

Platner, E.D.

1976-01-01

A fast logic system designed to select predetermined combinations of three hits in three detectors is described. Central to this system is a random access memory IC that was especially designed for this application

The need for theory evaluation in global citizenship programmes: The case of the GCSA programme.

Science.gov (United States)

Goodier, Sarah; Field, Carren; Goodman, Suki

2018-02-01

Many education programmes lack a documented programme theory. This is a problem for programme planners and evaluators as the ability to measure programme success is grounded in the plausibility of the programme's underlying causal logic. Where the programme theory has not been documented, conducting a theory evaluation offers a foundational evaluation step as it gives an indication of whether the theory behind a programme is sound. This paper presents a case of a theory evaluation of a Global Citizenship programme at a top-ranking university in South Africa, subsequently called the GCSA Programme. This evaluation highlights the need for documented programme theory in global citizenship-type programmes for future programme development. An articulated programme theory produced for the GCSA Programme, analysed against the available social science literature, indicated it is comparable to other such programmes in terms of its overarching framework. What the research found is that most other global citizenship programmes do not have an articulated programme theory. These programmes also do not explicitly link their specific activities to their intended outcomes, making demonstrating impact impossible. In conclusion, we argue that taking a theory-based approach can strengthen and enable outcome evaluations in global citizenship programmes. Copyright © 2017. Published by Elsevier Ltd.

All-spin logic operations: Memory device and reconfigurable computing

Science.gov (United States)

Patra, Moumita; Maiti, Santanu K.

2018-02-01

Exploiting spin degree of freedom of electron a new proposal is given to characterize spin-based logical operations using a quantum interferometer that can be utilized as a programmable spin logic device (PSLD). The ON and OFF states of both inputs and outputs are described by spin state only, circumventing spin-to-charge conversion at every stage as often used in conventional devices with the inclusion of extra hardware that can eventually diminish the efficiency. All possible logic functions can be engineered from a single device without redesigning the circuit which certainly offers the opportunities of designing new generation spintronic devices. Moreover, we also discuss the utilization of the present model as a memory device and suitable computing operations with proposed experimental setups.

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Science.gov (United States)

Al Hassan, Mohammad; Britton, Paul; Hatfield, Glen Spencer; Novack, Steven D.

2017-01-01

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Power consumption of programmable controllers; Energieverbrauch von Prozesssteuerungen (SPS)

Energy Technology Data Exchange (ETDEWEB)

Schalcher, M.; Battaglia, U.; Busch, E.

2003-07-01

This final report for the Swiss Federal Office for Energy addresses the field of programmable logic controllers and thus investigates a topic that has been neglected up to now - the energy consumption of such controllers. The results of measurements made on programmable logic controllers in use both in operational industrial plants and in the Automation Laboratory at the University of Applied Science in Chur, Switzerland are presented, where a detailed analysis was made on a demonstration plant. Also, technical documentation (catalogues) were evaluated and discussed with experts who had practical experience at their disposal. The results of the study are discussed: these show that the power consumption of any particular programmable logic controller is low in comparison to the energy consumption of the processes that are being controlled. Additionally, it was found that the optimisation of newer devices has to a great extent already been realised and that standard solutions for energy optimisation are not easy to put into practice. It is suggested that savings can possibly be made in the controllers by improving the efficiency of their power supply units and by choosing power ratings to better suit the actual power needed.

Methods of software V and V for a programmable logic controller in NPPs

International Nuclear Information System (INIS)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Son, Han Seong; Lee, Jang Soo; Kwon, Kee Choon

2004-01-01

This paper addresses the Verification and Validation (V and V) process and methodology for embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed in the Korea Nuclear Instrumentation and Control System (KNICS) projects. KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System (ESF-CCS) as well as safety-grade PLC. Safety-grade PLC will be a major component that composes the RPS systems and ESF-CCS systems as nuclear instruments and control equipments. This paper describes the V and V guidelines and procedure, V and V environment, V and V process and methodology, and the V and V tools by the KNICS projects. Specially, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase of the software development life cycle. Main activities of the real-time operating system Software Requirement Specification(SRS) V and V of the PLC are the technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14(MOST-KSRG 7/Appendix 15 in Korea will be issued soon) criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to verify the upcoming software life cycle in the KNICS projects. (author)

Field-programmable gate array based controller for multi spot light-addressable potentiometric sensors with integrated signal correction mode

Energy Technology Data Exchange (ETDEWEB)

Werner, Carl Frederik; Schusser, Sebastian; Spelthahn, Heiko [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany); Wagner, Torsten; Yoshinobu, Tatsuo [Tohoku University, Department of Electronic Engineering, 6-6-05 Aramaki Aza Aoba, Aoba-ku, Sendai, Miyagi 980-8579 (Japan); Schoening, Michael J., E-mail: schoening@fh-aachen.de [Aachen University of Applied Sciences, Juelich Campus, Institute of Nano- and Biotechnologies, Heinrich-Mussmann-Strasse 1, 52428 Juelich (Germany); Institute of Bio- and Nanosystems (IBN-2), Research Centre Juelich GmbH, 52425 Juelich (Germany)

2011-11-01

Highlights: > Flexible up-scalable design of a light-addressable potentiometric sensor set-up. > Utilisation of a field-programmable gate array to address LAPS measurement spots. > Measurements in amplitude-mode and phase-mode for different pH solutions. > Amplitude, phase and frequency behaviour of LAPS for single and multiple light stimulus. > Signal calibration method by brightness control to compensated systematic errors. - Abstract: A light-addressable potentiometric sensor (LAPS) can measure the concentration of one or several analytes at the sensor surface simultaneously in a spatially resolved manner. A modulated light pointer stimulates the semiconductor structure at the area of interest and a responding photocurrent can be read out. By simultaneous stimulation of several areas with light pointers of different modulation frequencies, the read out can be performed at the same time. With the new proposed controller electronic based on a field-programmable gate array (FPGA), it is possible to control the modulation frequencies, phase shifts, and light brightness of multiple light pointers independently and simultaneously. Thus, it is possible to investigate the frequency response of the sensor, and to examine the analyte concentration by the determination of the surface potential with the help of current/voltage curves and phase/voltage curves. Additionally, the ability to individually change the light intensities of each light pointer is used to perform signal correction.

A programmable systolic trigger processor for FERA bus data

International Nuclear Information System (INIS)

Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

1992-09-01

A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

International Nuclear Information System (INIS)

Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

1991-01-01

The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

Embedding Logics into Product Logic

Czech Academy of Sciences Publication Activity Database

Baaz, M.; Hájek, Petr; Krajíček, Jan; Švejda, David

1998-01-01

Roč. 61, č. 1 (1998), s. 35-47 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030601 Grant - others:COST(XE) Action 15 Keywords : fuzzy logic * Lukasiewicz logic * Gödel logic * product logic * computational complexity * arithmetical hierarchy Subject RIV: BA - General Mathematics

Design and Implementation of Video Shot Detection on Field Programmable Gate Arrays

Directory of Open Access Journals (Sweden)

Jharna Majumdar

2012-09-01

Full Text Available Video has become an interactive medium of communication in everyday life. The sheer volume of video makes it extremely difficult to browse through and find the required data. Hence extraction of key frames from the video which represents the abstract of the entire video becomes necessary. The aim of the video shot detection is to find the position of the shot boundaries, so that key frames can be selected from each shot for subsequent processing such as video summarization, indexing etc. For most of the surveillance applications like video summery, face recognition etc., the hardware (real time implementation of these algorithms becomes necessary. Here in this paper we present the architecture for simultaneous accessing of consecutive frames, which are then used for the implementation of various Video Shot Detection algorithms. We also present the real time implementation of three video shot detection algorithms using the above mentioned architecture on FPGA (Field Programmable Gate Arrays.

Synchronization in an array of coupled Boolean networks

International Nuclear Information System (INIS)

Li, Rui; Chu, Tianguang

2012-01-01

This Letter presents an analytical study of synchronization in an array of coupled deterministic Boolean networks. A necessary and sufficient criterion for synchronization is established based on algebraic representations of logical dynamics in terms of the semi-tensor product of matrices. Some basic properties of a synchronized array of Boolean networks are then derived for the existence of transient states and the upper bound of the number of fixed points. Particularly, an interesting consequence indicates that a “large” mismatch between two coupled Boolean networks in the array may result in loss of synchrony in the entire system. Examples, including the Boolean model of coupled oscillations in the cell cycle, are given to illustrate the present results. -- Highlights: ► We analytically study synchronization in an array of coupled Boolean networks. ► The study is based on the algebraic representations of logical dynamics. ► A necessary and sufficient algebraic criterion for synchronization is established. ► It reveals some basic properties of a synchronized array of Boolean networks. ► A large mismatch between two coupled networks may result in the loss of synchrony.

Programmable architecture for quantum computing

NARCIS (Netherlands)

Chen, J.; Wang, L.; Charbon, E.; Wang, B.

2013-01-01

A programmable architecture called “quantum FPGA (field-programmable gate array)” (QFPGA) is presented for quantum computing, which is a hybrid model combining the advantages of the qubus system and the measurement-based quantum computation. There are two kinds of buses in QFPGA, the local bus and

Application of Field Programmable Gate Arrays in Instrumentation and Control Systems of Nuclear Power Plants

International Nuclear Information System (INIS)

2016-01-01

Field programmable gate arrays (FPGAs) are gaining increased attention worldwide for application in nuclear power plant (NPP) instrumentation and control (I&C) systems, particularly for safety and safety related applications, but also for non-safety ones. NPP operators and equipment suppliers see potential advantages of FPGA based digital I&C systems as compared to microprocessor based applications. This is because FPGA based systems can be made simpler, more testable and less reliant on complex software (e.g. operating systems), and are easier to qualify for safety and safety related applications. This publication results from IAEA consultancy meetings covering the various aspects, including design, qualification, implementation, licensing, and operation, of FPGA based I&C systems in NPPs

Field programmable gate array based reconfigurable scanning probe/optical microscope.

Science.gov (United States)

Nowak, Derek B; Lawrence, A J; Dzegede, Zechariah K; Hiester, Justin C; Kim, Cliff; Sánchez, Erik J

2011-10-01

The increasing popularity of nanometrology and nanospectroscopy has pushed researchers to develop complex new analytical systems. This paper describes the development of a platform on which to build a microscopy tool that will allow for flexibility of customization to suit research needs. The novelty of the described system lies in its versatility of capabilities. So far, one version of this microscope has allowed for successful near-field and far-field fluorescence imaging with single molecule detection sensitivity. This system is easily adapted for reflection, polarization (Kerr magneto-optical (MO)), Raman, super-resolution techniques, and other novel scanning probe imaging and spectroscopic designs. While collecting a variety of forms of optical images, the system can simultaneously monitor topographic information of a sample with an integrated tuning fork based shear force system. The instrument has the ability to image at room temperature and atmospheric pressure or under liquid. The core of the design is a field programmable gate array (FPGA) data acquisition card and a single, low cost computer to control the microscope with analog control circuitry using off-the-shelf available components. A detailed description of electronics, mechanical requirements, and software algorithms as well as examples of some different forms of the microscope developed so far are discussed.

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Science.gov (United States)

Al Hassan, Mohammad; Novack, Steven D.; Hatfield, Glen S.; Britton, Paul

2017-01-01

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

System and method for programmable bank selection for banked memory subsystems

Energy Technology Data Exchange (ETDEWEB)

Blumrich, Matthias A. (Ridgefield, CT); Chen, Dong (Croton on Hudson, NY); Gara, Alan G. (Mount Kisco, NY); Giampapa, Mark E. (Irvington, NY); Hoenicke, Dirk (Seebruck-Seeon, DE); Ohmacht, Martin (Yorktown Heights, NY); Salapura, Valentina (Chappaqua, NY); Sugavanam, Krishnan (Mahopac, NY)

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Generalized look-ahead number conversion from signed digit to complement representation with optical logic operations

Science.gov (United States)

Qian, Feng; Li, Guoqiang

2001-12-01

In this paper a generalized look-ahead logic algorithm for number conversion from signed-digit to its complement representation is developed. By properly encoding the signed digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quaternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using electron-trapping device is employed, which is suitable for realizing complex logic functions in the form of sum-of-product. The proposed algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

Explicit logic circuits predict local properties of the neocortex's physiology and anatomy.

Directory of Open Access Journals (Sweden)

Lane Yoder

Full Text Available BACKGROUND: Two previous articles proposed an explicit model of how the brain processes information by its organization of synaptic connections. The family of logic circuits was shown to generate neural correlates of complex psychophysical phenomena in different sensory systems. METHODOLOGY/PRINCIPAL FINDINGS: Here it is shown that the most cost-effective architectures for these networks produce correlates of electrophysiological brain phenomena and predict major aspects of the anatomical structure and physiological organization of the neocortex. The logic circuits are markedly efficient in several respects and provide the foundation for all of the brain's combinational processing of information. CONCLUSIONS/SIGNIFICANCE: At the local level, these networks account for much of the physical structure of the neocortex as well its organization of synaptic connections. Electronic implementations of the logic circuits may be more efficient than current electronic logic arrays in generating both Boolean and fuzzy logic.

Reconfigurable logic via gate controlled domain wall trajectory in magnetic network structure

Science.gov (United States)

Murapaka, C.; Sethi, P.; Goolaup, S.; Lew, W. S.

2016-01-01

An all-magnetic logic scheme has the advantages of being non-volatile and energy efficient over the conventional transistor based logic devices. In this work, we present a reconfigurable magnetic logic device which is capable of performing all basic logic operations in a single device. The device exploits the deterministic trajectory of domain wall (DW) in ferromagnetic asymmetric branch structure for obtaining different output combinations. The programmability of the device is achieved by using a current-controlled magnetic gate, which generates a local Oersted field. The field generated at the magnetic gate influences the trajectory of the DW within the structure by exploiting its inherent transverse charge distribution. DW transformation from vortex to transverse configuration close to the output branch plays a pivotal role in governing the DW chirality and hence the output. By simply switching the current direction through the magnetic gate, two universal logic gate functionalities can be obtained in this device. Using magnetic force microscopy imaging and magnetoresistance measurements, all basic logic functionalities are demonstrated. PMID:26839036

V and V methods of a safety-critical software for a programmable logic controller

Energy Technology Data Exchange (ETDEWEB)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Kong, Seung Ju [Korea Hydro and Nuclear Power Co., Ltd, Daejeon (Korea, Republic of)

2005-11-15

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects.

V and V methods of a safety-critical software for a programmable logic controller

International Nuclear Information System (INIS)

Kim, Jang Yeol; Lee, Young Jun; Cha, Kyung Ho; Cheon, Se Woo; Lee, Jang Soo; Kwon, Kee Choon; Kong, Seung Ju

2005-01-01

This paper addresses the Verification an Validation(V and V) process and the methodology for an embedded real time software of a safety-grade Programmable Logic Controller(PLC). This safety-grade PLC is being developed as one of the Korean Nuclear Instrumentation and Control System(KNICS) project KNICS projects are developing a Reactor Protection System(RPS) and an Engineered Safety Feature-Component Control System(ESF-CCS) as well as a safety-grade PLC. The safety-grade PLC will be a major component that encomposes the RPS systems and the ESF-CCS systems as nuclear instruments and control equipment. This paper describes the V and V guidelines an procedures, V and V environment, V and V process and methodology, and the V and V tools in the KNICS projects. Specifically, it describes the real-time operating system V and V experience which corresponds to the requirement analysis phase, design phase and the implementation and testing phase of the software development life cycle. Main activities of the V and V for the PLC system software are a technical evaluation, licensing suitability evaluation, inspection and traceability analysis, formal verification, software safety analysis, and a software configuration management. The proposed V and V methodology satisfies the Standard Review Plan(SRP)/Branch Technical Position(BTP)-14 criteria for the safety software in nuclear power plants. The proposed V and V methodology is going to be used to verify the upcoming software life cycle in the KNICS projects

Gas Sensors Characterization and Multilayer Perceptron (MLP) Hardware Implementation for Gas Identification Using a Field Programmable Gate Array (FPGA)

Science.gov (United States)

Benrekia, Fayçal; Attari, Mokhtar; Bouhedda, Mounir

2013-01-01

This paper develops a primitive gas recognition system for discriminating between industrial gas species. The system under investigation consists of an array of eight micro-hotplate-based SnO2 thin film gas sensors with different selectivity patterns. The output signals are processed through a signal conditioning and analyzing system. These signals feed a decision-making classifier, which is obtained via a Field Programmable Gate Array (FPGA) with Very High-Speed Integrated Circuit Hardware Description Language. The classifier relies on a multilayer neural network based on a back propagation algorithm with one hidden layer of four neurons and eight neurons at the input and five neurons at the output. The neural network designed after implementation consists of twenty thousand gates. The achieved experimental results seem to show the effectiveness of the proposed classifier, which can discriminate between five industrial gases. PMID:23529119

Optical programmable metamaterials

Science.gov (United States)

Gong, Cheng; Zhang, Nan; Dai, Zijie; Liu, Weiwei

2018-02-01

We suggest and demonstrate the concept of optical programmable metamaterials which can configure the device's electromagnetic parameters by the programmable optical stimuli. In such metamaterials, the optical stimuli produced by a FPGA controlled light emitting diode array can switch or combine the resonance modes which are coupled in. As an example, an optical programmable metamaterial terahertz absorber is proposed. Each cell of the absorber integrates four meta-rings (asymmetric 1/4 rings) with photo-resistors connecting the critical gaps. The principle and design of the metamaterials are illustrated and the simulation results demonstrate the functionalities for programming the metamaterial absorber to change its bandwidth and resonance frequency.

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

Science.gov (United States)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

Science.gov (United States)

Li, Guoqiang; Qian, Feng

2001-11-01

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed- digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

International Nuclear Information System (INIS)

Song, S. H.; Lee, M. S.; Kim, T. H.; Park, C. H.; Park, S. P.; Kim, H. S.

2014-01-01

As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system

A Case Study on Cyber-security Program for the Programmable Logic Controller of Modern NPPs

Energy Technology Data Exchange (ETDEWEB)

Song, S. H. [Korea University, Seoul (Korea, Republic of); Lee, M. S.; Kim, T. H. [Formal Work Inc., Seoul (Korea, Republic of); Park, C. H. [LINE Corp., Tokyo (Japan); Park, S. P. [Ahnlab Inc., Seoul (Korea, Republic of); Kim, H. S. [Sejong University, Seoul (Korea, Republic of)

2014-08-15

As instrumentation and control (I and C) systems for modern Nuclear Power Plants (NPPs) have been digitalized to cope with their growing complexity, the cyber-security has become an important issue. To protect the I and C systems adequately from cyber threats, such as Stuxnet that attacked Iran's nuclear facilities, regulations of many countries require a cyber-security program covering all the life cycle phases of the system development, from the concept to the retirement. This paper presents a case study of cyber-security program that has been performed during the development of the programmable logic controller (PLC) for modern NPPs of Korea. In the case study, a cyber-security plan, including technical, management, and operational controls, was established through a security risk assessment. Cyber-security activities, such as development of security functions and periodic inspections, were conducted according to the plan: the security functions were applied to the PLC as the technical controls, and periodic inspections and audits were held to check the security of the development environment, as the management and operational controls. A final penetration test was conducted to inspect all the security problems that had been issued during the development. The case study has shown that the systematic cyber-security program detected and removed the vulnerabilities of the target system, which could not be found otherwise, enhancing the cyber-security of the system.

Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

CERN Document Server

Sivasubramaniyan, Sriram

Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

Memory states in small arrays of Josephson junctions

Energy Technology Data Exchange (ETDEWEB)

Braiman, Yehuda [ORNLOak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Neschke, Brendan [ORNLOak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Nair, Niketh S. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computer Science and Mathematics Division, Computing and Computational Science Directorate; Univ. of Tennessee, Knoxville, TN (United States). Dept. of Mechanical, Aerospace, and Biomedical Engineering; Imam, Neena [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Computing and Computational Science Directorat; Glowinski, R. [Univ. of Houston, TX (United States). Dept. of Mathematics

2017-11-30

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

Implementation of FPGA-Based Diverse Protection System

International Nuclear Information System (INIS)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min

2015-01-01

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails

Implementation of FPGA-Based Diverse Protection System

Energy Technology Data Exchange (ETDEWEB)

Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

2015-10-15

Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

Development of measurement system for radiation effect on static random access memory based field programmable gate array

International Nuclear Information System (INIS)

Yao Zhibin; He Baoping; Zhang Fengqi; Guo Hongxia; Luo Yinhong; Wang Yuanming; Zhang Keying

2009-01-01

Based on the detailed investigation in field programmable gate array(FPGA) radiation effects theory, a measurement system for radiation effects on static random access memory(SRAM)-based FPGA was developed. The testing principle of internal memory, function and power current was introduced. The hardware and software implement means of system were presented. Some important parameters for radiation effects on SRAM-based FPGA, such as configuration RAM upset section, block RAM upset section, function fault section and single event latchup section can be gained with this system. The transmission distance of the system can be over 50 m and the maximum number of tested gates can reach one million. (authors)

Data Logic

DEFF Research Database (Denmark)

Nilsson, Jørgen Fischer

A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students......A Gentle introduction to logical languages, logical modeling, formal reasoning and computational logic for computer science and software engineering students...

The screening approach for review of accident management programmes

International Nuclear Information System (INIS)

Misak, J.

1999-01-01

In this lecture the screening approach for review of accident management programmes are presented. It contains objective trees for accident management: logic structure of the approach; objectives and safety functions for accident management; safety principles

Extending Value Logic Thinking to Value Logic Portfolios

DEFF Research Database (Denmark)

Andersen, Poul Houman; Ritter, Thomas

2014-01-01

Based on value creation logic theory (Stabell & Fjeldstad, 1998), this paper suggests an extension of the original Stabell & Fjeldstad model by an additional fourth value logic, the value system logic. Furthermore, instead of only allowing one dominant value creation logic for a given firm...... or transaction, an understanding of firms and transactions as a portfolio of value logics (i.e. an interconnected coexistence of different value creation logics) is proposed. These additions to the original value creation logic theory imply interesting avenues for both, strategic decision making in firms...

Nanoeletromechanical switch and logic circuits formed therefrom

Science.gov (United States)

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Ferritin-Templated Quantum-Dots for Quantum Logic Gates

Science.gov (United States)

Choi, Sang H.; Kim, Jae-Woo; Chu, Sang-Hyon; Park, Yeonjoon; King, Glen C.; Lillehei, Peter T.; Kim, Seon-Jeong; Elliott, James R.

2005-01-01

Quantum logic gates (QLGs) or other logic systems are based on quantum-dots (QD) with a stringent requirement of size uniformity. The QD are widely known building units for QLGs. The size control of QD is a critical issue in quantum-dot fabrication. The work presented here offers a new method to develop quantum-dots using a bio-template, called ferritin, that ensures QD production in uniform size of nano-scale proportion. The bio-template for uniform yield of QD is based on a ferritin protein that allows reconstitution of core material through the reduction and chelation processes. One of the biggest challenges for developing QLG is the requirement of ordered and uniform size of QD for arrays on a substrate with nanometer precision. The QD development by bio-template includes the electrochemical/chemical reconsitution of ferritins with different core materials, such as iron, cobalt, manganese, platinum, and nickel. The other bio-template method used in our laboratory is dendrimers, precisely defined chemical structures. With ferritin-templated QD, we fabricated the heptagonshaped patterned array via direct nano manipulation of the ferritin molecules with a tip of atomic force microscope (AFM). We also designed various nanofabrication methods of QD arrays using a wide range manipulation techniques. The precise control of the ferritin-templated QD for a patterned arrangement are offered by various methods, such as a site-specific immobilization of thiolated ferritins through local oxidation using the AFM tip, ferritin arrays induced by gold nanoparticle manipulation, thiolated ferritin positioning by shaving method, etc. In the signal measurements, the current-voltage curve is obtained by measuring the current through the ferritin, between the tip and the substrate for potential sweeping or at constant potential. The measured resistance near zero bias was 1.8 teraohm for single holoferritin and 5.7 teraohm for single apoferritin, respectively.

Operating experiences with programmable logic controller (PLC) system of Indian Pressurised Heavy Water Reactors (PHWR)

International Nuclear Information System (INIS)

Ughade, A.V.; Singh, Ranjeet; Bhattacharya, P.K.; Kulkarni, R.K.; Chandra, Umesh

2005-01-01

PLC system was introduced for the first time in Kaiga-1,2 and RAPS-3,4 Nuclear Power Plants (NPPs) for Station Logic Control of Non Safety Related (NSR) and Safety related (SR) systems. However, the safety system logics are still relay based. The experience on the deployment of PLC system, which is computer-based, has brought out various implementation issues. This paper give details of such experiences, the solutions emerged and applied for plants under operation/construction. (author)

Three-valued logics in modal logic

NARCIS (Netherlands)

Kooi, Barteld; Tamminga, Allard

2013-01-01

Every truth-functional three-valued propositional logic can be conservatively translated into the modal logic S5. We prove this claim constructively in two steps. First, we define a Translation Manual that converts any propositional formula of any three-valued logic into a modal formula. Second, we

Towards a Formal Occurrence Logic based on Predicate Logic

DEFF Research Database (Denmark)

Badie, Farshad; Götzsche, Hans

2015-01-01

In this discussion we will concentrate on the main characteristics of an alternative kind of logic invented by Hans Götzsche: Occurrence Logic, which is not based on truth functionality. Our approach is based on temporal logic developed and elaborated by A. N. Prior. We will focus on characterising...... argumentation based on formal Occurrence Logic concerning events and occurrences, and illustrate the relations between Predicate Logic and Occurrence Logic. The relationships (and dependencies) is conducive to an approach that can analyse the occurrences of ”logical statements based on different logical...... principles” in different moments. We will also conclude that the elaborated Götzsche’s Occurrence Logic could be able to direct us to a truth-functional independent computer-based logic for analysing argumentation based on events and occurrences....

Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

Science.gov (United States)

Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

2010-12-01

An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

Logic programming extensions of Horn clause logic

Directory of Open Access Journals (Sweden)

Ron Sigal

1988-11-01

Full Text Available Logic programming is now firmly established as an alternative programming paradigm, distinct and arguably superior to the still dominant imperative style of, for instance, the Algol family of languages. The concept of a logic programming language is not precisely defined, but it is generally understood to be characterized buy: a declarative nature; foundation in some well understood logical system, e.g., first order logic.

Intuitionistic hybrid logic

DEFF Research Database (Denmark)

Braüner, Torben

2011-01-01

Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area.......Intuitionistic hybrid logic is hybrid modal logic over an intuitionistic logic basis instead of a classical logical basis. In this short paper we introduce intuitionistic hybrid logic and we give a survey of work in the area....

D0 General Support: The Use of Programmable Logic Controllers (PLCs) at D0

International Nuclear Information System (INIS)

Hance, R.

2000-01-01

With the exception of control of heating, ventilation, and air conditioning (HVAC) ventilation fans, and their shutdown in the case of smoke in the ducts, all implementations of Programmable Logic Controllers (PLCs) in Dzero have been made within the fundamental premise that no uncertified PLC apparatus shall be entrusted with the safety of equipment or personnel. Thus although PLCs are used to control and monitor all manner of intricate equipment, simple hardware interlocks and relief devices provide basic protection against component failure, control failure, or inappropriate control operation. Nevertheless, this report includes two observations as follows: (1) It may be prudent to reconfigure the link between the Pyrotronics system and the HVAC system such that the Pyrotronics system provides interlocks to the ventilation fans instead of control inputs to the uncertified HVAC PLCs. Although the Pyrotronics system is certified and maintained to life safety standards, the HVAC system is not. A hardware or software failure of the HVAC system probably should not be allowed to result in the situation where the ventilation fans in a smoke filled duct continue to operate. Dan Markley is investigating this matter. (2) It may also be prudent to examine the network security of those systems connected to the Fermilab WAN (HVAC, Cryo, and Solenoid Controls). Even though the impact of a successful hack might only be to operations, it might nevertheless be disruptive and could be expensive. The risks should perhaps be analyzed. One of the most attractive features of these systems, from a user's viewpoint, is their unlimited networking. The unlimited networking that makes the systems so convenient to legitimate access also makes them vulnerable to illegitimate access.

A programmable artificial retina

International Nuclear Information System (INIS)

Bernard, T.M.; Zavidovique, B.Y.; Devos, F.J.

1993-01-01

An artificial retina is a device that intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environments and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare Boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to 3 b, the authors have demonstrated both the technological practicality and the computational efficiency of this programmable Boolean retina concept. Using semi-static shifting structures together with some interaction circuitry, a minimal retina Boolean processor can be built with less than 30 transistors and controlled by as few as 6 global clock signals. The successful design, integration, and test of such a 65x76 Boolean retina on a 50-mm 2 CMOS 2-μm circuit are presented

Classical logic and logicism in human thought

OpenAIRE

Elqayam, Shira

2012-01-01

This chapter explores the role of classical logic as a theory of human reasoning. I distinguish between classical logic as a normative, computational and algorithmic system, and review its role is theories of human reasoning since the 1960s. The thesis I defend is that psychological theories have been moving further and further away from classical logic on all three levels. I examine some prominent example of logicist theories, which incorporate logic in their psychological account, includin...

FPGA based Fuzzy Logic Controller for plasma position control in ADITYA Tokamak

International Nuclear Information System (INIS)

Suratia, Pooja; Patel, Jigneshkumar; Rajpal, Rachana; Kotia, Sorum; Govindarajan, J.

2012-01-01

Highlights: ► Evaluation and comparison of the working performance of FLC is done with that of PID Controller. ► FLC is designed using MATLAB Fuzzy Logic Toolbox, and validated on ADITYA RZIP model. ► FLC was implemented on a FPGA. The close-loop testing is done by interfacing FPGA to MATLAB/Simulink. ► Developed FLC controller is able to maintain the plasma column within required range of ±0.05 m and was found to give robust control against various disturbances and faster and smoother response compared to PID Controller. - Abstract: Tokamaks are the most promising devices for obtaining nuclear fusion energy from high-temperature, ionized gas termed as Plasma. The successful operation of tokamak depends on its ability to confine plasma at the geometric center of vacuum vessel with sufficient stability. The quality of plasma discharge in ADITYA Tokamak is strongly related to the radial position of the plasma column in the vacuum vessel. If the plasma column approaches too near to the wall of vacuum vessel, it leads to minor or complete disruption of plasma. Hence the control of plasma position throughout the entire plasma discharge duration is a fundamental requirement. This paper describes Fuzzy Logic Controller (FLC) which is designed for radial plasma position control. This controller is tested and evaluated on the ADITYA RZIP control model. The performance of this FLC was compared with that of Proportional–Integral–Derivative (PID) Controller and the response was found to be faster and smoother. FLC was implemented on a Field Programmable Gate Array (FPGA) chip with the use of a Very High-Speed Integrated-Circuits Hardware Description-Language (VHDL).

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Science.gov (United States)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Nucleic acid programmable protein array a just-in-time multiplexed protein expression and purification platform.

Science.gov (United States)

Qiu, Ji; LaBaer, Joshua

2011-01-01

Systematic study of proteins requires the availability of thousands of proteins in functional format. However, traditional recombinant protein expression and purification methods have many drawbacks for such study at the proteome level. We have developed an innovative in situ protein expression and capture system, namely NAPPA (nucleic acid programmable protein array), where C-terminal tagged proteins are expressed using an in vitro expression system and efficiently captured/purified by antitag antibodies coprinted at each spot. The NAPPA technology presented in this chapter enable researchers to produce and display fresh proteins just in time in a multiplexed high-throughput fashion and utilize them for various downstream biochemical researches of interest. This platform could revolutionize the field of functional proteomics with it ability to produce thousands of spatially separated proteins in high density with narrow dynamic rand of protein concentrations, reproducibly and functionally. Copyright © 2011 Elsevier Inc. All rights reserved.

CMOS gate array characterization procedures

Science.gov (United States)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

The REGENT-PLR-precompiler, execution logic

International Nuclear Information System (INIS)

Enderle, G.; Steil, A.

1976-11-01

The REGENT-PLR-Precompiler is part of the integrated CAD-system REGENT. The algorithms of REGENT-subsystems are contained in modular program units, modules. Beyond the possibilities of the base language PL/1 the programmer of the moduls can be use the REGENT-facilities; dynamic program linkage, dynamic data management and error message handling. For easy and safe use of these facilities they are realized as PL/1-extensions. The PLR-Precompiler is able to translate the extensions into PL/1. This report contains a description of the internal program logic of the REGENT-PLR-Precompiler. (orig.) [de

Integrated development environment for fuzzy logic applications

Science.gov (United States)

Pagni, Andrea; Poluzzi, Rinaldo; Rizzotto, GianGuido; Lo Presti, Matteo

1993-12-01

During the last five years, Fuzzy Logic has gained enormous popularity, both in the academic and industrial worlds, breaking up the traditional resistance against changes thanks to its innovative approach to problems formalization. The success of this new methodology is pushing the creation of a brand new class of devices, called Fuzzy Machines, to overcome the limitations of traditional computing systems when acting as Fuzzy Systems and adequate Software Tools to efficiently develop new applications. This paper aims to present a complete development environment for the definition of fuzzy logic based applications. The environment is also coupled with a sophisticated software tool for semiautomatic synthesis and optimization of the rules with stability verifications. Later it is presented the architecture of WARP, a dedicate VLSI programmable chip allowing to compute in real time a fuzzy control process. The article is completed with two application examples, which have been carried out exploiting the aforementioned tools and devices.

Logical labyrinths

CERN Document Server

Smullyan, Raymond

2008-01-01

This book features a unique approach to the teaching of mathematical logic by putting it in the context of the puzzles and paradoxes of common language and rational thought. It serves as a bridge from the author's puzzle books to his technical writing in the fascinating field of mathematical logic. Using the logic of lying and truth-telling, the author introduces the readers to informal reasoning preparing them for the formal study of symbolic logic, from propositional logic to first-order logic, a subject that has many important applications to philosophy, mathematics, and computer science. T

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

International Nuclear Information System (INIS)

An, M.; Zhang, W.; Xiao, L.; Gao, C.; Chen, C.; Huang, G.; Ji, R.; Liu, J.; Pei, H.; Sun, X.; Wang, K.; Yang, P.; Zhou, W.; Han, M.; Mei, Y.; Li, X.; Sun, Q.

2017-01-01

We present the detailed study of the digital readout of Topmetal-II - CMOS pixel direct charge sensor. Topmetal-II - is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

In situ synthesis of protein arrays.

Science.gov (United States)

He, Mingyue; Stoevesandt, Oda; Taussig, Michael J

2008-02-01

In situ or on-chip protein array methods use cell free expression systems to produce proteins directly onto an immobilising surface from co-distributed or pre-arrayed DNA or RNA, enabling protein arrays to be created on demand. These methods address three issues in protein array technology: (i) efficient protein expression and availability, (ii) functional protein immobilisation and purification in a single step and (iii) protein on-chip stability over time. By simultaneously expressing and immobilising many proteins in parallel on the chip surface, the laborious and often costly processes of DNA cloning, expression and separate protein purification are avoided. Recently employed methods reviewed are PISA (protein in situ array) and NAPPA (nucleic acid programmable protein array) from DNA and puromycin-mediated immobilisation from mRNA.

Logical inference techniques for loop parallelization

KAUST Repository

Oancea, Cosmin E.; Rauchwerger, Lawrence

2012-01-01

This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = Ø, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) ⇒ S = Ø). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F(S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECTCLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers. Copyright © 2012 ACM.

Logical inference techniques for loop parallelization

KAUST Repository

Oancea, Cosmin E.

2012-01-01

This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop\\'s memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = Ø, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) ⇒ S = Ø). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F(S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECTCLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers. Copyright © 2012 ACM.

SPAD array chips with full frame readout for crystal characterization

Energy Technology Data Exchange (ETDEWEB)

Fischer, Peter; Blanco, Roberto; Sacco, Ilaria; Ritzert, Michael [Heidelberg University (Germany); Weyers, Sascha [Fraunhofer Institute for Microelectronic Circuits and Systems (Germany)

2015-05-18

We present single photon sensitive 2D camera chips containing 88x88 avalanche photo diodes which can be read out in full frame mode with up to 400.000 frames per second. The sensors have an imaging area of ~5mm x 5mm covered by square pixels of ~56µm x 56µm with a ~55% fill factor in the latest chip generation. The chips contain a self triggering logic with selectable (column) multiplicities of up to >=4 hits within an adjustable coincidence time window. The photon accumulation time window is programmable as well. First prototypes have demonstrated low dark count rates of <50kHz/mm2 (SPAD area) at 10 degree C for 10% masked pixels. One chip version contains an automated readout of the photon cluster position. The readout of the detailed photon distribution for single events allows the characterization of light sharing, optical crosstalk etc., in crystals or crystal arrays as they are used in PET instrumentation. This knowledge could lead to improvements in spatial or temporal resolution.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.

Science.gov (United States)

Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai

2017-08-02

Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.

A new data acquisition and imaging system for nuclear microscopy based on a Field Programmable Gate Array card

International Nuclear Information System (INIS)

Bettiol, A.A.; Udalagama, C.; Watt, F.

2009-01-01

The introduction of the new Field Programmable Gate Array (FPGA) cards by National Instruments has made it possible for the first time to develop reconfigurable custom data acquisition hardware easily with the LabVIEW programming environment. Data acquisition issues such as precise timing for scanning and operating system latencies can now be easily overcome using this new technology because the data acquisition software is embedded in the FPGA chip on the card. In this paper we present the first results of the new data acquisition system developed at the Centre for Ion Beam Applications (CIBA), National University of Singapore using the new National Instruments cards in conjunction with rack mountable Wilkinson type ADCs.

What makes children behave aggressively? The inner logic of Dutch children in special education

NARCIS (Netherlands)

Visser, M.; Singer, E.; van Geert, P.L.C.; Kunnen, S.E.

2009-01-01

The ambiguous results of existing intervention programmes show the need for new ways in research on aggression among children. The present study focuses on the children's own perspective on their aggressive behaviour. Based on a constructivist approach, the inner logic of narratives about peer

Efficient processing of two-dimensional arrays with C or C++

Science.gov (United States)

Donato, David I.

2017-07-20

Because fast and efficient serial processing of raster-graphic images and other two-dimensional arrays is a requirement in land-change modeling and other applications, the effects of 10 factors on the runtimes for processing two-dimensional arrays with C and C++ are evaluated in a comparative factorial study. This study’s factors include the choice among three C or C++ source-code techniques for array processing; the choice of Microsoft Windows 7 or a Linux operating system; the choice of 4-byte or 8-byte array elements and indexes; and the choice of 32-bit or 64-bit memory addressing. This study demonstrates how programmer choices can reduce runtimes by 75 percent or more, even after compiler optimizations. Ten points of practical advice for faster processing of two-dimensional arrays are offered to C and C++ programmers. Further study and the development of a C and C++ software test suite are recommended.Key words: array processing, C, C++, compiler, computational speed, land-change modeling, raster-graphic image, two-dimensional array, software efficiency

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

Science.gov (United States)

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

Smart trigger logic for focal plane arrays

Science.gov (United States)

Levy, James E; Campbell, David V; Holmes, Michael L; Lovejoy, Robert; Wojciechowski, Kenneth; Kay, Randolph R; Cavanaugh, William S; Gurrieri, Thomas M

2014-03-25

An electronic device includes a memory configured to receive data representing light intensity values from pixels in a focal plane array and a processor that analyzes the received data to determine which light values correspond to triggered pixels, where the triggered pixels are those pixels that meet a predefined set of criteria, and determines, for each triggered pixel, a set of neighbor pixels for which light intensity values are to be stored. The electronic device also includes a buffer that temporarily stores light intensity values for at least one previously processed row of pixels, so that when a triggered pixel is identified in a current row, light intensity values for the neighbor pixels in the previously processed row and for the triggered pixel are persistently stored, as well as a data transmitter that transmits the persistently stored light intensity values for the triggered and neighbor pixels to a data receiver.

Development and simulation of soft morphological operators for a field programmable gate array

Science.gov (United States)

Tickle, Andrew J.; Harvey, Paul K.; Smith, Jeremy S.; Wu, Q. Henry

2013-04-01

In image processing applications, soft mathematical morphology (MM) can be employed for both binary and grayscale systems and is derived from set theory. Soft MM techniques have improved behavior over standard morphological operations in noisy environments, as they can preserve small details within an image. This makes them suitable for use in image processing applications on portable field programmable gate arrays for tasks such as robotics and security. We explain how the systems were developed using Altera's DSP Builder in order to provide optimized code for the many different devices currently on the market. Also included is how the circuits can be inserted and combined with previously developed work in order to increase their functionality. The testing procedures involved loading different images into these systems and analyzing the outputs against MATLAB-generated validation images. A set of soft morphological operations are described, which can then be applied to various tasks and easily modified in size via altering the line buffer settings inside the system to accommodate a range of image attributes ranging from image sizes such as 320×240 pixels for basic webcam imagery up to high quality 4000×4000 pixel images for military applications.

Monolithic microwave integrated circuit with integral array antenna

International Nuclear Information System (INIS)

Stockton, R.J.; Munson, R.E.

1984-01-01

A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

Science.gov (United States)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

A DNAzyme-mediated logic gate for programming molecular capture and release on DNA origami.

Science.gov (United States)

Li, Feiran; Chen, Haorong; Pan, Jing; Cha, Tae-Gon; Medintz, Igor L; Choi, Jong Hyun

2016-06-28

Here we design a DNA origami-based site-specific molecular capture and release platform operated by a DNAzyme-mediated logic gate process. We show the programmability and versatility of this platform with small molecules, proteins, and nanoparticles, which may also be controlled by external light signals.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Xu Zhouxiang; Zhang Xian; Huang Kaikai; Lu Xuanhui [Physics Department, Zhejiang University, Hangzhou, 310027 (China)

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

The JOSHUA (J80) system programmer`s manual

Energy Technology Data Exchange (ETDEWEB)

Smetana, A.O.; McCort, J.T.; Westmoreland, B.W.

1993-08-01

The JOSHUA system routines (JS routines) can be used to manage a JOSHUA data base and execute JOSHUA modules on VAX/VMS and IBM/MVS computer systems. This manual provides instructions for using the JS routines and information about the internal data structures and logic used by the routines. It is intended for use primarily by JOSHUA systems programmers, however, advanced applications programmers may also find it useful. The JS routines are, as far as possible, written in ANSI FORTRAN 77 so that they are easily maintainable and easily portable to different computer systems. Nevertheless, the JOSHUA system provides features that are not available in ANSI FORTRAN 77, notably dynamic module execution and a data base of named, variable length, unformatted records, so some parts of the routines are coded in nonstandard FORTRAN or assembler (as a last resort). In most cases, the nonstandard sections of code are different for each computer system. To make it easy for programmers using the JS routines to avoid naming conflicts, the JS routines and common block all have six character names that begin with the characters {open_quotes}JS.{close_quotes} Before using this manual, one should be familiar with the JOSHUA system as described in {open_quotes}The JOSHUA Users` Manual,{close_quotes} ANSI FORTRAN 77, and at least one of the computer systems for which the JS routines have been implemented.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

Energy Technology Data Exchange (ETDEWEB)

O' Gorman, T.; Gibson, K. J.; Snape, J. A. [York Plasma Institute, Department of Physics, University of York, York YO10 5DD (United Kingdom); Naylor, G.; Huang, B.; McArdle, G. J.; Scannell, R.; Shibaev, S.; Thomas-Davies, N. [EURATOM/CCFE Fusion Association, Culham Science Centre, Oxfordshire OX14 3DB (United Kingdom)

2012-10-15

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate trigger from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m/n= 2/1 NTMs instabilities on a number of MAST discharges.

Evaluation of the Leon3 soft-core processor within a Xilinx radiation-hardened field-programmable gate array.

Energy Technology Data Exchange (ETDEWEB)

Learn, Mark Walter

2012-01-01

The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

Integrated evaluation framework. Based on the logical framework approach for project cycle management

International Nuclear Information System (INIS)

1996-11-01

This Integrated Evaluation Framework (IEF) was developed by TC Evaluation with the aim of presenting in a comprehensive manner the logic of thinking used when evaluating projects and programmes. Thus, in the first place, the intended audience for this report are evaluation officers, so that when applying the evaluation procedures and check lists, data can be organized following a systematic and logical scheme and conclusions can be derived ''objectively''. The value of such a framework for reporting on performance and in providing a quality reference for disbursements represents one of its major advantages. However, when developing and applying the IEF, it was realized that a Logical Framework Approach (LFA), like the one upon which the IEF is based, needs to be followed throughout the project life cycle, from the Country Programme Framework planning stage, through project design and implementation. Then, the helpful consequences flow into project design quality and smooth implementation. It is only in such an environment that meaningful and consistent evaluation can take place. Therefore the main audience for this report are Agency staff involved in planning, designing and implementing TC projects as well as their counterparts in Member States. In this understanding, the IEF was subjected to review by a consultants meeting, which included both external consultants and Agency staff. This Consultants Review Meeting encouraged the Secretariat to further adopt the LFA into the TC management process

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Saturday Programme for CineGlobe

CERN Multimedia

Marcelloni De Oliveira, Claudia

2015-01-01

The saturday programme had a special kids session, the kick of the Science Storytelling Hackaton and the Award Ceremony WINNERS 2015 The Jury Prize for documentary: Fecal Matters, Paul Gallasch - AU The Jury Prize for Fiction: Hybris, Arjan Brentjes - NL Award of Excellence in Narrative: Final Draft, Scott Calonico - UK The Audience Award for documentary: Logically policed, Damiano Petrucci - UK The Audience Award for Fiction: Slapkick, Dat Nguyen Chon-- DE The Special Prize "Time Vizualisation": Danielle, Anthony Cerniello - US

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

Science.gov (United States)

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Programmable full-adder computations in communicating three-dimensional cell cultures.

Science.gov (United States)

Ausländer, David; Ausländer, Simon; Pierrat, Xavier; Hellmann, Leon; Rachid, Leila; Fussenegger, Martin

2018-01-01

Synthetic biologists have advanced the design of trigger-inducible gene switches and their assembly into input-programmable circuits that enable engineered human cells to perform arithmetic calculations reminiscent of electronic circuits. By designing a versatile plug-and-play molecular-computation platform, we have engineered nine different cell populations with genetic programs, each of which encodes a defined computational instruction. When assembled into 3D cultures, these engineered cell consortia execute programmable multicellular full-adder logics in response to three trigger compounds.

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Directory of Open Access Journals (Sweden)

Shipra Upadhyay

2013-01-01

Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

Raising a Programmer: Teaching Saudi Children How to Code

Science.gov (United States)

Meccawy, Maram

2017-01-01

Teaching computer coding to children from a young age provides with them a competitive advantage for the future in a continually changing workplace. Programming strengthens logical and critical thinking as well as problem-solving skills, which lead to creative solutions for today's problems. The Little Programmer is an application for mobile…

Logical Characterisation of Ontology Construction using Fuzzy Description Logics

DEFF Research Database (Denmark)

Badie, Farshad; Götzsche, Hans

had the extension of ontologies with Fuzzy Logic capabilities which plan to make proper backgrounds for ontology driven reasoning and argumentation on vague and imprecise domains. This presentation conceptualises learning from fuzzy classes using the Inductive Logic Programming framework. Then......, employs Description Logics in characterising and analysing fuzzy statements. And finally, provides a conceptual framework describing fuzzy concept learning in ontologies using the Inductive Logic Programming....

Manipulating potential wells in Logical Stochastic Resonance to obtain XOR logic

International Nuclear Information System (INIS)

Storni, Remo; Ando, Hiroyasu; Aihara, Kazuyuki; Murali, K.; Sinha, Sudeshna

2012-01-01

Logical Stochastic Resonance (LSR) is the application of Stochastic Resonance to logic computation, namely the phenomenon where a nonlinear system driven by weak signals representing logic inputs, under optimal noise, can yield logic outputs. We extend the existing results, obtained in the context of bistable systems, to multi-stable dynamical systems, allowing us to obtain XOR logic, in addition to the AND (NAND) and OR (NOR) logic observed in earlier studies. This strategy widens the scope of LSR from the application point of view, as XOR forms the basis of ubiquitous bit-by-bit addition, and conceptually, showing the ability to yield non-monotonic input–output logic associations. -- Highlights: ► We generalize Logical Stochastic Resonance from bistable to multi-stable systems. ► We propose a tristable dynamical system formed of piecewise linear functions. ► The system can correctly reproduce XOR logic behavior using the LSR principle. ► The system yields different logic behavior without the need to change the dynamics.

Classical Mathematical Logic The Semantic Foundations of Logic

CERN Document Server

Epstein, Richard L

2011-01-01

In Classical Mathematical Logic, Richard L. Epstein relates the systems of mathematical logic to their original motivations to formalize reasoning in mathematics. The book also shows how mathematical logic can be used to formalize particular systems of mathematics. It sets out the formalization not only of arithmetic, but also of group theory, field theory, and linear orderings. These lead to the formalization of the real numbers and Euclidean plane geometry. The scope and limitations of modern logic are made clear in these formalizations. The book provides detailed explanations of all proo

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

Science.gov (United States)

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

Transforming equality logic to propositional logic

NARCIS (Netherlands)

Zantema, H.; Groote, J.F.

2003-01-01

Abstract We investigate and compare various ways of transforming equality formulas to propositional formulas, in order to be able to solve satisfiability in equality logic by means of satisfiability in propositional logic. We propose equality substitution as a new approach combining desirable

Field programmable gate array-based real-time optical Doppler tomography system for in vivo imaging of cardiac dynamics in the chick embryo

DEFF Research Database (Denmark)

Thrane, Lars; Larsen, Henning Engelbrecht; Norozi, Kambiz

2009-01-01

efficient and compact implementation by combining the conversion to an analytic signal with a pulse shaping function without the need for extra resources as compared to the Hilbert transform method. The conversion of the analytic signal to amplitude and phase is done by use of the coordinate rotation......We demonstrate a field programmable gate-array-based real-time optical Doppler tomography system. A complex-valued bandpass filter is used for the first time in optical coherence tomography signal processing to create the analytic signal. This method simplifies the filter design, and allows...

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

Science.gov (United States)

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

The pulsed amplitude unit for the SLC

International Nuclear Information System (INIS)

Rolfe, J.; Browne, M.J.; Jobe, R.K.

1987-02-01

There is a recurring requirement in the SLC for the control of devices such as magnets, phase shifters, and attenuators on a beam-by-beam basis. The Pulsed Amplitude Unit (PAU) is a single width CAMAC module developed for this purpose. It provides digitally programmed analog output voltages on a beam-by-beam basis. Up to 32 preprogrammed values of output voltage are available from the single analog output of the module, and any of these values can be associated with any of the 256 possible SLC beam definitions. A 12-bit Analog-to-Digital Converter (ADC) digitizes an analog input signal at the appropriate beam time and stores it in a buffer memory. This feature is normally used to monitor the response of the device being controlled by the PAU at each beam time. Initial application of the PAU is a part of the system that controls the output of Klystrons in the SLC. The PAU combines several different functions in a single module. In order to accommodate these functions in a single width CAMAC module, field programmed logic is used extensively. Field Programmable Logic Arrays, Programmed Array Logic, and a Field Programmable Logic Sequencer are employed

The pulsed amplitude unit for the SLC

International Nuclear Information System (INIS)

Rolfe, J.; Browne, M.J.; Jobe, R.K.

1987-01-01

There is a recurring requirement in the SLC for the control of devices such as magnets, phase shifters, and attenuators on a beam-by-beam basis. The Pulsed Amplitude Unit (PAU) is a single width CAMAC module developed for this purpose. It provides digitally programmed analog output voltages on a beam-by-beam basis. Up to 32 preprogrammed values of output voltage are available from the single analog output of the module, and any of these values can be associated with any of the 256 possible SLC beam definitions. A 12-bit Analog-to-Digital converter (ADC) digitizes an analog input signal at the appropriate beam time and stores it in a buffer memory. This feature is normally used to monitor the response of the device being controlled by the PAU at each beam time. Initial application of the PAU at is as part of the system that controls the output of Klystorns in the SLC. The PAU combines several different functions in a single module. In order to accommodate these functions in a single width CAMAC module, field programmed logic is used extensively. Field Programmable Logic Arrays, Programmed Array Logic, and a Field Programmable Logic Sequencer are employed

Innovative Columnar Type of Grid Array SJ BIST HALT Method, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Ridgetop will develop a superior method for testing and qualifying columnar type of grid arrays such as field programmable gate arrays (FPGAs) packaged in column...

Logic and Ontology

Directory of Open Access Journals (Sweden)

Newton C. A. da Costa

2002-12-01

Full Text Available In view of the present state of development of non classical logic, especially of paraconsistent logic, a new stand regarding the relations between logic and ontology is defended In a parody of a dictum of Quine, my stand May be summarized as follows. To be is to be the value of a variable a specific language with a given underlying logic Yet my stand differs from Quine’s, because, among other reasons, I accept some first order heterodox logics as genuine alternatives to classical logic I also discuss some questions of non classical logic to substantiate my argument, and suggest that may position complements and extends some ideas advanced by L Apostel.

Structural Logical Relations

DEFF Research Database (Denmark)

Schürmann, Carsten; Sarnat, Jeffrey

2008-01-01

Tait's method (a.k.a. proof by logical relations) is a powerful proof technique frequently used for showing foundational properties of languages based on typed lambda-calculi. Historically, these proofs have been extremely difficult to formalize in proof assistants with weak meta-logics......, such as Twelf, and yet they are often straightforward in proof assistants with stronger meta-logics. In this paper, we propose structural logical relations as a technique for conducting these proofs in systems with limited meta-logical strength by explicitly representing and reasoning about an auxiliary logic...

Multi-purpose logical device with integrated circuit for the automation of mine water disposal

Energy Technology Data Exchange (ETDEWEB)

Pop, E.; Pasculescu, M.

1980-06-01

After an analysis of the waste water disposal as an object of automation, the author presents a BASIC-language programme established to simulate the automated control system on a digital computer. Then a multi-purpose logical device with integrated circuits for the automation of the mine water disposal is presented. (In Romanian)

Upgrading of Alum Preparation and Dosing Unit for Sharq Dijla Water Treatment Plant by Using Programmable Logic Controller System

Directory of Open Access Journals (Sweden)

Aumar Al-Nakeeb

2018-02-01

Full Text Available One of the important units in Sharq Dijla Water Treatment Plant (WTP first and second extensions are the alum solution preparation and dosing unit. The existing operation of this unit accomplished manually starting from unloading the powder alum in the preparation basin and ending by controlling the alum dosage addition through the dosing pumps to the flash mix chambers. Because of the modern trend of monitoring and control the automatic operation of WTPs due to the great benefits that could be gain from optimum equipment operation, reducing the operating costs and human errors. This study deals with how to transform the conventional operation to an automatic monitoring and controlling system depending on a Programmable Logic Controller (PLC and online sensors for alum preparation and dosing unit in Sharq Dijla WTP. PLC system will receive, analyze transmitting data, compare them with preset points then automatically orders the operational equipment (such as pumps, valves, and mixers in a way that guarantees the safe and appropriate operation of the unit. As a result of Process and Instrumentation Diagrams (PID that were prepared in this study, these units can be fully operating and manage by using Supervisory Control and Data Acquisition (SCADA system.

A prototype of programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Dell'Orso, M.

1999-01-01

The authors present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into Field Programmable Gate Arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows them to keep up smoothly with technology improvements. A 64 PAM array has been assembled on a prototype VME board and fully tested up to 30 MHz

BDI Logics

NARCIS (Netherlands)

Meyer, J.J.Ch.; Broersen, J.M.; Herzig, A.

2015-01-01

This paper presents an overview of so-called BDI logics, logics where the notion of Beliefs, Desires and Intentions play a central role. Starting out from the basic ideas about BDI by Bratman, we consider various formalizations in logic, such as the approach of Cohen and Levesque, slightly

Many-valued logics

CERN Document Server

Bolc, Leonard

1992-01-01

Many-valued logics were developed as an attempt to handle philosophical doubts about the "law of excluded middle" in classical logic. The first many-valued formal systems were developed by J. Lukasiewicz in Poland and E.Post in the U.S.A. in the 1920s, and since then the field has expanded dramatically as the applicability of the systems to other philosophical and semantic problems was recognized. Intuitionisticlogic, for example, arose from deep problems in the foundations of mathematics. Fuzzy logics, approximation logics, and probability logics all address questions that classical logic alone cannot answer. All these interpretations of many-valued calculi motivate specific formal systems thatallow detailed mathematical treatment. In this volume, the authors are concerned with finite-valued logics, and especially with three-valued logical calculi. Matrix constructions, axiomatizations of propositional and predicate calculi, syntax, semantic structures, and methodology are discussed. Separate chapters deal w...

Practical programmable circuits a guide to PLDs, state machines, and microcontrollers

CERN Document Server

Broesch, James D

1991-01-01

This is a practical guide to programmable logic devices. It covers all devices related to PLD: PALs, PGAs, state machines, and microcontrollers. Usefulness is evaluated; support needed in order to effectively use the devices is discussed. All examples are based on real-world circuits.

Relevancies of multiple-interaction events and signal-to-noise ratio for Anger-logic based PET detector designs

Science.gov (United States)

Peng, Hao

2015-10-01

A fundamental challenge for PET block detector designs is to deploy finer crystal elements while limiting the number of readout channels. The standard Anger-logic scheme including light sharing (an 8 by 8 crystal array coupled to a 2×2 photodetector array with an optical diffuser, multiplexing ratio: 16:1) has been widely used to address such a challenge. Our work proposes a generalized model to study the impacts of two critical parameters on spatial resolution performance of a PET block detector: multiple interaction events and signal-to-noise ratio (SNR). The study consists of the following three parts: (1) studying light output profile and multiple interactions of 511 keV photons within crystal arrays of different crystal widths (from 4 mm down to 1 mm, constant height: 20 mm); (2) applying the Anger-logic positioning algorithm to investigate positioning/decoding uncertainties (i.e., "block effect") in terms of peak-to-valley ratio (PVR), with light sharing, multiple interactions and photodetector SNR taken into account; and (3) studying the dependency of spatial resolution on SNR in the context of modulation transfer function (MTF). The proposed model can be used to guide the development and evaluation of a standard Anger-logic based PET block detector including: (1) selecting/optimizing the configuration of crystal elements for a given photodetector SNR; and (2) predicting to what extent additional electronic multiplexing may be implemented to further reduce the number of readout channels.

Development of field programmable gate array-based reactor trip functions using systems engineering approach

Energy Technology Data Exchange (ETDEWEB)

Jung, Jae Cheon; Ahmed, Ibrahim [Nuclear Power Plant Engineering, KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

2016-08-15

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

Design of acoustic logging signal source of imitation based on field programmable gate array

Science.gov (United States)

Zhang, K.; Ju, X. D.; Lu, J. Q.; Men, B. Y.

2014-08-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes.

Full image-processing pipeline in field-programmable gate array for a small endoscopic camera

Science.gov (United States)

Mostafa, Sheikh Shanawaz; Sousa, L. Natércia; Ferreira, Nuno Fábio; Sousa, Ricardo M.; Santos, Joao; Wäny, Martin; Morgado-Dias, F.

2017-01-01

Endoscopy is an imaging procedure used for diagnosis as well as for some surgical purposes. The camera used for the endoscopy should be small and able to produce a good quality image or video, to reduce discomfort of the patients, and to increase the efficiency of the medical team. To achieve these fundamental goals, a small endoscopy camera with a footprint of 1 mm×1 mm×1.65 mm is used. Due to the physical properties of the sensors and human vision system limitations, different image-processing algorithms, such as noise reduction, demosaicking, and gamma correction, among others, are needed to faithfully reproduce the image or video. A full image-processing pipeline is implemented using a field-programmable gate array (FPGA) to accomplish a high frame rate of 60 fps with minimum processing delay. Along with this, a viewer has also been developed to display and control the image-processing pipeline. The control and data transfer are done by a USB 3.0 end point in the computer. The full developed system achieves real-time processing of the image and fits in a Xilinx Spartan-6LX150 FPGA.

Reconstruction and logical modeling of glucose repression signaling pathways in Saccharomyces cerevisiae

Directory of Open Access Journals (Sweden)

Oliveira Ana

2009-01-01

Full Text Available Abstract Background In the yeast Saccharomyces cerevisiae, the presence of high levels of glucose leads to an array of down-regulatory effects known as glucose repression. This process is complex due to the presence of feedback loops and crosstalk between different pathways, complicating the use of intuitive approaches to analyze the system. Results We established a logical model of yeast glucose repression, formalized as a hypergraph. The model was constructed based on verified regulatory interactions and it includes 50 gene transcripts, 22 proteins, 5 metabolites and 118 hyperedges. We computed the logical steady states of all nodes in the network in order to simulate wildtype and deletion mutant responses to different sugar availabilities. Evaluation of the model predictive power was achieved by comparing changes in the logical state of gene nodes with transcriptome data. Overall, we observed 71% true predictions, and analyzed sources of errors and discrepancies for the remaining. Conclusion Though the binary nature of logical (Boolean models entails inherent limitations, our model constitutes a primary tool for storing regulatory knowledge, searching for incoherencies in hypotheses and evaluating the effect of deleting regulatory elements involved in glucose repression.

Quantum Logic as a Dynamic Logic

NARCIS (Netherlands)

Baltag, A.; Smets, S.

We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear “no”.

Quantum logic as a dynamic logic

NARCIS (Netherlands)

Baltag, Alexandru; Smets, Sonja

We address the old question whether a logical understanding of Quantum Mechanics requires abandoning some of the principles of classical logic. Against Putnam and others (Among whom we may count or not E. W. Beth, depending on how we interpret some of his statements), our answer is a clear "no".

Product Lukasiewicz Logic

Czech Academy of Sciences Publication Activity Database

Horčík, Rostislav; Cintula, Petr

2004-01-01

Roč. 43, - (2004), s. 477-503 ISSN 1432-0665 R&D Projects: GA AV ČR IAA1030004; GA ČR GA201/02/1540 Grant - others:GA CTU(CZ) project 0208613; net CEEPUS(SK) SK-042 Institutional research plan: CEZ:AV0Z1030915 Keywords : fuzzy logic * many-valued logic * Lukasiewicz logic * Lpi logic * Takeuti-Titani logic * MV-algebras * product MV-algebras Subject RIV: BA - General Mathematics Impact factor: 0.295, year: 2004

Case for a field-programmable gate array multicore hybrid machine for an image-processing application

Science.gov (United States)

Rakvic, Ryan N.; Ives, Robert W.; Lira, Javier; Molina, Carlos

2011-01-01

General purpose computer designers have recently begun adding cores to their processors in order to increase performance. For example, Intel has adopted a homogeneous quad-core processor as a base for general purpose computing. PlayStation3 (PS3) game consoles contain a multicore heterogeneous processor known as the Cell, which is designed to perform complex image processing algorithms at a high level. Can modern image-processing algorithms utilize these additional cores? On the other hand, modern advancements in configurable hardware, most notably field-programmable gate arrays (FPGAs) have created an interesting question for general purpose computer designers. Is there a reason to combine FPGAs with multicore processors to create an FPGA multicore hybrid general purpose computer? Iris matching, a repeatedly executed portion of a modern iris-recognition algorithm, is parallelized on an Intel-based homogeneous multicore Xeon system, a heterogeneous multicore Cell system, and an FPGA multicore hybrid system. Surprisingly, the cheaper PS3 slightly outperforms the Intel-based multicore on a core-for-core basis. However, both multicore systems are beaten by the FPGA multicore hybrid system by >50%.

Development and applications of a computer-aided phased array assembly for ultrasonic testing

International Nuclear Information System (INIS)

Schenk, G.; Montag, H.J.; Wuestenberg, H.; Erhard, A.

1985-01-01

The use of modern electronic equipment for programmable signal delay increasingly allows transit-time controlled phased arrays to be applied in non-destructive, ultrasonic materials testing. A phased-array assembly is described permitting fast variation of incident angle of acoustic wave and of sonic beam focus, together with numerical evaluation of measured data. Phased arrays can be optimized by adding programmable electronic equipment so that the quality of conventional designs can be achieved. Applications of the new technical improvement are explained, referring to stress corrosion cracking, turbine testing, echo tomography of welded joints. (orig./HP) [de

Against Logical Form

Directory of Open Access Journals (Sweden)

P N Johnson-Laird

2010-10-01

Full Text Available An old view in logic going back to Aristotle is that an inference is valid in virtue of its logical form. Many psychologists have adopted the same point of view about human reasoning: the first step is to recover the logical form of an inference, and the second step is to apply rules of inference that match these forms in order to prove that the conclusion follows from the premises. The present paper argues against this idea. The logical form of an inference transcends the grammatical forms of the sentences used to express it, because logical form also depends on context. Context is not readily expressed in additional premises. And the recovery of logical form leads ineluctably to the need for infinitely many axioms to capture the logical properties of relations. An alternative theory is that reasoning depends on mental models, and this theory obviates the need to recover logical form.

Multiplier-free DCT approximations for RF multi-beam digital aperture-array space imaging and directional sensing

International Nuclear Information System (INIS)

Potluri, U S; Madanayake, A; Rajapaksha, N; Cintra, R J; Bayer, F M

2012-01-01

Multi-beamforming is an important requirement for broadband space imaging applications based on dense aperture arrays (AAs). Usually, the discrete Fourier transform is the transform of choice for AA electromagnetic imaging. Here, the discrete cosine transform (DCT) is proposed as an alternative, enabling the use of emerging fast algorithms that offer greatly reduced complexity in digital arithmetic circuits. We propose two novel high-speed digital architectures for recently proposed fast algorithms (Bouguezel, Ahmad and Swamy 2008 Electron. Lett. 44 1249–50) (BAS-2008) and (Cintra and Bayer 2011 IEEE Signal Process. Lett. 18 579–82) (CB-2011) that provide good approximations to the DCT at zero multiplicative complexity. Further, we propose a novel DCT approximation having zero multiplicative complexity that is shown to be better for multi-beamforming AAs when compared to BAS-2008 and CB-2011. The far-field array pattern of ideal DCT, BAS-2008, CB-2011 and proposed approximation are investigated with error analysis. Extensive hardware realizations, implementation details and performance metrics are provided for synchronous field programmable gate array (FPGA) technology from Xilinx. The resource consumption and speed metrics of BAS-2008, CB-2011 and the proposed approximation are investigated as functions of system word size. The 8-bit versions are mapped to emerging asynchronous FPGAs leading to significantly increased real-time throughput with clock rates at up to 925.6 MHz implying the fastest DCT approximations using reconfigurable logic devices in the literature. (paper)

Design and Simulation of Automatic Ballast System on Catamaran Ship Based on Programmable Logic Control

Directory of Open Access Journals (Sweden)

Indra Ranu Kusuma

2017-06-01

Full Text Available Characteristics of catamaran ship which has deficiency to ship stability during maneuvering. to that end, this paper concerns about ballast system design in support of the safety and comfort of passengers on the catamaran boat. the discussion is done by creating a mathematical model of each component in the block diagram of the ballast system. then determine the pid value of the system and add the compensator for the system to run stable. further analyzed with the help of matlab software to get transient system response. with the automation system on the ballast system, it is expected that the motion of the ship can work automatically and provide a better response in the stability of the catamaran type ship. the ballast system begins to work against the tilt of the ship at 6.7 seconds at a certain angle, and will continue to work during the vessel maneuvering. judging from the 6.7 second system response time, the convenience of the passengers is not disturbed (the system response is not too fast. one way to reduce the rolling that occurs on the ship is to optimize the performance of the ballast system. performance optimization is done by using programmable logic controller (plc. plc used is omron cpm1a-30cdr-a-v1. the process is done by making the installation plant model of the ballast system as a control medium. followed by creating a control circuit consisting of wiring i / o, limit switch circuits, power supplies and programming languages associated with plcs. the result of the control is expected to regulate fluid flow in the ballast system automatically resulting in a rapid response to the stability of the ship.

Superconductor fluxoid logic

International Nuclear Information System (INIS)

Andronov, A.A.; Kurin, V.V.; Levichev, M.Yu.; Ryndyk, D.A.; Vostokov, V.I.

1993-01-01

In recent years there has been much interest in superconductor logical devices. Our paper is devoted to the analysis of some new possibilities in this field. The main problems here are: minimization of time of logical operations and reducing of device scale. Josephson systems are quite appropriate for this purpose because of small size, short characteristic time and also small energy losses. Two different types of Josephson logic have been investigated during last years. The first type is based on hysteretic V-A characteristic of a single Josephson junction. Superconducting and resistive (with nonzero voltage) states are considered as logical zero and logical unit. The second one - rapid single flux quantum logic, has been developed recently and is based on SQUID-like bistability. Different logical states are the states with different number of magnetic flux quanta inside closed superconducting contour. Information is represented by voltage pulses with fixed ''area'' (∫ V(t)/dt). This pulses are generated when logical state of SQUID-like elementary cell changes. The fundamental role of magnetic flux quantization in this type of logic leads to the necessity of large enough self-inductance of superconductor contour and thus to limitations on minimal device dimensions. (orig.)

Advances in Modal Logic

DEFF Research Database (Denmark)

Modal logic is a subject with ancient roots in the western logical tradition. Up until the last few generations, it was pursued mainly as a branch of philosophy. But in recent years, the subject has taken new directions with connections to topics in computer science and mathematics. This volume...... is the proceedings of the conference of record in its fi eld, Advances in Modal Logic. Its contributions are state-of-the-art papers. The topics include decidability and complexity results for specifi c modal logics, proof theory of modal logic, logics for reasoning about time and space, provability logic, dynamic...... epistemic logic, and the logic of evidence....

Mathematical logic

CERN Document Server

Kleene, Stephen Cole

1967-01-01

Undergraduate students with no prior instruction in mathematical logic will benefit from this multi-part text. Part I offers an elementary but thorough overview of mathematical logic of 1st order. Part II introduces some of the newer ideas and the more profound results of logical research in the 20th century. 1967 edition.

Indeterministic Temporal Logic

Directory of Open Access Journals (Sweden)

Trzęsicki Kazimierz

2015-09-01

Full Text Available The questions od determinism, causality, and freedom have been the main philosophical problems debated since the beginning of temporal logic. The issue of the logical value of sentences about the future was stated by Aristotle in the famous tomorrow sea-battle passage. The question has inspired Łukasiewicz’s idea of many-valued logics and was a motive of A. N. Prior’s considerations about the logic of tenses. In the scheme of temporal logic there are different solutions to the problem. In the paper we consider indeterministic temporal logic based on the idea of temporal worlds and the relation of accessibility between them.

Realworld maximum power point tracking simulation of PV system based on Fuzzy Logic control

Science.gov (United States)

Othman, Ahmed M.; El-arini, Mahdi M. M.; Ghitas, Ahmed; Fathy, Ahmed

2012-12-01

In the recent years, the solar energy becomes one of the most important alternative sources of electric energy, so it is important to improve the efficiency and reliability of the photovoltaic (PV) systems. Maximum power point tracking (MPPT) plays an important role in photovoltaic power systems because it maximize the power output from a PV system for a given set of conditions, and therefore maximize their array efficiency. This paper presents a maximum power point tracker (MPPT) using Fuzzy Logic theory for a PV system. The work is focused on the well known Perturb and Observe (P&O) algorithm and is compared to a designed fuzzy logic controller (FLC). The simulation work dealing with MPPT controller; a DC/DC Ćuk converter feeding a load is achieved. The results showed that the proposed Fuzzy Logic MPPT in the PV system is valid.

VHDL, FPGA and the master trigger controller of BES

International Nuclear Information System (INIS)

Guo Yanan; Wang Jufang; Zhao Dixin

1996-01-01

A Master Trigger Controller was made using fast FPGA (Field-Programmable Gate Array) instead of ECLIC (Emitter-Coupled Logic Integrated Circuit). VHDL (Verilog Hardware Description Language) was used in its design. The same performance was obtained with increased flexibility

Classical Logic and Quantum Logic with Multiple and Common Lattice Models

Directory of Open Access Journals (Sweden)

Mladen Pavičić

2016-01-01

Full Text Available We consider a proper propositional quantum logic and show that it has multiple disjoint lattice models, only one of which is an orthomodular lattice (algebra underlying Hilbert (quantum space. We give an equivalent proof for the classical logic which turns out to have disjoint distributive and nondistributive ortholattices. In particular, we prove that both classical logic and quantum logic are sound and complete with respect to each of these lattices. We also show that there is one common nonorthomodular lattice that is a model of both quantum and classical logic. In technical terms, that enables us to run the same classical logic on both a digital (standard, two-subset, 0-1-bit computer and a nondigital (say, a six-subset computer (with appropriate chips and circuits. With quantum logic, the same six-element common lattice can serve us as a benchmark for an efficient evaluation of equations of bigger lattice models or theorems of the logic.

Toward Automating Web Protocol Configuration for a Programmable Logic Controller Emulator

Science.gov (United States)

2014-06-19

Security Risks for Industrial Control Systems ,” VDE 2004 Congress, Berlin, Germany, October 2004, pp. 1-7. [Cis12] Cisco, NetFlow Configuration Guide...Date 29 May 2014 Date AFIT-ENG-T-14-J-4 Abstract Industrial Control Systems (ICS) remain vulnerable through attack vectors that exist within programmable...5 2.2 Industrial Control Systems

Development of FPGA-Based Control Board

Energy Technology Data Exchange (ETDEWEB)

Lee, Yoon Hee; Jeong, See Chae; Choi, Woong Seock; Lee, Chang Jae; Jeong, Jin Kwon; Ha, Jae Hong [Korea Power Engineering Company Inc., Daejeon (Korea, Republic of)

2009-10-15

It is well known that existing nuclear power plant (NPP) control systems contain many components which are becoming obsolete at an increasing rate. Various studies have been conducted to address control system hardware obsolescence. Obsolete analog and digital control systems in non-nuclear power plants are commonly replaced with modern digital control systems, programmable logic controllers (PLC) and distributed control systems (DCS). Field Programmable Gate Arrays (FPGAs) are highlighted as an alternative means for obsolete control systems. FPGAs are advanced digital integrated circuits (ICs) that contain configurable (programmable) blocks of logic along with configurable interconnects between these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of Programmable Logic Device (PLD). Nowadays they can contain millions of logic gates by nanotechnology and so be used to implement extremely large and complex functions that previously could be realized only using Application-Specific Integrated Circuits (ASICs). This paper is to present the development of a FPGAbased control board performing user-defined control functions. An Actel ProASIC{sup plus} FPGA platform is implemented as the comparator of Plant Protection System (PPS). Functional simulation is implemented for the comparator.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Directory of Open Access Journals (Sweden)

Ion Stiharu

2010-08-01

Full Text Available Computer numerically controlled (CNC machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA-based sensor node.

A Field Programmable Gate Array-Based Reconfigurable Smart-Sensor Network for Wireless Monitoring of New Generation Computer Numerically Controlled Machines

Science.gov (United States)

Moreno-Tapia, Sandra Veronica; Vera-Salas, Luis Alberto; Osornio-Rios, Roque Alfredo; Dominguez-Gonzalez, Aurelio; Stiharu, Ion; de Jesus Romero-Troncoso, Rene

2010-01-01

Computer numerically controlled (CNC) machines have evolved to adapt to increasing technological and industrial requirements. To cover these needs, new generation machines have to perform monitoring strategies by incorporating multiple sensors. Since in most of applications the online Processing of the variables is essential, the use of smart sensors is necessary. The contribution of this work is the development of a wireless network platform of reconfigurable smart sensors for CNC machine applications complying with the measurement requirements of new generation CNC machines. Four different smart sensors are put under test in the network and their corresponding signal processing techniques are implemented in a Field Programmable Gate Array (FPGA)-based sensor node. PMID:22163602

Propositional Logics of Dependence

NARCIS (Netherlands)

Yang, F.; Väänänen, J.

2016-01-01

In this paper, we study logics of dependence on the propositional level. We prove that several interesting propositional logics of dependence, including propositional dependence logic, propositional intuitionistic dependence logic as well as propositional inquisitive logic, are expressively complete

Programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-04-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Contracts for Cooperation between Web Service Programmers and HTML Designers

DEFF Research Database (Denmark)

Böttger, Henning; Møller, Anders; Schwartzbach, Michael I.

2006-01-01

Interactive Web services consist of a mixture of HTML fragments and program code. The fragments, which are maintained by designers, are combined to form HTML pages that are shown to the clients. The code, which is maintained by programmers, is executed on the server to handle the business logic....... Current Web service frameworks provide little help in separating these constituents, which complicates cooperation between programmers and HTML designers. We propose a system based on XML templates and formalized contracts allowing a flexible separation of concerns. The contracts act as interfaces between...... the programmers and the HTML designers and permit tool support for statically checking that both parties fulfill their obligations. This ensures that (1) programmers and HTML designers work more independently focusing on their own expertises, (2) the Web service implementation is better structured and thus easier...

Abductive Logic Grammars

DEFF Research Database (Denmark)

Christiansen, Henning; Dahl, Veronica

2009-01-01

By extending logic grammars with constraint logic, we give them the ability to create knowledge bases that represent the meaning of an input string. Semantic information is thus defined through extra-grammatical means, and a sentence's meaning logically follows as a by-product of string rewriting....... We formalize these ideas, and exemplify them both within and outside first-order logic, and for both fixed and dynamic knowledge bases. Within the latter variety, we consider the usual left-to-right derivations that are traditional in logic grammars, but also -- in a significant departure from...

Fuzzy logic control of stand-alone photovoltaic system with battery storage

Science.gov (United States)

Lalouni, S.; Rekioua, D.; Rekioua, T.; Matagne, E.

Photovoltaic energy has nowadays an increased importance in electrical power applications, since it is considered as an essentially inexhaustible and broadly available energy resource. However, the output power provided via the photovoltaic conversion process depends on solar irradiation and temperature. Therefore, to maximize the efficiency of the photovoltaic energy system, it is necessary to track the maximum power point of the PV array. The present paper proposes a maximum power point tracker (MPPT) method, based on fuzzy logic controller (FLC), applied to a stand-alone photovoltaic system. It uses a sampling measure of the PV array power and voltage then determines an optimal increment required to have the optimal operating voltage which permits maximum power tracking. This method carries high accuracy around the optimum point when compared to the conventional one. The stand-alone photovoltaic system used in this paper includes two bi-directional DC/DC converters and a lead-acid battery bank to overcome the scare periods. One converter works as an MPP tracker, while the other regulates the batteries state of charge and compensates the power deficit to provide a continuous delivery of energy to the load. The Obtained simulation results show the effectiveness of the proposed fuzzy logic controller.

Applications of Logic Coverage Criteria and Logic Mutation to Software Testing

Science.gov (United States)

Kaminski, Garrett K.

2011-01-01

Logic is an important component of software. Thus, software logic testing has enjoyed significant research over a period of decades, with renewed interest in the last several years. One approach to detecting logic faults is to create and execute tests that satisfy logic coverage criteria. Another approach to detecting faults is to perform mutation…

Use of Field Programmable Gate Array Technology in Future Space Avionics

Science.gov (United States)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Vérification des propriétés temporisées des automates programmables industriels

OpenAIRE

Bel Mokadem , Houda

2006-01-01

Vérification of PLC (Programmable Logic Controller) programs is important when these programs are to control critical applications for reactive systems. This context has already been study for untimed programs. In this thesis, We are interested to timed properties and programs. More precisely, we give a formal semantics to (partial) Ladder diagrams and TON blocks, with timed automata. We also propose a timed logic in order to abstract transient events, where transient properties is parameteri...

Application of programmable controllers to vacuum system interlocks

International Nuclear Information System (INIS)

Lee, G.; Moore, D.

1979-11-01

This paper describes the Doublet III Vacuum Control System in which all input signals and output loads are connected to a programmable controller (PC) for logical interfacing. Input signals derived from CAMAC, control panels, limit switches, etc., are implemented as output signals to CAMAC, vacuum valves, pump motors, etc., according to a logic program stored in the PC memory. The memory can be easily programmed by anyone familar with either Boolean algebra or relay-ladder network diagrams. The program data is entered with the aid of a calculator like, keyboard instrument with LED readout displays. The PC system contains a 1024 word RAM memory with a battery backup system to provide 72 hours protection of contents in case of power failure

Stochastic coalgebraic logic

CERN Document Server

Doberkat, Ernst-Erich

2009-01-01

Combining coalgebraic reasoning, stochastic systems and logic, this volume presents the principles of coalgebraic logic from a categorical perspective. Modal logics are also discussed, including probabilistic interpretations and an analysis of Kripke models.

Control Logic for the Interlock system of the ATLAS Insertable B-Layer

CERN Document Server

Riegel, Christian

Part of the first upgrade program of the ATLAS detector is the installation of the Insertable B-Layer (IBL) as a fourth and innermost detector layer of the ATLAS pixel detector to prepare the tracking system for the expected increase of pile-up events. As with every sub-detector, the IBL and its components have to be monitored and controlled via a Detector Control System (DCS). A hardware-based interlock system is installed on-site to prevent detector and people working at the detector from serious harm and damage. For the IBL, the logical processing of interlock signals is realised in Interlock Matrix Crates (IMCs) using Complex Programmable Logic Devices (CPLD). One part of this master thesis is the automatic implementation of the logical assignments from database information. A script was developed to generate the needed file to program the CPLD. The second part of this thesis is the design of a test setup to verify the functionality of the electrical components of each IMC and to confirm the correct proce...

Block QCA Fault-Tolerant Logic Gates

Science.gov (United States)

Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon

2003-01-01

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA

Towards an arithmetical logic the arithmetical foundations of logic

CERN Document Server

Gauthier, Yvon

2015-01-01

This book offers an original contribution to the foundations of logic and mathematics, and focuses on the internal logic of mathematical theories, from arithmetic or number theory to algebraic geometry. Arithmetical logic is the term used to refer to the internal logic of classical arithmetic, here called Fermat-Kronecker arithmetic, and combines Fermat’s method of infinite descent with Kronecker’s general arithmetic of homogeneous polynomials. The book also includes a treatment of theories in physics and mathematical physics to underscore the role of arithmetic from a constructivist viewpoint. The scope of the work intertwines historical, mathematical, logical and philosophical dimensions in a unified critical perspective; as such, it will appeal to a broad readership from mathematicians to logicians, to philosophers interested in foundational questions. Researchers and graduate students in the fields of philosophy and mathematics will benefit from the author’s critical approach to the foundations of l...

Meta-Logical Reasoning in Higher-Order Logic

DEFF Research Database (Denmark)

Villadsen, Jørgen; Schlichtkrull, Anders; Hess, Andreas Viktor

The semantics of first-order logic (FOL) can be described in the meta-language of higher-order logic (HOL). Using HOL one can prove key properties of FOL such as soundness and completeness. Furthermore, one can prove sentences in FOL valid using the formalized FOL semantics. To aid...

Programmable controllers replace relays in MFTF-B personnel-safety interlocks

International Nuclear Information System (INIS)

Branum, J.D.

1981-01-01

This paper describes a new approach for implementing personnel safety interlocks logic using industrial-type programmable controllers. The logic for all personnel safety interlocks except those totally internal to a subsystem is implemented in two non-redundant controllers. A high degree of fail-safe reliability is achieved by augmenting the protective features intrinsic to each controller with those provided by a small amount of external support hardware. The controllers are interfaced to the host computer system via fiber optic data links to enable display of interlock and overall system status on the control room graphic displays. When fully implemented, the controllers will perform the equivalent of over 2000 discreet relay functions

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Realworld maximum power point tracking simulation of PV system based on Fuzzy Logic control

Directory of Open Access Journals (Sweden)

Ahmed M. Othman

2012-12-01

Full Text Available In the recent years, the solar energy becomes one of the most important alternative sources of electric energy, so it is important to improve the efficiency and reliability of the photovoltaic (PV systems. Maximum power point tracking (MPPT plays an important role in photovoltaic power systems because it maximize the power output from a PV system for a given set of conditions, and therefore maximize their array efficiency. This paper presents a maximum power point tracker (MPPT using Fuzzy Logic theory for a PV system. The work is focused on the well known Perturb and Observe (P&O algorithm and is compared to a designed fuzzy logic controller (FLC. The simulation work dealing with MPPT controller; a DC/DC Ćuk converter feeding a load is achieved. The results showed that the proposed Fuzzy Logic MPPT in the PV system is valid.

Field-programmable beam reconfiguring based on digitally-controlled coding metasurface

Science.gov (United States)

Wan, Xiang; Qi, Mei Qing; Chen, Tian Yi; Cui, Tie Jun

2016-02-01

Digital phase shifters have been applied in traditional phased array antennas to realize beam steering. However, the phase shifter deals with the phase of the induced current; hence, it has to be in the path of each element of the antenna array, making the phased array antennas very expensive. Metamaterials and/or metasurfaces enable the direct modulation of electromagnetic waves by designing subwavelength structures, which opens a new way to control the beam scanning. Here, we present a direct digital mechanism to control the scattered electromagnetic waves using coding metasurface, in which each unit cell loads a pin diode to produce binary coding states of “1” and “0”. Through data lines, the instant communications are established between the coding metasurface and the internal memory of field-programmable gate arrays (FPGA). Thus, we realize the digital modulation of electromagnetic waves, from which we present the field-programmable reflective antenna with good measurement performance. The proposed mechanism and functional device have great application potential in new-concept radar and communication systems.

Connections among quantum logics

International Nuclear Information System (INIS)

Lock, P.F.; Hardegree, G.M.

1985-01-01

In this paper, a theory of quantum logics is proposed which is general enough to enable us to reexamine a previous work on quantum logics in the context of this theory. It is then easy to assess the differences between the different systems studied. The quantum logical systems which are incorporated are divided into two groups which we call ''quantum propositional logics'' and ''quantum event logics''. The work of Kochen and Specker (partial Boolean algebras) is included and so is that of Greechie and Gudder (orthomodular partially ordered sets), Domotar (quantum mechanical systems), and Foulis and Randall (operational logics) in quantum propositional logics; and Abbott (semi-Boolean algebras) and Foulis and Randall (manuals) in quantum event logics, In this part of the paper, an axiom system for quantum propositional logics is developed and the above structures in the context of this system examined. (author)

Virtual Array Receiver Options for 64-ary Pulse Position Modulation (PPM)

Energy Technology Data Exchange (ETDEWEB)

Mendez, A J; Hernandez, V J; Gagliardi, R M; Bennett, C V

2009-01-12

NASA is developing technology for 64 64-ary PPM using relatively large PPM time slots (10 ns) an and relatively simple d electronic electronic-based receiver logic. In this paper we describe photonic photonics-based receiver options for the case of much higher data rates and inherently shorter decision times. The receivers take the form of virtual ( array or quadrant) arrays with associated comparison tests. Previously we explored this concept for 4-ary and 16-ary PPM at data rates of up to 10 Gb/s. The lessons learned are applied to the case of 64 64-ary PPM at 1.25 Gb/s s. Various receiver designs are compare, and t the optimum design, based on virtual array he arrays, is s, evaluated using numerical simulations.

Paraconsistent Computational Logic

DEFF Research Database (Denmark)

Jensen, Andreas Schmidt; Villadsen, Jørgen

2012-01-01

In classical logic everything follows from inconsistency and this makes classical logic problematic in areas of computer science where contradictions seem unavoidable. We describe a many-valued paraconsistent logic, discuss the truth tables and include a small case study....

Design of acoustic logging signal source of imitation based on field programmable gate array

International Nuclear Information System (INIS)

Zhang, K; Ju, X D; Lu, J Q; Men, B Y

2014-01-01

An acoustic logging signal source of imitation is designed and realized, based on the Field Programmable Gate Array (FPGA), to improve the efficiency of examining and repairing acoustic logging tools during research and field application, and to inspect and verify acoustic receiving circuits and corresponding algorithms. The design of this signal source contains hardware design and software design,and the hardware design uses an FPGA as the control core. Four signals are made first by reading the Random Access Memory (RAM) data which are inside the FPGA, then dealing with the data by digital to analog conversion, amplification, smoothing and so on. Software design uses VHDL, a kind of hardware description language, to program the FPGA. Experiments illustrate that the ratio of signal to noise for the signal source is high, the waveforms are stable, and also its functions of amplitude adjustment, frequency adjustment and delay adjustment are in accord with the characteristics of real acoustic logging waveforms. These adjustments can be used to imitate influences on sonic logging received waveforms caused by many kinds of factors such as spacing and span of acoustic tools, sonic speeds of different layers and fluids, and acoustic attenuations of different cementation planes. (paper)

Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

International Nuclear Information System (INIS)

Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa

2015-01-01

This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket

What are Institutional Logics

DEFF Research Database (Denmark)

Berg Johansen, Christina; Waldorff, Susanne Boch

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guides by institutional logics, as well...... as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to institutional theory at large, and which social matters institutional logics can and cannot explore...

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

Science.gov (United States)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

International Nuclear Information System (INIS)

Chen, Yuan-Ho

2017-01-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

Energy Technology Data Exchange (ETDEWEB)

Shan, Jaffry Syed [Hamdard University, Karachi (Pakistan); Abbas, Syed Haider; Lee, Jung Ryul [Dept. of Aerospace Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Kang, Dong Hoon [Advanced Materials Research Team, Korea Railroad Research Institute, Uiwang (Korea, Republic of)

2015-12-15

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm{sup 2} with 0.5 mm interval) to 87.5% (scanning of 200x200mm{sup 2} with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

Using field programmable gate array hardware for the performance improvement of ultrasonic wave propagation imaging system

International Nuclear Information System (INIS)

Shan, Jaffry Syed; Abbas, Syed Haider; Lee, Jung Ryul; Kang, Dong Hoon

2015-01-01

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of 100x100mm 2 with 0.5 mm interval) to 87.5% (scanning of 200x200mm 2 with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

Energy Technology Data Exchange (ETDEWEB)

Chen, Yuan-Ho, E-mail: chenyh@mail.cgu.edu.tw [Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Department of Radiation Oncology, Chang Gung Memorial Hospital, Tao-Yuan 333, Taiwan (China); Center for Reliability Sciences and Technologies, Chang Gung University, Tao-Yuan 333, Taiwan (China)

2017-05-11

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Dispositional logic

Science.gov (United States)

Le Balleur, J. C.

1988-01-01

The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.

Logic and structure

CERN Document Server

Dalen, Dirk

1983-01-01

A book which efficiently presents the basics of propositional and predicate logic, van Dalen’s popular textbook contains a complete treatment of elementary classical logic, using Gentzen’s Natural Deduction. Propositional and predicate logic are treated in separate chapters in a leisured but precise way. Chapter Three presents the basic facts of model theory, e.g. compactness, Skolem-Löwenheim, elementary equivalence, non-standard models, quantifier elimination, and Skolem functions. The discussion of classical logic is rounded off with a concise exposition of second-order logic. In view of the growing recognition of constructive methods and principles, one chapter is devoted to intuitionistic logic. Completeness is established for Kripke semantics. A number of specific constructive features, such as apartness and equality, the Gödel translation, the disjunction and existence property have been incorporated. The power and elegance of natural deduction is demonstrated best in the part of proof theory cal...

Radiation-Hardened Circuitry Using Mask-Programmable Analog Arrays. Report 3

Energy Technology Data Exchange (ETDEWEB)

Britton, Jr, Charles L. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Shelton, Jacob H. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Ericson, Milton Nance [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Blalock, Benjamin [Univ. of Tennessee, Knoxville, TN (United States)

2015-03-01

As the recent accident at Fukushima Daiichi so vividly demonstrated, telerobotic technologies capable of withstanding high radiation environments need to be readily available to enable operations, repair, and recovery under severe accident scenarios when human entry is extremely dangerous or not possible. Telerobotic technologies that enable remote operation in high dose rate environments have undergone revolutionary improvement over the past few decades. However, much of this technology cannot be employed in nuclear power environments because of the radiation sensitivity of the electronics and the organic insulator materials currently in use. This is a report of the activities involving Task 3 of the Nuclear Energy Enabling Technologies (NEET) 2 project Radiation Hardened Circuitry Using Mask-Programmable Analog Arrays [1]. Evaluation of the performance of the system for both pre- and post-irradiation as well as operation at elevated temperature will be performed. Detailed performance of the system will be documented to ensure the design meets requirements prior to any extended evaluation. A suite of tests will be developed which will allow evaluation before and after irradiation and during temperature. Selection of the radiation exposure facilities will be determined in the early phase of the project. Radiation exposure will consist of total integrated dose (TID) up to 200 kRad or above with several intermediate doses during test. Dose rates will be in various ranges determined by the facility that will be used with a target of 30 kRad/hr. Many samples of the pre-commercial devices to be used will have been tested in previous projects to doses of at least 300 kRad and temperatures up to 125C. The complete systems will therefore be tested for performance at intermediate doses. Extended temperature testing will be performed up to the limit of the commercial sensors. The test suite performed at each test point will consist of operational testing of the three basic

A programmable delay unit incorporating a semi-custom integrated circuit

International Nuclear Information System (INIS)

Linstadt, E.

1985-01-01

The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

Engineered modular biomaterial logic gates for environmentally triggered therapeutic delivery

Science.gov (United States)

Badeau, Barry A.; Comerford, Michael P.; Arakawa, Christopher K.; Shadish, Jared A.; Deforest, Cole A.

2018-03-01

The successful transport of drug- and cell-based therapeutics to diseased sites represents a major barrier in the development of clinical therapies. Targeted delivery can be mediated through degradable biomaterial vehicles that utilize disease biomarkers to trigger payload release. Here, we report a modular chemical framework for imparting hydrogels with precise degradative responsiveness by using multiple environmental cues to trigger reactions that operate user-programmable Boolean logic. By specifying the molecular architecture and connectivity of orthogonal stimuli-labile moieties within material cross-linkers, we show selective control over gel dissolution and therapeutic delivery. To illustrate the versatility of this methodology, we synthesized 17 distinct stimuli-responsive materials that collectively yielded all possible YES/OR/AND logic outputs from input combinations involving enzyme, reductant and light. Using these hydrogels we demonstrate the first sequential and environmentally stimulated release of multiple cell lines in well-defined combinations from a material. We expect these platforms will find utility in several diverse fields including drug delivery, diagnostics and regenerative medicine.

Biological applications of an LCoS-based programmable array microscope (PAM)

Science.gov (United States)

Hagen, Guy M.; Caarls, Wouter; Thomas, Martin; Hill, Andrew; Lidke, Keith A.; Rieger, Bernd; Fritsch, Cornelia; van Geest, Bert; Jovin, Thomas M.; Arndt-Jovin, Donna J.

2007-02-01

We report on a new generation, commercial prototype of a programmable array optical sectioning fluorescence microscope (PAM) for rapid, light efficient 3D imaging of living specimens. The stand-alone module, including light source(s) and detector(s), features an innovative optical design and a ferroelectric liquid-crystal-on-silicon (LCoS) spatial light modulator (SLM) instead of the DMD used in the original PAM design. The LCoS PAM (developed in collaboration with Cairn Research, Ltd.) can be attached to a port of a(ny) unmodified fluorescence microscope. The prototype system currently operated at the Max Planck Institute incorporates a 6-position high-intensity LED illuminator, modulated laser and lamp light sources, and an Andor iXon emCCD camera. The module is mounted on an Olympus IX71 inverted microscope with 60-150X objectives with a Prior Scientific x,y, and z high resolution scanning stages. Further enhancements recently include: (i) point- and line-wise spectral resolution and (ii) lifetime imaging (FLIM) in the frequency domain. Multiphoton operation and other nonlinear techniques should be feasible. The capabilities of the PAM are illustrated by several examples demonstrating single molecule as well as lifetime imaging in live cells, and the unique capability to perform photoconversion with arbitrary patterns and high spatial resolution. Using quantum dot coupled ligands we show real-time binding and subsequent trafficking of individual ligand-growth factor receptor complexes on and in live cells with a temporal resolution and sensitivity exceeding those of conventional CLSM systems. The combined use of a blue laser and parallel LED or visible laser sources permits photoactivation and rapid kinetic analysis of cellular processes probed by photoswitchable visible fluorescent proteins such as DRONPA.

First-Order Hybrid Logic

DEFF Research Database (Denmark)

Braüner, Torben

2011-01-01

Hybrid logic is an extension of modal logic which allows us to refer explicitly to points of the model in the syntax of formulas. It is easy to justify interest in hybrid logic on applied grounds, with the usefulness of the additional expressive power. For example, when reasoning about time one...... often wants to build up a series of assertions about what happens at a particular instant, and standard modal formalisms do not allow this. What is less obvious is that the route hybrid logic takes to overcome this problem often actually improves the behaviour of the underlying modal formalism....... For example, it becomes far simpler to formulate proof-systems for hybrid logic, and completeness results can be proved of a generality that is simply not available in modal logic. That is, hybridization is a systematic way of remedying a number of known deficiencies of modal logic. First-order hybrid logic...

Metamathematics of fuzzy logic

CERN Document Server

Hájek, Petr

1998-01-01

This book presents a systematic treatment of deductive aspects and structures of fuzzy logic understood as many valued logic sui generis. Some important systems of real-valued propositional and predicate calculus are defined and investigated. The aim is to show that fuzzy logic as a logic of imprecise (vague) propositions does have well-developed formal foundations and that most things usually named `fuzzy inference' can be naturally understood as logical deduction.

Equational type logic

NARCIS (Netherlands)

Manca, V.; Salibra, A.; Scollo, Giuseppe

1990-01-01

Equational type logic is an extension of (conditional) equational logic, that enables one to deal in a single, unified framework with diverse phenomena such as partiality, type polymorphism and dependent types. In this logic, terms may denote types as well as elements, and atomic formulae are either

Henkin and Hybrid Logic

DEFF Research Database (Denmark)

Blackburn, Patrick Rowan; Huertas, Antonia; Manzano, Maria

2014-01-01

Leon Henkin was not a modal logician, but there is a branch of modal logic that has been deeply influenced by his work. That branch is hybrid logic, a family of logics that extend orthodox modal logic with special proposition symbols (called nominals) that name worlds. This paper explains why...... Henkin’s techniques are so important in hybrid logic. We do so by proving a completeness result for a hybrid type theory called HTT, probably the strongest hybrid logic that has yet been explored. Our completeness result builds on earlier work with a system called BHTT, or basic hybrid type theory...... is due to the first-order perspective, which lies at the heart of Henin’s best known work and hybrid logic....

Institutional Logics in Action

DEFF Research Database (Denmark)

Lounsbury, Michael; Boxenbaum, Eva

2013-01-01

This double volume presents state-of-the-art research and thinking on the dynamics of actors and institutional logics. In the introduction, we briefly sketch the roots and branches of institutional logics scholarship before turning to the new buds of research on the topic of how actors engage...... institutional logics in the course of their organizational practice. We introduce an exciting line of new works on the meta-theoretical foundations of logics, institutional logic processes, and institutional complexity and organizational responses. Collectively, the papers in this volume advance the very...... prolific stream of research on institutional logics by deepening our insight into the active use of institutional logics in organizational action and interaction, including the institutional effects of such (inter)actions....

The Third Life of Quantum Logic: Quantum Logic Inspired by Quantum Computing

OpenAIRE

Dunn, J. Michael; Moss, Lawrence S.; Wang, Zhenghan

2013-01-01

We begin by discussing the history of quantum logic, dividing it into three eras or lives. The first life has to do with Birkhoff and von Neumann's algebraic approach in the 1930's. The second life has to do with attempt to understand quantum logic as logic that began in the late 1950's and blossomed in the 1970's. And the third life has to do with recent developments in quantum logic coming from its connections to quantum computation. We discuss our own work connecting quantum logic to quant...

Real Islamic Logic

NARCIS (Netherlands)

Bergstra, J.A.

2011-01-01

Four options for assigning a meaning to Islamic Logic are surveyed including a new proposal for an option named "Real Islamic Logic" (RIL). That approach to Islamic Logic should serve modern Islamic objectives in a way comparable to the functionality of Islamic Finance. The prospective role of RIL

What are Institutional Logics

OpenAIRE

Berg Johansen, Christina; Bock Waldorff, Susanne

2015-01-01

This study presents new insights into the explanatory power of the institutional logics perspective. With outset in a discussion of seminal theory texts, we identify two fundamental topics that frame institutional logics: overarching institutional orders guided by institutional logics, as well as change and agency generated by friction between logics. We use these topics as basis for an analysis of selected empirical papers, with the aim of understanding how institutional logics contribute to...

DBPM signal processing with field programmable gate arrays

International Nuclear Information System (INIS)

Lai Longwei; Yi Xing; Zhang Ning; Yang Guisen; Wang Baopeng; Xiong Yun; Leng Yongbin; Yan Yingbing

2011-01-01

DBPM system performance is determined by the design and implementation of beam position signal processing algorithm. In order to develop the system, a beam position signal processing algorithm is implemented on FPGA. The hardware is a PMC board ICS-1554A-002 (GE Corp.) with FPGA chip XC5VSX95T. This paper adopts quadrature frequency mixing to down convert high frequency signal to base. Different from conventional method, the mixing is implemented by CORDIC algorithm. The algorithm theory and implementation details are discussed in this paper. As the board contains no front end gain controller, this paper introduces a published patent-pending technique that has been adopted to realize the function in digital logic. The whole design is implemented with VHDL language. An on-line evaluation has been carried on SSRF (Shanghai Synchrotron Radiation Facility)storage ring. Results indicate that the system turn-by-turn data can measure the real beam movement accurately,and system resolution is 1.1μm. (authors)

Methodology for Assessing the Degree of Internationalization of Business Academic Study Programmes

OpenAIRE

Dan-Cristian Dabija; Cătălin Postelnicu; Nicolae Al. Pop

2014-01-01

The purpose of this paper is to develop a methodology for assessing the degree of internationalization of undergraduate, Master’s and doctoral business programmes with the aid of complex indicators designed to capture the vast array of characteristics displayed by these programmes and contribute to their promotion in the international academic competition. The methodology should include both general indicators applicable to any study programme and some indicators that are specifically develop...

The European Fusion Research and Development Programme and the ITER Project

International Nuclear Information System (INIS)

Green, B J

2006-01-01

The EURATOM fusion research and development programme is a well integrated and coordinated programme. It has the objective of ''developing the technology for a safe, sustainable, environmentally responsible and economically viable energy source.'' The programme is focussed on the magnetic confinement approach and supports 23 Associations which involve research entities (many with experimental and technology facilities) each having a bilateral contractual relationship with the European Commission. The paper will describe fusion reactions and present their potential advantages as an energy source. Further, it will describe the EURATOM programme and how it is organised and implemented. The success of the European programme and that of other national programmes, have provided the basis for the international ITER Project, which is the next logical step in the development of fusion energy. The paper will describe ITER, its aims, its design, and the supporting manufacture of prototype components. The European contribution to ITER, the exploitation of the Joint European Torus (JET), and the long-term reactor technology R and D are carried out under the multilateral European Fusion Development Agreement (EFDA)

Programme for test generation for combinatorial and sequential systems

International Nuclear Information System (INIS)

Tran Huy Hoan

1973-01-01

This research thesis reports the computer-assisted search for tests aimed at failure detection in combinatorial and sequential logic circuits. As he wants to deal with complex circuits with many modules such as those met in large scale integrated circuits (LSI), the author used propagation paths. He reports the development of a method which is valid for combinatorial systems and for several sequential circuits comprising elementary logic modules and JK and RS flip-flops. This method is developed on an IBM 360/91 computer in PL/1 language. The used memory space is limited and adjustable with respect to circuit dimension. Computing time is short when compared to that needed by other programmes. The solution is practical and efficient for failure test and localisation

Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System

OpenAIRE

Yen, Mao-Hsu; Chen, Sao-Jie; Lan, Sanko H.

2001-01-01

The advantages of a Multi-Chip Module (MCM) product are its low-power and small-size. But the design of an MCM system usually requires weeks of engineering effort, thus we need a generic MCM substrate with programmable interconnections to accelerate system prototyping. In this paper, we propose a Symmetric and Programmable MCM (SPMCM) substrate for this purpose. This SPMCM substrate consists of a symmetrical array of slots for bare-chip attachment and Field Programmable Interco...

Some relationships between logic programming and multiple-valued logic

International Nuclear Information System (INIS)

Rine, D.C.

1986-01-01

There have been suggestions in the artificial intelligence literature that investigations into relationships between logic programming and multiple-valued logic may be helpful. This paper presents some of these relationships through equivalent algebraic evaluations

Methods for roof-top mini-arrays

Science.gov (United States)

Hazen, W. E.; Hazen, E. S.

1985-08-01

To test the idea of the Linsley effect mini array for the study of giant air showers, it is desirable to have a trigger that exploits the effect itself. In addition to the trigger, it is necessary to have a method for measuring the relative arrival times of the particle swarm selected by the trigger. Since the idea of mini arrays is likely to appeal to small research groups, it is desirable to try to design relatively simple and inexpensive methods, and methods that utilize existing detectors. Clusters of small detectors have been designed for operation in the local particle density realm where the probability of or = 2 particles per detector is small. Consequently, this method can discriminate pulses from each detector and thenceforth deal mainly with logic pulses.

[Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

Science.gov (United States)

Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

2015-12-01

Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

Corporate traveler centered development of a loyalty programme

OpenAIRE

Keskiväli, Mika

2015-01-01

This thesis is a qualitative case study that examined how the airline corporate sales client company employee (known as business traveler) engagement could be developed by the customer co-creation methods in the loyalty programme perspective. The thesis is using the service marketing theory and the service- and customer-dominant logics as the base in understanding the service development and the customer-centric approach. The business-to-business and the relationship marketing theories are in...

People Like Logical Truth: Testing the Intuitive Detection of Logical Value in Basic Propositions.

Directory of Open Access Journals (Sweden)

Hiroko Nakamura

Full Text Available Recent studies on logical reasoning have suggested that people are intuitively aware of the logical validity of syllogisms or that they intuitively detect conflict between heuristic responses and logical norms via slight changes in their feelings. According to logical intuition studies, logically valid or heuristic logic no-conflict reasoning is fluently processed and induces positive feelings without conscious awareness. One criticism states that such effects of logicality disappear when confounding factors such as the content of syllogisms are controlled. The present study used abstract propositions and tested whether people intuitively detect logical value. Experiment 1 presented four logical propositions (conjunctive, biconditional, conditional, and material implications regarding a target case and asked the participants to rate the extent to which they liked the statement. Experiment 2 tested the effects of matching bias, as well as intuitive logic, on the reasoners' feelings by manipulating whether the antecedent or consequent (or both of the conditional was affirmed or negated. The results showed that both logicality and matching bias affected the reasoners' feelings, and people preferred logically true targets over logically false ones for all forms of propositions. These results suggest that people intuitively detect what is true from what is false during abstract reasoning. Additionally, a Bayesian mixed model meta-analysis of conditionals indicated that people's intuitive interpretation of the conditional "if p then q" fits better with the conditional probability, q given p.

A programmable associative memory for track finding

International Nuclear Information System (INIS)

Bardi, A.; Belforte, S.; Donati, S.; Galeotti, S.; Giannetti, P.; Morsani, F.; Passuello, D.; Spinella, F.; Cerri, A.; Punzi, G.; Ristori, L.; Dell'Orso, M.; Meschi, E.; Leger, A.; Speer, T.; Wu, X.

1998-01-01

We present a device, based on the concept of associative memory for pattern recognition, dedicated to on-line track finding in high-energy physics experiments. A large pattern bank, describing all possible tracks, can be organized into field programmable gate arrays where all patterns are compared in parallel to data coming from the detector during readout. Patterns, recognized among 2 66 possible combinations, are output in a few 30 MHz clock cycles. Programmability results in a flexible, simple architecture and it allows to keep up smoothly with technology improvements. (orig.)

Concurrent weighted logic

DEFF Research Database (Denmark)

Xue, Bingtian; Larsen, Kim Guldstrand; Mardare, Radu Iulian

2015-01-01

We introduce Concurrent Weighted Logic (CWL), a multimodal logic for concurrent labeled weighted transition systems (LWSs). The synchronization of LWSs is described using dedicated functions that, in various concurrency paradigms, allow us to encode the compositionality of LWSs. To reflect these......-completeness results for this logic. To complete these proofs we involve advanced topological techniques from Model Theory....

Bias-free spin-wave phase shifter for magnonic logic

Energy Technology Data Exchange (ETDEWEB)

Louis, Steven; Tyberkevych, Vasyl; Slavin, Andrei [Department of Physics, Oakland University, 2200 N. Squirrel Rd., Rochester, Michigan, 48309–4401 (United States); Lisenkov, Ivan, E-mail: ivan.lisenkov@phystech.edu [Department of Physics, Oakland University, 2200 N. Squirrel Rd., Rochester, Michigan, 48309–4401 (United States); Kotelnikov Institute of Radio-engineering and Electronics of RAS, 11–7 Mokhovaya st., Moscow, 125009 (Russian Federation); Nikitov, Sergei [Kotelnikov Institute of Radio-engineering and Electronics of RAS, 11–7 Mokhovaya st., Moscow, 125009 (Russian Federation); Moscow Institute of Physics and Technology, 9 Instituskij per., Dolgoprudny, 141700, Moscow Region (Russian Federation); Department of Physics, Saratov State University, 83 Astrakhanskaya Street, Saratov, 410012 (Russian Federation)

2016-06-15

A design of a magnonic phase shifter operating without an external bias magnetic field is proposed. The phase shifter uses a localized collective spin wave mode propagating along a domain wall “waveguide” in a dipolarly-coupled magnetic dot array with a chessboard antiferromagnetic (CAFM) ground state. It is demonstrated numerically that the remagnetization of a single magnetic dot adjacent to the domain wall waveguide introduces a controllable phase shift in the propagating spin wave mode without significant change to the mode amplitude. It is also demonstrated that a logic XOR gate can be realized in the same system.

Pulling the trigger on LHC electronics

CERN Document Server

CERN. Geneva

2001-01-01

The conditions at CERN's Large Hadron Collider pose severe challenges for the designers and builders of front-end, trigger and data acquisition electronics. A recent workshop reviewed the encouraging progress so far and discussed what remains to be done. The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology. The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector perform...

Action Type Deontic Logic

DEFF Research Database (Denmark)

Bentzen, Martin Mose

2014-01-01

A new deontic logic, Action Type Deontic Logic, is presented. To motivate this logic, a number of benchmark cases are shown, representing inferences a deontic logic should validate. Some of the benchmark cases are singled out for further comments and some formal approaches to deontic reasoning...... are evaluated with respect to the benchmark cases. After that follows an informal introduction to the ideas behind the formal semantics, focussing on the distinction between action types and action tokens. Then the syntax and semantics of Action Type Deontic Logic is presented and it is shown to meet...

A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

Science.gov (United States)

Männer, R.

1989-12-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8 x 8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology.

A programmable systolic array correlator as a trigger processor for electron pairs in RICH (ring image Cherenkov) counters

International Nuclear Information System (INIS)

Maenner, R.

1989-01-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128x128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8x8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology. (orig.)

Quantifiers for quantum logic

OpenAIRE

Heunen, Chris

2008-01-01

We consider categorical logic on the category of Hilbert spaces. More generally, in fact, any pre-Hilbert category suffices. We characterise closed subobjects, and prove that they form orthomodular lattices. This shows that quantum logic is just an incarnation of categorical logic, enabling us to establish an existential quantifier for quantum logic, and conclude that there cannot be a universal quantifier.

Logic delays of 5-μm resistor coupled Josephson logic

International Nuclear Information System (INIS)

Sone, J.; Yoshida, T.; Tahara, S.; Abe, H.

1982-01-01

Logic delays of resistor coupled Josephson logic (RCJL) have been investigated. An experimental circuit with a cascade chain of ten RCJL OR gates was fabricated using Pb-alloy Josephson IC technology with 5-μm minimum linewidth. Logic delay was measured to be as low as 10.8 ps with power dissipation of 11.7 μW. This demonstrates a switching operation faster than those reported for other Josephson gate designs. Comparison with computer-simulation results is also presented

Radiation tolerant combinational logic cell

Science.gov (United States)

Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)

2009-01-01

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

Erotetic epistemic logic

Czech Academy of Sciences Publication Activity Database

Peliš, Michal

2017-01-01

Roč. 26, č. 3 (2017), s. 357-381 ISSN 1425-3305 R&D Projects: GA ČR(CZ) GC16-07954J Institutional support: RVO:67985955 Keywords : epistemic logic * erotetic implication * erotetic logic * logic of questions Subject RIV: AA - Philosophy ; Religion OBOR OECD: Philosophy, History and Philosophy of science and technology http://apcz.umk.pl/czasopisma/index.php/LLP/article/view/LLP.2017.007

Implementing IEC 61850-7-420 DER Logical Nodes in a single board

Directory of Open Access Journals (Sweden)

Anderson Salazar-Zuluaga

2017-09-01

Full Text Available This article discusses the implementation of a variety of logical nodes (LNs of power generation systems based on distributed energy resources (DER in a single board computer (SBC. The SBC allows for the acquisition and encapsulation of analog signals from a photovoltaic (PV array with batteries, based on the IEC 61850-7-420 standard. To achieve this, an SBC integrated with an analog-digital conversion card (ADC enables to read the system’s analog values. The SBC communicates with the ADC card to encapsulate the collected data in the IEC 61850 data object by using the corresponding logical node (LN. An open license library was used to create the IEC 61850 server inside the SBC and the driver of the ADC card manufacturer to communicate both cards. This work aims to develop LNs for DERs in such way that manufacturers of power generation technologies based on renewable sources (such as the sun and/or the wind implement Intelligent Electronic Devices (IED and controllers in accordance with the scope of the standard for these logical nodes (LNs. Finally, the communication testing of the implementation and the results obtained are presented.

The Football of Logic

Directory of Open Access Journals (Sweden)

Schang Fabien

2017-03-01

Full Text Available An analogy is made between two rather different domains, namely: logic, and football (or soccer. Starting from a comparative table between the two activities, an alternative explanation of logic is given in terms of players, ball, goal, and the like. Our main thesis is that, just as the task of logic is preserving truth from premises to the conclusion, footballers strive to keep the ball as far as possible until the opposite goal. Assuming this analogy may help think about logic in the same way as in dialogical logic, but it should also present truth-values in an alternative sense of speech-acts occurring in a dialogue. The relativity of truth-values is focused by this way, thereby leading to an additional way of logical pluralism.

The Logic of Practice in the Practice of Logics

DEFF Research Database (Denmark)

Raviola, Elena; Dubini, Paola

2016-01-01

of logics through a six months full-time ethnographic study at Il Sole-24 Ore, the largest Italian financial newspaper, between 2007 and 2008. An original conceptual framework is developed to analyse how the logic of journalism is enacted vis-à-vis that of advertising in a setting in which an old technology...... for news production – print newspaper – coexists with a new one – website – and thus encounters between new and old technological possibilities make workings of institutional logics particularly visible. The findings point out different mechanisms of institutional work dealing with actions that, made...

A fast-slow logic system

International Nuclear Information System (INIS)

Kawashima, Hideo.

1977-01-01

A fast-slow logic system has been made for use in multi-detector experiments in nuclear physics such as particle-gamma and particle-particle coincidence experiments. The system consists of a fast logic system and a slow logic system. The fast logic system has a function of fast coincidences and provides timing signals for the slow logic system. The slow logic system has a function of slow coincidences and a routing control of input analog signals to the ADCs. (auth.)

Adaptive Fuzzy Logic based MPPT Control for PV System Under Partial Shading Condition

OpenAIRE

Choudhury, Subhashree; Rout, Pravat Kumar

2016-01-01

Partial shading causes power loss, hotspots and threatens the reliability of the Photovoltaic generation system. Moreover characteristic curves exhibit multiple peaks. Conventional MPPT techniques under this condition often fail to give optimum MPP. Focusing on the afore mentioned problem an attempt has been made to design an Adaptive Takagi-Sugeno Fuzzy Inference System based Fuzzy Logic Control MPPT.The mathematical model of PV array is simulated using in MATLAB/Simulink environment.Various...

Logical NAND and NOR Operations Using Algorithmic Self-assembly of DNA Molecules

Science.gov (United States)

Wang, Yanfeng; Cui, Guangzhao; Zhang, Xuncai; Zheng, Yan

DNA self-assembly is the most advanced and versatile system that has been experimentally demonstrated for programmable construction of patterned systems on the molecular scale. It has been demonstrated that the simple binary arithmetic and logical operations can be computed by the process of self assembly of DNA tiles. Here we report a one-dimensional algorithmic self-assembly of DNA triple-crossover molecules that can be used to execute five steps of a logical NAND and NOR operations on a string of binary bits. To achieve this, abstract tiles were translated into DNA tiles based on triple-crossover motifs. Serving as input for the computation, long single stranded DNA molecules were used to nucleate growth of tiles into algorithmic crystals. Our method shows that engineered DNA self-assembly can be treated as a bottom-up design techniques, and can be capable of designing DNA computer organization and architecture.

Topology optimization of Halbach magnet arrays using isoparametric projection

International Nuclear Information System (INIS)

Lee, Jaewook; Nomura, Tsuyoshi; Dede, Ercan M.

2017-01-01

Highlights: • Design method of Halbach magnet array is proposed using topology optimization. • Magnet strength and direction are simultaneously optimized by isoparametric projection. • For manufacturing feasibility of magnet, penalization and extrusion schemes are proposed. • Design results of circular shaped Halbach arrays are provided. • Halbach arrays in linear actuator are optimized to maximize magnetic force. - Abstract: Topology optimization using isoparametric projection for the design of permanent magnet patterns in Halbach arrays is proposed. Based on isoparametric shape functions used in the finite element analysis, the permanent magnet strength and magnetization directions in a Halbach array are simultaneously optimized for a given design goal. To achieve fabrication feasibility of a designed Halbach magnet array, two design schemes are combined with the isoparametric projection method. First, a penalization scheme is proposed for designing the permanent magnets to have discrete magnetization direction angles. Second, an extrusion scheme is proposed for the shape regularization of the permanent magnet segments. As a result, the method systematically finds the optimal permanent magnet patterns of a Halbach array considering manufacturing feasibility. In two numerical examples, a circular shaped permanent magnet Halbach array is designed to minimize the magnitude of the magnetic flux density and to maximize the upward direction magnetic flux density inside the magnet array. Logical extension of the method to the design of permanent magnet arrays in linear actuators is provided, where the design goal is to maximize the actuator magnetic force.

Topology optimization of Halbach magnet arrays using isoparametric projection

Energy Technology Data Exchange (ETDEWEB)

Lee, Jaewook, E-mail: jaewooklee@gist.ac.kr [School of Mechanical Engineering, Gwangju Institute of Science and Technology (GIST), Gwangju, 61005 (Korea, Republic of); Nomura, Tsuyoshi [Toyota Central R& D Labs., Inc., 41-1 Yokomichi, Aichi 480-1192 (Japan); Toyota Research Institute of North America, 1555 Woodridge Avenue, Ann Arbor, MI 48105 (United States); Dede, Ercan M. [Toyota Research Institute of North America, 1555 Woodridge Avenue, Ann Arbor, MI 48105 (United States)

2017-06-15

Highlights: • Design method of Halbach magnet array is proposed using topology optimization. • Magnet strength and direction are simultaneously optimized by isoparametric projection. • For manufacturing feasibility of magnet, penalization and extrusion schemes are proposed. • Design results of circular shaped Halbach arrays are provided. • Halbach arrays in linear actuator are optimized to maximize magnetic force. - Abstract: Topology optimization using isoparametric projection for the design of permanent magnet patterns in Halbach arrays is proposed. Based on isoparametric shape functions used in the finite element analysis, the permanent magnet strength and magnetization directions in a Halbach array are simultaneously optimized for a given design goal. To achieve fabrication feasibility of a designed Halbach magnet array, two design schemes are combined with the isoparametric projection method. First, a penalization scheme is proposed for designing the permanent magnets to have discrete magnetization direction angles. Second, an extrusion scheme is proposed for the shape regularization of the permanent magnet segments. As a result, the method systematically finds the optimal permanent magnet patterns of a Halbach array considering manufacturing feasibility. In two numerical examples, a circular shaped permanent magnet Halbach array is designed to minimize the magnitude of the magnetic flux density and to maximize the upward direction magnetic flux density inside the magnet array. Logical extension of the method to the design of permanent magnet arrays in linear actuators is provided, where the design goal is to maximize the actuator magnetic force.

Logic for Physicists

Science.gov (United States)

Pereyra, Nicolas A.

2018-06-01

This book gives a rigorous yet 'physics-focused' introduction to mathematical logic that is geared towards natural science majors. We present the science major with a robust introduction to logic, focusing on the specific knowledge and skills that will unavoidably be needed in calculus topics and natural science topics in general (rather than taking a philosophical-math-fundamental oriented approach that is commonly found in mathematical logic textbooks).

Logic of likelihood

International Nuclear Information System (INIS)

Wall, M.J.W.

1992-01-01

The notion of open-quotes probabilityclose quotes is generalized to that of open-quotes likelihood,close quotes and a natural logical structure is shown to exist for any physical theory which predicts likelihoods. Two physically based axioms are given for this logical structure to form an orthomodular poset, with an order-determining set of states. The results strengthen the basis of the quantum logic approach to axiomatic quantum theory. 25 refs

Fuzzy Logic Approach for the Prediction of Dross Formation in CO2 Laser Cutting of Mild Steel

Directory of Open Access Journals (Sweden)

Miloš Madić

2015-11-01

Full Text Available Dross free laser cutting is very important in the application of laser cutting technology. This paper focuses on the development of a fuzzy logic model to predict dross formation in CO2 laser oxygen cutting of mild steel. Laser cutting experiment, conducted according to Taguchi’s experimental design using L25 orthogonal array, provided a set of data for the development of a fuzzy rule base. The predicting fuzzy logic model is based on using Mamdani-type inference system. Developed fuzzy logic model considered the cutting speed, laser power and assist gas pressure as inputs. Using this model the effects of the selected laser cutting parameters on the dross formation were investigated. Additionally, 3-D surface plots were generated to study the interaction effects of the laser cutting parameters. The analysis revealed that the cutting speed has the most significant effect, followed by laser power and assist gas pressure. The results indicated that the fuzzy logic modeling approach can be effectively used for the dross formation prediction in CO2 laser cutting of mild steel.

The European fusion research and development programme and the ITER Project

International Nuclear Information System (INIS)

Green, B.J.

2004-01-01

The EURATOM fusion R and D programme is a well integrated and co-ordinated programme a good example of a European Research Area. Its goal is 'the joint creation of prototype reactors for power stations to meet the needs of society: operational safety, environmental compatibility, economic viability'. The programme is focussed on the magnetic confinement approach to fusion energy and supports 21 associated laboratories and a range of experimental and fusion technology facilities. The paper will briefly describe this programme and how it is organised and implemented. Its success and that of other national programmes has defined the international ITER Project, which is the next logical step in fusion R and D. The paper will describe ITER, its aims, its design, and the supporting manufacture of prototype components. The European contribution to ITER, as well as the exploitation of the Joint European Torus (JET) and long-term fusion reactor technology R and D are carried out under the European Fusion Development Agreement (EFDA). Finally, the potential advantages of fusion as an energy source will be presented. (author)

Microelectromechanical reprogrammable logic device

KAUST Repository

Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.

2016-01-01

on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance

One reason, several logics

Directory of Open Access Journals (Sweden)

Evandro Agazzi

2011-06-01

Full Text Available Humans have used arguments for defending or refuting statements long before the creation of logic as a specialized discipline. This can be interpreted as the fact that an intuitive notion of "logical consequence" or a psychic disposition to articulate reasoning according to this pattern is present in common sense, and logic simply aims at describing and codifying the features of this spontaneous capacity of human reason. It is well known, however, that several arguments easily accepted by common sense are actually "logical fallacies", and this indicates that logic is not just a descriptive, but also a prescriptive or normative enterprise, in which the notion of logical consequence is defined in a precise way and then certain rules are established in order to maintain the discourse in keeping with this notion. Yet in the justification of the correctness and adequacy of these rules commonsense reasoning must necessarily be used, and in such a way its foundational role is recognized. Moreover, it remains also true that several branches and forms of logic have been elaborated precisely in order to reflect the structural features of correct argument used in different fields of human reasoning and yet insufficiently mirrored by the most familiar logical formalisms.

Three challenges to the complementarity of the logic and the pragmatics of science.

Science.gov (United States)

Uebel, Thomas

2015-10-01

The bipartite metatheory thesis attributes to Rudolf Carnap, Philipp Frank and Otto Neurath a conception of the nature of post-metaphysical philosophy of science that sees the purely formal-logical analyses of the logic of science as complemented by empirical inquiries into the psychology, sociology and history of science. Three challenges to this thesis are considered in this paper: that Carnap did not share this conception of the nature of philosophy of science even on a programmatic level, that Carnap's detailed analysis of the language of science is incompatible with one developed by Neurath for the pursuit of empirical studies of science, and, finally, that Neurath himself was confused about the programme of which the bipartite metatheory thesis makes him a representative. I argue that all three challenges can be met and refuted. Copyright © 2015 Elsevier Ltd. All rights reserved.

GOAL Agents Instantiate Intention Logic

OpenAIRE

Hindriks, Koen; van der Hoek, Wiebe

2008-01-01

It is commonly believed there is a big gap between agent logics and computational agent frameworks. In this paper, we show that this gap is not as big as believed by showing that GOAL agents instantiate Intention Logic of Cohen and Levesque. That is, we show that GOAL agent programs can be formally related to Intention Logic.We do so by proving that the GOAL Verification Logic can be embedded into Intention Logic. It follows that (a fragment of) Intention Logic can be used t...

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Energy Technology Data Exchange (ETDEWEB)

Kish, Laszlo B. [Texas A and M University, Department of Electrical and Computer Engineering, College Station, TX 77843-3128 (United States)], E-mail: laszlo.kish@ece.tamu.edu

2009-03-02

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

International Nuclear Information System (INIS)

Kish, Laszlo B.

2009-01-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case (N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart

Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states

Science.gov (United States)

Kish, Laszlo B.

2009-03-01

A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case ( N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.

Intelligent layered nanoflare: ``lab-on-a-nanoparticle'' for multiple DNA logic gate operations and efficient intracellular delivery

Science.gov (United States)

Yang, Bin; Zhang, Xiao-Bing; Kang, Li-Ping; Huang, Zhi-Mei; Shen, Guo-Li; Yu, Ru-Qin; Tan, Weihong

2014-07-01

DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of Boolean logic gate operations, including three basic logic gates, one three-input AND gate, and two complex logic operations, in a digital non-leaky way. In addition, the layered nanoflare can serve as a programmable strategy to sequentially tune the size of nanoparticles, as well as a new fingerprint spectrum technique for intelligent multiplex biosensing. More importantly, the nanoflare developed here can also act as a single entity for intracellular DNA logic gate delivery, without the need of commercial transfection agents or other auxiliary carriers. By incorporating DNA circuits on nanoparticles, the presented layered nanoflare will broaden the applications of DNA circuits in biological systems, and facilitate the development of DNA nanotechnology.DNA strand displacement cascades have been engineered to construct various fascinating DNA circuits. However, biological applications are limited by the insufficient cellular internalization of naked DNA structures, as well as the separated multicomponent feature. In this work, these problems are addressed by the development of a novel DNA nanodevice, termed intelligent layered nanoflare, which integrates DNA computing at the nanoscale, via the self-assembly of DNA flares on a single gold nanoparticle. As a ``lab-on-a-nanoparticle'', the intelligent layered nanoflare could be engineered to perform a variety of

Logic circuits based on individual semiconducting and metallic carbon-nanotube devices

International Nuclear Information System (INIS)

Ryu, Hyeyeon; Kaelblein, Daniel; Ante, Frederik; Zschieschang, Ute; Kern, Klaus; Klauk, Hagen; Weitz, R Thomas; Schmidt, Oliver G

2010-01-01

Nanoscale transistors employing an individual semiconducting carbon nanotube as the channel hold great potential for logic circuits with large integration densities that can be manufactured on glass or plastic substrates. Carbon nanotubes are usually produced as a mixture of semiconducting and metallic nanotubes. Since only semiconducting nanotubes yield transistors, the metallic nanotubes are typically not utilized. However, integrated circuits often require not only transistors, but also resistive load devices. Here we show that many of the metallic carbon nanotubes that are deposited on the substrate along with the semiconducting nanotubes can be conveniently utilized as load resistors with favorable characteristics for the design of integrated circuits. We also demonstrate the fabrication of arrays of transistors and resistors, each based on an individual semiconducting or metallic carbon nanotube, and their integration on glass substrates into logic circuits with switching frequencies of up to 500 kHz using a custom-designed metal interconnect layer.

Full-frame, programmable hyperspectral imager

Science.gov (United States)

Love, Steven P.; Graff, David L.

2017-07-25

A programmable, many-band spectral imager based on addressable spatial light modulators (ASLMs), such as micro-mirror-, micro-shutter- or liquid-crystal arrays, is described. Capable of collecting at once, without scanning, a complete two-dimensional spatial image with ASLM spectral processing applied simultaneously to the entire image, the invention employs optical assemblies wherein light from all image points is forced to impinge at the same angle onto the dispersing element, eliminating interplay between spatial position and wavelength. This is achieved, as examples, using telecentric optics to image light at the required constant angle, or with micro-optical array structures, such as micro-lens- or capillary arrays, that aim the light on a pixel-by-pixel basis. Light of a given wavelength then emerges from the disperser at the same angle for all image points, is collected at a unique location for simultaneous manipulation by the ASLM, then recombined with other wavelengths to form a final spectrally-processed image.

Neuron array with plastic synapses and programmable dendrites.

Science.gov (United States)

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Using evaluability assessment to assess local community development health programmes: a Scottish case-study

Directory of Open Access Journals (Sweden)

Melissa Belford

2017-04-01

Full Text Available Abstract Background Evaluation of the potential effectiveness of a programme’s objectives (health or otherwise is important in demonstrating how programmes work. However, evaluations are expensive and can focus on unrealistic outcomes not grounded in strong theory, especially where there is pressure to show effectiveness. The aim of this research was to demonstrate that the evaluability assessment (a cost-effective pre-evaluation tool that primarily gives quick, constructive feedback can be used to help develop programme and outcome objectives to improve programmes while they run and to assist in producing more effective evaluations. This was done using the example of a community development programme aiming to improve health and reduce health inequalities in its target population. Methods The setting was Glasgow, Scotland, UK and focused on the Health Issues in the Community programme. Data were collected from documents and nine individual stakeholder interviews. Thematic analysis and a realist approach were used to analyse both datasets and, in conjunction with a workshop with stakeholders, produce a logic model of the programme theory and related evaluation options to explore further. Results Five main themes emerged from the analysis: History; Framework; Structure and Delivery of the Course; Theory of Action; and Barriers to Delivery and Successful Outcomes. These themes aided in drafting the logic model which revealed they key programme activities (e.g. facilitating group learning and 23 potential outcomes. The majority of these outcomes (16 were deemed to be short-term outcomes (more easily measured within the timeframe of an individual being involved in the programme e.g. increased self-esteem or awareness of individual/community health. The remaining 6 outcomes were deemed longer-term and included outcomes such as increased social capital and individual mental health and wellbeing. Conclusions We have shown that the evaluability

Understanding Social Media Logic

Directory of Open Access Journals (Sweden)

José van Dijck

2013-08-01

Full Text Available Over the past decade, social media platforms have penetrated deeply into the mech­anics of everyday life, affecting people's informal interactions, as well as institutional structures and professional routines. Far from being neutral platforms for everyone, social media have changed the conditions and rules of social interaction. In this article, we examine the intricate dynamic between social media platforms, mass media, users, and social institutions by calling attention to social media logic—the norms, strategies, mechanisms, and economies—underpin­ning its dynamics. This logic will be considered in light of what has been identified as mass me­dia logic, which has helped spread the media's powerful discourse outside its institutional boundaries. Theorizing social media logic, we identify four grounding principles—programmabil­ity, popularity, connectivity, and datafication—and argue that these principles become increas­ingly entangled with mass media logic. The logic of social media, rooted in these grounding principles and strategies, is gradually invading all areas of public life. Besides print news and broadcasting, it also affects law and order, social activism, politics, and so forth. Therefore, its sustaining logic and widespread dissemination deserve to be scrutinized in detail in order to better understand its impact in various domains. Concentrating on the tactics and strategies at work in social media logic, we reassess the constellation of power relationships in which social practices unfold, raising questions such as: How does social media logic modify or enhance ex­isting mass media logic? And how is this new media logic exported beyond the boundaries of (social or mass media proper? The underlying principles, tactics, and strategies may be relat­ively simple to identify, but it is much harder to map the complex connections between plat­forms that distribute this logic: users that employ them, technologies that

Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors.

Science.gov (United States)

Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin

2016-06-22

In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.

Conference Trends in Logic XI

CERN Document Server

Wansing, Heinrich; Willkommen, Caroline; Recent Trends in Philosophical Logic

2014-01-01

This volume presents recent advances in philosophical logic with chapters focusing on non-classical logics, including paraconsistent logics, substructural logics, modal logics of agency and other modal logics. The authors cover themes such as the knowability paradox, tableaux and sequent calculi, natural deduction, definite descriptions, identity, truth, dialetheism, and possible worlds semantics.   The developments presented here focus on challenging problems in the specification of fundamental philosophical notions, as well as presenting new techniques and tools, thereby contributing to the development of the field. Each chapter contains a bibliography, to assist the reader in making connections in the specific areas covered. Thus this work provides both a starting point for further investigations into philosophical logic and an update on advances, techniques and applications in a dynamic field.   The chapters originate from papers presented during the Trends in Logic XI conference at the Ruhr University ...

Logic analysis and verification of n-input genetic logic circuits

DEFF Research Database (Denmark)

Baig, Hasan; Madsen, Jan

2017-01-01

. In this paper, we present an approach to analyze and verify the Boolean logic of a genetic circuit from the data obtained through stochastic analog circuit simulations. The usefulness of this analysis is demonstrated through different case studies illustrating how our approach can be used to verify the expected......Nature is using genetic logic circuits to regulate the fundamental processes of life. These genetic logic circuits are triggered by a combination of external signals, such as chemicals, proteins, light and temperature, to emit signals to control other gene expressions or metabolic pathways...... accordingly. As compared to electronic circuits, genetic circuits exhibit stochastic behavior and do not always behave as intended. Therefore, there is a growing interest in being able to analyze and verify the logical behavior of a genetic circuit model, prior to its physical implementation in a laboratory...

Prospects of luminescence based molecular scale logic gates and logic circuits

International Nuclear Information System (INIS)

Speiser, Shammai

2016-01-01

In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder

Prospects of luminescence based molecular scale logic gates and logic circuits

Energy Technology Data Exchange (ETDEWEB)

Speiser, Shammai, E-mail: speiser@technion.ac.il

2016-01-15

In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder.

Application of linear logic to simulation

Science.gov (United States)

Clarke, Thomas L.

1998-08-01

Linear logic, since its introduction by Girard in 1987 has proven expressive and powerful. Linear logic has provided natural encodings of Turing machines, Petri nets and other computational models. Linear logic is also capable of naturally modeling resource dependent aspects of reasoning. The distinguishing characteristic of linear logic is that it accounts for resources; two instances of the same variable are considered differently from a single instance. Linear logic thus must obey a form of the linear superposition principle. A proportion can be reasoned with only once, unless a special operator is applied. Informally, linear logic distinguishes two kinds of conjunction, two kinds of disjunction, and also introduces a modal storage operator that explicitly indicates propositions that can be reused. This paper discuses the application of linear logic to simulation. A wide variety of logics have been developed; in addition to classical logic, there are fuzzy logics, affine logics, quantum logics, etc. All of these have found application in simulations of one sort or another. The special characteristics of linear logic and its benefits for simulation will be discussed. Of particular interest is a connection that can be made between linear logic and simulated dynamics by using the concept of Lie algebras and Lie groups. Lie groups provide the connection between the exponential modal storage operators of linear logic and the eigen functions of dynamic differential operators. Particularly suggestive are possible relations between complexity result for linear logic and non-computability results for dynamical systems.

Microprocessor system design a practical introduction

CERN Document Server

Spinks, Michael J

2013-01-01

Microprocessor System Design: A Practical Introduction describes the concepts and techniques incorporated into the design of electronic circuits, particularly microprocessor boards and their peripherals. The book reviews the basic building blocks of the electronic systems composed of digital (logic levels, gate output circuitry) and analog components (resistors, capacitors, diodes, transistors). The text also describes operational amplifiers (op-amp) that use a negative feedback technique to improve the parameters of the op-amp. The design engineer can use programmable array logic (PAL) to rep

R-1 (C-620-A) and R-2 (C-620-B) air compressor control logic, computer software description. Revision 1

International Nuclear Information System (INIS)

Walter, K.E.

1995-01-01

This document provides an updated computer software description for the software used on the FFTF R-1 (C-620-A) and R-2 (C-620-B) air compressor programmable controllers. Logic software design changes were required to allow automatic starting of a compressor that had not been previously started

Quantum logics with existence property

International Nuclear Information System (INIS)

Schindler, C.

1991-01-01

A quantum logic (σ-orthocomplete orthomodular poset L with a convex, unital, and separating set Δ of states) is said to have the existence property if the expectation functionals on lin(Δ) associated with the bounded observables of L form a vector space. Classical quantum logics as well as the Hilbert space logics of traditional quantum mechanics have this property. The author shows that, if a quantum logic satisfies certain conditions in addition to having property E, then the number of its blocks (maximal classical subsystems) must either be one (classical logics) or uncountable (as in Hilbert space logics)

A water pumping control system with a programmable logic controller (PLC) and industrial wireless modules for industrial plants--an experimental setup.

Science.gov (United States)

Bayindir, Ramazan; Cetinceviz, Yucel

2011-04-01

This paper describes a water pumping control system that is designed for production plants and implemented in an experimental setup in a laboratory. These plants contain harsh environments in which chemicals, vibrations or moving parts exist that could potentially damage the cabling or wires that are part of the control system. Furthermore, the data has to be transferred over paths that are accessible to the public. The control systems that it uses are a programmable logic controller (PLC) and industrial wireless local area network (IWLAN) technologies. It is implemented by a PLC, an communication processor (CP), two IWLAN modules, and a distributed input/output (I/O) module, as well as the water pump and sensors. Our system communication is based on an Industrial Ethernet and uses the standard Transport Control Protocol/Internet Protocol for parameterisation, configuration and diagnostics. The main function of the PLC is to send a digital signal to the water pump to turn it on or off, based on the tank level, using a pressure transmitter and inputs from limit switches that indicate the level of the water in the tank. This paper aims to provide a convenient solution in process plants where cabling is not possible. It also has lower installation and maintenance cost, provides reliable operation, and robust and flexible construction, suitable for industrial applications. Copyright © 2010 ISA. Published by Elsevier Ltd. All rights reserved.

Complex cellular logic computation using ribocomputing devices.

Science.gov (United States)

Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

2017-08-03

Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

Flat Coalgebraic Fixed Point Logics

Science.gov (United States)

Schröder, Lutz; Venema, Yde

Fixed point logics are widely used in computer science, in particular in artificial intelligence and concurrency. The most expressive logics of this type are the μ-calculus and its relatives. However, popular fixed point logics tend to trade expressivity for simplicity and readability, and in fact often live within the single variable fragment of the μ-calculus. The family of such flat fixed point logics includes, e.g., CTL, the *-nesting-free fragment of PDL, and the logic of common knowledge. Here, we extend this notion to the generic semantic framework of coalgebraic logic, thus covering a wide range of logics beyond the standard μ-calculus including, e.g., flat fragments of the graded μ-calculus and the alternating-time μ-calculus (such as ATL), as well as probabilistic and monotone fixed point logics. Our main results are completeness of the Kozen-Park axiomatization and a timed-out tableaux method that matches ExpTime upper bounds inherited from the coalgebraic μ-calculus but avoids using automata.

Quantum-classical interface based on single flux quantum digital logic

Science.gov (United States)

McDermott, R.; Vavilov, M. G.; Plourde, B. L. T.; Wilhelm, F. K.; Liebermann, P. J.; Mukhanov, O. A.; Ohki, T. A.

2018-04-01

We describe an approach to the integrated control and measurement of a large-scale superconducting multiqubit array comprising up to 108 physical qubits using a proximal coprocessor based on the Single Flux Quantum (SFQ) digital logic family. Coherent control is realized by irradiating the qubits directly with classical bitstreams derived from optimal control theory. Qubit measurement is performed by a Josephson photon counter, which provides access to the classical result of projective quantum measurement at the millikelvin stage. We analyze the power budget and physical footprint of the SFQ coprocessor and discuss challenges and opportunities associated with this approach.

MEMS Logic Using Mixed-Frequency Excitation

KAUST Repository

Ilyas, Saad

2017-06-22

We present multi-function microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, OR, universal logic gates NAND, NOR, and a tristate logic gate using mixed-frequency excitation. The concept is based on exciting combination resonances due to the mixing of two or more input signals. The device vibrates at two steady states: a high state when the combination resonance is activated and a low state when no resonance is activated. These vibration states are assigned to logical value 1 or 0 to realize the logic gates. Using ac signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. We found that the energy consumption per cycle of the proposed logic resonator is higher than those of existing technologies. Hence, integration of such logic devices to build complex computational system needs to take into consideration lowering the total energy consumption. [2017-0041

Dynamic array of dark optical traps

DEFF Research Database (Denmark)

Daria, V.R.; Rodrigo, P.J.; Glückstad, J.

2004-01-01

A dynamic array of dark optical traps is generated for simultaneous trapping and arbitrary manipulation of multiple low-index microstructures. The dynamic intensity patterns forming the dark optical trap arrays are generated using a nearly loss-less phase-to-intensity conversion of a phase......-encoded coherent light source. Two-dimensional input phase distributions corresponding to the trapping patterns are encoded using a computer-programmable spatial light modulator, enabling each trap to be shaped and moved arbitrarily within the plane of observation. We demonstrate the generation of multiple dark...... optical traps for simultaneous manipulation of hollow "air-filled" glass microspheres suspended in an aqueous medium. (C) 2004 American Institute of Physics....

Amplifying genetic logic gates.

Science.gov (United States)

Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

2013-05-03

Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

Design of Circularly-Polarised, Crossed Drooping Dipole, Phased Array Antenna Using Genetic Algorithm Optimisation

DEFF Research Database (Denmark)

Larsen, Niels Vesterdal

2007-01-01

A printed drooping dipole array is designed and constructed. The design is based on a genetic algorithm optimisation procedure used in conjunction with the software programme AWAS. By optimising the array G/T for specific combinations of scan angles and frequencies an optimum design is obtained...

The Quantum Logical Challenge: Peter Mittelstaedt's Contributions to Logic and Philosophy of Science

Science.gov (United States)

Beltrametti, E.; Dalla Chiara, M. L.; Giuntini, R.

2017-12-01

Peter Mittelstaedt's contributions to quantum logic and to the foundational problems of quantum theory have significantly realized the most authentic spirit of the International Quantum Structures Association: an original research about hard technical problems, which are often "entangled" with the emergence of important changes in our general world-conceptions. During a time where both the logical and the physical community often showed a skeptical attitude towards Birkhoff and von Neumann's quantum logic, Mittelstaedt brought into light the deeply innovating features of a quantum logical thinking that allows us to overcome some strong and unrealistic assumptions of classical logical arguments. Later on his intense research on the unsharp approach to quantum theory and to the measurement problem stimulated the increasing interest for unsharp forms of quantum logic, creating a fruitful interaction between the work of quantum logicians and of many-valued logicians. Mittelstaedt's general views about quantum logic and quantum theory seem to be inspired by a conjecture that is today more and more confirmed: there is something universal in the quantum theoretic formalism that goes beyond the limits of microphysics, giving rise to interesting applications to a number of different fields.

Querying Natural Logic Knowledge Bases

DEFF Research Database (Denmark)

Andreasen, Troels; Bulskov, Henrik; Jensen, Per Anker

2017-01-01

This paper describes the principles of a system applying natural logic as a knowledge base language. Natural logics are regimented fragments of natural language employing high level inference rules. We advocate the use of natural logic for knowledge bases dealing with querying of classes...... in ontologies and class-relationships such as are common in life-science descriptions. The paper adopts a version of natural logic with recursive restrictive clauses such as relative clauses and adnominal prepositional phrases. It includes passive as well as active voice sentences. We outline a prototype...... for partial translation of natural language into natural logic, featuring further querying and conceptual path finding in natural logic knowledge bases....

Use of FPGA and CPLD in nuclear reactor safety systems and its regulatory review requirements for reactor safety

International Nuclear Information System (INIS)

Roy, Suvadip; Biswas, Animesh; Pradhan, S.K.

2015-01-01

Field Programmable Gate Arrays (FPGA) and Complex Programmable Logic Devices (CPLD) is being used widely in safety critical and safety related systems in nuclear power plans like in trip logic units, Engineered Safety Feature (ESF) actuation decision logic and neutronic signal processing for their reprogrammability feature and compact design. These HDL Programmable devices (HPD) are complex devices consisting of both hardware and software which is used to implement the logic on the FPGA. It is observed that these Programmable devices suffer from various modes of failure and the major failures in these devices are due to Single Event Upset (SEU), where a highly energetic ionizing radiation may lead to device failure which can even occur in radiologically benign environment. Other failures can occur during steps of developing the hardware using software tools like during Synthesis and placement and routing of the desired hardware. Here a study on use of such devices in Nuclear Reactors, study on mode of failures of these devices, way to tackle such failure and development of review guidelines for review of such devices used in safety critical and safety related systems with special emphasis on choice of software tools, way to mitigate effects of SEU and simulation and hardware testing results to be reviewed by regulatory body during design safety review is done. (author)

Questions and dependency in intuitionistic logic

NARCIS (Netherlands)

Ciardelli, Ivano; Iemhoff, Rosalie; Yang, Fan

2017-01-01

In recent years, the logic of questions and dependencies has been investigated in the closely related frameworks of inquisitive logic and dependence logic. These investigations have assumed classical logic as the background logic of statements, and added formulas expressing questions and

Logic Meeting

CERN Document Server

Tugué, Tosiyuki; Slaman, Theodore

1989-01-01

These proceedings include the papers presented at the logic meeting held at the Research Institute for Mathematical Sciences, Kyoto University, in the summer of 1987. The meeting mainly covered the current research in various areas of mathematical logic and its applications in Japan. Several lectures were also presented by logicians from other countries, who visited Japan in the summer of 1987.

Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

International Nuclear Information System (INIS)

Hennig, Christine; Kneupner, Klaus; Kinna, David

2012-01-01

Highlights: ► We describe 2 ways connecting PLCs to fusion control and data acquisition software. ► At W7-X standardization of the PLC type eases the maintenance of the software. ► At JET PLCs are interfaced with a daemon that hides the PLC specific part. ► There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse “black box protocol” approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and observed via timeout mechanisms. The use of PLCs for Wendelstein 7-X is standardized. Therefore a single

Connecting programmable logic controllers (PLC) to control and data acquisition a comparison of the JET and Wendelstein 7-X approach

Energy Technology Data Exchange (ETDEWEB)

Hennig, Christine, E-mail: Christine.Hennig@ipp.mpg.de [Max-Planck-Institut fuer Plasmaphysik, Wendelsteinstrasse 1, 17491 Greifswald (Germany); Kneupner, Klaus; Kinna, David [JET-EFDA, Culham Science Centre, OX14 3DB Abingdon (United Kingdom)

2012-12-15

Highlights: Black-Right-Pointing-Pointer We describe 2 ways connecting PLCs to fusion control and data acquisition software. Black-Right-Pointing-Pointer At W7-X standardization of the PLC type eases the maintenance of the software. Black-Right-Pointing-Pointer At JET PLCs are interfaced with a daemon that hides the PLC specific part. Black-Right-Pointing-Pointer There is potential to unify the approaches towards a common fusion PLC interface. - Abstract: The use of programmable logic controllers (PLC) for automation of electromechanical processes is an industrial control system technology. It is more and more in use within the fusion community. Traditionally PLC based systems are operated and maintained using proprietary SCADA systems (supervisory control and data acquisition). They are hardly ever integrated with the fusion control and data acquisition systems. An overview of the state of the art in fusion is given in the article. At JET an inhouse 'black box protocol' approach has been developed to communicate with any external system via a dedicated http based protocol. However, a PLC usually cannot be modified to implement this special protocol. Hence, a software layer has been developed that interfaces a PLC by implementing the PLC specific communication part on one side and the black box protocol part on the other side. The software is completely data driven i.e. editing the data structure changes the logic accordingly. It can be tested using the web capability of the black box protocol. Multiple PLC types from different vendors are supported, thus multiple protocols to interface the PLC are in use. Depending on the PLC type and available tools it can be necessary to program the PLC accordingly. Wendelstein 7-X uses another approach. For every single PLC a dedicated communication from and to CoDaC is implemented. This communication is projected (programmed) in the PLC and configurable (data driven) on the CoDaC side. The protocol is UDP based and

What is mathematical logic?

CERN Document Server

Crossley, J N; Brickhill, CJ; Stillwell, JC

2010-01-01

Although mathematical logic can be a formidably abstruse topic, even for mathematicians, this concise book presents the subject in a lively and approachable fashion. It deals with the very important ideas in modern mathematical logic without the detailed mathematical work required of those with a professional interest in logic.The book begins with a historical survey of the development of mathematical logic from two parallel streams: formal deduction, which originated with Aristotle, Euclid, and others; and mathematical analysis, which dates back to Archimedes in the same era. The streams beg

Introduction to mathematical logic

CERN Document Server

Mendelson, Elliott

2015-01-01

The new edition of this classic textbook, Introduction to Mathematical Logic, Sixth Edition explores the principal topics of mathematical logic. It covers propositional logic, first-order logic, first-order number theory, axiomatic set theory, and the theory of computability. The text also discusses the major results of Gödel, Church, Kleene, Rosser, and Turing.The sixth edition incorporates recent work on Gödel's second incompleteness theorem as well as restoring an appendix on consistency proofs for first-order arithmetic. This appendix last appeared in the first edition. It is offered in th

A Logic for Choreographies

DEFF Research Database (Denmark)

Lopez, Hugo Andres; Carbone, Marco; Hildebrandt, Thomas

2010-01-01

We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL...... ), a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof...

A novel GUI modeled fuzzy logic controller for a solar powered energy utilization scheme

International Nuclear Information System (INIS)

Altas, I. H.; Sharaf, A. M.

2007-01-01

Photovoltaic PVA-solar powered electrical systems comprise different components and subsystems to be controlled separately. Since the generated solar power is dependant on uncontrollable environmental conditions, it requires extra caution to design controllers that handle unpredictable events and maintain efficient load matching power. In this study, a photovoltaic (PV) solar array model is developed for Matlab/Simulink GUI environment and controlled using a fuzzy logic controller (FLC), which is also developed for GUI environment. The FLC is also used to control the DC load bus voltage at constant value as well as controlling the speed of a PMDC motor as one of the loads being fed. The FLC controller designed using the Matlab/Simuling GUI environment has flexible design criteria's so that it can easily be modified and extended for controlling different systems. The proposed FLC is used in three different parts of the PVA stand alone utilization scheme here. One of these parts is the speed control of the PMDC load, one of the other parts is controlling the DC load bus voltage, and the third part is the maximum power point (MPPT) tracking control, which is used to operate the PVA at its available maximum power as the solar insolation and ambient temperature change. This paper presents a study of a standalone Photovoltaic energy utilization system feeding a DC and AC hybrid electric load and is fully controlled by a novel and simple on-line fuzzy logic based dynamic search, detection and tracking controller that ensures maximum power point operation under excursions in Solar Insolation, Ambient temperature and electric load variations. The maximum power point MPP-Search and Detection algorithm is fully dynamic in nature and operates without any required direct measurement or forecasted PV array information about the irradiation and temperature. An added Search sensitivity measure is defined and also used in the MPP search algorithm to sense and dynamic response for

Implementation of a Loosely-Coupled Lockstep Approach in the Xilinx Zynq-7000 All Programmable SoC for High Consequence Applications

Science.gov (United States)

2017-03-01

Programmable SoC™ is made possible through the use of ARM® Cortex ™-A9 MPCore™ Asymmetric Multiprocessing; processor configurations utilizing the...core ARM Cortex -A9 MPCore based Processing System (PS) and Programmable Logic (PL) portions. These features allow for two processors to run...SoC™ precludes a tightly-coupled lockstep approach between the two processors . Therefore, a loosely-coupled lockstep approach implemented by a

Fuzzy Logic and Arithmetical Hierarchy III

Czech Academy of Sciences Publication Activity Database

Hájek, Petr

2001-01-01

Roč. 68, č. 1 (2001), s. 129-142 ISSN 0039-3215 R&D Projects: GA AV ČR IAA1030004 Institutional research plan: AV0Z1030915 Keywords : fuzzy logic * basic fuzzy logic * Lukasiewicz logic * Godel logic * product logic * arithmetical hierarchy Subject RIV: BA - General Mathematics

Modern logic and quantum mechanics

International Nuclear Information System (INIS)

Garden, R.W.

1984-01-01

The book applies the methods of modern logic and probabilities to ''interpreting'' quantum mechanics. The subject is described and discussed under the chapter headings: classical and quantum mechanics, modern logic, the propositional logic of mechanics, states and measurement in mechanics, the traditional analysis of probabilities, the probabilities of mechanics and the model logic of predictions. (U.K.)

Semantic theory for logic programming

Energy Technology Data Exchange (ETDEWEB)

Brown, F M

1981-01-01

The author axiomatizes a number of meta theoretic concepts which have been used in logic programming, including: meaning, logical truth, nonentailment, assertion and erasure, thus showing that these concepts are logical in nature and need not be defined as they have previously been defined in terms of the operations of any particular interpreter for logic programs. 10 references.

Logic and Learning

DEFF Research Database (Denmark)

Hendricks, Vincent Fella; Gierasimczuk, Nina; de Jong, Dick

2014-01-01

Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study of inform......Learning and learnability have been long standing topics of interests within the linguistic, computational, and epistemological accounts of inductive in- ference. Johan van Benthem’s vision of the “dynamic turn” has not only brought renewed life to research agendas in logic as the study...... of information processing, but likewise helped bring logic and learning in close proximity. This proximity relation is examined with respect to learning and belief revision, updating and efficiency, and with respect to how learnability fits in the greater scheme of dynamic epistemic logic and scientific method....

Magnonic logic circuits

International Nuclear Information System (INIS)

Khitun, Alexander; Bao Mingqiang; Wang, Kang L

2010-01-01

We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.

Relativistic quantum logic

International Nuclear Information System (INIS)

Mittelstaedt, P.

1983-01-01

on the basis of the well-known quantum logic and quantum probability a formal language of relativistic quantum physics is developed. This language incorporates quantum logical as well as relativistic restrictions. It is shown that relativity imposes serious restrictions on the validity regions of propositions in space-time. By an additional postulate this relativistic quantum logic can be made consistent. The results of this paper are derived exclusively within the formal quantum language; they are, however, in accordance with well-known facts of relativistic quantum physics in Hilbert space. (author)

Theory and implementation of a very high throughput true random number generator in field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Hui, Cong; Liu, Chong; Xu, Chao [Department of Modern Physics, University of Science and Technology of China, Hefei 230026 (China)

2016-04-15

The contribution of this paper is proposing a new entropy extraction mechanism based on sampling phase jitter in ring oscillators to make a high throughput true random number generator in a field programmable gate array (FPGA) practical. Starting from experimental observation and analysis of the entropy source in FPGA, a multi-phase sampling method is exploited to harvest the clock jitter with a maximum entropy and fast sampling speed. This parametrized design is implemented in a Xilinx Artix-7 FPGA, where the carry chains in the FPGA are explored to realize the precise phase shifting. The generator circuit is simple and resource-saving, so that multiple generation channels can run in parallel to scale the output throughput for specific applications. The prototype integrates 64 circuit units in the FPGA to provide a total output throughput of 7.68 Gbps, which meets the requirement of current high-speed quantum key distribution systems. The randomness evaluation, as well as its robustness to ambient temperature, confirms that the new method in a purely digital fashion can provide high-speed high-quality random bit sequences for a variety of embedded applications.

Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation

Science.gov (United States)

Kyrkou, Christos; Theocharides, Theocharis

2016-07-01

Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024×768 pixels images per second with a significantly reduced number of false positives.

Implementing conventional logic unconventionally: photochromic molecular populations as registers and logic gates.

Science.gov (United States)

Chaplin, J C; Russell, N A; Krasnogor, N

2012-07-01

In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Microlens array processor with programmable weight mask and direct optical input

Science.gov (United States)

Schmid, Volker R.; Lueder, Ernst H.; Bader, Gerhard; Maier, Gert; Siegordner, Jochen

1999-03-01

We present an optical feature extraction system with a microlens array processor. The system is suitable for online implementation of a variety of transforms such as the Walsh transform and DCT. Operating with incoherent light, our processor accepts direct optical input. Employing a sandwich- like architecture, we obtain a very compact design of the optical system. The key elements of the microlens array processor are a square array of 15 X 15 spherical microlenses on acrylic substrate and a spatial light modulator as transmissive mask. The light distribution behind the mask is imaged onto the pixels of a customized a-Si image sensor with adjustable gain. We obtain one output sample for each microlens image and its corresponding weight mask area as summation of the transmitted intensity within one sensor pixel. The resulting architecture is very compact and robust like a conventional camera lens while incorporating a high degree of parallelism. We successfully demonstrate a Walsh transform into the spatial frequency domain as well as the implementation of a discrete cosine transform with digitized gray values. We provide results showing the transformation performance for both synthetic image patterns and images of natural texture samples. The extracted frequency features are suitable for neural classification of the input image. Other transforms and correlations can be implemented in real-time allowing adaptive optical signal processing.

A Logic for Choreographies

Directory of Open Access Journals (Sweden)

Marco Carbone

2011-10-01

Full Text Available We explore logical reasoning for the global calculus, a coordination model based on the notion of choreography, with the aim to provide a methodology for specification and verification of structured communications. Starting with an extension of Hennessy-Milner logic, we present the global logic (GL, a modal logic describing possible interactions among participants in a choreography. We illustrate its use by giving examples of properties on service specifications. Finally, we show that, despite GL is undecidable, there is a significant decidable fragment which we provide with a sound and complete proof system for checking validity of formulae.

Relational Parametricity and Separation Logic

DEFF Research Database (Denmark)

Birkedal, Lars; Yang, Hongseok

2008-01-01

Separation logic is a recent extension of Hoare logic for reasoning about programs with references to shared mutable data structures. In this paper, we provide a new interpretation of the logic for a programming language with higher types. Our interpretation is based on Reynolds's relational...... parametricity, and it provides a formal connection between separation logic and data abstraction. Udgivelsesdato: 2008...

Reliability analysis of the solar array based on Fault Tree Analysis

International Nuclear Information System (INIS)

Wu Jianing; Yan Shaoze

2011-01-01

The solar array is an important device used in the spacecraft, which influences the quality of in-orbit operation of the spacecraft and even the launches. This paper analyzes the reliability of the mechanical system and certifies the most vital subsystem of the solar array. The fault tree analysis (FTA) model is established according to the operating process of the mechanical system based on DFH-3 satellite; the logical expression of the top event is obtained by Boolean algebra and the reliability of the solar array is calculated. The conclusion shows that the hinges are the most vital links between the solar arrays. By analyzing the structure importance(SI) of the hinge's FTA model, some fatal causes, including faults of the seal, insufficient torque of the locking spring, temperature in space, and friction force, can be identified. Damage is the initial stage of the fault, so limiting damage is significant to prevent faults. Furthermore, recommendations for improving reliability associated with damage limitation are discussed, which can be used for the redesigning of the solar array and the reliability growth planning.

Reliability analysis of the solar array based on Fault Tree Analysis

Energy Technology Data Exchange (ETDEWEB)

Wu Jianing; Yan Shaoze, E-mail: yansz@mail.tsinghua.edu.cn [State Key Laboratory of Tribology, Department of Precision Instruments and Mechanology, Tsinghua University,Beijing 100084 (China)

2011-07-19

The solar array is an important device used in the spacecraft, which influences the quality of in-orbit operation of the spacecraft and even the launches. This paper analyzes the reliability of the mechanical system and certifies the most vital subsystem of the solar array. The fault tree analysis (FTA) model is established according to the operating process of the mechanical system based on DFH-3 satellite; the logical expression of the top event is obtained by Boolean algebra and the reliability of the solar array is calculated. The conclusion shows that the hinges are the most vital links between the solar arrays. By analyzing the structure importance(SI) of the hinge's FTA model, some fatal causes, including faults of the seal, insufficient torque of the locking spring, temperature in space, and friction force, can be identified. Damage is the initial stage of the fault, so limiting damage is significant to prevent faults. Furthermore, recommendations for improving reliability associated with damage limitation are discussed, which can be used for the redesigning of the solar array and the reliability growth planning.

Heterogeneous logics of competition

DEFF Research Database (Denmark)

Mossin, Christiane

2015-01-01

of competition are only realized as particular forms of social organization by virtue of interplaying with other kinds of logics, like legal logics. (2) Competition logics enjoy a peculiar status in-between constructedness and givenness; although competition depends on laws and mechanisms of socialization, we...... still experience competition as an expression of spontaneous human activities. On the basis of these perspectives, a study of fundamental rights of EU law, springing from the principle of ‘free movement of people’, is conducted. The first part of the empirical analysis seeks to detect the presence...... of a presumed logic of competition within EU law, whereas the second part focuses on particular legal logics. In this respect, the so-called ‘real link criterion’ (determining the access to transnational social rights for certain groups of unemployed people) is given special attention. What is particularly...

Basic logic and quantum entanglement

International Nuclear Information System (INIS)

Zizzi, P A

2007-01-01

As it is well known, quantum entanglement is one of the most important features of quantum computing, as it leads to massive quantum parallelism, hence to exponential computational speed-up. In a sense, quantum entanglement is considered as an implicit property of quantum computation itself. But... can it be made explicit? In other words, is it possible to find the connective 'entanglement' in a logical sequent calculus for the machine language? And also, is it possible to 'teach' the quantum computer to 'mimic' the EPR 'paradox'? The answer is in the affirmative, if the logical sequent calculus is that of the weakest possible logic, namely Basic logic. - A weak logic has few structural rules. But in logic, a weak structure leaves more room for connectives (for example the connective 'entanglement'). Furthermore, the absence in Basic logic of the two structural rules of contraction and weakening corresponds to the validity of the no-cloning and no-erase theorems, respectively, in quantum computing

Logic regression and its extensions.

Science.gov (United States)

Schwender, Holger; Ruczinski, Ingo

2010-01-01

Logic regression is an adaptive classification and regression procedure, initially developed to reveal interacting single nucleotide polymorphisms (SNPs) in genetic association studies. In general, this approach can be used in any setting with binary predictors, when the interaction of these covariates is of primary interest. Logic regression searches for Boolean (logic) combinations of binary variables that best explain the variability in the outcome variable, and thus, reveals variables and interactions that are associated with the response and/or have predictive capabilities. The logic expressions are embedded in a generalized linear regression framework, and thus, logic regression can handle a variety of outcome types, such as binary responses in case-control studies, numeric responses, and time-to-event data. In this chapter, we provide an introduction to the logic regression methodology, list some applications in public health and medicine, and summarize some of the direct extensions and modifications of logic regression that have been proposed in the literature. Copyright © 2010 Elsevier Inc. All rights reserved.

Using Abductive Research Logic: "The Logic of Discovery", to Construct a Rigorous Explanation of Amorphous Evaluation Findings

Science.gov (United States)

Levin-Rozalis, Miri

2010-01-01

Background: Two kinds of research logic prevail in scientific research: deductive research logic and inductive research logic. However, both fail in the field of evaluation, especially evaluation conducted in unfamiliar environments. Purpose: In this article I wish to suggest the application of a research logic--"abduction"--"the logic of…

An integrated software testing framework for FGA-based controllers in nuclear power plants

International Nuclear Information System (INIS)

Kim, Jae Yeob; Kim, Eun Sub; Yoo, Jun Beom; Lee, Young Jun; Choi, Jong Gyun

2016-01-01

Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs

Fault-tolerance techniques for SRAM-based FPGAs

CERN Document Server

Kastensmidt, Fernanda Lima; Reis, Ricardo

2006-01-01

Fault-tolerance in integrated circuits is no longer the exclusive concern of space designers or highly-reliable applications engineers. Today, designers of many next-generation products must cope with reduced margin noises. The continuous evolution of fabrication technology of semiconductor components – shrinking transistor geometry, power supply, speed, and logic density – has significantly reduced the reliability of very deep submicron integrated circuits, in face of various internal and external sources of noise. Field Programmable Gate Arrays (FPGAs), customizable by SRAM cells, are the latest advance in the integrated circuit evolution: millions of memory cells to implement the logic, embedded memories, routing, and embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with current requirements.

Connections among quantum logics

International Nuclear Information System (INIS)

Lock, P.F.; Hardegree, G.M.

1985-01-01

This paper gives a brief introduction to the major areas of work in quantum event logics: manuals (Foulis and Randall) and semi-Boolean algebras (Abbott). The two theories are compared, and the connection between quantum event logics and quantum propositional logics is made explicit. In addition, the work on manuals provides us with many examples of results stated in Part I. (author)

Comparison of fuzzy logic and neural network in maximum power point tracker for PV systems

Energy Technology Data Exchange (ETDEWEB)

Ben Salah, Chokri; Ouali, Mohamed [Research Unit on Intelligent Control, Optimization, Design and Optimization of Complex Systems (ICOS), Department of Electrical Engineering, National School of Engineers of Sfax, BP. W, 3038, Sfax (Tunisia)

2011-01-15

This paper proposes two methods of maximum power point tracking using a fuzzy logic and a neural network controllers for photovoltaic systems. The two maximum power point tracking controllers receive solar radiation and photovoltaic cell temperature as inputs, and estimated the optimum duty cycle corresponding to maximum power as output. The approach is validated on a 100 Wp PVP (two parallels SM50-H panel) connected to a 24 V dc load. The new method gives a good maximum power operation of any photovoltaic array under different conditions such as changing solar radiation and PV cell temperature. From the simulation and experimental results, the fuzzy logic controller can deliver more power than the neural network controller and can give more power than other different methods in literature. (author)

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications

International Nuclear Information System (INIS)

Linn, E; Ferch, S; Waser, R; Menzel, S

2013-01-01

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications. (paper)

Safety logic systems of PFBR

International Nuclear Information System (INIS)

Sambasivan, S. Ilango

2004-01-01

Full text : PFBR is provided with two independent, fast acting and diverse shutdown systems to detect any abnormalities and to initiate safety action. Each system consists of sensors, signal processing systems, logics, drive mechanisms and absorber rods. The absorber rods of the first system are Control and Safety Rods (CSR) and that of the second are called as Diverse Safety Rods (DSR). There are nine CSR and three DSR. While CSR are used for startup, control of reactor power, controlled shutdown and SCRAM, the DSR are used only for SCRAM. The respective drive mechanisms are called as CSRDM and DSRDM. Each of these two systems is capable of executing the shutdown satisfactorily with single failure criteria. Two independent safety logic systems based on diverse principles have been designed for the two shut down systems. The analog outputs of the sensors of Core Monitoring Systems comprising of reactor flux monitoring, core temperature monitoring, failed fuel detection and core flow monitoring systems are processed and converted into binary signals depending on their instantaneous values. Safety logic systems receive the binary signals from these core-monitoring systems and process them logically to protect the reactor against postulated initiating events. Neutronic and power to flow (P/Q) signals form the inputs to safety logic system-I and temperature signals are inputs to the safety logic system II. Failed fuel detection signals are processed by both the shut down systems. The two logic systems to actuate the safety rods are also based on two diverse designs and implemented with solid-state devices to meet all the requirements of safety systems. Safety logic system I that caters to neutronic and P/Q signals is designed around combinational logic and has an on-line test facility to detect struck at faults. The second logic system is based on dynamic logic and hence is inherently safe. This paper gives an overview of the two logic systems that have been

Logic from A to Z the Routledge encyclopedia of philosophy glossary of logical and mathematical terms

CERN Document Server

Bacon, John B; McCarty, David Charles; Bacon, John B

1999-01-01

First published in the most ambitious international philosophy project for a generation; the Routledge Encyclopedia of Philosophy. Logic from A to Z is a unique glossary of terms used in formal logic and the philosophy of mathematics. Over 500 entries include key terms found in the study of: * Logic: Argument, Turing Machine, Variable * Set and model theory: Isomorphism, Function * Computability theory: Algorithm, Turing Machine * Plus a table of logical symbols. Extensively cross-referenced to help comprehension and add detail, Logic from A to Z provides an indispensable reference source for students of all branches of logic.

A Paraconsistent Higher Order Logic

DEFF Research Database (Denmark)

Villadsen, Jørgen

2004-01-01

of paraconsistent logics in knowledge-based systems, logical semantics of natural language, etc. Higher order logics have the advantages of being expressive and with several automated theorem provers available. Also the type system can be helpful. We present a concise description of a paraconsistent higher order...... of the logic is examined by a case study in the domain of medicine. Thus we try to build a bridge between the HOL and MVL communities. A sequent calculus is proposed based on recent work by Muskens. Many non-classical logics are, at the propositional level, funny toys which work quite good, but when one wants...

Breaking the fault tree circular logic

International Nuclear Information System (INIS)

Lankin, M.

2000-01-01

Event tree - fault tree approach to model failures of nuclear plants as well as of other complex facilities is noticeably dominant now. This approach implies modeling an object in form of unidirectional logical graph - tree, i.e. graph without circular logic. However, genuine nuclear plants intrinsically demonstrate quite a few logical loops (circular logic), especially where electrical systems are involved. This paper shows the incorrectness of existing practice of circular logic breaking by elimination of part of logical dependencies and puts forward a formal algorithm, which enables the analyst to correctly model the failure of complex object, which involves logical dependencies between system and components, in form of fault tree. (author)

Indexical Hybrid Tense Logic

DEFF Research Database (Denmark)

Blackburn, Patrick Rowan; Jørgensen, Klaus Frovin

2012-01-01

In this paper we explore the logic of now, yesterday, today and tomorrow by combining the semantic approach to indexicality pioneered by Hans Kamp [9] and refined by David Kaplan [10] with hybrid tense logic. We first introduce a special now nominal (our @now corresponds to Kamp’s original now...... operator N) and prove completeness results for both logical and contextual validity. We then add propositional constants to handle yesterday, today and tomorrow; our system correctly treats sentences like “Niels will die yesterday” as contextually unsatisfiable. Building on our completeness results for now......, we prove completeness for the richer language, again for both logical and contextual validity....

Reversible logic gates on Physarum Polycephalum

International Nuclear Information System (INIS)

Schumann, Andrew

2015-01-01

In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

Logical entropy of quantum dynamical systems

Directory of Open Access Journals (Sweden)

Ebrahimzadeh Abolfazl

2016-01-01

Full Text Available This paper introduces the concepts of logical entropy and conditional logical entropy of hnite partitions on a quantum logic. Some of their ergodic properties are presented. Also logical entropy of a quantum dynamical system is dehned and ergodic properties of dynamical systems on a quantum logic are investigated. Finally, the version of Kolmogorov-Sinai theorem is proved.

A beginner's guide to mathematical logic

CERN Document Server

Smullyan, Raymond M

2014-01-01

Combining stories of great philosophers, quotations, and riddles with the fundamentals of mathematical logic, this new textbook for first courses in mathematical logic was written by the subject's creative master. Raymond Smullyan offers clear, incremental presentations of difficult logic concepts with creative explanations and unique problems related to proofs, propositional logic and first-order logic, undecidability, recursion theory, and other topics.

From Logical to Distributional Models

Directory of Open Access Journals (Sweden)

Anne Preller

2014-12-01

Full Text Available The paper relates two variants of semantic models for natural language, logical functional models and compositional distributional vector space models, by transferring the logic and reasoning from the logical to the distributional models. The geometrical operations of quantum logic are reformulated as algebraic operations on vectors. A map from functional models to vector space models makes it possible to compare the meaning of sentences word by word.

Application of fuzzy logic in multicomponent analysis by optodes.

Science.gov (United States)

Wollenweber, M; Polster, J; Becker, T; Schmidt, H L

1997-01-01

Fuzzy logic can be a useful tool for the determination of substrate concentrations applying optode arrays in combination with flow injection analysis, UV-VIS spectroscopy and kinetics. The transient diffuse reflectance spectra in the visible wavelength region from four optodes were evaluated to carry out the simultaneous determination of artificial mixtures of ampicillin and penicillin. The discrimination of the samples was achieved by changing the composition of the receptor gel and working pH. Different algorithms of pre-processing were applied on the data to reduce the spectral information to a few analytic-specific variables. These variables were used to develop the fuzzy model. After calibration the model was validated by an independent test data set.

Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates.

Science.gov (United States)

Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar

2012-12-26

The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.

Imaging of the dynamic magnetic structure in a parallel array of shunted Josephson junctions

DEFF Research Database (Denmark)

Doderer, T.; Kaplunenko, V. K.; Mygind, Jesper

1994-01-01

A one-dimensional (1D) parallel array of shunted Josephson junctions is one of the basic elements in the family of rapid single-flux quantum logic circuits. It was found recently that current steps always show up in the current-voltage curve of the generator junction when an additional bias current...

Functions and generality of logic reflections on Dedekind's and Frege's logicisms

CERN Document Server

Benis-Sinaceur, Hourya; Sandu, Gabriel

2015-01-01

This book examines three connected aspects of Frege's logicism: the differences between Dedekind's and Frege's interpretation of the term 'logic' and related terms and reflects on Frege's notion of function, comparing its understanding and the role it played in Frege's and Lagrange's foundational programs. It concludes with an examination of the notion of arbitrary function, taking into account Frege's, Ramsey's and Russell's view on the subject. Composed of three chapters, this book sheds light on important aspects of Dedekind's and Frege's logicisms. The first chapter explains how, although he shares Frege's aim at substituting logical standards of rigor to intuitive imports from spatio-temporal experience into the deductive presentation of arithmetic, Dedekind had a different goal and used or invented different tools. The chapter highlights basic dissimilarities between Dedekind's and Frege's actual ways of doing and thinking. The second chapter reflects on Frege's notion of a function, in comparison with ...

An Algebraic View of Super-Belnap Logics

Czech Academy of Sciences Publication Activity Database

Albuquerque, H.; Přenosil, Adam; Rivieccio, U.

2017-01-01

Roč. 105, č. 6 (2017), s. 1051-1086 ISSN 0039-3215 R&D Projects: GA ČR GBP202/12/G061 Grant - others:EU(XE) PIRSES- GA-2012-31898 Institutional support: RVO:67985807 Keywords : Super-Belnap logics * Four-valued logic * Paraconsistent logic * Belnap–Dunn logic * FDE * Logic of Paradox * Kleene logic * Exactly True logic * De Morgan algebras * Abstract Algebraic Logic * Leibniz filters * Strong versions of logics Subject RIV: BA - General Mathematics OBOR OECD: Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8) Impact factor: 0.589, year: 2016

Logic Programming: PROLOG.

Science.gov (United States)

Lopez, Antonio M., Jr.

1989-01-01

Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)

Single-flux-quantum logic circuits exploiting collision-based fusion gates

International Nuclear Information System (INIS)

Asai, T.; Yamada, K.; Amemiya, Y.

2008-01-01

We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock

Basic logic and quantum entanglement

Energy Technology Data Exchange (ETDEWEB)

Zizzi, P A [Dipartimento di Matematica Pura ed Applicata, Via Trieste 63, 35121 Padova (Italy)

2007-05-15

As it is well known, quantum entanglement is one of the most important features of quantum computing, as it leads to massive quantum parallelism, hence to exponential computational speed-up. In a sense, quantum entanglement is considered as an implicit property of quantum computation itself. But... can it be made explicit? In other words, is it possible to find the connective 'entanglement' in a logical sequent calculus for the machine language? And also, is it possible to 'teach' the quantum computer to 'mimic' the EPR 'paradox'? The answer is in the affirmative, if the logical sequent calculus is that of the weakest possible logic, namely Basic logic. - A weak logic has few structural rules. But in logic, a weak structure leaves more room for connectives (for example the connective 'entanglement'). Furthermore, the absence in Basic logic of the two structural rules of contraction and weakening corresponds to the validity of the no-cloning and no-erase theorems, respectively, in quantum computing.

A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications.

Science.gov (United States)

Kim, Kuk-Hwan; Gaba, Siddharth; Wheeler, Dana; Cruz-Albrecht, Jose M; Hussain, Tahir; Srinivasa, Narayan; Lu, Wei

2012-01-11

Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a high-density, fully operational hybrid crossbar/CMOS system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/CMOS system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. © 2011 American Chemical Society

Implicational (semilinear) logics III: completeness properties

Czech Academy of Sciences Publication Activity Database

Cintula, Petr; Noguera, Carles

2018-01-01

Roč. 57, 3-4 (2018), s. 391-420 ISSN 0933-5846 R&D Projects: GA ČR GA13-14654S EU Projects: European Commission(XE) 689176 - SYSMICS Institutional support: RVO:67985807 ; RVO:67985556 Keywords : abstract algebraic logic * protoalgebraic logics * implicational logics * disjunctional logics * semilinear logics * non-classical logics * completeness theorems * rational completeness Subject RIV: BA - General Mathematics; BA - General Mathematics (UTIA-B) OBOR OECD: Computer science s, information science , bioinformathics (hardware development to be 2.2, social aspect to be 5.8) Impact factor: 0.394, year: 2016

Implicational (semilinear) logics III: completeness properties

Czech Academy of Sciences Publication Activity Database

Cintula, Petr; Noguera, Carles

2018-01-01

Roč. 57, 3-4 (2018), s. 391-420 ISSN 0933-5846 R&D Projects: GA ČR GA13-14654S EU Projects: European Commission(XE) 689176 - SYSMICS Institutional support: RVO:67985807 ; RVO:67985556 Keywords : abstract algebraic logic * protoalgebraic logics * implicational logics * disjunctional logics * semilinear logics * non-classical logics * completeness theorems * rational completeness Subject RIV: BA - General Mathematics; BA - General Mathematics (UTIA-B) OBOR OECD: Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8) Impact factor: 0.394, year: 2016

Free-running ADC- and FPGA-based signal processing method for brain PET using GAPD arrays

Energy Technology Data Exchange (ETDEWEB)

Hu, Wei [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Choi, Yong, E-mail: ychoi.image@gmail.com [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Hong, Key Jo [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kang, Jihoon [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Jung, Jin Ho [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Huh, Youn Suk [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Lim, Hyun Keong; Kim, Sang Su [Department of Electronic Engineering, Sogang University, 1 Shinsu-Dong, Mapo-Gu, Seoul 121-742 (Korea, Republic of); Kim, Byung-Tae [Department of Nuclear Medicine, Samsung Medical Center, Sungkyunkwan University School of Medicine, 50 Ilwon-Dong, Gangnam-Gu, Seoul 135-710 (Korea, Republic of); Chung, Yonghyun [Department of Radiological Science, Yonsei University College of Health Science, 234 Meaji, Heungup Wonju, Kangwon-Do 220-710 (Korea, Republic of)

2012-02-01

Currently, for most photomultiplier tube (PMT)-based PET systems, constant fraction discriminators (CFD) and time to digital converters (TDC) have been employed to detect gamma ray signal arrival time, whereas anger logic circuits and peak detection analog-to-digital converters (ADCs) have been implemented to acquire position and energy information of detected events. As compared to PMT the Geiger-mode avalanche photodiodes (GAPDs) have a variety of advantages, such as compactness, low bias voltage requirement and MRI compatibility. Furthermore, the individual read-out method using a GAPD array coupled 1:1 with an array scintillator can provide better image uniformity than can be achieved using PMT and anger logic circuits. Recently, a brain PET using 72 GAPD arrays (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm) coupled 1:1 with LYSO scintillators (4 Multiplication-Sign 4 array, pixel size: 3 mm Multiplication-Sign 3 mm Multiplication-Sign 20 mm) has been developed for simultaneous PET/MRI imaging in our laboratory. Eighteen 64:1 position decoder circuits (PDCs) were used to reduce GAPD channel number and three off-the-shelf free-running ADC and field programmable gate array (FPGA) combined data acquisition (DAQ) cards were used for data acquisition and processing. In this study, a free-running ADC- and FPGA-based signal processing method was developed for the detection of gamma ray signal arrival time, energy and position information all together for each GAPD channel. For the method developed herein, three DAQ cards continuously acquired 18 channels of pre-amplified analog gamma ray signals and 108-bit digital addresses from 18 PDCs. In the FPGA, the digitized gamma ray pulses and digital addresses were processed to generate data packages containing pulse arrival time, baseline value, energy value and GAPD channel ID. Finally, these data packages were saved to a 128 Mbyte on-board synchronous dynamic random access memory (SDRAM) and

Microelectromechanical reprogrammable logic device

Science.gov (United States)

Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

2016-01-01

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

Microelectromechanical reprogrammable logic device

KAUST Repository

Hafiz, Md Abdullah Al

2016-03-29

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units

Directory of Open Access Journals (Sweden)

Chi Wai Yu

2008-01-01

Full Text Available This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1 FPUs should have a square aspect ratio; (2 they should be positioned near the center of the FPGA; (3 their I/O pins should be arranged around all four sides of the FPU; (4 embedded memory should be located between the FPUs; and (5 connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.

The design of nuclear magnetic resonance programmable pulsed source based SOPC

International Nuclear Information System (INIS)

Zhang Qingshun; Zhang Yakun; Wang Wenli

2012-01-01

The design of pulse source in the equipment of pulsed Nuclear Magnetic Resonance is studied based on SOPC. The strong processing power of Nios Ⅱ embedded processor and the design flexibility of FPGA are fully used. The SOPC system is built. The overall design plan for the pulse source is described. The design of programmable multi-pulse generation logic user-defined components in the FPGA is introduced mainly. Part of the implementation program and the task logic simulation waveforms are presented. The pulse source has better application value because a clear, stable and good quality multi-pulse output waveform can be shown on the oscilloscope finally. The system software and hardware are easy to be modified and upgraded, meeting different application of pulsed NMR pulse sequence in variety of requirements. (authors)

Unlimited multistability and Boolean logic in microbial signalling

DEFF Research Database (Denmark)

Kothamachu, Varun B; Feliu, Elisenda; Cardelli, Luca

2015-01-01

The ability to map environmental signals onto distinct internal physiological states or programmes is critical for single-celled microbes. A crucial systems dynamics feature underpinning such ability is multistability. While unlimited multistability is known to arise from multi-site phosphorylation...... seen in the signalling networks of eukaryotic cells, a similarly universal mechanism has not been identified in microbial signalling systems. These systems are generally known as two-component systems comprising histidine kinase (HK) receptors and response regulator proteins engaging in phosphotransfer...... further prove that sharing of downstream components allows a system with n multi-domain hybrid HKs to attain 3n steady states. We find that such systems, when sensing distinct signals, can readily implement Boolean logic functions on these signals. Using two experimentally studied examples of two...

Coherent quantum logic

International Nuclear Information System (INIS)

Finkelstein, D.

1987-01-01

The von Neumann quantum logic lacks two basic symmetries of classical logic, that between sets and classes, and that between lower and higher order predicates. Similarly, the structural parallel between the set algebra and linear algebra of Grassmann and Peano was left incomplete by them in two respects. In this work a linear algebra is constructed that completes this correspondence and is interpreted as a new quantum logic that restores these invariances, and as a quantum set theory. It applies to experiments with coherent quantum phase relations between the quantum and the apparatus. The quantum set theory is applied to model a Lorentz-invariant quantum time-space complex

A Compute Environment of ABC95 Array Computer Based on Multi-FPGA Chip