ARTiS, an Asymmetric Real-Time Scheduler for Linux on Multi-Processor Architectures

OpenAIRE

Piel , Éric; Marquet , Philippe; Soula , Julien; Osuna , Christophe; Dekeyser , Jean-Luc

2005-01-01

The ARTiS system is a real-time extension of the GNU/Linux scheduler dedicated to SMP (Symmetric Multi-Processors) systems. It allows to mix High Performance Computing and real-time. ARTiS exploits the SMP architecture to guarantee the preemption of a processor when the system has to schedule a real-time task. The implementation is available as a modification of the Linux kernel, especially focusing (but not restricted to) IA-64 architecture. The basic idea of ARTiS is to assign a selected se...

A survey of Tumult, a real-time multi-processor system

International Nuclear Information System (INIS)

Jansen, P.G.

1986-01-01

Tumult (Twente University MULTi processor system) is the name of an ongoing project aiming at the design and implementation of a modular extendible multiprocessor system. All memory is distributed and processors communicate in parallel via a fast and reliable local switching network instead of a shared bus. A distributed real-time operating system is being designed and implemented, consisting of a multi-tasking subsystem per processor. Processes can communicate via a message passing mechanism. Communication links and processes are dynamically created and disposed by the application. In this article a brief description of the system is given; communication aspects are emphasized. (Auth.)

Consumer Electronics Processors for Critical Real-Time Systems: a (Failed) Practical Experience

OpenAIRE

Fernandez , Gabriel; Cazorla , Francisco; Abella , Jaume

2018-01-01

International audience; The convergence between consumer electronics and critical real-time markets has increased the need for hardware platforms able to deliver high performance as well as high (sustainable) performance guarantees. Using the ARM big.LITTLE architecture as example of those platforms, in this paper we report our experience with one of its implementations (the Qualcomm SnapDragon 810 processor) to derive performance bounds with measurement-based techniques. Our theoretical and ...

Feasibility analysis of real-time physical modeling using WaveCore processor technology on FPGA

NARCIS (Netherlands)

Verstraelen, Martinus Johannes Wilhelmina; Pfeifle, Florian; Bader, Rolf

2015-01-01

WaveCore is a scalable many-core processor technology. This technology is specifically developed and optimized for real-time acoustical modeling applications. The programmable WaveCore soft-core processor is silicon-technology independent and hence can be targeted to ASIC or FPGA technologies. The

A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System.

Science.gov (United States)

Zhang, Zhen; Ma, Cheng; Zhu, Rong

2017-08-23

Artificial Neural Networks (ANNs), including Deep Neural Networks (DNNs), have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA) architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP). The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO) real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

A FPGA-Based, Granularity-Variable Neuromorphic Processor and Its Application in a MIMO Real-Time Control System

Directory of Open Access Journals (Sweden)

Zhen Zhang

2017-08-01

Full Text Available Artificial Neural Networks (ANNs, including Deep Neural Networks (DNNs, have become the state-of-the-art methods in machine learning and achieved amazing success in speech recognition, visual object recognition, and many other domains. There are several hardware platforms for developing accelerated implementation of ANN models. Since Field Programmable Gate Array (FPGA architectures are flexible and can provide high performance per watt of power consumption, they have drawn a number of applications from scientists. In this paper, we propose a FPGA-based, granularity-variable neuromorphic processor (FBGVNP. The traits of FBGVNP can be summarized as granularity variability, scalability, integrated computing, and addressing ability: first, the number of neurons is variable rather than constant in one core; second, the multi-core network scale can be extended in various forms; third, the neuron addressing and computing processes are executed simultaneously. These make the processor more flexible and better suited for different applications. Moreover, a neural network-based controller is mapped to FBGVNP and applied in a multi-input, multi-output, (MIMO real-time, temperature-sensing and control system. Experiments validate the effectiveness of the neuromorphic processor. The FBGVNP provides a new scheme for building ANNs, which is flexible, highly energy-efficient, and can be applied in many areas.

A distributed agent architecture for real-time knowledge-based systems: Real-time expert systems project, phase 1

Science.gov (United States)

Lee, S. Daniel

1990-01-01

We propose a distributed agent architecture (DAA) that can support a variety of paradigms based on both traditional real-time computing and artificial intelligence. DAA consists of distributed agents that are classified into two categories: reactive and cognitive. Reactive agents can be implemented directly in Ada to meet hard real-time requirements and be deployed on on-board embedded processors. A traditional real-time computing methodology under consideration is the rate monotonic theory that can guarantee schedulability based on analytical methods. AI techniques under consideration for reactive agents are approximate or anytime reasoning that can be implemented using Bayesian belief networks as in Guardian. Cognitive agents are traditional expert systems that can be implemented in ART-Ada to meet soft real-time requirements. During the initial design of cognitive agents, it is critical to consider the migration path that would allow initial deployment on ground-based workstations with eventual deployment on on-board processors. ART-Ada technology enables this migration while Lisp-based technologies make it difficult if not impossible. In addition to reactive and cognitive agents, a meta-level agent would be needed to coordinate multiple agents and to provide meta-level control.

State-based Communication on Time-predictable Multicore Processors

DEFF Research Database (Denmark)

Sørensen, Rasmus Bo; Schoeberl, Martin; Sparsø, Jens

2016-01-01

Some real-time systems use a form of task-to-task communication called state-based or sample-based communication that does not impose any flow control among the communicating tasks. The concept is similar to a shared variable, where a reader may read the same value multiple times or may not read...... a given value at all. This paper explores time-predictable implementations of state-based communication in network-on-chip based multicore platforms through five algorithms. With the presented analysis of the implemented algorithms, the communicating tasks of one core can be scheduled independently...... of tasks on other cores. Assuming a specific time-predictable multicore processor, we evaluate how the read and write primitives of the five algorithms contribute to the worst-case execution time of the communicating tasks. Each of the five algorithms has specific capabilities that make them suitable...

Preemptive and Non-Preemptive Real-Time UniProcessor Scheduling

OpenAIRE

George , Laurent; Rivierre , Nicolas; Spuri , Marco

1996-01-01

Projet REFLECS; Scheduling theory, as it applies to hard-real-time environment, has been widely studied in the last twenty years and it might be unclear to make it out within the plethora of results available. Our goal is first to collect in a single paper the results known for uniproces sor, non-idling, preemptive/non-preemptive, fixed/dynamic priority driven contexts, consid ering general task sets as a central figure for the description of possible processor loads. Second to establish new ...

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

Science.gov (United States)

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

Real-time portable system for fabric defect detection using an ARM processor

Science.gov (United States)

Fernandez-Gallego, J. A.; Yañez-Puentes, J. P.; Ortiz-Jaramillo, B.; Alvarez, J.; Orjuela-Vargas, S. A.; Philips, W.

2012-06-01

Modern textile industry seeks to produce textiles as little defective as possible since the presence of defects can decrease the final price of products from 45% to 65%. Automated visual inspection (AVI) systems, based on image analysis, have become an important alternative for replacing traditional inspections methods that involve human tasks. An AVI system gives the advantage of repeatability when implemented within defined constrains, offering more objective and reliable results for particular tasks than human inspection. Costs of automated inspection systems development can be reduced using modular solutions with embedded systems, in which an important advantage is the low energy consumption. Among the possibilities for developing embedded systems, the ARM processor has been explored for acquisition, monitoring and simple signal processing tasks. In a recent approach we have explored the use of the ARM processor for defects detection by implementing the wavelet transform. However, the computation speed of the preprocessing was not yet sufficient for real time applications. In this approach we significantly improve the preprocessing speed of the algorithm, by optimizing matrix operations, such that it is adequate for a real time application. The system was tested for defect detection using different defect types. The paper is focused in giving a detailed description of the basis of the algorithm implementation, such that other algorithms may use of the ARM operations for fast implementations.

Airborne ocean water lidar (OWL) real time processor (RTP)

Science.gov (United States)

Hryszko, M.

1995-03-01

The Hyperflo Real Time Processor (RTP) was developed by Pacific-Sierra Research Corporation as a part of the Naval Air Warfare Center's Ocean Water Lidar (OWL) system. The RTP was used for real time support of open ocean field tests at Barbers Point, Hawaii, in March 1993 (EMERALD I field test), and Jacksonville, Florida, in July 1994 (EMERALD I field test). This report describes the system configuration, and accomplishments associated with the preparation and execution of these exercises. This document is intended to supplement the overall test reports and provide insight into the development and use of the PTP. A secondary objective is to provide basic information on the capabilities, versatility and expandability of the Hyperflo RTP for possible future projects. It is assumed herein that the reader has knowledge of the OWL system, field test operations, general lidar processing methods, and basic computer architecture.

Multi-processor system for real-time flow estimation in medical ultrasound imaging

DEFF Research Database (Denmark)

Stetson, Paul F.; Jensen, Jesper Lomborg; Antonius, Peter

1997-01-01

the processed data. The generous bandwidth of the links makes it easy to balance the computational load among the processors.In order to manage the shared system memory and to make use of the parallel processing capabilities of the system, a real-time multitasking kernel has been developed. The kernel uses...

Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors

Directory of Open Access Journals (Sweden)

Abhishek Jain

2016-01-01

Full Text Available In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW implementation, reference for firmware (FW implementation, and bit-true certification. The universal verification methodology- (UVM- based functional verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional verification environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI approach. This modeling and functional verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and verification of image signal processor (ISP designs. The proposed framework shows better results and significant improvement is observed in product verification time, verification cost, and quality of the designs.

A new approach in simulating RF linacs using a general, linear real-time signal processor

International Nuclear Information System (INIS)

Young, A.; Jachim, S.P.

1991-01-01

Strict requirements on the tolerances of the amplitude and phase of the radio frequency (RF) cavity field are necessary to advance the field of accelerator technology. Due to these stringent requirements upon modern accelerators,a new approach of modeling and simulating is essential in developing and understanding their characteristics. This paper describes the implementation of a general, linear model of an RF cavity which is used to develop a real-time signal processor. This device fully emulates the response of an RF cavity upon receiving characteristic parameters (Q 0 , ω 0 , Δω, R S , Z 0 ). Simulating an RF cavity with a real-time signal processor is beneficial to an accelerator designer because the device allows one to answer fundamental questions on the response of the cavity to a particular stimulus without operating the accelerator. In particular, the complex interactions between the RF power and the control systems, the beam and cavity fields can simply be observed in a real-time domain. The signal processor can also be used upon initialization of the accelerator as a diagnostic device and as a dummy load for determining the closed-loop error of the control system. In essence, the signal processor is capable of providing information that allows an operator to determine whether the control systems and peripheral devices are operating properly without going through the tedious procedure of running the beam through a cavity

Fuzzy logic based power-efficient real-time multi-core system

CERN Document Server

Ahmed, Jameel; Najam, Shaheryar; Najam, Zohaib

2017-01-01

This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors. .

Temporal analysis and scheduling of hard real-time radios running on a multi-processor

NARCIS (Netherlands)

Moreira, O.

2012-01-01

On a multi-radio baseband system, multiple independent transceivers must share the resources of a multi-processor, while meeting each its own hard real-time requirements. Not all possible combinations of transceivers are known at compile time, so a solution must be found that either allows for

Multi-processor system for real-time deconvolution and flow estimation in medical ultrasound

DEFF Research Database (Denmark)

Jensen, Jesper Lomborg; Jensen, Jørgen Arendt; Stetson, Paul F.

1996-01-01

of the algorithms. Many of the algorithms can only be properly evaluated in a clinical setting with real-time processing, which generally cannot be done with conventional equipment. This paper therefore presents a multi-processor system capable of performing 1.2 billion floating point operations per second on RF...... filter is used with a second time-reversed recursive estimation step. Here it is necessary to perform about 70 arithmetic operations per RF sample or about 1 billion operations per second for real-time deconvolution. Furthermore, these have to be floating point operations due to the adaptive nature...... interfaced to our previously-developed real-time sampling system that can acquire RF data at a rate of 20 MHz and simultaneously transmit the data at 20 MHz to the processing system via several parallel channels. These two systems can, thus, perform real-time processing of ultrasound data. The advantage...

Safety-critical Java on a time-predictable processor

DEFF Research Database (Denmark)

Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

2015-01-01

For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor SOC

NARCIS (Netherlands)

Nelson, A.T.; Goossens, K.G.W.; Akesson, K.B.

2015-01-01

Embedded systems often contain multiple applications, some of which have real-time requirements and whose performance must be guaranteed. To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM

Real-time autocorrelator for fluorescence correlation spectroscopy based on graphical-processor-unit architecture: method, implementation, and comparative studies

Science.gov (United States)

Laracuente, Nicholas; Grossman, Carl

2013-03-01

We developed an algorithm and software to calculate autocorrelation functions from real-time photon-counting data using the fast, parallel capabilities of graphical processor units (GPUs). Recent developments in hardware and software have allowed for general purpose computing with inexpensive GPU hardware. These devices are more suited for emulating hardware autocorrelators than traditional CPU-based software applications by emphasizing parallel throughput over sequential speed. Incoming data are binned in a standard multi-tau scheme with configurable points-per-bin size and are mapped into a GPU memory pattern to reduce time-expensive memory access. Applications include dynamic light scattering (DLS) and fluorescence correlation spectroscopy (FCS) experiments. We ran the software on a 64-core graphics pci card in a 3.2 GHz Intel i5 CPU based computer running Linux. FCS measurements were made on Alexa-546 and Texas Red dyes in a standard buffer (PBS). Software correlations were compared to hardware correlator measurements on the same signals. Supported by HHMI and Swarthmore College

Interference control by best-effort process duty-cycling in chip multi-processor systems for real-time medical image processing

NARCIS (Netherlands)

Westmijze, M.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria

2013-01-01

Systems with chip multi-processors are currently used for several applications that have real-time requirements. In chip multi-processor architectures, many hardware resources such as parts of the cache hierarchy are shared between cores and by using such resources, applications can significantly

QERx- A Faster than Real-Time Emulator for Space Processors

Science.gov (United States)

Carvalho, B.; Pidgeon, A.; Robinson, P.

2012-08-01

Developing software for space systems is challenging. Especially because, in order to be sure it can cope with the harshness of the environment and the imperative requirements and constrains imposed by the platform were it will run, it needs to be tested exhaustively. Software Validation Facilities (SVF) are known to the industry and developers, and provide the means to run the On-Board Software (OBSW) in a realistic environment, allowing the development team to debug and test the software.But the challenge is to be able to keep up with the performance of the new processors (LEON2 and LEON3), which need to be emulated within the SVF. Such processor emulators are also used in Operational Simulators, used to support mission preparation and train mission operators. These simulators mimic the satellite and its behaviour, as realistically as possible. For test/operational efficiency reasons and because they will need to interact with external systems, both these uses cases require the processor emulators to provide real-time, or faster, performance.It is known to the industry that the performance of previously available emulators is not enough to cope with the performance of the new processors available in the market. SciSys approached this problem with dynamic translation technology trying to keep costs down by avoiding a hardware solution and keeping the integration flexibility of full software emulation.SciSys presented “QERx: A High Performance Emulator for Software Validation and Simulations” [1], in a previous DASIA event. Since then that idea has evolved and QERx has been successfully validated. SciSys is now presenting QERx as a product that can be tailored to fit different emulation needs. This paper will present QERx latest developments and current status.

Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

DEFF Research Database (Denmark)

Sparsø, Jens

2012-01-01

This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

Confabulation Based Real-time Anomaly Detection for Wide-area Surveillance Using Heterogeneous High Performance Computing Architecture

Science.gov (United States)

2015-06-01

CONFABULATION BASED REAL-TIME ANOMALY DETECTION FOR WIDE-AREA SURVEILLANCE USING HETEROGENEOUS HIGH PERFORMANCE COMPUTING ARCHITECTURE SYRACUSE...DETECTION FOR WIDE-AREA SURVEILLANCE USING HETEROGENEOUS HIGH PERFORMANCE COMPUTING ARCHITECTURE 5a. CONTRACT NUMBER FA8750-12-1-0251 5b. GRANT...processors including graphic processor units (GPUs) and Intel Xeon Phi processors. Experimental results showed significant speedups, which can enable

Real-time image processing of TOF range images using a reconfigurable processor system

Science.gov (United States)

Hussmann, S.; Knoll, F.; Edeler, T.

2011-07-01

During the last years, Time-of-Flight sensors achieved a significant impact onto research fields in machine vision. In comparison to stereo vision system and laser range scanners they combine the advantages of active sensors providing accurate distance measurements and camera-based systems recording a 2D matrix at a high frame rate. Moreover low cost 3D imaging has the potential to open a wide field of additional applications and solutions in markets like consumer electronics, multimedia, digital photography, robotics and medical technologies. This paper focuses on the currently implemented 4-phase-shift algorithm in this type of sensors. The most time critical operation of the phase-shift algorithm is the arctangent function. In this paper a novel hardware implementation of the arctangent function using a reconfigurable processor system is presented and benchmarked against the state-of-the-art CORDIC arctangent algorithm. Experimental results show that the proposed algorithm is well suited for real-time processing of the range images of TOF cameras.

Improvement of the real-time processor in JT-60 data processing system

International Nuclear Information System (INIS)

Sakata, S.; Kiyono, K.; Sato, M.; Kominato, T.; Sueoka, M.; Hosoyama, H.; Kawamata, Y.

2009-01-01

Real-time processor, RTP is a basic subsystem in the JT-60 data processing system and plays an important role in JT-60 feedback control for plasma experiment. During the experiment, RTP acquires various diagnostic signals, processes them into a form of physical values, and transfers them as sensor signals to the particle supply and heating control supervisor for feedback control via reflective memory synchronization with 1 ms clock signals. After the start of RTP operation in 1997, to meet the demand for advanced plasma experiment, RTP had been improved continuously such as by addition of diagnostic signals with faster digitizers, reducing time for data transfer utilizing reflective memory instead of CAMAC. However, it is becoming increasingly difficult to maintain, manage, and improve the outdated RTP with limited system CPU capability. Currently, a prototype RTP system is being developed for the next real-time processing system, which is composed of clustered system utilizing VxWorks computer. The processes on the existing RTP system will be decentralized to the VxWorks computer to solve the issues of the existing RTP system. The prototype RTP system will start to operate in August 2008.

Processor core for real time background identification of HD video based on OpenCV Gaussian mixture model algorithm

Science.gov (United States)

Genovese, Mariangela; Napoli, Ettore

2013-05-01

The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television.

An embedded real-time red peach detection system based on an OV7670 camera, ARM Cortex-M4 processor and 3D Look-Up Tables

OpenAIRE

Teixidó Cairol, Mercè; Font Calafell, Davinia; Pallejà Cabrè, Tomàs; Tresánchez Ribes, Marcel; Nogués Aymamí, Miquel; Palacín Roca, Jordi

2012-01-01

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future...

Research of real-time performance based on VxWorks embedded system

International Nuclear Information System (INIS)

Liu Daming; Li Haiming

2011-01-01

In the research of mechanism and heating efficiency of Ion Cyclotron Range of Frequency (ICRF) heating, data acquisition system with high real-time performance needed. By the means of system logic analyzer, SPY and other relevant software on VxWorks embedded operating system for real-time testing gives real-time data of the system. Real-time level to achieve balances used time and processor idle time, real-time data acquisition, and minimize the interference of external to the system, ensure the system work in its own set of scheduling trajectory. Interrupt switching time and task context switching time meet the system requirements. (authors)

Data processing system for real-time control

International Nuclear Information System (INIS)

Oasa, K.; Mochizuki, O.; Toyokawa, R.; Yahiro, K.

1983-01-01

Real-time control, for large Tokamak JT-60, requires various data processings between diagnostic devices to control system. These processings require to high speed performance so that it aims at giving information necessary for feedback control during discharges. Then, the architecture of this system has hierachical structure of processors. These processors are connected each other by the CAMAC modules and the optical communication network, which is the 5 M bytes/second CAMAC serial highway. This system has two kinds of intelligences for this purpose. One is ACM-PU pairs in some torus hall crates which has a microcomputerized auxiliary controller and a preprocessing unit. Other is real-time processor which has a minicomputer and preprocessing unit. Most of the real-time processing, for example Abel inversion are characteristic to the diagnostic devices. Such a processing is carried out by an ACM-PU pair in the crate dedicated to the diagnostic device. Some processings, however, are also necessary which compute secondary parameters as functions of primary parameters. A typical example is Zeff, which is a function of Te, Ne and bremsstrahluny intensity. The real-time processor is equipped for such secondary processings and transfer the results. Preprocessing unit -PU- attached to ACM and real-time processor contains a signal processor, which executes in parallel such function as move, add and multiply during one micro-instruction cycle of 200 nsec. According to the progress of the experiment, more high speed processing are required, so the authors developed the PU-X module that contains multi signal processors. After a shot, inter-shot-processor which consists of general-purpose computers, gathers data into the database, then analyze them, and improve these processes to more effective

The Chimera II Real-Time Operating System for advanced sensor-based control applications

Science.gov (United States)

Stewart, David B.; Schmitz, Donald E.; Khosla, Pradeep K.

1992-01-01

Attention is given to the Chimera II Real-Time Operating System, which has been developed for advanced sensor-based control applications. The Chimera II provides a high-performance real-time kernel and a variety of IPC features. The hardware platform required to run Chimera II consists of commercially available hardware, and allows custom hardware to be easily integrated. The design allows it to be used with almost any type of VMEbus-based processors and devices. It allows radially differing hardware to be programmed using a common system, thus providing a first and necessary step towards the standardization of reconfigurable systems that results in a reduction of development time and cost.

Implementation of SoC Based Real-Time Electromagnetic Transient Simulator

Directory of Open Access Journals (Sweden)

I. Herrera-Leandro

2017-01-01

Full Text Available Real-time electromagnetic transient simulators are important tools in the design stage of new control and protection systems for power systems. Real-time simulators are used to test and stress new devices under similar conditions that the device will deal with in a real network with the purpose of finding errors and bugs in the design. The computation of an electromagnetic transient is complex and computationally demanding, due to features such as the speed of the phenomenon, the size of the network, and the presence of time variant and nonlinear elements in the network. In this work, the development of a SoC based real-time and also offline electromagnetic transient simulator is presented. In the design, the required performance is met from two sides, (a using a technique to split the power system into smaller subsystems, which allows parallelizing the algorithm, and (b with specialized and parallel hardware designed to boost the solution flow. The results of this work have shown that for the proposed case studies, based on a balanced distribution of the node of subsystems, the proposed approach has decreased the total simulation time by up to 99 times compared with the classical approach running on a single high performance 32-bit embedded processor ARM-Cortex A9.

The evolution of real-time control systems at JET

Energy Technology Data Exchange (ETDEWEB)

Goodyear, A.; Dorling, S.; Felton, R

2001-07-01

Real-time feedback control of the JET experiment is based upon a collection of diagnostics providing signals which are processed by various controllers that manipulate actuator parameters for plasma current, shape and heating. The real-time data network (RTDN) connects the diagnostic, controller and actuator systems to form a flexible feedback and protection system for plasma monitoring and control. The controllers are mainly VME systems based on the Motorola 680X0 (68K) processor with some computationally intensive systems utilising Texas Instruments TMS320C40 (C40) digital signal processors (DSP), though lately there has been a move towards PowerPC 750 based processors. The majority of 68K VME systems use VxWorks, a hard real time operating system. There is an ongoing requirement to improve the efficiency of the real-time control systems at JET. This is driven by a desire to either add more input signals, reduce the feedback cycle time or increase algorithm complexity. New technology has a major role to play in the upgrade of the real-time control systems but the novel redeployment of existing equipment can also be used to enhance performance. This paper examines the configuration of existing systems, both hardware and software, and how new technology can be gradually integrated without jeopardising the current functionality. The adoption of Asynchronous Transfer Mode (ATM) as the connection medium for the RTDN is key to the evolutional development of the control systems. The ATM network is extremely flexible to configure and benefits from low message latency and deterministic delivery time, essential properties for a real-time network. (author)

An Embedded Real-Time Red Peach Detection System Based on an OV7670 Camera, ARM Cortex-M4 Processor and 3D Look-Up Tables

Directory of Open Access Journals (Sweden)

Marcel Tresanchez

2012-10-01

Full Text Available This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6 processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

An embedded real-time red peach detection system based on an OV7670 camera, ARM cortex-M4 processor and 3D look-up tables.

Science.gov (United States)

Teixidó, Mercè; Font, Davinia; Pallejà, Tomàs; Tresanchez, Marcel; Nogués, Miquel; Palacín, Jordi

2012-10-22

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT) defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

Real-Time Adaptive Lossless Hyperspectral Image Compression using CCSDS on Parallel GPGPU and Multicore Processor Systems

Science.gov (United States)

Hopson, Ben; Benkrid, Khaled; Keymeulen, Didier; Aranki, Nazeeh; Klimesh, Matt; Kiely, Aaron

2012-01-01

The proposed CCSDS (Consultative Committee for Space Data Systems) Lossless Hyperspectral Image Compression Algorithm was designed to facilitate a fast hardware implementation. This paper analyses that algorithm with regard to available parallelism and describes fast parallel implementations in software for GPGPU and Multicore CPU architectures. We show that careful software implementation, using hardware acceleration in the form of GPGPUs or even just multicore processors, can exceed the performance of existing hardware and software implementations by up to 11x and break the real-time barrier for the first time for a typical test application.

Real-Time Plasma Control Tools for Advanced Tokamak Operation

International Nuclear Information System (INIS)

Varandas, C. A. F.; Sousa, J.; Rodrigues, A. P.; Carvalho, B. B.; Fernandes, H.; Batista, A. J.; Cruz, N.; Combo, A.; Pereira, R. C.

2006-01-01

Real-time control will play an important role in the operation and scientific exploitation of the new generation fusion devices. This paper summarizes the real-time systems and diagnostics developed by the Portuguese Fusion Euratom Association based on digital signal processors and field programmable gate arrays

CUDA-based real time surgery simulation.

Science.gov (United States)

Liu, Youquan; De, Suvranu

2008-01-01

In this paper we present a general software platform that enables real time surgery simulation on the newly available compute unified device architecture (CUDA)from NVIDIA. CUDA-enabled GPUs harness the power of 128 processors which allow data parallel computations. Compared to the previous GPGPU, it is significantly more flexible with a C language interface. We report implementation of both collision detection and consequent deformation computation algorithms. Our test results indicate that the CUDA enables a twenty times speedup for collision detection and about fifteen times speedup for deformation computation on an Intel Core 2 Quad 2.66 GHz machine with GeForce 8800 GTX.

Real-Time Audio Processing on the T-CREST Multicore Platform

DEFF Research Database (Denmark)

Ausin, Daniel Sanz; Pezzarossa, Luca; Schoeberl, Martin

2017-01-01

of the audio signal. This paper presents a real-time multicore audio processing system based on the T-CREST platform. T-CREST is a time-predictable multicore processor for real-time embedded systems. Multiple audio effect tasks have been implemented, which can be connected together in different configurations...... forming sequential and parallel effect chains, and using a network-onchip for intercommunication between processors. The evaluation of the system shows that real-time processing of multiple effect configurations is possible, and that the estimation and control of latency ensures real-time behavior.......Multicore platforms are nowadays widely used for audio processing applications, due to the improvement of computational power that they provide. However, some of these systems are not optimized for temporally constrained environments, which often leads to an undesired increase in the latency...

Developing infrared array controller with software real time operating system

Science.gov (United States)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

Science.gov (United States)

Coffey, Stephen; Connell, Joseph

2005-06-01

This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Development and upgrade of new real time processor in JT-60 data processing system

International Nuclear Information System (INIS)

Sakata, Shinya; Koiwa, Motonao; Matsuda, Toshiaki; Aoyagi, Tetsuo

2000-07-01

At the beginning of JT-60 experiments, the real time processor (RTP) in the data processing system was mainly constructed by PANAFACOM U-1500. As the computer became superannuated, however, it gradually became difficult to maintain both hardware and software. A performance of a recent UNIX workstation has been remarkably progressed. The UNIX workstation has a large flexibility for user application programs, an easiness for maintenance of the hardware and an ability of expansion to peripheral devices. Therefore, the RTP system is newly reconstructed by using the UNIX workstation. This report describes the overview, the basic design and the recent upgrade on the RTP in the data processing system. (author)

Real-time machine vision system using FPGA and soft-core processor

Science.gov (United States)

Malik, Abdul Waheed; Thörnberg, Benny; Meng, Xiaozhou; Imran, Muhammad

2012-06-01

This paper presents a machine vision system for real-time computation of distance and angle of a camera from reference points in the environment. Image pre-processing, component labeling and feature extraction modules were modeled at Register Transfer (RT) level and synthesized for implementation on field programmable gate arrays (FPGA). The extracted image component features were sent from the hardware modules to a soft-core processor, MicroBlaze, for computation of distance and angle. A CMOS imaging sensor operating at a clock frequency of 27MHz was used in our experiments to produce a video stream at the rate of 75 frames per second. Image component labeling and feature extraction modules were running in parallel having a total latency of 13ms. The MicroBlaze was interfaced with the component labeling and feature extraction modules through Fast Simplex Link (FSL). The latency for computing distance and angle of camera from the reference points was measured to be 2ms on the MicroBlaze, running at 100 MHz clock frequency. In this paper, we present the performance analysis, device utilization and power consumption for the designed system. The FPGA based machine vision system that we propose has high frame speed, low latency and a power consumption that is much lower compared to commercially available smart camera solutions.

Real time image synthesis on a SIMD linear array processor: algorithms and architectures

International Nuclear Information System (INIS)

Letellier, Laurent

1993-01-01

Nowadays, image synthesis has become a widely used technique. The impressive computing power required for real time applications necessitates the use of parallel architectures. In this context, we evaluate an SIMD linear parallel architecture, SYMPATI2, dedicated to image processing. The objective of this study is to propose a cost-effective graphics accelerator relying on SYMPATI2's modular and programmable structure. The parallelization of basic image synthesis algorithms on SYMPATI2 enables us to determine its limits in this application field. These limits lead us to evaluate a new structure with a fast intercommunication network between processors, but processors have to support the message consistency, which brings about a strong decrease in performance. To solve this problem, we suggest a simple network whose access priorities are represented by tokens. The simulations of this new architecture indicate that the SIMD mode causes a drastic cut in parallelism. To cope with this drawback, we propose a context switching procedure which reduces the SIMD rigidity and increases the parallelism rate significantly. Then, the graphics accelerator we propose is compared with existing graphics workstations. This comparison indicates that our structure, which is able to accelerate both image synthesis and image processing, is competitive and well-suited for multimedia applications. (author) [fr

A Time-Composable Operating System for the Patmos Processor

DEFF Research Database (Denmark)

Ziccardi, Marco; Schoeberl, Martin; Vardanega, Tullio

2015-01-01

-composable operating system, on top of a time-composable processor, facilitates incremental development, which is highly desirable for industry. This paper makes a twofold contribution. First, we present enhancements to the Patmos processor to allow achieving time composability at the operating system level. Second......, we extend an existing time-composable operating system, TiCOS, to make best use of advanced Patmos hardware features in the pursuit of time composability.......In the last couple of decades we have witnessed a steady growth in the complexity and widespread of real-time systems. In order to master the rising complexity in the timing behaviour of those systems, rightful attention has been given to the development of time-predictable computer architectures...

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Timing organization of a real-time multicore processor

DEFF Research Database (Denmark)

Schoeberl, Martin; Sparsø, Jens

2017-01-01

Real-time systems need a time-predictable computing platform. Computation, communication, and access to shared resources needs to be time-predictable. We use time division multiplexing to statically schedule all computation and communication resources, such as access to main memory or message...... passing over a network-on-chip. We use time-driven communication over an asynchronous network-on-chip to enable time division multiplexing even in a globally asynchronous, locally synchronous multicore architecture. Using time division multiplexing at all levels of the architecture yields in a time...

Interactive Real-time Magnetic Resonance Imaging

DEFF Research Database (Denmark)

Brix, Lau

seeks to implement and assess existing reconstruction algorithms using multi-processors of modern graphics cards and many-core computer processors and to cover some of the potential clinical applications which might benefit from using an interactive real-time MRI system. First an off...

Real time implementation of a linear predictive coding algorithm on digital signal processor DSP32C

International Nuclear Information System (INIS)

Sheikh, N.M.; Usman, S.R.; Fatima, S.

2002-01-01

Pulse Code Modulation (PCM) has been widely used in speech coding. However, due to its high bit rate. PCM has severe limitations in application where high spectral efficiency is desired, for example, in mobile communication, CD quality broadcasting system etc. These limitation have motivated research in bit rate reduction techniques. Linear predictive coding (LPC) is one of the most powerful complex techniques for bit rate reduction. With the introduction of powerful digital signal processors (DSP) it is possible to implement the complex LPC algorithm in real time. In this paper we present a real time implementation of the LPC algorithm on AT and T's DSP32C at a sampling frequency of 8192 HZ. Application of the LPC algorithm on two speech signals is discussed. Using this implementation , a bit rate reduction of 1:3 is achieved for better than tool quality speech, while a reduction of 1.16 is possible for speech quality required in military applications. (author)

T-L Plane Abstraction-Based Energy-Efficient Real-Time Scheduling for Multi-Core Wireless Sensors

Directory of Open Access Journals (Sweden)

Youngmin Kim

2016-07-01

Full Text Available Energy efficiency is considered as a critical requirement for wireless sensor networks. As more wireless sensor nodes are equipped with multi-cores, there are emerging needs for energy-efficient real-time scheduling algorithms. The T-L plane-based scheme is known to be an optimal global scheduling technique for periodic real-time tasks on multi-cores. Unfortunately, there has been a scarcity of studies on extending T-L plane-based scheduling algorithms to exploit energy-saving techniques. In this paper, we propose a new T-L plane-based algorithm enabling energy-efficient real-time scheduling on multi-core sensor nodes with dynamic power management (DPM. Our approach addresses the overhead of processor mode transitions and reduces fragmentations of the idle time, which are inherent in T-L plane-based algorithms. Our experimental results show the effectiveness of the proposed algorithm compared to other energy-aware scheduling methods on T-L plane abstraction.

An Asynchronous Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

DEFF Research Database (Denmark)

Kasapaki, Evangelia

is an important part of the T-CREST paltform and used in a number of configurations. The flexible timing organization of Argo combines asynchronous routers with mesochronous NIs, which are connected to individually clocked cores, supporting a GALS system organization. The mesochronous NIs operate at the same......Multi-processor architectures using networks-on-chip (NOCs) for communication are becoming the standard approach in the development of embedded systems and general purpose platforms. Typically, multi-processor platforms follow a globally asynchronous locally synchronous (GALS) timing organization....... This thesis focuses on the design of Argo, a NOC targeted at hard real-time multi-processor platforms with a GALS timing organization. To support real-time communication, NOCs establish end-to-end connections and provide latency and throughput guarantees for these connections. Argo uses time division...

The Design of a Real-Time Distributed System

NARCIS (Netherlands)

Hertzberger, L.O.; Mullender, S.J.; Poletiek, G.; van Renesse, R.; Tanenbaum, A.S.; Tuynman, F.; Vermeulen, J.C.

1986-01-01

In modern physics experiments an increasing number and variety of programmable processors is used. As a consequence, a software environment is needed that provides an integrated approach to development, testing and use of real-time distributed software. This contribution is based on work being done

Blocking Optimality in Distributed Real-Time Locking Protocols

Directory of Open Access Journals (Sweden)

Björn Bernhard Brandenburg

2014-09-01

Full Text Available Lower and upper bounds on the maximum priority inversion blocking (pi-blocking that is generally unavoidable in distributed multiprocessor real-time locking protocols (where resources may be accessed only from specific synchronization processors are established. Prior work on suspension-based shared-memory multiprocessor locking protocols (which require resources to be accessible from all processors has established asymptotically tight bounds of Ω(m and Ω(n maximum pi-blocking under suspension-oblivious and suspension-aware analysis, respectively, where m denotes the total number of processors and n denotes the number of tasks. In this paper, it is shown that, in the case of distributed semaphore protocols, there exist two different task allocation scenarios that give rise to distinct lower bounds. In the case of co-hosted task allocation, where application tasks may also be assigned to synchronization processors (i.e., processors hosting critical sections, Ω(Φ · n maximum pi-blocking is unavoidable for some tasks under any locking protocol under both suspension-aware and suspension-oblivious schedulability analysis, where Φ denotes the ratio of the maximum response time to the shortest period. In contrast, in the case of disjoint task allocation (i.e., if application tasks may not be assigned to synchronization processors, only Ω(m and Ω(n maximum pi-blocking is fundamentally unavoidable under suspension-oblivious and suspension-aware analysis, respectively, as in the shared-memory case. These bounds are shown to be asymptotically tight with the construction of two new distributed real-time locking protocols that ensure O(m and O(n maximum pi-blocking under suspension-oblivious and suspension-aware analysis, respectively.

Distributed Arithmetic for Efficient Base-Band Processing in Real-Time GNSS Software Receivers

Directory of Open Access Journals (Sweden)

Grégoire Waelchli

2010-01-01

Full Text Available The growing market of GNSS capable mobile devices is driving the interest of GNSS software solutions, as they can share many system resources (processor, memory, reducing both the size and the cost of their integration. Indeed, with the increasing performance of modern processors, it becomes now feasible to implement in software a multichannel GNSS receiver operating in real time. However, a major issue with this approach is the large computing resources required for the base-band processing, in particular for the correlation operations. Therefore, new algorithms need to be developed in order to reduce the overall complexity of the receiver architecture. Towards that aim, this paper first introduces the challenges of the software implementation of a GPS receiver, with a main focus given to the base-band processing and correlation operations. It then describes the already existing solutions and, from this, introduces a new algorithm based on distributed arithmetic.

Real-time video compressing under DSP/BIOS

Science.gov (United States)

Chen, Qiu-ping; Li, Gui-ju

2009-10-01

This paper presents real-time MPEG-4 Simple Profile video compressing based on the DSP processor. The programming framework of video compressing is constructed using TMS320C6416 Microprocessor, TDS510 simulator and PC. It uses embedded real-time operating system DSP/BIOS and the API functions to build periodic function, tasks and interruptions etcs. Realize real-time video compressing. To the questions of data transferring among the system. Based on the architecture of the C64x DSP, utilized double buffer switched and EDMA data transfer controller to transit data from external memory to internal, and realize data transition and processing at the same time; the architecture level optimizations are used to improve software pipeline. The system used DSP/BIOS to realize multi-thread scheduling. The whole system realizes high speed transition of a great deal of data. Experimental results show the encoder can realize real-time encoding of 768*576, 25 frame/s video images.

Static Schedulers for Embedded Real-Time Systems

Science.gov (United States)

1989-12-01

Because of the need for having efficient scheduling algorithms in large scale real time systems , software engineers put a lot of effort on developing...provide static schedulers for he Embedded Real Time Systems with single processor using Ada programming language. The independent nonpreemptable...support the Computer Aided Rapid Prototyping for Embedded Real Time Systems so that we determine whether the system, as designed, meets the required

Time Manager Software for a Flight Processor

Science.gov (United States)

Zoerne, Roger

2012-01-01

Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

FPGA-based architecture for motion recovering in real-time

Science.gov (United States)

Arias-Estrada, Miguel; Maya-Rueda, Selene E.; Torres-Huitzil, Cesar

2002-03-01

A key problem in the computer vision field is the measurement of object motion in a scene. The main goal is to compute an approximation of the 3D motion from the analysis of an image sequence. Once computed, this information can be used as a basis to reach higher level goals in different applications. Motion estimation algorithms pose a significant computational load for the sequential processors limiting its use in practical applications. In this work we propose a hardware architecture for motion estimation in real time based on FPGA technology. The technique used for motion estimation is Optical Flow due to its accuracy, and the density of velocity estimation, however other techniques are being explored. The architecture is composed of parallel modules working in a pipeline scheme to reach high throughput rates near gigaflops. The modules are organized in a regular structure to provide a high degree of flexibility to cover different applications. Some results will be presented and the real-time performance will be discussed and analyzed. The architecture is prototyped in an FPGA board with a Virtex device interfaced to a digital imager.

The Fast Tracker Real Time Processor: high quality real-time tracking at ATLAS

CERN Document Server

Stabile, A; The ATLAS collaboration

2011-01-01

As the LHC luminosity is ramped up to the design level of 1x1034 cm−2 s−1 and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the most important physics and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK)[1], [2] is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK is a dedicated Super Computer based on a mixture of advanced technologies. The architecture broadly employs powerf...

High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

Science.gov (United States)

Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

2016-04-01

In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

The design of a real-time distributed system

International Nuclear Information System (INIS)

Hertzberger, L.O.; Tuynman, F.; Mullender, S.J.; Poletiek, G.; Vermeulen, J.C.; Renesse, R. van; Tanenbaum, A.S.

1986-01-01

In modern physics experiments an increasing number and variety of programmable processors is used. As a consequence, a software environment is needed that provides an integrated approach to development, testing and use of real-time distributed software. This contribution is based on work being done in the AMOEBA Distributed Operating System Project and the FADOS Real-Time Distributed Operating System Project. A short description of both systems is presented as an example of how basic real-time operating system services can be organized. AMOEBA is the result of fundamental research in the field of distributed operating systems, while FADOS has been designed for applications as encountered in experimental high-energy physics. (Auth.)

A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

DEFF Research Database (Denmark)

Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

2017-01-01

-source DPR controller specially developed for hard real-time systems and prototyped in connection with the open-source multi-core platform for real-time applications T-CREST. The controller enables a processor to perform reconfiguration in a time-predictable manner and supports different operating modes......In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading....... The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example...

Real-time communication for distributed plasma control systems

Energy Technology Data Exchange (ETDEWEB)

Luchetta, A. [Consorzio RFX, Associazione Euratom-ENEA sulla Fusione, Corso Stati Uniti 4, Padova 35127 (Italy)], E-mail: adriano.luchetta@igi.cnr.it; Barbalace, A.; Manduchi, G.; Soppelsa, A.; Taliercio, C. [Consorzio RFX, Associazione Euratom-ENEA sulla Fusione, Corso Stati Uniti 4, Padova 35127 (Italy)

2008-04-15

Real-time control applications will benefit in the near future from the enhanced performance provided by multi-core processor architectures. Nevertheless real-time communication will continue to be critical in distributed plasma control systems where the plant under control typically is distributed over a wide area. At RFX-mod real-time communication is crucial for hard real-time plasma control, due to the distributed architecture of the system, which consists of several VMEbus stations. The system runs under VxWorks and uses Gigabit Ethernet for sub-millisecond real-time communication. To optimize communication in the system, a set of detailed measurements has been carried out on the target platforms (Motorola MVME5100 and MVME5500) using either the VxWorks User Datagram Protocol (UDP) stack or raw communication based on the data link layer. Measurements have been carried out also under Linux, using its UDP stack or, in alternative, RTnet, an open source hard real-time network protocol stack. RTnet runs under Xenomai or RTAI, two popular real-time extensions based on the Linux kernel. The paper reports on the measurements carried out and compares the results, showing that the performance obtained by using open source code is suitable for sub-millisecond real-time communication in plasma control.

Java Processor Optimized for RTSJ

Directory of Open Access Journals (Sweden)

Tu Shiliang

2007-01-01

Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

Design Optimization of Mixed-Criticality Real-Time Embedded Systems

DEFF Research Database (Denmark)

Tamas-Selicean, Domitian; Pop, Paul

2015-01-01

is allocated several time slots on a processor. Tasks of different SILs can share a partition only if they are all elevated to the highest SIL among them. Such elevation leads to increased development costs, which increase dramatically with each SIL. Tasks of higher SILs can be decomposed into redundant...... structures of lower SIL tasks. We are interested to determine (i) the mapping of tasks to processors, (ii) the assignment of tasks to partitions, (iii) the decomposition of tasks into redundant lower SIL tasks, (iv) the sequence and size of the partition time slots on each processor, and (v) the schedule...... tables, such that all the applications are schedulable and the development costs are minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks....

The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

International Nuclear Information System (INIS)

Clark, D.L.

1983-01-01

The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

A HARDWARE SUPPORTED OPERATING SYSTEM KERNEL FOR EMBEDDED HARD REAL-TIME APPLICATIONS

NARCIS (Netherlands)

COLNARIC, M; HALANG, WA; TOL, RM

1994-01-01

The concept of the kernel, i.e. the time critical part of a real-time operating system, and its dedicated co-processor, especially tailored for embedded applications, are presented. The co-processor acts as a system controller and operates in conjunction with one or more conventional processors in

Real-time implementation of logo detection on open source BeagleBoard

Science.gov (United States)

George, M.; Kehtarnavaz, N.; Estevez, L.

2011-03-01

This paper presents the real-time implementation of our previously developed logo detection and tracking algorithm on the open source BeagleBoard mobile platform. This platform has an OMAP processor that incorporates an ARM Cortex processor. The algorithm combines Scale Invariant Feature Transform (SIFT) with k-means clustering, online color calibration and moment invariants to robustly detect and track logos in video. Various optimization steps that are carried out to allow the real-time execution of the algorithm on BeagleBoard are discussed. The results obtained are compared to the PC real-time implementation results.

The Fast Tracker Real Time Processor

CERN Document Server

Annovi, A; The ATLAS collaboration

2011-01-01

As the LHC luminosity is ramped up to the SLHC Phase I level and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in, and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK)[1], is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting massive parallelism of associative memories [2] that ...

Design and realization of real-time processing system for seismic exploration

International Nuclear Information System (INIS)

Zhang Sifeng; Cao Ping; Song Kezhu; Yao Lin

2010-01-01

For solving real-time seismic data processing problems, a high-speed, large-capacity and real-time data processing system is designed based on FPGA and ARM. With the advantages of multi-processor, DRPS has the characteristics of high-speed data receiving, large-capacity data storage, protocol analysis, data splicing, data converting from time sequence into channel sequence, no dead time data ping-pong storage, etc. And with the embedded Linux operating system, DRPS has the characteristics of flexibility and reliability. (authors)

Support for the Logical Execution Time Model on a Time-predictable Multicore Processor

DEFF Research Database (Denmark)

Kluge, Florian; Schoeberl, Martin; Ungerer, Theo

2016-01-01

The logical execution time (LET) model increases the compositionality of real-time task sets. Removal or addition of tasks does not influence the communication behavior of other tasks. In this work, we extend a multicore operating system running on a time-predictable multicore processor to support...... the LET model. For communication between tasks we use message passing on a time-predictable network-on-chip to avoid the bottleneck of shared memory. We report our experiences and present results on the costs in terms of memory and execution time....

Distributed Issues for Ada Real-Time Systems

Science.gov (United States)

1990-07-23

NUMBERS Distributed Issues for Ada Real - Time Systems MDA 903-87- C- 0056 S. AUTHOR(S) Thomas E. Griest 7. PERFORMING ORGANiZATION NAME(S) AND ADORESS(ES) 8...considerations. I Adding to the problem of distributed real - time systems is the issue of maintaining a common sense of time among all of the processors...because -omeone is waiting for the final output of a very large set of computations. However in real - time systems , consistent meeting of short-term

Real time animation of space plasma phenomena

International Nuclear Information System (INIS)

Jordan, K.F.; Greenstadt, E.W.

1987-01-01

In pursuit of real time animation of computer simulated space plasma phenomena, the code was rewritten for the Massively Parallel Processor (MPP). The program creates a dynamic representation of the global bowshock which is based on actual spacecraft data and designed for three dimensional graphic output. This output consists of time slice sequences which make up the frames of the animation. With the MPP, 16384, 512 or 4 frames can be calculated simultaneously depending upon which characteristic is being computed. The run time was greatly reduced which promotes the rapid sequence of images and makes real time animation a foreseeable goal. The addition of more complex phenomenology in the constructed computer images is now possible and work proceeds to generate these images

Array processors based on Gaussian fraction-free method

Energy Technology Data Exchange (ETDEWEB)

Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

1998-03-01

The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

A UNIX-based prototype biomedical virtual image processor

International Nuclear Information System (INIS)

Fahy, J.B.; Kim, Y.

1987-01-01

The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

ISTTOK real-time architecture

Energy Technology Data Exchange (ETDEWEB)

Carvalho, Ivo S., E-mail: ivoc@ipfn.ist.utl.pt; Duarte, Paulo; Fernandes, Horácio; Valcárcel, Daniel F.; Carvalho, Pedro J.; Silva, Carlos; Duarte, André S.; Neto, André; Sousa, Jorge; Batista, António J.N.; Hekkert, Tiago; Carvalho, Bernardo B.

2014-03-15

Highlights: • All real-time diagnostics and actuators were integrated in the same control platform. • A 100 μs control cycle was achieved under the MARTe framework. • Time-windows based control with several event-driven control strategies implemented. • AC discharges with exception handling on iron core flux saturation. • An HTML discharge configuration was developed for configuring the MARTe system. - Abstract: The ISTTOK tokamak was upgraded with a plasma control system based on the Advanced Telecommunications Computing Architecture (ATCA) standard. This control system was designed to improve the discharge stability and to extend the operational space to the alternate plasma current (AC) discharges as part of the ISTTOK scientific program. In order to accomplish these objectives all ISTTOK diagnostics and actuators relevant for real-time operation were integrated in the control system. The control system was programmed in C++ over the Multi-threaded Application Real-Time executor (MARTe) which provides, among other features, a real-time scheduler, an interrupt handler, an intercommunications interface between code blocks and a clearly bounded interface with the external devices. As a complement to the MARTe framework, the BaseLib2 library provides the foundations for the data, code introspection and also a Hypertext Transfer Protocol (HTTP) server service. Taking advantage of the modular nature of MARTe, the algorithms of each diagnostic data processing, discharge timing, context switch, control and actuators output reference generation, run on well-defined blocks of code named Generic Application Module (GAM). This approach allows reusability of the code, simplified simulation, replacement or editing without changing the remaining GAMs. The ISTTOK control system GAMs run sequentially each 100 μs cycle on an Intel{sup ®} Q8200 4-core processor running at 2.33 GHz located in the ATCA crate. Two boards (inside the ATCA crate) with 32 analog

ISTTOK real-time architecture

International Nuclear Information System (INIS)

Carvalho, Ivo S.; Duarte, Paulo; Fernandes, Horácio; Valcárcel, Daniel F.; Carvalho, Pedro J.; Silva, Carlos; Duarte, André S.; Neto, André; Sousa, Jorge; Batista, António J.N.; Hekkert, Tiago; Carvalho, Bernardo B.

2014-01-01

Highlights: • All real-time diagnostics and actuators were integrated in the same control platform. • A 100 μs control cycle was achieved under the MARTe framework. • Time-windows based control with several event-driven control strategies implemented. • AC discharges with exception handling on iron core flux saturation. • An HTML discharge configuration was developed for configuring the MARTe system. - Abstract: The ISTTOK tokamak was upgraded with a plasma control system based on the Advanced Telecommunications Computing Architecture (ATCA) standard. This control system was designed to improve the discharge stability and to extend the operational space to the alternate plasma current (AC) discharges as part of the ISTTOK scientific program. In order to accomplish these objectives all ISTTOK diagnostics and actuators relevant for real-time operation were integrated in the control system. The control system was programmed in C++ over the Multi-threaded Application Real-Time executor (MARTe) which provides, among other features, a real-time scheduler, an interrupt handler, an intercommunications interface between code blocks and a clearly bounded interface with the external devices. As a complement to the MARTe framework, the BaseLib2 library provides the foundations for the data, code introspection and also a Hypertext Transfer Protocol (HTTP) server service. Taking advantage of the modular nature of MARTe, the algorithms of each diagnostic data processing, discharge timing, context switch, control and actuators output reference generation, run on well-defined blocks of code named Generic Application Module (GAM). This approach allows reusability of the code, simplified simulation, replacement or editing without changing the remaining GAMs. The ISTTOK control system GAMs run sequentially each 100 μs cycle on an Intel ® Q8200 4-core processor running at 2.33 GHz located in the ATCA crate. Two boards (inside the ATCA crate) with 32 analog

Real-time software for the COMPASS tokamak plasma control

International Nuclear Information System (INIS)

Valcarcel, D.F.; Duarte, A.S.; Neto, A.; Carvalho, I.S.; Carvalho, B.B.; Fernandes, H.; Sousa, J.; Sartori, F.; Janky, F.; Cahyna, P.; Hron, M.; Panek, R.

2010-01-01

The COMPASS tokamak has started its operation recently in Prague and to meet the necessary operation parameters its real-time system, for data processing and control, must be designed for both flexibility and performance, allowing the easy integration of code from several developers and to guarantee the desired time cycle. For this purpose an Advanced Telecommunications Computing Architecture based real-time system has been deployed with a solution built on a multi-core x86 processor. It makes use of two software components: the BaseLib2 and the MARTe (Multithreaded Application Real-Time executor) real-time frameworks. The BaseLib2 framework is a generic real-time library with optimized objects for the implementation of real-time algorithms. This allowed to build a library of modules that process the acquired data and execute control algorithms. MARTe executes these modules in kernel space Real-Time Application Interface allowing to attain the required cycle time and a jitter of less than 1.5 μs. MARTe configuration and data storage are accomplished through a Java hardware client that connects to the FireSignal control and data acquisition software. This article details the implementation of the real-time system for the COMPASS tokamak, in particular the organization of the control code, the design and implementation of the communications with the actuators and how MARTe integrates with the FireSignal software.

Real-time software for the COMPASS tokamak plasma control

Energy Technology Data Exchange (ETDEWEB)

Valcarcel, D.F., E-mail: danielv@ipfn.ist.utl.p [Associacao EURATOM/IST, Instituto de Plasmas e Fusao Nuclear - Laboratorio Associado, Instituto Superior Tecnico, P-1049-001 Lisboa (Portugal); Duarte, A.S.; Neto, A.; Carvalho, I.S.; Carvalho, B.B.; Fernandes, H.; Sousa, J. [Associacao EURATOM/IST, Instituto de Plasmas e Fusao Nuclear - Laboratorio Associado, Instituto Superior Tecnico, P-1049-001 Lisboa (Portugal); Sartori, F. [Euratom-UKAEA, Culham Science Centre, Abingdon, OX14 3DB Oxon (United Kingdom); Janky, F.; Cahyna, P.; Hron, M.; Panek, R. [Institute of Plasma Physics AS CR, v.v.i., Association EURATOM/IPP.CR, Za Slovankou 3, 182 00 Prague (Czech Republic)

2010-07-15

The COMPASS tokamak has started its operation recently in Prague and to meet the necessary operation parameters its real-time system, for data processing and control, must be designed for both flexibility and performance, allowing the easy integration of code from several developers and to guarantee the desired time cycle. For this purpose an Advanced Telecommunications Computing Architecture based real-time system has been deployed with a solution built on a multi-core x86 processor. It makes use of two software components: the BaseLib2 and the MARTe (Multithreaded Application Real-Time executor) real-time frameworks. The BaseLib2 framework is a generic real-time library with optimized objects for the implementation of real-time algorithms. This allowed to build a library of modules that process the acquired data and execute control algorithms. MARTe executes these modules in kernel space Real-Time Application Interface allowing to attain the required cycle time and a jitter of less than 1.5 {mu}s. MARTe configuration and data storage are accomplished through a Java hardware client that connects to the FireSignal control and data acquisition software. This article details the implementation of the real-time system for the COMPASS tokamak, in particular the organization of the control code, the design and implementation of the communications with the actuators and how MARTe integrates with the FireSignal software.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery.

Science.gov (United States)

Qi, Baogui; Shi, Hao; Zhuang, Yin; Chen, He; Chen, Liang

2018-04-25

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery

Science.gov (United States)

Qi, Baogui; Zhuang, Yin; Chen, He; Chen, Liang

2018-01-01

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited. PMID:29693585

Energy-efficient fault tolerance in multiprocessor real-time systems

Science.gov (United States)

Guo, Yifeng

The recent progress in the multiprocessor/multicore systems has important implications for real-time system design and operation. From vehicle navigation to space applications as well as industrial control systems, the trend is to deploy multiple processors in real-time systems: systems with 4 -- 8 processors are common, and it is expected that many-core systems with dozens of processing cores will be available in near future. For such systems, in addition to general temporal requirement common for all real-time systems, two additional operational objectives are seen as critical: energy efficiency and fault tolerance. An intriguing dimension of the problem is that energy efficiency and fault tolerance are typically conflicting objectives, due to the fact that tolerating faults (e.g., permanent/transient) often requires extra resources with high energy consumption potential. In this dissertation, various techniques for energy-efficient fault tolerance in multiprocessor real-time systems have been investigated. First, the Reliability-Aware Power Management (RAPM) framework, which can preserve the system reliability with respect to transient faults when Dynamic Voltage Scaling (DVS) is applied for energy savings, is extended to support parallel real-time applications with precedence constraints. Next, the traditional Standby-Sparing (SS) technique for dual processor systems, which takes both transient and permanent faults into consideration while saving energy, is generalized to support multiprocessor systems with arbitrary number of identical processors. Observing the inefficient usage of slack time in the SS technique, a Preference-Oriented Scheduling Framework is designed to address the problem where tasks are given preferences for being executed as soon as possible (ASAP) or as late as possible (ALAP). A preference-oriented earliest deadline (POED) scheduler is proposed and its application in multiprocessor systems for energy-efficient fault tolerance is

Hardware Approach for Real Time Machine Stereo Vision

Directory of Open Access Journals (Sweden)

Michael Tornow

2006-02-01

Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

Real-time phase correlation based integrated system for seizure detection

Science.gov (United States)

Romaine, James B.; Delgado-Restituto, Manuel; Leñero-Bardallo, Juan A.; Rodríguez-Vázquez, Ángel

2017-05-01

This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.

Optimal processor for malfunction detection in operating nuclear reactor

International Nuclear Information System (INIS)

Ciftcioglu, O.

1990-01-01

An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

A real-time expert system for nuclear power plant failure diagnosis and operational guide

International Nuclear Information System (INIS)

Naito, N.; Sakuma, A.; Shigeno, K.; Mori, N.

1987-01-01

A real-time expert system (DIAREX) has been developed to diagnose plant failure and to offer a corrective operational guide for boiling water reactor (BWR) power plants. The failure diagnosis model used in DIAREX was systematically developed, based mainly on deep knowledge, to cover heuristics. Complex paradigms for knowledge representation were adopted, i.e., the process representation language and the failure propagation tree. The system is composed of a knowledge base, knowledge base editor, preprocessor, diagnosis processor, and display processor. The DIAREX simulation test has been carried out for many transient scenarios, including multiple failures, using a real-time full-scope simulator modeled after the 1100-MW(electric) BWR power plant. Test results showed that DIAREX was capable of diagnosing a plant failure quickly and of providing a corrective operational guide with a response time fast enough to offer valuable information to plant operators

Hardware processor for tracking particles in an alternating-gradient synchrotron

International Nuclear Information System (INIS)

Johnson, M.; Avilez, C.

1987-01-01

We discuss the design and performance of special-purpose processors for tracking particles through an alternating-gradient synchrotron. We present block diagram designs for two hardware processors. Both processors use algorithms based on the 'kick' approximation, i.e., transport matrices are used for dipoles and quadrupoles, and the thin-lens approximation is used for all higher multipoles. The faster processor makes extensive use of memory look-up tables for evaluating functions. For the case of magnets with multipoles up to pole 30 and using one kick per magnet, this processor can track 19 particles through an accelerator at a rate that is only 220 times slower than the time it takes real particles to travel around the machine. For a model consisting of only thin lenses, it is only 150 times slower than real particles. An additional factor of 2 can be obtained with chips now becoming available. The number of magnets in the accelerator is limited only by the amount of memory available for storing magnet parameters. (author) 20 refs., 7 figs., 2 tabs

An SDRAM controller for real-time systems

DEFF Research Database (Denmark)

Lakis, Edgar; Schoeberl, Martin

2013-01-01

For real-time systems we need to statically determine worst-case execution times (WCET) of tasks to proof the schedulability of the system. To enable static WCET analysis, the platform needs to be time-predictable. The platform includes the processor, the caches, the memory system, the operating...... system, and the application software itself. All those components need to be timing analyzable. Current computers use DRAM as a cost effective main memory. However, these DRAM chips have timing requirements that depend on former accesses and also need to be refreshed to retain their content. Standard...... a base of the memory hierarchy for time-predictable systems....

Embedded Real-Time Architecture for Level-Set-Based Active Contours

Directory of Open Access Journals (Sweden)

Dejnožková Eva

2005-01-01

Full Text Available Methods described by partial differential equations have gained a considerable interest because of undoubtful advantages such as an easy mathematical description of the underlying physics phenomena, subpixel precision, isotropy, or direct extension to higher dimensions. Though their implementation within the level set framework offers other interesting advantages, their vast industrial deployment on embedded systems is slowed down by their considerable computational effort. This paper exploits the high parallelization potential of the operators from the level set framework and proposes a scalable, asynchronous, multiprocessor platform suitable for system-on-chip solutions. We concentrate on obtaining real-time execution capabilities. The performance is evaluated on a continuous watershed and an object-tracking application based on a simple gradient-based attraction force driving the active countour. The proposed architecture can be realized on commercially available FPGAs. It is built around general-purpose processor cores, and can run code developed with usual tools.

Powerful conveyer belt real-time online detection system based on x-ray

Science.gov (United States)

Rong, Feng; Miao, Chang-yun; Meng, Wei

2009-07-01

The powerful conveyer belt is widely used in the mine, dock, and so on. After used for a long time, internal steel rope of the conveyor belt may fracture, rust, joints moving, and so on .This would bring potential safety problems. A kind of detection system based on x-ray is designed in this paper. Linear array detector (LDA) is used. LDA cost is low, response fast; technology mature .Output charge of LDA is transformed into differential voltage signal by amplifier. This kind of signal have great ability of anti-noise, is suitable for long-distance transmission. The processor is FPGA. A IP core control 4-channel A/D convertor, achieve parallel output data collection. Soft-core processor MicroBlaze which process tcp/ip protocol is embedded in FPGA. Sampling data are transferred to a computer via Ethernet. In order to improve the image quality, algorithm of getting rid of noise from the measurement result and taking gain normalization for pixel value is studied and designed. Experiments show that this system work well, can real-time online detect conveyor belt of width of 2.0m and speed of 5 m/s, does not affect the production. Image is clear, visual and can easily judge the situation of conveyor belt.

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

Science.gov (United States)

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Implementing real-time robotic systems using CHIMERA II

Science.gov (United States)

Stewart, David B.; Schmitz, Donald E.; Khosla, Pradeep K.

1990-01-01

A description is given of the CHIMERA II programming environment and operating system, which was developed for implementing real-time robotic systems. Sensor-based robotic systems contain both general- and special-purpose hardware, and thus the development of applications tends to be a time-consuming task. The CHIMERA II environment is designed to reduce the development time by providing a convenient software interface between the hardware and the user. CHIMERA II supports flexible hardware configurations which are based on one or more VME-backplanes. All communication across multiple processors is transparent to the user through an extensive set of interprocessor communication primitives. CHIMERA II also provides a high-performance real-time kernel which supports both deadline and highest-priority-first scheduling. The flexibility of CHIMERA II allows hierarchical models for robot control, such as NASREM, to be implemented with minimal programming time and effort.

Real-time multi-camera video acquisition and processing platform for ADAS

Science.gov (United States)

Saponara, Sergio

2016-04-01

The paper presents the design of a real-time and low-cost embedded system for image acquisition and processing in Advanced Driver Assisted Systems (ADAS). The system adopts a multi-camera architecture to provide a panoramic view of the objects surrounding the vehicle. Fish-eye lenses are used to achieve a large Field of View (FOV). Since they introduce radial distortion of the images projected on the sensors, a real-time algorithm for their correction is also implemented in a pre-processor. An FPGA-based hardware implementation, re-using IP macrocells for several ADAS algorithms, allows for real-time processing of input streams from VGA automotive CMOS cameras.

Hardware trigger processor for the MDT system

CERN Document Server

AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

2017-01-01

We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

High-level synthesis for reduction of WCET in real-time systems

DEFF Research Database (Denmark)

Kristensen, Andreas Toftegaard; Pezzarossa, Luca; Sparsø, Jens

2017-01-01

. Compared to executing the high-level language code on a processor, HLS can be used to create hardware that accelerates critical parts of the code. When discussing performance in the context or real-time systems, it is the worst-case execution time (WCET) of a task that matters. WCET obviously benefits from...... hardware acceleration, but it may also benefit from a tighter bound on the WCET. This paper explores the use of and integration of accelerators generated using HLS into a time-predictable processor intended for real-time systems. The high-level design tool, Vivado HLS, is used to generate hardware...

WCET Analysis of ARM Processors using Real-Time Model Checking

DEFF Research Database (Denmark)

Toft, Martin; Olesen, Mads Christian; Dalsgaard, Andreas

2009-01-01

This paper presents a flexible method that utilises real-time model checking to determine safe and sharp WCETs for processes running on hardware platforms featuring pipelining and caching.......This paper presents a flexible method that utilises real-time model checking to determine safe and sharp WCETs for processes running on hardware platforms featuring pipelining and caching....

A class of kernel based real-time elastography algorithms.

Science.gov (United States)

Kibria, Md Golam; Hasan, Md Kamrul

2015-08-01

In this paper, a novel real-time kernel-based and gradient-based Phase Root Seeking (PRS) algorithm for ultrasound elastography is proposed. The signal-to-noise ratio of the strain image resulting from this method is improved by minimizing the cross-correlation discrepancy between the pre- and post-compression radio frequency signals with an adaptive temporal stretching method and employing built-in smoothing through an exponentially weighted neighborhood kernel in the displacement calculation. Unlike conventional PRS algorithms, displacement due to tissue compression is estimated from the root of the weighted average of the zero-lag cross-correlation phases of the pair of corresponding analytic pre- and post-compression windows in the neighborhood kernel. In addition to the proposed one, the other time- and frequency-domain elastography algorithms (Ara et al., 2013; Hussain et al., 2012; Hasan et al., 2012) proposed by our group are also implemented in real-time using Java where the computations are serially executed or parallely executed in multiple processors with efficient memory management. Simulation results using finite element modeling simulation phantom show that the proposed method significantly improves the strain image quality in terms of elastographic signal-to-noise ratio (SNRe), elastographic contrast-to-noise ratio (CNRe) and mean structural similarity (MSSIM) for strains as high as 4% as compared to other reported techniques in the literature. Strain images obtained for the experimental phantom as well as in vivo breast data of malignant or benign masses also show the efficacy of our proposed method over the other reported techniques in the literature. Copyright © 2015 Elsevier B.V. All rights reserved.

Real-time recursive motion segmentation of video data on a programmable device

NARCIS (Netherlands)

Wittebrood, R.B; Haan, de G.

2001-01-01

We previously reported on a recursive algorithm enabling real-time object-based motion estimation (OME) of standard definition video on a digital signal processor (DSP). The algorithm approximates the motion of the objects in the image with parametric motion models and creates a segmentation mask by

New technologies for supporting real-time on-board software development

Science.gov (United States)

Kerridge, D.

1995-03-01

The next generation of on-board data management systems will be significantly more complex than current designs, and will be required to perform more complex and demanding tasks in software. Improved hardware technology, in the form of the MA31750 radiation hard processor, is one key component in addressing the needs of future embedded systems. However, to complement these hardware advances, improved support for the design and implementation of real-time data management software is now needed. This will help to control the cost and risk assoicated with developing data management software development as it becomes an increasingly significant element within embedded systems. One particular problem with developing embedded software is managing the non-functional requirements in a systematic way. This paper identifies how Logica has exploited recent developments in hard real-time theory to address this problem through the use of new hard real-time analysis and design methods which can be supported by specialized tools. The first stage in transferring this technology from the research domain to industrial application has already been completed. The MA37150 Hard Real-Time Embedded Software Support Environment (HESSE) is a loosely integrated set of hardware and software tools which directly support the process of hard real-time analysis for software targeting the MA31750 processor. With further development, this HESSE promises to provide embedded system developers with software tools which can reduce the risks associated with developing complex hard real-time software. Supported in this way by more sophisticated software methods and tools, it is foreseen that MA31750 based embedded systems can meet the processing needs for the next generation of on-board data management systems.

Real-Time Hand-Held Magnetometer Array

Science.gov (United States)

2016-04-01

measurements, we swung a target, pendulum-style, from the ceiling above the array. We could easily observe that the height of the target was varying... crystal oscillator clock signal. The Microblaze processor boots up with the program already present in its RAM at startup. MR-2104 Real-Time

Real time operating system for a nuclear power plant computer

International Nuclear Information System (INIS)

Alger, L.S.; Lala, J.H.

1986-01-01

A quadruply redundant synchronous fault tolerant processor (FTP) is now under fabrication at the C.S. Draper Laboratory to be used initially as a trip monitor for the Experimental Breeder Reactor EBR-II operated by the Argonne National Laboratory in Idaho Falls, Idaho. The real time operating system for this processor is described

Design Optimization of Mixed-Criticality Real-Time Applications on Cost-Constrained Partitioned Architectures

DEFF Research Database (Denmark)

Tamas-Selicean, Domitian; Pop, Paul

2011-01-01

In this paper we are interested to implement mixed-criticality hard real-time applications on a given heterogeneous distributed architecture. Applications have different criticality levels, captured by their Safety-Integrity Level (SIL), and are scheduled using static-cyclic scheduling. Mixed......-criticality tasks can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. We consider that the separation is provided by partitioning, such that applications run in separate partitions, and each partition is allocated several time slots on a processor. Tasks...... slots on each processor and (iv) the schedule tables, such that all the applications are schedulable and the development costs are minimized. We have proposed a Tabu Search-based approach to solve this optimization problem. The proposed algorithm has been evaluated using several synthetic and real...

Model-Checking Real-Time Control Programs

DEFF Research Database (Denmark)

Iversen, T. K.; Kristoffersen, K. J.; Larsen, Kim Guldstrand

2000-01-01

In this paper, we present a method for automatic verification of real-time control programs running on LEGO(R) RCX(TM) bricks using the verification tool UPPALL. The control programs, consisting of a number of tasks running concurrently, are automatically translated into the mixed automata model...... of UPPAAL. The fixed scheduling algorithm used by the LEGO(R) RCX(TM) processor is modeled in UPPALL, and supply of similar (sufficient) timed automata models for the environment allows analysis of the overall real-time system using the tools of UPPALL. To illustrate our technique for sorting LEGO(R) bricks...

Self-Organization in Embedded Real-Time Systems

CERN Document Server

Brinkschulte, Uwe; Rettberg, Achim

2013-01-01

This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems.  Self-organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self-organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self-X features such as self-configuration, self-optimization, self-adaptation, self-healing and self-protection. Presents open components for embedded real-time adaptive and self-organizing applications; Describes innovative techniques in: scheduling, memory management, quality of service, communications supporting organic real-time applications; Covers multi-/many-core embedded systems supporting real-time adaptive systems and power-aware, adaptive hardware and software systems; Includes case studies of open embedded real-time self-organizi...

Verifying real-time systems against scenario-based requirements

DEFF Research Database (Denmark)

Larsen, Kim Guldstrand; Li, Shuhao; Nielsen, Brian

2009-01-01

We propose an approach to automatic verification of real-time systems against scenario-based requirements. A real-time system is modeled as a network of Timed Automata (TA), and a scenario-based requirement is specified as a Live Sequence Chart (LSC). We define a trace-based semantics for a kernel...... subset of the LSC language. By equivalently translating an LSC chart into an observer TA and then non-intrusively composing this observer with the original system model, the problem of verifying a real-time system against a scenario-based requirement reduces to a classical real-time model checking...

A real-time data transmission method based on Linux for physical experimental readout systems

International Nuclear Information System (INIS)

Cao Ping; Song Kezhu; Yang Junfeng

2012-01-01

In a typical physical experimental instrument, such as a fusion or particle physical application, the readout system generally implements an interface between the data acquisition (DAQ) system and the front-end electronics (FEE). The key task of a readout system is to read, pack, and forward the data from the FEE to the back-end data concentration center in real time. To guarantee real-time performance, the VxWorks operating system (OS) is widely used in readout systems. However, VxWorks is not an open-source OS, which gives it has many disadvantages. With the development of multi-core processor and new scheduling algorithm, Linux OS exhibits performance in real-time applications similar to that of VxWorks. It has been successfully used even for some hard real-time systems. Discussions and evaluations of real-time Linux solutions for a possible replacement of VxWorks arise naturally. In this paper, a real-time transmission method based on Linux is introduced. To reduce the number of transfer cycles for large amounts of data, a large block of contiguous memory buffer for DMA transfer is allocated by modifying the Linux Kernel (version 2.6) source code slightly. To increase the throughput for network transmission, the user software is designed into formation of parallelism. To achieve high performance in real-time data transfer from hardware to software, mapping techniques must be used to avoid unnecessary data copying. A simplified readout system is implemented with 4 readout modules in a PXI crate. This system can support up to 48 MB/s data throughput from the front-end hardware to the back-end concentration center through a Gigabit Ethernet connection. There are no restrictions on the use of this method, hardware or software, which means that it can be easily migrated to other interrupt related applications.

Safe and Efficient Support for Embeded Multi-Processors in ADA

Science.gov (United States)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

A distributed real-time operating system

International Nuclear Information System (INIS)

Tuynman, F.; Hertzberger, L.O.

1984-07-01

A distributed real-time operating system, Fados, has been developed for an embedded multi-processor system. The operating system is based on a host target approach and provides for communication between arbitrary processes on host and target machine. The facilities offered are, apart from process communication, access to the file system on the host by programs on the target machine and monitoring and debugging of programs on the target machine from the host. The process communication has been designed in such a way that the possibilities are the same as those offered by the Ada programming language. The operating system is implemented on a MC 68000 based multiprocessor system in combination with a Unix host. (orig.)

RTSPM: real-time Linux control software for scanning probe microscopy.

Science.gov (United States)

Chandrasekhar, V; Mehta, M M

2013-01-01

Real time computer control is an essential feature of scanning probe microscopes, which have become important tools for the characterization and investigation of nanometer scale samples. Most commercial (and some open-source) scanning probe data acquisition software uses digital signal processors to handle the real time data processing and control, which adds to the expense and complexity of the control software. We describe here scan control software that uses a single computer and a data acquisition card to acquire scan data. The computer runs an open-source real time Linux kernel, which permits fast acquisition and control while maintaining a responsive graphical user interface. Images from a simulated tuning-fork based microscope as well as a standard topographical sample are also presented, showing some of the capabilities of the software.

Real-time generation of the Wigner distribution of complex functions using phase conjugation in photorefractive materials.

Science.gov (United States)

Sun, P C; Fainman, Y

1990-09-01

An optical processor for real-time generation of the Wigner distribution of complex amplitude functions is introduced. The phase conjugation of the input signal is accomplished by a highly efficient self-pumped phase conjugator based on a 45 degrees -cut barium titanate photorefractive crystal. Experimental results on the real-time generation of Wigner distribution slices for complex amplitude two-dimensional optical functions are presented and discussed.

Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux

Directory of Open Access Journals (Sweden)

Daniel Pierre Bovet

2008-01-01

Full Text Available Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems. ASMP-LINUX is a modified, high responsiveness, open-source hard real-time operating system for multiprocessor systems capable of providing high real-time performance while maintaining the code simple and not impacting on the performances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking. In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platforms and configurations.

Hard Real-Time Performances in Multiprocessor-Embedded Systems Using ASMP-Linux

Directory of Open Access Journals (Sweden)

Betti Emiliano

2008-01-01

Full Text Available Abstract Multiprocessor systems, especially those based on multicore or multithreaded processors, and new operating system architectures can satisfy the ever increasing computational requirements of embedded systems. ASMP-LINUX is a modified, high responsiveness, open-source hard real-time operating system for multiprocessor systems capable of providing high real-time performance while maintaining the code simple and not impacting on the performances of the rest of the system. Moreover, ASMP-LINUX does not require code changing or application recompiling/relinking. In order to assess the performances of ASMP-LINUX, benchmarks have been performed on several hardware platforms and configurations.

NInFEA: an embedded framework for the real-time evaluation of fetal ECG extraction algorithms.

Science.gov (United States)

Pani, Danilo; Barabino, Gianluca; Raffo, Luigi

2013-02-01

Fetal electrocardiogram (ECG) extraction from non-invasive biopotential recordings is a long-standing research topic. Despite the significant number of algorithms presented in the scientific literature, it is difficult to find information about embedded hardware implementations able to provide real-time support for the required features, bridging the gap between theory and practice. This article presents the NInFEA (non-invasive fetal ECG analysis) tool, an embedded hardware/software framework based on the hybrid dual-core OMAP-L137 low-power processor for the real-time evaluation of fetal ECG extraction algorithms. The hybrid platform, including a digital signal processor (DSP) and a general-purpose processor (GPP), allows achieving the best performance compared with single-core architectures. The GPP provides a portable graphical user interface, whereas the DSP is extensively used for advanced signal processing tasks. As a case study, three state-of-the-art fetal ECG extraction algorithms have been ported onto NInFEA, along with some support routines needed to provide the additional information required by the clinicians and supported by the user interface. NInFEA can be regarded both as a reference design for similar applications and as a common embedded low-power testbed for real-time fetal ECG extraction algorithms.

Architecture for dynamically reconfigurable real-time lossless compression

Science.gov (United States)

Carter, Alison J.; Audsley, Neil C.

2004-05-01

Image compression is a computationally intensive task, which can be undertaken most efficiently by dedicated hardware. If a portable device is to carry out real-time compression on a variety of image types, then it may be useful to reconfigure the circuitry dynamically. Using commercial off-the shelf (COTS) chips, reconfiguration is usually implemented by a complete re-load from memory, but it is also possible to perform a partial reconfiguration. This work studies the use of programmable hardware devices to implement the lossless JPEG compression algorithm in real-time on a stream of independent image frames. The data rate is faster than can be compressed serially in hardware by a single processor, so the operation is split amongst several processors. These are implemented as programmable circuits, together with necessary buffering of input and output data. The timing of input and output, bearing in mind the different, and context-dependent amounts of data due to Huffman coding, is analyzed using storage-timing graphs. Because there may be differing parameters from one frame to the next, several different configurations are prepared and stored, ready to load as required. The scheduling of these reconfigurations, and the distribution/recombination of data streams is studied, giving an analysis of the real-time performance.

Model-based framework for multi-axial real-time hybrid simulation testing

Science.gov (United States)

Fermandois, Gaston A.; Spencer, Billie F.

2017-10-01

Real-time hybrid simulation is an efficient and cost-effective dynamic testing technique for performance evaluation of structural systems subjected to earthquake loading with rate-dependent behavior. A loading assembly with multiple actuators is required to impose realistic boundary conditions on physical specimens. However, such a testing system is expected to exhibit significant dynamic coupling of the actuators and suffer from time lags that are associated with the dynamics of the servo-hydraulic system, as well as control-structure interaction (CSI). One approach to reducing experimental errors considers a multi-input, multi-output (MIMO) controller design, yielding accurate reference tracking and noise rejection. In this paper, a framework for multi-axial real-time hybrid simulation (maRTHS) testing is presented. The methodology employs a real-time feedback-feedforward controller for multiple actuators commanded in Cartesian coordinates. Kinematic transformations between actuator space and Cartesian space are derived for all six-degrees-offreedom of the moving platform. Then, a frequency domain identification technique is used to develop an accurate MIMO transfer function of the system. Further, a Cartesian-domain model-based feedforward-feedback controller is implemented for time lag compensation and to increase the robustness of the reference tracking for given model uncertainty. The framework is implemented using the 1/5th-scale Load and Boundary Condition Box (LBCB) located at the University of Illinois at Urbana- Champaign. To demonstrate the efficacy of the proposed methodology, a single-story frame subjected to earthquake loading is tested. One of the columns in the frame is represented physically in the laboratory as a cantilevered steel column. For realtime execution, the numerical substructure, kinematic transformations, and controllers are implemented on a digital signal processor. Results show excellent performance of the maRTHS framework when six

Low-level processing for real-time image analysis

Science.gov (United States)

Eskenazi, R.; Wilf, J. M.

1979-01-01

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

Video rate morphological processor based on a redundant number representation

Science.gov (United States)

Kuczborski, Wojciech; Attikiouzel, Yianni; Crebbin, Gregory A.

1992-03-01

This paper presents a video rate morphological processor for automated visual inspection of printed circuit boards, integrated circuit masks, and other complex objects. Inspection algorithms are based on gray-scale mathematical morphology. Hardware complexity of the known methods of real-time implementation of gray-scale morphology--the umbra transform and the threshold decomposition--has prompted us to propose a novel technique which applied an arithmetic system without carrying propagation. After considering several arithmetic systems, a redundant number representation has been selected for implementation. Two options are analyzed here. The first is a pure signed digit number representation (SDNR) with the base of 4. The second option is a combination of the base-2 SDNR (to represent gray levels of images) and the conventional twos complement code (to represent gray levels of structuring elements). Operation principle of the morphological processor is based on the concept of the digit level systolic array. Individual processing units and small memory elements create a pipeline. The memory elements store current image windows (kernels). All operation primitives of processing units apply a unified direction of digit processing: most significant digit first (MSDF). The implementation technology is based on the field programmable gate arrays by Xilinx. This paper justified the rationality of a new approach to logic design, which is the decomposition of Boolean functions instead of Boolean minimization.

Linux real-time framework for fusion devices

Energy Technology Data Exchange (ETDEWEB)

Neto, Andre [Associacao Euratom-IST, Instituto de Plasmas e Fusao Nuclear, Av. Rovisco Pais, 1049-001 Lisboa (Portugal)], E-mail: andre.neto@cfn.ist.utl.pt; Sartori, Filippo; Piccolo, Fabio [Euratom-UKAEA, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Barbalace, Antonio [Euratom-ENEA Association, Consorzio RFX, 35127 Padova (Italy); Vitelli, Riccardo [Dipartimento di Informatica, Sistemi e Produzione, Universita di Roma, Tor Vergata, Via del Politecnico 1-00133, Roma (Italy); Fernandes, Horacio [Associacao Euratom-IST, Instituto de Plasmas e Fusao Nuclear, Av. Rovisco Pais, 1049-001 Lisboa (Portugal)

2009-06-15

A new framework for the development and execution of real-time codes is currently being developed and commissioned at JET. The foundations of the system are Linux, the Real Time Application Interface (RTAI) and a wise exploitation of the new i386 multi-core processors technology. The driving motivation was the need to find a real-time operating system for the i386 platform able to satisfy JET Vertical Stabilisation Enhancement project requirements: 50 {mu}s cycle time. Even if the initial choice was the VxWorks operating system, it was decided to explore an open source alternative, mostly because of the costs involved in the commercial product. The work started with the definition of a precise set of requirements and milestones to achieve: Linux distribution and kernel versions to be used for the real-time operating system; complete characterization of the Linux/RTAI real-time capabilities; exploitation of the multi-core technology; implementation of all the required and missing features; commissioning of the system. Latency and jitter measurements were compared for Linux and RTAI in both user and kernel-space. The best results were attained using the RTAI kernel solution where the time to reschedule a real-time task after an external interrupt is of 2.35 {+-} 0.35 {mu}s. In order to run the real-time codes in the kernel-space, a solution to provide user-space functionalities to the kernel modules had to be designed. This novel work provided the most common functions from the standard C library and transparent interaction with files and sockets to the kernel real-time modules. Kernel C++ support was also tested, further developed and integrated in the framework. The work has produced very convincing results so far: complete isolation of the processors assigned to real-time from the Linux non real-time activities, high level of stability over several days of benchmarking operations and values well below 3 {mu}s for task rescheduling after external interrupt. From

Linux real-time framework for fusion devices

International Nuclear Information System (INIS)

Neto, Andre; Sartori, Filippo; Piccolo, Fabio; Barbalace, Antonio; Vitelli, Riccardo; Fernandes, Horacio

2009-01-01

A new framework for the development and execution of real-time codes is currently being developed and commissioned at JET. The foundations of the system are Linux, the Real Time Application Interface (RTAI) and a wise exploitation of the new i386 multi-core processors technology. The driving motivation was the need to find a real-time operating system for the i386 platform able to satisfy JET Vertical Stabilisation Enhancement project requirements: 50 μs cycle time. Even if the initial choice was the VxWorks operating system, it was decided to explore an open source alternative, mostly because of the costs involved in the commercial product. The work started with the definition of a precise set of requirements and milestones to achieve: Linux distribution and kernel versions to be used for the real-time operating system; complete characterization of the Linux/RTAI real-time capabilities; exploitation of the multi-core technology; implementation of all the required and missing features; commissioning of the system. Latency and jitter measurements were compared for Linux and RTAI in both user and kernel-space. The best results were attained using the RTAI kernel solution where the time to reschedule a real-time task after an external interrupt is of 2.35 ± 0.35 μs. In order to run the real-time codes in the kernel-space, a solution to provide user-space functionalities to the kernel modules had to be designed. This novel work provided the most common functions from the standard C library and transparent interaction with files and sockets to the kernel real-time modules. Kernel C++ support was also tested, further developed and integrated in the framework. The work has produced very convincing results so far: complete isolation of the processors assigned to real-time from the Linux non real-time activities, high level of stability over several days of benchmarking operations and values well below 3 μs for task rescheduling after external interrupt. From being the

Evaluation of the Xeon phi processor as a technology for the acceleration of real-time control in high-order adaptive optics systems

Science.gov (United States)

Barr, David; Basden, Alastair; Dipper, Nigel; Schwartz, Noah; Vick, Andy; Schnetler, Hermine

2014-08-01

We present wavefront reconstruction acceleration of high-order AO systems using an Intel Xeon Phi processor. The Xeon Phi is a coprocessor providing many integrated cores and designed for accelerating compute intensive, numerical codes. Unlike other accelerator technologies, it allows virtually unchanged C/C++ to be recompiled to run on the Xeon Phi, giving the potential of making development, upgrade and maintenance faster and less complex. We benchmark the Xeon Phi in the context of AO real-time control by running a matrix vector multiply (MVM) algorithm. We investigate variability in execution time and demonstrate a substantial speed-up in loop frequency. We examine the integration of a Xeon Phi into an existing RTC system and show that performance improvements can be achieved with limited development effort.

First Results of an “Artificial Retina” Processor Prototype

International Nuclear Information System (INIS)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

2016-01-01

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

X-LUNA: Extending Free/Open Source Real Time Executive for On-Board Space Applications

Science.gov (United States)

Braga, P.; Henriques, L.; Zulianello, M.

2008-08-01

In this paper we present xLuna, a system based on the RTEMS [1] Real-Time Operating System that is able to run on demand a GNU/Linux Operating System [2] as RTEMS' lowest priority task. Linux runs in user-mode and in a different memory partition. This allows running Hard Real-Time tasks and Linux applications on the same system sharing the Hardware resources while keeping a safe isolation and the Real-Time characteristics of RTEMS. Communication between both Systems is possible through a loose coupled mechanism based on message queues. Currently only SPARC LEON2 processor with Memory Management Unit (MMU) is supported. The advantage in having two isolated systems is that non critical components are quickly developed or simply ported reducing time-to-market and budget.

Analyzing the effect of gain time on soft task scheduling policies in real-time systems

OpenAIRE

Búrdalo Rapa, Luis Antonio; Terrasa Barrena, Andrés Martín; Espinosa Minguet, Agustín Rafael; García Fornes, Ana María

2012-01-01

In hard real-time systems, gain time is defined as the difference between the Worst Case Execution Time (WCET) of a hard task and its actual processor consumption at runtime. This paper presents the results of an empirical study about how the presence of a significant amount of gain time in a hard real-time system questions the advantages of using the most representative scheduling algorithms or policies for aperiodic or soft tasks in fixed-priority preemptive systems. The work presented here...

Color sensor and neural processor on one chip

Science.gov (United States)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

Real-time inspection of metal laminates by means of CNNs

Science.gov (United States)

Preciado, Victor M.; Guinea, Domingo; Montufar-Chaveznava, Rodrigo; Vicente, Jose

2001-04-01

Analog CNN array computer arises as an alternative to traditional digital processors in many industrial inspection like visual quality control of metal laminants, capable of make in a single chip Tera equivalent operations per second. A 4096 analog CNN processor array is able to perform complex space-time image analysis, being much faster than a camera- computer system in continuous inspection applications. Both chips have been implemented in CMOS technology and they are managed by a 32-bit high-performance low-cost micro- controller that closes the pan, tilt, lighting, focus and zoom loops required in the implementation of the active vision strategies. Several convolution masks for the Cellular Processors has been selected to detect particular changes in the texture, size, direction or orientation of the image entities, reprogramming `on the fly' the pixel resolution of shape when necessary. Laboratory results present these Cellular Processors and multiple resolution imager circuits as a promising architecture for visual inspection of industrial processes in real time.

Real-time performance evaluation of media pipeline plug-in architectures

CSIR Research Space (South Africa)

Sentongo, VN

2011-09-01

Full Text Available Deployment of real-time applications has become ubiquitous in recent years. These applications (e.g. streaming video over the Internet) however, are processor intensive and require fast video-processing techniques for more flexible, efficient...

Approaching near real-time biosensing: microfluidic microsphere based biosensor for real-time analyte detection.

Science.gov (United States)

Cohen, Noa; Sabhachandani, Pooja; Golberg, Alexander; Konry, Tania

2015-04-15

In this study we describe a simple lab-on-a-chip (LOC) biosensor approach utilizing well mixed microfluidic device and a microsphere-based assay capable of performing near real-time diagnostics of clinically relevant analytes such cytokines and antibodies. We were able to overcome the adsorption kinetics reaction rate-limiting mechanism, which is diffusion-controlled in standard immunoassays, by introducing the microsphere-based assay into well-mixed yet simple microfluidic device with turbulent flow profiles in the reaction regions. The integrated microsphere-based LOC device performs dynamic detection of the analyte in minimal amount of biological specimen by continuously sampling micro-liter volumes of sample per minute to detect dynamic changes in target analyte concentration. Furthermore we developed a mathematical model for the well-mixed reaction to describe the near real time detection mechanism observed in the developed LOC method. To demonstrate the specificity and sensitivity of the developed real time monitoring LOC approach, we applied the device for clinically relevant analytes: Tumor Necrosis Factor (TNF)-α cytokine and its clinically used inhibitor, anti-TNF-α antibody. Based on the reported results herein, the developed LOC device provides continuous sensitive and specific near real-time monitoring method for analytes such as cytokines and antibodies, reduces reagent volumes by nearly three orders of magnitude as well as eliminates the washing steps required by standard immunoassays. Copyright © 2014 Elsevier B.V. All rights reserved.

Real-time on a standard UNIX workstation?

International Nuclear Information System (INIS)

Glanzman, T.

1992-09-01

This is a report of an ongoing R ampersand D project which is investigating the use of standard UNIX workstations for the real-time data acquisition from a major new experimental initiative, the SLAC B Factory (PEP II). For this work an IBM RS/6000 workstation running the AIX operating system is used. Real-time extensions to the UNIX operating system are explored and performance measured. These extensions comprise a set of AIX-specific and POSIX-compliant system services. Benchmark comparisons are made with embedded processor technologies. Results are presented for a simple prototype on-line system for laboratory-testing of a new prototype drift chamber

A fast inner product processor based on equal alignments

Energy Technology Data Exchange (ETDEWEB)

Smith, S.P.; Torng, H.C.

1985-11-01

Inner product computation is an important operation, invoked repeatedly in matrix multiplications. A high-speed inner product processor can be very useful (among many possible applications) in real-time signal processing. This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost. The inner product processor is implemented with a tree of carry-propagate or carry-save adders; this structure is obtained with the incorporation of three innovations in the conventional multiply/add tree: The leaf-multipliers are expanded into adder subtrees, thus achieving an O(log Nb) latency, where N denotes the number of elements in a vector and b the number of bits in each element. The partial products, to be summed in producing an inner product, are reordered according to their ''minimum alignments.'' This reordering brings approximately a 20% savings in hardware-including adders and data paths. The reduction in adder widths also yields savings in carry propagation time for carry-propagate adders. For trees implemented with carry-save adders, the partial product reordering also serves to truncate the carry propagation chain in the final propagation stage by 2 log b - 1 positions, thus significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.

Definition of an auxiliary processor dedicated to real-time operating system kernels

Science.gov (United States)

Halang, Wolfgang A.

1988-01-01

In order to increase the efficiency of process control data processing, it is necessary to enhance the productivity of real time high level languages and to automate the task administration, because presently 60 percent or more of the applications are still programmed in assembly languages. This may be achieved by migrating apt functions for the support of process control oriented languages into the hardware, i.e., by new architectures. Whereas numerous high level languages have already been defined or realized, there are no investigations yet on hardware assisted implementation of real time features. The requirements to be fulfilled by languages and operating systems in hard real time environment are summarized. A comparison of the most prominent languages, viz. Ada, HAL/S, LTR, Pearl, as well as the real time extensions of FORTRAN and PL/1, reveals how existing languages meet these demands and which features still need to be incorporated to enable the development of reliable software with predictable program behavior, thus making it possible to carry out a technical safety approval. Accordingly, Pearl proved to be the closest match to the mentioned requirements.

Real-Time Software for the Compass Tokamak Plasma Control

Energy Technology Data Exchange (ETDEWEB)

Valcarcel, D.F.; Duarte, A.S.; Neto, A.; Carvalho, I.S.; Carvalho, B.B.; Fernandes, H.; Sousa, J. [Instituto de Plasmas e Fusao Nuclear, Instituto Superior Tecnico, Lisboa (Portugal); Sartori, F. [Euratom-UKAEA, Culham Science Centre, Abingdon, OX14 3DB Oxon (United Kingdom); Janky, F.; Cahyna, P.; Hron, M.; Panek, R. [Institute of Plasma Physics AS CR, v.v.i., Association EURATOM / IPP.CR, Prague (Costa Rica)

2009-07-01

This poster presents the flexible and high-performance real time system that guarantees the desired time cycles for plasma control on the COMPASS tokamak: 500 {mu}s for toroidal field, current, equilibrium and shaping; 50 {mu}s for fast control of the equilibrium and vertical instability. This system was developed on top of a high-performance processor and a software framework (MARTe) tailored for real-time. The preliminary measurements indicate that the time constraints will be met on the final solution. The system allows the making of modifications in the future to improve software components. (A.C.)

A 16-channel real-time digital processor for pulse-shape discrimination in multiplicity assay

International Nuclear Information System (INIS)

Joyce, Malcolm J.; Aspinall, M.D.; Cave, F.D.; Lavietes, A.

2013-06-01

In recent years, real-time neutron/γ-ray pulse-shape discrimination has become feasible for use with scintillator-based detectors that respond extremely quickly, on the order of 25 ns in terms of pulse width, and their application to a variety of nuclear material assays has been reported. For the in-situ analysis of nuclear materials, measurements are often based on the multiplicity assessment of spontaneous fission events. An example of this is the 240 Pu eff assessment stemming from long-established techniques developed for 3 He-based neutron coincidence counters when 3 He was abundant and cheap. However, such measurements when using scintillator detectors can be plagued by low detection efficiencies and low orders of coincidence (often limited to triples) if the number of detectors in use is similarly limited to 3-4 detectors. Conversely, an array of >10 detector modules arranged to optimize efficiency and multiplicity sensitivity, shifts the emphasis in terms of performance requirement to the real-time digital analyzer and, critically, to the scope remaining in the temporal processing window of these systems. In this paper we report on the design, development and commissioning of a bespoke, 16-channel real-time pulse-shape discrimination analyzer specified for the materials assay challenge summarized above. The analyzer incorporates 16 dedicated and independent high-voltage supplies along with 16 independent digital processing channels offering pulse-shape discrimination at a rate of 3 x 10 6 events per second. These functions are configured from a dedicated graphical user interface, and all settings can be adjusted on-the-fly with the analyzer effectively configured one-time-only (where desired) for subsequent plug-and-play connection, for example to a fuel bundle organic scintillation detector array. (authors)

Real-time motional Stark effect in jet

International Nuclear Information System (INIS)

Alves, D.; Stephen, A.; Hawkes, N.; Dalley, S.; Goodyear, A.; Felton, R.; Joffrin, E.; Fernandes, H.

2004-01-01

The increasing importance of real-time measurements and control systems in JET experiments, regarding e.g. Internal Transport Barrier (ITB) and q-profile control, has motivated the development of a real-time motional Stark effect (MSE) system. The MSE diagnostic allows the measurement of local magnetic fields in different locations along the neutral beam path providing, therefore, local measurement of the current and q-profiles. Recently in JET, an upgrade of the MSE diagnostic has been implemented, incorporating a totally new system which allows the use of this diagnostic as a real-time control tool as well as an extended data source for off-line analysis. This paper will briefly describe the technical features of the real-time diagnostic with main focus on the system architecture, which consists of a VME crate hosting three PowerPC processor boards and a fast ADC, all connected via Front Panel Data Port (FPDP). The DSP algorithm implements a lockin-amplifier required to demodulate the JET MSE signals. Some applications for the system will be covered such as: feeding the real-time equilibrium reconstruction code (EQUINOX) and allowing the full coverage analysis of the Neutral Beam time window. A brief comparison between the real-time MSE analysis and the off-line analysis will also be presented

MARTe: A Multiplatform Real-Time Framework

Science.gov (United States)

Neto, André C.; Sartori, Filippo; Piccolo, Fabio; Vitelli, Riccardo; De Tommasi, Gianmaria; Zabeo, Luca; Barbalace, Antonio; Fernandes, Horacio; Valcarcel, Daniel F.; Batista, Antonio J. N.

2010-04-01

Development of real-time applications is usually associated with nonportable code targeted at specific real-time operating systems. The boundary between hardware drivers, system services, and user code is commonly not well defined, making the development in the target host significantly difficult. The Multithreaded Application Real-Time executor (MARTe) is a framework built over a multiplatform library that allows the execution of the same code in different operating systems. The framework provides the high-level interfaces with hardware, external configuration programs, and user interfaces, assuring at the same time hard real-time performances. End-users of the framework are required to define and implement algorithms inside a well-defined block of software, named Generic Application Module (GAM), that is executed by the real-time scheduler. Each GAM is reconfigurable with a set of predefined configuration meta-parameters and interchanges information using a set of data pipes that are provided as inputs and required as output. Using these connections, different GAMs can be chained either in series or parallel. GAMs can be developed and debugged in a non-real-time system and, only once the robustness of the code and correctness of the algorithm are verified, deployed to the real-time system. The software also supplies a large set of utilities that greatly ease the interaction and debugging of a running system. Among the most useful are a highly efficient real-time logger, HTTP introspection of real-time objects, and HTTP remote configuration. MARTe is currently being used to successfully drive the plasma vertical stabilization controller on the largest magnetic confinement fusion device in the world, with a control loop cycle of 50 ?s and a jitter under 1 ?s. In this particular project, MARTe is used with the Real-Time Application Interface (RTAI)/Linux operating system exploiting the new ?86 multicore processors technology.

Combining instruction prefetching with partial cache locking to improve WCET in real-time systems.

Directory of Open Access Journals (Sweden)

Fan Ni

Full Text Available Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.

Combining instruction prefetching with partial cache locking to improve WCET in real-time systems.

Science.gov (United States)

Ni, Fan; Long, Xiang; Wan, Han; Gao, Xiaopeng

2013-01-01

Caches play an important role in embedded systems to bridge the performance gap between fast processor and slow memory. And prefetching mechanisms are proposed to further improve the cache performance. While in real-time systems, the application of caches complicates the Worst-Case Execution Time (WCET) analysis due to its unpredictable behavior. Modern embedded processors often equip locking mechanism to improve timing predictability of the instruction cache. However, locking the whole cache may degrade the cache performance and increase the WCET of the real-time application. In this paper, we proposed an instruction-prefetching combined partial cache locking mechanism, which combines an instruction prefetching mechanism (termed as BBIP) with partial cache locking to improve the WCET estimates of real-time applications. BBIP is an instruction prefetching mechanism we have already proposed to improve the worst-case cache performance and in turn the worst-case execution time. The estimations on typical real-time applications show that the partial cache locking mechanism shows remarkable WCET improvement over static analysis and full cache locking.

Towards real-time communication between in vivo neurophysiological data sources and simulator-based brain biomimetic models.

Science.gov (United States)

Lee, Giljae; Matsunaga, Andréa; Dura-Bernal, Salvador; Zhang, Wenjie; Lytton, William W; Francis, Joseph T; Fortes, José Ab

2014-11-01

Development of more sophisticated implantable brain-machine interface (BMI) will require both interpretation of the neurophysiological data being measured and subsequent determination of signals to be delivered back to the brain. Computational models are the heart of the machine of BMI and therefore an essential tool in both of these processes. One approach is to utilize brain biomimetic models (BMMs) to develop and instantiate these algorithms. These then must be connected as hybrid systems in order to interface the BMM with in vivo data acquisition devices and prosthetic devices. The combined system then provides a test bed for neuroprosthetic rehabilitative solutions and medical devices for the repair and enhancement of damaged brain. We propose here a computer network-based design for this purpose, detailing its internal modules and data flows. We describe a prototype implementation of the design, enabling interaction between the Plexon Multichannel Acquisition Processor (MAP) server, a commercial tool to collect signals from microelectrodes implanted in a live subject and a BMM, a NEURON-based model of sensorimotor cortex capable of controlling a virtual arm. The prototype implementation supports an online mode for real-time simulations, as well as an offline mode for data analysis and simulations without real-time constraints, and provides binning operations to discretize continuous input to the BMM and filtering operations for dealing with noise. Evaluation demonstrated that the implementation successfully delivered monkey spiking activity to the BMM through LAN environments, respecting real-time constraints.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

Science.gov (United States)

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

A Survey of Real-Time Operating Systems and Virtualization Solutions for Space Systems

Science.gov (United States)

2015-03-01

x86, Xilinx, ARM, PIC, Freescale user, supervisor (PowerPC) ~5-10KB Use of hardware MPU on Cortex -M3 and ARM processors Priority based...unit (MPU) regions, but this requires the specific port of FreeRTOS 40 to run on processors that support an MPU such as the ARM Cortex -M3 (Real...paravirtualized version of FreeRTOS and supports Linux, RTEMS and µcos and is compatible with the ARM-9 and Cortex processors . X-Hyp is available under both

Memory controllers for high-performance and real-time MPSoCs : requirements, architectures, and future trends

NARCIS (Netherlands)

Akesson, K.B.; Huang, Po-Chun; Clermidy, F.; Dutoit, D.; Goossens, K.G.W.; Chang, Yuan-Hao; Kuo, Tei-Wei; Vivet, P.; Wingard, D.

2011-01-01

Designing memory controllers for complex real-time and high-performance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four

Design of a real-time wind turbine simulator using a custom parallel architecture

Science.gov (United States)

Hoffman, John A.; Gluck, R.; Sridhar, S.

1995-01-01

The design of a new parallel-processing digital simulator is described. The new simulator has been developed specifically for analysis of wind energy systems in real time. The new processor has been named: the Wind Energy System Time-domain simulator, version 3 (WEST-3). Like previous WEST versions, WEST-3 performs many computations in parallel. The modules in WEST-3 are pure digital processors, however. These digital processors can be programmed individually and operated in concert to achieve real-time simulation of wind turbine systems. Because of this programmability, WEST-3 is very much more flexible and general than its two predecessors. The design features of WEST-3 are described to show how the system produces high-speed solutions of nonlinear time-domain equations. WEST-3 has two very fast Computational Units (CU's) that use minicomputer technology plus special architectural features that make them many times faster than a microcomputer. These CU's are needed to perform the complex computations associated with the wind turbine rotor system in real time. The parallel architecture of the CU causes several tasks to be done in each cycle, including an IO operation and the combination of a multiply, add, and store. The WEST-3 simulator can be expanded at any time for additional computational power. This is possible because the CU's interfaced to each other and to other portions of the simulation using special serial buses. These buses can be 'patched' together in essentially any configuration (in a manner very similar to the programming methods used in analog computation) to balance the input/ output requirements. CU's can be added in any number to share a given computational load. This flexible bus feature is very different from many other parallel processors which usually have a throughput limit because of rigid bus architecture.

Performance enhancement of various real-time image processing techniques via speculative execution

Science.gov (United States)

Younis, Mohamed F.; Sinha, Purnendu; Marlowe, Thomas J.; Stoyenko, Alexander D.

1996-03-01

In real-time image processing, an application must satisfy a set of timing constraints while ensuring the semantic correctness of the system. Because of the natural structure of digital data, pure data and task parallelism have been used extensively in real-time image processing to accelerate the handling time of image data. These types of parallelism are based on splitting the execution load performed by a single processor across multiple nodes. However, execution of all parallel threads is mandatory for correctness of the algorithm. On the other hand, speculative execution is an optimistic execution of part(s) of the program based on assumptions on program control flow or variable values. Rollback may be required if the assumptions turn out to be invalid. Speculative execution can enhance average, and sometimes worst-case, execution time. In this paper, we target various image processing techniques to investigate applicability of speculative execution. We identify opportunities for safe and profitable speculative execution in image compression, edge detection, morphological filters, and blob recognition.

Research of real-time video processing system based on 6678 multi-core DSP

Science.gov (United States)

Li, Xiangzhen; Xie, Xiaodan; Yin, Xiaoqiang

2017-10-01

In the information age, the rapid development in the direction of intelligent video processing, complex algorithm proposed the powerful challenge on the performance of the processor. In this article, through the FPGA + TMS320C6678 frame structure, the image to fog, merge into an organic whole, to stabilize the image enhancement, its good real-time, superior performance, break through the traditional function of video processing system is simple, the product defects such as single, solved the video application in security monitoring, video, etc. Can give full play to the video monitoring effectiveness, improve enterprise economic benefits.

Scenario-based verification of real-time systems using UPPAAL

DEFF Research Database (Denmark)

Li, Shuhao; Belaguer, Sandie; David, Alexandre

2010-01-01

Abstract This paper proposes two approaches to tool-supported automatic verification of dense real-time systems against scenario-based requirements, where a system is modeled as a network of timed automata (TAs) or as a set of driving live sequence charts (LSCs), and a requirement is specified...... as a separate monitored LSC chart. We make timed extensions to a kernel subset of the LSC language and define a trace-based semantics. By translating a monitored LSC chart to a behavior-equivalent observer TA and then non-intrusively composing this observer with the original TA modeled real-time system......, the problem of scenario-based verification reduces to a computation tree logic (CTL) real-time model checking problem. In case the real time system is modeled as a set of driving LSC charts, we translate these driving charts and the monitored chart into a behavior-equivalent network of TAs by using a “one...

Design and realization of the real-time spectrograph controller for LAMOST based on FPGA

Science.gov (United States)

Wang, Jianing; Wu, Liyan; Zeng, Yizhong; Dai, Songxin; Hu, Zhongwen; Zhu, Yongtian; Wang, Lei; Wu, Zhen; Chen, Yi

2008-08-01

A large Schmitt reflector telescope, Large Sky Area Multi-Object Fiber Spectroscopic Telescope(LAMOST), is being built in China, which has effective aperture of 4 meters and can observe the spectra of as many as 4000 objects simultaneously. To fit such a large amount of observational objects, the dispersion part is composed of a set of 16 multipurpose fiber-fed double-beam Schmidt spectrographs, of which each has about ten of moveable components realtimely accommodated and manipulated by a controller. An industrial Ethernet network connects those 16 spectrograph controllers. The light from stars is fed to the entrance slits of the spectrographs with optical fibers. In this paper, we mainly introduce the design and realization of our real-time controller for the spectrograph, our design using the technique of System On Programmable Chip (SOPC) based on Field Programmable Gate Array (FPGA) and then realizing the control of the spectrographs through NIOSII Soft Core Embedded Processor. We seal the stepper motor controller as intellectual property (IP) cores and reuse it, greatly simplifying the design process and then shortening the development time. Under the embedded operating system μC/OS-II, a multi-tasks control program has been well written to realize the real-time control of the moveable parts of the spectrographs. At present, a number of such controllers have been applied in the spectrograph of LAMOST.

Real-time 3-D SAFT-UT system evaluation and validation

International Nuclear Information System (INIS)

Doctor, S.R.; Schuster, G.J.; Reid, L.D.; Hall, T.E.

1996-09-01

SAFT-UT technology is shown to provide significant enhancements to the inspection of materials used in US nuclear power plants. This report provides guidelines for the implementation of SAFT-UT technology and shows the results from its application. An overview of the development of SAFT-UT is provided so that the reader may become familiar with the technology. Then the basic fundamentals are presented with an extensive list of references. A comprehensive operating procedure, which is used in conjunction with the SAFT-UT field system developed by Pacific Northwest Laboratory (PNL), provides the recipe for both SAFT data acquisition and analysis. The specification for the hardware implementation is provided for the SAFT-UT system along with a description of the subsequent developments and improvements. One development of technical interest is the SAFT real time processor. Performance of the real-time processor is impressive and comparison is made of this dedicated parallel processor to a conventional computer and to the newer high-speed computer architectures designed for image processing. Descriptions of other improvements, including a robotic scanner, are provided. Laboratory parametric and application studies, performed by PNL and not previously reported, are discussed followed by a section on field application work in which SAFT was used during inservice inspections of operating reactors

Real-time 3-D SAFT-UT system evaluation and validation

Energy Technology Data Exchange (ETDEWEB)

Doctor, S.R.; Schuster, G.J.; Reid, L.D.; Hall, T.E. [Pacific Northwest National Lab., Richland, WA (United States)

1996-09-01

SAFT-UT technology is shown to provide significant enhancements to the inspection of materials used in US nuclear power plants. This report provides guidelines for the implementation of SAFT-UT technology and shows the results from its application. An overview of the development of SAFT-UT is provided so that the reader may become familiar with the technology. Then the basic fundamentals are presented with an extensive list of references. A comprehensive operating procedure, which is used in conjunction with the SAFT-UT field system developed by Pacific Northwest Laboratory (PNL), provides the recipe for both SAFT data acquisition and analysis. The specification for the hardware implementation is provided for the SAFT-UT system along with a description of the subsequent developments and improvements. One development of technical interest is the SAFT real time processor. Performance of the real-time processor is impressive and comparison is made of this dedicated parallel processor to a conventional computer and to the newer high-speed computer architectures designed for image processing. Descriptions of other improvements, including a robotic scanner, are provided. Laboratory parametric and application studies, performed by PNL and not previously reported, are discussed followed by a section on field application work in which SAFT was used during inservice inspections of operating reactors.

A real-time photogrammetry system based on embedded architecture

Directory of Open Access Journals (Sweden)

S. Y. Zheng

2014-06-01

Full Text Available In order to meet the demand of real-time spatial data processing and improve the online processing capability of photogrammetric system, a kind of real-time photogrammetry method is proposed in this paper. According to the proposed method, system based on embedded architecture is then designed: using FPGA, ARM+DSP and other embedded computing technology to build specialized hardware operating environment, transplanting and optimizing the existing photogrammetric algorithm to the embedded system, and finally real-time photogrammetric data processing is realized. At last, aerial photogrammetric experiment shows that the method can achieve high-speed and stable on-line processing of photogrammetric data. And the experiment also verifies the feasibility of the proposed real-time photogrammetric system based on embedded architecture. It is the first time to realize real-time aerial photogrammetric system, which can improve the online processing efficiency of photogrammetry to a higher level and broaden the application field of photogrammetry.

Method and apparatus for real-time measurement of fuel gas compositions and heating values

Science.gov (United States)

Zelepouga, Serguei; Pratapas, John M.; Saveliev, Alexei V.; Jangale, Vilas V.

2016-03-22

An exemplary embodiment can be an apparatus for real-time, in situ measurement of gas compositions and heating values. The apparatus includes a near infrared sensor for measuring concentrations of hydrocarbons and carbon dioxide, a mid infrared sensor for measuring concentrations of carbon monoxide and a semiconductor based sensor for measuring concentrations of hydrogen gas. A data processor having a computer program for reducing the effects of cross-sensitivities of the sensors to components other than target components of the sensors is also included. Also provided are corresponding or associated methods for real-time, in situ determination of a composition and heating value of a fuel gas.

Advanced real time radioscopy and computed tomography

International Nuclear Information System (INIS)

Sauerwein, Ch.; Nuding, W.; Grimm, R.; Wiacker, H.

1996-01-01

The paper describes three x-ray inspection systems. One radioscopic system is designed for the inspection of castings. The next integrates a radioscopic and a tomographic mode. The radioscopy has a high resolution camera and real time image processor. Radiation sources are a 450 kV industrial and a 200 kV microfocus tube. The third system is a tomographic system with 30 scintillation detectors for the inspection of nuclear waste containers. (author)

Real-time implementations of acoustic signal enhancement techniques for aerial based surveillance and rescue applications

Science.gov (United States)

Ramos, Antonio L. L.; Shao, Zhili; Holthe, Aleksander; Sandli, Mathias F.

2017-05-01

The introduction of the System-on-Chip (SoC) technology has brought exciting new opportunities for the development of smart low cost embedded systems spanning a wide range of applications. Currently available SoC devices are capable of performing high speed digital signal processing tasks in software while featuring relatively low development costs and reduced time-to-market. Unmanned aerial vehicles (UAV) are an application example that has shown tremendous potential in an increasing number of scenarios, ranging from leisure to surveillance as well as in search and rescue missions. Video capturing from UAV platforms is a relatively straightforward task that requires almost no preprocessing. However, that does not apply to audio signals, especially in cases where the data is to be used to support real-time decision making. In fact, the enormous amount of acoustic interference from the surroundings, including the noise from the UAVs propellers, becomes a huge problem. This paper discusses a real-time implementation of the NLMS adaptive filtering algorithm applied to enhancing acoustic signals captured from UAV platforms. The model relies on a combination of acoustic sensors and a computational inexpensive algorithm running on a digital signal processor. Given its simplicity, this solution can be incorporated into the main processing system of an UAV using the SoC technology, and run concurrently with other required tasks, such as flight control and communications. Simulations and real-time DSP-based implementations have shown significant signal enhancement results by efficiently mitigating the interference from the noise generated by the UAVs propellers as well as from other external noise sources.

Extensions to the Parallel Real-Time Artificial Intelligence System (PRAIS) for fault-tolerant heterogeneous cycle-stealing reasoning

Science.gov (United States)

Goldstein, David

1991-01-01

Extensions to an architecture for real-time, distributed (parallel) knowledge-based systems called the Parallel Real-time Artificial Intelligence System (PRAIS) are discussed. PRAIS strives for transparently parallelizing production (rule-based) systems, even under real-time constraints. PRAIS accomplished these goals (presented at the first annual C Language Integrated Production System (CLIPS) conference) by incorporating a dynamic task scheduler, operating system extensions for fact handling, and message-passing among multiple copies of CLIPS executing on a virtual blackboard. This distributed knowledge-based system tool uses the portability of CLIPS and common message-passing protocols to operate over a heterogeneous network of processors. Results using the original PRAIS architecture over a network of Sun 3's, Sun 4's and VAX's are presented. Mechanisms using the producer-consumer model to extend the architecture for fault-tolerance and distributed truth maintenance initiation are also discussed.

Reconfigurable signal processor designs for advanced digital array radar systems

Science.gov (United States)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

A study of real-time content marketing : formulating real-time content marketing based on content, search and social media

OpenAIRE

Nguyen, Thi Kim Duyen

2015-01-01

The primary objective of this research is to understand profoundly the new concept of content marketing – real-time content marketing on the aspect of the digital marketing experts. Particularly, the research will focus on the real-time content marketing theories and how to build real-time content marketing strategy based on content, search and social media. It also finds out how marketers measure and keep track of conversion rates of their real-time content marketing plan. Practically, th...

Online Fastbus processor for LEP

International Nuclear Information System (INIS)

Mueller, H.

1986-01-01

The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

Development and implementation of real-time data acquisition systems for fusion devices with Open Source software

International Nuclear Information System (INIS)

Zilker, M.; Behler, K.; Bluhm, T.; Heimann, P.; Hennig, Ch.; Kroiss, H.; Kuehner, G.; Laqua, H.; Lewerentz, M.; Maier, J.; Neu, G.; Raupp, G.; Reich, M.; Riemann, H.; Schacht, J.; Spring, A.; Treutterer, W.; Werner, A.; Zehetbauer, T.

2010-01-01

To improve the plasma position and shape control system in ASDEX Upgrade, it is constantly expanded by the integration of data acquisition systems of important and interesting diagnostics. Usually the main responsibility of data acquisition systems is to collect data and subsequently put it into a data base archive system from where it is later analysed. The obligation now is also to simultaneously process the acquired data with an appropriate algorithm and send the pre-processed data in real-time to the plasma control system during a discharge. To achieve this requirements the used hardware must provide enough processing power and the operating system has to meet some real-time constraints. To avoid the burden of using proprietary real-time operating systems the trend is to use Open Source variants mainly based on Linux. Some of these solutions also allow us doing real-time capable communication using standard Ethernet hardware. By way of an example the implementation process of a prototype of a real-time data acquisition system based on a multi-core processor and Xenomai is demonstrated. Other possible solutions like Realtime Linux and their differences to Xenomai which we propose as the most sophisticated real-time framework for Linux are discussed in this paper.

FPGA-based real-time embedded system for RISS/GPS integrated navigation.

Science.gov (United States)

Abdelfatah, Walid Farid; Georgy, Jacques; Iqbal, Umar; Noureldin, Aboelmagd

2012-01-01

Navigation algorithms integrating measurements from multi-sensor systems overcome the problems that arise from using GPS navigation systems in standalone mode. Algorithms which integrate the data from 2D low-cost reduced inertial sensor system (RISS), consisting of a gyroscope and an odometer or wheel encoders, along with a GPS receiver via a Kalman filter has proved to be worthy in providing a consistent and more reliable navigation solution compared to standalone GPS receivers. It has been also shown to be beneficial, especially in GPS-denied environments such as urban canyons and tunnels. The main objective of this paper is to narrow the idea-to-implementation gap that follows the algorithm development by realizing a low-cost real-time embedded navigation system capable of computing the data-fused positioning solution. The role of the developed system is to synchronize the measurements from the three sensors, relative to the pulse per second signal generated from the GPS, after which the navigation algorithm is applied to the synchronized measurements to compute the navigation solution in real-time. Employing a customizable soft-core processor on an FPGA in the kernel of the navigation system, provided the flexibility for communicating with the various sensors and the computation capability required by the Kalman filter integration algorithm.

System-level power optimization for real-time distributed embedded systems

Science.gov (United States)

Luo, Jiong

Power optimization is one of the crucial design considerations for modern electronic systems. In this thesis, we present several system-level power optimization techniques for real-time distributed embedded systems, based on dynamic voltage scaling, dynamic power management, and management of peak power and variance of the power profile. Dynamic voltage scaling has been widely acknowledged as an important and powerful technique to trade off dynamic power consumption and delay. Efficient dynamic voltage scaling requires effective variable-voltage scheduling mechanisms that can adjust voltages and clock frequencies adaptively based on workloads and timing constraints. For this purpose, we propose static variable-voltage scheduling algorithms utilizing criticalpath driven timing analysis for the case when tasks are assumed to have uniform switching activities, as well as energy-gradient driven slack allocation for a more general scenario. The proposed techniques can achieve closeto-optimal power savings with very low computational complexity, without violating any real-time constraints. We also present algorithms for power-efficient joint scheduling of multi-rate periodic task graphs along with soft aperiodic tasks. The power issue is addressed through both dynamic voltage scaling and power management. Periodic task graphs are scheduled statically. Flexibility is introduced into the static schedule to allow the on-line scheduler to make local changes to PE schedules through resource reclaiming and slack stealing, without interfering with the validity of the global schedule. We provide a unified framework in which the response times of aperiodic tasks and power consumption are dynamically optimized simultaneously. Interconnection network fabrics point to a new generation of power-efficient and scalable interconnection architectures for distributed embedded systems. As the system bandwidth continues to increase, interconnection networks become power/energy limited as

A Real-Time Image Acquisition And Processing System For A RISC-Based Microcomputer

Science.gov (United States)

Luckman, Adrian J.; Allinson, Nigel M.

1989-03-01

A low cost image acquisition and processing system has been developed for the Acorn Archimedes microcomputer. Using a Reduced Instruction Set Computer (RISC) architecture, the ARM (Acorn Risc Machine) processor provides instruction speeds suitable for image processing applications. The associated improvement in data transfer rate has allowed real-time video image acquisition without the need for frame-store memory external to the microcomputer. The system is comprised of real-time video digitising hardware which interfaces directly to the Archimedes memory, and software to provide an integrated image acquisition and processing environment. The hardware can digitise a video signal at up to 640 samples per video line with programmable parameters such as sampling rate and gain. Software support includes a work environment for image capture and processing with pixel, neighbourhood and global operators. A friendly user interface is provided with the help of the Archimedes Operating System WIMP (Windows, Icons, Mouse and Pointer) Manager. Windows provide a convenient way of handling images on the screen and program control is directed mostly by pop-up menus.

General purpose computers in real time

International Nuclear Information System (INIS)

Biel, J.R.

1989-01-01

I see three main trends in the use of general purpose computers in real time. The first is more processing power. The second is the use of higher speed interconnects between computers (allowing more data to be delivered to the processors). The third is the use of larger programs running in the computers. Although there is still work that needs to be done, I believe that all indications are that the online need for general purpose computers should be available for the SCC and LHC machines. 2 figs

Recommending the heterogeneous cluster type multi-processor system computing

International Nuclear Information System (INIS)

Iijima, Nobukazu

2010-01-01

Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

Graphics processing unit accelerated intensity-based optical coherence tomography angiography using differential frames with real-time motion correction.

Science.gov (United States)

Watanabe, Yuuki; Takahashi, Yuhei; Numazawa, Hiroshi

2014-02-01

We demonstrate intensity-based optical coherence tomography (OCT) angiography using the squared difference of two sequential frames with bulk-tissue-motion (BTM) correction. This motion correction was performed by minimization of the sum of the pixel values using axial- and lateral-pixel-shifted structural OCT images. We extract the BTM-corrected image from a total of 25 calculated OCT angiographic images. Image processing was accelerated by a graphics processing unit (GPU) with many stream processors to optimize the parallel processing procedure. The GPU processing rate was faster than that of a line scan camera (46.9 kHz). Our OCT system provides the means of displaying structural OCT images and BTM-corrected OCT angiographic images in real time.

Operating system for a real-time multiprocessor propulsion system simulator

Science.gov (United States)

Cole, G. L.

1984-01-01

The success of the Real Time Multiprocessor Operating System (RTMPOS) in the development and evaluation of experimental hardware and software systems for real time interactive simulation of air breathing propulsion systems was evaluated. The Real Time Multiprocessor Operating System (RTMPOS) provides the user with a versatile, interactive means for loading, running, debugging and obtaining results from a multiprocessor based simulator. A front end processor (FEP) serves as the simulator controller and interface between the user and the simulator. These functions are facilitated by the RTMPOS which resides on the FEP. The RTMPOS acts in conjunction with the FEP's manufacturer supplied disk operating system that provides typical utilities like an assembler, linkage editor, text editor, file handling services, etc. Once a simulation is formulated, the RTMPOS provides for engineering level, run time operations such as loading, modifying and specifying computation flow of programs, simulator mode control, data handling and run time monitoring. Run time monitoring is a powerful feature of RTMPOS that allows the user to record all actions taken during a simulation session and to receive advisories from the simulator via the FEP. The RTMPOS is programmed mainly in PASCAL along with some assembly language routines. The RTMPOS software is easily modified to be applicable to hardware from different manufacturers.

SCI-Clone/32 - a distributed real time simulation system

International Nuclear Information System (INIS)

Wilks, C.F.

1986-01-01

Advances in engineering and in particular digital computers has enabled the simulation manufacturers to deliver a realism of a kind undreamt of a decade ago. 32-bit computers ranging in processor power from several hundred thousand instructions per second to many millions are at the heart of each simulator. Gould has pioneered digital computers in simulation with real time systems using shared memory, parallel processors, 64KByte cache, and shadow memory. The market is planning for higher iteration rates, lower life cycle costs, and the development of part task products. These can be met by distributing the tasks amongst nodal computers having a unique architecture for sharing data variables with minimal contention. (Auth.)

Thermal Dissipation Efficiency in a Micro-Processor Using Carbon Nanotubes Based Composite

Science.gov (United States)

Thang, Bui Hung; Van Quang, Cao; Nghia, Van Trong; Hong, Phan Ngoc; Van Chuc, Nguyen; Tam, Ngo Thi Thanh; Quang, Le Dinh; Khang, Dao Duc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

Modern electronic and optoelectronic devices such as μ-processor, light emitting diode, semiconductor laser issued a challenge in the thermal dissipation problem. Finding an effective way for thermal dissipation therefore becomes a very important issue. It is known that carbon nanotubes (CNTs) is one of the most valuable materials with high thermal conductivity (2000 W/m.K compared to thermal conductivity of Ag 419 W/m.K). This suggested an approach in applying the CNTs as an essential component for thermal dissipation media to improve the performance of computer processor and other high power electronic devices. In this work multi walled carbon nanotubes (MWCNTs) based composites were utilized as the thermal dissipation media in a micro processor of a personal computer. The MWCNTs of different concentrations were added into polyaniline, commercial silicon thermal paste and commercial silver thermal paste by mechanical methods. A personal computer with configuration: Intel Pentium IV 3.066 GHz, 512 MB of RAM and Windows XP Service Pack 2 Operating System was employed. The thermal dissipation efficiency of the system was evaluated by directly measure the temperature of the μ-processor during the operation of the computer in different CPU speeds. The measured results showed that the CNTs based composite could reduce the temperature of the u-processor more than 5° C, and the time for increasing the temperature of the μ-processor was three times longer than that when using commercial thermal paste.

Real-time digital control, data acquisition, and analysis system for the DIII-D multipulse Thomson scattering diagnostic

International Nuclear Information System (INIS)

Greenfield, C.M.; Campbell, G.L.; Carlstrom, T.N.; DeBoo, J.C.; Hsieh, C.; Snider, R.T.; Trost, P.K.

1990-01-01

A VME-based real-time computer system for laser control, data acquisition, and analysis for the DIII-D multipulse Thomson scattering diagnostic is described. The laser control task requires precise timing of up to eight Nd:YAG lasers, each with an average firing rate of 20 Hz. A cpu module in a real-time multiprocessing computer system will operate the lasers with evenly staggered laser pulses or in a ''burst mode,'' where all available (fully charged) lasers can be fired at 50--100 μs intervals upon receipt of an external event trigger signal. One or more cpu modules, along with a LeCroy FERA (fast encoding and readout ADC) system, will perform real-time data acquisition and analysis. Partial electron temperature and density profiles will be available for plasma feedback control within 1 ms following each laser pulse. The VME-based computer system consists of two or more target processor modules (25 MHz Motorola 68030) running the VMEexec real-time operating system connected to a Unix-based host system (also a 68030). All real-time software is fully interrupt driven to maximize system efficiency. Operator interaction and (non-real-time) data analysis takes place on a MicroVAX 3400 connected via DECnet

On the design of a real-time volume rendering engine

NARCIS (Netherlands)

Smit, Jaap; Wessels, H.L.F.; van der Horst, A.; Bentum, Marinus Jan

1992-01-01

An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator

On the design of a real-time volume rendering engine

NARCIS (Netherlands)

Smit, Jaap; Wessels, H.J.; van der Horst, A.; Bentum, Marinus Jan

1995-01-01

An architecture for a Real-Time Volume Rendering Engine (RT-VRE) is given, capable of computing 750 × 750 × 512 samples from a 3D dataset at a rate of 25 images per second. The RT-VRE uses for this purpose 64 dedicated rendering chips, cooperating with 16 RISC-processors. A plane interpolator

Design and development of FPGA based TCP/IP module for real time computers in nuclear power plants

International Nuclear Information System (INIS)

Balasri, G. Janani; Santhana Raj, A.; Gour, Aditya; Murali, N.; Manikandan, J.

2013-01-01

An VME (Virtual Module Europa) bus based Real Time Computer's (RTC's) are being developed for Prototype Fast Breeder Reactor (PFBR) which is in an advanced stage of construction at Kalpakkam, where the RTC's have to communicate to the central process computer on the data collected from the field instrument and receive data from the central process computer. A Distributed Digital Control System (DDSC) architecture has been designed for this communication which is based on Transfer Communication Protocol/Internet Protocol (TCP/IP) over Ethernet. Currently the RTC's uses 'Wiznet Module', a bought out chip which implements the TCP/IP stack in hardware. This project concentrates on the design and development of Field Programmable Gate Array (FPGA) based TCP/IP module that runs on Microblaze, a 32-bit softcore processor, to take care of the communication as that of Wiznet module. Advantage of switching over to FPGA based system are its reconfigurability, desired number of sockets, and the design is stable even if the FPGA's get obsolete. (author)

Improved Real-time Denoising Method Based on Lifting Wavelet Transform

Directory of Open Access Journals (Sweden)

Liu Zhaohua

2014-06-01

Full Text Available Signal denoising can not only enhance the signal to noise ratio (SNR but also reduce the effect of noise. In order to satisfy the requirements of real-time signal denoising, an improved semisoft shrinkage real-time denoising method based on lifting wavelet transform was proposed. The moving data window technology realizes the real-time wavelet denoising, which employs wavelet transform based on lifting scheme to reduce computational complexity. Also hyperbolic threshold function and recursive threshold computing can ensure the dynamic characteristics of the system, in addition, it can improve the real-time calculating efficiency as well. The simulation results show that the semisoft shrinkage real-time denoising method has quite a good performance in comparison to the traditional methods, namely soft-thresholding and hard-thresholding. Therefore, this method can solve more practical engineering problems.

A knowledge-based system framework for real-time monitoring applications

International Nuclear Information System (INIS)

Heaberlin, J.O.; Robinson, A.H.

1989-01-01

A real-time environment presents a challenge for knowledge-based systems for process monitoring with on-line data acquisition in nuclear power plants. These applications are typically data intensive. This, coupled with the dynamic nature of events on which problematic decisions are based, requires the development of techniques fundamentally different from those generally employed. Traditional approaches involve knowledge management techniques developed for static data, the majority of which is elicited directly from the user in a consultation environment. Inference mechanisms are generally noninterruptible, requiring all appropriate rules to be fired before new data can be accommodated. As a result, traditional knowledge-based applications in real-time environments have inherent problems in dealing with the time dependence of both the data and the solution process. For example, potential problems include obtaining a correct solution too late to be of use or focusing computing resources on problems that no longer exist. A knowledge-based system framework, the real-time framework (RTF), has been developed that can accommodate the time dependencies and resource trade-offs required for real-time process monitoring applications. This framework provides real-time functionality by using generalized problem-solving goals and control strategies that are modifiable during system operation and capable of accommodating feedback for redirection of activities

A data base processor semantics specification package

Science.gov (United States)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

X-real-time executive (X-RTE) an ultra-high reliable real-time executive for safety critical systems

International Nuclear Information System (INIS)

Suresh Babu, R.M.

1995-01-01

With growing number of application of computers in safety critical systems of nuclear plants there has been a need to assure high quality and reliability of the software used in these systems. One way to assure software quality is to use qualified software components. Since the safety systems and control systems are real-time systems there is a need for a real-time supervisory software to guarantee temporal response of the system. This report describes one such software package, called X-Real-Time Executive (or X-RTE), which was developed in Reactor Control Division, BARC. The report describes all the capabilities and unique features of X-RTE and compares it with a commercially available operating system. The features of X-RTE include pre-emptive scheduling, process synchronization, inter-process communication, multi-processor support, temporal support, debug facility, high portability, high reliability, high quality, and extensive documentation. Examples have been used very liberally to illustrate the underlying concepts. Besides, the report provides a brief description about the methods used, during the software development, to assure high quality and reliability of X-RTE. (author). refs., 11 figs., tabs

Progress in real-time feedback control systems in RFX

Energy Technology Data Exchange (ETDEWEB)

Barana, O.; Luchetta, A. E-mail: adriano.luchetta@igi.cnr.it; Manduchi, G.; Taliercio, C

2004-06-01

Major modifications of the RFX load assembly and power supplies are in progress to allow extensive active control schemes, such as equilibrium and plasma position control and innovative control of the MHD modes. The digital control system is implemented in VME64 using a distributed architecture. The use of a 'stable' operating system that is likely to survive some generations of processors can help coping with evolution of technology. PowerPC and Pentium processors were thus considered as candidates and tested and the first one has been selected due to the better performance in floating point computation. Wind River VxWorks has been chosen as real-time operating system. 100 Mbit switched Ethernet has been evaluated for real-time communication by using the user datagram protocol (UDP). Measurements have been executed on a prototype system to assess data transfer latency, jitter and reliability and the results confirm that the solution is suitable for the application. The paper describes in detail the reasons for the choice in the hardware components. Results from several tests comparing the performance of different solutions are also provided.

Timing Analysis of Mixed-Criticality Hard Real-Time Applications Implemented on Distributed Partitioned Architectures

DEFF Research Database (Denmark)

Marinescu, Sorin Ovidiu; Tamas-Selicean, Domitian; Acretoaie, Vlad

In this paper we are interested in the timing analysis of mixed-criticality embedded real-time applications mapped on distributed heterogeneous architectures. Mixedcriticality tasks can be integrated onto the same architecture only if there is enough spatial and temporal separation among them. We...... in partitions using fixedpriority preemptive scheduling. We have extended the stateof- the-art algorithms for schedulability analysis to take into account the partitions. The proposed algorithm has been evaluated using several synthetic and real-life benchmarks....... consider that the separation is provided by partitioning, such that applications run in separate partitions, and each partition is allocated several time slots on a processor. Each partition can have its own scheduling policy. We are interested to determine the worst-case response times of tasks scheduled...

DSPACE Real-Time Implementation of MPPT-Based FLC Method

Directory of Open Access Journals (Sweden)

Abdullah M. Noman

2013-01-01

Full Text Available Maximum power point trackers are so important in photovoltaic systems to improve their overall efficiency. This paper presents a photovoltaic system with maximum power point tracking facility. An intelligent fuzzy logic controller method is proposed in this paper to achieve the maximum power point tracking of PV modules. The system consists of a photovoltaic solar module connected to a DC-DC buck-boost converter. The system is modeled using MATLAB/SIMULINK. The system has been experienced under disturbance in the photovoltaic temperature and irradiation levels. The simulation results show that the proposed maximum power tracker tracks the maximum power accurately and successfully in all conditions tested. The MPPT system is then experimentally implemented. DSPACE is used in the implementation of the MPPT hardware setup for real-time control. Data acquisition and control system is implemented using dSPACE 1104 software and digital signal processor card. The simulation and practical results show that the proposed system tracked the maximum power accurately and successfully under all atmospheric conditions.

The Case For Prediction-based Best-effort Real-time Systems.

Science.gov (United States)

1999-01-01

Real - time Systems Peter A. Dinda Loukas Kallivokas January...DISTRIBUTION STATEMENT A Approved for Public Release Distribution Unlimited DTIG QUALBR DISSECTED X The Case For Prediction-based Best-effort Real - time Systems Peter...Mellon University Pittsburgh, PA 15213 A version of this paper appeared in the Seventh Workshop on Parallel and Distributed Real - Time Systems

Securing Real-Time Sessions in an IMS-Based Architecture

Science.gov (United States)

Cennamo, Paolo; Fresa, Antonio; Longo, Maurizio; Postiglione, Fabio; Robustelli, Anton Luca; Toro, Francesco

The emerging all-IP mobile network infrastructures based on 3rd Generation IP Multimedia Subsystem philosophy are characterised by radio access technology independence and ubiquitous connectivity for mobile users. Currently, great focus is being devoted to security issues since most of the security threats presently affecting the public Internet domain, and the upcoming ones as well, are going to be suffered by mobile users in the years to come. While a great deal of research activity, together with standardisation efforts and experimentations, is carried out on mechanisms for signalling protection, very few integrated frameworks for real-time multimedia data protection have been proposed in a context of IP Multimedia Subsystem, and even fewer experimental results based on testbeds are available. In this paper, after a general overview of the security issues arising in an advanced IP Multimedia Subsystem scenario, a comprehensive infrastructure for real-time multimedia data protection, based on the adoption of the Secure Real-Time Protocol, is proposed; then, the development of a testbed incorporating such functionalities, including mechanisms for key management and cryptographic context transfer, and allowing the setup of Secure Real-Time Protocol sessions is presented; finally, experimental results are provided together with quantitative assessments and comparisons of system performances for audio sessions with and without the adoption of the Secure Real-Time Protocol framework.

Real-time particle image velocimetry based on FPGA technology

International Nuclear Information System (INIS)

Iriarte Munoz, Jose Miguel

2008-01-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach. [es

A high performance load balance strategy for real-time multicore systems.

Science.gov (United States)

Cho, Keng-Mao; Tsai, Chun-Wei; Chiu, Yi-Shiuan; Yang, Chu-Sing

2014-01-01

Finding ways to distribute workloads to each processor core and efficiently reduce power consumption is of vital importance, especially for real-time systems. In this paper, a novel scheduling algorithm is proposed for real-time multicore systems to balance the computation loads and save power. The developed algorithm simultaneously considers multiple criteria, a novel factor, and task deadline, and is called power and deadline-aware multicore scheduling (PDAMS). Experiment results show that the proposed algorithm can greatly reduce energy consumption by up to 54.2% and the deadline times missed, as compared to the other scheduling algorithms outlined in this paper.

3081/E processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.

1984-04-01

The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

The processor farm for online triggering and full event reconstruction of the HERA-B experiment at HERA

International Nuclear Information System (INIS)

Gellrich, A.; Dippel, R.; Gensch, U.; Kowallik, R.; Legrand, I.C.; Leich, H.; Sun, F.; Wegner, P.

1996-01-01

The main goal of the HERA-B experiment which start taking data in 1988 is to study CP violation in B decays. This article describes the concept and the planned implementation of a multi-processor system, called processor farm,as the last part of the data acquisition and trigger system of the HERA B experiment. The third level trigger task and a full online event reconstruction will be performed on this processor farm, consisting of more then 100 powerful RISC processors which are based on commercial hardware boards. The controlling will be done by a real-time operating system which provides a software development environment, including FORTRAN and C compilers. (author)

FPGA based image processing for optical surface inspection with real time constraints

Science.gov (United States)

Hasani, Ylber; Bodenstorfer, Ernst; Brodersen, Jörg; Mayer, Konrad J.

2015-02-01

Today, high-quality printing products like banknotes, stamps, or vouchers, are automatically checked by optical surface inspection systems. In a typical optical surface inspection system, several digital cameras acquire the printing products with fine resolution from different viewing angles and at multiple wavelengths of the visible and also near infrared spectrum of light. The cameras deliver data streams with a huge amount of image data that have to be processed by an image processing system in real time. Due to the printing industry's demand for higher throughput together with the necessity to check finer details of the print and its security features, the data rates to be processed tend to explode. In this contribution, a solution is proposed, where the image processing load is distributed between FPGAs and digital signal processors (DSPs) in such a way that the strengths of both technologies can be exploited. The focus lies upon the implementation of image processing algorithms in an FPGA and its advantages. In the presented application, FPGAbased image-preprocessing enables real-time implementation of an optical color surface inspection system with a spatial resolution of 100 μm and for object speeds over 10 m/s. For the implementation of image processing algorithms in the FPGA, pipeline parallelism with clock frequencies up to 150 MHz together with spatial parallelism based on multiple instantiations of modules for parallel processing of multiple data streams are exploited for the processing of image data of two cameras and three color channels. Due to their flexibility and their fast response times, it is shown that FPGAs are ideally suited for realizing a configurable all-digital PLL for the processing of camera line-trigger signals with frequencies about 100 kHz, using pure synchronous digital circuit design.

A real-time digital control, data acquisition and analysis system for the DIII-D multipulse Thomson scattering diagnostic

International Nuclear Information System (INIS)

Greenfield, C.M.; Campbell, G.L.; Carlstrom, T.N.; DeBoo, J.C.; Hsieh, C.-L.; Snider, R.T.; Trost, P.K.

1990-10-01

A VME-based real-time computer systems for laser control, data acquisition and analysis for the DIII-D multipulse Thomson scattering diagnostic is described. The laser control task requires precise timing of up to 8 Nd:YAG lasers, each with an average firing rate of 20 Hz. A cpu module in real-time multiprocessing computer system will operate the lasers with evenly staggered laser pulses or in a ''burst mode'', where all available (fully charged) lasers can be fired at 50--100 μsec intervals upon receipt of an external event trigger signal. One of more cpu modules, along with a LeCroy FERA (Fast Encoding and Readout ADC) system, will perform real-time data acquisition and analysis. Partial electron temperature and density profiles will be available for plasma feedback control within 1 msec following each laser pulse. The VME-based computer system consists of 2 or more target processor modules (25 MHz Motorola 68030) running the VMEexec real-time operating system connected to a Unix based host system (also a 68030). All real-time software is fully interrupt driven to maximize system efficiency. Operator interaction and (non real-time) data analysis takes place on a MicroVAX 3400 connected via DECnet. 17 refs., 1 fig

Hardware processors for pattern recognition tasks in experiments with wire chambers

International Nuclear Information System (INIS)

Verkerk, C.

1975-01-01

Hardware processors for pattern recognition tasks in experiments with multiwire proportional chambers or drift chambers are described. They vary from simple ones used for deciding in real time if particle trajectories are straight to complex ones for recognition of curved tracks. Schematics and block-diagrams of different processors are shown

Time synchronization for an Ethernet-based real-time token network

NARCIS (Netherlands)

Hanssen, F.T.Y.; van den Boom, Joost; Jansen, P.G.; Scholten, Johan

We present a distributed clock synchronization algorithm. It performs clock synchronization on an Ethernet-based real-time token local area network, without the use of an external clock source. It is used to enable the token schedulers in each node to agree upon a common time. Its intended use is in

Continuous data recording on fast real-time systems

Energy Technology Data Exchange (ETDEWEB)

Zabeo, L., E-mail: lzabeo@jet.u [Euratom-CCFE, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Sartori, F. [Euratom-CCFE, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Neto, A. [Associacao Euratom-IST, Instituto de Plasmas e Fusao Nuclear, Av. Rovisco Pais, 1049-001 Lisboa (Portugal); Piccolo, F. [Euratom-CCFE, Culham Science Centre, Abingdon, Oxon OX14 3DB (United Kingdom); Alves, D. [Associacao Euratom-IST, Instituto de Plasmas e Fusao Nuclear, Av. Rovisco Pais, 1049-001 Lisboa (Portugal); Vitelli, R. [Dipartimento di Informatica, Sistemi e Produzione, Universita di Roma, Tor Vergata, Via del Politecnico, 1-00133 Roma (Italy); Barbalace, A. [Euratom-ENEA Association, Consorzio RFX, 35127 Padova (Italy); De Tommasi, G. [Associazione EURATOM/ENEA/CREATE, Universita di Napoli Federico II, Napoli (Italy)

2010-07-15

The PCU-Project launched for the enhancement of the vertical stabilisation system at JET required the design of a new real-time control system with the challenging specifications of 2Gops and a cycle time of 50 {mu}s. The RTAI based architecture running on an x86 multi-core processor technology demonstrated to be the best platform for meeting the high requirements. Moreover, on this architecture thanks to the smart allocation of the interrupts it was possible to demonstrate simultaneous data streaming at 50 MBs on Ethernet while handling a real-time 100 kHz interrupt source with a maximum jitter of just 3 {mu}s. Because of the memory limitation imposed by 32 bit version Linux running in kernel mode, the RTAI-based new controller allows a maximum practical data storage of 800 MB per pulse. While this amount of data can be accepted for JET normal operation it posed some limitations in the debugging and commissioning of the system. In order to increase the capability of the data acquisition of the system we have designed a mechanism that allows continuous full bandwidth (56 MB/s) data streaming from the real-time task (running in kernel mode) to either a data collector (running in user mode) or an external data acquisition server. The exploited architecture involves a peer to peer mechanisms where the sender running in RTAI kernel mode broadcasts large chunks of data using UDP packets, implemented using the 'fcomm' RTAI extension , to a receiver that will store the data. The paper will present the results of the initial RTAI operating system tests, the design of the streaming architecture and the first experimental results.

Real-Time EEG-Based Happiness Detection System

Directory of Open Access Journals (Sweden)

Noppadon Jatupaiboon

2013-01-01

Full Text Available We propose to use real-time EEG signal to classify happy and unhappy emotions elicited by pictures and classical music. We use PSD as a feature and SVM as a classifier. The average accuracies of subject-dependent model and subject-independent model are approximately 75.62% and 65.12%, respectively. Considering each pair of channels, temporal pair of channels (T7 and T8 gives a better result than the other area. Considering different frequency bands, high-frequency bands (Beta and Gamma give a better result than low-frequency bands. Considering different time durations for emotion elicitation, that result from 30 seconds does not have significant difference compared with the result from 60 seconds. From all of these results, we implement real-time EEG-based happiness detection system using only one pair of channels. Furthermore, we develop games based on the happiness detection system to help user recognize and control the happiness.

Real-Time Wait-Free Queues using Micro-Transactions

OpenAIRE

Meawad, Fadi; Iyer, Karthik; Schoeberl, Martin; Vitek, Jan

2011-01-01

This paper evaluates the applicability of transactional mem- ory to the implementation of dierent non-blocking data structures in the context of the Real-time Specication for Java. In particular, we argue that hardware support for micro-transaction allows us to implement eciently data structures that are often dicult to realize with the atomic operations provided by stock hardware. Our main imple- mentation platform is the Java Optimized Processor sys- tem. We report on the performance of dat...

Bridging FPGA and GPU technologies for AO real-time control

Science.gov (United States)

Perret, Denis; Lainé, Maxime; Bernard, Julien; Gratadour, Damien; Sevin, Arnaud

2016-07-01

Our team has developed a common environment for high performance simulations and real-time control of AO systems based on the use of Graphics Processors Units in the context of the COMPASS project. Such a solution, based on the ability of the real time core in the simulation to provide adequate computing performance, limits the cost of developing AO RTC systems and makes them more scalable. A code developed and validated in the context of the simulation may be injected directly into the system and tested on sky. Furthermore, the use of relatively low cost components also offers significant advantages for the system hardware platform. However, the use of GPUs in an AO loop comes with drawbacks: the traditional way of offloading computation from CPU to GPUs - involving multiple copies and unacceptable overhead in kernel launching - is not well suited in a real time context. This last application requires the implementation of a solution enabling direct memory access (DMA) to the GPU memory from a third party device, bypassing the operating system. This allows this device to communicate directly with the real-time core of the simulation feeding it with the WFS camera pixel stream. We show that DMA between a custom FPGA-based frame-grabber and a computation unit (GPU, FPGA, or Coprocessor such as Xeon-phi) across PCIe allows us to get latencies compatible with what will be needed on ELTs. As a fine-grained synchronization mechanism is not yet made available by GPU vendors, we propose the use of memory polling to avoid interrupts handling and involvement of a CPU. Network and Vision protocols are handled by the FPGA-based Network Interface Card (NIC). We present the results we obtained on a complete AO loop using camera and deformable mirror simulators.

System-on-chip architecture and validation for real-time transceiver optimization: APC implementation on FPGA

Science.gov (United States)

Suarez, Hernan; Zhang, Yan R.

2015-05-01

New radar applications need to perform complex algorithms and process large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression for real-time transceiver optimization are presented, they are based on a System-on-Chip architecture for Xilinx devices. This study also evaluates the performance of dedicated coprocessor as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through the high performance AXI buses, to perform floating-point operations, control the processing blocks, and communicate with external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band tested together with a low-cost channel emulator for different types of waveforms.

A Cloud-Based Infrastructure for Near-Real-Time Processing and Dissemination of NPP Data

Science.gov (United States)

Evans, J. D.; Valente, E. G.; Chettri, S. S.

2011-12-01

data volumes or user demand, but that computing capacity (and hourly costs) can be dropped almost instantly once the surge passes. Cloud computing also allows low-risk experimentation with a variety of machine architectures (processor types; bandwidth, memory, and storage capacities, etc.) and of system configurations (including massively parallel computing patterns). Finally, our service-based approach (in which user applications invoke software processes on a Web-accessible server) facilitates access into datasets of arbitrary size and resolution, and allows users to request and receive tailored products on demand. To maximize the usefulness and impact of our technology, we have emphasized open, industry-standard software interfaces. We are also using and developing open source software to facilitate the widespread adoption of similar, derived, or interoperable systems for processing and serving near-real-time data from NPP and other sources.

A High Performance Load Balance Strategy for Real-Time Multicore Systems

Directory of Open Access Journals (Sweden)

Keng-Mao Cho

2014-01-01

Full Text Available Finding ways to distribute workloads to each processor core and efficiently reduce power consumption is of vital importance, especially for real-time systems. In this paper, a novel scheduling algorithm is proposed for real-time multicore systems to balance the computation loads and save power. The developed algorithm simultaneously considers multiple criteria, a novel factor, and task deadline, and is called power and deadline-aware multicore scheduling (PDAMS. Experiment results show that the proposed algorithm can greatly reduce energy consumption by up to 54.2% and the deadline times missed, as compared to the other scheduling algorithms outlined in this paper.

AirNow Information Management System - Global Earth Observation System of Systems Data Processor for Real-Time Air Quality Data Products

Science.gov (United States)

Haderman, M.; Dye, T. S.; White, J. E.; Dickerson, P.; Pasch, A. N.; Miller, D. S.; Chan, A. C.

2012-12-01

Built upon the success of the U.S. Environmental Protection Agency's (EPA) AirNow program (www.AirNow.gov), the AirNow-International (AirNow-I) system contains an enhanced suite of software programs that process and quality control real-time air quality and environmental data and distribute customized maps, files, and data feeds. The goals of the AirNow-I program are similar to those of the successful U.S. program and include fostering the exchange of environmental data; making advances in air quality knowledge and applications; and building a community of people, organizations, and decision makers in environmental management. In 2010, Shanghai became the first city in China to run this state-of-the-art air quality data management and notification system. AirNow-I consists of a suite of modules (software programs and schedulers) centered on a database. One such module is the Information Management System (IMS), which can automatically produce maps and other data products through the use of GIS software to provide the most current air quality information to the public. Developed with Global Earth Observation System of Systems (GEOSS) interoperability in mind, IMS is based on non-proprietary standards, with preference to formal international standards. The system depends on data and information providers accepting and implementing a set of interoperability arrangements, including technical specifications for collecting, processing, storing, and disseminating shared data, metadata, and products. In particular, the specifications include standards for service-oriented architecture and web-based interfaces, such as a web mapping service (WMS), web coverage service (WCS), web feature service (WFS), sensor web services, and Really Simple Syndication (RSS) feeds. IMS is flexible, open, redundant, and modular. It also allows the merging of data grids to create complex grids that show comprehensive air quality conditions. For example, the AirNow Satellite Data Processor

Real-time collaboration in activity-based architectures

DEFF Research Database (Denmark)

Bardram, Jakob Eyvind; Christensen, Henrik Bærbak

2004-01-01

With the growing research into mobile and ubiquitous computing, there is a need for addressing how such infrastructures can support collaboration between nomadic users. We present the activity based computing paradigm and outline a proposal for handling collaboration in an activity......-based architecture. We argue that activity-based computing establishes a natural and sound conceptual and architectural basis for session management in real-time, synchronous collaboration....

Sojourn time asymptotics in processor-sharing queues

NARCIS (Netherlands)

Borst, S.C.; Núñez Queija, R.; Zwart, B.

2006-01-01

Over the past few decades, the Processor-Sharing (PS) discipline has attracted a great deal of attention in the queueing literature. While the PS paradigm emerged in the sixties as an idealization of round-robin scheduling in time-shared computer systems, it has recently captured renewed interest as

Supertracker: A Programmable Parallel Pipeline Arithmetic Processor For Auto-Cueing Target Processing

Science.gov (United States)

Mack, Harold; Reddi, S. S.

1980-04-01

Supertracker represents a programmable parallel pipeline computer architecture that has been designed to meet the real time image processing requirements of auto-cueing target data processing. The prototype bread-board currently under development will be designed to perform input video preprocessing and processing for 525-line and 875-line TV formats FLIR video, automatic display gain and contrast control, and automatic target cueing, classification, and tracking. The video preprocessor is capable of performing operations full frames of video data in real time, e.g., frame integration, storage, 3 x 3 convolution, and neighborhood processing. The processor architecture is being implemented using bit-slice microprogrammable arithmetic processors, operating in parallel. Each processor is capable of up to 20 million operations per second. Multiple frame memories are used for additional flexibility.

Rational calculation accuracy in acousto-optical matrix-vector processor

Science.gov (United States)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

VEST: An Aspect-Based Composition Tool for Real-Time Systems

Science.gov (United States)

2003-01-01

VEST: An Aspect-Based Composition Tool for Real - Time Systems * John A. Stankovic Ruiqing Zhu Ram Poornalingam Chenyang Lu Zhendong Yu Marty Humphrey...Composition Tool for Real - Time Systems 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e. TASK...it is obvious that designers of embedded real - time systems face many difficult problems. By working through various product scenarios with avionics

Emergency product generation for disaster management using RISAT and DMSAR quick look SAR processors

Science.gov (United States)

Desai, Nilesh; Sharma, Ritesh; Kumar, Saravana; Misra, Tapan; Gujraty, Virendra; Rana, SurinderSingh

2006-12-01

Since last few years, ISRO has embarked upon the development of two complex Synthetic Aperture Radar (SAR) missions, viz. Spaceborne Radar Imaging Satellite (RISAT) and Airborne SAR for Disaster Mangement (DMSAR), as a capacity building measure under country's Disaster Management Support (DMS) Program, for estimating the extent of damage over large areas (~75 Km) and also assess the effectiveness of the relief measures undertaken during natural disasters such as cyclones, epidemics, earthquakes, floods and landslides, forest fires, crop diseases etc. Synthetic Aperture Radar (SAR) has an unique role to play in mapping and monitoring of large areas affected by natural disasters especially floods, owing to its unique capability to see through clouds as well as all-weather imaging capability. The generation of SAR images with quick turn around time is very essential to meet the above DMS objectives. Thus the development of SAR Processors, for these two SAR systems poses considerable challenges and design efforts. Considering the growing user demand and inevitable necessity for a full-fledged high throughput processor, to process SAR data and generate image in real or near-real time, the design and development of a generic SAR Processor has been taken up and evolved, which will meet the SAR processing requirements for both Airborne and Spaceborne SAR systems. This hardware SAR processor is being built, to the extent possible, using only Commercial-Off-The-Shelf (COTS) DSP and other hardware plug-in modules on a Compact PCI (cPCI) platform. Thus, the major thrust has been on working out Multi-processor Digital Signal Processor (DSP) architecture and algorithm development and optimization rather than hardware design and fabrication. For DMSAR, this generic SAR Processor operates as a Quick Look SAR Processor (QLP) on-board the aircraft to produce real time full swath DMSAR images and as a ground based Near-Real Time high precision full swath Processor (NRTP). It will

Development of an MMS/PC based real time simulation of the B and W NSS plant for advanced control system design

International Nuclear Information System (INIS)

Bartells, P.S.; Brownell, R.B.

1990-01-01

The development of this personal-computer-based simulation of the Babcock and Wilcox nuclear steam system (NSS) was prompted in part by the need for a real-time analysis tool to be used in evaluating advanced control concepts for the NSS. NSS control is currently accomplished via conventional analog systems that are becoming increasingly obsolete. With the widespread use of digital micro-processor-based control systems for fossil power and other applications, the B and W Owners Group Advanced Control System Task Force is developing a next-generation control system for upgrading existing B and W power plants. To take advantage of the digital control technology, it is desirable to have a flexible, cost-effective, and portable control analysis tool available that can simulate various postulated control strategies and algorithms and couple these with simulated plant responses in real time to determine overall effectiveness. To develop the desired capability, B and W has incorporated the simulation methodology of the Modular Modeling System (MMS) and the knowledge gained during development of a similar Department of Energy-funded project. The MMS-based NSS model was developed and then modified to increase execution speed, ported to an IBM Personal System 2 (Model 80) and interfaced with user-friendly graphics. The user can develop alternative control strategies and readily interface them with the NSS model for real-time display and evaluation. The paper addresses the key considerations and programming techniques used to accomplish the resulting simulation

High performance graphics processors for medical imaging applications

International Nuclear Information System (INIS)

Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

1989-01-01

This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

Simulation of a processor switching circuit with APLSV

International Nuclear Information System (INIS)

Dilcher, H.

1979-01-01

The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

Comparison of Three Smart Camera Architectures for Real-Time Machine Vision System

Directory of Open Access Journals (Sweden)

Abdul Waheed Malik

2013-12-01

Full Text Available This paper presents a machine vision system for real-time computation of distance and angle of a camera from a set of reference points located on a target board. Three different smart camera architectures were explored to compare performance parameters such as power consumption, frame speed and latency. Architecture 1 consists of hardware machine vision modules modeled at Register Transfer (RT level and a soft-core processor on a single FPGA chip. Architecture 2 is commercially available software based smart camera, Matrox Iris GT. Architecture 3 is a two-chip solution composed of hardware machine vision modules on FPGA and an external microcontroller. Results from a performance comparison show that Architecture 2 has higher latency and consumes much more power than Architecture 1 and 3. However, Architecture 2 benefits from an easy programming model. Smart camera system with FPGA and external microcontroller has lower latency and consumes less power as compared to single FPGA chip having hardware modules and soft-core processor.

High-speed real-time OFDM transmission based on FPGA

Science.gov (United States)

Xiao, Xin; Li, Fan; Yu, Jianjun

2016-02-01

In this paper, we review our recent research progresses on real-time orthogonal frequency division multiplexing (OFDM) transmission based on FPGA. We successfully demonstrated four-channel wavelength-division multiplexing (WDM) 256.51Gb/s 16-ary quadrature amplitude modulation (16QAM)-OFDM signal transmission system for short-reach optical amplifier free inter-connection with real-time reception. Four optical carriers are modulated by four different 16QAM-OFDM signals via 10G-class direct modulation lasers (DMLs). We achieved highest capacity real-time reception optical OFDM signal transmission over 2.4-km SMF with the bit-error ratio (BER) under soft-decision forward error correction (SD-FEC) limitation of 2.4×10-2. In order to achieve higher spectrum efficiency (SE), we demonstrate 4-channel high level QAM-OFDM transmission over 20-km SMF-28 with real-time reception. 58.72-Gb/s 256QAM-OFDM and 56.4-Gb/s 128QAM-OFDM signal transmission within 25-GHz grid is achieved with the BER under 2.4×10-2 and real-time reception.

A real-time expert system for self-repairing flight control

Science.gov (United States)

Gaither, S. A.; Agarwal, A. K.; Shah, S. C.; Duke, E. L.

1989-01-01

An integrated environment for specifying, prototyping, and implementing a self-repairing flight-control (SRFC) strategy is described. At an interactive workstation, the user can select paradigms such as rule-based expert systems, state-transition diagrams, and signal-flow graphs and hierarchically nest them, assign timing and priority attributes, establish blackboard-type communication, and specify concurrent execution on single or multiple processors. High-fidelity nonlinear simulations of aircraft and SRFC systems can be performed off-line, with the possibility of changing SRFC rules, inference strategies, and other heuristics to correct for control deficiencies. Finally, the off-line-generated SRFC can be transformed into highly optimized application-specific real-time C-language code. An application of this environment to the design of aircraft fault detection, isolation, and accommodation algorithms is presented in detail.

Frequency Based Real-time Pricing for Residential Prosumers

Science.gov (United States)

Hambridge, Sarah Mabel

This work is the first to explore frequency based pricing for secondary frequency control as a price-reactive control mechanism for residential prosumers. A frequency based real-time electricity rate is designed as an autonomous market control mechanism for residential prosumers to provide frequency support as an ancillary service. In addition, prosumers are empowered to participate in dynamic energy transactions, therefore integrating Distributed Energy Resources (DERs), and increasing distributed energy storage onto the distributed grid. As the grid transitions towards DERs, a new market based control system will take the place of the legacy distributed system and possibly the legacy bulk power system. DERs provide many benefits such as energy independence, clean generation, efficiency, and reliability to prosumers during blackouts. However, the variable nature of renewable energy and current lack of installed energy storage on the grid will create imbalances in supply and demand as uptake increases, affecting the grid frequency and system operation. Through a frequency-based electricity rate, prosumers will be encouraged to purchase energy storage systems (ESS) to offset their neighbor's distributed generation (DG) such as solar. Chapter 1 explains the deregulation of the power system and move towards Distributed System Operators (DSOs), as prosumers become owners of microgrids and energy cells connected to the distributed system. Dynamic pricing has been proposed as a benefit to prosumers, giving them the ability to make decisions in the energy market, while also providing a way to influence and control their behavior. Frequency based real-time pricing is a type of dynamic pricing which falls between price-reactive control and transactive control. Prosumer-to-prosumer transactions may take the place of prosumer-to-utility transactions, building The Energy Internet. Frequency based pricing could be a mechanism for determining prosumer prices and supporting

A real time tracking vision system and its application to robotics

International Nuclear Information System (INIS)

Inoue, Hirochika

1994-01-01

Among various sensing channels the vision is most important for making robot intelligent. If provided with a high speed visual tracking capability, the robot-environment interaction becomes dynamic instead of static, and thus the potential repertoire of robot behavior becomes very rich. For this purpose we developed a real-time tracking vision system. The fundamental operation on which our system based is the calculation of correlation between local images. Use of special chip for correlation and the multi-processor configuration enable the robot to track more than hundreds cues in full video rate. In addition to the fundamental visual performance, applications for robot behavior control are also introduced. (author)

Real-time interactive three-dimensional display of CT and MR imaging volume data

International Nuclear Information System (INIS)

Yla-Jaaski, J.; Kubler, O.; Kikinis, R.

1987-01-01

Real-time reconstruction of surfaces from CT and MR imaging volume data is demonstrated using a new algorithm and implementation in a parallel computer system. The display algorithm accepts noncubic 16-bit voxels directly as input. Operations such as interpolation, classification by thresholding, depth coding, simple lighting effects, and removal of parts of the volume by clipping planes are all supported on-line. An eight-processor implementation of the algorithm renders surfaces from typical CT data sets in real time to allow interactive rotation of the volume

Real-time scintillation probe measurement of left ventricular function

International Nuclear Information System (INIS)

Green, M.V.; Ostrow, H.G.; Bacharach, S.L.; Allen, S.I.; Bonow, R.O.; Johnston, G.S.

1981-01-01

The micro-processor based system described in this report was designed for maximum flexibility and utility. While the principle function of the system is to acquire, create, analyze and display (in real-time) left ventricular time activity (or volume) curves, provision is also made to acquire additional physiologic signals (e.g., ECG, flowmeter, etc.) and to calculate and display relationships between these various data. The system was designed for interactive use so that the system user can alter the course of a series of measurements based on previous results. These general capabilities are illustrated with several examples. In the first, LV function was measured continuously in a subject from (supine) rest through exercise and recovery. The second example illustrates the use of the system in acquiring (LV) pressure-volume loops. Several technical problems, such as correction for LV background radiation, appear at present to limit the probes applicability. Even now, however, probe systems are demonstrably useful in the study of global left ventricular function when this function is changing rapidly with time in response to various interventions. (orig.) [de

Analysis and optimization techniques for real-time streaming image processing software on general purpose systems

NARCIS (Netherlands)

Westmijze, Mark

2018-01-01

Commercial Off The Shelf (COTS) Chip Multi-Processor (CMP) systems are for cost reasons often used in industry for soft real-time stream processing. COTS CMP systems typically have a low timing predictability, which makes it difficult to develop software applications for these systems with tight

Real-Time Reconnaissance-A Systems Look At Advanced Technology

Science.gov (United States)

Lapp, Henry

1981-12-01

An important role for reconnaissance is the location and identification of targets in real time. Current technology has been compartmented into sensors, automatic target recognizers, data links, ground exploitation and finally dissemination. In the days of bring home film recce, this segmentation of functions was appropriate. With the current emphasis on real time decision making from outputs of high resolution sensors this thinking has to be re-analyzed. A total systems approach to data management must be employed using the constraints imposed by technology as well as the atmosphere, survivable flight profiles, and the human workload. This paper will analyze the target acquisition through exploitation tasks and discuss the current advanced development technology that are applicable. A philosophy of processing data to get information as early as possible in the data handling chain is examined in the context of ground exploitation and dissemination needs. Examples of how the various real time sensors (screeners and processors), jam resistant data links and near real time ground data handling systems fit into this scenario are discussed. Specific DoD programs will be used to illustrate the credibility of this integrated approach.

Multibus-based parallel processor for simulation

Science.gov (United States)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Real-time traffic signal optimization model based on average delay time per person

Directory of Open Access Journals (Sweden)

Pengpeng Jiao

2015-10-01

Full Text Available Real-time traffic signal control is very important for relieving urban traffic congestion. Many existing traffic control models were formulated using optimization approach, with the objective functions of minimizing vehicle delay time. To improve people’s trip efficiency, this article aims to minimize delay time per person. Based on the time-varying traffic flow data at intersections, the article first fits curves of accumulative arrival and departure vehicles, as well as the corresponding functions. Moreover, this article transfers vehicle delay time to personal delay time using average passenger load of cars and buses, employs such time as the objective function, and proposes a signal timing optimization model for intersections to achieve real-time signal parameters, including cycle length and green time. This research further implements a case study based on practical data collected at an intersection in Beijing, China. The average delay time per person and queue length are employed as evaluation indices to show the performances of the model. The results show that the proposed methodology is capable of improving traffic efficiency and is very effective for real-world applications.

Real-time biscuit tile image segmentation method based on edge detection.

Science.gov (United States)

Matić, Tomislav; Aleksi, Ivan; Hocenski, Željko; Kraus, Dieter

2018-05-01

In this paper we propose a novel real-time Biscuit Tile Segmentation (BTS) method for images from ceramic tile production line. BTS method is based on signal change detection and contour tracing with a main goal of separating tile pixels from background in images captured on the production line. Usually, human operators are visually inspecting and classifying produced ceramic tiles. Computer vision and image processing techniques can automate visual inspection process if they fulfill real-time requirements. Important step in this process is a real-time tile pixels segmentation. BTS method is implemented for parallel execution on a GPU device to satisfy the real-time constraints of tile production line. BTS method outperforms 2D threshold-based methods, 1D edge detection methods and contour-based methods. Proposed BTS method is in use in the biscuit tile production line. Copyright © 2018 ISA. Published by Elsevier Ltd. All rights reserved.

Architecture of the APS real-time orbit feedback system

International Nuclear Information System (INIS)

Carwardine, J. A.; Lenkszus, F. R.

1997-01-01

The APS Real-Time Orbit Feedback System is designed to stabilize the orbit of the stored positron beam against low-frequency sources such as mechanical vibration and power supply ripple. A distributed array of digital signal processors is used to measure the orbit and compute corrections at a 1kHz rate. The system also provides extensive beam diagnostic tools. This paper describes the architectural aspects of the system and describes how the orbit correction algorithms are implemented

Architecture of the APS real-time orbit feedback system.

Energy Technology Data Exchange (ETDEWEB)

Carwardine, J. A.; Lenkszus, F. R.

1997-11-21

The APS Real-Time Orbit Feedback System is designed to stabilize the orbit of the stored positron beam against low-frequency sources such as mechanical vibration and power supply ripple. A distributed array of digital signal processors is used to measure the orbit and compute corrections at a 1kHz rate. The system also provides extensive beam diagnostic tools. This paper describes the architectural aspects of the system and describes how the orbit correction algorithms are implemented.

An evaluation of safety-critical Java on a Java processor

OpenAIRE

Rios Rivas, Juan Ricardo; Schoeberl, Martin

2014-01-01

The safety-critical Java (SCJ) specification provides a restricted set of the Java language intended for applications that require certification. In order to test the specification, implementations are emerging and the need to evaluate those implementations in a systematic way is becoming important. In this paper we evaluate our SCJ implementation which is based on the Java Optimized Processor JOP and we measure different performance and timeliness criteria relevant to hard real-time systems....

Commodity multi-processor systems in the ATLAS level-2 trigger

International Nuclear Information System (INIS)

Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

2000-01-01

Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

Commodity multi-processor systems in the ATLAS level-2 trigger

CERN Document Server

Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

2000-01-01

Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

Real-time digital filtering, event triggering, and tomographic reconstruction of JET soft x-ray data (abstract)

Science.gov (United States)

Edwards, A. W.; Blackler, K.; Gill, R. D.; van der Goot, E.; Holm, J.

1990-10-01

Based upon the experience gained with the present soft x-ray data acquisition system, new techniques are being developed which make extensive use of digital signal processors (DSPs). Digital filters make 13 further frequencies available in real time from the input sampling frequency of 200 kHz. In parallel, various algorithms running on further DSPs generate triggers in response to a range of events in the plasma. The sawtooth crash can be detected, for example, with a delay of only 50 μs from the onset of the collapse. The trigger processor interacts with the digital filter boards to ensure data of the appropriate frequency is recorded throughout a plasma discharge. An independent link is used to pass 780 and 24 Hz filtered data to a network of transputers. A full tomographic inversion and display of the 24 Hz data is carried out in real time using this 15 transputer array. The 780 Hz data are stored for immediate detailed playback following the pulse. Such a system could considerably improve the quality of present plasma diagnostic data which is, in general, sampled at one fixed frequency throughout a discharge. Further, it should provide valuable information towards designing diagnostic data acquisition systems for future long pulse operation machines when a high degree of real-time processing will be required, while retaining the ability to detect, record, and analyze events of interest within such long plasma discharges.

Compensation of F0 and formant frequencies in a real-time pitch-perturbation paradigm

DEFF Research Database (Denmark)

Eckey, Andreas; MacDonald, Ewen

2015-01-01

While producing speech, talkers monitor both somatosensory and auditory feedback. Many studies have demonstrated that if auditory feedback is manipulated in real-time (e.g., using an effects processor to shift the frequency spectrum), subjects compensate by modifying their F0 in the direction opp...

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

Science.gov (United States)

Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

2008-04-01

This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

Real Time Corner Detection for Miniaturized Electro-Optical Sensors Onboard Small Unmanned Aerial Systems

Directory of Open Access Journals (Sweden)

Antonio Moccia

2012-01-01

Full Text Available This paper describes the target detection algorithm for the image processor of a vision-based system that is installed onboard an unmanned helicopter. It has been developed in the framework of a project of the French national aerospace research center Office National d’Etudes et de Recherches Aérospatiales (ONERA which aims at developing an air-to-ground target tracking mission in an unknown urban environment. In particular, the image processor must detect targets and estimate ground motion in proximity of the detected target position. Concerning the target detection function, the analysis has dealt with realizing a corner detection algorithm and selecting the best choices in terms of edge detection methods, filtering size and type and the more suitable criterion of detection of the points of interest in order to obtain a very fast algorithm which fulfills the computation load requirements. The compared criteria are the Harris-Stephen and the Shi-Tomasi, ones, which are the most widely used in literature among those based on intensity. Experimental results which illustrate the performance of the developed algorithm and demonstrate that the detection time is fully compliant with the requirements of the real-time system are discussed.

Microgrids Real-Time Pricing Based on Clustering Techniques

Directory of Open Access Journals (Sweden)

Hao Liu

2018-05-01

Full Text Available Microgrids are widely spreading in electricity markets worldwide. Besides the security and reliability concerns for these microgrids, their operators need to address consumers’ pricing. Considering the growth of smart grids and smart meter facilities, it is expected that microgrids will have some level of flexibility to determine real-time pricing for at least some consumers. As such, the key challenge is finding an optimal pricing model for consumers. This paper, accordingly, proposes a new pricing scheme in which microgrids are able to deploy clustering techniques in order to understand their consumers’ load profiles and then assign real-time prices based on their load profile patterns. An improved weighted fuzzy average k-means is proposed to cluster load curve of consumers in an optimal number of clusters, through which the load profile of each cluster is determined. Having obtained the load profile of each cluster, real-time prices are given to each cluster, which is the best price given to all consumers in that cluster.

Real-Time Wait-Free Queues using Micro-Transactions

DEFF Research Database (Denmark)

Meawad, Fadi; Iyer, Karthik; Schoeberl, Martin

2011-01-01

This paper evaluates the applicability of transactional mem- ory to the implementation of dierent non-blocking data structures in the context of the Real-time Specication for Java. In particular, we argue that hardware support for micro-transaction allows us to implement eciently data structures...... that are often dicult to realize with the atomic operations provided by stock hardware. Our main imple- mentation platform is the Java Optimized Processor sys- tem. We report on the performance of data structures imple- mented with locks, compare and swap and micro-transactions. Our results conrm...

Sojourn times in finite-capacity processor-sharing queues

NARCIS (Netherlands)

Borst, S.C.; Boxma, O.J.; Hegde, N.

2005-01-01

Motivated by the need to develop simple parsimonious models for evaluating the performance of wireless data systems, we consider finite-capacity processor-sharing systems. For such systems, we analyze the sojourn time distribution, which presents a useful measure for the transfer delay of documents

MPC Related Computational Capabilities of ARMv7A Processors

DEFF Research Database (Denmark)

Frison, Gianluca; Jørgensen, John Bagterp

2015-01-01

In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

Science.gov (United States)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

A GPS-based Real-time Road Traffic Monitoring System

Science.gov (United States)

Tanti, Kamal Kumar

In recent years, monitoring systems are astonishingly inclined towards ever more automatic; reliably interconnected, distributed and autonomous operation. Specifically, the measurement, logging, data processing and interpretation activities may be carried out by separate units at different locations in near real-time. The recent evolution of mobile communication devices and communication technologies has fostered a growing interest in the GIS & GPS-based location-aware systems and services. This paper describes a real-time road traffic monitoring system based on integrated mobile field devices (GPS/GSM/IOs) working in tandem with advanced GIS-based application software providing on-the-fly authentications for real-time monitoring and security enhancement. The described system is developed as a fully automated, continuous, real-time monitoring system that employs GPS sensors and Ethernet and/or serial port communication techniques are used to transfer data between GPS receivers at target points and a central processing computer. The data can be processed locally or remotely based on the requirements of client’s satisfaction. Due to the modular architecture of the system, other sensor types may be supported with minimal effort. Data on the distributed network & measurements are transmitted via cellular SIM cards to a Control Unit, which provides for post-processing and network management. The Control Unit may be remotely accessed via an Internet connection. The new system will not only provide more consistent data about the road traffic conditions but also will provide methods for integrating with other Intelligent Transportation Systems (ITS). For communication between the mobile device and central monitoring service GSM technology is used. The resulting system is characterized by autonomy, reliability and a high degree of automation.

A Lecture Supporting System Based on Real-Time Learning Analytics

Science.gov (United States)

Shimada, Atsushi; Konomi, Shin'ichi

2017-01-01

A new lecture supporting system based on real-time learning analytics is proposed. Our target is on-site classrooms where teachers give their lectures, and a lot of students listen to teachers' explanation, conduct exercises etc. We utilize not only an e-Learning system, but also an e-Book system to collect real-time learning activities during the…

Suboptimal processor for anomaly detection for system surveillance and diagnosis

Energy Technology Data Exchange (ETDEWEB)

Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van

1989-06-01

Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.

Power Minimization for Parallel Real-Time Systems with Malleable Jobs and Homogeneous Frequencies

OpenAIRE

Paolillo, Antonio; Goossens, Joël; Hettiarachchi, Pradeep M.; Fisher, Nathan

2014-01-01

In this work, we investigate the potential benefit of parallelization for both meeting real-time constraints and minimizing power consumption. We consider malleable Gang scheduling of implicit-deadline sporadic tasks upon multiprocessors. By extending schedulability criteria for malleable jobs to DVFS-enabled multiprocessor platforms, we are able to derive an offline polynomial-time optimal processor/frequency-selection algorithm. Simulations of our algorithm on randomly generated task system...

Real-time wavefront processors for the next generation of adaptive optics systems: a design and analysis

Science.gov (United States)

Truong, Tuan; Brack, Gary L.; Troy, Mitchell; Trinh, Thang; Shi, Fang; Dekany, Richard G.

2003-02-01

Adaptive optics (AO) systems currently under investigation will require at least two orders of magitude increase in the number of actuators, which in turn translates to effectively a 104 increase in compute latency. Since the performance of an AO system invariably improves as the compute latency decreases, it is important to study how today's computer systems will scale to address this expected increase in actuator utilization. This paper answers this question by characterizing the performance of a single deformable mirror (DM) Shack-Hartmann natural guide star AO system implemented on the present-generation digital signal processor (DSP) TMS320C6701 from Texas Instruments. We derive the compute latency of such a system in terms of a few basic parameters, such as the number of DM actuators, the number of data channels used to read out the camera pixels, the number of DSPs, the available memory bandwidth, as well as the inter-processor communication (IPC) bandwidth and the pixel transfer rate. We show how the results would scale for future systems that utilizes multiple DMs and guide stars. We demonstrate that the principal performance bottleneck of such a system is the available memory bandwidth of the processors and to lesser extent the IPC bandwidth. This paper concludes with suggestions for mitigating this bottleneck.

Reconfigurable vision system for real-time applications

Science.gov (United States)

Torres-Huitzil, Cesar; Arias-Estrada, Miguel

2002-03-01

Recently, a growing community of researchers has used reconfigurable systems to solve computationally intensive problems. Reconfigurability provides optimized processors for systems on chip designs, and makes easy to import technology to a new system through reusable modules. The main objective of this work is the investigation of a reconfigurable computer system targeted for computer vision and real-time applications. The system is intended to circumvent the inherent computational load of most window-based computer vision algorithms. It aims to build a system for such tasks by providing an FPGA-based hardware architecture for task specific vision applications with enough processing power, using the minimum amount of hardware resources as possible, and a mechanism for building systems using this architecture. Regarding the software part of the system, a library of pre-designed and general-purpose modules that implement common window-based computer vision operations is being investigated. A common generic interface is established for these modules in order to define hardware/software components. These components can be interconnected to develop more complex applications, providing an efficient mechanism for transferring image and result data among modules. Some preliminary results are presented and discussed.

Real-Time Location-Based Rendering of Urban Underground Pipelines

Directory of Open Access Journals (Sweden)

Wei Li

2018-01-01

Full Text Available The concealment and complex spatial relationships of urban underground pipelines present challenges in managing them. Recently, augmented reality (AR has been a hot topic around the world, because it can enhance our perception of reality by overlaying information about the environment and its objects onto the real world. Using AR, underground pipelines can be displayed accurately, intuitively, and in real time. We analyzed the characteristics of AR and their application in underground pipeline management. We mainly focused on the AR pipeline rendering procedure based on the BeiDou Navigation Satellite System (BDS and simultaneous localization and mapping (SLAM technology. First, in aiming to improve the spatial accuracy of pipeline rendering, we used differential corrections received from the Ground-Based Augmentation System to compute the precise coordinates of users in real time, which helped us accurately retrieve and draw pipelines near the users, and by scene recognition the accuracy can be further improved. Second, in terms of pipeline rendering, we used Visual-Inertial Odometry (VIO to track the rendered objects and made some improvements to visual effects, which can provide steady dynamic tracking of pipelines even in relatively markerless environments and outdoors. Finally, we used the occlusion method based on real-time 3D reconstruction to realistically express the immersion effect of underground pipelines. We compared our methods to the existing methods and concluded that the method proposed in this research improves the spatial accuracy of pipeline rendering and the portability of the equipment. Moreover, the updating of our rendering procedure corresponded with the moving of the user’s location, thus we achieved a dynamic rendering of pipelines in the real environment.

An Overview on Base Real-Time Hard Shadow Techniques in Virtual Environments

Directory of Open Access Journals (Sweden)

Mohd Shahrizal Sunar

2012-03-01

Full Text Available Shadows are elegant to create a realistic scene in virtual environments variety type of shadow techniques encourage us to prepare an overview on all base shadow techniques. Non real-time and real-time techniques are big subdivision of shadow generation. In non real-time techniques ray tracing, ray casting and radiosity are well known and are described deeply. Radiosity is implemented to create very realistic shadow on non real-time scene. Although traditional radiosity algorithm is difficult to implement, we have proposed a simple one. The proposed pseudo code is easier to understand and implement. Ray tracing is used to prevent of collision of movement objects. Projection shadow, shadow volume and shadow mapping are used to create real-time shadow in virtual environments. We have used projection shadow for some objects are static and have shadow on flat surface. Shadow volume is used to create accurate shadow with sharp outline. Shadow mapping that is the base of most recently techniques is reconstructed. The reconstruct algorithm gives some new idea to propose another algorithm based on shadow mapping.

Embedded and real-time operating systems

CERN Document Server

Wang, K C

2017-01-01

This book covers the basic concepts and principles of operating systems, showing how to apply them to the design and implementation of complete operating systems for embedded and real-time systems. It includes all the foundational and background information on ARM architecture, ARM instructions and programming, toolchain for developing programs, virtual machines for software implementation and testing, program execution image, function call conventions, run-time stack usage and link C programs with assembly code. It describes the design and implementation of a complete OS for embedded systems in incremental steps, explaining the design principles and implementation techniques. For Symmetric Multiprocessing (SMP) embedded systems, the author examines the ARM MPcore processors, which include the SCU and GIC for interrupts routing and interprocessor communication and synchronization by Software Generated Interrupts (SGIs). Throughout the book, complete working sample systems demonstrate the design principles and...

Real-time DSP implementation for MRF-based video motion detection.

Science.gov (United States)

Dumontier, C; Luthon, F; Charras, J P

1999-01-01

This paper describes the real time implementation of a simple and robust motion detection algorithm based on Markov random field (MRF) modeling, MRF-based algorithms often require a significant amount of computations. The intrinsic parallel property of MRF modeling has led most of implementations toward parallel machines and neural networks, but none of these approaches offers an efficient solution for real-world (i.e., industrial) applications. Here, an alternative implementation for the problem at hand is presented yielding a complete, efficient and autonomous real-time system for motion detection. This system is based on a hybrid architecture, associating pipeline modules with one asynchronous module to perform the whole process, from video acquisition to moving object masks visualization. A board prototype is presented and a processing rate of 15 images/s is achieved, showing the validity of the approach.

Real-time electricity pricing mechanism in China based on system dynamics

International Nuclear Information System (INIS)

He, Yongxiu; Zhang, Jixiang

2015-01-01

Highlights: • The system dynamics is used to research the real-time electricity pricing mechanism. • Four kinds of the real-time electricity pricing models are carried out and simulated. • It analysed the electricity price, the user satisfaction and the social benefits under the different models. • Market pricing is the trend of the real-time electricity pricing mechanism. • Initial development path of the real-time price mechanism for China is designed between 2015 and 2030. - Abstract: As an important means of demand-side response, the reasonable formulation of the electricity price mechanism will have an important impact on the balance between the supply and demand of electric power. With the introduction of Chinese intelligence apparatus and the rapid development of smart grids, real-time electricity pricing, as the frontier electricity pricing mechanism in the smart grid, will have great significance on the promotion of energy conservation and the improvement of the total social surplus. From the perspective of system dynamics, this paper studies different real-time electricity pricing mechanisms based on load structure, cost structure and bidding and analyses the situation of user satisfaction and the total social surplus under different pricing mechanisms. Finally, through the comparative analysis of examples under different real-time pricing scenarios, this paper aims to explore and design the future dynamic real-time electricity pricing mechanism in China, predicts the dynamic real-time pricing level and provides a reference for real-time electricity price promotion in the future

Web-based Toolkit for Dynamic Generation of Data Processors

Science.gov (United States)

Patel, J.; Dascalu, S.; Harris, F. C.; Benedict, K. K.; Gollberg, G.; Sheneman, L.

2011-12-01

All computation-intensive scientific research uses structured datasets, including hydrology and all other types of climate-related research. When it comes to testing their hypotheses, researchers might use the same dataset differently, and modify, transform, or convert it to meet their research needs. Currently, many researchers spend a good amount of time performing data processing and building tools to speed up this process. They might routinely repeat the same process activities for new research projects, spending precious time that otherwise could be dedicated to analyzing and interpreting the data. Numerous tools are available to run tests on prepared datasets and many of them work with datasets in different formats. However, there is still a significant need for applications that can comprehensively handle data transformation and conversion activities and help prepare the various processed datasets required by the researchers. We propose a web-based application (a software toolkit) that dynamically generates data processors capable of performing data conversions, transformations, and customizations based on user-defined mappings and selections. As a first step, the proposed solution allows the users to define various data structures and, in the next step, can select various file formats and data conversions for their datasets of interest. In a simple scenario, the core of the proposed web-based toolkit allows the users to define direct mappings between input and output data structures. The toolkit will also support defining complex mappings involving the use of pre-defined sets of mathematical, statistical, date/time, and text manipulation functions. Furthermore, the users will be allowed to define logical cases for input data filtering and sampling. At the end of the process, the toolkit is designed to generate reusable source code and executable binary files for download and use by the scientists. The application is also designed to store all data

Dual-EKF-Based Real-Time Celestial Navigation for Lunar Rover

Directory of Open Access Journals (Sweden)

Li Xie

2012-01-01

Full Text Available A key requirement of lunar rover autonomous navigation is to acquire state information accurately in real-time during its motion and set up a gradual parameter-based nonlinear kinematics model for the rover. In this paper, we propose a dual-extended-Kalman-filter- (dual-EKF- based real-time celestial navigation (RCN method. The proposed method considers the rover position and velocity on the lunar surface as the system parameters and establishes a constant velocity (CV model. In addition, the attitude quaternion is considered as the system state, and the quaternion differential equation is established as the state equation, which incorporates the output of angular rate gyroscope. Therefore, the measurement equation can be established with sun direction vector from the sun sensor and speed observation from the speedometer. The gyro continuous output ensures the algorithm real-time operation. Finally, we use the dual-EKF method to solve the system equations. Simulation results show that the proposed method can acquire the rover position and heading information in real time and greatly improve the navigation accuracy. Our method overcomes the disadvantage of the cumulative error in inertial navigation.

Sojourn time tails in processor-sharing systems

NARCIS (Netherlands)

Egorova, R.R.

2009-01-01

The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

Detection of Histoplasma capsulatum from clinical specimens by cycling probe-based real-time PCR and nested real-time PCR.

Science.gov (United States)

Muraosa, Yasunori; Toyotome, Takahito; Yahiro, Maki; Watanabe, Akira; Shikanai-Yasuda, Maria Aparecida; Kamei, Katsuhiko

2016-05-01

We developed new cycling probe-based real-time PCR and nested real-time PCR assays for the detection of Histoplasma capsulatum that were designed to detect the gene encoding N-acetylated α-linked acidic dipeptidase (NAALADase), which we previously identified as an H. capsulatum antigen reacting with sera from patients with histoplasmosis. Both assays specifically detected the DNAs of all H. capsulatum strains but not those of other fungi or human DNA. The limited of detection (LOD) of the real-time PCR assay was 10 DNA copies when using 10-fold serial dilutions of the standard plasmid DNA and 50 DNA copies when using human serum spiked with standard plasmid DNA. The nested real-time PCR improved the LOD to 5 DNA copies when using human serum spiked with standard plasmid DNA, which represents a 10-fold higher than that observed with the real-time PCR assay. To assess the ability of the two assays to diagnose histoplasmosis, we analyzed a small number of clinical specimens collected from five patients with histoplasmosis, such as sera (n = 4), formalin-fixed paraffin-embedded (FFPE) tissue (n = 4), and bronchoalveolar lavage fluid (BALF) (n = 1). Although clinical sensitivity of the real-time PCR assay was insufficiently sensitive (33%), the nested real-time PCR assay increased the clinical sensitivity (77%), suggesting it has a potential to be a useful method for detecting H. capsulatum DNA in clinical specimens. © The Author 2015. Published by Oxford University Press on behalf of The International Society for Human and Animal Mycology. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

Science.gov (United States)

Hayashi, Akihiro; Wada, Yasutaka; Watanabe, Takeshi; Sekiguchi, Takeshi; Mase, Masayoshi; Shirako, Jun; Kimura, Keiji; Kasahara, Hironori

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

Microcomputer-based real-time optical signal processing system

Science.gov (United States)

Yu, F. T. S.; Cao, M. F.; Ludman, J. E.

1986-01-01

A microcomputer-based real-time programmable optical signal processing system utilizing a Magneto-Optic Spatial Light Modulator (MOSLM) and a Liquid Crystal Light Valve (LCLV) is described. This system can perform a myriad of complicated optical operations, such as image correlation, image subtraction, matrix multiplication and many others. The important assets of this proposed system must be the programmability and the capability of real-time addressing. The design specification and the progress toward practical implementation of this proposed system are discussed. Some preliminary experimental demonstrations are conducted. The feasible applications of this proposed system to image correlation for optical pattern recognition, image subtraction for IC chip inspection and matrix multiplication for optical computing are demonstrated.

Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

NARCIS (Netherlands)

Anjam, F.

2013-01-01

In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

Using Sun’s Java Real-Time System to Manage Behavior-Based Mobile Robot Controllers

Directory of Open Access Journals (Sweden)

Andrew McKenzie

2011-01-01

Full Text Available Implementing a robot controller that can effectively manage limited resources in a deterministic, real-time manner is challenging. Behavior-based architectures that decompose autonomy into levels of intelligence are popular due to their robustness but do not provide real-time features that enforce timing constraints or support determinism. We propose an architecture and approach for using the real-time features of the Real-Time Specification for Java (RTSJ in a behavior-based mobile robot controller to show that timing constraints affect performance. This is accomplished by extending a real-time aware architecture that explicitly enumerates timing requirements for each behavior. It is not enough to reduce latency. The usefulness of this approach is demonstrated via an implementation on Solaris 10 and the Sun Java Real-Time System (Java RTS. Experimental results are obtained using a K-team Koala robot performing path following with four composite behaviors. Experiments were conducted using several task period sets in three cases: real-time threads with the real-time garbage collector, real-time threads with the non- real-time garbage collector, and non-real-time threads with the non-real-time garbage collector. Results show that even if latency and determinism are improved, the timing of each individual behavior significantly affects task performance.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

A Multi-ASIC Real-Time Implementation of the Two Dimensional Affine Transform with a Bilinear Interpolation Scheme

NARCIS (Netherlands)

Bentum, Marinus Jan; Samsom, M.M.; Samsom, Martin M.; Slump, Cornelis H.

1995-01-01

Some image processing applications (e.g. computer graphics and robot vision) require the rotation, scaling and translation of digitized images in real-time (25–30 images per second). Today's standard image processors can not meet this timing constraint so other solutions have to be considered. This

Development of Real-Time Precise Positioning Algorithm Using GPS L1 Carrier Phase Data

Directory of Open Access Journals (Sweden)

Jeong-Ho Joh

2002-12-01

Full Text Available We have developed Real-time Phase DAta Processor(RPDAP for GPS L1 carrier. And also, we tested the RPDAP's positioning accuracy compared with results of real time kinematic(RTK positioning. While quality of the conventional L1 RTK positioning highly depend on receiving condition, the RPDAP can gives more stable positioning result because of different set of common GPS satellites, which searched by elevation mask angle and signal strength. In this paper, we demonstrated characteristics of the RPDAP compared with the L1 RTK technique. And we discussed several improvement ways to apply the RPDAP to precise real-time positioning using low-cost GPS receiver. With correcting the discussed weak points in near future, the RPDAP will be used in the field of precise real-time application, such as precise car navigation and precise personal location services.

Online Synchrophasor-Based Dynamic State Estimation using Real-Time Digital Simulator

DEFF Research Database (Denmark)

Khazraj, Hesam; Adewole, Adeyemi Charles; Udaya, Annakkage

2018-01-01

Dynamic state estimation is a very important control center application used in the dynamic monitoring of state variables. This paper presents and validates a time-synchronized phasor measurement unit (PMU)-based for dynamic state estimation by unscented Kalman filter (UKF) method using the real-...... using the RTDS (real-time digital simulator). The dynamic state variables of multi-machine systems are monitored and measured for the study on the transient behavior of power systems.......Dynamic state estimation is a very important control center application used in the dynamic monitoring of state variables. This paper presents and validates a time-synchronized phasor measurement unit (PMU)-based for dynamic state estimation by unscented Kalman filter (UKF) method using the real......-time digital simulator (RTDS). The dynamic state variables of the system are the rotor angle and speed of the generators. The performance of the UKF method is tested with PMU measurements as inputs using the IEEE 14-bus test system. This test system was modeled in the RSCAD software and tested in real time...

Real-time simulation of a Doubly-Fed Induction Generator based wind power system on eMEGASimRTM Real-Time Digital Simulator

Science.gov (United States)

Boakye-Boateng, Nasir Abdulai

The growing demand for wind power integration into the generation mix prompts the need to subject these systems to stringent performance requirements. This study sought to identify the required tools and procedures needed to perform real-time simulation studies of Doubly-Fed Induction Generator (DFIG) based wind generation systems as basis for performing more practical tests of reliability and performance for both grid-connected and islanded wind generation systems. The author focused on developing a platform for wind generation studies and in addition, the author tested the performance of two DFIG models on the platform real-time simulation model; an average SimpowerSystemsRTM DFIG wind turbine, and a detailed DFIG based wind turbine using ARTEMiSRTM components. The platform model implemented here consists of a high voltage transmission system with four integrated wind farm models consisting in total of 65 DFIG based wind turbines and it was developed and tested on OPAL-RT's eMEGASimRTM Real-Time Digital Simulator.

Lessons Learned from Real-Time, Event-Based Internet Science Communications

Science.gov (United States)

Phillips, T.; Myszka, E.; Gallagher, D. L.; Adams, M. L.; Koczor, R. J.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

For the last several years the Science Directorate at Marshall Space Flight Center has carried out a diverse program of Internet-based science communication. The Directorate's Science Roundtable includes active researchers, NASA public relations, educators, and administrators. The Science@NASA award-winning family of Web sites features science, mathematics, and space news. The program includes extended stories about NASA science, a curriculum resource for teachers tied to national education standards, on-line activities for students, and webcasts of real-time events. The focus of sharing science activities in real-time has been to involve and excite students and the public about science. Events have involved meteor showers, solar eclipses, natural very low frequency radio emissions, and amateur balloon flights. In some cases, broadcasts accommodate active feedback and questions from Internet participants. Through these projects a pattern has emerged in the level of interest or popularity with the public. The pattern differentiates projects that include science from those that do not, All real-time, event-based Internet activities have captured public interest at a level not achieved through science stories or educator resource material exclusively. The worst event-based activity attracted more interest than the best written science story. One truly rewarding lesson learned through these projects is that the public recognizes the importance and excitement of being part of scientific discovery. Flying a camera to 100,000 feet altitude isn't as interesting to the public as searching for viable life-forms at these oxygen-poor altitudes. The details of these real-time, event-based projects and lessons learned will be discussed.

Hardware Algorithms For Tile-Based Real-Time Rendering

NARCIS (Netherlands)

Crisu, D.

2012-01-01

In this dissertation, we present the GRAphics AcceLerator (GRAAL) framework for developing embedded tile-based rasterization hardware for mobile devices, meant to accelerate real-time 3-D graphics (OpenGL compliant) applications. The goal of the framework is a low-cost, low-power, high-performance

Rapid diagnosis of sepsis with TaqMan-Based multiplex real-time PCR.

Science.gov (United States)

Liu, Chang-Feng; Shi, Xin-Ping; Chen, Yun; Jin, Ye; Zhang, Bing

2018-02-01

The survival rate of septic patients mainly depends on a rapid and reliable diagnosis. A rapid, broad range, specific and sensitive quantitative diagnostic test is the urgent need. Thus, we developed a TaqMan-Based Multiplex real-time PCR assays to identify bloodstream pathogens within a few hours. Primers and TaqMan probes were designed to be complementary to conserved regions in the 16S rDNA gene of different kinds of bacteria. To evaluate accurately, sensitively, and specifically, the known bacteria samples (Standard strains, whole blood samples) are determined by TaqMan-Based Multiplex real-time PCR. In addition, 30 blood samples taken from patients with clinical symptoms of sepsis were tested by TaqMan-Based Multiplex real-time PCR and blood culture. The mean frequency of positive for Multiplex real-time PCR was 96% at a concentration of 100 CFU/mL, and it was 100% at a concentration greater than 1000 CFU/mL. All the known blood samples and Standard strains were detected positively by TaqMan-Based Multiplex PCR, no PCR products were detected when DNAs from other bacterium were used in the multiplex assay. Among the 30 patients with clinical symptoms of sepsis, 18 patients were confirmed positive by Multiplex real-time PCR and seven patients were confirmed positive by blood culture. TaqMan-Based Multiplex real-time PCR assay with highly sensitivity, specificity and broad detection range, is a rapid and accurate method in the detection of bacterial pathogens of sepsis and should have a promising usage in the diagnosis of sepsis. © 2017 Wiley Periodicals, Inc.

Improving the effectiveness of real-time flood forecasting through Predictive Uncertainty estimation: the multi-temporal approach

Science.gov (United States)

Barbetta, Silvia; Coccia, Gabriele; Moramarco, Tommaso; Todini, Ezio

2015-04-01

The negative effects of severe flood events are usually contrasted through structural measures that, however, do not fully eliminate flood risk. Non-structural measures, such as real-time flood forecasting and warning, are also required. Accurate stage/discharge future predictions with appropriate forecast lead-time are sought by decision-makers for implementing strategies to mitigate the adverse effects of floods. Traditionally, flood forecasting has been approached by using rainfall-runoff and/or flood routing modelling. Indeed, both types of forecasts, cannot be considered perfectly representing future outcomes because of lacking of a complete knowledge of involved processes (Todini, 2004). Nonetheless, although aware that model forecasts are not perfectly representing future outcomes, decision makers are de facto implicitly assuming the forecast of water level/discharge/volume, etc. as "deterministic" and coinciding with what is going to occur. Recently the concept of Predictive Uncertainty (PU) was introduced in hydrology (Krzysztofowicz, 1999), and several uncertainty processors were developed (Todini, 2008). PU is defined as the probability of occurrence of the future realization of a predictand (water level/discharge/volume) conditional on: i) prior observations and knowledge, ii) the available information obtained on the future value, typically provided by one or more forecast models. Unfortunately, PU has been frequently interpreted as a measure of lack of accuracy rather than the appropriate tool allowing to take the most appropriate decisions, given a model or several models' forecasts. With the aim to shed light on the benefits for appropriately using PU, a multi-temporal approach based on the MCP approach (Todini, 2008; Coccia and Todini, 2011) is here applied to stage forecasts at sites along the Upper Tiber River. Specifically, the STAge Forecasting-Rating Curve Model Muskingum-based (STAFOM-RCM) (Barbetta et al., 2014) along with the Rating

Hard real-time multibody simulations using ARM-based embedded systems

Energy Technology Data Exchange (ETDEWEB)

Pastorino, Roland, E-mail: roland.pastorino@kuleuven.be, E-mail: rpastorino@udc.es; Cosco, Francesco, E-mail: francesco.cosco@kuleuven.be; Naets, Frank, E-mail: frank.naets@kuleuven.be; Desmet, Wim, E-mail: wim.desmet@kuleuven.be [KU Leuven, PMA division, Department of Mechanical Engineering (Belgium); Cuadrado, Javier, E-mail: javicuad@cdf.udc.es [Universidad de La Coruña, Laboratorio de Ingeniería Mecánica (Spain)

2016-05-15

The real-time simulation of multibody models on embedded systems is of particular interest for controllers and observers such as model predictive controllers and state observers, which rely on a dynamic model of the process and are customarily executed in electronic control units. This work first identifies the software techniques and tools required to easily write efficient code for multibody models to be simulated on ARM-based embedded systems. Automatic Programming and Source Code Translation are the two techniques that were chosen to generate source code for multibody models in different programming languages. Automatic Programming is used to generate procedural code in an intermediate representation from an object-oriented library and Source Code Translation is used to translate the intermediate representation automatically to an interpreted language or to a compiled language for efficiency purposes. An implementation of these techniques is proposed. It is based on a Python template engine and AST tree walkers for Source Code Generation and on a model-driven translator for the Source Code Translation. The code is translated from a metalanguage to any of the following four programming languages: Python-Numpy, Matlab, C++-Armadillo, C++-Eigen. Two examples of multibody models were simulated: a four-bar linkage with multiple loops and a 3D vehicle steering system. The code for these examples has been generated and executed on two ARM-based single-board computers. Using compiled languages, both models could be simulated faster than real-time despite the low resources and performance of these embedded systems. Finally, the real-time performance of both models was evaluated when executed in hard real-time on Xenomai for both embedded systems. This work shows through measurements that Automatic Programming and Source Code Translation are valuable techniques to develop real-time multibody models to be used in embedded observers and controllers.

Hard real-time multibody simulations using ARM-based embedded systems

International Nuclear Information System (INIS)

Pastorino, Roland; Cosco, Francesco; Naets, Frank; Desmet, Wim; Cuadrado, Javier

2016-01-01

The real-time simulation of multibody models on embedded systems is of particular interest for controllers and observers such as model predictive controllers and state observers, which rely on a dynamic model of the process and are customarily executed in electronic control units. This work first identifies the software techniques and tools required to easily write efficient code for multibody models to be simulated on ARM-based embedded systems. Automatic Programming and Source Code Translation are the two techniques that were chosen to generate source code for multibody models in different programming languages. Automatic Programming is used to generate procedural code in an intermediate representation from an object-oriented library and Source Code Translation is used to translate the intermediate representation automatically to an interpreted language or to a compiled language for efficiency purposes. An implementation of these techniques is proposed. It is based on a Python template engine and AST tree walkers for Source Code Generation and on a model-driven translator for the Source Code Translation. The code is translated from a metalanguage to any of the following four programming languages: Python-Numpy, Matlab, C++-Armadillo, C++-Eigen. Two examples of multibody models were simulated: a four-bar linkage with multiple loops and a 3D vehicle steering system. The code for these examples has been generated and executed on two ARM-based single-board computers. Using compiled languages, both models could be simulated faster than real-time despite the low resources and performance of these embedded systems. Finally, the real-time performance of both models was evaluated when executed in hard real-time on Xenomai for both embedded systems. This work shows through measurements that Automatic Programming and Source Code Translation are valuable techniques to develop real-time multibody models to be used in embedded observers and controllers.

The associative memory system for the FTK processor at ATLAS

CERN Document Server

Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

2014-01-01

In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

Distribution Locational Real-Time Pricing Based Smart Building Control and Management

Energy Technology Data Exchange (ETDEWEB)

Hao, Jun; Dai, Xiaoxiao; Zhang, Yingchen; Zhang, Jun; Gao, Wenzhong

2016-11-21

This paper proposes an real-virtual parallel computing scheme for smart building operations aiming at augmenting overall social welfare. The University of Denver's campus power grid and Ritchie fitness center is used for demonstrating the proposed approach. An artificial virtual system is built in parallel to the real physical system to evaluate the overall social cost of the building operation based on the social science based working productivity model, numerical experiment based building energy consumption model and the power system based real-time pricing mechanism. Through interactive feedback exchanged between the real and virtual system, enlarged social welfare, including monetary cost reduction and energy saving, as well as working productivity improvements, can be achieved.

Real-time Vision using FPGAs, GPUs and Multi-core CPUs

DEFF Research Database (Denmark)

Kjær-Nielsen, Anders

the introduction and evolution of a wide variety of powerful hardware architectures have made the developed theory more applicable in performance demanding and real-time applications. Three different architectures have dominated the field due to their parallel capabilities that are often desired when dealing...... processors in the vision community. The introduction of programming languages like CUDA from NVIDIA has made it easier to utilize the high parallel processing powers of the GPU for general purpose computing and thereby realistic to use based on the effort involved with development. The increased clock...... frequencies and number of Configurable Logic Blocks (CLBs) of the FPGAs, as well as the introduction of dedicated hardware implementations like multipliers, Digital Signal Processing (DSP) slices and even embedded hard-core CPU implementations have made them more applicable for general purpose computing...

Linear Regression Based Real-Time Filtering

Directory of Open Access Journals (Sweden)

Misel Batmend

2013-01-01

Full Text Available This paper introduces real time filtering method based on linear least squares fitted line. Method can be used in case that a filtered signal is linear. This constraint narrows a band of potential applications. Advantage over Kalman filter is that it is computationally less expensive. The paper further deals with application of introduced method on filtering data used to evaluate a position of engraved material with respect to engraving machine. The filter was implemented to the CNC engraving machine control system. Experiments showing its performance are included.

A flexible software architecture for scalable real-time image and video processing applications

Science.gov (United States)

Usamentiaga, Rubén; Molleda, Julio; García, Daniel F.; Bulnes, Francisco G.

2012-06-01

Real-time image and video processing applications require skilled architects, and recent trends in the hardware platform make the design and implementation of these applications increasingly complex. Many frameworks and libraries have been proposed or commercialized to simplify the design and tuning of real-time image processing applications. However, they tend to lack flexibility because they are normally oriented towards particular types of applications, or they impose specific data processing models such as the pipeline. Other issues include large memory footprints, difficulty for reuse and inefficient execution on multicore processors. This paper presents a novel software architecture for real-time image and video processing applications which addresses these issues. The architecture is divided into three layers: the platform abstraction layer, the messaging layer, and the application layer. The platform abstraction layer provides a high level application programming interface for the rest of the architecture. The messaging layer provides a message passing interface based on a dynamic publish/subscribe pattern. A topic-based filtering in which messages are published to topics is used to route the messages from the publishers to the subscribers interested in a particular type of messages. The application layer provides a repository for reusable application modules designed for real-time image and video processing applications. These modules, which include acquisition, visualization, communication, user interface and data processing modules, take advantage of the power of other well-known libraries such as OpenCV, Intel IPP, or CUDA. Finally, we present different prototypes and applications to show the possibilities of the proposed architecture.

Biosensor-based real-time monitoring of paracetamol photocatalytic degradation.

Science.gov (United States)

Calas-Blanchard, Carole; Istamboulié, Georges; Bontoux, Margot; Plantard, Gaël; Goetz, Vincent; Noguer, Thierry

2015-07-01

This paper presents for the first time the integration of a biosensor for the on-line, real-time monitoring of a photocatalytic degradation process. Paracetamol was used as a model molecule due to its wide use and occurrence in environmental waters. The biosensor was developed based on tyrosinase immobilization in a polyvinylalcohol photocrosslinkable polymer. It was inserted in a computer-controlled flow system installed besides a photocatalytic reactor including titanium dioxide (TiO2) as photocatalyst. It was shown that the biosensor was able to accurately monitor the paracetamol degradation with time. Compared with conventional HPLC analysis, the described device provides a real-time information on the reaction advancement, allowing a better control of the photodegradation process. Copyright © 2015 Elsevier Ltd. All rights reserved.

"Real-Time Optical Laboratory Linear Algebra Solution Of Partial Differential Equations"

Science.gov (United States)

Casasent, David; Jackson, James

1986-03-01

A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) employing space and frequency-multiplexing, new partitioning and data flow, and achieving high accuracy performance with a non base-2 number system is described. Laboratory data on the performance of this system and the solution of parabolic Partial Differential Equations (PDEs) is provided. A multi-processor OLAP system is also described for the first time. It use in the solution of multiple banded matrices that frequently arise is then discussed. The utility and flexibility of this processor compared to digital systolic architectures should be apparent.

FPGA-Based Real-Time Motion Detection for Automated Video Surveillance Systems

Directory of Open Access Journals (Sweden)

Sanjay Singh

2016-03-01

Full Text Available Design of automated video surveillance systems is one of the exigent missions in computer vision community because of their ability to automatically select frames of interest in incoming video streams based on motion detection. This research paper focuses on the real-time hardware implementation of a motion detection algorithm for such vision based automated surveillance systems. A dedicated VLSI architecture has been proposed and designed for clustering-based motion detection scheme. The working prototype of a complete standalone automated video surveillance system, including input camera interface, designed motion detection VLSI architecture, and output display interface, with real-time relevant motion detection capabilities, has been implemented on Xilinx ML510 (Virtex-5 FX130T FPGA platform. The prototyped system robustly detects the relevant motion in real-time in live PAL (720 × 576 resolution video streams directly coming from the camera.

Real-time all-optical OFDM transmission system based on time-domain optical fourier transformation

DEFF Research Database (Denmark)

Guan, Pengyu; Kong, Deming; Røge, Kasper Meldgaard

2014-01-01

We propose a novel simple all-optical OFDM transmission system based on time-domain OFT using time-lenses. A real-time 160 Gbit/s DPSK OFDM transmission with 16 decorrelated data subcarriers is successfully demonstrated over 100 km....

Neurovision processor for designing intelligent sensors

Science.gov (United States)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

Real time 1.55 μm VCSEL-based coherent detection link

DEFF Research Database (Denmark)

Rodes Lopez, Roberto; Parekh, D.; Jensen, Jesper Bevensee

2012-01-01

This paper presents an experimental demonstration of VCSEL-based PON with simplified real-time coherent receiver at 2.5 Gbps. Receiver sensitivity of −37 dBm is achieved proving splitting ratio up to 2048 after 17 km fiber transmission.......This paper presents an experimental demonstration of VCSEL-based PON with simplified real-time coherent receiver at 2.5 Gbps. Receiver sensitivity of −37 dBm is achieved proving splitting ratio up to 2048 after 17 km fiber transmission....

Design and implementation of real-time wireless projection system based on ARM embedded system

Science.gov (United States)

Long, Zhaohua; Tang, Hao; Huang, Junhua

2018-04-01

Aiming at the shortage of existing real-time screen sharing system, a real-time wireless projection system is proposed in this paper. Based on the proposed system, a weight-based frame deletion strategy combined sampling time period and data variation is proposed. By implementing the system on the hardware platform, the results show that the system can achieve good results. The weight-based strategy can improve the service quality, reduce the delay and optimize the real-time customer service system [1].

A Real-Time Capable Software-Defined Receiver Using GPU for Adaptive Anti-Jam GPS Sensors

Science.gov (United States)

Seo, Jiwon; Chen, Yu-Hsuan; De Lorenzo, David S.; Lo, Sherman; Enge, Per; Akos, Dennis; Lee, Jiyun

2011-01-01

Due to their weak received signal power, Global Positioning System (GPS) signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs). However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR) with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU) coupled with a new generation Graphics Processing Unit (GPU) having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities. PMID:22164116

A Real-Time Capable Software-Defined Receiver Using GPU for Adaptive Anti-Jam GPS Sensors

Directory of Open Access Journals (Sweden)

Dennis Akos

2011-09-01

Full Text Available Due to their weak received signal power, Global Positioning System (GPS signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs. However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU coupled with a new generation Graphics Processing Unit (GPU having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities.

Cf-252 based neutron radiography using real-time image processing system

International Nuclear Information System (INIS)

Mochiki, Koh-ichi; Koiso, Manabu; Yamaji, Akihiro; Iwata, Hideki; Kihara, Yoshitaka; Sano, Shigeru; Murata, Yutaka

2001-01-01

For compact Cf-252 based neutron radiography, a real-time image processing system by particle counting technique has been developed. The electronic imaging system consists of a supersensitive imaging camera, a real-time corrector, a real-time binary converter, a real-time calculator for centroid, a display monitor and a computer. Three types of accumulated NR image; ordinary, binary and centroid images, can be observed during a measurement. Accumulated NR images were taken by the centroid mode, the binary mode and ordinary mode using of Cf-252 neutron source and those images were compared. The centroid mode presented the sharpest image and its statistical characteristics followed the Poisson distribution, while the ordinary mode showed the smoothest image as the averaging effect by particle bright spots with distributed brightness was most dominant. (author)

Agent-Based Modeling of Day-Ahead Real Time Pricing in a Pool-Based Electricity Market

Directory of Open Access Journals (Sweden)

Sh. Yousefi

2011-09-01

Full Text Available In this paper, an agent-based structure of the electricity retail market is presented based on which day-ahead (DA energy procurement for customers is modeled. Here, we focus on operation of only one Retail Energy Provider (REP agent who purchases energy from DA pool-based wholesale market and offers DA real time tariffs to a group of its customers. As a model of customer response to the offered real time prices, an hourly acceptance function is proposed in order to represent the hourly changes in the customer’s effective demand according to the prices. Here, Q-learning (QL approach is applied in day-ahead real time pricing for the customers enabling the REP agent to discover which price yields the most benefit through a trial-and-error search. Numerical studies are presented based on New England day-ahead market data which include comparing the results of RTP based on QL approach with that of genetic-based pricing.

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

Towards real-time photon Monte Carlo dose calculation in the cloud

Science.gov (United States)

Ziegenhein, Peter; Kozin, Igor N.; Kamerling, Cornelis Ph; Oelfke, Uwe

2017-06-01

Near real-time application of Monte Carlo (MC) dose calculation in clinic and research is hindered by the long computational runtimes of established software. Currently, fast MC software solutions are available utilising accelerators such as graphical processing units (GPUs) or clusters based on central processing units (CPUs). Both platforms are expensive in terms of purchase costs and maintenance and, in case of the GPU, provide only limited scalability. In this work we propose a cloud-based MC solution, which offers high scalability of accurate photon dose calculations. The MC simulations run on a private virtual supercomputer that is formed in the cloud. Computational resources can be provisioned dynamically at low cost without upfront investment in expensive hardware. A client-server software solution has been developed which controls the simulations and transports data to and from the cloud efficiently and securely. The client application integrates seamlessly into a treatment planning system. It runs the MC simulation workflow automatically and securely exchanges simulation data with the server side application that controls the virtual supercomputer. Advanced encryption standards were used to add an additional security layer, which encrypts and decrypts patient data on-the-fly at the processor register level. We could show that our cloud-based MC framework enables near real-time dose computation. It delivers excellent linear scaling for high-resolution datasets with absolute runtimes of 1.1 seconds to 10.9 seconds for simulating a clinical prostate and liver case up to 1% statistical uncertainty. The computation runtimes include the transportation of data to and from the cloud as well as process scheduling and synchronisation overhead. Cloud-based MC simulations offer a fast, affordable and easily accessible alternative for near real-time accurate dose calculations to currently used GPU or cluster solutions.

A real-time spike sorting method based on the embedded GPU.

Science.gov (United States)

Zelan Yang; Kedi Xu; Xiang Tian; Shaomin Zhang; Xiaoxiang Zheng

2017-07-01

Microelectrode arrays with hundreds of channels have been widely used to acquire neuron population signals in neuroscience studies. Online spike sorting is becoming one of the most important challenges for high-throughput neural signal acquisition systems. Graphic processing unit (GPU) with high parallel computing capability might provide an alternative solution for increasing real-time computational demands on spike sorting. This study reported a method of real-time spike sorting through computing unified device architecture (CUDA) which was implemented on an embedded GPU (NVIDIA JETSON Tegra K1, TK1). The sorting approach is based on the principal component analysis (PCA) and K-means. By analyzing the parallelism of each process, the method was further optimized in the thread memory model of GPU. Our results showed that the GPU-based classifier on TK1 is 37.92 times faster than the MATLAB-based classifier on PC while their accuracies were the same with each other. The high-performance computing features of embedded GPU demonstrated in our studies suggested that the embedded GPU provide a promising platform for the real-time neural signal processing.

Design of Mixed-Criticality Applications on Distributed Real-Time Systems

DEFF Research Database (Denmark)

Tamas-Selicean, Domitian

the concept of virtual links, and temporal separation, enforced through schedule tables for TT messages and bandwidth allocation for RC messages. The objective of this thesis is to develop methods and tools for distributed mixed-criticality real-time systems. At the processor level, we are interested......A mixed-criticality system implements applications of different safety-criticality levels onto the same platform. In such cases, the certification standards require that applications of different criticality levels are protected so they cannot influence each other. Otherwise, all tasks have...

A first near real-time seismology-based landquake monitoring system.

Science.gov (United States)

Chao, Wei-An; Wu, Yih-Min; Zhao, Li; Chen, Hongey; Chen, Yue-Gau; Chang, Jui-Ming; Lin, Che-Min

2017-03-02

Hazards from gravity-driven instabilities on hillslope (termed 'landquake' in this study) are an important problem facing us today. Rapid detection of landquake events is crucial for hazard mitigation and emergency response. Based on the real-time broadband data in Taiwan, we have developed a near real-time landquake monitoring system, which is a fully automatic process based on waveform inversion that yields source information (e.g., location and mechanism) and identifies the landquake source by examining waveform fitness for different types of source mechanisms. This system has been successfully tested offline using seismic records during the passage of the 2009 Typhoon Morakot in Taiwan and has been in online operation during the typhoon season in 2015. In practice, certain levels of station coverage (station gap 10 6  m 3 and area > 0.20 km 2 ) are required to ensure good performance (fitness > 0.6 for successful source identification) of the system, which can be readily implemented in other places in the world with real-time seismic networks and high landquake activities.

Real-time underwater image enhancement: An improved approach ...

Indian Academy of Sciences (India)

1School of Mechatronics, CSIR-Central Mechanical Engineering Research Institute, Durgapur 713209, India. 2Robotics and ...... a general purpose computer with Intel core i3 processor, frequency 2.20 ... Adobe Photoshop CS4 software. Table 6. .... 1In general, vision (e.g. camera) aided navigation requires on-board real-.

A Versatile Image Processor For Digital Diagnostic Imaging And Its Application In Computed Radiography

Science.gov (United States)

Blume, H.; Alexandru, R.; Applegate, R.; Giordano, T.; Kamiya, K.; Kresina, R.

1986-06-01

In a digital diagnostic imaging department, the majority of operations for handling and processing of images can be grouped into a small set of basic operations, such as image data buffering and storage, image processing and analysis, image display, image data transmission and image data compression. These operations occur in almost all nodes of the diagnostic imaging communications network of the department. An image processor architecture was developed in which each of these functions has been mapped into hardware and software modules. The modular approach has advantages in terms of economics, service, expandability and upgradeability. The architectural design is based on the principles of hierarchical functionality, distributed and parallel processing and aims at real time response. Parallel processing and real time response is facilitated in part by a dual bus system: a VME control bus and a high speed image data bus, consisting of 8 independent parallel 16-bit busses, capable of handling combined up to 144 MBytes/sec. The presented image processor is versatile enough to meet the video rate processing needs of digital subtraction angiography, the large pixel matrix processing requirements of static projection radiography, or the broad range of manipulation and display needs of a multi-modality diagnostic work station. Several hardware modules are described in detail. For illustrating the capabilities of the image processor, processed 2000 x 2000 pixel computed radiographs are shown and estimated computation times for executing the processing opera-tions are presented.

Real-time unmanned aircraft systems surveillance video mosaicking using GPU

Science.gov (United States)

Camargo, Aldo; Anderson, Kyle; Wang, Yi; Schultz, Richard R.; Fevig, Ronald A.

2010-04-01

Digital video mosaicking from Unmanned Aircraft Systems (UAS) is being used for many military and civilian applications, including surveillance, target recognition, border protection, forest fire monitoring, traffic control on highways, monitoring of transmission lines, among others. Additionally, NASA is using digital video mosaicking to explore the moon and planets such as Mars. In order to compute a "good" mosaic from video captured by a UAS, the algorithm must deal with motion blur, frame-to-frame jitter associated with an imperfectly stabilized platform, perspective changes as the camera tilts in flight, as well as a number of other factors. The most suitable algorithms use SIFT (Scale-Invariant Feature Transform) to detect the features consistent between video frames. Utilizing these features, the next step is to estimate the homography between two consecutives video frames, perform warping to properly register the image data, and finally blend the video frames resulting in a seamless video mosaick. All this processing takes a great deal of resources of resources from the CPU, so it is almost impossible to compute a real time video mosaic on a single processor. Modern graphics processing units (GPUs) offer computational performance that far exceeds current CPU technology, allowing for real-time operation. This paper presents the development of a GPU-accelerated digital video mosaicking implementation and compares it with CPU performance. Our tests are based on two sets of real video captured by a small UAS aircraft; one video comes from Infrared (IR) and Electro-Optical (EO) cameras. Our results show that we can obtain a speed-up of more than 50 times using GPU technology, so real-time operation at a video capture of 30 frames per second is feasible.

Near real-time digital holographic microscope based on GPU parallel computing

Science.gov (United States)

Zhu, Gang; Zhao, Zhixiong; Wang, Huarui; Yang, Yan

2018-01-01

A transmission near real-time digital holographic microscope with in-line and off-axis light path is presented, in which the parallel computing technology based on compute unified device architecture (CUDA) and digital holographic microscopy are combined. Compared to other holographic microscopes, which have to implement reconstruction in multiple focal planes and are time-consuming the reconstruction speed of the near real-time digital holographic microscope can be greatly improved with the parallel computing technology based on CUDA, so it is especially suitable for measurements of particle field in micrometer and nanometer scale. Simulations and experiments show that the proposed transmission digital holographic microscope can accurately measure and display the velocity of particle field in micrometer scale, and the average velocity error is lower than 10%.With the graphic processing units(GPU), the computing time of the 100 reconstruction planes(512×512 grids) is lower than 120ms, while it is 4.9s using traditional reconstruction method by CPU. The reconstruction speed has been raised by 40 times. In other words, it can handle holograms at 8.3 frames per second and the near real-time measurement and display of particle velocity field are realized. The real-time three-dimensional reconstruction of particle velocity field is expected to achieve by further optimization of software and hardware. Keywords: digital holographic microscope,

Design optimization of TTEthernet-based distributed real-time systems

DEFF Research Database (Denmark)

Tamas-Selicean, Domitian; Pop, Paul; Steiner, Wilfried

2015-01-01

Many safety-critical real-time applications are implemented using distributed architectures, composed of heterogeneous processing elements interconnected in a network. Our focus in this paper is on the TTEthernet protocol, a deterministic, synchronized and congestion-free network protocol based o...

An evaluation of safety-critical Java on a Java processor

DEFF Research Database (Denmark)

Rios Rivas, Juan Ricardo; Schoeberl, Martin

2014-01-01

The safety-critical Java (SCJ) specification provides a restricted set of the Java language intended for applications that require certification. In order to test the specification, implementations are emerging and the need to evaluate those implementations in a systematic way is becoming important....... In this paper we evaluate our SCJ implementation which is based on the Java Optimized Processor JOP and we measure different performance and timeliness criteria relevant to hard real-time systems. Our implementation targets Level 0 and Level1 of the specification and to test it we use a series of micro...

SPP: A data base processor data communications protocol

Science.gov (United States)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

RISC Processors and High Performance Computing

Science.gov (United States)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Science.gov (United States)

Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava; Lantz, Steven; Lefebvre, Matthieu; Masciovecchio, Mario; McDermott, Kevin; Riley, Daniel; Tadel, Matevž; Wittich, Peter; Würthwein, Frank; Yagil, Avi

2017-08-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Directory of Open Access Journals (Sweden)

Cerati Giuseppe

2017-01-01

Full Text Available For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU, ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC, for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

Energy Technology Data Exchange (ETDEWEB)

Cerati, Giuseppe [Fermilab; Elmer, Peter [Princeton U.; Krutelyov, Slava [UC, San Diego; Lantz, Steven [Cornell U.; Lefebvre, Matthieu [Princeton U.; Masciovecchio, Mario [UC, San Diego; McDermott, Kevin [Cornell U.; Riley, Daniel [Cornell U., LNS; Tadel, Matevž [UC, San Diego; Wittich, Peter [Cornell U.; Würthwein, Frank [UC, San Diego; Yagil, Avi [UC, San Diego

2017-01-01

For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

Investigation of phosphor-LED lamp for real-time half-duplex wireless VLC system

International Nuclear Information System (INIS)

Yeh, Chien-Hung; Chow, Chi-Wai; Chen, Hsing-Yu; Liu, Yen-Liang; Hsu, Dar-Zu

2016-01-01

In this investigation, a 71.3 to 148.4 Mbit s −1 white phosphor-LED visible light communication (VLC) system is proposed and demonstrated under the practical transmission length of 140 to 210 cm. Here, a commercial white-light LED lamp with five cascaded phosphor-LED chips is utilized for illumination and communication simultaneously. In the measurement, we utilize the optical orthogonal frequency division multiplexing quadrature amplitude modulation (OFDM-QAM) with bit-loading algorithm and propose an optimal bias-tee circuit design to improve the modulation bandwidth from 1 MHz to 27 MHz. Moreover, a blue optical filter is not used on the client side. Finally, to realize and demonstrate the real-time transmission performance in the proposed LED VLC system, a commercial OFDM-based digital signal processor (DSP) chip is utilized on the LED lighting side and client side, respectively. Hence, the proposed real-time half-duplex VLC transmission could achieve the 70 Mbit s −1 downstream and upstream data throughputs, under a practical transmission length of 200 cm. (paper)

Real-time vibration measurement by a spatial phase-shifting technique with a tilted holographic interferogram.

Science.gov (United States)

Nakadate, S; Isshiki, M

1997-01-01

Real-time vibration measurement by a tilted holographic interferogram is presented that utilizes the real-time digital fringe processor of a video signal. Three intensity data sampled at every one-third of the fringe spacing of the tilted fringes are used to calculate the modulation term of the fringe that is a function of a vibration amplitude. A three-dimensional lookup table performs the calculation in a TV repetition rate to give a new fringe profile that contours the vibration amplitude. Vibration modes at the resonant frequencies of a flat speaker were displayed on a monitor as changing the exciting frequency of vibration.

Power System Real-Time Monitoring by Using PMU-Based Robust State Estimation Method

DEFF Research Database (Denmark)

Zhao, Junbo; Zhang, Gexiang; Das, Kaushik

2016-01-01

Accurate real-time states provided by the state estimator are critical for power system reliable operation and control. This paper proposes a novel phasor measurement unit (PMU)-based robust state estimation method (PRSEM) to real-time monitor a power system under different operation conditions...... the system real-time states with good robustness and can address several kinds of BD.......-based bad data (BD) detection method, which can handle the smearing effect and critical measurement errors, is presented. We evaluate PRSEM by using IEEE benchmark test systems and a realistic utility system. The numerical results indicate that, in short computation time, PRSEM can effectively track...

GPU-based real-time triggering in the NA62 experiment

CERN Document Server

Ammendola, R.; Cretaro, P.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P.S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Vicini, P.

2016-01-01

Over the last few years the GPGPU (General-Purpose computing on Graphics Processing Units) paradigm represented a remarkable development in the world of computing. Computing for High-Energy Physics is no exception: several works have demonstrated the effectiveness of the integration of GPU-based systems in high level trigger of different experiments. On the other hand the use of GPUs in the low level trigger systems, characterized by stringent real-time constraints, such as tight time budget and high throughput, poses several challenges. In this paper we focus on the low level trigger in the CERN NA62 experiment, investigating the use of real-time computing on GPUs in this synchronous system. Our approach aimed at harvesting the GPU computing power to build in real-time refined physics-related trigger primitives for the RICH detector, as the the knowledge of Cerenkov rings parameters allows to build stringent conditions for data selection at trigger level. Latencies of all components of the trigger chain have...

Real time expert systems

International Nuclear Information System (INIS)

Asami, Tohru; Hashimoto, Kazuo; Yamamoto, Seiichi

1992-01-01

Recently, aiming at the application to the plant control for nuclear reactors and traffic and communication control, the research and the practical use of the expert system suitable to real time processing have become conspicuous. In this report, the condition for the required function to control the object that dynamically changes within a limited time is presented, and the technical difference between the real time expert system developed so as to satisfy it and the expert system of conventional type is explained with the actual examples and from theoretical aspect. The expert system of conventional type has the technical base in the problem-solving equipment originating in STRIPS. The real time expert system is applied to the fields accompanied by surveillance and control, to which conventional expert system is hard to be applied. The requirement for the real time expert system, the example of the real time expert system, and as the techniques of realizing real time processing, the realization of interruption processing, dispersion processing, and the mechanism of maintaining the consistency of knowledge are explained. (K.I.)

Open-circuit respirometry: real-time, laboratory-based systems.

Science.gov (United States)

Ward, Susan A

2018-05-04

This review explores the conceptual and technological factors integral to the development of laboratory-based, automated real-time open-circuit mixing-chamber and breath-by-breath (B × B) gas-exchange systems, together with considerations of assumptions and limitations. Advances in sensor technology, signal analysis, and digital computation led to the emergence of these technologies in the mid-20th century, at a time when investigators were beginning to recognise the interpretational advantages of nonsteady-state physiological-system interrogation in understanding the aetiology of exercise (in)tolerance in health, sport, and disease. Key milestones include the 'Auchincloss' description of an off-line system to estimate alveolar O 2 uptake B × B during exercise. This was followed by the first descriptions of real-time automated O 2 uptake and CO 2 output B × B measurement by Beaver and colleagues and by Linnarsson and Lindborg, and mixing-chamber measurement by Wilmore and colleagues. Challenges to both approaches soon emerged: e.g., the influence of mixing-chamber washout kinetics on mixed-expired gas concentration determination, and B × B alignment of gas-concentration signals with respired flow. The challenging algorithmic and technical refinements required for gas-exchange estimation at the alveolar level have also been extensively explored. In conclusion, while the technology (both hardware and software) underpinning real-time automated gas-exchange measurement has progressively advanced, there are still concerns regarding accuracy especially under the challenging conditions of changing metabolic rate.

Real-time objects development: Study and proposal for a parallel scheduling architecture

International Nuclear Information System (INIS)

Rioux, Laurent

1997-01-01

This thesis contributes to the programming and the execution control of real-time object oriented applications. Using real-time objects is very interesting for programming real- time applications, because this model can introduce the concurrence with the encapsulation properties, with modularity and reusability by taking into account the real-time constraints of the application. One essential quality of this approach is that it can directly specify the parallelism and the real-time constraints at the model level of the application. An annotation system of C++ has been defined to describe the real-time specifications in the model (or in the source code) of the application. It will supply to the execution support the different information it needs for the control. In this approach of multitasking, the control is distributed and encapsulated inside each real time object. Three complementary levels of control have been defined: the state level (defining the capability of an object to treat an operation), the concurrence level (assuring the coherence between the object attributes) and a scheduling control (allocating the processors resources to the object by taking real-time constraints into account). The proposed control architecture, named OROS, manages the attribute access of each object in an individual way, then it can parallel treatments which do not access at the same data. This architecture makes a dynamic control of an application that can take benefit from the parallelism of the new machines both for the execution parallelism and the control itself. This architecture uses only the simplest primitives of the industrial real-time operating systems which ensures its feasibility and portability. (author) [fr

Digital video timing analyzer for the evaluation of PC-based real-time simulation systems

Science.gov (United States)

Jones, Shawn R.; Crosby, Jay L.; Terry, John E., Jr.

2009-05-01

Due to the rapid acceleration in technology and the drop in costs, the use of commercial off-the-shelf (COTS) PC-based hardware and software components for digital and hardware-in-the-loop (HWIL) simulations has increased. However, the increase in PC-based components creates new challenges for HWIL test facilities such as cost-effective hardware and software selection, system configuration and integration, performance testing, and simulation verification/validation. This paper will discuss how the Digital Video Timing Analyzer (DiViTA) installed in the Aviation and Missile Research, Development and Engineering Center (AMRDEC) provides quantitative characterization data for PC-based real-time scene generation systems. An overview of the DiViTA is provided followed by details on measurement techniques, applications, and real-world examples of system benefits.

The Maia Spectroscopy Detector System: Engineering for Integrated Pulse Capture, Low-Latency Scanning and Real-Time Processing

International Nuclear Information System (INIS)

Kirkham, R.; Siddons, D.; Dunn, P.A.; Kuczewski, A.J.; Dodanwela, R.; Moorhead, G.F.; Ryan, C.G.; De Geronimo, G.; Beuttenmuller, R.; Pinelli, D.; Pfeffer, M.; Davey, P.; Jensen, M.; de Jonge, M.D.; Howard, D.L.; Kusel, M.; McKinlay, J.

2010-01-01

The Maia detector system is engineered for energy dispersive x-ray fluorescence spectroscopy and elemental imaging at photon rates exceeding 10 7 /s, integrated scanning of samples for pixel transit times as small as 50 (micro)s and high definition images of 10 8 pixels and real-time processing of detected events for spectral deconvolution and online display of pure elemental images. The system developed by CSIRO and BNL combines a planar silicon 384 detector array, application-specific integrated circuits for pulse shaping and peak detection and sampling and optical data transmission to an FPGA-based pipelined, parallel processor. This paper describes the system and the underpinning engineering solutions.

Accuracy Limitations in Optical Linear Algebra Processors

Science.gov (United States)

Batsell, Stephen Gordon

1990-01-01

One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

Real Time Animation of Trees Based on BBSC in Computer Games

Directory of Open Access Journals (Sweden)

Xuefeng Ao

2009-01-01

Full Text Available That researchers in the field of computer games usually find it is difficult to simulate the motion of actual 3D model trees lies in the fact that the tree model itself has very complicated structure, and many sophisticated factors need to be considered during the simulation. Though there are some works on simulating 3D tree and its motion, few of them are used in computer games due to the high demand for real-time in computer games. In this paper, an approach of animating trees in computer games based on a novel tree model representation—Ball B-Spline Curves (BBSCs are proposed. By taking advantage of the good features of the BBSC-based model, physical simulation of the motion of leafless trees with wind blowing becomes easier and more efficient. The method can generate realistic 3D tree animation in real-time, which meets the high requirement for real time in computer games.

A near real-time satellite-based global drought climate data record

International Nuclear Information System (INIS)

AghaKouchak, Amir; Nakhjiri, Navid

2012-01-01

Reliable drought monitoring requires long-term and continuous precipitation data. High resolution satellite measurements provide valuable precipitation information on a quasi-global scale. However, their short lengths of records limit their applications in drought monitoring. In addition to this limitation, long-term low resolution satellite-based gauge-adjusted data sets such as the Global Precipitation Climatology Project (GPCP) one are not available in near real-time form for timely drought monitoring. This study bridges the gap between low resolution long-term satellite gauge-adjusted data and the emerging high resolution satellite precipitation data sets to create a long-term climate data record of droughts. To accomplish this, a Bayesian correction algorithm is used to combine GPCP data with real-time satellite precipitation data sets for drought monitoring and analysis. The results showed that the combined data sets after the Bayesian correction were a significant improvement compared to the uncorrected data. Furthermore, several recent major droughts such as the 2011 Texas, 2010 Amazon and 2010 Horn of Africa droughts were detected in the combined real-time and long-term satellite observations. This highlights the potential application of satellite precipitation data for regional to global drought monitoring. The final product is a real-time data-driven satellite-based standardized precipitation index that can be used for drought monitoring especially over remote and/or ungauged regions. (letter)

Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

Science.gov (United States)

Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

2011-03-01

Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code

Shape based kinetic outlier detection in real-time PCR

Directory of Open Access Journals (Sweden)

D'Atri Mario

2010-04-01

Full Text Available Abstract Background Real-time PCR has recently become the technique of choice for absolute and relative nucleic acid quantification. The gold standard quantification method in real-time PCR assumes that the compared samples have similar PCR efficiency. However, many factors present in biological samples affect PCR kinetic, confounding quantification analysis. In this work we propose a new strategy to detect outlier samples, called SOD. Results Richards function was fitted on fluorescence readings to parameterize the amplification curves. There was not a significant correlation between calculated amplification parameters (plateau, slope and y-coordinate of the inflection point and the Log of input DNA demonstrating that this approach can be used to achieve a "fingerprint" for each amplification curve. To identify the outlier runs, the calculated parameters of each unknown sample were compared to those of the standard samples. When a significant underestimation of starting DNA molecules was found, due to the presence of biological inhibitors such as tannic acid, IgG or quercitin, SOD efficiently marked these amplification profiles as outliers. SOD was subsequently compared with KOD, the current approach based on PCR efficiency estimation. The data obtained showed that SOD was more sensitive than KOD, whereas SOD and KOD were equally specific. Conclusion Our results demonstrated, for the first time, that outlier detection can be based on amplification shape instead of PCR efficiency. SOD represents an improvement in real-time PCR analysis because it decreases the variance of data thus increasing the reliability of quantification.

Real-time application of knowledge-based systems

Science.gov (United States)

Brumbaugh, Randal W.; Duke, Eugene L.

1989-01-01

The Rapid Prototyping Facility (RPF) was developed to meet a need for a facility which allows flight systems concepts to be prototyped in a manner which allows for real-time flight test experience with a prototype system. This need was focused during the development and demonstration of the expert system flight status monitor (ESFSM). The ESFSM was a prototype system developed on a LISP machine, but lack of a method for progressive testing and problem identification led to an impractical system. The RPF concept was developed, and the ATMS designed to exercise its capabilities. The ATMS Phase 1 demonstration provided a practical vehicle for testing the RPF, as well as a useful tool. ATMS Phase 2 development continues. A dedicated F-18 is expected to be assigned for facility use in late 1988, with RAV modifications. A knowledge-based autopilot is being developed using the RPF. This is a system which provides elementary autopilot functions and is intended as a vehicle for testing expert system verification and validation methods. An expert system propulsion monitor is being prototyped. This system provides real-time assistance to an engineer monitoring a propulsion system during a flight.

A Lyapunov Function Based Remedial Action Screening Tool Using Real-Time Data

Energy Technology Data Exchange (ETDEWEB)

Mitra, Joydeep [Michigan State Univ., East Lansing, MI (United States); Ben-Idris, Mohammed [Univ. of Nevada, Reno, NV (United States); Faruque, Omar [Florida State Univ., Tallahassee, FL (United States); Backhaus, Scott [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Deb, Sidart [LCG Consulting, Los Altos, CA (United States)

2016-03-30

This report summarizes the outcome of a research project that comprised the development of a Lyapunov function based remedial action screening tool using real-time data (L-RAS). The L-RAS is an advanced computational tool that is intended to assist system operators in making real-time redispatch decisions to preserve power grid stability. The tool relies on screening contingencies using a homotopy method based on Lyapunov functions to avoid, to the extent possible, the use of time domain simulations. This enables transient stability evaluation at real-time speed without the use of massively parallel computational resources. The project combined the following components. 1. Development of a methodology for contingency screening using a homotopy method based on Lyapunov functions and real-time data. 2. Development of a methodology for recommending remedial actions based on the screening results. 3. Development of a visualization and operator interaction interface. 4. Testing of screening tool, validation of control actions, and demonstration of project outcomes on a representative real system simulated on a Real-Time Digital Simulator (RTDS) cluster. The project was led by Michigan State University (MSU), where the theoretical models including homotopy-based screening, trajectory correction using real-time data, and remedial action were developed and implemented in the form of research-grade software. Los Alamos National Laboratory (LANL) contributed to the development of energy margin sensitivity dynamics, which constituted a part of the remedial action portfolio. Florida State University (FSU) and Southern California Edison (SCE) developed a model of the SCE system that was implemented on FSU's RTDS cluster to simulate real-time data that was streamed over the internet to MSU where the L-RAS tool was executed and remedial actions were communicated back to FSU to execute stabilizing controls on the simulated system. LCG Consulting developed the visualization

Sojourn time asymptotics in Processor Sharing queues with varying service rate

NARCIS (Netherlands)

Egorova, R.; Mandjes, M.R.H.; Zwart, B.

2007-01-01

Abstract This paper addresses the sojourn time asymptotics for a GI/GI/⋅ queue operating under the Processor Sharing (PS) discipline with stochastically varying service rate. Our focus is on the logarithmic estimates of the tail of sojourn-time distribution, under the assumption that the job-size

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

Science.gov (United States)

Lindgren, R. W.; Tarbell, T. D.

1981-01-01

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Simulated and measured performance of a real-time processor for RFI detection and mitigation on-board spaceborne microwave radiometers

DEFF Research Database (Denmark)

Skou, Niels; Kristensen, Steen Savstrup; Søbjærg, Sten Schmidl

2017-01-01

An RFI processor breadboard has been designed and developed for future spaceborne microwave radiometer systems. RFI detection is based on the anomalous amplitude, kurtosis, and cross-frequency algorithms. These are implemented in VHDL code in an FPGA. Thus algorithm performance can be assessed...... by proper code simulation. The breadboard has been integrated with a Ku band radiometer subjected to RFI-like signals from a laboratory generator. Simulations show that the algorithms as implemented work according to theory when subjected to pulsed sinusoidal and QPSK signals. The laboratory measurements...

Mean sojourn times for phase-type discriminatory processor sharing systems

NARCIS (Netherlands)

Haviv, M.; van der Wal, J.

2008-01-01

In a discriminatory processor sharing (DPS) queueing model, each job (or customer) belongs to one out of finitely many classes. The arrival processes are Poisson. Classes differ with respect to arrival rates and service time distributions. Moreover, classes have different priority levels. All jobs

Load power device and system for real-time execution of hierarchical load identification algorithms

Science.gov (United States)

Yang, Yi; Madane, Mayura Arun; Zambare, Prachi Suresh

2017-11-14

A load power device includes a power input; at least one power output for at least one load; and a plurality of sensors structured to sense voltage and current at the at least one power output. A processor is structured to provide real-time execution of: (a) a plurality of load identification algorithms, and (b) event detection and operating mode detection for the at least one load.

Array processor architecture

Science.gov (United States)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Green computing: power optimisation of vfi-based real-time multiprocessor dataflow applications

NARCIS (Netherlands)

Ahmad, W.; Holzenspies, P.K.F.; Stoelinga, Mariëlle Ida Antoinette; van de Pol, Jan Cornelis

2015-01-01

Execution time is no longer the only performance metric for computer systems. In fact, a trend is emerging to trade raw performance for energy savings. Techniques like Dynamic Power Management (DPM, switching to low power state) and Dynamic Voltage and Frequency Scaling (DVFS, throttling processor

Real-time systems

OpenAIRE

Badr, Salah M.; Bruztman, Donald P.; Nelson, Michael L.; Byrnes, Ronald Benton

1992-01-01

This paper presents an introduction to the basic issues involved in real-time systems. Both real-time operating sys and real-time programming languages are explored. Concurrent programming and process synchronization and communication are also discussed. The real-time requirements of the Naval Postgraduate School Autonomous Under Vehicle (AUV) are then examined. Autonomous underwater vehicle (AUV), hard real-time system, real-time operating system, real-time programming language, real-time sy...

Subsurface Scattering-Based Object Rendering Techniques for Real-Time Smartphone Games

Directory of Open Access Journals (Sweden)

Won-Sun Lee

2014-01-01

Full Text Available Subsurface scattering that simulates the path of a light through the material in a scene is one of the advanced rendering techniques in the field of computer graphics society. Since it takes a number of long operations, it cannot be easily implemented in real-time smartphone games. In this paper, we propose a subsurface scattering-based object rendering technique that is optimized for smartphone games. We employ our subsurface scattering method that is utilized for a real-time smartphone game. And an example game is designed to validate how the proposed method can be operated seamlessly in real time. Finally, we show the comparison results between bidirectional reflectance distribution function, bidirectional scattering distribution function, and our proposed subsurface scattering method on a smartphone game.

Benchmarking NWP Kernels on Multi- and Many-core Processors

Science.gov (United States)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

Connectivity-based neurofeedback: Dynamic causal modeling for real-time fMRI☆

Science.gov (United States)

Koush, Yury; Rosa, Maria Joao; Robineau, Fabien; Heinen, Klaartje; W. Rieger, Sebastian; Weiskopf, Nikolaus; Vuilleumier, Patrik; Van De Ville, Dimitri; Scharnowski, Frank

2013-01-01

Neurofeedback based on real-time fMRI is an emerging technique that can be used to train voluntary control of brain activity. Such brain training has been shown to lead to behavioral effects that are specific to the functional role of the targeted brain area. However, real-time fMRI-based neurofeedback so far was limited to mainly training localized brain activity within a region of interest. Here, we overcome this limitation by presenting near real-time dynamic causal modeling in order to provide feedback information based on connectivity between brain areas rather than activity within a single brain area. Using a visual–spatial attention paradigm, we show that participants can voluntarily control a feedback signal that is based on the Bayesian model comparison between two predefined model alternatives, i.e. the connectivity between left visual cortex and left parietal cortex vs. the connectivity between right visual cortex and right parietal cortex. Our new approach thus allows for training voluntary control over specific functional brain networks. Because most mental functions and most neurological disorders are associated with network activity rather than with activity in a single brain region, this novel approach is an important methodological innovation in order to more directly target functionally relevant brain networks. PMID:23668967

Sojourn time asymptotics in the M/G/1 processor sharing queue

NARCIS (Netherlands)

A.P. Zwart (Bert); O.J. Boxma (Onno)

1998-01-01

textabstractWe show for the M/G/1 processor sharing queue that the service time distribution is regularly varying of index $-nu$, $nu$ non-integer, iff the sojourn time distribution is regularly varying of index $-nu $. This result is derived from a new expression for the Laplace-Stieltjes transform

SMOS near-real-time soil moisture product: processor overview and first validation results

Science.gov (United States)

Rodríguez-Fernández, Nemesio J.; Muñoz Sabater, Joaquin; Richaume, Philippe; de Rosnay, Patricia; Kerr, Yann H.; Albergel, Clement; Drusch, Matthias; Mecklenburg, Susanne

2017-10-01

Measurements of the surface soil moisture (SM) content are important for a wide range of applications. Among them, operational hydrology and numerical weather prediction, for instance, need SM information in near-real-time (NRT), typically not later than 3 h after sensing. The European Space Agency (ESA) Soil Moisture and Ocean Salinity (SMOS) satellite is the first mission specifically designed to measure SM from space. The ESA Level 2 SM retrieval algorithm is based on a detailed geophysical modelling and cannot provide SM in NRT. This paper presents the new ESA SMOS NRT SM product. It uses a neural network (NN) to provide SM in NRT. The NN inputs are SMOS brightness temperatures for horizontal and vertical polarizations and incidence angles from 30 to 45°. In addition, the NN uses surface soil temperature from the European Centre for Medium-Range Weather Forecasts (ECMWF) Integrated Forecast System (IFS). The NN was trained on SMOS Level 2 (L2) SM. The swath of the NRT SM retrieval is somewhat narrower (˜ 915 km) than that of the L2 SM dataset (˜ 1150 km), which implies a slightly lower revisit time. The new SMOS NRT SM product was compared to the SMOS Level 2 SM product. The NRT SM data show a standard deviation of the difference with respect to the L2 data of Organisation for the Exploitation of Meteorological Satellites (EUMETSAT) multicast service (EUMETCast).

ARM Processor Based Embedded System for Remote Data Acquisition

OpenAIRE

Raj Kumar Tiwari; Santosh Kumar Agrahari

2014-01-01

The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

High speed real-time wavefront processing system for a solid-state laser system

Science.gov (United States)

Liu, Yuan; Yang, Ping; Chen, Shanqiu; Ma, Lifang; Xu, Bing

2008-03-01

A high speed real-time wavefront processing system for a solid-state laser beam cleanup system has been built. This system consists of a core2 Industrial PC (IPC) using Linux and real-time Linux (RT-Linux) operation system (OS), a PCI image grabber, a D/A card. More often than not, the phase aberrations of the output beam from solid-state lasers vary fast with intracavity thermal effects and environmental influence. To compensate the phase aberrations of solid-state lasers successfully, a high speed real-time wavefront processing system is presented. Compared to former systems, this system can improve the speed efficiently. In the new system, the acquisition of image data, the output of control voltage data and the implementation of reconstructor control algorithm are treated as real-time tasks in kernel-space, the display of wavefront information and man-machine conversation are treated as non real-time tasks in user-space. The parallel processing of real-time tasks in Symmetric Multi Processors (SMP) mode is the main strategy of improving the speed. In this paper, the performance and efficiency of this wavefront processing system are analyzed. The opened-loop experimental results show that the sampling frequency of this system is up to 3300Hz, and this system can well deal with phase aberrations from solid-state lasers.

T-UPPAAL: Online Model-based Testing of Real-Time Systems

DEFF Research Database (Denmark)

Mikucionis, Marius; Larsen, Kim Guldstrand; Nielsen, Brian

2004-01-01

The goal of testing is to gain confidence in a physical computer based system by means of executing it. More than one third of typical project resources is spent on testing embedded and real-time systems, but still it remains ad-hoc, based on heuristics, and error-prone. Therefore systematic...

FPGA cluster for high-performance AO real-time control system

Science.gov (United States)

Geng, Deli; Goodsell, Stephen J.; Basden, Alastair G.; Dipper, Nigel A.; Myers, Richard M.; Saunter, Chris D.

2006-06-01

Whilst the high throughput and low latency requirements for the next generation AO real-time control systems have posed a significant challenge to von Neumann architecture processor systems, the Field Programmable Gate Array (FPGA) has emerged as a long term solution with high performance on throughput and excellent predictability on latency. Moreover, FPGA devices have highly capable programmable interfacing, which lead to more highly integrated system. Nevertheless, a single FPGA is still not enough: multiple FPGA devices need to be clustered to perform the required subaperture processing and the reconstruction computation. In an AO real-time control system, the memory bandwidth is often the bottleneck of the system, simply because a vast amount of supporting data, e.g. pixel calibration maps and the reconstruction matrix, need to be accessed within a short period. The cluster, as a general computing architecture, has excellent scalability in processing throughput, memory bandwidth, memory capacity, and communication bandwidth. Problems, such as task distribution, node communication, system verification, are discussed.

A Metrics-Based Approach to Intrusion Detection System Evaluation for Distributed Real-Time Systems

Science.gov (United States)

2002-04-01

Based Approach to Intrusion Detection System Evaluation for Distributed Real - Time Systems Authors: G. A. Fink, B. L. Chappell, T. G. Turner, and...Distributed, Security. 1 Introduction Processing and cost requirements are driving future naval combat platforms to use distributed, real - time systems of...distributed, real - time systems . As these systems grow more complex, the timing requirements do not diminish; indeed, they may become more constrained

ECH system developments including the design of an intelligent fault processor on the DIII-D tokamak

International Nuclear Information System (INIS)

Ponce, D.; Lohr, J.; Tooker, J.F.; O'Neill, R.C.; Moeller, C.P.; Doane, J.L.; Noraky, S.; Dubovenko, K.; Gorelov, Y.A.; Cengher, M.; Penaflor, B.G.; Ellis, R.A.

2011-01-01

A new generation fault processor is in development which is intended to increase fault handling flexibility and reduce the number of incomplete DIII-D shots due to gyrotron faults. The processor, which is based upon a field programmable gate array device, will analyze signals for aberrant operation and ramp down high voltage to try to avoid hard faults. The processor will then attempt to ramp back up to an attainable operating point. The new generation fault processor will be developed during an expansion of the electron cyclotron heating (ECH) areas that will include the installation of a depressed collector gyrotron and associated equipment. Existing systems will also be upgraded. Testing of real-time control of the ECH launcher poloidal drives by the DIII-D plasma control system will be completed. The ECH control system software will be upgraded for increased scalability and to increase operator productivity. Resources permitting, all systems will receive an extra layer of interlocks for the filament and magnet power supplies, added shielding for the tank electronics, programmable filament boost shape for long pulses, and electronics upgrades for the installation of the advanced fault processor.

Hybrid Modeling of Intra-DCT Coefficients for Real-Time Video Encoding

Directory of Open Access Journals (Sweden)

Li Jin

2008-01-01

Full Text Available Abstract The two-dimensional discrete cosine transform (2-D DCT and its subsequent quantization are widely used in standard video encoders. However, since most DCT coefficients become zeros after quantization, a number of redundant computations are performed. This paper proposes a hybrid statistical model used to predict the zeroquantized DCT (ZQDCT coefficients for intratransform and to achieve better real-time performance. First, each pixel block at the input of DCT is decomposed into a series of mean values and a residual block. Subsequently, a statistical model based on Gaussian distribution is used to predict the ZQDCT coefficients of the residual block. Then, a sufficient condition under which each quantized coefficient becomes zero is derived from the mean values. Finally, a hybrid model to speed up the DCT and quantization calculations is proposed. Experimental results show that the proposed model can reduce more redundant computations and achieve better real-time performance than the reference in the literature at the cost of negligible video quality degradation. Experiments also show that the proposed model significantly reduces multiplications for DCT and quantization. This is particularly suitable for processors in portable devices where multiplications consume more power than additions. Computational reduction implies longer battery lifetime and energy economy.

Space Weather and Real-Time Monitoring

Directory of Open Access Journals (Sweden)

S Watari

2009-04-01

Full Text Available Recent advance of information and communications technology enables to collect a large amount of ground-based and space-based observation data in real-time. The real-time data realize nowcast of space weather. This paper reports a history of space weather by the International Space Environment Service (ISES in association with the International Geophysical Year (IGY and importance of real-time monitoring in space weather.

Real-time stereo matching architecture based on 2D MRF model: a memory-efficient systolic array

Directory of Open Access Journals (Sweden)

Park Sungchan

2011-01-01

Full Text Available Abstract There is a growing need in computer vision applications for stereopsis, requiring not only accurate distance but also fast and compact physical implementation. Global energy minimization techniques provide remarkably precise results. But they suffer from huge computational complexity. One of the main challenges is to parallelize the iterative computation, solving the memory access problem between the big external memory and the massive processors. Remarkable memory saving can be obtained with our memory reduction scheme, and our new architecture is a systolic array. If we expand it into N's multiple chips in a cascaded manner, we can cope with various ranges of image resolutions. We have realized it using the FPGA technology. Our architecture records 19 times smaller memory than the global minimization technique, which is a principal step toward real-time chip implementation of the various iterative image processing algorithms with tiny and distributed memory resources like optical flow, image restoration, etc.

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Directory of Open Access Journals (Sweden)

Hiroki Iwaizumi

2013-01-01

Full Text Available A processor design for singular value decomposition (SVD and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs and arithmetic instructions specialized in complex matrix operations.

RTX Correction Accuracy and Real-Time Data Processing of the New Integrated SeismoGeodetic System with Real-Time Acceleration and Displacement Measurements for Earthquake Characterization Based on High-Rate Seismic and GPS Data

Science.gov (United States)

Zimakov, L. G.; Raczka, J.; Barrientos, S. E.

2016-12-01

We will discuss and show the results obtained from an integrated SeismoGeodetic System, model SG160-09, installed in the Chile (Chilean National Network), Italy (University of Naples Network), and California. The SG160-09 provides the user high rate GNSS and accelerometer data, full epoch-by-epoch measurement integrity and the ability to create combined GNSS and accelerometer high-rate (200Hz) displacement time series in real-time. The SG160-09 combines seismic recording with GNSS geodetic measurement in a single compact, ruggedized case. The system includes a low-power, 220-channel GNSS receiver powered by the latest Trimble-precise Maxwell™6 technology and supports tracking GPS, GLONASS and Galileo signals. The receiver incorporates on-board GNSS point positioning using Real-Time Precise Point Positioning (PPP) technology with satellite clock and orbit corrections delivered over IP networks. The seismic recording includes an ANSS Class A, force balance accelerometer with the latest, low power, 24-bit A/D converter, producing high-resolution seismic data. The SG160-09 processor acquires and packetizes both seismic and geodetic data and transmits it to the central station using an advanced, error-correction protocol providing data integrity between the field and the processing center. The SG160-09 has been installed in three seismic stations in different geographic locations with different Trimble global reference stations coverage The hardware includes the SG160-09 system, external Zephyr Geodetic-2 GNSS antenna, both radio and high-speed Internet communication media. Both acceleration and displacement data was transmitted in real-time to the centralized Data Acquisition Centers for real-time data processing. Command/Control of the field station and real-time GNSS position correction are provided via the Pivot platform. Data from the SG160-09 system was used for seismic event characterization along with data from traditional seismic and geodetic stations

The SAFT-UT (synthetic aperture focusing technique for ultrasonic testing) real-time inspection system: Operational principles and implementation

Energy Technology Data Exchange (ETDEWEB)

Hall, T. E.; Reid, L. D.; Doctor, S. R.

1988-06-01

This document provides a technical description of the real-time imaging system developed for rapid flaw detection and characterization utilizing the synthetic aperture focusing technique for ultrasonic testing (SAFT-UT). The complete fieldable system has been designed to perform inservice inspection of light-water reactor components. Software was written on a DEC LSI 11/23 computer system to control data collection. The unprocessed data is transferred to a VAX 11/730 host computer to perform data processing and image display tasks. A parallel architecture peripheral to the host computer, referred to as the Real-Time SAFT Processor, rapidly performs the SAFT processing function. From the host's point of view, this device operates on the SAFT data in such a way that one may consider it to be a specialized or SAFT array processor. A guide to SAFT-UT theory and conventions is included, along with a detailed description of the operation of the software, how to install the software, and a detailed hardware description.

Integration of domain and resource-based reasoning for real-time control in dynamic environments

Science.gov (United States)

Morgan, Keith; Whitebread, Kenneth R.; Kendus, Michael; Cromarty, Andrew S.

1993-01-01

A real-time software controller that successfully integrates domain-based and resource-based control reasoning to perform task execution in a dynamically changing environment is described. The design of the controller is based on the concept of partitioning the process to be controlled into a set of tasks, each of which achieves some process goal. It is assumed that, in general, there are multiple ways (tasks) to achieve a goal. The controller dynamically determines current goals and their current criticality, choosing and scheduling tasks to achieve those goals in the time available. It incorporates rule-based goal reasoning, a TMS-based criticality propagation mechanism, and a real-time scheduler. The controller has been used to build a knowledge-based situation assessment system that formed a major component of a real-time, distributed, cooperative problem solving system built under DARPA contract. It is also being employed in other applications now in progress.

Performance analysis and kernel size study of the Lynx real-time operating system

Science.gov (United States)

Liu, Yuan-Kwei; Gibson, James S.; Fernquist, Alan R.

1993-01-01

This paper analyzes the Lynx real-time operating system (LynxOS), which has been selected as the operating system for the Space Station Freedom Data Management System (DMS). The features of LynxOS are compared to other Unix-based operating system (OS). The tools for measuring the performance of LynxOS, which include a high-speed digital timer/counter board, a device driver program, and an application program, are analyzed. The timings for interrupt response, process creation and deletion, threads, semaphores, shared memory, and signals are measured. The memory size of the DMS Embedded Data Processor (EDP) is limited. Besides, virtual memory is not suitable for real-time applications because page swap timing may not be deterministic. Therefore, the DMS software, including LynxOS, has to fit in the main memory of an EDP. To reduce the LynxOS kernel size, the following steps are taken: analyzing the factors that influence the kernel size; identifying the modules of LynxOS that may not be needed in an EDP; adjusting the system parameters of LynxOS; reconfiguring the device drivers used in the LynxOS; and analyzing the symbol table. The reductions in kernel disk size, kernel memory size and total kernel size reduction from each step mentioned above are listed and analyzed.

Microcontroller-based real-time QRS detection.

Science.gov (United States)

Sun, Y; Suppappola, S; Wrublewski, T A

1992-01-01

The authors describe the design of a system for real-time detection of QRS complexes in the electrocardiogram based on a single-chip microcontroller (Motorola 68HC811). A systematic analysis of the instrumentation requirements for QRS detection and of the various design techniques is also given. Detection algorithms using different nonlinear transforms for the enhancement of QRS complexes are evaluated by using the ECG database of the American Heart Association. The results show that the nonlinear transform involving multiplication of three adjacent, sign-consistent differences in the time domain gives a good performance and a quick response. When implemented with an appropriate sampling rate, this algorithm is also capable of rejecting pacemaker spikes. The eight-bit single-chip microcontroller provides sufficient throughput and shows a satisfactory performance. Implementation of multiple detection algorithms in the same system improves flexibility and reliability. The low chip count in the design also favors maintainability and cost-effectiveness.

Discussion paper for a highly parallel array processor-based machine

International Nuclear Information System (INIS)

Hagstrom, R.; Bolotin, G.; Dawson, J.

1984-01-01

The architectural plant for a quickly realizable implementation of a highly parallel special-purpose computer system with peak performance in the range of 6 billion floating point operations per second is discussed. The architecture is suitable to Lattice Gauge theoretical computations of fundamental physics interest and may be applicable to a range of other problems which deal with numerically intensive computational problems. The plan is quickly realizable because it employs a maximum of commercially available hardware subsystems and because the architecture is software-transparent to the individual processors, allowing straightforward re-use of whatever commercially available operating-systems and support software that is suitable to run on the commercially-produced processors. A tiny prototype instrument, designed along this architecture has already operated. A few elementary examples of programs which can run efficiently are presented. The large machine which the authors would propose to build would be based upon a highly competent array-processor, the ST-100 Array Processor, and specific design possibilities are discussed. The first step toward realizing this plan practically is to install a single ST-100 to allow algorithm development to proceed while a demonstration unit is built using two of the ST-100 Array Processors

Performance Evaluation of Components Using a Granularity-based Interface Between Real-Time Calculus and Timed Automata

Directory of Open Access Journals (Sweden)

Karine Altisen

2010-06-01

Full Text Available To analyze complex and heterogeneous real-time embedded systems, recent works have proposed interface techniques between real-time calculus (RTC and timed automata (TA, in order to take advantage of the strengths of each technique for analyzing various components. But the time to analyze a state-based component modeled by TA may be prohibitively high, due to the state space explosion problem. In this paper, we propose a framework of granularity-based interfacing to speed up the analysis of a TA modeled component. First, we abstract fine models to work with event streams at coarse granularity. We perform analysis of the component at multiple coarse granularities and then based on RTC theory, we derive lower and upper bounds on arrival patterns of the fine output streams using the causality closure algorithm. Our framework can help to achieve tradeoffs between precision and analysis time.

Hard Real-Time Networking on Firewire

NARCIS (Netherlands)

Zhang, Yuchen; Orlic, Bojan; Visser, Peter; Broenink, Jan

2005-01-01

This paper investigates the possibility of using standard, low-cost, widely used FireWire as a new generation fieldbus medium for real-time distributed control applications. A real-time software subsys- tem, RT-FireWire was designed that can, in combination with Linux-based real-time operating

Indoor Localization of a Quadrotor Based on WSN: A Real-Time Application

Directory of Open Access Journals (Sweden)

Jose L. Rullan-Lara

2013-01-01

Full Text Available A real-time localization algorithm is presented in this paper. The algorithm presented here uses an extended Kalman filter and is based on Time Difference Of Arrivals (TDOA measurements of radio signal. The position and velocity of an Unmanned Aerial Vehicle (UAV are successfully estimated in closed-loop in real-time, both in hover and path following flights. Relatively small position errors obtained from the experiments prove the good performance of the proposed algorithm.

Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring

OpenAIRE

Chen, Jieshi; Schafer, Benjamin Carrion; Ho, Ivan Wang-Hei

2016-01-01

With the growing demand of real-time traffic monitoring nowadays, software-based image processing can hardly meet the real-time data processing requirement due to the serial data processing nature. In this paper, the implementation of a hardware-based feature detection and networking system prototype for real-time traffic monitoring as well as data transmission is presented. The hardware architecture of the proposed system is mainly composed of three parts: data collection, feature detection,...

Real-time image reconstruction and display system for MRI using a high-speed personal computer.

Science.gov (United States)

Haishi, T; Kose, K

1998-09-01

A real-time NMR image reconstruction and display system was developed using a high-speed personal computer and optimized for the 32-bit multitasking Microsoft Windows 95 operating system. The system was operated at various CPU clock frequencies by changing the motherboard clock frequency and the processor/bus frequency ratio. When the Pentium CPU was used at the 200 MHz clock frequency, the reconstruction time for one 128 x 128 pixel image was 48 ms and that for the image display on the enlarged 256 x 256 pixel window was about 8 ms. NMR imaging experiments were performed with three fast imaging sequences (FLASH, multishot EPI, and one-shot EPI) to demonstrate the ability of the real-time system. It was concluded that in most cases, high-speed PC would be the best choice for the image reconstruction and display system for real-time MRI. Copyright 1998 Academic Press.

Field Installation and Real-Time Data Processing of the New Integrated SeismoGeodetic System with Real-Time Acceleration and Displacement Measurements for Earthquake Characterization Based on High-Rate Seismic and GPS Data

Science.gov (United States)

Zimakov, Leonid; Jackson, Michael; Passmore, Paul; Raczka, Jared; Alvarez, Marcos; Barrientos, Sergio

2015-04-01

We will discuss and show the results obtained from an integrated SeismoGeodetic System, model SG160-09, installed in the Chilean National Network. The SG160-09 provides the user high rate GNSS and accelerometer data, full epoch-by-epoch measurement integrity and, using the Trimble Pivot™ SeismoGeodetic App, the ability to create combined GNSS and accelerometer high-rate (200Hz) displacement time series in real-time. The SG160-09 combines seismic recording with GNSS geodetic measurement in a single compact, ruggedized package. The system includes a low-power, 220-channel GNSS receiver powered by the latest Trimble-precise Maxwell™6 technology and supports tracking GPS, GLONASS and Galileo signals. The receiver incorporates on-board GNSS point positioning using Real-Time Precise Point Positioning (PPP) technology with satellite clock and orbit corrections delivered over IP networks. The seismic recording element includes an ANSS Class A, force balance triaxial accelerometer with the latest, low power, 24-bit A/D converter, which produces high-resolution seismic data. The SG160-09 processor acquires and packetizes both seismic and geodetic data and transmits it to the central station using an advanced, error-correction protocol with back fill capability providing data integrity between the field and the processing center. The SG160-09 has been installed in the seismic station close to the area of the Iquique earthquake of April 1, 2014, in northern Chile, a seismically prone area at the current time. The hardware includes the SG160-09 system, external Zephyr Geodetic-2 GNSS antenna, and high-speed Internet communication media. Both acceleration and displacement data was transmitted in real-time to the National Seismological Center in Santiago for real-time data processing using Earthworm / Early Bird software. Command/Control of the field station and real-time GNSS position correction are provided via the Pivot software suite. Data from the SG160-09 system was

Real time implementation and control validation of the wind energy conversion system

Science.gov (United States)

Sattar, Adnan

The purpose of the thesis is to analyze dynamic and transient characteristics of wind energy conversion systems including the stability issues in real time environment using the Real Time Digital Simulator (RTDS). There are different power system simulation tools available in the market. Real time digital simulator (RTDS) is one of the powerful tools among those. RTDS simulator has a Graphical User Interface called RSCAD which contains detail component model library for both power system and control relevant analysis. The hardware is based upon the digital signal processors mounted in the racks. RTDS simulator has the advantage of interfacing the real world signals from the external devices, hence used to test the protection and control system equipments. Dynamic and transient characteristics of the fixed and variable speed wind turbine generating systems (WTGSs) are analyzed, in this thesis. Static Synchronous Compensator (STATCOM) as a flexible ac transmission system (FACTS) device is used to enhance the fault ride through (FRT) capability of the fixed speed wind farm. Two level voltage source converter based STATCOM is modeled in both VSC small time-step and VSC large time-step of RTDS. The simulation results of the RTDS model system are compared with the off-line EMTP software i.e. PSCAD/EMTDC. A new operational scheme for a MW class grid-connected variable speed wind turbine driven permanent magnet synchronous generator (VSWT-PMSG) is developed. VSWT-PMSG uses fully controlled frequency converters for the grid interfacing and thus have the ability to control the real and reactive powers simultaneously. Frequency converters are modeled in the VSC small time-step of the RTDS and three phase realistic grid is adopted with RSCAD simulation through the use of optical analogue digital converter (OADC) card of the RTDS. Steady state and LVRT characteristics are carried out to validate the proposed operational scheme. Simulation results show good agreement with real

Bounds on achievable accuracy in analog optical linear-algebra processors

Science.gov (United States)

Batsell, Stephen G.; Walkup, John F.; Krile, Thomas F.

1990-07-01

Upper arid lower bounds on the number of bits of accuracy achievable are determined by applying a seconth-ortler statistical model to the linear algebra processor. The use of bounds was found necessary due to the strong signal-dependence of the noise at the output of the optical linear algebra processor (OLAP). 1 1. ACCURACY BOUNDS One of the limiting factors in applying OLAPs to real world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication ard addition operations spatial variations across arrays and crosstalk. We have previously examined these noise sources and determined a general model for the output noise mean and variance. The model demonstrates a strony signaldependency in the noise at the output of the processor which has been confirmed by our experiments. 1 We define accuracy similar to its definition for an analog signal input to an analog-to-digital (ND) converter. The number of bits of accuracy achievable is related to the log (base 2) of the number of separable levels at the P/D converter output. The number of separable levels is fouri by dividing the dynamic range by m times the standard deviation of the signal a. 2 Here m determines the error rate in the P/D conversion. The dynamic range can be expressed as the

Real-time vision systems

Energy Technology Data Exchange (ETDEWEB)

Johnson, R.; Hernandez, J.E.; Lu, Shin-yee [Lawrence Livermore National Lab., CA (United States)

1994-11-15

Many industrial and defence applications require an ability to make instantaneous decisions based on sensor input of a time varying process. Such systems are referred to as `real-time systems` because they process and act on data as it occurs in time. When a vision sensor is used in a real-time system, the processing demands can be quite substantial, with typical data rates of 10-20 million samples per second. A real-time Machine Vision Laboratory (MVL) was established in FY94 to extend our years of experience in developing computer vision algorithms to include the development and implementation of real-time vision systems. The laboratory is equipped with a variety of hardware components, including Datacube image acquisition and processing boards, a Sun workstation, and several different types of CCD cameras, including monochrome and color area cameras and analog and digital line-scan cameras. The equipment is reconfigurable for prototyping different applications. This facility has been used to support several programs at LLNL, including O Division`s Peacemaker and Deadeye Projects as well as the CRADA with the U.S. Textile Industry, CAFE (Computer Aided Fabric Inspection). To date, we have successfully demonstrated several real-time applications: bullet tracking, stereo tracking and ranging, and web inspection. This work has been documented in the ongoing development of a real-time software library.

Real-time SHVC software decoding with multi-threaded parallel processing

Science.gov (United States)

Gudumasu, Srinivas; He, Yuwen; Ye, Yan; He, Yong; Ryu, Eun-Seok; Dong, Jie; Xiu, Xiaoyu

2014-09-01

This paper proposes a parallel decoding framework for scalable HEVC (SHVC). Various optimization technologies are implemented on the basis of SHVC reference software SHM-2.0 to achieve real-time decoding speed for the two layer spatial scalability configuration. SHVC decoder complexity is analyzed with profiling information. The decoding process at each layer and the up-sampling process are designed in parallel and scheduled by a high level application task manager. Within each layer, multi-threaded decoding is applied to accelerate the layer decoding speed. Entropy decoding, reconstruction, and in-loop processing are pipeline designed with multiple threads based on groups of coding tree units (CTU). A group of CTUs is treated as a processing unit in each pipeline stage to achieve a better trade-off between parallelism and synchronization. Motion compensation, inverse quantization, and inverse transform modules are further optimized with SSE4 SIMD instructions. Simulations on a desktop with an Intel i7 processor 2600 running at 3.4 GHz show that the parallel SHVC software decoder is able to decode 1080p spatial 2x at up to 60 fps (frames per second) and 1080p spatial 1.5x at up to 50 fps for those bitstreams generated with SHVC common test conditions in the JCT-VC standardization group. The decoding performance at various bitrates with different optimization technologies and different numbers of threads are compared in terms of decoding speed and resource usage, including processor and memory.

A State-of-the-Art Review of the Real-Time Computer-Aided Study of the Writing Process

Science.gov (United States)

Abdel Latif, Muhammad M.

2008-01-01

Writing researchers have developed various methods for investigating the writing process since the 1970s. The early 1980s saw the occurrence of the real-time computer-aided study of the writing process that relies on the protocols generated by recording the computer screen activities as writers compose using the word processor. This article…

Robust real-time pattern matching using bayesian sequential hypothesis testing.

Science.gov (United States)

Pele, Ofir; Werman, Michael

2008-08-01

This paper describes a method for robust real time pattern matching. We first introduce a family of image distance measures, the "Image Hamming Distance Family". Members of this family are robust to occlusion, small geometrical transforms, light changes and non-rigid deformations. We then present a novel Bayesian framework for sequential hypothesis testing on finite populations. Based on this framework, we design an optimal rejection/acceptance sampling algorithm. This algorithm quickly determines whether two images are similar with respect to a member of the Image Hamming Distance Family. We also present a fast framework that designs a near-optimal sampling algorithm. Extensive experimental results show that the sequential sampling algorithm performance is excellent. Implemented on a Pentium 4 3 GHz processor, detection of a pattern with 2197 pixels, in 640 x 480 pixel frames, where in each frame the pattern rotated and was highly occluded, proceeds at only 0.022 seconds per frame.

The micro-processor controlled process radiation monitoring system for reactor safety systems

International Nuclear Information System (INIS)

Mizuno, K.; Noguchi, A.; Kumagami, S.; Gotoh, Y.; Kumahara, T.; Arita, S.

1986-01-01

Digital computers are soon expected to be applied to various real-time safety and safety-related systems in nuclear power plants. Hitachi is now engaged in the development of a micro-processor controlled process radiation monitoring system, which operates on digital processing methods employed with a log ratemeter. A newly defined methodology of design and test procedures is being applied as a means of software program verification for these safety systems. Recently implemented micro-processor technology will help to achieve an advanced man-machine interface and highly reliable performance. (author)

Video-based real-time on-street parking occupancy detection system

Science.gov (United States)

Bulan, Orhan; Loce, Robert P.; Wu, Wencheng; Wang, YaoRong; Bernal, Edgar A.; Fan, Zhigang

2013-10-01

Urban parking management is receiving significant attention due to its potential to reduce traffic congestion, fuel consumption, and emissions. Real-time parking occupancy detection is a critical component of on-street parking management systems, where occupancy information is relayed to drivers via smart phone apps, radio, Internet, on-road signs, or global positioning system auxiliary signals. Video-based parking occupancy detection systems can provide a cost-effective solution to the sensing task while providing additional functionality for traffic law enforcement and surveillance. We present a video-based on-street parking occupancy detection system that can operate in real time. Our system accounts for the inherent challenges that exist in on-street parking settings, including illumination changes, rain, shadows, occlusions, and camera motion. Our method utilizes several components from video processing and computer vision for motion detection, background subtraction, and vehicle detection. We also present three traffic law enforcement applications: parking angle violation detection, parking boundary violation detection, and exclusion zone violation detection, which can be integrated into the parking occupancy cameras as a value-added option. Our experimental results show that the proposed parking occupancy detection method performs in real-time at 5 frames/s and achieves better than 90% detection accuracy across several days of videos captured in a busy street block under various weather conditions such as sunny, cloudy, and rainy, among others.

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

Directory of Open Access Journals (Sweden)

Jian (Denny Lin

2014-05-01

Full Text Available With the advanced technology used to design VLSI (Very Large Scale Integration circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

Neural Network Based Real-time Correction of Transducer Dynamic Errors

Science.gov (United States)

Roj, J.

2013-12-01

In order to carry out real-time dynamic error correction of transducers described by a linear differential equation, a novel recurrent neural network was developed. The network structure is based on solving this equation with respect to the input quantity when using the state variables. It is shown that such a real-time correction can be carried out using simple linear perceptrons. Due to the use of a neural technique, knowledge of the dynamic parameters of the transducer is not necessary. Theoretical considerations are illustrated by the results of simulation studies performed for the modeled second order transducer. The most important properties of the neural dynamic error correction, when emphasizing the fundamental advantages and disadvantages, are discussed.

The FERMI-Elettra distributed real-time framework

International Nuclear Information System (INIS)

Pivetta, L.; Gaio, G.; Passuello, R.; Scalamera, G.

2012-01-01

FERMI-Elettra is a Free Electron Laser (FEL) based on a 1.5 GeV linac. The pulsed operation of the accelerator and the necessity to characterize and control each electron bunch requires synchronous acquisition of the beam diagnostics together with the ability to drive actuators in real-time at the linac repetition rate. The Adeos/Xenomai real-time extensions have been adopted in order to add real-time capabilities to the Linux based control system computers running the Tango software. A software communication protocol based on Gigabit Ethernet and known as Network Reflective Memory (NRM) has been developed to implement a shared memory across the whole control system, allowing computers to communicate in real-time. The NRM architecture, the real-time performance and the integration in the control system are described. (authors)

Heterogeneous reconfigurable processors for real-time baseband processing from algorithm to architecture

CERN Document Server

Zhang, Chenxin; Öwall, Viktor

2016-01-01

This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfigur...

Heterogeneous real-time computing in radio astronomy

Science.gov (United States)

Ford, John M.; Demorest, Paul; Ransom, Scott

2010-07-01

Modern computer architectures suited for general purpose computing are often not the best choice for either I/O-bound or compute-bound problems. Sometimes the best choice is not to choose a single architecture, but to take advantage of the best characteristics of different computer architectures to solve your problems. This paper examines the tradeoffs between using computer systems based on the ubiquitous X86 Central Processing Units (CPU's), Field Programmable Gate Array (FPGA) based signal processors, and Graphical Processing Units (GPU's). We will show how a heterogeneous system can be produced that blends the best of each of these technologies into a real-time signal processing system. FPGA's tightly coupled to analog-to-digital converters connect the instrument to the telescope and supply the first level of computing to the system. These FPGA's are coupled to other FPGA's to continue to provide highly efficient processing power. Data is then packaged up and shipped over fast networks to a cluster of general purpose computers equipped with GPU's, which are used for floating-point intensive computation. Finally, the data is handled by the CPU and written to disk, or further processed. Each of the elements in the system has been chosen for its specific characteristics and the role it can play in creating a system that does the most for the least, in terms of power, space, and money.

SABA: A Testbed for a Real-Time MIMO System

Directory of Open Access Journals (Sweden)

Brühl Lars

2006-01-01

Full Text Available The growing demand for high data rates for wireless communication systems leads to the development of new technologies to increase the channel capacity thus increasing the data rate. MIMO (multiple-input multiple-output systems are best qualified for these applications. In this paper, we present a MIMO test environment for high data rate transmissions in frequency-selective environments. An overview of the testbed is given, including the analyzed algorithms, the digital signal processing with a new highly parallel processor to perform the algorithms in real time, as well as the analog front-ends. A brief overview of the influence of polarization on the channel capacity is given as well.

Design of real-time communication system for image recognition based colony picking instrument

Science.gov (United States)

Wang, Qun; Zhang, Rongfu; Yan, Hua; Wu, Huamin

2017-11-01

In order to aachieve autommated observatiion and pickinng of monocloonal colonies, an overall dessign and realizzation of real-time commmunication system based on High-throoughput monooclonal auto-piicking instrumment is propossed. The real-time commmunication system is commposed of PCC-PLC commuunication systtem and Centrral Control CComputer (CCC)-PLC communicatioon system. Bassed on RS232 synchronous serial communnication methood to develop a set of dedicated shoort-range commmunication prootocol betweenn the PC and PPLC. Furthermmore, the systemm uses SQL SSERVER database to rrealize the dataa interaction between PC andd CCC. Moreoover, the commmunication of CCC and PC, adopted Socket Ethernnet communicaation based on TCP/IP protoccol. TCP full-dduplex data cannnel to ensure real-time data eexchange as well as immprove system reliability andd security. We tested the commmunication syystem using sppecially develooped test software, thee test results show that the sysstem can realizze the communnication in an eefficient, safe aand stable way between PLC, PC andd CCC, keep thhe real-time conntrol to PLC annd colony inforrmation collecttion.

A Kinect-Based Segmentation of Touching-Pigs for Real-Time Monitoring

Directory of Open Access Journals (Sweden)

Miso Ju

2018-05-01

Full Text Available Segmenting touching-pigs in real-time is an important issue for surveillance cameras intended for the 24-h tracking of individual pigs. However, methods to do so have not yet been reported. We particularly focus on the segmentation of touching-pigs in a crowded pig room with low-contrast images obtained using a Kinect depth sensor. We reduce the execution time by combining object detection techniques based on a convolutional neural network (CNN with image processing techniques instead of applying time-consuming operations, such as optimization-based segmentation. We first apply the fastest CNN-based object detection technique (i.e., You Only Look Once, YOLO to solve the separation problem for touching-pigs. If the quality of the YOLO output is not satisfied, then we try to find the possible boundary line between the touching-pigs by analyzing the shape. Our experimental results show that this method is effective to separate touching-pigs in terms of both accuracy (i.e., 91.96% and execution time (i.e., real-time execution, even with low-contrast images obtained using a Kinect depth sensor.

Near Real Time Ship Detection Experiments

Science.gov (United States)

Brusch, S.; Lehner, S.; Schwarz, E.; Fritz, T.

2010-04-01

A new Near Real Time (NRT) ship detection processor SAINT (SAR AIS Integrated Toolbox) was developed in the framework of the ESA project MARISS. Data are received at DLRs ground segment DLR-BN (Neustrelitz, Germany). Results of the ship detection are available on ftp server within 30 min after the acquisition started. The detectability of ships on Synthetic Aperture Radar (SAR) ERS-2, ENVISAT ASAR and TerraSAR-X (TS-X) images is validated by coastal (live) AIS and space AIS. The monitoring areas chosen for surveillance are the North-, Baltic Sea, and Cape Town. The detectability in respect to environmental parameters like wind field, sea state, currents and changing coastlines due to tidal effects is investigated. In the South Atlantic a tracking experiment of the German research vessel Polarstern has been performed. Issues of piracy in particular in respect to ships hijacked at the Somali coast are discussed. Some examples using high resolution images from TerraSAR-X are given.

Improvements to Web Toolkits for Antelope-based Real-time Monitoring Systems

Science.gov (United States)

Lindquist, K. G.; Newman, R. L.; Vernon, F. L.; Hansen, T. S.; Orcutt, J.

2005-12-01

The Antelope Environmental Monitoring System (http://www.brtt.com) is a robust middleware architecture for near-real-time data collection, analysis, archiving and distribution. Antelope has an extensive toolkit allowing users to interact directly with their datasets. A rudimentary interface was developed in previous work between Antelope and the web-scripting language PHP (The PHP language is described in more detail at http://www.php.net). This interface allowed basic application development for remote access to and interaction with near-real-time data through a World Wide Web interface. We have added over 70 new functions for the Antelope interface to PHP, providing a solid base for web-scripting of near-real-time Antelope database applications. In addition, we have designed a new structure for web sites to be created from the Antelope platform, including PHP applications and Perl CGI scripts as well as static pages. Finally we have constructed the first version of the dbwebproject program, designed to dynamically create and maintain web-sites from specified recipes. These tools have already proven valuable for the creation of web tools for the dissemination of and interaction with near-real-time data streams from multi-signal-domain real-time sensor networks. We discuss current and future directions of this work in the context of the ROADNet project. Examples and applications of these core tools are elaborated in a companion presentation in this session (Newman et al., AGU 2005, session IN06).

Real-Time Fixed-Order Lateral H2 Controller for Micro Air Vehicle

Directory of Open Access Journals (Sweden)

Meenakshi M.

2011-01-01

Full Text Available This paper presents the design and development of a fixed low-order, robust H2 controller for a micro air vehicle (MAV named Sarika-2. The controller synthesis uses strengthened discrete optimal projection equations and frequency-dependent performance index to achieve robust performance and stability. A single fixed gain low-order dynamic controller provides simultaneous stabilization, disturbance rejection, and sensor noise attenuation over the entire flight speed range of 16 m/sec to 26 m/sec. Comparative study indicates that the low-order H2-controller achieves robust performance levels similar to that of full order controller. Subsequently, the controller is implemented on a digital signal processor-based flight computer and is validated through the real time hardware in loop simulation. The responses obtained with hardware in loop simulation compares well with those obtained from the offline simulation.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

Science.gov (United States)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

Real-Time Control of an Articulatory-Based Speech Synthesizer for Brain Computer Interfaces.

Directory of Open Access Journals (Sweden)

Florent Bocquelet

2016-11-01

Full Text Available Restoring natural speech in paralyzed and aphasic people could be achieved using a Brain-Computer Interface (BCI controlling a speech synthesizer in real-time. To reach this goal, a prerequisite is to develop a speech synthesizer producing intelligible speech in real-time with a reasonable number of control parameters. We present here an articulatory-based speech synthesizer that can be controlled in real-time for future BCI applications. This synthesizer converts movements of the main speech articulators (tongue, jaw, velum, and lips into intelligible speech. The articulatory-to-acoustic mapping is performed using a deep neural network (DNN trained on electromagnetic articulography (EMA data recorded on a reference speaker synchronously with the produced speech signal. This DNN is then used in both offline and online modes to map the position of sensors glued on different speech articulators into acoustic parameters that are further converted into an audio signal using a vocoder. In offline mode, highly intelligible speech could be obtained as assessed by perceptual evaluation performed by 12 listeners. Then, to anticipate future BCI applications, we further assessed the real-time control of the synthesizer by both the reference speaker and new speakers, in a closed-loop paradigm using EMA data recorded in real time. A short calibration period was used to compensate for differences in sensor positions and articulatory differences between new speakers and the reference speaker. We found that real-time synthesis of vowels and consonants was possible with good intelligibility. In conclusion, these results open to future speech BCI applications using such articulatory-based speech synthesizer.

Mixed-mode Operating System for Real-time Performance

Directory of Open Access Journals (Sweden)

M.M. Hasan

2017-11-01

Full Text Available The purpose of the mixed-mode system research is to handle devices with the accuracy of real-time systems and at the same time, having all the benefits and facilities of a matured Graphic User Interface (GUI operating system which is typically nonreal-time. This mixed-mode operating system comprising of a real-time portion and a non-real-time portion was studied and implemented to identify the feasibilities and performances in practical applications (in the context of scheduled the real-time events. In this research an i8751 microcontroller-based hardware was used to measure the performance of the system in real-time-only as well as non-real-time-only configurations. The real-time portion is an 486DX-40 IBM PC system running under DOS-based realtime kernel and the non-real-time portion is a Pentium III based system running under Windows NT. It was found that mixed-mode systems performed as good as a typical realtime system and in fact, gave many additional benefits such as simplified/modular programming and load tolerance.

Recent developments in predictive uncertainty assessment based on the model conditional processor approach

Directory of Open Access Journals (Sweden)

G. Coccia

2011-10-01

Full Text Available The work aims at discussing the role of predictive uncertainty in flood forecasting and flood emergency management, its relevance to improve the decision making process and the techniques to be used for its assessment.

Real time flood forecasting requires taking into account predictive uncertainty for a number of reasons. Deterministic hydrological/hydraulic forecasts give useful information about real future events, but their predictions, as usually done in practice, cannot be taken and used as real future occurrences but rather used as pseudo-measurements of future occurrences in order to reduce the uncertainty of decision makers. Predictive Uncertainty (PU is in fact defined as the probability of occurrence of a future value of a predictand (such as water level, discharge or water volume conditional upon prior observations and knowledge as well as on all the information we can obtain on that specific future value from model forecasts. When dealing with commensurable quantities, as in the case of floods, PU must be quantified in terms of a probability distribution function which will be used by the emergency managers in their decision process in order to improve the quality and reliability of their decisions.

After introducing the concept of PU, the presently available processors are introduced and discussed in terms of their benefits and limitations. In this work the Model Conditional Processor (MCP has been extended to the possibility of using two joint Truncated Normal Distributions (TNDs, in order to improve adaptation to low and high flows.

The paper concludes by showing the results of the application of the MCP on two case studies, the Po river in Italy and the Baron Fork river, OK, USA. In the Po river case the data provided by the Civil Protection of the Emilia Romagna region have been used to implement an operational example, where the predicted variable is the observed water level. In the Baron Fork River

Real-Time Data Processing in the muon system of the D0 detector

International Nuclear Information System (INIS)

Neeti Parashar et al.

2001-01-01

This paper presents a real-time application of the 16-bit fixed point Digital Signal Processors (DSPs), in the Muon System of the D0 detector located at the Fermilab Tevatron, presently the world's highest-energy hadron collider. As part of the Upgrade for a run beginning in the year 2000, the system is required to process data at an input event rate of 10 KHz without incurring significant deadtime in readout. The ADSP21csp01 processor has high I/O bandwidth, single cycle instruction execution and fast task switching support to provide efficient multisignal processing. The processor's internal memory consists of 4K words of Program Memory and 4K words of Data Memory. In addition there is an external memory of 32K words for general event buffering and 16K words of Dual port Memory for input data queuing. This DSP fulfills the requirement of the Muon subdetector systems for data readout. All error handling, buffering, formatting and transferring of the data to the various trigger levels of the data acquisition system is done in software. The algorithms developed for the system complete these tasks in about 20 micros per event

Mixed - mode Operating System for Real - time Performance

Directory of Open Access Journals (Sweden)

Hasan M. M.

2017-11-01

Full Text Available The purpose of the mixed-mode system research is to handle devices with the accuracy of real-time systems and at the same time, having all the benefits and facilities of a matured Graphic User Interface(GUIoperating system which is typicallynon-real-time. This mixed-mode operating system comprising of a real-time portion and a non-real-time portion was studied and implemented to identify the feasibilities and performances in practical applications (in the context of scheduled the real-time events. In this research an i8751 microcontroller-based hardware was used to measure the performance of the system in real-time-only as well as non-real-time-only configurations. The real-time portion is an 486DX-40 IBM PC system running under DOS-based real-time kernel and the non-real-time portion is a Pentium IIIbased system running under Windows NT. It was found that mixed-mode systems performed as good as a typical real-time system and in fact, gave many additional benefits such as simplified/modular programming and load tolerance.

Cluster Computing For Real Time Seismic Array Analysis.

Science.gov (United States)

Martini, M.; Giudicepietro, F.

A seismic array is an instrument composed by a dense distribution of seismic sen- sors that allow to measure the directional properties of the wavefield (slowness or wavenumber vector) radiated by a seismic source. Over the last years arrays have been widely used in different fields of seismological researches. In particular they are applied in the investigation of seismic sources on volcanoes where they can be suc- cessfully used for studying the volcanic microtremor and long period events which are critical for getting information on the volcanic systems evolution. For this reason arrays could be usefully employed for the volcanoes monitoring, however the huge amount of data produced by this type of instruments and the processing techniques which are quite time consuming limited their potentiality for this application. In order to favor a direct application of arrays techniques to continuous volcano monitoring we designed and built a small PC cluster able to near real time computing the kinematics properties of the wavefield (slowness or wavenumber vector) produced by local seis- mic source. The cluster is composed of 8 Intel Pentium-III bi-processors PC working at 550 MHz, and has 4 Gigabytes of RAM memory. It runs under Linux operating system. The developed analysis software package is based on the Multiple SIgnal Classification (MUSIC) algorithm and is written in Fortran. The message-passing part is based upon the LAM programming environment package, an open-source imple- mentation of the Message Passing Interface (MPI). The developed software system includes modules devote to receiving date by internet and graphical applications for the continuous displaying of the processing results. The system has been tested with a data set collected during a seismic experiment conducted on Etna in 1999 when two dense seismic arrays have been deployed on the northeast and the southeast flanks of this volcano. A real time continuous acquisition system has been simulated by

A system for EPID-based real-time treatment delivery verification during dynamic IMRT treatment.

Science.gov (United States)

Fuangrod, Todsaporn; Woodruff, Henry C; van Uytven, Eric; McCurdy, Boyd M C; Kuncic, Zdenka; O'Connor, Daryl J; Greer, Peter B

2013-09-01

To design and develop a real-time electronic portal imaging device (EPID)-based delivery verification system for dynamic intensity modulated radiation therapy (IMRT) which enables detection of gross treatment delivery errors before delivery of substantial radiation to the patient. The system utilizes a comprehensive physics-based model to generate a series of predicted transit EPID image frames as a reference dataset and compares these to measured EPID frames acquired during treatment. The two datasets are using MLC aperture comparison and cumulative signal checking techniques. The system operation in real-time was simulated offline using previously acquired images for 19 IMRT patient deliveries with both frame-by-frame comparison and cumulative frame comparison. Simulated error case studies were used to demonstrate the system sensitivity and performance. The accuracy of the synchronization method was shown to agree within two control points which corresponds to approximately ∼1% of the total MU to be delivered for dynamic IMRT. The system achieved mean real-time gamma results for frame-by-frame analysis of 86.6% and 89.0% for 3%, 3 mm and 4%, 4 mm criteria, respectively, and 97.9% and 98.6% for cumulative gamma analysis. The system can detect a 10% MU error using 3%, 3 mm criteria within approximately 10 s. The EPID-based real-time delivery verification system successfully detected simulated gross errors introduced into patient plan deliveries in near real-time (within 0.1 s). A real-time radiation delivery verification system for dynamic IMRT has been demonstrated that is designed to prevent major mistreatments in modern radiation therapy.

A fast density-based clustering algorithm for real-time Internet of Things stream.

Science.gov (United States)

Amini, Amineh; Saboohi, Hadi; Wah, Teh Ying; Herawan, Tutut

2014-01-01

Data streams are continuously generated over time from Internet of Things (IoT) devices. The faster all of this data is analyzed, its hidden trends and patterns discovered, and new strategies created, the faster action can be taken, creating greater value for organizations. Density-based method is a prominent class in clustering data streams. It has the ability to detect arbitrary shape clusters, to handle outlier, and it does not need the number of clusters in advance. Therefore, density-based clustering algorithm is a proper choice for clustering IoT streams. Recently, several density-based algorithms have been proposed for clustering data streams. However, density-based clustering in limited time is still a challenging issue. In this paper, we propose a density-based clustering algorithm for IoT streams. The method has fast processing time to be applicable in real-time application of IoT devices. Experimental results show that the proposed approach obtains high quality results with low computation time on real and synthetic datasets.

Using a digital signal processor as a data stream controller for digital subtraction angiography

International Nuclear Information System (INIS)

Meng, J.D.; Katz, J.E.

1991-10-01

High speed, flexibility, and good arithmetic abilities make digital signal processors (DSP) a good choice as input/output controllers for real time applications. The DSP can be made to pre-process data in real time to reduce data volume, to open early windows on what is being acquired and to implement local servo loops. We present an example of a DSP as an input/output controller for a digital subtraction angiographic imaging system. The DSP pre-processes the raw data, reducing data volume by a factor of two, and is potentially capable of producing real-time subtracted images for immediate display

Development of a processor embedded timing unit for the synchronized operation in KSTAR

Energy Technology Data Exchange (ETDEWEB)

Lee, Woongryol, E-mail: wrlee@nfri.re.kr; Lee, Taegu; Hong, Jaesic

2016-11-15

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

Development of a processor embedded timing unit for the synchronized operation in KSTAR

International Nuclear Information System (INIS)

Lee, Woongryol; Lee, Taegu; Hong, Jaesic

2016-01-01

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

A SiPM based real time dosimeter for radiotherapic beams

Energy Technology Data Exchange (ETDEWEB)

Berra, A., E-mail: alessandro.berra@gmail.it [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11 22100 Como (Italy); Conti, V. [Ospedale Sant' Anna, Servizio di Fisica Sanitaria, Como (Italy); Lietti, D.; Milan, L.; Novati, C. [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11 22100 Como (Italy); Ostinelli, A. [Ospedale Sant' Anna, Servizio di Fisica Sanitaria, Como (Italy); Prest, M.; Romanó, C. [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11 22100 Como (Italy); Vallazza, E. [INFN sezione di Trieste (Italy)

2015-02-11

This paper describes the development of a scintillator dosimeter prototype for radiotherapic applications based on plastic scintillating fibers readout by Silicon PhotoMultipliers. The dosimeter, whose probes are water equivalent, could be used for quality control measurements, beam characterization and in vivo dosimetry, allowing a real time measurement of the dose spatial distribution. This paper describes the preliminary percentual depth dose scan performed with clinical 6 and 18 MV photon beams, comparing the results with a reference curve. The measurements were performed using a Varian Clinac iX linear accelerator at the Radiotherapy Department of the St. Anna Hospital in Como (IT). The prototype has given promising results, allowing real time measurements of relative dose without applying any correction factors.

Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

International Nuclear Information System (INIS)

Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

2016-01-01

The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

Bank switched memory interface for an image processor

International Nuclear Information System (INIS)

Barron, M.; Downward, J.

1980-09-01

A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

Real Time Engineering Analysis Based on a Generative Component Implementation

DEFF Research Database (Denmark)

Kirkegaard, Poul Henning; Klitgaard, Jens

2007-01-01

The present paper outlines the idea of a conceptual design tool with real time engineering analysis which can be used in the early conceptual design phase. The tool is based on a parametric approach using Generative Components with embedded structural analysis. Each of these components uses the g...

Real-Time Hand Position Sensing Technology Based on Human Body Electrostatics

Directory of Open Access Journals (Sweden)

Kai Tang

2018-05-01

Full Text Available Non-contact human-computer interactions (HCI based on hand gestures have been widely investigated. Here, we present a novel method to locate the real-time position of the hand using the electrostatics of the human body. This method has many advantages, including a delay of less than one millisecond, low cost, and does not require a camera or wearable devices. A formula is first created to sense array signals with five spherical electrodes. Next, a solving algorithm for the real-time measured hand position is introduced and solving equations for three-dimensional coordinates of hand position are obtained. A non-contact real-time hand position sensing system was established to perform verification experiments, and the principle error of the algorithm and the systematic noise were also analyzed. The results show that this novel technology can determine the dynamic parameters of hand movements with good robustness to meet the requirements of complicated HCI.

Real-time pricing strategy of micro-grid energy centre considering price-based demand response

Science.gov (United States)

Xu, Zhiheng; Zhang, Yongjun; Wang, Gan

2017-07-01

With the development of energy conversion technology such as power to gas (P2G), fuel cell and so on, the coupling between energy sources becomes more and more closely. Centralized dispatch among electricity, natural gas and heat will become a trend. With the goal of maximizing the system revenue, this paper establishes the model of micro-grid energy centre based on energy hub. According to the proposed model, the real-time pricing strategy taking into account price-based demand response of load is developed. And the influence of real-time pricing strategy on the peak load shifting is discussed. In addition, the impact of wind power predicted inaccuracy on real-time pricing strategy is analysed.

Loss less real-time data compression based on LZO for steady-state Tokamak DAS

International Nuclear Information System (INIS)

Pujara, H.D.; Sharma, Manika

2008-01-01

The evolution of data acquisition system (DAS) for steady-state operation of Tokamak has been technology driven. Steady-state Tokamak demands a data acquisition system which is capable enough to acquire data losslessly from diagnostics. The needs of loss less continuous acquisition have a significant effect on data storage and takes up a greater portion of any data acquisition systems. Another basic need of steady state of nature of operation demands online viewing of data which loads the LAN significantly. So there is strong demand for something that would control the expansion of both these portion by a way of employing compression technique in real time. This paper presents a data acquisition systems employing real-time data compression technique based on LZO. It is a data compression library which is suitable for data compression and decompression in real time. The algorithm used favours speed over compression ratio. The system has been rigged up based on PXI bus and dual buffer mode architecture is implemented for loss less acquisition. The acquired buffer is compressed in real time and streamed to network and hard disk for storage. Observed performance of measure on various data type like binary, integer float, types of different type of wave form as well as compression timing overheads has been presented in the paper. Various software modules for real-time acquiring, online viewing of data on network nodes have been developed in LabWindows/CVI based on client server architecture

4g-Based Specialty Vehicles Real-Time Monitoring System Design and Implementation

Directory of Open Access Journals (Sweden)

Zhuang Yu-Feng

2017-01-01

Full Text Available In the future development of natural gas transportation industry, emerging ITS technology will be applied more and more, aiming at integrating precise positioning technology, geographic information system technology, database technology, multimedia technology and modern communication technology, sensor network technology and video capture technology, so as to achieve the transport steam (oil vehicles in real time monitoring and management. The main research content of this paper is to design and research the monitoring and locating system of luck (oil vehicle based on 4G on Android System. Real-time monitoring and alarming by sensor module, real-time video recording and uploading through camera module, real-time position recording and uploading through GPS module, vehicle navigation module and quick alarm module, which is composed of five parts. The system is the application of new intelligent transport technology in the field of special vehicle transport. It apply electronic information technology and internet of things technology to the vehicle system, so we can monitor natural gas and other special dangerous goods anytime, anywhere.

Dense time discretization technique for verification of real time systems

International Nuclear Information System (INIS)

Makackas, Dalius; Miseviciene, Regina

2016-01-01

Verifying the real-time system there are two different models to control the time: discrete and dense time based models. This paper argues a novel verification technique, which calculates discrete time intervals from dense time in order to create all the system states that can be reached from the initial system state. The technique is designed for real-time systems specified by a piece-linear aggregate approach. Key words: real-time system, dense time, verification, model checking, piece-linear aggregate

Compiling models into real-time systems

International Nuclear Information System (INIS)

Dormoy, J.L.; Cherriaux, F.; Ancelin, J.

1992-08-01

This paper presents an architecture for building real-time systems from models, and model-compiling techniques. This has been applied for building a real-time model-based monitoring system for nuclear plants, called KSE, which is currently being used in two plants in France. We describe how we used various artificial intelligence techniques for building it: a model-based approach, a logical model of its operation, a declarative implementation of these models, and original knowledge-compiling techniques for automatically generating the real-time expert system from those models. Some of those techniques have just been borrowed from the literature, but we had to modify or invent other techniques which simply did not exist. We also discuss two important problems, which are often underestimated in the artificial intelligence literature: size, and errors. Our architecture, which could be used in other applications, combines the advantages of the model-based approach with the efficiency requirements of real-time applications, while in general model-based approaches present serious drawbacks on this point

Compiling models into real-time systems

International Nuclear Information System (INIS)

Dormoy, J.L.; Cherriaux, F.; Ancelin, J.

1992-08-01

This paper presents an architecture for building real-time systems from models, and model-compiling techniques. This has been applied for building a real-time model-base monitoring system for nuclear plants, called KSE, which is currently being used in two plants in France. We describe how we used various artificial intelligence techniques for building it: a model-based approach, a logical model of its operation, a declarative implementation of these models, and original knowledge-compiling techniques for automatically generating the real-time expert system from those models. Some of those techniques have just been borrowed from the literature, but we had to modify or invent other techniques which simply did not exist. We also discuss two important problems, which are often underestimated in the artificial intelligence literature: size, and errors. Our architecture, which could be used in other applications, combines the advantages of the model-based approach with the efficiency requirements of real-time applications, while in general model-based approaches present serious drawbacks on this point

The Molen Polymorphic Media Processor

NARCIS (Netherlands)

Kuzmanov, G.K.

2004-01-01

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

Near Real Time Processing Chain for Suomi NPP Satellite Data

Science.gov (United States)

Monsorno, Roberto; Cuozzo, Giovanni; Costa, Armin; Mateescu, Gabriel; Ventura, Bartolomeo; Zebisch, Marc

2014-05-01

Since 2009, the EURAC satellite receiving station, located at Corno del Renon, in a free obstacle site at 2260 m a.s.l., has been acquiring data from Aqua and Terra NASA satellites equipped with Moderate Resolution Imaging Spectroradiometer (MODIS) sensors. The experience gained with this local ground segmenthas given the opportunity of adapting and modifying the processing chain for MODIS data to the Suomi NPP, the natural successor to Terra and Aqua satellites. The processing chain, initially implemented by mean of a proprietary system supplied by Seaspace and Advanced Computer System, was further developed by EURAC's Institute for Applied Remote Sensing engineers. Several algorithms have been developed using MODIS and Visible Infrared Imaging Radiometer Suite (VIIRS) data to produce Snow Cover, Particulate Matter estimation and Meteo maps. These products are implemented on a common processor structure based on the use of configuration files and a generic processor. Data and products have then automatically delivered to the customers such as the Autonomous Province of Bolzano-Civil Protection office. For the processing phase we defined two goals: i) the adaptation and implementation of the products already available for MODIS (and possibly new ones) to VIIRS, that is one of the sensors onboard Suomi NPP; ii) the use of an open source processing chain in order to process NPP data in Near Real Time, exploiting the knowledge we acquired on parallel computing. In order to achieve the second goal, the S-NPP data received and ingested are sent as input to RT-STPS (Real-time Software Telemetry Processing System) software developed by the NASA Direct Readout Laboratory 1 (DRL) that gives as output RDR files (Raw Data Record) for VIIRS, ATMS (Advanced Technology Micorwave Sounder) and CrIS (Cross-track Infrared Sounder)sensors. RDR are then transferred to a server equipped with CSPP2 (Community Satellite Processing Package) software developed by the University of

Real time 3D structural and Doppler OCT imaging on graphics processing units

Science.gov (United States)

Sylwestrzak, Marcin; Szlag, Daniel; Szkulmowski, Maciej; Gorczyńska, Iwona; Bukowska, Danuta; Wojtkowski, Maciej; Targowski, Piotr

2013-03-01

In this report the application of graphics processing unit (GPU) programming for real-time 3D Fourier domain Optical Coherence Tomography (FdOCT) imaging with implementation of Doppler algorithms for visualization of the flows in capillary vessels is presented. Generally, the time of the data processing of the FdOCT data on the main processor of the computer (CPU) constitute a main limitation for real-time imaging. Employing additional algorithms, such as Doppler OCT analysis, makes this processing even more time consuming. Lately developed GPUs, which offers a very high computational power, give a solution to this problem. Taking advantages of them for massively parallel data processing, allow for real-time imaging in FdOCT. The presented software for structural and Doppler OCT allow for the whole processing with visualization of 2D data consisting of 2000 A-scans generated from 2048 pixels spectra with frame rate about 120 fps. The 3D imaging in the same mode of the volume data build of 220 × 100 A-scans is performed at a rate of about 8 frames per second. In this paper a software architecture, organization of the threads and optimization applied is shown. For illustration the screen shots recorded during real time imaging of the phantom (homogeneous water solution of Intralipid in glass capillary) and the human eye in-vivo is presented.

A system for EPID-based real-time treatment delivery verification during dynamic IMRT treatment

Energy Technology Data Exchange (ETDEWEB)

Fuangrod, Todsaporn [Faculty of Engineering and Built Environment, School of Electrical Engineering and Computer Science, the University of Newcastle, NSW 2308 (Australia); Woodruff, Henry C.; O’Connor, Daryl J. [Faculty of Science and IT, School of Mathematical and Physical Sciences, the University of Newcastle, NSW 2308 (Australia); Uytven, Eric van; McCurdy, Boyd M. C. [Division of Medical Physics, CancerCare Manitoba, 675 McDermot Avenue, Winnipeg, Manitoba R3E 0V9 (Canada); Department of Physics and Astronomy, University of Manitoba, Winnipeg, Manitoba R3T 2N2 (Canada); Department of Radiology, University of Manitoba, Winnipeg, Manitoba R3T 2N2 (Canada); Kuncic, Zdenka [School of Physics, University of Sydney, Sydney, NSW 2006 (Australia); Greer, Peter B. [Faculty of Science and IT, School of Mathematical and Physical Sciences, the University of Newcastle, NSW 2308, Australia and Department of Radiation Oncology, Calvary Mater Newcastle Hospital, Locked Bag 7, Hunter region Mail Centre, Newcastle, NSW 2310 (Australia)

2013-09-15

Purpose: To design and develop a real-time electronic portal imaging device (EPID)-based delivery verification system for dynamic intensity modulated radiation therapy (IMRT) which enables detection of gross treatment delivery errors before delivery of substantial radiation to the patient.Methods: The system utilizes a comprehensive physics-based model to generate a series of predicted transit EPID image frames as a reference dataset and compares these to measured EPID frames acquired during treatment. The two datasets are using MLC aperture comparison and cumulative signal checking techniques. The system operation in real-time was simulated offline using previously acquired images for 19 IMRT patient deliveries with both frame-by-frame comparison and cumulative frame comparison. Simulated error case studies were used to demonstrate the system sensitivity and performance.Results: The accuracy of the synchronization method was shown to agree within two control points which corresponds to approximately ∼1% of the total MU to be delivered for dynamic IMRT. The system achieved mean real-time gamma results for frame-by-frame analysis of 86.6% and 89.0% for 3%, 3 mm and 4%, 4 mm criteria, respectively, and 97.9% and 98.6% for cumulative gamma analysis. The system can detect a 10% MU error using 3%, 3 mm criteria within approximately 10 s. The EPID-based real-time delivery verification system successfully detected simulated gross errors introduced into patient plan deliveries in near real-time (within 0.1 s).Conclusions: A real-time radiation delivery verification system for dynamic IMRT has been demonstrated that is designed to prevent major mistreatments in modern radiation therapy.

A system for EPID-based real-time treatment delivery verification during dynamic IMRT treatment

International Nuclear Information System (INIS)

Fuangrod, Todsaporn; Woodruff, Henry C.; O’Connor, Daryl J.; Uytven, Eric van; McCurdy, Boyd M. C.; Kuncic, Zdenka; Greer, Peter B.

2013-01-01

Purpose: To design and develop a real-time electronic portal imaging device (EPID)-based delivery verification system for dynamic intensity modulated radiation therapy (IMRT) which enables detection of gross treatment delivery errors before delivery of substantial radiation to the patient.Methods: The system utilizes a comprehensive physics-based model to generate a series of predicted transit EPID image frames as a reference dataset and compares these to measured EPID frames acquired during treatment. The two datasets are using MLC aperture comparison and cumulative signal checking techniques. The system operation in real-time was simulated offline using previously acquired images for 19 IMRT patient deliveries with both frame-by-frame comparison and cumulative frame comparison. Simulated error case studies were used to demonstrate the system sensitivity and performance.Results: The accuracy of the synchronization method was shown to agree within two control points which corresponds to approximately ∼1% of the total MU to be delivered for dynamic IMRT. The system achieved mean real-time gamma results for frame-by-frame analysis of 86.6% and 89.0% for 3%, 3 mm and 4%, 4 mm criteria, respectively, and 97.9% and 98.6% for cumulative gamma analysis. The system can detect a 10% MU error using 3%, 3 mm criteria within approximately 10 s. The EPID-based real-time delivery verification system successfully detected simulated gross errors introduced into patient plan deliveries in near real-time (within 0.1 s).Conclusions: A real-time radiation delivery verification system for dynamic IMRT has been demonstrated that is designed to prevent major mistreatments in modern radiation therapy

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

CERN Document Server

Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

2014-01-01

The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

Real-time particle image velocimetry based on FPGA technology;Velocimetria PIV en tiempo real basada en logica programable FPGA

Energy Technology Data Exchange (ETDEWEB)

Iriarte Munoz, Jose Miguel [Universidad Nacional de Cuyo, Instituto Balseiro, Centro Atomico Bariloche (Argentina)

2008-07-01

Particle image velocimetry (PIV), based on laser sheet, is a method for image processing and calculation of distributed velocity fields.It is well established as a fluid dynamics measurement tool, being applied to liquid, gases and multiphase flows.Images of particles are processed by means of computationally demanding algorithms, what makes its real-time implementation difficult.The most probable displacements are found applying two dimensional cross-correlation function. In this work, we detail how it is possible to achieve real-time visualization of PIV method by designing an adaptive embedded architecture based on FPGA technology.We show first results of a physical field of velocity calculated by this platform system in a real-time approach.;La velocimetria por imagenes de particulas (PIV), basada en plano laser, es una potente herramienta de medicion en dinamica de fluidos, capaz de medir sin grandes errores, un campo de velocidades distribuido en liquidos, gases y flujo multifase.Los altos requerimientos computacionales de los algoritmos PIV dificultan su empleo en tiempo-real.En este trabajo presentamos el diseno de una plataforma basada en tecnologia FPGA para capturar video y procesar en tiempo real el algoritmo de correlacion cruzada bidimensional.Mostramos resultados de un primer abordaje de la captura de imagenes y procesamiento de un campo fisico de velocidades en tiempo real.

Coherent time-stretch transformation for real-time capture of wideband signals.

Science.gov (United States)

Buckley, Brandon W; Madni, Asad M; Jalali, Bahram

2013-09-09

Time stretch transformation of wideband waveforms boosts the performance of analog-to-digital converters and digital signal processors by slowing down analog electrical signals before digitization. The transform is based on dispersive Fourier transformation implemented in the optical domain. A coherent receiver would be ideal for capturing the time-stretched optical signal. Coherent receivers offer improved sensitivity, allow for digital cancellation of dispersion-induced impairments and optical nonlinearities, and enable decoding of phase-modulated optical data formats. Because time-stretch uses a chirped broadband (>1 THz) optical carrier, a new coherent detection technique is required. In this paper, we introduce and demonstrate coherent time stretch transformation; a technique that combines dispersive Fourier transform with optically broadband coherent detection.

Computation Offloading for Frame-Based Real-Time Tasks under Given Server Response Time Guarantees

Directory of Open Access Journals (Sweden)

Anas S. M. Toma

2014-11-01

Full Text Available Computation offloading has been adopted to improve the performance of embedded systems by offloading the computation of some tasks, especially computation-intensive tasks, to servers or clouds. This paper explores computation offloading for real-time tasks in embedded systems, provided given response time guarantees from the servers, to decide which tasks should be offloaded to get the results in time. We consider frame-based real-time tasks with the same period and relative deadline. When the execution order of the tasks is given, the problem can be solved in linear time. However, when the execution order is not specified, we prove that the problem is NP-complete. We develop a pseudo-polynomial-time algorithm for deriving feasible schedules, if they exist.  An approximation scheme is also developed to trade the error made from the algorithm and the complexity. Our algorithms are extended to minimize the period/relative deadline of the tasks for performance maximization. The algorithms are evaluated with a case study for a surveillance system and synthesized benchmarks.

CHIMERA II - A real-time multiprocessing environment for sensor-based robot control

Science.gov (United States)

Stewart, David B.; Schmitz, Donald E.; Khosla, Pradeep K.

1989-01-01

A multiprocessing environment for a wide variety of sensor-based robot system, providing the flexibility, performance, and UNIX-compatible interface needed for fast development of real-time code is addressed. The requirements imposed on the design of a programming environment for sensor-based robotic control is outlined. The details of the current hardware configuration are presented, along with the details of the CHIMERA II software. Emphasis is placed on the kernel, low-level interboard communication, user interface, extended file system, user-definable and dynamically selectable real-time schedulers, remote process synchronization, and generalized interprocess communication. A possible implementation of a hierarchical control model, the NASA/NBS standard reference model for telerobot control system is demonstrated.

Monte Carlo dose calculation using a cell processor based PlayStation 3 system

International Nuclear Information System (INIS)

Chow, James C L; Lam, Phil; Jaffray, David A

2012-01-01

This study investigates the performance of the EGSnrc computer code coupled with a Cell-based hardware in Monte Carlo simulation of radiation dose in radiotherapy. Performance evaluations of two processor-intensive functions namely, HOWNEAR and RANMAR G ET in the EGSnrc code were carried out basing on the 20-80 rule (Pareto principle). The execution speeds of the two functions were measured by the profiler gprof specifying the number of executions and total time spent on the functions. A testing architecture designed for Cell processor was implemented in the evaluation using a PlayStation3 (PS3) system. The evaluation results show that the algorithms examined are readily parallelizable on the Cell platform, provided that an architectural change of the EGSnrc was made. However, as the EGSnrc performance was limited by the PowerPC Processing Element in the PS3, PC coupled with graphics processing units or GPCPU may provide a more viable avenue for acceleration.

Monte Carlo dose calculation using a cell processor based PlayStation 3 system

Science.gov (United States)

Chow, James C. L.; Lam, Phil; Jaffray, David A.

2012-02-01

This study investigates the performance of the EGSnrc computer code coupled with a Cell-based hardware in Monte Carlo simulation of radiation dose in radiotherapy. Performance evaluations of two processor-intensive functions namely, HOWNEAR and RANMAR_GET in the EGSnrc code were carried out basing on the 20-80 rule (Pareto principle). The execution speeds of the two functions were measured by the profiler gprof specifying the number of executions and total time spent on the functions. A testing architecture designed for Cell processor was implemented in the evaluation using a PlayStation3 (PS3) system. The evaluation results show that the algorithms examined are readily parallelizable on the Cell platform, provided that an architectural change of the EGSnrc was made. However, as the EGSnrc performance was limited by the PowerPC Processing Element in the PS3, PC coupled with graphics processing units or GPCPU may provide a more viable avenue for acceleration.

Monte Carlo dose calculation using a cell processor based PlayStation 3 system

Energy Technology Data Exchange (ETDEWEB)

Chow, James C L; Lam, Phil; Jaffray, David A, E-mail: james.chow@rmp.uhn.on.ca [Department of Radiation Oncology, University of Toronto and Radiation Medicine Program, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2M9 (Canada)

2012-02-09

This study investigates the performance of the EGSnrc computer code coupled with a Cell-based hardware in Monte Carlo simulation of radiation dose in radiotherapy. Performance evaluations of two processor-intensive functions namely, HOWNEAR and RANMAR{sub G}ET in the EGSnrc code were carried out basing on the 20-80 rule (Pareto principle). The execution speeds of the two functions were measured by the profiler gprof specifying the number of executions and total time spent on the functions. A testing architecture designed for Cell processor was implemented in the evaluation using a PlayStation3 (PS3) system. The evaluation results show that the algorithms examined are readily parallelizable on the Cell platform, provided that an architectural change of the EGSnrc was made. However, as the EGSnrc performance was limited by the PowerPC Processing Element in the PS3, PC coupled with graphics processing units or GPCPU may provide a more viable avenue for acceleration.

Programmable level-1 trigger with 3D-Flow processor array

International Nuclear Information System (INIS)

Crosetto, D.

1994-01-01

The 3D-Flow parallel processing system is a new concept in processor architecture, system architecture, and assembly architecture. Compared to the electronics used in present systems, this approach reduces the cost and complexity of the hardware and allows easy assembly, disassembly, incremental upgrading, and maintenance of different interconnection topologies. The 3D-Flow parallel-processing system benefits high energy physics (HEP) by allowing: (1) common less costly hardware to be used in different experiments. (2) new uses of existing installations. (3) tuning of trigger based on the first analyzed data, and (4) selection of desired events directly from raw data. The goal of this parallel-processing architecture is to acquire multiple data in parallel (up to 100 million frames per second) and to process them at high speed, accomplishing digital filtering on the input data, pattern recognition (particle identification), data moving, and data formatting. The main features of the system are its programmability, scalability, high-speed communication, and low cost. The compactness of the 3D-Flow parallel-processing system in concert with the processor architecture allows processor interconnections to be mapped into the geometry of sensors (detectors in HEP) without large interconnection signal delay, enabling real-time pattern recognition. The overall 3D-Flow project has passed a major design review at Fermilab (Reviewers included experts in computers, triggering, system assembly, and electronics)

A Fast Density-Based Clustering Algorithm for Real-Time Internet of Things Stream

Science.gov (United States)

Ying Wah, Teh

2014-01-01

Data streams are continuously generated over time from Internet of Things (IoT) devices. The faster all of this data is analyzed, its hidden trends and patterns discovered, and new strategies created, the faster action can be taken, creating greater value for organizations. Density-based method is a prominent class in clustering data streams. It has the ability to detect arbitrary shape clusters, to handle outlier, and it does not need the number of clusters in advance. Therefore, density-based clustering algorithm is a proper choice for clustering IoT streams. Recently, several density-based algorithms have been proposed for clustering data streams. However, density-based clustering in limited time is still a challenging issue. In this paper, we propose a density-based clustering algorithm for IoT streams. The method has fast processing time to be applicable in real-time application of IoT devices. Experimental results show that the proposed approach obtains high quality results with low computation time on real and synthetic datasets. PMID:25110753

Demonstration of a real-time implementation of the ICVision holographic stereogram display

Science.gov (United States)

Kulick, Jeffrey H.; Jones, Michael W.; Nordin, Gregory P.; Lindquist, Robert G.; Kowel, Stephen T.; Thomsen, Axel

1995-07-01

There is increasing interest in real-time autostereoscopic 3D displays. Such systems allow 3D objects or scenes to be viewed by one or more observers with correct motion parallax without the need for glasses or other viewing aids. Potential applications of such systems include mechanical design, training and simulation, medical imaging, virtual reality, and architectural design. One approach to the development of real-time autostereoscopic display systems has been to develop real-time holographic display systems. The approach taken by most of the systems is to compute and display a number of holographic lines at one time, and then use a scanning system to replicate the images throughout the display region. The approach taken in the ICVision system being developed at the University of Alabama in Huntsville is very different. In the ICVision display, a set of discrete viewing regions called virtual viewing slits are created by the display. Each pixel is required fill every viewing slit with different image data. When the images presented in two virtual viewing slits separated by an interoccular distance are filled with stereoscopic pair images, the observer sees a 3D image. The images are computed so that a different stereo pair is presented each time the viewer moves 1 eye pupil diameter (approximately mm), thus providing a series of stereo views. Each pixel is subdivided into smaller regions, called partial pixels. Each partial pixel is filled with a diffraction grating that is just that required to fill an individual virtual viewing slit. The sum of all the partial pixels in a pixel then fill all the virtual viewing slits. The final version of the ICVision system will form diffraction gratings in a liquid crystal layer on the surface of VLSI chips in real time. Processors embedded in the VLSI chips will compute the display in real- time. In the current version of the system, a commercial AMLCD is sandwiched with a diffraction grating array. This paper will discuss

REAL TIME SYSTEM OPERATIONS 2006-2007

Energy Technology Data Exchange (ETDEWEB)

Eto, Joseph H.; Parashar, Manu; Lewis, Nancy Jo