Transport properties of hydrogen passivated silicon nanotubes and silicon nanotube field effect transistors

KAUST Repository

Montes Muñoz, Enrique

2017-01-24

We investigate the electronic transport properties of silicon nanotubes attached to metallic electrodes from first principles, using density functional theory and the non-equilibrium Green\\'s function method. The influence of the surface termination is studied as well as the dependence of the transport characteristics on the chirality, diameter, and length. Strong electronic coupling between nanotubes and electrodes is found to be a general feature that results in low contact resistance. The conductance in the tunneling regime is discussed in terms of the complex band structure. Silicon nanotube field effect transistors are simulated by applying a uniform potential gate. Our results demonstrate very high values of transconductance, outperforming the best commercial silicon field effect transistors, combined with low values of sub-threshold swing.

Electrothermal Behavior of High-Frequency Silicon-On-Glass Transistors

NARCIS (Netherlands)

Nenadovic, N.

2004-01-01

In this thesis, research is focused on the investigation of electrothermal effects in high-speed silicon transistors. At high current levels the power dissipation in these devices can lead to heating of both the device itself and the adjacent devices. In advanced transistors these effects are

High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures.

Science.gov (United States)

Liu, Yuan; Sheng, Jiming; Wu, Hao; He, Qiyuan; Cheng, Hung-Chieh; Shakir, Muhammad Imran; Huang, Yu; Duan, Xiangfeng

2016-06-01

Scalable fabrication of vertical-tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm(-2) . This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene-silicon heterostructures. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ballistic Spin Field Effect Transistor Based on Silicon Nanowires

Science.gov (United States)

Osintsev, Dmitri; Sverdlov, Viktor; Stanojevic, Zlatan; Selberherr, Siegfried

2011-03-01

We investigate the properties of ballistic spin field-effect transistors build on silicon nanowires. An accurate description of the conduction band based on the k . p} model is necessary in thin and narrow silicon nanostructures. The subband effective mass and subband splitting dependence on the nanowire dimensions is analyzed and used in the transport calculations. The spin transistor is formed by sandwiching the nanowire between two ferromagnetic metallic contacts. Delta-function barriers at the interfaces between the contacts and the silicon channel are introduced. The major contribution to the electric field-dependent spin-orbit interaction in confined silicon systems is due to the interface-induced inversion asymmetry which is of the Dresselhaus type. We study the current and conductance through the system for the contacts being in parallel and anti-parallel configurations. Differences between the [100] and [110] orientated structures are investigated in details. This work is supported by the European Research Council through the grant #247056 MOSILSPIN.

Effect of TMAH Etching Duration on the Formation of Silicon Nano wire Transistor Patterned by AFM Nano lithography

International Nuclear Information System (INIS)

Hutagalung, S.D.; Lew, K.C.

2012-01-01

Atomic force microscopy (AFM) lithography was applied to produce nano scale pattern for silicon nano wire transistor fabrication. This technique takes advantage of imaging facility of AFM and the ability of probe movement controlling over the sample surface to create nano patterns. A conductive AFM tip was used to grow the silicon oxide nano patterns on silicon on insulator (SOI) wafer. The applied tip-sample voltage and writing speed were well controlled in order to form pre-designed silicon oxide nano wire transistor structures. The effect of tetra methyl ammonium hydroxide (TMAH) etching duration on the oxide covered silicon nano wire transistor structure has been investigated. A completed silicon nano wire transistor was obtained by removing the oxide layer via hydrofluoric acid etching process. The fabricated silicon nano wire transistor consists of a silicon nano wire that acts as a channel with source and drain pads. A lateral gate pad with a nano wire head was fabricated very close to the channel in the formation of transistor structures. (author)

Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

International Nuclear Information System (INIS)

Foster, D.J.

1983-01-01

Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

Research of the voltage and current stabilization processes by using the silicon field-effect transistor

International Nuclear Information System (INIS)

Karimov, A.V.; Yodgorova, D.M.; Kamanov, B.M.; Giyasova, F.A.; Yakudov, A.A.

2012-01-01

The silicon field-effect transistors were investigated to use in circuits for stabilization of current and voltage. As in gallium arsenide field-effect transistors, in silicon field-effect transistors with p-n-junction a new mechanism of saturation of the drain current is experimentally found out due to both transverse and longitudinal compression of channel by additional resistance between the source and the gate of the transistor. The criteria for evaluating the coefficients of stabilization of transient current suppressors and voltage stabilizator based on the field-effect transistor are considered. (authors)

Contribution to the study of the behaviour of silicon planar transistors exposed to the {sup 60}Co {gamma} rays; Contribution a l'etude du comportement des transistors silicium a structure plane soumis aux rayons {gamma} du {sup 60}Co

Energy Technology Data Exchange (ETDEWEB)

Le Ber, J [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

1967-05-15

This report gives an account of studies carried out on bipolar silicon planar transistors irradiated by {sup 60}Co {gamma} rays. The author describes the interactions on the matter of the different types of particles and he gives a brief bibliographical recall of foreign studies. The technological structure of the planar transistors is then described in order to help the understanding of the phenomena, general comments are made about the choice of measured parameters and on the statistical interpretation of results. An automatic instrument for the measurement of the gain is described and the reproducibility of the results is stated The complexity of the problem and the difficulty to predict the behaviour of the semiconductors components are clearly shown. It is stated that the observed dispersions depend on: - the electrical bias during irradiation - the injection level in the emitter-base junction during the measurement - the manufacturer for a given type - the instantaneous dose rate - the geometry used The problem is then examined from the reliability point of view and methods are given to evaluate the reliability for a given dose - 'Worst case' method - moment method - Monte Carlo method. (author) [French] Ce rapport rend compte du travail effectue sur les transistors bipolaires au silicium irradies au rayons {gamma} du cobalt 60. On passe en revue les mecanismes d'interaction des differents rayonnements avec la matiere et on fait un bref rappel bibliographique des etudes effectuees a l'etranger. On decrit ensuite la structure technologique du transistor pour aider a la comprehension des phenomenes, puis on donne des generalites sur le choix des parametres mesures et l'interpretation statistique des resultats. On decrit l'ensemble du systeme de mesure de gain et on s'attache a montrer la reproductibilite des mesures. Les resultats experimentaux mentionnes etablissent clairement la complexite du probleme et la difficulte qu'il y a de faire des previsions. On

Development and characterization of vertical double-gate MOS field-effect transistors

International Nuclear Information System (INIS)

Trellenkamp, S.

2004-07-01

Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 μA/μm and transconductances up to 480 μS/μm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated. (orig.)

Insights into operation of planar tri-gate tunnel field effect transistor for dynamic memory application

Science.gov (United States)

Navlakha, Nupur; Kranti, Abhinav

2017-07-01

Insights into device physics and operation through the control of energy barriers are presented for a planar tri-gate Tunnel Field Effect Transistor (TFET) based dynamic memory. The architecture consists of a double gate (G1) at the source side and a single gate (G2) at the drain end of the silicon film. Dual gates (G1) effectively enhance the tunneling based read mechanism through the enhanced coupling and improved electrostatic control over the channel. The single gate (G2) controls the holes in the potential barrier induced through the proper selection of bias and workfunction. The results indicate that the planar tri-gate achieves optimum performance evaluated in terms of two composite metrics (M1 and M2), namely, product of (i) Sense Margin (SM) and Retention Time (RT) i.e., M1 = SM × RT and (ii) Sense Margin and Current Ratio (CR) i.e., M2 = SM × CR. The regulation of barriers created by the gates (G1 and G2) through the optimal use of device parameters leads to better performance metrics, with significant improvement at scaled lengths as compared to other tunneling based dynamic memory architectures. The investigation shows that lengths of G1, G2 and lateral spacing can be scaled down to 25 nm, 50 nm, and 30 nm, respectively, while achieving reasonable values for (M1, M2). The work demonstrates a systematic approach to showcase the advancement in TFET based Dynamic Random Access Memory (DRAM) through the use of planar tri-gate topology at a lower bias value. The concept, design, and operation of planar tri-gate architecture provide valuable viewpoints for TFET based DRAM.

A fabrication guide for planar silicon quantum dot heterostructures

Science.gov (United States)

Spruijtenburg, Paul C.; Amitonov, Sergey V.; van der Wiel, Wilfred G.; Zwanenburg, Floris A.

2018-04-01

We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.

Phosphorus diffusion with the help of the solid planar source in the manufacturing of the integrated circuits

Directory of Open Access Journals (Sweden)

B. A. Shangereeva

2008-02-01

Full Text Available The results of the development and realization of the basic process of the phosphorus diffusion for the formation of the active region of the power silicon transistor have been considered. It is shown that the obtained optimum technological conditions of the phosphorus diffusion using solid planar source allow to get the transistors with improved electrophysical parameters.

Integration of lateral porous silicon membranes into planar microfluidics.

Science.gov (United States)

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

2011-01-01

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

KAUST Repository

Fahad, Hossain M.

2011-10-12

We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

An innovative large scale integration of silicon nanowire-based field effect transistors

Science.gov (United States)

Legallais, M.; Nguyen, T. T. T.; Mouis, M.; Salem, B.; Robin, E.; Chenevier, P.; Ternon, C.

2018-05-01

Since the early 2000s, silicon nanowire field effect transistors are emerging as ultrasensitive biosensors while offering label-free, portable and rapid detection. Nevertheless, their large scale production remains an ongoing challenge due to time consuming, complex and costly technology. In order to bypass these issues, we report here on the first integration of silicon nanowire networks, called nanonet, into long channel field effect transistors using standard microelectronic process. A special attention is paid to the silicidation of the contacts which involved a large number of SiNWs. The electrical characteristics of these FETs constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.

Planar edgeless silicon detectors for the TOTEM experiment

CERN Document Server

Ruggiero, G; Noschis, E

2007-01-01

Recently the first prototype of microstrip edgeless silicon detector for the TOTEM experiment has been successfully produced and tested. This detector is fabricated with standard planar technology, reach sensitivity 50 μm from the cut edge and can operate with high bias at room temperature. These almost edgeless detectors employ a newly conceived terminating structure, which, although being reduced with respect to the conventional ones, still controls the electric field at the device periphery and prevents leakage current breakdown for high bias. Detectors with the new terminating structure are being produced now and will be installed at LHC in the Roman Pots, a special beam insertion, to allow the TOTEM experiment to detect leading protons at 10 σ from the beam. This paper will describe this new terminating structure for planar silicon detectors, how it applies to big size devices and the experimental tests proving their functionality.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

Science.gov (United States)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Transport spectroscopy of coupled donors in silicon nano-transistors

Science.gov (United States)

Moraru, Daniel; Samanta, Arup; Anh, Le The; Mizuno, Takeshi; Mizuta, Hiroshi; Tabe, Michiharu

2014-01-01

The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed: dopant-atom-based transistors. So far, most studies report transport through dopants randomly located in the channel. However, for practical applications, it is critical to control the location of the donors with simple techniques. Here, we fabricate silicon transistors with selectively nanoscale-doped channels using nano-lithography and thermal-diffusion doping processes. Coupled phosphorus donors form a quantum dot with the ground state split into a number of levels practically equal to the number of coupled donors, when the number of donors is small. Tunneling-transport spectroscopy reveals fine features which can be correlated with the different numbers of donors inside the quantum dot, as also suggested by first-principles simulation results. PMID:25164032

Tin - an unlikely ally for silicon field effect transistors?

KAUST Repository

Hussain, Aftab M.

2014-01-13

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high-κ/metal gate based multi-gate-field-effect-transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Mechanics of silicon nitride thin-film stressors on a transistor-like geometry

Directory of Open Access Journals (Sweden)

S. Reboh

2013-10-01

Full Text Available To understand the behavior of silicon nitride capping etch stopping layer stressors in nanoscale microelectronics devices, a simplified structure mimicking typical transistor geometries was studied. Elastic strains in the silicon substrate were mapped using dark-field electron holography. The results were interpreted with the aid of finite element method modeling. We show, in a counterintuitive sense, that the stresses developed by the film in the vertical sections around the transistor gate can reach much higher values than the full sheet reference. This is an important insight for advanced technology nodes where the vertical contribution of such liners is predominant over the horizontal part.

Low-power bacteriorhodopsin-silicon n-channel metal-oxide field-effect transistor photoreceiver.

Science.gov (United States)

Shin, Jonghyun; Bhattacharya, Pallab; Yuan, Hao-Chih; Ma, Zhenqiang; Váró, György

2007-03-01

A bacteriorhodopsin (bR)-silicon n-channel metal-oxide field-effect transistor (NMOSFET) monolithically integrated photoreceiver is demonstrated. The bR film is selectively formed on an external gate electrode of the transistor by electrophoretic deposition. A modified biasing circuit is incorporated, which helps to match the resistance of the bR film to the input impedance of the NMOSFET and to shift the operating point of the transistor to coincide with the maximum gain. The photoreceiver exhibits a responsivity of 4.7 mA/W.

Characteristics of thin-film transistors based on silicon nitride passivation by excimer laser direct patterning

International Nuclear Information System (INIS)

Chen, Chao-Nan; Huang, Jung-Jie

2013-01-01

This study explored the removal of silicon nitride using KrF laser ablation technology with a high threshold fluence of 990 mJ/cm 2 . This technology was used for contact hole patterning to fabricate SiN x -passivation-based amorphous-silicon thin films in a transistor device. Compared to the photolithography process, laser direct patterning using KrF laser ablation technology can reduce the number of process steps by at least three. Experimental results showed that the mobility and threshold voltages of thin film transistors patterned using the laser process were 0.16 cm 2 /V-sec and 0.2 V, respectively. The device performance and the test results of gate voltage stress reliability demonstrated that laser direct patterning is a promising alternative to photolithography in the panel manufacturing of thin-film transistors for liquid crystal displays. - Highlights: ► KrF laser ablation technology is used to remove silicon nitride. ► A simple method for direct patterning contact-hole in thin-film-transistor device. ► Laser technology reduced processing by at least three steps

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

Science.gov (United States)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Exploring graphene field effect transistor devices to improve spectral resolution of semiconductor radiation detectors

Energy Technology Data Exchange (ETDEWEB)

Harrison, Richard Karl [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Howell, Stephen Wayne [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Martin, Jeffrey B. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Hamilton, Allister B. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2013-12-01

Graphene, a planar, atomically thin form of carbon, has unique electrical and material properties that could enable new high performance semiconductor devices. Graphene could be of specific interest in the development of room-temperature, high-resolution semiconductor radiation spectrometers. Incorporating graphene into a field-effect transistor architecture could provide an extremely high sensitivity readout mechanism for sensing charge carriers in a semiconductor detector, thus enabling the fabrication of a sensitive radiation sensor. In addition, the field effect transistor architecture allows us to sense only a single charge carrier type, such as electrons. This is an advantage for room-temperature semiconductor radiation detectors, which often suffer from significant hole trapping. Here we report on initial efforts towards device fabrication and proof-of-concept testing. This work investigates the use of graphene transferred onto silicon and silicon carbide, and the response of these fabricated graphene field effect transistor devices to stimuli such as light and alpha radiation.

Neutron Radiation Effect On 2N2222 And NTE 123 NPN Silicon Bipolar Junction Transistors

International Nuclear Information System (INIS)

Oo, Myo Min; Rashid, N K A Md; Hasbullah, N F; Karim, J Abdul; Zin, M R Mohamed

2013-01-01

This paper examines neutron radiation with PTS (Pneumatic Transfer System) effect on silicon NPN bipolar junction transistors (2N2222 and NTE 123) and analysis of the transistors in terms of electrical characterization such as current gain after neutron radiation. The key parameters are measured with Keithley 4200SCS. Experiment results show that the current gain degradation of the transistors is very sensitive to neutron radiation. The neutron radiation can cause displacement damage in the bulk layer of the transistor structure. The current degradation is believed to be governed by increasing recombination current between the base and emitter depletion region

Analytical Model of Subthreshold Drain Current Characteristics of Ballistic Silicon Nanowire Transistors

Directory of Open Access Journals (Sweden)

Wanjie Xu

2015-01-01

Full Text Available A physically based subthreshold current model for silicon nanowire transistors working in the ballistic regime is developed. Based on the electric potential distribution obtained from a 2D Poisson equation and by performing some perturbation approximations for subband energy levels, an analytical model for the subthreshold drain current is obtained. The model is further used for predicting the subthreshold slopes and threshold voltages of the transistors. Our results agree well with TCAD simulation with different geometries and under different biasing conditions.

Transistor data book

International Nuclear Information System (INIS)

1988-03-01

It introduces how to use this book. It lists transistor data and index, which are Type No, Cross index, Germanium PNP low power transistors, silicon NPN low power transistors, Germanium PNP high power transistors, Switching transistors, transistor arrays, Miscellaneous transistors, types with U.S military specifications, direct replacement transistors, suggested replacement transistors, schematic drawings, outline drawings, device number keys and manufacturer's logos.

Monolithic integration of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Batignani, Giovanni; Boscardin, Maurizio; Bosisio, Luciano; Gregori, Paolo; Pancheri, Lucio; Piemonte, Claudio; Ratti, Lodovico; Verzellesi, Giovanni; Zorzi, Nicola

2007-01-01

We report on the most recent results from an R and D activity aimed at the development of silicon radiation detectors with embedded front-end electronics. The key features of the fabrication technology and the available active devices are described. Selected results from the characterization of transistors and test structures are presented and discussed, and the considered application fields are addressed

Experimental realization of a silicon spin field-effect transistor

OpenAIRE

Huang, Biqin; Monsma, Douwe J.; Appelbaum, Ian

2007-01-01

A longitudinal electric field is used to control the transit time (through an undoped silicon vertical channel) of spin-polarized electrons precessing in a perpendicular magnetic field. Since an applied voltage determines the final spin direction at the spin detector and hence the output collector current, this comprises a spin field-effect transistor. An improved hot-electron spin injector providing ~115% magnetocurrent, corresponding to at least ~38% electron current spin polarization after...

Suppression of photo-leakage current in amorphous silicon thin-film transistors by n-doped nanocrystalline silicon

International Nuclear Information System (INIS)

Lin, Hung-Chien; Ho, King-Yuan; Hsu, Chih-Chieh; Yan, Jing-Yi; Ho, Jia-Chong

2011-01-01

The reduction of photo-leakage current of amorphous silicon thin-film transistors (a-Si TFTs) is investigated and is found to be successfully suppressed by the use of an n-doped nanocrystalline silicon layer (n+ nc-Si) as an ohmic contact layer. The shallow-level defects of n+ nc-Si can become trapping centres of photo-induced electrons as the a-Si TFT is operated under light illumination. A lower oxygen concentration during n+ nc-Si deposition can increase the creation of shallow-level defects and improve the contrast ratio of active matrix organic light-emitting diode panels.

Adaptive silicone-membrane lenses: planar vs. shaped membrane

CSIR Research Space (South Africa)

Schneider, F

2009-08-01

Full Text Available Engineering, Georges-Koehler-Allee 102, Freiburg 79110, Germany florian.schneider@imtek.uni-freiburg.de ABSTRACT We compare the performance and optical quality of two types of adaptive fluidic silicone-membrane lenses. The membranes feature either a...-membrane lenses: planar vs. shaped membrane Florian Schneider1,2, Philipp Waibel2 and Ulrike Wallrabe2 1 CSIR, Materials Science and Manufacturing, PO Box 395, Pretoria 0001, South Africa 2 University of Freiburg – IMTEK, Department of Microsystems...

Integrating carbon nanotubes into silicon by means of vertical carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi; Wang, Qingxiao; Yue, Weisheng; Guo, Zaibing; LI, LIANG; Zhao, Chao; Wang, Xianbin; Abutaha, Anas I.; Alshareef, Husam N.; Zhang, Yafei; Zhang, Xixiang

2014-01-01

Single-walled carbon nanotubes have been integrated into silicon for use in vertical carbon nanotube field-effect transistors (CNTFETs). A unique feature of these devices is that a silicon substrate and a metal contact are used as the source and drain for the vertical transistors, respectively. These CNTFETs show very different characteristics from those fabricated with two metal contacts. Surprisingly, the transfer characteristics of the vertical CNTFETs can be either ambipolar or unipolar (p-type or n-type) depending on the sign of the drain voltage. Furthermore, the p-type/n-type character of the devices is defined by the doping type of the silicon substrate used in the fabrication process. A semiclassical model is used to simulate the performance of these CNTFETs by taking the conductance change of the Si contact under the gate voltage into consideration. The calculation results are consistent with the experimental observations. This journal is © the Partner Organisations 2014.

Cryogenic preamplification of a single-electron-transistor using a silicon-germanium heterojunction-bipolar-transistor

Energy Technology Data Exchange (ETDEWEB)

Curry, M. J. [Department of Physics and Astronomy, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); England, T. D.; Bishop, N. C.; Ten-Eyck, G.; Wendt, J. R.; Pluym, T.; Lilly, M. P.; Carroll, M. S. [Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States); Carr, S. M. [Center for Quantum Information and Control, University of New Mexico, Albuquerque, New Mexico 87131 (United States); Sandia National Laboratories, 1515 Eubank Blvd SE, Albuquerque, New Mexico 87123 (United States)

2015-05-18

We examine a silicon-germanium heterojunction bipolar transistor (HBT) for cryogenic pre-amplification of a single electron transistor (SET). The SET current modulates the base current of the HBT directly. The HBT-SET circuit is immersed in liquid helium, and its frequency response from low frequency to several MHz is measured. The current gain and the noise spectrum with the HBT result in a signal-to-noise-ratio (SNR) that is a factor of 10–100 larger than without the HBT at lower frequencies. The transition frequency defined by SNR = 1 has been extended by as much as a factor of 10 compared to without the HBT amplification. The power dissipated by the HBT cryogenic pre-amplifier is approximately 5 nW to 5 μW for the investigated range of operation. The circuit is also operated in a single electron charge read-out configuration in the time-domain as a proof-of-principle demonstration of the amplification approach for single spin read-out.

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

Functionalization and microfluidic integration of silicon nanowire biologically gated field effect transistors

DEFF Research Database (Denmark)

Pfreundt, Andrea; Svendsen, Winnie Edith; Dimaki, Maria

2016-01-01

This thesis deals with the development of a novel biosensor for the detection of biomolecules based on a silicon nanowire biologically gated field-effect transistor and its integration into a point-of-care device. The sensor and electrical on-chip integration was developed in a different project...

α-spectra hyperfine structure resolution by silicon planar detectors

International Nuclear Information System (INIS)

Eremin, V.K.; Verbitskaya, E.M.; Strokan, N.B.; Sukhanov, V.L.; Malyarenko, A.M.

1986-01-01

The lines with 13 keV step from the main one is α-spectra of nuclei with an odd number of nucleons take place. Silicon planar detectors n-Si with the operation surface of 10 mm 2 are developed for resolution of this hyperfine structure. The mechanism of losses in detectors for short-range-path particles is analyzed. The results of measurements from detectors with 10 keV resolution are presented

Study of silicon-silicon nitride interface properties on planar (1 0 0), planar (1 1 1) and textured surfaces using deep-level transient spectroscopy

International Nuclear Information System (INIS)

Gong, Chun; Simoen, Eddy; Posthuma, Niels E; Van Kerschaver, Emmanuel; Poortmans, Jef; Mertens, Robert

2010-01-01

Deep-level transient spectroscopy (DLTS) has been applied to metal-insulator-semiconductor (MIS) capacitors fabricated on planar (1 0 0), planar (1 1 1) orientations and textured n-type silicon wafers. Low frequency direct plasma-enhanced chemical vapour deposition Si-SiN x interface properties with and without plasma NH 3 pre-treatment, with and without rapid thermal annealing (RTA) have been investigated. It is shown that three different kinds of defect states are identified at the Si-SiN x interface. For the planar (1 0 0) surface, samples with plasma NH 3 pre-treatment plus RTA show the lowest DLTS signals, which suggests the lowest overall interface states density. For planar (1 1 1) Si surfaces, plasma NH 3 pre-treatment and RTA yield a small improvement. With the textured surface, the RTA step improves the surface passivation quality further but no obvious impact is found with plasma NH 3 pre-treatment. Energy-dependent electron capture cross sections were also measured by small-pulse DLTS. The capture cross sections depend strongly on the energy level and decrease towards the conduction band edge.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

Science.gov (United States)

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

Sub-parts per million NO2 chemi-transistor sensors based on composite porous silicon/gold nanostructures prepared by metal-assisted etching.

Science.gov (United States)

Sainato, Michela; Strambini, Lucanos Marsilio; Rella, Simona; Mazzotta, Elisabetta; Barillaro, Giuseppe

2015-04-08

Surface doping of nano/mesostructured materials with metal nanoparticles to promote and optimize chemi-transistor sensing performance represents the most advanced research trend in the field of solid-state chemical sensing. In spite of the promising results emerging from metal-doping of a number of nanostructured semiconductors, its applicability to silicon-based chemi-transistor sensors has been hindered so far by the difficulties in integrating the composite metal-silicon nanostructures using the complementary metal-oxide-semiconductor (CMOS) technology. Here we propose a facile and effective top-down method for the high-yield fabrication of chemi-transistor sensors making use of composite porous silicon/gold nanostructures (cSiAuNs) acting as sensing gate. In particular, we investigate the integration of cSiAuNs synthesized by metal-assisted etching (MAE), using gold nanoparticles (NPs) as catalyst, in solid-state junction-field-effect transistors (JFETs), aimed at the detection of NO2 down to 100 parts per billion (ppb). The chemi-transistor sensors, namely cSiAuJFETs, are CMOS compatible, operate at room temperature, and are reliable, sensitive, and fully recoverable for the detection of NO2 at concentrations between 100 and 500 ppb, up to 48 h of continuous operation.

Capabilities of silicon Shottki barriers and planar detectors in low-energy proton spectometry

Energy Technology Data Exchange (ETDEWEB)

Verbitskaya, E M; Eremin, V K; Malyarenko, A M; Sakharov, V I; Serenkov, I T; Strokan, N B; Sukhanov, V L

1987-05-12

Dependence of the resolution of surface barrier and planar diffusion silicon detectors on proton energy is investigated. The experiment was conducted at the device, representing the double mass spectrometer with the maximal energy of single-charged ions up to 200 keV. Two advantages of using planar diffusion detectors for light low-energy ion spectrometry is established: high energy resolution and independence of signal amplitude of bias voltage. Background noise represents the main factor dictaiting resolution, but fluctuations of losses in input window are sufficient as well. It was concluded that planar detector application for spectrometry of protons with energy of less than 200 keV would improve the resolution up to 2.2 keV without detector cooling.

cap alpha. -spectra hyperfine structure resolution by silicon planar detectors

Energy Technology Data Exchange (ETDEWEB)

Eremin, V K; Verbitskaya, E M; Strokan, N B; Sukhanov, V L; Malyarenko, A M

1986-10-01

The lines with 13 keV step from the main one is ..cap alpha..-spectra of nuclei with an odd number of nucleons take place. Silicon planar detectors n-Si with the operation surface of 10 mm/sup 2/ are developed for resolution of this hyperfine structure. The mechanism of losses in detectors for short-range-path particles is analyzed. The results of measurements from detectors with 10 keV resolution are presented.

A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

Energy Technology Data Exchange (ETDEWEB)

Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

2017-06-15

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

NARCIS (Netherlands)

Moh, T.S.Y.

2013-01-01

In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

On the timing performance of thin planar silicon sensors

Science.gov (United States)

Akchurin, N.; Ciriolo, V.; Currás, E.; Damgov, J.; Fernández, M.; Gallrapp, C.; Gray, L.; Junkes, A.; Mannelli, M.; Martin Kwok, K. H.; Meridiani, P.; Moll, M.; Nourbakhsh, S.; Pigazzini, S.; Scharf, C.; Silva, P.; Steinbrueck, G.; de Fatis, T. Tabarelli; Vila, I.

2017-07-01

We report on the signal timing capabilities of thin silicon sensors when traversed by multiple simultaneous minimum ionizing particles (MIP). Three different planar sensors, with depletion thicknesses 133, 211, and 285 μm, have been exposed to high energy muons and electrons at CERN. We describe signal shape and timing resolution measurements as well as the response of these devices as a function of the multiplicity of MIPs. We compare these measurements to simulations where possible. We achieve better than 20 ps timing resolution for signals larger than a few tens of MIPs.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-01-01

Since 1989 the Solenoidal Detector Collaboration (SDC) has been developing a general purpose detector to be operated at the Superconducting Super Collider (SSC). A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDS silicon tracker. The IC was designed and tested at LBL and was fabricated using AT and T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a φ = 10 14 protons/cm 2 have been performed on the JC, demonstrating the radiation hardness of the complementary bipolar process

Resonant tunnelling features in a suspended silicon nanowire single-hole transistor

Energy Technology Data Exchange (ETDEWEB)

Llobet, Jordi; Pérez-Murano, Francesc, E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Institut de Microelectrònica de Barcelona (IMB-CNM CSIC), Campus UAB, E-08193 Bellaterra, Catalonia (Spain); Krali, Emiljana; Wang, Chen; Jones, Mervyn E.; Durrani, Zahid A. K., E-mail: francesc.perez@csic.es, E-mail: z.durrani@imperial.ac.uk [Department of Electrical and Electronic Engineering, Imperial College London, South Kensington, London SW7 2AZ (United Kingdom); Arbiol, Jordi [Institució Catalana de Recerca i Estudis Avançats (ICREA) and Institut Català de Nanociència i Nanotecnologia (ICN2), Campus UAB, 08193 Bellaterra, Catalonia (Spain); CELLS-ALBA Synchrotron Light Facility, 08290 Cerdanyola, Catalonia (Spain)

2015-11-30

Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.

Resonant tunnelling features in a suspended silicon nanowire single-hole transistor

International Nuclear Information System (INIS)

Llobet, Jordi; Pérez-Murano, Francesc; Krali, Emiljana; Wang, Chen; Jones, Mervyn E.; Durrani, Zahid A. K.; Arbiol, Jordi

2015-01-01

Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystal quantum dots has been used to form a single-hole transistor. Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal. Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations

Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

International Nuclear Information System (INIS)

Olsen, Sarah H.

2002-01-01

Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

Planar Silicon Optical Waveguide Light Modulators

DEFF Research Database (Denmark)

Leistiko, Otto; Bak, H.

1994-01-01

that values in the nanosecond region should be possible, however, the measured values are high, 20 microseconds, due to the large area of the injector junctions, 1× 10¿2 cm2, and the limitations imposed by the detection circuit. The modulating properties of these devices are impressive, measurements......The results of an experimental investigation of a new type of optical waveguide based on planar technology in which the liglht guiding and modulation are achieved by exploiting free carrier effects in silicon are presented. Light is guided between the n+ substrate and two p+ regions, which also...... serve as carrier injectors for controling absorption. Light confinement of single mode devices is good, giving spot sizes of 9 ¿m FWHM. Insertion loss measurements indicate that the absorption losses for these waveguides are extremely low, less 1 dB/cm. Estimates of the switching speed indicate...

3D NANOTUBE FIELD EFFECT TRANSISTORS FOR HYBRID HIGH-PERFORMANCE AND LOW-POWER OPERATION WITH HIGH CHIP-AREA EFFICIENCY

KAUST Repository

Fahad, Hossain M.

2014-03-01

Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep

Touch sensors based on planar liquid crystal-gated-organic field-effect transistors

International Nuclear Information System (INIS)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi; Lee, Sooyong; Nam, Sungho; Kim, Youngkyoo; Kim, Hwajeong; Lee, Joon-Hyung; Park, Soo-Young; Kang, Inn-Kyu

2014-01-01

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4 ′ -pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5 cm 2 /Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V D ) and gate (V G ) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V D and V G . The best voltage combination was V D = −0.2 V and V G = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

Science.gov (United States)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

The design of a new spiking neuron using dual work function silicon nanowire transistors

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2007-01-01

A new spike neuron cell is designed using vertically grown, undoped silicon nanowire transistors. This study presents an entire design cycle from designing and optimizing vertical nanowire transistors for minimal power dissipation to realizing a neuron cell and measuring its dynamic power consumption, performance and layout area. The design cycle starts with determining individual metal gate work functions for NMOS and PMOS transistors as a function of wire radius to produce a 300 mV threshold voltage. The wire radius and effective channel length are subsequently varied to find a common body geometry for both transistors that yields smaller than 1 pA OFF current while producing maximum drive currents. A spike neuron cell is subsequently built using these transistors to measure its transient performance, power dissipation and layout area. Post-layout simulation results indicate that the neuron consumes 0.397 μW to generate a +1 V and 1.12 μW to generate a -1 V output pulse for a fan-out of five synapses at 500 MHz; the power dissipation increases by approximately 3 nW for each additional synapse at the output for generating either pulse. The neuron circuit occupies approximately 0.27 μm 2

Fabrication of double-dot single-electron transistor in silicon nanowire

International Nuclear Information System (INIS)

Jo, Mingyu; Kaizawa, Takuya; Arita, Masashi; Fujiwara, Akira; Ono, Yukinori; Inokawa, Hiroshi; Choi, Jung-Bum; Takahashi, Yasuo

2010-01-01

We propose a simple method for fabricating Si single-electron transistors (SET) with coupled dots by means of a pattern-dependent-oxidation (PADOX) method. The PADOX method is known to convert a small one-dimensional Si wire formed on a silicon-on-insulator (SOI) substrate into a SET automatically. We fabricated a double-dot Si SET when we oxidized specially designed Si nanowires formed on SOI substrates. We analyzed the measured electrical characteristics by fitting the measurement and simulation results and confirmed the double-dot formation and the position of the two dots in the Si wire.

Physical limits of silicon transistors and circuits

International Nuclear Information System (INIS)

Keyes, Robert W

2005-01-01

A discussion on transistors and electronic computing including some history introduces semiconductor devices and the motivation for miniaturization of transistors. The changing physics of field-effect transistors and ways to mitigate the deterioration in performance caused by the changes follows. The limits of transistors are tied to the requirements of the chips that carry them and the difficulties of fabricating very small structures. Some concluding remarks about transistors and limits are presented

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi

2014-07-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

Science.gov (United States)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Unique Characteristics of Vertical Carbon Nanotube Field-effect Transistors on Silicon

KAUST Repository

Li, Jingqi; Yue, Weisheng; Guo, Zaibing; Yang, Yang; Wang, Xianbin; Syed, Ahad A.; Zhang, Yafei

2014-01-01

A vertical carbon nanotube field-effect transistor (CNTFET) based on silicon (Si) substrate has been proposed and simulated using a semi-classical theory. A single-walled carbon nanotube (SWNT) and an n-type Si nanowire in series construct the channel of the transistor. The CNTFET presents ambipolar characteristics at positive drain voltage (Vd) and n-type characteristics at negative Vd. The current is significantly influenced by the doping level of n-Si and the SWNT band gap. The n-branch current of the ambipolar characteristics increases with increasing doping level of the n-Si while the p-branch current decreases. The SWNT band gap has the same influence on the p-branch current at a positive Vd and n-type characteristics at negative Vd. The lower the SWNT band gap, the higher the current. However, it has no impact on the n-branch current in the ambipolar characteristics. Thick oxide is found to significantly degrade the current and the subthreshold slope of the CNTFETs.

Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry

Energy Technology Data Exchange (ETDEWEB)

Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu; Gouker, Pascale M.

2013-09-01

Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd{sub 2}O{sub 3} than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron–hole recombination or conversion electron loss in interconnect wiring above the transistors. -- Highlights: • A novel Gd{sub 2}O{sub 3} coated FDSOI MOSFET thermal neutron dosimeter is presented. • Dosimeter can detect charges generated from {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. • Measured neutron sensitivity is comparable to that calculated theoretically. • Dosimeter requires zero power during operation, enabling new application areas.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

Science.gov (United States)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Indium-gallium-zinc-oxide thin-film transistor with a planar split dual-gate structure

Science.gov (United States)

Liu, Yu-Rong; Liu, Jie; Song, Jia-Qi; Lai, Pui-To; Yao, Ruo-He

2017-12-01

An amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) with a planar split dual gate (PSDG) structure has been proposed, fabricated and characterized. Experimental results indicate that the two independent gates can provide dynamical control of device characteristics such as threshold voltage, sub-threshold swing, off-state current and saturation current. The transconductance extracted from the output characteristics of the device increases from 4.0 × 10-6S to 1.6 × 10-5S for a change of control gate voltage from -2 V to 2 V, and thus the device could be used in a variable-gain amplifier. A significant advantage of the PSDG structure is its flexibility in controlling the device performance according to the need of practical applications.

Improvement in switching characteristics and long-term stability of Zn-O-N thin-film transistors by silicon doping

Directory of Open Access Journals (Sweden)

Hiroshi Tsuji

2017-06-01

Full Text Available The effects of silicon doping on the properties of Zn-O-N (ZnON films and on the device characteristics of ZnON thin-film transistors (TFTs were investigated by co-sputtering silicon and zinc targets. Silicon doping was effective at decreasing the carrier concentration in ZnON films; therefore, the conductivity of the films can be controlled by the addition of a small amount of silicon. Doped silicon atoms also form bonds with nitrogen atoms, which suppresses nitrogen desorption from the films. Furthermore, Si-doped ZnON-TFTs are demonstrated to exhibit less negative threshold voltages, smaller subthreshold swings, and better long-term stability than non-doped ZnON-TFTs.

Modeling and Simulation of - and Silicon Germanium-Base Bipolar Transistors Operating at a Wide Range of Temperatures.

Science.gov (United States)

Shaheed, M. Reaz

1995-01-01

Higher speed at lower cost and at low power consumption is a driving force for today's semiconductor technology. Despite a substantial effort toward achieving this goal via alternative technologies such as III-V compounds, silicon technology still dominates mainstream electronics. Progress in silicon technology will continue for some time with continual scaling of device geometry. However, there are foreseeable limits on achievable device performance, reliability and scaling for room temperature technologies. Thus, reduced temperature operation is commonly viewed as a means for continuing the progress towards higher performance. Although silicon CMOS will be the first candidate for low temperature applications, bipolar devices will be used in a hybrid fashion, as line drivers or in limited critical path elements. Silicon -germanium-base bipolar transistors look especially attractive for low-temperature bipolar applications. At low temperatures, various new physical phenomena become important in determining device behavior. Carrier freeze-out effects which are negligible at room temperature, become of crucial importance for analyzing the low temperature device characteristics. The conventional Pearson-Bardeen model of activation energy, used for calculation of carrier freeze-out, is based on an incomplete picture of the physics that takes place and hence, leads to inaccurate results at low temperatures. Plasma -induced bandgap narrowing becomes more pronounced in device characteristics at low temperatures. Even with modern numerical simulators, this effect is not well modeled or simulated. In this dissertation, improved models for such physical phenomena are presented. For accurate simulation of carrier freeze-out, the Pearson-Bardeen model has been extended to include the temperature dependence of the activation energy. The extraction of the model is based on the rigorous, first-principle theoretical calculations available in the literature. The new model is shown

A study on the beta voltaic micro-nuclear battery based on the planar technology silicon detector

International Nuclear Information System (INIS)

Zhang Kai; He Gaokui; Huang Xiaojian; Liu Yang; Meng Xin; Hao Xiaoyong

2011-01-01

It describes briefly the beta voltaic micro-nuclear battery based on the planar technology silicon detector and radioisotope. Different sensitive area of silicon detectors are used to cooperate with 63 Ni source to buildup of beta voltaic micro-nuclear batteries. The experimental data show that the larger sensitive area the silicon detector has, the higher open circuit voltage it produces, and the open circuit voltage of single cell has reached an excellent result from 0.15 V to 0.30 V. It is possible to get high output power by series or parallel connecting the beta voltaic micro-nuclear batteries. (authors)

Fabrication of a novel silicon single electron transistor for Si:P quantum computer devices

International Nuclear Information System (INIS)

Angus, S.J.; Smith, C.E.A.; Gauja, E.; Dzurak, A.S.; Clark, R.G.; Snider, G.L.

2004-01-01

Full text: Quantum computation relies on the successful measurement of quantum states. Single electron transistors (SETs) are known to be able to perform fast and sensitive charge measurements of solid state qubits. However, due to their sensitivity, SETs are also very susceptible to random charge fluctuations in a solid-state materials environment. In previous dc transport measurements, silicon-based SETs have demonstrated greater charge stability than A1/A1 2 O 3 SETs. We have designed and fabricated a novel silicon SET architecture for a comparison of the noise characteristics of silicon and aluminium based devices. The silicon SET described here is designed for controllable and reproducible low temperature operation. It is fabricated using a novel dual gate structure on a silicon-on-insulator substrate. A silicon quantum wire is formed in a 100nm thick high-resistivity superficial silicon layer using reactive ion etching. Carriers are induced in the silicon wire by a back gate in the silicon substrate. The tunnel barriers are created electrostatically, using lithographically defined metallic electrodes (∼40nm width). These tunnel barriers surround the surface of the quantum wire, thus producing excellent electrostatic confinement. This architecture provides independent control of tunnel barrier height and island occupancy, thus promising better control of Coulomb blockade oscillations than in previously investigated silicon SETs. The use of a near intrinsic silicon substrate offers compatibility with Si:P qubits in the longer term

Heavy-ion irradiation effects on passivated implanted planar silicon detectors

International Nuclear Information System (INIS)

Coster, W. de; Brijs, B.; Vandervorst, W.; Burger, P.

1992-01-01

Commercially available p + nn + passivated implanted planar silicon detectors have been shown to be very performing for standard RBS-analysis with 4 He beams. Lifetimes are found to range up till >10 9 particles. The end of lifetime occurs concurrent with internal breakdown of the detector. Inverted n + np + detectors where the junction is located well outside the damage region, are expected to be less sensitive to the radiation damage and to have a higher lifetime. In the present paper the characteristics for heavy-ion detection of both types of detector are investigated and discussed upon. (orig.)

Transistor challenges - A DRAM perspective

International Nuclear Information System (INIS)

Faul, Juergen W.; Henke, Dietmar

2005-01-01

Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for 'on pitch' circuits at the array edge will come up due to the aggressive cell size scaling

Design and simulation of a novel GaN based resonant tunneling high electron mobility transistor on a silicon substrate

International Nuclear Information System (INIS)

Chowdhury, Subhra; Biswas, Dhrubes; Chattaraj, Swarnabha

2015-01-01

For the first time, we have introduced a novel GaN based resonant tunneling high electron mobility transistor (RTHEMT) on a silicon substrate. A monolithically integrated GaN based inverted high electron mobility transistor (HEMT) and a resonant tunneling diode (RTD) are designed and simulated using the ATLAS simulator and MATLAB in this study. The 10% Al composition in the barrier layer of the GaN based RTD structure provides a peak-to-valley current ratio of 2.66 which controls the GaN based HEMT performance. Thus the results indicate an improvement in the current–voltage characteristics of the RTHEMT by controlling the gate voltage in this structure. The introduction of silicon as a substrate is a unique step taken by us for this type of RTHEMT structure. (paper)

Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Energy Technology Data Exchange (ETDEWEB)

Clément, N., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr; Han, X. L. [Institute of Electronics, Microelectronics and Nanotechnology, CNRS, Avenue Poincaré, 59652 Villeneuve d' Ascq (France); Larrieu, G., E-mail: nicolas.clement@iemn.univ-lille1.fr, E-mail: guilhem.larrieu@laas.fr [Laboratory for Analysis and Architecture of Systems (LAAS), CNRS, Universite de Toulouse, 7 Avenue Colonel Roche, 31077 Toulouse (France)

2013-12-23

Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact.

On the 50th Anniversary of the Transistor

DEFF Research Database (Denmark)

Stassen, Flemming

1997-01-01

This paper celebrates the 50th anniversary of the invention of the bipolar transistor in 1947. Combined with the inventions of integration and planar technology, the invention of the transistor marks the beginning of a period of unprecedented growth, the industrialization of electronics....

Transfer-free fabrication of graphene transistors

OpenAIRE

Wessely, P.J.; Wessely, F.; Birinci, E.; Schwalke, U.; Riedinger, B.

2012-01-01

The authors invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon, a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane-based growth process, monolayer graphene field-effect transistors and...

Group IV nanotube transistors for next generation ubiquitous computing

KAUST Repository

Fahad, Hossain M.; Hussain, Aftab M.; Sevilla, Galo T.; Banerjee, Sanjay K.; Hussain, Muhammad Mustafa

2014-01-01

Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However

Non-classical polycrystalline silicon thin-film transistor with embedded block-oxide for suppressing the short channel effect

International Nuclear Information System (INIS)

Lin, Jyi-Tsong; Huang, Kuo-Dong; Hu, Shu-Fen

2008-01-01

In this paper, a polycrystalline silicon (polysilicon) thin-film transistor with a block oxide enclosing body, BTFT, is fabricated and investigated. By utilizing the block-oxide structure of thin-film transistors, the BTFT is shown to suppress the short channel effect. This proposed structure is formed by burying self-aligned oxide spacers along the sidewalls of the source and drain junctions, which reduces the P–N junction area, thereby reducing the junction capacitance and leakage current. Measurements demonstrate that the BTFT eliminates the punch-through effect even down to gate lengths of 1.5 µm, whereas the conventional TFT suffers serious short channel effects at this gate length

High temperature study of flexible silicon-on-insulator fin field-effect transistors

KAUST Repository

Diab, Amer El Hajj

2014-09-29

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

Silicon dioxide with a silicon interfacial layer as an insulating gate for highly stable indium phosphide metal-insulator-semiconductor field effect transistors

Science.gov (United States)

Kapoor, V. J.; Shokrani, M.

1991-01-01

A novel gate insulator consisting of silicon dioxide (SiO2) with a thin silicon (Si) interfacial layer has been investigated for high-power microwave indium phosphide (InP) metal-insulator-semiconductor field effect transistors (MISFETs). The role of the silicon interfacial layer on the chemical nature of the SiO2/Si/InP interface was studied by high-resolution X-ray photoelectron spectroscopy. The results indicated that the silicon interfacial layer reacted with the native oxide at the InP surface, thus producing silicon dioxide, while reducing the native oxide which has been shown to be responsible for the instabilities in InP MISFETs. While a 1.2-V hysteresis was present in the capacitance-voltage (C-V) curve of the MIS capacitors with silicon dioxide, less than 0.1 V hysteresis was observed in the C-V curve of the capacitors with the silicon interfacial layer incorporated in the insulator. InP MISFETs fabricated with the silicon dioxide in combination with the silicon interfacial layer exhibited excellent stability with drain current drift of less than 3 percent in 10,000 sec, as compared to 15-18 percent drift in 10,000 sec for devices without the silicon interfacial layer. High-power microwave InP MISFETs with Si/SiO2 gate insulators resulted in an output power density of 1.75 W/mm gate width at 9.7 GHz, with an associated power gain of 2.5 dB and 24 percent power added efficiency.

Evolution of the MOS transistor - From conception to VLSI

International Nuclear Information System (INIS)

Sah, C.T.

1988-01-01

Historical developments of the metal-oxide-semiconductor field-effect-transistor (MOSFET) during the last sixty years are reviewed, from the 1928 patent disclosures of the field-effect conductivity modulation concept and the semiconductor triodes structures proposed by Lilienfeld to the 1947 Shockley-originated efforts which led to the laboratory demonstration of the modern silicon MOSFET thirty years later in 1960. A survey is then made of the milestones of the past thirty years leading to the latest submicron silicon logic CMOS (Complementary MOS) and BICMOS (Bipolar-Junction-Transistor CMOS combined) arrays and the three-dimensional and ferroelectric extensions of Dennard's one-transistor dynamic random access memory (DRAM) cell. Status of the submicron lithographic technologies (deep ultra-violet light, X-ray, electron-beam) are summarized. Future trends of memory cell density and logic gate speed are projected. Comparisons of the switching speed of the silicon MOSFET with that of silicon bipolar and GaAs field-effect transistors are reviewed. Use of high-temperature superconducting wires and GaAs-on-Si monolithic semiconductor optical clocks to break the interconnect-wiring delay barrier is discussed. Further needs in basic research and mathematical modeling on the failure mechanisms in submicron silicon transistors at high electric fields (hot electron effects) and in interconnection conductors at high current densities and low as well as high electric fields (electromigration) are indicated

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

Energy Technology Data Exchange (ETDEWEB)

Bomben, M., E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Bagolini, A.; Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, L. [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, Pisa (Italy); INFN Sez. di Pisa, Pisa (Italy); Chauveau, J. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

2013-12-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

International Nuclear Information System (INIS)

Bomben, M.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

2013-01-01

In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown

A strained silicon cold electron bolometer using Schottky contacts

Energy Technology Data Exchange (ETDEWEB)

Brien, T. L. R., E-mail: tom.brien@astro.cf.ac.uk; Ade, P. A. R.; Barry, P. S.; Dunscombe, C.; Morozov, D. V.; Sudiwala, R. V. [School of Physics and Astronomy, Cardiff University, Queen' s Buildings, The Parade, Cardiff CF24 3AA (United Kingdom); Leadley, D. R.; Myronov, M.; Parker, E. H. C.; Prest, M. J.; Whall, T. E. [Department of Physics, University of Warwick, Coventry CV4 7AL (United Kingdom); Prunnila, M. [VTT Technical Research Centre of Finland, P.O. Box 1000, FI-02044 VTT Espoo (Finland); Mauskopf, P. D. [School of Physics and Astronomy, Cardiff University, Queen' s Buildings, The Parade, Cardiff CF24 3AA (United Kingdom); Department of Physics and School of Earth and Space Exploration, Arizona State University, 650 E. Tyler Mall, Tempe, Arizona 85287 (United States)

2014-07-28

We describe optical characterisation of a strained silicon cold electron bolometer (CEB), operating on a 350 mK stage, designed for absorption of millimetre-wave radiation. The silicon cold electron bolometer utilises Schottky contacts between a superconductor and an n{sup ++} doped silicon island to detect changes in the temperature of the charge carriers in the silicon, due to variations in absorbed radiation. By using strained silicon as the absorber, we decrease the electron-phonon coupling in the device and increase the responsivity to incoming power. The strained silicon absorber is coupled to a planar aluminium twin-slot antenna designed to couple to 160 GHz and that serves as the superconducting contacts. From the measured optical responsivity and spectral response, we calculate a maximum optical efficiency of 50% for radiation coupled into the device by the planar antenna and an overall noise equivalent power, referred to absorbed optical power, of 1.1×10{sup −16} W Hz{sup −1/2} when the detector is observing a 300 K source through a 4 K throughput limiting aperture. Even though this optical system is not optimized, we measure a system noise equivalent temperature difference of 6 mK Hz{sup −1/2}. We measure the noise of the device using a cross-correlation of time stream data, measured simultaneously with two junction field-effect transistor amplifiers, with a base correlated noise level of 300 pV Hz{sup −1/2} and find that the total noise is consistent with a combination of photon noise, current shot noise, and electron-phonon thermal noise.

Gate Tunable Transport in Graphene/MoS₂/(Cr/Au) Vertical Field-Effect Transistors.

Science.gov (United States)

Nazir, Ghazanfar; Khan, Muhammad Farooq; Aftab, Sikandar; Afzal, Amir Muhammad; Dastgeer, Ghulam; Rehman, Malik Abdul; Seo, Yongho; Eom, Jonghwa

2017-12-28

Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS₂/(Cr/Au) vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr), the electrical transport in our Gr/MoS₂/(Cr/Au) vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS₂ can be modified by back-gate voltage and the current bias. Vertical resistance (R vert ) of a Gr/MoS₂/(Cr/Au) transistor is compared with planar resistance (R planar ) of a conventional lateral MoS₂ field-effect transistor. We have also studied electrical properties for various thicknesses of MoS₂ channels in both vertical and lateral transistors. As the thickness of MoS₂ increases, R vert increases, but R planar decreases. The increase of R vert in the thicker MoS₂ film is attributed to the interlayer resistance in the vertical direction. However, R planar shows a lower value for a thicker MoS₂ film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

Science.gov (United States)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

Science.gov (United States)

Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

2018-02-01

We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

The impact of silicon nano-wire technology on the design of single-work-function CMOS transistors and circuits

International Nuclear Information System (INIS)

Bindal, Ahmet; Hamedi-Hagh, Sotoudeh

2006-01-01

This three-dimensional exploratory study on vertical silicon wire MOS transistors with metal gates and undoped bodies demonstrates that these transistors dissipate less power and occupy less layout area while producing comparable transient response with respect to the state-of-the-art bulk and SOI technologies. The study selects a single metal gate work function for both NMOS and PMOS transistors to alleviate fabrication difficulties and then determines a common device geometry to produce an OFF current smaller than 1 pA for each transistor. Once an optimum wire radius and effective channel length is determined, DC characteristics including threshold voltage roll-off, drain-induced barrier lowering and sub-threshold slope of each transistor are measured. Simple CMOS gates such as an inverter, two- and three-input NAND, NOR and XOR gates and a full adder, composed of the optimum NMOS and PMOS transistors, are built to measure transient performance, power dissipation and layout area. Simulation results indicate that worst-case transient time and worst-case delay are 1.63 and 1.46 ps, respectively, for a two-input NAND gate and 7.51 and 7.43 ps, respectively, for a full adder for a fan-out of six transistor gates (24 aF). Worst-case power dissipation is 62.1 nW for a two-input NAND gate and 118.1 nW for a full adder at 1 GHz for the same output capacitance. The layout areas are 0.0066 μm 2 for the two-input NAND gate and 0.049 μm 2 for the full adder circuits

Fabrication and characterization of novel gate-all-around polycrystalline silicon junctionless field-effect transistors with ultrathin horizontal tube-shape channel

Science.gov (United States)

Chang, You-Tai; Peng, Kang-Ping; Li, Pei-Wen; Lin, Horng-Chih

2018-04-01

In this paper, we report on a novel fabrication process for the production of junctionless field-effect transistors with an ultrathin polycrystalline silicon (poly-Si) tube channel in a gate-all-around (GAA) configuration. The core of the poly-Si tube channel is filled with either a silicon nitride or a silicon oxide layer, and the effects of the core layers on the device characteristics are evaluated. The devices show excellent switching performance, thanks to the combination of the ultrathin tube channel and the GAA structure. Hysteresis loops in the transfer characteristics of the nitride-core devices are observed, owing to the dynamic trapping of electrons in the nitride core.

Bottom-Up Tri-gate Transistors and Submicrosecond Photodetectors from Guided CdS Nanowalls.

Science.gov (United States)

Xu, Jinyou; Oksenberg, Eitan; Popovitz-Biro, Ronit; Rechav, Katya; Joselevich, Ernesto

2017-11-08

Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or "fins"). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm 2 ) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10 8 , 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.

Gold nanoparticle-pentacene memory-transistors

OpenAIRE

Novembre , Christophe; Guerin , David; Lmimouni , Kamal; Gamrat , Christian; Vuillaume , Dominique

2008-01-01

We demonstrate an organic memory-transistor device based on a pentacene-gold nanoparticles active layer. Gold (Au) nanoparticles are immobilized on the gate dielectric (silicon dioxide) of a pentacene transistor by an amino-terminated self-assembled monolayer. Under the application of writing and erasing pulses on the gate, large threshold voltage shift (22 V) and on/off drain current ratio of ~3E4 are obtained. The hole field-effect mobility of the transistor is similar in the on and off sta...

Optical study of Erbium-doped-porous silicon based planar waveguides

Energy Technology Data Exchange (ETDEWEB)

Najar, A. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B.P. 80518, 22305 Lannion Cedex (France) and Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia)]. E-mail: najar.adel@laposte.net; Ajlani, H. [Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Charrier, J. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B.P. 80518, 22305 Lannion Cedex (France); Lorrain, N. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B.P. 80518, 22305 Lannion Cedex (France); Haesaert, S. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B.P. 80518, 22305 Lannion Cedex (France); Oueslati, M. [Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Haji, L. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B.P. 80518, 22305 Lannion Cedex (France)

2007-06-15

Planar waveguides were formed from porous silicon layers obtained on P{sup +} substrates. These waveguides were then doped by erbium using an electrochemical method. Erbium concentration in the range 2.2-2.5 at% was determined by energy dispersive X-ray (EDX) analysis performed on SEM cross sections. The refractive index of layers was studied before and after doping and thermal treatments. The photoluminescence of Er{sup 3+} ions in the IR range and the decay curve of the 1.53 {mu}m emission peak were studied as a function of the excitation power. The value of excited Er density was equal to 0.07%. Optical loss contributions were analyzed on these waveguides and the losses were equal to 1.1 dB/cm at 1.55 {mu}m after doping.

Coaxial-structured ZnO/silicon nanowires extended-gate field-effect transistor as pH sensor

International Nuclear Information System (INIS)

Li, Hung-Hsien; Yang, Chi-En; Kei, Chi-Chung; Su, Chung-Yi; Dai, Wei-Syuan; Tseng, Jung-Kuei; Yang, Po-Yu; Chou, Jung-Chuan; Cheng, Huang-Chung

2013-01-01

An extended-gate field-effect transistor (EGFET) of coaxial-structured ZnO/silicon nanowires as pH sensor was demonstrated in this paper. The oriented 1-μm-long silicon nanowires with the diameter of about 50 nm were vertically synthesized by the electroless metal deposition method at room temperature and were sequentially capped with the ZnO films using atomic layer deposition at 50 °C. The transfer characteristics (I DS –V REF ) of such ZnO/silicon nanowire EGFET sensor exhibited the sensitivity and linearity of 46.25 mV/pH and 0.9902, respectively for the different pH solutions (pH 1–pH 13). In contrast to the ZnO thin-film ones, the ZnO/silicon nanowire EGFET sensor achieved much better sensitivity and superior linearity. It was attributed to a high surface-to-volume ratio of the nanowire structures, reflecting a larger effective sensing area. The output voltage and time characteristics were also measured to indicate good reliability and durability for the ZnO/silicon nanowires sensor. Furthermore, the hysteresis was 9.74 mV after the solution was changed as pH 7 → pH 3 → pH 7 → pH 11 → pH 7. - Highlights: ► Coaxial-structured ZnO/silicon nanowire EGFET was demonstrated as pH sensor. ► EMD and ALD methods were proposed to fabricate ZnO/silicon nanowires. ► ZnO/silicon nanowire EGFET sensor achieved better sensitivity and linearity. ► ZnO/silicon nanowire EGFET sensor had good reliability and durability

Low-background transistors for application in nuclear electronics

International Nuclear Information System (INIS)

Krasnokutskij, R.N.; Kurchaninov, L.L.; Fedyakin, N.N.; Shuvalov, R.S.

1988-01-01

Investigations of silicon transistors were carried out to determine transistors with low value of base distributed resistance (R). Measurement results for R and current amplification coefficient β are presented for bipolar transistor several types. Correlations between R and β were studied. KT 399A, 2T640A and KT3117B transistors are found to be most adequate ones as a base for low-background amplifier development

BUSFET -- A radiation-hardened SOI transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

International Nuclear Information System (INIS)

Liu Ying; He Jin; Chan Mansun; Ye Yun; Zhao Wei; Wu Wen; Deng Wan-Ling; Wang Wen-Ping; Du Cai-Xia

2014-01-01

An analytical model of gate-all-around (GAA) silicon nanowire tunneling field effect transistors (NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling (BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane's expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Parametrization of the radiation induced leakage current increase of NMOS transistors

International Nuclear Information System (INIS)

Backhaus, M.

2017-01-01

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to silicon dioxide interface the leakage current results as a function of the exposure time to ionizing radiation. This function is fitted to data of the leakage current of single transistors as well as to data of the supply current of full ASICs.

BUSFET - A Novel Radiation-Hardened SOI Transistor

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

1999-01-01

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

Improvements in or relating to transistor circuits

International Nuclear Information System (INIS)

Richards, R.F.; Williamson, P.W.

1978-01-01

This invention relates to transistor circuits and in particular to integrated transistor circuits formed on a substrate of semi-conductor material such as silicon. The invention is concerned with providing integrated circuits in which malfunctions caused by the effects of ionising, e.g. nuclear, radiations are reduced. (author)

Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.

Science.gov (United States)

Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon

2016-10-20

Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

Science.gov (United States)

Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

2017-10-01

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

Process Simulation and Characterization of Substrate Engineered Silicon Thin Film Transistor for Display Sensors and Large Area Electronics

International Nuclear Information System (INIS)

Hashmi, S M; Ahmed, S

2013-01-01

Design, simulation, fabrication and post-process qualification of substrate-engineered Thin Film Transistors (TFTs) are carried out to suggest an alternate manufacturing process step focused on display sensors and large area electronics applications. Damage created by ion implantation of Helium and Silicon ions into single-crystalline n-type silicon substrate provides an alternate route to create an amorphized region responsible for the fabrication of TFT structures with controllable and application-specific output parameters. The post-process qualification of starting material and full-cycle devices using Rutherford Backscattering Spectrometry (RBS) and Proton or Particle induced X-ray Emission (PIXE) techniques also provide an insight to optimize the process protocols as well as their applicability in the manufacturing cycle

Nanogranular SiO{sub 2} proton gated silicon layer transistor mimicking biological synapses

Energy Technology Data Exchange (ETDEWEB)

Liu, M. J.; Huang, G. S., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Guo, Q. L.; Tian, Z. A.; Li, G. J.; Mei, Y. F. [Department of Materials Science, Fudan University, Shanghai 200433 (China); Feng, P., E-mail: gshuang@fudan.edu.cn, E-mail: pfeng@nju.edu.cn; Shao, F.; Wan, Q. [School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

2016-06-20

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO{sub 2} proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Harnessing light energy with a planar transparent hybrid of graphene/single wall carbon nanotube/n-type silicon heterojunction solar cell

DEFF Research Database (Denmark)

Chen, Leifeng; Yu, Hua; Zhong, Jiasong

2015-01-01

The photovoltaic conversion efficiency of a solar cell fabricated by a simple electrophoretic method with a planar transparent hybrid of graphenes (GPs) and single wall carbon nanotubes (SCNTs)/n-type silicon heterojunction was significantly increased compared to GPs/n-Si and SCNTs/n-Si solar cells...

On theory of single-molecule transistor

International Nuclear Information System (INIS)

Tran Tien Phuc

2009-01-01

The results of the study on single-molecule transistor are mainly investigated in this paper. The structure of constructed single-molecule transistor is similar to a conventional MOSFET. The conductive channel of the transistors is a single-molecule of halogenated benzene derivatives. The chemical simulation software CAChe was used to design and implement for the essential parameter of the molecules utilized as the conductive channel. The GUI of Matlab has been built to design its graphical interface, calculate and plot the output I-V characteristic curves for the transistor. The influence of temperature, length and width of the conductive channel, and gate voltage is considered. As a result, the simulated curves are similar to the traditional MOSFET's. The operating temperature range of the transistors is wider compared with silicon semiconductors. The supply voltage for transistors is only about 1 V. The size of transistors in this research is several nanometers.

CMOS-compatible fabrication of top-gated field-effect transistor silicon nanowire-based biosensors

International Nuclear Information System (INIS)

Ginet, Patrick; Akiyama, Sho; Takama, Nobuyuki; Fujita, Hiroyuki; Kim, Beomjoon

2011-01-01

Field-effect transistor (FET) nanowire-based biosensors are very promising tools for medical diagnosis. In this paper, we introduce a simple method to fabricate FET silicon nanowires using only standard microelectromechanical system (MEMS) processes. The key steps of our fabrication process were a local oxidation of silicon (LOCOS) and anisotropic KOH etchings that enabled us to reduce the width of the initial silicon structures from 10 µm to 170 nm. To turn the nanowires into a FET, a top-gate electrode was patterned in gold next to them in order to apply the gate voltage directly through the investigated liquid environment. An electrical characterization demonstrated the p-type behaviour of the nanowires. Preliminary chemical sensing tested the sensitivity to pH of our device. The effect of the binding of streptavidin on biotinylated nanowires was monitored in order to evaluate their biosensing ability. In this way, streptavidin was detected down to a 100 ng mL −1 concentration in phosphate buffered saline by applying a gate voltage less than 1.2 V. The use of a top-gate electrode enabled the detection of biological species with only very low voltages that were compatible with future handheld-requiring applications. We thus demonstrated the potential of our devices and their fabrication as a solution for the mass production of efficient and reliable FET nanowire-based biological sensors

Transistor reset preamplifier for high-rate high-resolution spectroscopy

International Nuclear Information System (INIS)

Landis, D.A.; Cork, C.P.; Madden, N.W.; Goulding, F.S.

1981-10-01

Pulsed transistor reset of high resolution charge sensitive preamplifiers used in cooled semiconductor spectrometers can sometimes have an advantage over pulsed light reset systems. Several versions of transistor reset spectrometers using both silicon and germanium detectors have been built. This paper discusses the advantages of the transistor reset system and illustrates several configurations of the packages used for the FET and reset transistor. It also describes the preamplifer circuit and shows the performance of the spectrometer at high rates

Investigation of neutron-produced defects in silicon by transconductance measurements of junction field-effect transistors

International Nuclear Information System (INIS)

Tokuda, Y.; Usami, A.

1976-01-01

Defects introduced in silicon by neutron irradiation were investigated by measuring the phase angle theta of the small-signal transconductance of the junction field-effect transistors (JFET). Measurements of theta as a function of frequency allowed the determination of the time constant for each defect. From the temperature dependence of the time constant, assuming that capture cross sections are independent of temperature, the energy levels of E/sub v/+0.19 and E/sub v/+0.35 eV in p-type silicon and E/sub c/-0.16, E/sub c/-0.19, and E/sub c/-0.44 eV in n-type silicon were obtained. For these defects, calculations gave majority-carrier capture cross-section values of 2.8 x 10 -15 and 1.1 x 10 -14 cm 2 in p-type silicon, and 3.9 x 10 -14 , 1.6 x 10 -16 , and 2.3 x 10 -14 cm 2 in n-type silicon, respectively. Comparing with other published data, it was found that the energy level of E/sub c/-0.44 eV showed the value between the previously reported energy levels of E/sub c/-0.4 and E/sub c/-0.5 eV correlated with the doubly negative charge state and singly negative charge state of the divacancy, respectively. Thus, it is believed that a total of six energy levels are introduced in silicon by neutron irradiation. The energy levels of E/sub c/-0.16 and E/sub v/+0.35 eV were found to be correlated with the A center and the divacancy, respectively

Radiation effect on silicon transistors in mixed neutrons-gamma environment

Science.gov (United States)

Assaf, J.; Shweikani, R.; Ghazi, N.

2014-10-01

The effects of gamma and neutron irradiations on two different types of transistors, Junction Field Effect Transistor (JFET) and Bipolar Junction Transistor (BJT), were investigated. Irradiation was performed using a Syrian research reactor (RR) (Miniature Neutron Source Reactor (MNSR)) and a gamma source (Co-60 cell). For RR irradiation, MCNP code was used to calculate the absorbed dose received by the transistors. The experimental results showed an overall decrease in the gain factors of the transistors after irradiation, and the JFETs were more resistant to the effects of radiation than BJTs. The effect of RR irradiation was also greater than that of gamma source for the same dose, which could be because neutrons could cause more damage than gamma irradiation.

Analytical and Experimental Evaluation of Joining Silicon Carbide to Silicon Carbide and Silicon Nitride to Silicon Nitride for Advanced Heat Engine Applications Phase II

Energy Technology Data Exchange (ETDEWEB)

Sundberg, G.J.

1994-01-01

Techniques were developed to produce reliable silicon nitride to silicon nitride (NCX-5101) curved joins which were used to manufacture spin test specimens as a proof of concept to simulate parts such as a simple rotor. Specimens were machined from the curved joins to measure the following properties of the join interlayer: tensile strength, shear strength, 22 C flexure strength and 1370 C flexure strength. In parallel, extensive silicon nitride tensile creep evaluation of planar butt joins provided a sufficient data base to develop models with accurate predictive capability for different geometries. Analytical models applied satisfactorily to the silicon nitride joins were Norton's Law for creep strain, a modified Norton's Law internal variable model and the Monkman-Grant relationship for failure modeling. The Theta Projection method was less successful. Attempts were also made to develop planar butt joins of siliconized silicon carbide (NT230).

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

International Nuclear Information System (INIS)

Hanna, A. N.; Ghoneim, M. T.; Bahabry, R. R.; Hussain, A. M.; Hussain, M. M.

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir; Ghoneim, Mohamed T.; Bahabry, Rabab R.; Hussain, Aftab M.; Hussain, Muhammad Mustafa

2013-01-01

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Zinc oxide integrated area efficient high output low power wavy channel thin film transistor

KAUST Repository

Hanna, Amir

2013-11-26

We report an atomic layer deposition based zinc oxide channel material integrated thin film transistor using wavy channel architecture allowing expansion of the transistor width in the vertical direction using the fin type features. The experimental devices show area efficiency, higher normalized output current, and relatively lower power consumption compared to the planar architecture. This performance gain is attributed to the increased device width and an enhanced applied electric field due to the architecture when compared to a back gated planar device with the same process conditions.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface

International Nuclear Information System (INIS)

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-01-01

Silicon nanowire field effect transistor sensors with SiO 2 /HfO 2 as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO 2 as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Optimization of pH sensing using silicon nanowire field effect transistors with HfO2 as the sensing surface.

Science.gov (United States)

Zafar, Sufi; D'Emic, Christopher; Afzali, Ali; Fletcher, Benjamin; Zhu, Y; Ning, Tak

2011-10-07

Silicon nanowire field effect transistor sensors with SiO(2)/HfO(2) as the gate dielectric sensing surface are fabricated using a top down approach. These sensors are optimized for pH sensing with two key characteristics. First, the pH sensitivity is shown to be independent of buffer concentration. Second, the observed pH sensitivity is enhanced and is equal to the Nernst maximum sensitivity limit of 59 mV/pH with a corresponding subthreshold drain current change of ∼ 650%/pH. These two enhanced pH sensing characteristics are attributed to the use of HfO(2) as the sensing surface and an optimized fabrication process compatible with silicon processing technology.

Vertically aligned carbon nanotube field-effect transistors

KAUST Repository

Li, Jingqi

2012-10-01

Vertically aligned carbon nanotube field-effect transistors (CNTFETs) have been developed using pure semiconducting carbon nanotubes. The source and drain were vertically stacked, separated by a dielectric, and the carbon nanotubes were placed on the sidewall of the stack to bridge the source and drain. Both the effective gate dielectric and gate electrode were normal to the substrate surface. The channel length is determined by the dielectric thickness between source and drain electrodes, making it easier to fabricate sub-micrometer transistors without using time-consuming electron beam lithography. The transistor area is much smaller than the planar CNTFET due to the vertical arrangement of source and drain and the reduced channel area. © 2012 Elsevier Ltd. All rights reserved.

Narrow, highly P-doped, planar wires in silicon created by scanning probe microscopy

Energy Technology Data Exchange (ETDEWEB)

Ruess, F J [Australian Research Council Centre of Excellence for Quantum Computer Technology, University of New South Wales, Sydney, NSW 2052 (Australia); Goh, K E J [Australian Research Council Centre of Excellence for Quantum Computer Technology, University of New South Wales, Sydney, NSW 2052 (Australia); Butcher, M J [School of Physics, University of New South Wales, Sydney, NSW 2052 (Australia); Reusch, T C G [Australian Research Council Centre of Excellence for Quantum Computer Technology, University of New South Wales, Sydney, NSW 2052 (Australia); Oberbeck, L [Australian Research Council Centre of Excellence for Quantum Computer Technology, University of New South Wales, Sydney, NSW 2052 (Australia); Weber, B [School of Physics, University of New South Wales, Sydney, NSW 2052 (Australia); Hamilton, A R [School of Physics, University of New South Wales, Sydney, NSW 2052 (Australia); Simmons, M Y [Australian Research Council Centre of Excellence for Quantum Computer Technology, University of New South Wales, Sydney, NSW 2052 (Australia)

2007-01-31

We demonstrate the use of a scanning tunnelling microscope (STM) to pattern buried, highly planar phosphorus-doped silicon wires with widths down to the sub-10 nm level. We confirm the structural integrity of these wires using both buried dopant imaging techniques and ex situ electrical characterization. Four terminal I-V characteristics at 4 K show ohmic behaviour for all wires with resistivities between 1 and 24 x 10{sup -8} {omega} cm. Magnetotransport measurements reveal that conduction is dominated by disordered scattering with quantum corrections consistent with 2D weak localization theory. Our results show that these quantum corrections become more pronounced as the electron phase coherence length approaches the width of the wire.

Amorphous silicon pixel radiation detectors and associated thin film transistor electronics readout

International Nuclear Information System (INIS)

Perez-Mendez, V.; Drewery, J.; Hong, W.S.; Jing, T.; Kaplan, S.N.; Lee, H.; Mireshghi, A.

1994-10-01

We describe the characteristics of thin (1 μm) and thick (>30 μm) hydrogenated amorphous silicon p-i-n diodes which are optimized for detecting and recording the spatial distribution of charged particles, x-rays and γ rays. For x-ray, γ ray, and charged particle detection we can use thin p-i-n photosensitive diode arrays coupled to evaporated layers of suitable scintillators. For direct detection of charged particles with high resistance to radiation damage, we use the thick p-i-n diode arrays. Deposition techniques using helium dilution, which produce samples with low stress are described. Pixel arrays for flux exposures can be readout by transistor, single diode or two diode switches. Polysilicon charge sensitive pixel amplifiers for single event detection are described. Various applications in nuclear, particle physics, x-ray medical imaging, neutron crystallography, and radionuclide chromatography are discussed

High mobility and quantum well transistors design and TCAD simulation

CERN Document Server

Hellings, Geert

2013-01-01

For many decades, the semiconductor industry has miniaturized transistors, delivering increased computing power to consumers at decreased cost. However, mere transistor downsizing does no longer provide the same improvements. One interesting option to further improve transistor characteristics is to use high mobility materials such as germanium and III-V materials. However, transistors have to be redesigned in order to fully benefit from these alternative materials. High Mobility and Quantum Well Transistors: Design and TCAD Simulation investigates planar bulk Germanium pFET technology in chapters 2-4, focusing on both the fabrication of such a technology and on the process and electrical TCAD simulation. Furthermore, this book shows that Quantum Well based transistors can leverage the benefits of these alternative materials, since they confine the charge carriers to the high-mobility material using a heterostructure. The design and fabrication of one particular transistor structure - the SiGe Implant-Free Qu...

Parametrization of the radiation induced leakage current increase of NMOS transistors

CERN Document Server

Backhaus, Malte

2017-01-13

The increase of the leakage current of NMOS transistors during exposure to ionizing radiation is known and well studied. Radiation hardness by design techniques have been developed to mitigate this effect and have been successfully used. More recent developments in smaller feature size technologies do not make use of these techniques due to their drawbacks in terms of logic density and requirement of dedicated libraries. During operation the resulting increase of the supply current is a serious challenge and needs to be considered during the system design. A simple parametrization of the leakage current of NMOS transistors as a function of total ionizing dose is presented. The parametrization uses a transistor transfer characteristics of the parasitic transistor along the shallow trench isolation to describe the leakage current of the nominal transistor. Together with a parametrization of the number of positive charges trapped in the silicon dioxide and number of activated interface traps in the silicon to si...

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates.

Science.gov (United States)

Lee, Myeongwon; Koo, Jamin; Chung, Eun-Ae; Jeong, Dong-Young; Koo, Yong-Seo; Kim, Sangsig

2009-11-11

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p+ drain and n+ channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates

International Nuclear Information System (INIS)

Lee, Myeongwon; Koo, Jamin; Chung, Eun-Ae; Jeong, Dong-Young; Kim, Sangsig; Koo, Yong-Seo

2009-01-01

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p + drain and n + channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates

Energy Technology Data Exchange (ETDEWEB)

Lee, Myeongwon; Koo, Jamin; Chung, Eun-Ae; Jeong, Dong-Young; Kim, Sangsig [Department of Electrical Engineering and Institute for Nano Science, Korea University, 5-1, Anam-Dong, Seongbuk-Gu, Seoul 136-701 (Korea, Republic of); Koo, Yong-Seo, E-mail: sangsig@korea.ac.k [Department of Electrical Engineering, Seokyeong University, 16-1, Jungneung-dong, Seongbuk-gu, Seoul 136-704 (Korea, Republic of)

2009-11-11

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p{sup +} drain and n{sup +} channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

Science.gov (United States)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Optical study of planar waveguides based on oxidized porous silicon impregnated with laser dyes

Energy Technology Data Exchange (ETDEWEB)

Chouket, A. [Unite de recherche de Spectroscopie Raman, Departement de Physique, Faculte des Sciences de Tunis, Elmanar 2092, Tunis (Tunisia); Charrier, J. [Laboratoire d' Optronique CNRS-UMR FOTON 6082, Universite de Rennes 1, ENSSAT-6 rue de Kerampont, BP 80518, 22305 Lannion Cedex (France); Elhouichet, H. [Unite de recherche de Spectroscopie Raman, Departement de Physique, Faculte des Sciences de Tunis, Elmanar 2092, Tunis (Tunisia)], E-mail: habib.elhouichet@fst.rnu.tn; Oueslati, M. [Unite de recherche de Spectroscopie Raman, Departement de Physique, Faculte des Sciences de Tunis, Elmanar 2092, Tunis (Tunisia)

2009-05-15

Oxidized porous silicon optical planar waveguides were elaborated and impregnated with rhodamine B and rhodamine 6G. The waveguiding, absorption, and photoluminescence properties of these impregnated waveguides were studied. Successful impregnation of the structure with laser dyes is shown from photoluminescence and reflectivity measurements. Furthermore, the reflectivity spectra prove the homogenous incorporation of both dye molecules inside the pores of the matrices. The refractive indices of waveguide layers were determined before and after dye impregnation to indicate the conservation of guiding conditions. The optical losses in the visible wavelengths are studied as a function of dye concentration. The dye absorption is the main reason for these losses.

Artificial neural systems using memristive synapses and nano-crystalline silicon thin-film transistors

Science.gov (United States)

Cantley, Kurtis D.

Future computer systems will not rely solely on digital processing of inputs from well-defined data sets. They will also be required to perform various computational tasks using large sets of ill-defined information from the complex environment around them. The most efficient processor of this type of information known today is the human brain. Using a large number of primitive elements (˜1010 neurons in the neocortex) with high parallel connectivity (each neuron has ˜104 synapses), brains have the remarkable ability to recognize and classify patterns, predict outcomes, and learn from and adapt to incredibly diverse sets of problems. A reasonable goal in the push to increase processing power of electronic systems would thus be to implement artificial neural networks in hardware that are compatible with today's digital processors. This work focuses on the feasibility of utilizing non-crystalline silicon devices in neuromorphic electronics. Hydrogenated amorphous silicon (a-Si:H) nanowire transistors with Schottky barrier source/drain junctions, as well as a-Si:H/Ag resistive switches are fabricated and characterized. In the transistors, it is found that the on-current scales linearly with the effective width W eff of the channel nanowire array down to at least 20 nm. The solid-state electrolyte resistive switches (memristors) are shown to exhibit the proper current-voltage hysteresis. SPICE models of similar devices are subsequently developed to investigate their performance in neural circuits. The resulting SPICE simulations demonstrate spiking properties and synaptic learning rules that are incredibly similar to those in biology. Specifically, the neuron circuits can be designed to mimic the firing characteristics of real neurons, and Hebbian learning rules are investigated. Finally, some applications are presented, including associative learning analogous to the classical conditioning experiments originally performed by Pavlov, and frequency and pattern

Direct-current substrate bias effects on amorphous silicon sputter-deposited films for thin film transistor fabrication

International Nuclear Information System (INIS)

Jun, Seung-Ik; Rack, Philip D.; McKnight, Timothy E.; Melechko, Anatoli V.; Simpson, Michael L.

2005-01-01

The effect that direct current (dc) substrate bias has on radio frequency-sputter-deposited amorphous silicon (a-Si) films has been investigated. The substrate bias produces a denser a-Si film with fewer defects compared to unbiased films. The reduced number of defects results in a higher resistivity because defect-mediated conduction paths are reduced. Thin film transistors (TFTs) that were completely sputter deposited were fabricated and characterized. The TFT with the biased a-Si film showed lower leakage (off-state) current, higher on/off current ratio, and higher transconductance (field effect mobility) than the TFT with the unbiased a-Si film

Pushing the Performance Limit of Sub-100 nm Molybdenum Disulfide Transistors.

Science.gov (United States)

Liu, Yuan; Guo, Jian; Wu, Yecun; Zhu, Enbo; Weiss, Nathan O; He, Qiyuan; Wu, Hao; Cheng, Hung-Chieh; Xu, Yang; Shakir, Imran; Huang, Yu; Duan, Xiangfeng

2016-10-12

Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS 2 ) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS 2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS 2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized contact in short channel devices, we demonstrate sub-100 nm MoS 2 transistor delivering a record high ON-current of 0.83 mA/μm at 300 K and 1.48 mA/μm at 20 K, which compares well with that of silicon devices. Our study, for the first time, demonstrates that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2DSC electronics.

Analysing organic transistors based on interface approximation

International Nuclear Information System (INIS)

Akiyama, Yuto; Mori, Takehiko

2014-01-01

Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region

DC characteristics and parameters of silicon carbide high-voltage power BJTs

International Nuclear Information System (INIS)

Patrzyk, Joanna; Zarębski, Janusz; Bisewski, Damian

2016-01-01

The paper shows the static characteristics and operating parameters of the bipolar power transistors made of silicon carbide and for comparison their equivalents made of classical silicon technology. The characteristics and values of selected operating parameters with special emphasis on the effect of temperature and operating point of considered devices are discussed. Quantitative as well as qualitative differences between the characteristics of the transistor made of silicon and silicon carbide are indicated as well

The Complete Semiconductor Transistor and Its Incomplete Forms

International Nuclear Information System (INIS)

Jie Binbin; Sah, C.-T.

2009-01-01

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor, BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

Institute of Scientific and Technical Information of China (English)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38％ reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10％ reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40％ of those of the superjunction MOSFET,respectively.

Applications, Prospects and Challenges of Silicon Carbide Junction Field Effect Transistor (SIC JFET

Directory of Open Access Journals (Sweden)

Frederick Ojiemhende Ehiagwina

2016-09-01

Full Text Available Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si.  A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.

Performance Enhancement of Power Transistors and Radiation effect

International Nuclear Information System (INIS)

Hassn, Th.A.A.

2012-01-01

The main objective of this scientific research is studying the characteristic of bipolar junction transistor device and its performance under radiation fields and temperature effect as a control element in many power circuits. In this work we present the results of experimental measurements and analytical simulation of gamma – radiation effects on the electrical characteristics and operation of power transistor types 2N3773, 2N3055(as complementary silicon power transistor are designed for general-purpose switching and amplifier applications), three samples of each type were irradiated by gamma radiation with doses, 1 K rad, 5 K rad, 10 K rad, 30 K rad, and 10 Mrad, the experimental data are utilized to establish an analytical relation between the total absorbed dose of gamma irradiation and corresponding to effective density of generated charge in the internal structure of transistor, the electrical parameters which can be measured to estimate the generated defects in the power transistor are current gain, collector current and collected emitter leakage current , these changes cause the circuit to case proper functioning. Collector current and transconductance of each device are calibrated as a function of irradiated dose. Also the threshold voltage and transistor gain can be affected and also calibrated as a function of dose. A silicon NPN power transistor type 2N3773 intended for general purpose applications, were used in this work. It was designed for medium current and high power circuits. Performance and characteristic were discusses under temperature and gamma radiation doses. Also the internal junction thermal system of the transistor represented in terms of a junction thermal resistance (Rjth). The thermal resistance changed by ΔRjth, due to the external intended, also due to the gamma doses intended. The final result from the model analysis reveals that the emitter-bias configuration is quite stable by resistance ratio RB/RE. Also the current

Lg = 100 nm T-shaped gate AlGaN/GaN HEMTs on Si substrates with non-planar source/drain regrowth of highly-doped n+-GaN layer by MOCVD

International Nuclear Information System (INIS)

Huang Jie; Li Ming; Tang Chak-Wah; Lau Kei-May

2014-01-01

High-performance AlGaN/GaN high electron mobility transistors (HEMTs) grown on silicon substrates by metal—organic chemical-vapor deposition (MOCVD) with a selective non-planar n-type GaN source/drain (S/D) regrowth are reported. A device exhibited a non-alloyed Ohmic contact resistance of 0.209 Ω·mm and a comprehensive transconductance (g m ) of 247 mS/mm. The current gain cutoff frequency f T and maximum oscillation frequency f MAX of 100-nm HEMT with S/D regrowth were measured to be 65 GHz and 69 GHz. Compared with those of the standard GaN HEMT on silicon substrate, the f T and f MAX is 50% and 52% higher, respectively. (interdisciplinary physics and related areas of science and technology)

Electrical characteristics of silicon percolating nanonet-based field effect transistors in the presence of dispersion

Science.gov (United States)

Cazimajou, T.; Legallais, M.; Mouis, M.; Ternon, C.; Salem, B.; Ghibaudo, G.

2018-05-01

We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in back-gated transistor mode, for future use as gas or biosensors. These devices featured P-type field-effect characteristics. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as apparent low field mobility, threshold voltage and subthreshold slope ideality factor. Their variation with channel length and nanowire density was related to the change of conduction regime from direct source/drain connection by parallel nanowires to percolating channels. Experimental results could be related in part to an influence of the threshold voltage dispersion of individual nanowires.

The Bipolar Field-Effect Transistor: XIII. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

International Nuclear Information System (INIS)

Sah, C.-T.; Jie Binbin

2009-01-01

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

Science.gov (United States)

Kukita, Kentaro; Uechi, Tadayoshi; Shimokawa, Junji; Goto, Masakazu; Yokota, Yoshinori; Kawanaka, Shigeru; Tanamoto, Tetsufumi; Tanimoto, Hiroyoshi; Takagi, Shinichi

2018-04-01

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= V gs = V ds) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current I on (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length L ov.

Proton migration mechanism for the instability of organic field-effect transistors

NARCIS (Netherlands)

Sharma, A.; Mathijssen, S.G.J.; Kemerink, M.; Leeuw, de D.M.; Bobbert, P.A.

2009-01-01

During prolonged application of a gate bias, organic field-effect transistors show an instability involving a gradual shift of the threshold voltage toward the applied gate bias voltage. We propose a model for this instability in p-type transistors with a silicon-dioxide gate dielectric, based on

Detection of DNA of genetically modified maize by a silicon nanowire field-effect transistor

International Nuclear Information System (INIS)

Pham, Van Binh; Tung Pham, Xuan Thanh; Duong Dang, Ngoc Thuy; Tuyen Le, Thi Thanh; Tran, Phu Duy; Nguyen, Thanh Chien; Nguyen, Van Quoc; Dang, Mau Chien; Tong, Duy Hien; Van Rijn, Cees J M

2011-01-01

A silicon nanowire field-effect transistor based sensor (SiNW-FET) has been proved to be the most sensitive and powerful device for bio-detection applications. In this paper, SiNWs were first fabricated by using our recently developed deposition and etching under angle technique (DEA), then used to build up the complete SiNW device based biosensor. The fabricated SiNW biosensor was used to detect DNA of genetically modified maize. As the DNA of the genetically modified maize has particular DNA sequences of 35S promoter, we therefore designed 21 mer DNA oligonucleotides, which are used as a receptor to capture the transferred DNA of maize. In our work, the SiNW biosensor could detect DNA of genetically modified maize with concentrations down to about 200 pM

Organic semiconductors for organic field-effect transistors

International Nuclear Information System (INIS)

Yamashita, Yoshiro

2009-01-01

The advantages of organic field-effect transistors (OFETs), such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed. (topical review)

Organic semiconductors for organic field-effect transistors

Directory of Open Access Journals (Sweden)

Yoshiro Yamashita

2009-01-01

Full Text Available The advantages of organic field-effect transistors (OFETs, such as low cost, flexibility and large-area fabrication, have recently attracted much attention due to their electronic applications. Practical transistors require high mobility, large on/off ratio, low threshold voltage and high stability. Development of new organic semiconductors is key to achieving these parameters. Recently, organic semiconductors have been synthesized showing comparable mobilities to amorphous-silicon-based FETs. These materials make OFETs more attractive and their applications have been attempted. New organic semiconductors resulting in high-performance FET devices are described here and the relationship between transistor characteristics and chemical structure is discussed.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

International Nuclear Information System (INIS)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R on,sp ), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R on,sp are investigated, and the optimized results with BV of 83 V and R on,sp of 54 mΩ·mm 2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior 'R on,sp /BV' trade-off to the conventional VDMOS (a 38% reduction of R on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively. (interdisciplinary physics and related areas of science and technology)

Transistor analogs of emergent iono-neuronal dynamics.

Science.gov (United States)

Rachmuth, Guy; Poon, Chi-Sang

2008-06-01

Neuromorphic analog metal-oxide-silicon (MOS) transistor circuits promise compact, low-power, and high-speed emulations of iono-neuronal dynamics orders-of-magnitude faster than digital simulation. However, their inherently limited input voltage dynamic range vs power consumption and silicon die area tradeoffs makes them highly sensitive to transistor mismatch due to fabrication inaccuracy, device noise, and other nonidealities. This limitation precludes robust analog very-large-scale-integration (aVLSI) circuits implementation of emergent iono-neuronal dynamics computations beyond simple spiking with limited ion channel dynamics. Here we present versatile neuromorphic analog building-block circuits that afford near-maximum voltage dynamic range operating within the low-power MOS transistor weak-inversion regime which is ideal for aVLSI implementation or implantable biomimetic device applications. The fabricated microchip allowed robust realization of dynamic iono-neuronal computations such as coincidence detection of presynaptic spikes or pre- and postsynaptic activities. As a critical performance benchmark, the high-speed and highly interactive iono-neuronal simulation capability on-chip enabled our prompt discovery of a minimal model of chaotic pacemaker bursting, an emergent iono-neuronal behavior of fundamental biological significance which has hitherto defied experimental testing or computational exploration via conventional digital or analog simulations. These compact and power-efficient transistor analogs of emergent iono-neuronal dynamics open new avenues for next-generation neuromorphic, neuroprosthetic, and brain-machine interface applications.

Studies of annealing of neutron-produced defects in silicon by transconductance measurements of junction field-effect transistors

International Nuclear Information System (INIS)

Tokuda, Y.; Usami, A.

1978-01-01

Annealing behavior of neutron-produced defects in silicon was studied by measuring the phase angle theta of the small-signal transconductance of the junction field-effect transistors (JFET's). Three deep levels (N-1, N-2, and N-3 levels) in n-type silicon and two deep levels (P-1 and P-2 levels) in p-type silicon, introduced by irradiation, annealed gradually. Their energy levels and capture cross sections have been already reported by us. Three deep levels (P-3, P-4, and P-5 levels) were observed in annealed p-type silicon in the temperature range 150--300 0 C. For these defects, theta was measured as a function of frequency to obtain the time constant. From the temperature dependence of the time constant, assuming that capture cross sections are independent of temperature, the energy levels of P-3, P-4, and P-5 were estimated to be E/sub v/+0.21, E/sub v/+0.40, and E/sub v/+0.30 eV, respectively. The calculated hole capture cross sections of these levels were 2.2 x 10 -15 , 8.7 x 10 -14 , and 1.2 x 10 -14 cm 2 , respectively. Comparison with other published data was made. It was found that N-3 and P-2 levels corresponded to the divacancy. Furthermore, it seemed that P-3, P-4, and P-5 levels corresponded to the high-order vacancy defects

Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

Directory of Open Access Journals (Sweden)

Gammon P.M.

2017-01-01

Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

A Novel SPM Probe with MOS Transistor and Nano Tip for Surface Electric Properties

International Nuclear Information System (INIS)

Lee, Sang H; Lim, Geunbae; Moon, Wonkyu

2007-01-01

In this paper, the novel SPM (Scanning Probe Microscope) probe with the planar MOS (Metal-Oxide-Semiconductor) transistor and the FIB (Focused Ion Beam) nano tip is fabricated for the surface electric properties. Since the MOS transistor has high working frequency, the device can overcome the speed limitation of EFM (Electrostatic Force Microscope) system. The sensitivity is also high, and no bulky device such as lock-in-amplifier is required. Moreover, the nano tip with nanometer scale tip radius is fabricated with FIB system, and the resolution can be improved. Therefore, the probe can rapidly detect small localized electric properties with high sensitivity and high resolution. The MOS transistor is fabricated with the common semiconductor process, and the nano tip is grown by the FIB system. The planar structure of the MOS transistor makes the fabrication process easier, which is the advantage on the commercial production. Various electric signals are applied using the function generator, and the measured data represent the well-established electric properties of the device. It shows the promising aspect of the local surface electric property detection with high sensitivity and high resolution

Highly Conductive Graphene/Ag Hybrid Fibers for Flexible Fiber-Type Transistors.

Science.gov (United States)

Yoon, Sang Su; Lee, Kang Eun; Cha, Hwa-Jin; Seong, Dong Gi; Um, Moon-Kwang; Byun, Joon-Hyung; Oh, Youngseok; Oh, Joon Hak; Lee, Wonoh; Lee, Jea Uk

2015-11-09

Mechanically robust, flexible, and electrically conductive textiles are highly suitable for use in wearable electronic applications. In this study, highly conductive and flexible graphene/Ag hybrid fibers were prepared and used as electrodes for planar and fiber-type transistors. The graphene/Ag hybrid fibers were fabricated by the wet-spinning/drawing of giant graphene oxide and subsequent functionalization with Ag nanoparticles. The graphene/Ag hybrid fibers exhibited record-high electrical conductivity of up to 15,800 S cm(-1). As the graphene/Ag hybrid fibers can be easily cut and placed onto flexible substrates by simply gluing or stitching, ion gel-gated planar transistors were fabricated by using the hybrid fibers as source, drain, and gate electrodes. Finally, fiber-type transistors were constructed by embedding the graphene/Ag hybrid fiber electrodes onto conventional polyurethane monofilaments, which exhibited excellent flexibility (highly bendable and rollable properties), high electrical performance (μh = 15.6 cm(2) V(-1) s(-1), Ion/Ioff > 10(4)), and outstanding device performance stability (stable after 1,000 cycles of bending tests and being exposed for 30 days to ambient conditions). We believe that our simple methods for the fabrication of graphene/Ag hybrid fiber electrodes for use in fiber-type transistors can potentially be applied to the development all-organic wearable devices.

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

International Nuclear Information System (INIS)

Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

2008-01-01

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

Science.gov (United States)

Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.

2016-03-01

This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.

Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

Energy Technology Data Exchange (ETDEWEB)

Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

2008-03-03

The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

Quality control on planar n-in-n pixel sensors — Recent progress of ATLAS planar pixel sensors

International Nuclear Information System (INIS)

Klingenberg, R.

2013-01-01

To extend the physics reach of the Large Hadron Collider (LHC), upgrades to the accelerator are planned which will increase the peak luminosity by a factor 5–10. To cope with the increased occupancy and radiation damage, the ATLAS experiment plans to introduce an all-silicon inner tracker with the high luminosity upgrade (HL-LHC). To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Upgrade Planar Pixel Sensor (PPS) R and D Project was established. Main areas of research are the performance of planar pixel sensors at highest fluences, the exploration of possibilities for cost reduction to enable the instrumentation of large areas, the achievement of slim or active edges to provide low geometric inefficiencies without the need for shingling of modules and the investigation of the operation of highly irradiated sensors at low thresholds to increase the efficiency. The Insertable b-layer (IBL) is the first upgrade project within the ATLAS experiment and will employ a new detector layer consisting of silicon pixel sensors, which were improved and prototyped in the framework of the planar pixel sensor R and D project. A special focus of this paper is the status of the development and testing of planar n-in-n pixel sensors including the quality control of the on-going series production and postprocessing of sensor wafers. A high yield of produced planar sensor wafers and FE-I4 double chip sensors after first steps of post-processing including under bump metallization and dicing is observed. -- Highlights: ► Prototypes of irradiated planar n-in-n sensors have been successfully tested under laboratory conditions. ► A quality assurance programme on the series production of planar sensors for the IBL has started. ► A high yield of double chip sensors during the series production is observed which are compatible to the specifications to this detector component.

Influence of metal induced crystallization parameters on the performance of polycrystalline silicon thin film transistors

International Nuclear Information System (INIS)

Pereira, L.; Barquinha, P.; Fortunato, E.; Martins, R.

2005-01-01

In this work, metal induced crystallization using nickel was employed to obtain polycrystalline silicon by crystallization of amorphous films for thin film transistor applications. The devices were produced through only one lithographic process with a bottom gate configuration using a new gate dielectric consisting of a multi-layer of aluminum oxide/titanium oxide produced by atomic layer deposition. The best results were obtained for TFTs with the active layer of poly-Si crystallized for 20 h at 500 deg. C using a nickel layer of 0.5 nm where the effective mobility is 45.5 cm 2 V -1 s -1 . The threshold voltage, the on/off current ratio and the sub-threshold voltage are, respectively, 11.9 V, 5.55x10 4 and 2.49 V/dec

Microwave-signal generation in a planar Gunn diode with radiation exposure taken into account

Energy Technology Data Exchange (ETDEWEB)

Obolenskaya, E. S., E-mail: bess009@mail.ru, E-mail: obolensk@rf.unn.ru; Tarasova, E. A.; Churin, A. Yu.; Obolensky, S. V. [Lobachevsky State University of Nizhny Novgorod (NNSU) (Russian Federation); Kozlov, V. A. [Russian Academy of Sciences, Institute for Physics of Microstructures (Russian Federation)

2016-12-15

Microwave-signal generation in planar Gunn diodes with a two-dimensional electron gas, in which we previously studied steady-state electron transport, is theoretically studied. The applicability of a control electrode similar to a field-effect transistor gate to control the parameters of the output diode microwave signal is considered. The results of physical-topological modeling of semiconductor structures with different diode active-region structures, i.e., without a quantum well, with one and two quantum wells separated by a potential barrier, are compared. The calculated results are compared with our previous experimental data on recording Gunn generation in a Schottky-gate field-effect transistor. It is theoretically and experimentally shown that the power of the signal generated by the planar Gunn diode with a quantum well and a control electrode is sufficient to implement monolithic integrated circuits of different functionalities. It is theoretically and experimentally shown that the use of a control electrode on account of the introduction of corrective feedback allows a significant increase in the radiation resistance of a microwave generator with Schottky-gate field-effect transistors.

Microwave-signal generation in a planar Gunn diode with radiation exposure taken into account

International Nuclear Information System (INIS)

Obolenskaya, E. S.; Tarasova, E. A.; Churin, A. Yu.; Obolensky, S. V.; Kozlov, V. A.

2016-01-01

Microwave-signal generation in planar Gunn diodes with a two-dimensional electron gas, in which we previously studied steady-state electron transport, is theoretically studied. The applicability of a control electrode similar to a field-effect transistor gate to control the parameters of the output diode microwave signal is considered. The results of physical-topological modeling of semiconductor structures with different diode active-region structures, i.e., without a quantum well, with one and two quantum wells separated by a potential barrier, are compared. The calculated results are compared with our previous experimental data on recording Gunn generation in a Schottky-gate field-effect transistor. It is theoretically and experimentally shown that the power of the signal generated by the planar Gunn diode with a quantum well and a control electrode is sufficient to implement monolithic integrated circuits of different functionalities. It is theoretically and experimentally shown that the use of a control electrode on account of the introduction of corrective feedback allows a significant increase in the radiation resistance of a microwave generator with Schottky-gate field-effect transistors.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

Science.gov (United States)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

CMOS-based carbon nanotube pass-transistor logic integrated circuits

Science.gov (United States)

Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

2012-01-01

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

Carbon nanotube transistors scaled to a 40-nanometer footprint.

Science.gov (United States)

Cao, Qing; Tersoff, Jerry; Farmer, Damon B; Zhu, Yu; Han, Shu-Jen

2017-06-30

The International Technology Roadmap for Semiconductors challenges the device research community to reduce the transistor footprint containing all components to 40 nanometers within the next decade. We report on a p-channel transistor scaled to such an extremely small dimension. Built on one semiconducting carbon nanotube, it occupies less than half the space of leading silicon technologies, while delivering a significantly higher pitch-normalized current density-above 0.9 milliampere per micrometer at a low supply voltage of 0.5 volts with a subthreshold swing of 85 millivolts per decade. Furthermore, we show transistors with the same small footprint built on actual high-density arrays of such nanotubes that deliver higher current than that of the best-competing silicon devices under the same overdrive, without any normalization. We achieve this using low-resistance end-bonded contacts, a high-purity semiconducting carbon nanotube source, and self-assembly to pack nanotubes into full surface-coverage aligned arrays. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

EDITORIAL: Reigniting innovation in the transistor Reigniting innovation in the transistor

Science.gov (United States)

Demming, Anna

2012-09-01

Today the transistor is integral to the electronic circuitry that wires our lives. When Bardeen and Brattain first observed an amplified signal by connecting electrodes to a germanium crystal they saw that their 'semiconductor triode' could prove a useful alternative to the more cumbersome vacuum tubes used at the time [1]. But it was perhaps William Schottky who recognized the extent of the transistor's potential. A basic transistor has three or more terminals and current across one pair of terminals can switch or amplify current through another pair. Bardeen, Brattain and Schottky were jointly awarded a Nobel Prize in 1956 'for their researches on semiconductors and their discovery of the transistor effect' [2]. Since then many new forms of the transistor have been developed and understanding of the underlying properties is constantly advancing. In this issue Chen and Shih and colleagues at Taiwan National University and Drexel University report a pyroelectrics transistor. They show how a novel optothermal gating mechanism can modulate the current, allowing a range of developments in nanoscale optoelectronics and wireless devices [3]. The explosion of interest in nanoscale devices in the 1990s inspired electronics researchers to look for new systems that can act as transistors, such as carbon nanotube [4] and silicon nanowire [5] transistors. Generally these transistors function by raising and lowering an energy barrier of kBT -1, but researchers in the US and Canada have demonstrated that the quantum interference between two electronic pathways through aromatic molecules can also modulate the current flow [6]. The device has advantages for further miniaturization where energy dissipation in conventional systems may eventually cause complications. Interest in transistor technology has also led to advances in fabrication techniques for achieving high production quantities, such as printing [7]. Researchers in Florida in the US demonstrated field effect transistor

Silicon photonic integration in telecommunications

Directory of Open Access Journals (Sweden)

Christopher Richard Doerr

2015-08-01

Full Text Available Silicon photonics is the guiding of light in a planar arrangement of silicon-based materials to perform various functions. We focus here on the use of silicon photonics to create transmitters and receivers for fiber-optic telecommunications. As the need to squeeze more transmission into a given bandwidth, a given footprint, and a given cost increases, silicon photonics makes more and more economic sense.

High Sensitivity pH Sensor Based on Porous Silicon (PSi) Extended Gate Field-Effect Transistor.

Science.gov (United States)

Al-Hardan, Naif H; Abdul Hamid, Muhammad Azmi; Ahmed, Naser M; Jalar, Azman; Shamsudin, Roslinda; Othman, Norinsan Kamil; Kar Keng, Lim; Chiu, Weesiong; Al-Rawi, Hamzah N

2016-06-07

In this study, porous silicon (PSi) was prepared and tested as an extended gate field-effect transistor (EGFET) for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Modeling and simulation of 4H-SiC field effect transistor

Science.gov (United States)

Pedryc, A.; Martychowiec, A.; Kociubiński, A.

2017-08-01

This paper presents the technological issue of silicon carbide MOSFET design. Through the use of simulations of silicon carbide transistor, the influence of the different the technological parameters are described and discussed. MOSFET transistor was performed in Silvaco TCAD using technology elaborated at Lublin University of Technology. The most important parameters related to ion implantation, which was used in p-i-n photodiode technology. The electrical simulations were performed, transfer and output characteristics for different values of technological parameters were generated - influence of gate oxide thickness on threshold voltage and influence of channel length modulation were checked. The results of simulations as well as transfer and output characteristics allowed to select optimal parameters between expected device working and available technology - gate oxide thickness and transistor channel length were established. This work was in fact carried out to increase our understanding of the device characteristics so as to allow the design of new SiC circuits which could meet the stressful requirements of ultraviolet detector systems.

Chemical vapor deposition based tungsten disulfide (WS2) thin film transistor

KAUST Repository

Hussain, Aftab M.

2013-04-01

Tungsten disulfide (WS2) is a layered transition metal dichalcogenide with a reported band gap of 1.8 eV in bulk and 1.32-1.4 eV in its thin film form. 2D atomic layers of metal dichalcogenides have shown changes in conductivity with applied electric field. This makes them an interesting option for channel material in field effect transistors (FETs). Therefore, we show a highly manufacturable chemical vapor deposition (CVD) based simple process to grow WS2 directly on silicon oxide in a furnace and then its transistor action with back gated device with room temperature field effect mobility of 0.1003 cm2/V-s using the Schottky barrier contact model. We also show the semiconducting behavior of this WS2 thin film which is more promising than thermally unstable organic materials for thin film transistor application. Our direct growth method on silicon oxide also holds interesting opportunities for macro-electronics applications. © 2013 IEEE.

A novel ultra-planar, long-stroke and low-voltage piezoelectric micromirror

Science.gov (United States)

Bakke, Thor; Vogl, Andreas; Żero, Oleg; Tyholdt, Frode; Johansen, Ib-Rune; Wang, Dag

2010-06-01

A novel piston-type micromirror with a stroke of up to 20 µm at 20 V formed out of a silicon-on-insulator wafer with integrated piezoelectric actuators was designed, fabricated and characterized. The peak-to-valley planarity of a 2 mm diameter mirror was better than 15 nm, and tip-to-tip tilt upon actuation less than 30 nm. A resonance frequency of 9.8 kHz was measured. Analytical and finite element models were developed and compared to measurements. The design is based on a silicon-on-insulator wafer where the circular mirror is formed out of the handle silicon, thus forming a thick, highly rigid and ultra-planar mirror surface. The mirror plate is connected to a supporting frame through a membrane formed out of the device silicon layer. A piezoelectric actuator made of lead-zirconate-titanate (PZT) thin film is structured on top of the membrane, providing mirror deflection by deformation of the membrane. Two actuator designs were tested: one with a single ring and the other with a double ring providing bidirectional movement of the mirror. The fabricated mirrors were characterized by white light interferometry to determine the static and temporal response as well as mirror planarity.

A novel ultra-planar, long-stroke and low-voltage piezoelectric micromirror

International Nuclear Information System (INIS)

Bakke, Thor; Vogl, Andreas; Żero, Oleg; Tyholdt, Frode; Johansen, Ib-Rune; Wang, Dag

2010-01-01

A novel piston-type micromirror with a stroke of up to 20 µm at 20 V formed out of a silicon-on-insulator wafer with integrated piezoelectric actuators was designed, fabricated and characterized. The peak-to-valley planarity of a 2 mm diameter mirror was better than 15 nm, and tip-to-tip tilt upon actuation less than 30 nm. A resonance frequency of 9.8 kHz was measured. Analytical and finite element models were developed and compared to measurements. The design is based on a silicon-on-insulator wafer where the circular mirror is formed out of the handle silicon, thus forming a thick, highly rigid and ultra-planar mirror surface. The mirror plate is connected to a supporting frame through a membrane formed out of the device silicon layer. A piezoelectric actuator made of lead–zirconate–titanate (PZT) thin film is structured on top of the membrane, providing mirror deflection by deformation of the membrane. Two actuator designs were tested: one with a single ring and the other with a double ring providing bidirectional movement of the mirror. The fabricated mirrors were characterized by white light interferometry to determine the static and temporal response as well as mirror planarity.

Carbon nanotube transistors with graphene oxide films as gate dielectrics

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

Germanium field-effect transistor made from a high-purity substrate

International Nuclear Information System (INIS)

Hansen, W.L.; Goulding, F.S.; Haller, E.E.

1978-11-01

Field effect transistors have been fabricated on high-purity germanium substrates using low-temperature technology. The aim of this work is to preserve the low density of trapping centers in high-quality starting material by low-temperature ( 0 C) processing. The use of germanium promises to eliminate some of the traps which cause generation-recombination noise in silicon field-effect transistors (FET's) at low temperatures. Typically, the transconductance (g/sub m/) in the germanium FET's is 10 mA/V and the gate leakage can be less than 10 -12 A. Present devices exhibit a large 1/f noise component and most of this noise must be eliminated if they are to be competitive with silicon FET's commonly used in high-resolution nuclear spectrometers

Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

International Nuclear Information System (INIS)

Kim, Minsoo; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi

2014-01-01

We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al 2 O 3 -based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I ON /I OFF ratio of 10 3 –10 4 were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation

A planar lens based on the electrowetting of two immiscible liquids

International Nuclear Information System (INIS)

Liu Chaoxuan; Park, Jihwan; Choi, Jin-Woo

2008-01-01

This paper reports the development and characterization of a planar liquid lens based on electrowetting. The working concept of electrowetting two immiscible liquids is demonstrated with measurement and characterization of contact angles with regard to externally applied electric voltages. Consequently, a planar liquid lens is designed and implemented based on this competitive electrowetting. A droplet of silicone oil confined in an aqueous solution (1% KCl) works as a liquid lens. Electrowetting then controls the shape of the confined silicone oil and the focal length of the liquid lens varies depending upon an applied dc voltage. A unique feature of this lens design is the double-ring planar electrodes beneath the hydrophobic substrate. While an outer ring electrode provides an initial boundary for the silicone oil droplet, an inner ring works as the actuation electrode for the lens. Further, the planar electrodes, instead of vertical or out-of-plane wall electrodes, facilitate the integration of liquid lenses into microfluidic systems. With the voltage applied in the range of 50–250 V, the confined silicone oil droplet changed its shape and the optical magnification of a 3 mm-diameter liquid lens was clearly demonstrated. Moreover, focal lengths of liquid lenses with diameters of 2 mm, 3 mm and 4 mm were characterized, respectively. The obtained results suggest that a larger lens diameter yields a longer focal length and a wider range of focal length change in response to voltage. The demonstrated liquid lens has a simple structure and is easy to fabricate

Experimental study of the hysteresis in hydrogenated amorphous silicon thin-film transistors for an active matrix organic light-emitting diode

International Nuclear Information System (INIS)

Lee, Jae-Hoon; Shin, Kwang-Sub; Park, Joong-Hyun; Han, Min-Koo

2006-01-01

An experimental scheme for validating the cause of the hysteresis phenomenon in hydrogenated amorphous-silicon-thin-film transistors (a-Si:H TFTs) is reported. A different gate starting voltage to the desired gate voltage has been considered to prove an effect of filling an acceptor-like or donor-like state in the interface. The integration time of the semiconductor parameter analyzer has also been controlled to investigate the effect between the de-trapping rate and hysteresis. The experimental results show that the previous data voltage in the (n-1)th frame affects the OLED current in the (n)th frame.

High Sensitivity pH Sensor Based on Porous Silicon (PSi Extended Gate Field-Effect Transistor

Directory of Open Access Journals (Sweden)

Naif H. Al-Hardan

2016-06-01

Full Text Available In this study, porous silicon (PSi was prepared and tested as an extended gate field-effect transistor (EGFET for pH sensing. The prepared PSi has pore sizes in the range of 500 to 750 nm with a depth of approximately 42 µm. The results of testing PSi for hydrogen ion sensing in different pH buffer solutions reveal that the PSi has a sensitivity value of 66 mV/pH that is considered a super Nernstian value. The sensor considers stability to be in the pH range of 2 to 12. The hysteresis values of the prepared PSi sensor were approximately 8.2 and 10.5 mV in the low and high pH loop, respectively. The result of this study reveals a promising application of PSi in the field for detecting hydrogen ions in different solutions.

Induced nano-scale self-formed metal-oxide interlayer in amorphous silicon tin oxide thin film transistors.

Science.gov (United States)

Liu, Xianzhe; Xu, Hua; Ning, Honglong; Lu, Kuankuan; Zhang, Hongke; Zhang, Xiaochen; Yao, Rihui; Fang, Zhiqiang; Lu, Xubing; Peng, Junbiao

2018-03-07

Amorphous Silicon-Tin-Oxide thin film transistors (a-STO TFTs) with Mo source/drain electrodes were fabricated. The introduction of a ~8 nm MoO x interlayer between Mo electrodes and a-STO improved the electron injection in a-STO TFT. Mo adjacent to the a-STO semiconductor mainly gets oxygen atoms from the oxygen-rich surface of a-STO film to form MoO x interlayer. The self-formed MoO x interlayer acting as an efficient interface modification layer could conduce to the stepwise internal transport barrier formation while blocking Mo atoms diffuse into a-STO layer, which would contribute to the formation of ohmic contact between Mo and a-STO film. It can effectively improve device performance, reduce cost and save energy for the realization of large-area display with high resolution in future.

Current-Induced Transistor Sensorics with Electrogenic Cells

Directory of Open Access Journals (Sweden)

Peter Fromherz

2016-04-01

Full Text Available The concepts of transistor recording of electroactive cells are considered, when the response is determined by a current-induced voltage in the electrolyte due to cellular activity. The relationship to traditional transistor recording, with an interface-induced response due to interactions with the open gate oxide, is addressed. For the geometry of a cell-substrate junction, the theory of a planar core-coat conductor is described with a one-compartment approximation. The fast electrical relaxation of the junction and the slow change of ion concentrations are pointed out. On that basis, various recording situations are considered and documented by experiments. For voltage-gated ion channels under voltage clamp, the effects of a changing extracellular ion concentration and the enhancement/depletion of ion conductances in the adherent membrane are addressed. Inhomogeneous ion conductances are crucial for transistor recording of neuronal action potentials. For a propagating action potential, the effects of an axon-substrate junction and the surrounding volume conductor are distinguished. Finally, a receptor-transistor-sensor is described, where the inhomogeneity of a ligand–activated ion conductance is achieved by diffusion of the agonist and inactivation of the conductance. Problems with regard to a development of reliable biosensors are mentioned.

Effects of silicon-nitride passivation on the electrical behavior of 0.1-μm pseudomorphic high-electron-mobility transistors

International Nuclear Information System (INIS)

Oh, Jung-Hun; Sul, Woo-Suk; Han, Hyo-Jong; Jang, Hae-Kang; Son, Myung-Sik; Rhee, Jin-Koo; Kim, Sam- Dong

2004-01-01

We examine the effects of surface state formation due to silicon-nitride passivation on the electrical characteristics of GaAs-based 0.1-μm pseudomorphic high-electron-mobility transistors (pHEMTs). In this study, DC and noise characteristic are investigated before and after the passivation of the pHEMTs. After the passivation, we observe significant degradation of noise performance in the frequency range of 55 - 62 GHz. We also observe clear increases in the drain-source saturation current at a gate voltage of 0 V and in the extrinsic transconductance at a drain voltage of 1 V from 325 and 264 to 365 mA/mm and 304 mS/mm, respectively, with no significant variation in pinchoff voltage. We propose that the observed variations in the DC and the noise characteristics are due to the positively charged surface state after deposition of the silicon nitride passivation film. Hydrodynamic device model simulations were performed based upon the proposed mechanisms for the change in electrical behavior, and the calculated results show good agreement with the experimental results.

Silicon nanowire field-effect transistors for the detection of proteins

Science.gov (United States)

Madler, Carsten

In this dissertation I present results on our efforts to increase the sensitivity and selectivity of silicon nanowire ion-sensitive field-effect transistors for the detection of biomarkers, as well as a novel method for wireless power transfer based on metamaterial rectennas for their potential use as implantable sensors. The sensing scheme is based on changes in the conductance of the semiconducting nanowires upon binding of charged entities to the surface, which induces a field-effect. Monitoring the differential conductance thus provides information of the selective binding of biological molecules of interest to previously covalently linked counterparts on the nanowire surface. In order to improve on the performance of the nanowire sensing, we devised and fabricated a nanowire Wheatstone bridge, which allows canceling out of signal drift due to thermal fluctuations and dynamics of fluid flow. We showed that balancing the bridge significantly improves the signal-to-noise ratio. Further, we demonstrated the sensing of novel melanoma biomarker TROY at clinically relevant concentrations and distinguished it from nonspecific binding by comparing the reaction kinetics. For increased sensitivity, an amplification method was employed using an enzyme which catalyzes a signal-generating reaction by changing the redox potential of a redox pair. In addition, we investigated the electric double layer, which forms around charges in an electrolytic solution. It causes electrostatic screening of the proteins of interest, which puts a fundamental limitation on the biomarker detection in solutions with high salt concentrations, such as blood. We solved the coupled Nernst-Planck and Poisson equations for the electrolyte under influence of an oscillating electric field and discovered oscillations of the counterion concentration at a characteristic frequency. In addition to exploring different methods for improved sensing capabilities, we studied an innovative method to supply power

Low-resistance gateless high electron mobility transistors using three-dimensional inverted pyramidal AlGaN/GaN surfaces

International Nuclear Information System (INIS)

So, Hongyun; Senesky, Debbie G.

2016-01-01

In this letter, three-dimensional gateless AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated with 54% reduction in electrical resistance and 73% increase in surface area compared with conventional gateless HEMTs on planar substrates. Inverted pyramidal AlGaN/GaN surfaces were microfabricated using potassium hydroxide etched silicon with exposed (111) surfaces and metal-organic chemical vapor deposition of coherent AlGaN/GaN thin films. In addition, electrical characterization of the devices showed that a combination of series and parallel connections of the highly conductive two-dimensional electron gas along the pyramidal geometry resulted in a significant reduction in electrical resistance at both room and high temperatures (up to 300 °C). This three-dimensional HEMT architecture can be leveraged to realize low-power and reliable power electronics, as well as harsh environment sensors with increased surface area

Low-resistance gateless high electron mobility transistors using three-dimensional inverted pyramidal AlGaN/GaN surfaces

Energy Technology Data Exchange (ETDEWEB)

So, Hongyun, E-mail: hyso@stanford.edu [Department of Aeronautics and Astronautics, Stanford University, Stanford, California 94305 (United States); Senesky, Debbie G. [Department of Aeronautics and Astronautics, Stanford University, Stanford, California 94305 (United States); Department of Electrical Engineering, Stanford University, Stanford, California 94305 (United States)

2016-01-04

In this letter, three-dimensional gateless AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated with 54% reduction in electrical resistance and 73% increase in surface area compared with conventional gateless HEMTs on planar substrates. Inverted pyramidal AlGaN/GaN surfaces were microfabricated using potassium hydroxide etched silicon with exposed (111) surfaces and metal-organic chemical vapor deposition of coherent AlGaN/GaN thin films. In addition, electrical characterization of the devices showed that a combination of series and parallel connections of the highly conductive two-dimensional electron gas along the pyramidal geometry resulted in a significant reduction in electrical resistance at both room and high temperatures (up to 300 °C). This three-dimensional HEMT architecture can be leveraged to realize low-power and reliable power electronics, as well as harsh environment sensors with increased surface area.

Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

KAUST Repository

Zhai, Yujia

2012-11-26

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

KAUST Repository

Zhai, Yujia; Palard, Marylene; Mathew, Leo; Hussain, Muhammad Mustafa; Willson, Grant Grant; Tutuc, Emanuel; Banerjee, Sanjay Kumar

2012-01-01

We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf

Memristive device based on a depletion-type SONOS field effect transistor

Science.gov (United States)

Himmel, N.; Ziegler, M.; Mähne, H.; Thiem, S.; Winterfeld, H.; Kohlstedt, H.

2017-06-01

State-of-the-art SONOS (silicon-oxide-nitride-oxide-polysilicon) field effect transistors were operated in a memristive switching mode. The circuit design is a variation of the MemFlash concept and the particular properties of depletion type SONOS-transistors were taken into account. The transistor was externally wired with a resistively shunted pn-diode. Experimental current-voltage curves show analog bipolar switching characteristics within a bias voltage range of ±10 V, exhibiting a pronounced asymmetric hysteresis loop. The experimental data are confirmed by SPICE simulations. The underlying memristive mechanism is purely electronic, which eliminates an initial forming step of the as-fabricated cells. This fact, together with reasonable design flexibility, in particular to adjust the maximum R ON/R OFF ratio, makes these cells attractive for neuromorphic applications. The relative large set and reset voltage around ±10 V might be decreased by using thinner gate-oxides. The all-electric operation principle, in combination with an established silicon manufacturing process of SONOS devices at the Semiconductor Foundry X-FAB, promise reliable operation, low parameter spread and high integration density.

Field emission current from a junction field-effect transistor

International Nuclear Information System (INIS)

Monshipouri, Mahta; Abdi, Yaser

2015-01-01

Fabrication of a titanium dioxide/carbon nanotube (TiO 2 /CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO 2 nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO 2 /CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO 2 /CNT hetero-structure is also investigated, and well modeled

Graphene Field Effect Transistor for Radiation Detection

Science.gov (United States)

Li, Mary J. (Inventor); Chen, Zhihong (Inventor)

2016-01-01

The present invention relates to a graphene field effect transistor-based radiation sensor for use in a variety of radiation detection applications, including manned spaceflight missions. The sensing mechanism of the radiation sensor is based on the high sensitivity of graphene in the local change of electric field that can result from the interaction of ionizing radiation with a gated undoped silicon absorber serving as the supporting substrate in the graphene field effect transistor. The radiation sensor has low power and high sensitivity, a flexible structure, and a wide temperature range, and can be used in a variety of applications, particularly in space missions for human exploration.

DARPA, SDI, and GaAs

International Nuclear Information System (INIS)

Karp, S.; Rooslid, S.

1986-01-01

When silicon replaced germanium in the early 1960's as the semiconductor of choice for solid state devices, it converted the entire industry in just a few years because of two important characteristics. First, silicon has a higher energy bandgap, which permits silicon-based devices to operate over a wider temperature range (a feature especially important to the military). Second, and more important, silicon has a native oxide that provided for improved stability and planar, rather than mesa, type devices. Planar technology soon spawned integrated circuits. The integrated circuit in turn brought on the electronics revolution, allowing the complexity of circuits to increase by a factor of two every year (Moore's Law) and bringing us from single transistors to megabit memory chips

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

KAUST Repository

Hussain, Muhammad Mustafa

2013-05-30

Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%). © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

KAUST Repository

Hussain, Muhammad Mustafa; Rojas, Jhonathan Prieto; Sevilla, Galo T.

2013-01-01

Today’s information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor – heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon – industry’s darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%). © (2013) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Fabrication of a vertical channel field effect transistor and a study of its electrical performances

International Nuclear Information System (INIS)

Bhuiyan, A.S.

1983-01-01

A vertical channel field effect transistor on silicon was fabricated by diffusion technique and its electrical characteristics were studied as a function of voltage and temperature. It was found that this transistor has relatively high breakdown voltage of 65 volts for drain source and of 7.5 volts for gate source terminals. (author)

Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs

Directory of Open Access Journals (Sweden)

Michael Loong Peng Tan

2013-01-01

Full Text Available Long channel carbon nanotube transistor (CNT can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL effects in silicon MOSFET while sustaining the same unit area at higher current density.

Nanowire size dependence on sensitivity of silicon nanowire field-effect transistor-based pH sensor

Science.gov (United States)

Lee, Ryoongbin; Kwon, Dae Woong; Kim, Sihyun; Kim, Sangwan; Mo, Hyun-Sun; Kim, Dae Hwan; Park, Byung-Gook

2017-12-01

In this study, we investigated the effects of nanowire size on the current sensitivity of silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs). The changes in on-current (I on) and resistance according to pH were measured in fabricated SiNW ISFETs of various lengths and widths. As a result, it was revealed that the sensitivity expressed as relative I on change improves as the width decreases. Through technology computer-aided design (TCAD) simulation analysis, the width dependence on the relative I on change can be explained by the observation that the target molecules located at the edge region along the channel width have a stronger effect on the sensitivity as the SiNW width is reduced. Additionally, the length dependence on the sensitivity can be understood in terms of the resistance ratio of the fixed parasitic resistance, including source/drain resistance, to the varying channel resistance as a function of channel length.

Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

Science.gov (United States)

Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

2015-10-06

We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

Science.gov (United States)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil

2017-11-13

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor\\'s width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Silicon etch process

International Nuclear Information System (INIS)

Day, D.J.; White, J.C.

1984-01-01

A silicon etch process wherein an area of silicon crystal surface is passivated by radiation damage and non-planar structure produced by subsequent anisotropic etching. The surface may be passivated by exposure to an energetic particle flux - for example an ion beam from an arsenic, boron, phosphorus, silicon or hydrogen source, or an electron beam. Radiation damage may be used for pattern definition and/or as an etch stop. Ethylenediamine pyrocatechol or aqueous potassium hydroxide anisotropic etchants may be used. The radiation damage may be removed after etching by thermal annealing. (author)

Tunnel field-effect transistors with germanium/strained-silicon hetero-junctions for low power applications

Energy Technology Data Exchange (ETDEWEB)

Kim, Minsoo, E-mail: minsoo@mosfet.t.u-tokyo.ac.jp; Kim, Younghyun; Yokoyama, Masafumi; Nakane, Ryosho; Kim, SangHyeon; Takenaka, Mitsuru; Takagi, Shinichi

2014-04-30

We have studied a simple structure n-channel tunnel field-effect transistor with a pure-Ge/strained-Si hetero-junction. The device operation was demonstrated for the devices fabricated by combining epitaxially-grown Ge on strained-silicon-on-insulator substrates. Atomic-layer-deposition-Al{sub 2}O{sub 3}-based gate stacks were formed with electron cyclotron resonance plasma post oxidation to ensure the high quality metal–oxide–semiconductor interface between the high-k insulator and Ge. While the gate leakage current and drain current saturation are well controlled, relatively higher minimum subthreshold swing of 125 mV/dec and lower I{sub ON}/I{sub OFF} ratio of 10{sup 3}–10{sup 4} were obtained. It is expected that these device characteristics can be improved by further process optimization. - Highlights: • Layer by layer growth of Ge • Uniform interface between Ge and the insulator • Gate leakage current and drain current saturation seem to be well controlled. • The output characteristics show good saturation.

DEVICE TECHNOLOGY. Nanomaterials in transistors: From high-performance to thin-film applications.

Science.gov (United States)

Franklin, Aaron D

2015-08-14

For more than 50 years, silicon transistors have been continuously shrunk to meet the projections of Moore's law but are now reaching fundamental limits on speed and power use. With these limits at hand, nanomaterials offer great promise for improving transistor performance and adding new applications through the coming decades. With different transistors needed in everything from high-performance servers to thin-film display backplanes, it is important to understand the targeted application needs when considering new material options. Here the distinction between high-performance and thin-film transistors is reviewed, along with the benefits and challenges to using nanomaterials in such transistors. In particular, progress on carbon nanotubes, as well as graphene and related materials (including transition metal dichalcogenides and X-enes), outlines the advances and further research needed to enable their use in transistors for high-performance computing, thin films, or completely new technologies such as flexible and transparent devices. Copyright © 2015, American Association for the Advancement of Science.

Controllable film densification and interface flatness for high-performance amorphous indium oxide based thin film transistors

Energy Technology Data Exchange (ETDEWEB)

Ou-Yang, Wei, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp; Mitoma, Nobuhiko; Kizu, Takio; Gao, Xu; Lin, Meng-Fang; Tsukagoshi, Kazuhito, E-mail: OUYANG.Wei@nims.go.jp, E-mail: TSUKAGOSHI.Kazuhito@nims.go.jp [International Center for Materials Nanoarchitectronics (WPI-MANA), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan); Nabatame, Toshihide [MANA Foundry and MANA Advanced Device Materials Group, National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044 (Japan)

2014-10-20

To avoid the problem of air sensitive and wet-etched Zn and/or Ga contained amorphous oxide transistors, we propose an alternative amorphous semiconductor of indium silicon tungsten oxide as the channel material for thin film transistors. In this study, we employ the material to reveal the relation between the active thin film and the transistor performance with aid of x-ray reflectivity study. By adjusting the pre-annealing temperature, we find that the film densification and interface flatness between the film and gate insulator are crucial for achieving controllable high-performance transistors. The material and findings in the study are believed helpful for realizing controllable high-performance stable transistors.

Nonplanar Nanoscale Fin Field Effect Transistors on Textile, Paper, Wood, Stone, and Vinyl via Soft Material-Enabled Double-Transfer Printing.

Science.gov (United States)

Rojas, Jhonathan P; Torres Sevilla, Galo A; Alfaraj, Nasir; Ghoneim, Mohamed T; Kutbee, Arwa T; Sridharan, Ashvitha; Hussain, Muhammad Mustafa

2015-05-26

The ability to incorporate rigid but high-performance nanoscale nonplanar complementary metal-oxide semiconductor (CMOS) electronics with curvilinear, irregular, or asymmetric shapes and surfaces is an arduous but timely challenge in enabling the production of wearable electronics with an in situ information-processing ability in the digital world. Therefore, we are demonstrating a soft-material enabled double-transfer-based process to integrate flexible, silicon-based, nanoscale, nonplanar, fin-shaped field effect transistors (FinFETs) and planar metal-oxide-semiconductor field effect transistors (MOSFETs) on various asymmetric surfaces to study their compatibility and enhanced applicability in various emerging fields. FinFET devices feature sub-20 nm dimensions and state-of-the-art, high-κ/metal gate stacks, showing no performance alteration after the transfer process. A further analysis of the transferred MOSFET devices, featuring 1 μm gate length, exhibits an ION value of nearly 70 μA/μm (VDS = 2 V, VGS = 2 V) and a low subthreshold swing of around 90 mV/dec, proving that a soft interfacial material can act both as a strong adhesion/interposing layer between devices and final substrate as well as a means to reduce strain, which ultimately helps maintain the device's performance with insignificant deterioration even at a high bending state.

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Science.gov (United States)

Sengupta, Sarmista; Pandit, Soumya

2015-06-01

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length Lg = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa; Fahad, Hossain M.; Smith, Casey E.; Rojas, Jhonathan Prieto

2015-01-01

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Cylindrical-shaped nanotube field effect transistor

KAUST Repository

Hussain, Muhammad Mustafa

2015-12-29

A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I.sub.on/I.sub.off) than conventional transistor devices. The cylindrical-shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Controlling charge current through a DNA based molecular transistor

Energy Technology Data Exchange (ETDEWEB)

Behnia, S., E-mail: s.behnia@sci.uut.ac.ir; Fathizadeh, S.; Ziaei, J.

2017-01-05

Molecular electronics is complementary to silicon-based electronics and may induce electronic functions which are difficult to obtain with conventional technology. We have considered a DNA based molecular transistor and study its transport properties. The appropriate DNA sequence as a central chain in molecular transistor and the functional interval for applied voltages is obtained. I–V characteristic diagram shows the rectifier behavior as well as the negative differential resistance phenomenon of DNA transistor. We have observed the nearly periodic behavior in the current flowing through DNA. It is reported that there is a critical gate voltage for each applied bias which above it, the electrical current is always positive. - Highlights: • Modeling a DNA based molecular transistor and studying its transport properties. • Choosing the appropriate DNA sequence using the quantum chaos tools. • Choosing the functional interval for voltages via the inverse participation ratio tool. • Detecting the rectifier and negative differential resistance behavior of DNA.

Field emission current from a junction field-effect transistor

Energy Technology Data Exchange (ETDEWEB)

Monshipouri, Mahta; Abdi, Yaser, E-mail: y.abdi@ut.ac.ir [University of Tehran, Nano-Physics Research Laboratory, Department of Physics (Iran, Islamic Republic of)

2015-04-15

Fabrication of a titanium dioxide/carbon nanotube (TiO{sub 2}/CNT)-based transistor is reported. The transistor can be considered as a combination of a field emission transistor and a junction field-effect transistor. Using direct current plasma-enhanced chemical vapor deposition (DC-PECVD) technique, CNTs were grown on a p-typed (100)-oriented silicon substrate. The CNTs were then covered by TiO{sub 2} nanoparticles 2–5 nm in size, using an atmospheric pressure CVD technique. In this device, TiO{sub 2}/CNT junction is responsible for controlling the emission current. High on/off-current ratio and proper gate control are the most important advantages of device. A model based on Fowler–Nordheim equation is utilized for calculation of the emission current and the results are compared with experimental data. The effect of TiO{sub 2}/CNT hetero-structure is also investigated, and well modeled.

Non-Planar Nanotube and Wavy Architecture Based Ultra-High Performance Field Effect Transistors

KAUST Repository

Hanna, Amir

2016-01-01

This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving

Hybrid heterojunction solar cell based on organic-inorganic silicon nanowire array architecture.

Science.gov (United States)

Shen, Xiaojuan; Sun, Baoquan; Liu, Dong; Lee, Shuit-Tong

2011-12-07

Silicon nanowire arrays (SiNWs) on a planar silicon wafer can be fabricated by a simple metal-assisted wet chemical etching method. They can offer an excellent light harvesting capability through light scattering and trapping. In this work, we demonstrated that the organic-inorganic solar cell based on hybrid composites of conjugated molecules and SiNWs on a planar substrate yielded an excellent power conversion efficiency (PCE) of 9.70%. The high efficiency was ascribed to two aspects: one was the improvement of the light absorption by SiNWs structure on the planar components; the other was the enhancement of charge extraction efficiency, resulting from the novel top contact by forming a thin organic layer shell around the individual silicon nanowire. On the contrary, the sole planar junction solar cell only exhibited a PCE of 6.01%, due to the lower light trapping capability and the less hole extraction efficiency. It indicated that both the SiNWs structure and the thin organic layer top contact were critical to achieve a high performance organic/silicon solar cell. © 2011 American Chemical Society

Transport properties and device-design of Z-shaped MoS2 nanoribbon planar junctions

Science.gov (United States)

Zhang, Hua; Zhou, Wenzhe; Liu, Qi; Yang, Zhixiong; Pan, Jiangling; Ouyang, Fangping; Xu, Hui

2017-09-01

Based on MoS2 nanoribbons, metal-semiconductor-metal planar junction devices were constructed. The electronic and transport properties of the devices were studied by using density function theory (DFT) and nonequilibrium Green's functions (NEGF). It is found that a band gap about 0.4 eV occurs in the planar junction. The electron and hole transmissions of the devices are mainly contributed by the Mo atomic orbitals. The electron transport channel is located at the edge of armchair MoS2 nanoribbon, while the hole transport channel is delocalized in the channel region. The I-V curve of the two-probe device shows typical transport behavior of Schottky barrier, and the threshold voltage is of about 0.2 V. The field effect transistors (FET) based on the planar junction turn out to be good bipolar transistors, the maximum current on/off ratio can reach up to 1 × 104, and the subthreshold swing is 243 mV/dec. It is found that the off-state current is dependent on the length and width of the channel, while the on-state current is almost unaffected. The switching performance of the FET is improved with increasing the length of the channel, and shows oscillation behavior with the change of the channel width.

Area and energy efficient high-performance ZnO wavy channel thin-film transistor

KAUST Repository

Hanna, Amir

2014-09-01

Increased output current while maintaining low power consumption in thin-film transistors (TFTs) is essential for future generation large-area high-resolution displays. Here, we show wavy channel (WC) architecture in TFT that allows the expansion of the transistor width in the direction perpendicular to the substrate through integrating continuous fin features on the underlying substrate. This architecture enables expanding the TFT width without consuming any additional chip area, thus enabling increased performance while maintaining the real estate integrity. The experimental WCTFTs show a linear increase in output current as a function of number of fins per device resulting in (3.5×) increase in output current when compared with planar counterparts that consume the same chip area. The new architecture also allows tuning the threshold voltage as a function of the number of fin features included in the device, as threshold voltage linearly decreased from 6.8 V for planar device to 2.6 V for WC devices with 32 fins. This makes the new architecture more power efficient as lower operation voltages could be used for WC devices compared with planar counterparts. It was also found that field effect mobility linearly increases with the number of fins included in the device, showing almost \\\\(1.8×) enhancements in the field effect mobility than that of the planar counterparts. This can be attributed to higher electric field in the channel due to the fin architecture and threshold voltage shift. © 2014 IEEE.

Transformational silicon electronics

KAUST Repository

Rojas, Jhonathan Prieto

2014-02-25

In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

Practical guide to organic field effect transistor circuit design

CERN Document Server

Sou, Antony

2016-01-01

The field of organic electronics spans a very wide range of disciplines from physics and chemistry to hardware and software engineering. This makes the field of organic circuit design a daunting prospect full of intimidating complexities, yet to be exploited to its true potential. Small focussed research groups also find it difficult to move beyond their usual boundaries and create systems-on-foil that are comparable with the established silicon world.This book has been written to address these issues, intended for two main audiences; firstly, physics or materials researchers who have thus far designed circuits using only basic drawing software; and secondly, experienced silicon CMOS VLSI design engineers who are already knowledgeable in the design of full custom transistor level circuits but are not familiar with organic devices or thin film transistor (TFT) devices.In guiding the reader through the disparate and broad subject matters, a concise text has been written covering the physics and chemistry of the...

Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

Institute of Scientific and Technical Information of China (English)

潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

2011-01-01

Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95％ active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

Heteroepitaxial growth of In{sub 0.30}Ga{sub 0.70}As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

Energy Technology Data Exchange (ETDEWEB)

Kohen, David, E-mail: david.kohen@asm.com; Nguyen, Xuan Sang; Made, Riko I; Lee, Kwang Hong; Lee, Kenneth Eng Kian [Low Energy Electronic Systems IRG (LEES), Singapore-MIT Alliance for Research and Technology, 1 CREATE Way, Singapore 138602 (Singapore); Yadav, Sachin; Kumar, Annie; Gong, Xiao; Yeo, Yee Chia [National University of Singapore, 21 Lower Kent Ridge Rd, Singapore 119077 (Singapore); Heidelberger, Christopher [Department of Materials Science and Engineering, Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, MA 02139 (United States); Yoon, Soon Fatt [Low Energy Electronic Systems IRG (LEES), Singapore-MIT Alliance for Research and Technology, 1 CREATE Way, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Fitzgerald, Eugene A. [Low Energy Electronic Systems IRG (LEES), Singapore-MIT Alliance for Research and Technology, 1 CREATE Way, Singapore 138602 (Singapore); Department of Materials Science and Engineering, Massachusetts Institute of Technology, 77 Massachusetts Avenue, Cambridge, MA 02139 (United States)

2016-08-15

We report on the growth of an In{sub 0.30}Ga{sub 0.70}As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 10{sup 7} cm{sup −2} with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with I{sub DS} of 70 μA/μm and g{sub m} of above 60 μS/μm, demonstrating the high quality of the grown materials.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

Science.gov (United States)

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Planar metasurface retroreflector

Science.gov (United States)

Arbabi, Amir; Arbabi, Ehsan; Horie, Yu; Kamali, Seyedeh Mahsa; Faraon, Andrei

2017-07-01

Metasurfaces are two-dimensional arrangements of subwavelength scatterers that control the propagation of optical waves. Here, we show that cascaded metasurfaces, each performing a predefined mathematical transformation, provide a new optical design framework that enables new functionalities not yet demonstrated with single metasurfaces. Specifically, we demonstrate that retroreflection can be achieved with two vertically stacked planar metasurfaces, the first performing a spatial Fourier transform and its inverse, and the second imparting a spatially varying momentum to the Fourier transform of the incident light. Using this concept, we fabricate and test a planar monolithic near-infrared retroreflector composed of two layers of silicon nanoposts, which reflects light along its incident direction with a normal incidence efficiency of 78% and a large half-power field of view of 60°. The metasurface retroreflector demonstrates the potential of cascaded metasurfaces for implementing novel high-performance components, and enables low-power and low-weight passive optical transmitters.

Monolithic acoustic graphene transistors based on lithium niobate thin film

Science.gov (United States)

Liang, J.; Liu, B.-H.; Zhang, H.-X.; Zhang, H.; Zhang, M.-L.; Zhang, D.-H.; Pang, W.

2018-05-01

This paper introduces an on-chip acoustic graphene transistor based on lithium niobate thin film. The graphene transistor is embedded in a microelectromechanical systems (MEMS) acoustic wave device, and surface acoustic waves generated by the resonator induce a macroscopic current in the graphene due to the acousto-electric (AE) effect. The acoustic resonator and the graphene share the lithium niobate film, and a gate voltage is applied through the back side of the silicon substrate. The AE current induced by the Rayleigh and Sezawa modes was investigated, and the transistor outputs a larger current in the Rayleigh mode because of a larger coupling to velocity ratio. The output current increases linearly with the input radiofrequency power and can be effectively modulated by the gate voltage. The acoustic graphene transistor realized a five-fold enhancement in the output current at an optimum gate voltage, outperforming its counterpart with a DC input. The acoustic graphene transistor demonstrates a paradigm for more-than-Moore technology. By combining the benefits of MEMS and graphene circuits, it opens an avenue for various system-on-chip applications.

Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

KAUST Repository

Hanna, Amir

2015-12-04

High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

Wavy channel Thin Film Transistor for area efficient, high performance and low power applications

KAUST Repository

Hanna, Amir

2014-06-01

We report a new Thin Film Transistor (TFT) architecture that allows expansion of the device width using wavy (continuous without separation) fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.4x increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, similar to 100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers a pragmatic opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications without any limitation any TFT materials.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Science.gov (United States)

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Chemical vapor deposition based tungsten disulfide (WS2) thin film transistor

KAUST Repository

Hussain, Aftab M.; Sevilla, Galo T.; Rader, Kelly; Hussain, Muhammad Mustafa

2013-01-01

electric field. This makes them an interesting option for channel material in field effect transistors (FETs). Therefore, we show a highly manufacturable chemical vapor deposition (CVD) based simple process to grow WS2 directly on silicon oxide in a furnace

Measurement of low-frequency base and collector current noise and coherence in SiGe heterojunction bipolar transistors using transimpedance amplifiers

NARCIS (Netherlands)

Bruce, S.P.O.; Vandamme, L.K.J.; Rydberg, A.

1999-01-01

Transimpedance amplifiers have been used for direct study of current noise in silicon germanium (SiGe) heterojunction bipolar transistors (HBT's) at different biasing conditions. This has facilitated a wider range of resistances in the measurement circuit around the transistor than is possible when

Planar silicon sensors for the CMS Tracker upgrade

CERN Document Server

Junkes, Alexandra

2013-01-01

The CMS tracker collaboration has initiated a large material investigation and irradiation campaign to identify the silicon material and design that fulfills all requirements for detectors for the high-luminosity phase of the Large Hadron Collider (HL-LHC).A variety of silicon p-in-n and n-in-p test-sensors made from Float Zone, Deep-Diffused FZ and Magnetic Czochralski materials were manufactured by one single industrial producer, thus guaranteeing similar conditions for the production and design of the test-structures. Properties of different silicon materials and design choices have been systematically studied and compared.The samples have been irradiated with 1 MeV neutrons and protons corresponding to maximal fluences as expected for the positions of detector layers in the future tracker. Irradiations with protons of different energies (23 MeV and 23 GeV) have been performed to evaluate the energy dependence of the defect generation in oxygen rich material. All materials have been characterized before an...

Introduction to thin film transistors physics and technology of TFTs

CERN Document Server

Brotherton, S D

2013-01-01

Introduction to Thin Film Transistors reviews the operation, application, and technology of the main classes of thin film transistor (TFT) of current interest for large area electronics. The TFT materials covered include hydrogenated amorphous silicon (a-Si:H), poly-crystalline silicon (poly-Si), transparent amorphous oxide semiconductors (AOS), and organic semiconductors. The large scale manufacturing of a-Si:H TFTs forms the basis of the active matrix flat panel display industry. Poly-Si TFTs facilitate the integration of electronic circuits into portable active matrix liquid crystal displays, and are increasingly used in active matrix organic light emitting diode (AMOLED) displays for smart phones. The recently developed AOS TFTs are seen as an alternative option to poly-Si and a-Si:H for AMOLED TV and large AMLCD TV applications, respectively. The organic TFTs are regarded as a cost effective route into flexible electronics. As well as treating the highly divergent preparation and properties of these mat...

Towards high frequency heterojunction transistors: Electrical characterization of N-doped amorphous silicon-graphene diodes

Science.gov (United States)

Strobel, C.; Chavarin, C. A.; Kitzmann, J.; Lupina, G.; Wenger, Ch.; Albert, M.; Bartha, J. W.

2017-06-01

N-type doped amorphous hydrogenated silicon (a-Si:H) is deposited on top of graphene (Gr) by means of very high frequency (VHF) and radio frequency plasma-enhanced chemical vapor deposition (PECVD). In order to preserve the structural integrity of the monolayer graphene, a plasma excitation frequency of 140 MHz was successfully applied during the a-Si:H VHF-deposition. Raman spectroscopy results indicate the absence of a defect peak in the graphene spectrum after the VHF-PECVD of (n)-a-Si:H. The diode junction between (n)-a-Si:H and graphene was characterized using temperature dependent current-voltage (IV) and capacitance-voltage measurements, respectively. We demonstrate that the current at the (n)-a-Si:H-graphene interface is dominated by thermionic emission and recombination in the space charge region. The Schottky barrier height (qΦB), derived by temperature dependent IV-characteristics, is about 0.49 eV. The junction properties strongly depend on the applied deposition method of (n)-a-Si:H with a clear advantage of the VHF(140 MHz)-technology. We have demonstrated that (n)-a-Si:H-graphene junctions are a promising technology approach for high frequency heterojunction transistors.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

KAUST Repository

Hanna, Amir

2013-12-23

We demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features - termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in \\'ON\\' current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar \\'OFF\\' current value, ~100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large-area high-resolution display applications. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Breakdown voltage analysis of Al0.25Ga0.75N/GaN high electron mobility transistors with partial silicon doping in the AlGaN layer

International Nuclear Information System (INIS)

Duan Bao-Xing; Yang Yin-Tang

2012-01-01

In this paper, two-dimensional electron gas (2DEG) regions in AlGaN/GaN high electron mobility transistors (HEMTs) are realized by doping partial silicon into the AlGaN layer for the first time. A new electric field peak is introduced along the interface between the AlGaN and GaN buffer by the electric field modulation effect due to partial silicon positive charge. The high electric field near the gate for the complete silicon doping structure is effectively decreased, which makes the surface electric field uniform. The high electric field peak near the drain results from the potential difference between the surface and the depletion regions. Simulated breakdown curves that are the same as the test results are obtained for the first time by introducing an acceptor-like trap into the N-type GaN buffer. The proposed structure with partial silicon doping is better than the structure with complete silicon doping and conventional structures with the electric field plate near the drain. The breakdown voltage is improved from 296 V for the conventional structure to 400 V for the proposed one resulting from the uniform surface electric field. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

Energy Technology Data Exchange (ETDEWEB)

Dib, E., E-mail: elias.dib@for.unipi.it [Dipartimento di Ingegneria dell' Informazione, Università di Pisa, 56122 Pisa (Italy); Carrillo-Nuñez, H. [Integrated Systems Laboratory ETH Zürich, Gloriastrasse 35, 8092 Zürich (Switzerland); Cavassilas, N.; Bescond, M. [IM2NP, UMR CNRS 6242, Bât. IRPHE, Technopôle de Château-Gombert, 13384 Marseille Cedex 13 (France)

2016-01-28

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations.

Comparison of junctionless and inversion-mode p-type metal-oxide-semiconductor field-effect transistors in presence of hole-phonon interactions

International Nuclear Information System (INIS)

Dib, E.; Carrillo-Nuñez, H.; Cavassilas, N.; Bescond, M.

2016-01-01

Junctionless transistors are being considered as one of the alternatives to conventional metal-oxide field-effect transistors. In this work, it is then presented a simulation study of silicon double-gated p-type junctionless transistors compared with its inversion-mode counterpart. The quantum transport problem is solved within the non-equilibrium Green's function formalism, whereas hole-phonon interactions are tackled by means of the self-consistent Born approximation. Our findings show that junctionless transistors should perform as good as a conventional transistor only for ultra-thin channels, with the disadvantage of requiring higher supply voltages in thicker channel configurations

A CMOS silicon spin qubit

Science.gov (United States)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Tin - an unlikely ally for silicon field effect transistors?

KAUST Repository

Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

2014-01-01

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows

Lifetime-Enhanced Transport in Silicon due to Spin and Valley Blockade

NARCIS (Netherlands)

Lansbergen, G.P.; Rahman, R.; Verduijn, J.; Tettamanzi, G.C.; Collaert, N.; Biesemans, S.; Klimeck, G.; Hollenberg, L.C.L.; Rogge, S.

2011-01-01

We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition

Electrical effects of transient neutron irradiation of silicon devices

International Nuclear Information System (INIS)

Hjalmarson, H.P.; Pease, R.L.; Van Ginhoven, R.M.; Schultz, P.A.; Modine, N.A.

2007-01-01

The key effects of combined transient neutron and ionizing radiation on silicon diodes and bipolar junctions transistors are described. The results show that interstitial defect reactions dominate the annealing effects in the first stage of annealing for certain devices. Furthermore, the results show that oxide trapped charge can influence the effects of bulk silicon displacement damage for particular devices

Silicon photonics fundamentals and devices

CERN Document Server

Deen, M Jamal

2012-01-01

The creation of affordable high speed optical communications using standard semiconductor manufacturing technology is a principal aim of silicon photonics research. This would involve replacing copper connections with optical fibres or waveguides, and electrons with photons. With applications such as telecommunications and information processing, light detection, spectroscopy, holography and robotics, silicon photonics has the potential to revolutionise electronic-only systems. Providing an overview of the physics, technology and device operation of photonic devices using exclusively silicon and related alloys, the book includes: * Basic Properties of Silicon * Quantum Wells, Wires, Dots and Superlattices * Absorption Processes in Semiconductors * Light Emitters in Silicon * Photodetectors , Photodiodes and Phototransistors * Raman Lasers including Raman Scattering * Guided Lightwaves * Planar Waveguide Devices * Fabrication Techniques and Material Systems Silicon Photonics: Fundamentals and Devices outlines ...

Technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE)

Science.gov (United States)

Wegrzecka, Iwona; Panas, Andrzej; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kozłowski, Roman; Sarnecki, Jerzy; Słysz, Wojciech; Szmigiel, Dariusz; Wegrzecki, Maciej; Zaborowski, Michał

2013-07-01

The paper discusses the technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE). The developed technology enables the fabrication of both planar and epiplanar p+-ν-n+ detector structures with an active area of up to 50 cm2. The starting material for epiplanar structures are silicon wafers with a high-resistivity n-type epitaxial layer ( ν layer - ρ < 3 kΩcm) deposited on a highly doped n+-type substrate (ρ< 0,02Ωcm) developed and fabricated at the Institute of Electronic Materials Technology. Active layer thickness of the epiplanar detectors (νlayer) may range from 10 μm to 150 μm. Imported silicon with min. 5 kΩcm resistivity is used to fabricate planar detectors. Active layer thickness of the planar detectors (ν) layer) may range from 200 μm to 1 mm. This technology enables the fabrication of both discrete and multi-junction detectors (monolithic detector arrays), such as single-sided strip detectors (epiplanar and planar) and double-sided strip detectors (planar). Examples of process diagrams for fabrication of the epiplanar and planar detectors are presented in the paper, and selected technological processes are discussed.

Fabrication of planar optical waveguides by 6.0 MeV silicon ion implantation in Nd-doped phosphate glasses

Science.gov (United States)

Shen, Xiao-Liang; Dai, Han-Qing; Zhang, Liao-Lin; Wang, Yue; Zhu, Qi-Feng; Guo, Hai-Tao; Li, Wei-Nan; Liu, Chun-Xiao

2018-04-01

We report the fabrication of a planar optical waveguide by silicon ion implantation into Nd-doped phosphate glass at an energy of 6.0 MeV and a dose of 5.0 × 1014 ions/cm2. The change in the surface morphology of the glass after the implantation can be clearly observed by scanning electron microscopy. The measurement of the dark mode spectrum of the waveguide is conducted using a prism coupler at 632.8 nm. The refractive index distribution of the waveguide is reconstructed by the reflectivity calculation method. The near-field optical intensity profile of the waveguide is measured using an end-face coupling system. The waveguide with good optical properties on the glass matrix may be valuable for the application of the Nd-doped phosphate glass in integrated optical devices.

Passivated graphene transistors fabricated on a millimeter-sized single-crystal graphene film prepared with chemical vapor deposition

International Nuclear Information System (INIS)

Lin, Meng-Yu; Lee, Si-Chen; Lin, Shih-Yen; Wang, Cheng-Hung; Chang, Shu-Wei

2015-01-01

In this work, we first investigate the effects of partial pressures and flow rates of precursors on the single-crystal graphene growth using chemical vapor depositions on copper foils. These factors are shown to be critical to the growth rate, seeding density and size of graphene single crystals. The prepared graphene films in millimeter sizes are then bubbling transferred to silicon-dioxide/silicon substrates for high-mobility graphene transistor fabrications. After high-temperature annealing and hexamethyldisilazane passivation, the water attachment is removed from the graphene channel. The elimination of uncontrolled doping and enhancement of carrier mobility accompanied by these procedures indicate that they are promising for fabrications of graphene transistors. (paper)

Device Innovation and Material Challenges at the Limits of CMOS Technology

Science.gov (United States)

Solomon, P. M.

2000-08-01

Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

Sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

Growth and characterization of textured well-faceted ZnO on planar Si(100, planar Si(111, and textured Si(100 substrates for solar cell applications

Directory of Open Access Journals (Sweden)

Chin-Yi Tsai

2017-09-01

Full Text Available In this work, textured, well-faceted ZnO materials grown on planar Si(100, planar Si(111, and textured Si(100 substrates by low-pressure chemical vapor deposition (LPCVD were analyzed by X-ray diffraction (XRD, scanning electron microscopy (SEM, atomic force microscopy (AFM, and cathode luminescence (CL measurements. The results show that ZnO grown on planar Si(100, planar Si(111, and textured Si(100 substrates favor the growth of ZnO(110 ridge-like, ZnO(002 pyramid-like, and ZnO(101 pyramidal-tip structures, respectively. This could be attributed to the constraints of the lattice mismatch between the ZnO and Si unit cells. The average grain size of ZnO on the planar Si(100 substrate is slightly larger than that on the planar Si(111 substrate, while both of them are much larger than that on the textured Si(100 substrate. The average grain sizes (about 10–50 nm of the ZnO grown on the different silicon substrates decreases with the increase of their strains. These results are shown to strongly correlate with the results from the SEM, AFM, and CL as well. The reflectance spectra of these three samples show that the antireflection function provided by theses samples mostly results from the nanometer-scaled texture of the ZnO films, while the micrometer-scaled texture of the Si substrate has a limited contribution. The results of this work provide important information for optimized growth of textured and well-faceted ZnO grown on wafer-based silicon solar cells and can be utilized for efficiency enhancement and optimization of device materials and structures, such as heterojunction with intrinsic thin layer (HIT solar cells.

High-performance silicon nanotube tunneling FET for ultralow-power logic applications

KAUST Repository

Fahad, Hossain M.; Hussain, Muhammad Mustafa

2013-01-01

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

Simulation for silicon-compatible InGaAs-based junctionless field-effect transistor using InP buffer layer

Science.gov (United States)

Seo, Jae Hwa; Cho, Seongjae; Kang, In Man

2013-10-01

In this paper, we present the optimized performances of indium gallium arsenide (InGaAs)-based compound junctionless field-effect transistors (JLFETs) using an indium phosphide (InP) buffer layer. The proposed InGaAs-InP material combination with little lattice mismatch provides a significant improvement in current drivability securing various potential applications. Device optimization is performed in terms of primary dc parameters and characterization is investigated by two-dimensional (2D) technology computer-aided design simulations. The optimization variables were the channel doping concentration (Nch), the buffer doping concentration (Nbf), and the channel thickness (Tch). For the optimally designed InGaAs JLFET, on-state current (Ion) of 325 µA µm-1, subthreshold swing (S) of 80 mV dec-1, and current ratio (Ion/Ioff) of 109 were obtained. In the end, the results are compared with the data of silicon (Si)-based JL MOSFETs to confirm the improvements.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model.

Science.gov (United States)

Penumatcha, Ashish V; Salazar, Ramon B; Appenzeller, Joerg

2015-11-13

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

Fabrication of detectors and transistors on high-resistivity silicon

International Nuclear Information System (INIS)

Holland, S.

1988-06-01

A new process for the fabrication of silicon p-i-n diode radiation detectors is described. The utilization of backside gettering in the fabrication process results in the actual physical removal of detrimental impurities from critical device regions. This reduces the sensitivity of detector properties to processing variables while yielding low diode reverse-leakage currents. In addition, gettering permits the use of processing temperatures compatible with integrated-circuit fabrication. P-channel MOSFETs and silicon p-i-n diodes have been fabricated simultaneously on 10 kΩ/centerreverse arrowdot/cm silicon using conventional integrated-circuit processing techniques. 25 refs., 5 figs

Solution-processed single-walled carbon nanotube field effect transistors and bootstrapped inverters for disintegratable, transient electronics

Energy Technology Data Exchange (ETDEWEB)

Jin, Sung Hun, E-mail: harin74@gmail.com, E-mail: jhl@snu.ac.kr, E-mail: jrogers@illinois.edu; Shin, Jongmin; Cho, In-Tak; Lee, Jong-Ho, E-mail: harin74@gmail.com, E-mail: jhl@snu.ac.kr, E-mail: jrogers@illinois.edu [Department of Electrical and Computer Engineering and Inter-University Semiconductor Research Center, Seoul National University, Seoul 151-742 (Korea, Republic of); Han, Sang Youn [Department of Materials Science and Engineering, Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 (United States); Display R and D Center, Samsung Display Co., Yongin-city, Gyeongki-do 446–711 (Korea, Republic of); Lee, Dong Joon; Lee, Chi Hwan; Rogers, John A., E-mail: harin74@gmail.com, E-mail: jhl@snu.ac.kr, E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois 61801 (United States)

2014-07-07

This paper presents materials, device designs, and physical/electrical characteristics of a form of nanotube electronics that is physically transient, in the sense that all constituent elements dissolve and/or disperse upon immersion into water. Studies of contact effects illustrate the ability to use water soluble metals such as magnesium for source/drain contacts in nanotube based field effect transistors. High mobilities and on/off ratios in transistors that use molybdenum, silicon nitride, and silicon oxide enable full swing characteristics for inverters at low voltages (∼5 V) and with high gains (∼30). Dissolution/disintegration tests of such systems on water soluble sheets of polyvinyl alcohol demonstrate physical transience within 30 min.

Solution-processed single-walled carbon nanotube field effect transistors and bootstrapped inverters for disintegratable, transient electronics

International Nuclear Information System (INIS)

Jin, Sung Hun; Shin, Jongmin; Cho, In-Tak; Lee, Jong-Ho; Han, Sang Youn; Lee, Dong Joon; Lee, Chi Hwan; Rogers, John A.

2014-01-01

This paper presents materials, device designs, and physical/electrical characteristics of a form of nanotube electronics that is physically transient, in the sense that all constituent elements dissolve and/or disperse upon immersion into water. Studies of contact effects illustrate the ability to use water soluble metals such as magnesium for source/drain contacts in nanotube based field effect transistors. High mobilities and on/off ratios in transistors that use molybdenum, silicon nitride, and silicon oxide enable full swing characteristics for inverters at low voltages (∼5 V) and with high gains (∼30). Dissolution/disintegration tests of such systems on water soluble sheets of polyvinyl alcohol demonstrate physical transience within 30 min.

High-Performance Flexible Thin-Film Transistors Based on Single-Crystal-like Silicon Epitaxially Grown on Metal Tape by Roll-to-Roll Continuous Deposition Process.

Science.gov (United States)

Gao, Ying; Asadirad, Mojtaba; Yao, Yao; Dutta, Pavel; Galstyan, Eduard; Shervin, Shahab; Lee, Keon-Hwa; Pouladi, Sara; Sun, Sicong; Li, Yongkuan; Rathi, Monika; Ryou, Jae-Hyun; Selvamanickam, Venkat

2016-11-02

Single-crystal-like silicon (Si) thin films on bendable and scalable substrates via direct deposition are a promising material platform for high-performance and cost-effective devices of flexible electronics. However, due to the thick and unintentionally highly doped semiconductor layer, the operation of transistors has been hampered. We report the first demonstration of high-performance flexible thin-film transistors (TFTs) using single-crystal-like Si thin films with a field-effect mobility of ∼200 cm 2 /V·s and saturation current, I/l W > 50 μA/μm, which are orders-of-magnitude higher than the device characteristics of conventional flexible TFTs. The Si thin films with a (001) plane grown on a metal tape by a "seed and epitaxy" technique show nearly single-crystalline properties characterized by X-ray diffraction, Raman spectroscopy, reflection high-energy electron diffraction, and transmission electron microscopy. The realization of flexible and high-performance Si TFTs can establish a new pathway for extended applications of flexible electronics such as amplification and digital circuits, more than currently dominant display switches.

Additive advantage in characteristics of MIMCAPs on flexible silicon (100) fabric with release-first process

KAUST Repository

Ghoneim, Mohamed T.

2013-11-20

We report the inherent increase in capacitance per unit planar area of state-of-the art high-κ integrated metal/insulator/metal capacitors (MIMCAPs) fabricated on flexible silicon fabric with release-first process. We methodically study and show that our approach to transform bulk silicon (100) into a flexible fabric adds an inherent advantage of enabling higher integration density dynamic random access memory (DRAM) on the same chip area. Our approach is to release an ultra-thin silicon (100) fabric (25 μm thick) from the bulk silicon wafer, then build MIMCAPs using sputtered aluminium electrodes and successive atomic layer depositions (ALD) without break-ing the vacuum of a high-κ aluminium oxide sandwiched between two tantalum nitride layers. This result shows that we can obtain flexible electronics on silicon without sacrificing the high density integration aspects and also utilize the non-planar geometry associated with fabrication process to obtain a higher integration density compared to bulk silicon integration due to an increased normalized capacitance per unit planar area. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High mobility solution-processed hybrid light emitting transistors

International Nuclear Information System (INIS)

Walker, Bright; Kim, Jin Young; Ullah, Mujeeb; Burn, Paul L.; Namdas, Ebinazar B.; Chae, Gil Jo; Cho, Shinuk; Seo, Jung Hwa

2014-01-01

We report the design, fabrication, and characterization of high-performance, solution-processed hybrid (inorganic-organic) light emitting transistors (HLETs). The devices employ a high-mobility, solution-processed cadmium sulfide layer as the switching and transport layer, with a conjugated polymer Super Yellow as an emissive material in non-planar source/drain transistor geometry. We demonstrate HLETs with electron mobilities of up to 19.5 cm 2 /V s, current on/off ratios of >10 7 , and external quantum efficiency of 10 −2 % at 2100 cd/m 2 . These combined optical and electrical performance exceed those reported to date for HLETs. Furthermore, we provide full analysis of charge injection, charge transport, and recombination mechanism of the HLETs. The high brightness coupled with a high on/off ratio and low-cost solution processing makes this type of hybrid device attractive from a manufacturing perspective

Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

International Nuclear Information System (INIS)

Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

2002-01-01

Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

Quantum engineering of transistors based on 2D materials heterostructures

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Quantum engineering of transistors based on 2D materials heterostructures.

Science.gov (United States)

Iannaccone, Giuseppe; Bonaccorso, Francesco; Colombo, Luigi; Fiori, Gianluca

2018-03-01

Quantum engineering entails atom-by-atom design and fabrication of electronic devices. This innovative technology that unifies materials science and device engineering has been fostered by the recent progress in the fabrication of vertical and lateral heterostructures of two-dimensional materials and by the assessment of the technology potential via computational nanotechnology. But how close are we to the possibility of the practical realization of next-generation atomically thin transistors? In this Perspective, we analyse the outlook and the challenges of quantum-engineered transistors using heterostructures of two-dimensional materials against the benchmark of silicon technology and its foreseeable evolution in terms of potential performance and manufacturability. Transistors based on lateral heterostructures emerge as the most promising option from a performance point of view, even if heterostructure formation and control are in the initial technology development stage.

Electrical parameters of silicon on sapphire; influence on aluminium gate MOS devices performances

International Nuclear Information System (INIS)

Suat, J.P.; Borel, J.

1976-01-01

The question is the quality level of the substrate obtained with MOS technologies on silicon on an insulating substrate. Experimental results are presented on the main electrical parameters of MOS transistors made on silicon on sapphire, e.g. mean values and spreads of: threhold voltage and surface mobilities of transistors, breakdown voltages, and leakage currents of diodes. These devices have been made in three different technologies: enhancement P. channel technology, depletion-enhancement P. channel technology, and complementary MOS technology. These technologies are all aluminium gate processes with standard design rules and 5μm channel length. Measurements show that presently available silicon on sapphire can be considered as a very suitable substrate for many MOS digital applications (but not for dynamic circuits) [fr

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

Science.gov (United States)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Loss-Less planar waveguide 1:4 power splitter at 1550 nm

DEFF Research Database (Denmark)

Sckerl, Mads W.; Guldberg-Kjær, Søren Andreas; Laurent-Lund, Christian

1999-01-01

By a unique desposition/etching technique an erbuim-doped planar silica waveguide with intergrated splitter on a silicon substrate was produced and is demonstrated to show net gain at 1550 nm and good saturation and noise characteristics....

Controlling morphology and molecular order of solution-processed organic semiconductors for transistors

NARCIS (Netherlands)

Li, X.

2012-01-01

As a potential low-cost alternative to traditional amorphous-silicon based devices, organic field-effect transistors (OFETs) are expected to be incorporated into all-plastic integrated circuits and flexible display backplanes. More recently, breakthroughs have been made in the performance of OFETs

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays

KAUST Repository

Hanna, Amir Nabil; Kutbee, Arwa Talal; Subedi, Ram Chandra; Ooi, Boon S.; Hussain, Muhammad Mustafa

2017-01-01

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

A Comparison of Photo-Induced Hysteresis Between Hydrogenated Amorphous Silicon and Amorphous IGZO Thin-Film Transistors.

Science.gov (United States)

Ha, Tae-Jun; Cho, Won-Ju; Chung, Hong-Bay; Koo, Sang-Mo

2015-09-01

We investigate photo-induced instability in thin-film transistors (TFTs) consisting of amorphous indium-gallium-zinc-oxide (a-IGZO) as active semiconducting layers by comparing with hydrogenated amorphous silicon (a-Si:H). An a-IGZO TFT exhibits a large hysteresis window in the illuminated measuring condition but no hysteresis window in the dark condition. On the contrary, a large hysteresis window measured in the dark condition in a-Si:H was not observed in the illuminated condition. Even though such materials possess the structure of amorphous phase, optical responses or photo instability in TFTs looks different from each other. Photo-induced hysteresis results from initially trapped charges at the interface between semiconductor and dielectric films or in the gate dielectric which possess absorption energy to interact with deep trap-states and affect the movement of Fermi energy level. In order to support our claim, we also perform CV characteristics in photo-induced hysteresis and demonstrate thermal-activated hysteresis. We believe that this work can provide important information to understand different material systems for optical engineering which includes charge transport and band transition.

A simulation study of antimatter-helium ion planar channeling in silicon

International Nuclear Information System (INIS)

Wijesundera, Dharshana; Jayarathna, Sandun; Bellwied, Rene; Chu, Wei-Kan

2012-01-01

With the physical significance arising with the reports on experimental observation of antimatter-He nuclei, we have investigated a case of 2 MeV antimatter-He ion planar channeling in Si (1 0 0) in comparison with He channeling, by simulation. For a negatively charged antimatter-He nucleus, the planar potential well is centered at the atomic plane itself as opposed to the center-channel minimum for He ions; the antimatter-He ion distribution therefore tends to concentrate toward the atomic lattice planes. The antimatter-He ion flux distribution and the resulting close encounter probability are crucial in determining the probability of close encounter events including annihilation at channeling incidence. We have therefore analyzed the variation of antimatter-He ion flux distribution within the channels with respect to the angle of incidence and have thereby derived the orientation dependence of probability of close encounter events, or an antimatter-He channeling angular scan. The angular scan is inverted with a maximum yield at the perfect beam-planar alignment. The half-angle is narrower compared to He channeling, as a consequence of the narrower planar channeling potential centered at the lattice planes. The high de-channeling rate associated with the higher antimatter-He ion concentration in the proximity of lattice planes causes the maximum yield to be less prominent and to decrease rapidly with depth. The shoulder region shows strong depth dependent reduction that can be associated to near surface depth dependent ion flux variation.

Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

Science.gov (United States)

Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

2017-01-01

This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

High-performance silicon nanotube tunneling FET for ultralow-power logic applications

KAUST Repository

Fahad, Hossain M.

2013-03-01

To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET\\'s effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

OpenAIRE

Roeckerath, M.; Lopes, J. M. J.; Durgun Özben, E.; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D.G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of < 1 nA/cm(2). Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated ...

Si/Ge hetero-structure nanotube tunnel field effect transistor

KAUST Repository

Hanna, A. N.

2015-01-07

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.

Si/Ge hetero-structure nanotube tunnel field effect transistor

KAUST Repository

Hanna, A. N.; Hussain, Muhammad Mustafa

2015-01-01

We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

Science.gov (United States)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

International Nuclear Information System (INIS)

Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

2014-01-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

Monolithic junction field-effect transistor charge preamplifier for calorimetry at high luminosity hadron colliders

International Nuclear Information System (INIS)

Radeka, V.; Rescia, S.; Rehn, L.A.; Manfredi, P.F.; Speziali, V.

1991-11-01

The outstanding noise and radiation hardness characteristics of epitaxial-channel junction field-effect transistors (JFET) suggest that a monolithic preamplifier based upon them may be able to meet the strict specifications for calorimetry at high luminosity colliders. Results obtained so far with a buried layer planar technology, among them an entire monolithic charge-sensitive preamplifier, are described

Temperature Dependence of Field-Effect Mobility in Organic Thin-Film Transistors: Similarity to Inorganic Transistors.

Science.gov (United States)

Okada, Jun; Nagase, Takashi; Kobayashi, Takashi; Naito, Hiroyoshi

2016-04-01

Carrier transport in solution-processed organic thin-film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8-BTBT) has been investigated in a wide temperature range from 296 to 10 K. The field-effect mobility shows thermally activated behavior whose activation energy becomes smaller with decreasing temperature. The temperature dependence of field-effect mobility found in C8-BTBT is similar to that of others materials: organic semiconducting polymers, amorphous oxide semiconductors and hydrogenated amorphous silicon. These results indicate that hopping transport between isoenergetic localized states becomes dominated in a low temperature regime in these materials.

Silicon-Germanium Front-End Electronics for Space-Based Radar Applications

Data.gov (United States)

National Aeronautics and Space Administration — Over the past two decades, Silicon-Germanium (SiGe) heterojunction bipolar transistor (HBT) technology has emerged as a strong platform for high-frequency...

Nuclear radiation detectors using high resistivity neutron transmutation doped silicon

International Nuclear Information System (INIS)

Gessner, T.; Irmer, K.

1983-01-01

A method for the production of semiconductor detectors based on high resistivity n-type silicon is described. The n-type silicon is produced by neutron irradiation of p-type silicon. The detectors are produced by planar technique. They are suitable for the spectrometry of alpha particles and for the pulse count measurement of beta particles at room temperature. (author)

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

Science.gov (United States)

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

A new detector concept for silicon photomultipliers

Energy Technology Data Exchange (ETDEWEB)

Sadigov, A., E-mail: saazik@yandex.ru [National Nuclear Research Center, Baku (Azerbaijan); Ahmadov, F.; Ahmadov, G. [National Nuclear Research Center, Baku (Azerbaijan); Ariffin, A.; Khorev, S. [Zecotek Photonics Inc., Vancouver (Canada); Sadygov, Z. [National Nuclear Research Center, Baku (Azerbaijan); Joint Institute for Nuclear Research, Dubna (Russian Federation); Suleymanov, S. [National Nuclear Research Center, Baku (Azerbaijan); Zerrouk, F. [Zecotek Photonics Inc., Vancouver (Canada); Madatov, R. [Institute of Radiation Problems, Baku (Azerbaijan)

2016-07-11

A new design and principle of operation of silicon photomultipliers are presented. The new design comprises a semiconductor substrate and an array of independent micro-phototransistors formed on the substrate. Each micro-phototransistor comprises a photosensitive base operating in Geiger mode and an individual micro-emitter covering a small part of the base layer, thereby creating, together with this latter, a micro-transistor. Both micro-emitters and photosensitive base layers are connected with two respective independent metal grids via their individual micro-resistors. The total value of signal gain in the proposed silicon photomultiplier is a result of both the avalanche gain in the base layer and the corresponding gain in the micro-transistor. The main goals of the new design are: significantly lower both optical crosstalk and after-pulse effects at high signal amplification, improve speed of single photoelectron pulse formation, and significantly reduce the device capacitance.

The bipolar silicon microstrip detector: A proposal for a novel precision tracking device

International Nuclear Information System (INIS)

Horisberger, R.

1990-01-01

It is proposed to combine the technology of fully depleted microstrip detectors fabricated on n doped high resistivity silicon with the concept of the bipolar transistor. This is done by adding a n ++ doped region inside the normal p + implanted region of the reverse biased p + n diode. The resulting structure has amplifying properties and is referred to as bipaolar pixel transistor. The simplest readout scheme of a bipolar pixel array by an aluminium strip bus leads to the bipolar microstrip detector. The bipolar pixel structure is expected to give a better signal-to-noise performance for the detection of minimum ionizing charged particle tracks than the normal silicon diode strip detector and therefore should allow in future the fabrication of thinner silicon detectors for precision tracking. (orig.)

Development of a diffuse element matrix in 'planar' technology. A particular application: logical gate with coupled emitter; Etude et realisation d'une matrice d'elements diffuses selon la technologie 'planar'. Application particuliere: porte logique a emetteurs couples

Energy Technology Data Exchange (ETDEWEB)

Rousseau, P [Commissariat a l' Energie Atomique, 38 - Grenoble (France). Centre d' Etudes Nucleaires

1967-06-01

In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [French] Dans uns premiere partie, apres un bref rappel de la technologie 'planar' nous etudions les divers elements parasites associes a tout composant d'un circuit integre. Un developpement sommaire des expressions mathematiques de ces elements est propose. Dans une seconde partie nous presentons la matrice de 22 transistors et 12 resistances que nous avons realisee. Cette matrice repond aux principaux besoins de l'electronique nucleaire. Nous proposons ensuite quelques exemples de circuits realises a partir de cette matrice dont notamment une porte logique a emetteurs couples de performances tres interessantes. (auteur)

Solid-state diffusion as an efficient doping method for silicon nanowires and nanowire field effect transistors

International Nuclear Information System (INIS)

Moselund, K E; Ghoneim, H; Schmid, H; Bjoerk, M T; Loertscher, E; Karg, S; Signorello, G; Webb, D; Tschudy, M; Beyeler, R; Riel, H

2010-01-01

In this work we investigate doping by solid-state diffusion from a doped oxide layer, obtained by plasma-enhanced chemical vapor deposition (PECVD), as a means for selectively doping silicon nanowires (NWs). We demonstrate both n-type (phosphorous) and p-type (boron) doping up to concentrations of 10 20 cm -3 , and find that this doping mechanism is more efficient for NWs as opposed to planar substrates. We observe no diameter dependence in the range of 25 to 80 nm, which signifies that the NWs are uniformly doped. The drive-in temperature (800-950 deg. C) can be used to adjust the actual doping concentration in the range 2 x 10 18 to 10 20 cm -3 . Furthermore, we have fabricated NMOS and PMOS devices to show the versatility of this approach and the possibility of achieving segmented doping of NWs. The devices show high I on /I off ratios of around 10 7 and, especially for the PMOS, good saturation behavior and low hysteresis.

Multiplication in Silicon p-n Junctions

DEFF Research Database (Denmark)

Moll, John L.

1965-01-01

Multiplication values were measured in the collector junctions of silicon p-n-p and n-p-n transistors before and after bombardment by 1016 neutrons/cm2. Within experimental error there was no change either in junction fields, as deduced from capacitance measurements, or in multiplication values i...

Modeling of strain effects on the device behaviors of ferroelectric memory field-effect transistors

International Nuclear Information System (INIS)

Yang, Feng; Hu, Guangda; Wu, Weibing; Yang, Changhong; Wu, Haitao; Tang, Minghua

2013-01-01

The influence of strains on the channel current–gate voltage behaviors and memory windows of ferroelectric memory field-effect transistors (FeMFETs) were studied using an improved model based on the Landau–Devonshire theory. ‘Channel potential–gate voltage’ ferroelectric polarization and silicon surface potential diagrams were constructed for strained single-domain BaTiO 3 FeMFETs. The compressive strains can increase (or decrease) the amplitude of transistor currents and enlarge memory windows. However, tensile strains only decrease the maximum value of transistor currents and compress memory windows. Mismatch strains were found to have a significant influence on the electrical behaviors of the devices, therefore, they must be considered in FeMFET device designing. (fast track communication)

Noise and degradation of amorphous silicon devices

NARCIS (Netherlands)

Bakker, J.P.R.

2003-01-01

Electrical noise measurements are reported on two devices of the disordered semiconductor hydrogenated amorphous silicon (a-Si:H). The material is applied in sandwich structures and in thin-film transistors (TFTs). In a sandwich configuration of an intrinsic layer and two thin doped layers, the

Charge based DC compact modeling of bulk FinFET transistor

Science.gov (United States)

Cerdeira, A.; Garduño, I.; Tinoco, J.; Ritzenthaler, R.; Franco, J.; Togo, M.; Chiarella, T.; Claeys, C.

2013-09-01

Multiple-gate MOSFETs became an industrial reality in the last years. Due to a pragmatic trade-off between CMOS process baselines compatibility, improved performance compared to planar bulk architecture, and cost, bulk FinFETs emerged as the technological solution to provide downscaling for the 14/22 nm technological nodes. In this work, a charge based DC compact model based on the SDDG Model is demonstrated for this new generation of FinFET transistors and describes continuously the transistor characteristics in all operating regions. Validating the model against two bulk FinFET baselines (NMOS, PMOS, various gate lengths and EOT), an excellent agreement is found for transfer and output characteristics (linear and saturation regimes), transconductance/output conductance, and gm/IDS characteristics. Temperature dependence is also taken into account and validated (T range from 25 °C up to 175 °C).

Transistor Effect in Improperly Connected Transistors.

Science.gov (United States)

Luzader, Stephen; Sanchez-Velasco, Eduardo

1996-01-01

Discusses the differences between the standard representation and a realistic representation of a transistor. Presents an experiment that helps clarify the explanation of the transistor effect and shows why transistors should be connected properly. (JRH)

Silicon junctionless field effect transistors as room temperature terahertz detectors

Energy Technology Data Exchange (ETDEWEB)

Marczewski, J., E-mail: jmarcz@ite.waw.pl; Tomaszewski, D.; Zaborowski, M. [Institute of Electron Technology, al. Lotnikow 32/46, 02-668 Warsaw (Poland); Knap, W. [Institute of High Pressure Physics of the Polish Academy of Sciences, ul. Sokolowska 29/37, 01-142 Warsaw (Poland); Laboratory Charles Coulomb, Montpellier University & CNRS, Place E. Bataillon, Montpellier 34095 (France); Zagrajek, P. [Institute of Optoelectronics, Military University of Technology, ul. gen. S. Kaliskiego 2, 00-908 Warsaw (Poland)

2015-09-14

Terahertz (THz) radiation detection by junctionless metal-oxide-semiconductor field-effect transistors (JL MOSFETs) was studied and compared with THz detection using conventional MOSFETs. It has been shown that in contrast to the behavior of standard transistors, the junctionless devices have a significant responsivity also in the open channel (low resistance) state. The responsivity for a photolithographically defined JL FET was 70 V/W and the noise equivalent power 460 pW/√Hz. Working in the open channel state may be advantageous for THz wireless and imaging applications because of its low thermal noise and possible high operating speed or large bandwidth. It has been proven that the junctionless MOSFETs can also operate in a zero gate bias mode, which enables simplification of the THz array circuitry. Existing models of THz detection by MOSFETs were considered and it has been demonstrated that the process of detection by these junctionless devices cannot be explained within the framework of the commonly accepted models and therefore requires a new theoretical approach.

Geometric photovoltaics applied to amorphous silicon thin film solar cells

Science.gov (United States)

Kirkpatrick, Timothy

Geometrically generalized analytical expressions for device transport are derived from first principles for a photovoltaic junction. Subsequently, conventional planar and unconventional coaxial and hemispherical photovoltaic architectures are applied to detail the device physics of the junction based on their respective geometry. For the conventional planar cell, the one-dimensional transport equations governing carrier dynamics are recovered. For the unconventional coaxial and hemispherical junction designs, new multi-dimensional transport equations are revealed. Physical effects such as carrier generation and recombination are compared for each cell architecture, providing insight as to how non-planar junctions may potentially enable greater energy conversion efficiencies. Numerical simulations are performed for arrays of vertically aligned, nanostructured coaxial and hemispherical amorphous silicon solar cells and results are compared to those from simulations performed for the standard planar junction. Results indicate that fundamental physical changes in the spatial dependence of the energy band profile across the intrinsic region of an amorphous silicon p-i-n junction manifest as an increase in recombination current for non-planar photovoltaic architectures. Despite an increase in recombination current, however, the coaxial architecture still appears to be able to surpass the efficiency predicted for the planar geometry, due to the geometry of the junction leading to a decoupling of optics and electronics.

Hydrogen interactions with silicon-on-insulator materials

OpenAIRE

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array.

Science.gov (United States)

Otsuka, Keigo; Inoue, Taiki; Maeda, Etsuo; Kometani, Reo; Chiashi, Shohei; Maruyama, Shigeo

2017-11-28

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Structure and field emission of graphene layers on top of silicon nanowire arrays

International Nuclear Information System (INIS)

Huang, Bohr-Ran; Chan, Hui-Wen; Jou, Shyankay; Chen, Guan-Yu; Kuo, Hsiu-An; Song, Wan-Jhen

2016-01-01

Graphical abstract: - Highlights: • We prepared graphene on top of silicon nanowires by transfer-print technique. • Graphene changed from discrete flakes to a continuous by repeated transfer-print. • The triple-layer graphene had high electron field emission due to large edge ratio. - Abstract: Monolayer graphene was grown on copper foils and then transferred on planar silicon substrates and on top of silicon nanowire (SiNW) arrays to form single- to quadruple-layer graphene films. The morphology, structure, and electron field emission (FE) of these graphene films were investigated. The graphene films on the planar silicon substrates were continuous. The single- to triple-layer graphene films on the SiNW arrays were discontinuous and while the quadruple-layer graphene film featured a mostly continuous area. The Raman spectra of the graphene films on the SiNW arrays showed G and G′ bands with a singular-Lorentzian shape together with a weak D band. The D band intensity decreased as the number of graphene layers increased. The FE efficiency of the graphene films on the planar silicon substrates and the SiNW arrays varied with the number of graphene layers. The turn-on field for the single- to quadruple-layer graphene films on planar silicon substrates were 4.3, 3.7, 3.5 and 3.4 V/μm, respectively. The turn-on field for the single- to quadruple-layer graphene films on SiNW arrays decreased to 3.9, 3.3, 3.0 and 3.3 V/μm, respectively. Correlation of the FE with structure and morphology of the graphene films is discussed.

Structure and field emission of graphene layers on top of silicon nanowire arrays

Energy Technology Data Exchange (ETDEWEB)

Huang, Bohr-Ran; Chan, Hui-Wen [Graduate Institute of Electro-Optical Engineering and Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Jou, Shyankay, E-mail: sjou@mail.ntust.edu.tw [Department of Materials Science and Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Chen, Guan-Yu [Graduate Institute of Electro-Optical Engineering and Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China); Kuo, Hsiu-An; Song, Wan-Jhen [Department of Materials Science and Engineering, National Taiwan University of Science and Technology, Taipei 106, Taiwan (China)

2016-01-30

Graphical abstract: - Highlights: • We prepared graphene on top of silicon nanowires by transfer-print technique. • Graphene changed from discrete flakes to a continuous by repeated transfer-print. • The triple-layer graphene had high electron field emission due to large edge ratio. - Abstract: Monolayer graphene was grown on copper foils and then transferred on planar silicon substrates and on top of silicon nanowire (SiNW) arrays to form single- to quadruple-layer graphene films. The morphology, structure, and electron field emission (FE) of these graphene films were investigated. The graphene films on the planar silicon substrates were continuous. The single- to triple-layer graphene films on the SiNW arrays were discontinuous and while the quadruple-layer graphene film featured a mostly continuous area. The Raman spectra of the graphene films on the SiNW arrays showed G and G′ bands with a singular-Lorentzian shape together with a weak D band. The D band intensity decreased as the number of graphene layers increased. The FE efficiency of the graphene films on the planar silicon substrates and the SiNW arrays varied with the number of graphene layers. The turn-on field for the single- to quadruple-layer graphene films on planar silicon substrates were 4.3, 3.7, 3.5 and 3.4 V/μm, respectively. The turn-on field for the single- to quadruple-layer graphene films on SiNW arrays decreased to 3.9, 3.3, 3.0 and 3.3 V/μm, respectively. Correlation of the FE with structure and morphology of the graphene films is discussed.

Electromagnetically Induced Transparency in Symmetric Planar Metamaterial at THz Wavelengths

Directory of Open Access Journals (Sweden)

Abdelwaheb Ourir

2015-03-01

Full Text Available We report the experimental observation and the evidence of the analogue of electromagnetically-induced transparency (EIT in a symmetric planar metamaterial. This effect has been obtained in the THz range thanks to a destructive Fano-interference between the two first modes of an array of multi-gap split ring resonators deposited on a silicon substrate. This structure is a planar thin film material with four-fold symmetry. Thanks to this property, a polarization-independent transmission has been achieved. The proposed metamaterial is well adapted to variety of slow-light applications in the infrared and optical range.

Electrical characterization of commercial NPN bipolar junction transistors under neutron and gamma irradiation

Directory of Open Access Journals (Sweden)

OO Myo Min

2014-01-01

Full Text Available Electronics components such as bipolar junction transistors, diodes, etc. which are used in deep space mission are required to be tolerant to extensive exposure to energetic neutrons and ionizing radiation. This paper examines neutron radiation with pneumatic transfer system of TRIGA Mark-II reactor at the Malaysian Nuclear Agency. The effects of the gamma radiation from Co-60 on silicon NPN bipolar junction transistors is also be examined. Analyses on irradiated transistors were performed in terms of the electrical characteristics such as current gain, collector current and base current. Experimental results showed that the current gain on the devices degraded significantly after neutron and gamma radiations. Neutron radiation can cause displacement damage in the bulk layer of the transistor structure and gamma radiation can induce ionizing damage in the oxide layer of emitter-base depletion layer. The current gain degradation is believed to be governed by the increasing recombination current in the base-emitter depletion region.

Silicon nanowire structures as high-sensitive pH-sensors

International Nuclear Information System (INIS)

Belostotskaya, S O; Chuyko, O V; Kuznetsov, A E; Kuznetsov, E V; Rybachek, E N

2012-01-01

Sensitive elements for pH-sensors created on silicon nanostructures were researched. Silicon nanostructures have been used as ion-sensitive field effect transistor (ISFET) for the measurement of solution pH. Silicon nanostructures have been fabricated by 'top-down' approach and have been studied as pH sensitive elements. Nanowires have the higher sensitivity. It was shown, that sensitive element, which is made of 'one-dimensional' silicon nanostructure have bigger pH-sensitivity as compared with 'two-dimensional' structure. Integrated element formed from two p- and n-type nanowire ISFET ('inverter') can be used as high sensitivity sensor for local relative change [H+] concentration in very small volume.

Structured-gate organic field-effect transistors

International Nuclear Information System (INIS)

Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B

2012-01-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)

Structured-gate organic field-effect transistors

Science.gov (United States)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Use of cermet thin film resistors with nitride passivated metal insulator field effect transistor

Science.gov (United States)

Brown, G. A.; Harrap, V.

1971-01-01

Film deposition of cermet resistors on same chip with metal nitride oxide silicon field effect transistors permits protection of contamination sensitive active devices from contaminants produced in cermet deposition and definition processes. Additional advantages include lower cost, greater reliability, and space savings.

SOI Transistor measurement techniques using body contacted transistors

International Nuclear Information System (INIS)

Worley, E.R.; Williams, R.

1989-01-01

Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

A simple ionizing radiation spectrometer/dosimeter based on radiation sensing field effect transistors (RadFETs)

International Nuclear Information System (INIS)

Moreno, D.J.; Hughes, R.C.; Jenkins, M.W.; Drumm, C.R.

1997-01-01

This paper reports on the processing steps in a silicon foundry leading to improved performance of the Radiation Sensing Field Effect Transistor (RadFET) and the use of multiple RadFETs in a handheld, battery operated, combination spectrometer/dosimeter

Advances in silicon nanophotonics

DEFF Research Database (Denmark)

Hvam, Jørn Märcher; Pu, Minhao

Silicon has long been established as an ideal material for passive integrated optical circuitry due to its high refractive index, with corresponding strong optical confinement ability, and its low-cost CMOS-compatible manufacturability. However, the inversion symmetry of the silicon crystal lattice.......g. in high-bit-rate optical communication circuits and networks, it is vital that the nonlinear optical effects of silicon are being strongly enhanced. This can among others be achieved in photonic-crystal slow-light waveguides and in nano-engineered photonic-wires (Fig. 1). In this talk I shall present some...... recent advances in this direction. The efficient coupling of light between optical fibers and the planar silicon devices and circuits is of crucial importance. Both end-coupling (Fig. 1) and grating-coupling solutions will be discussed along with polarization issues. A new scheme for a hybrid III...

Plasma wave instability and amplification of terahertz radiation in field-effect-transistor arrays

International Nuclear Information System (INIS)

Popov, V V; Tsymbalov, G M; Shur, M S

2008-01-01

We show that the strong amplification of terahertz radiation takes place in an array of field-effect transistors at small DC drain currents due to hydrodynamic plasmon instability of the collective plasmon mode. Planar designs compatible with standard integrated circuit fabrication processes and strong coupling of terahertz radiation to plasmon modes in FET arrays make such arrays very attractive for potential applications in solid-state terahertz amplifiers and emitters

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

Science.gov (United States)

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

New all-passive 4x4 planar optical phase diversity network

NARCIS (Netherlands)

Soldano, L.B.; Smit, M.K.; Vreede, De A.H.; Uffelen, van J.W.M.; Verbeek, B.H.; Bennekom, van P.K.; Krom, de W.H.C.; Etten, van W.C.

1991-01-01

The realisation and performance of an all-passive silicon-based 4*4 planar optical hybrid receiver for operation at 1.55- mu m wavelength is reported here for the first time. Measurements show 5 degrees /12 degrees /12 degrees /9 degrees output phase deviations, without tuning or trimming. Network

Low temperature sacrificial wafer bonding for planarization after very deep etching

NARCIS (Netherlands)

Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

1994-01-01

A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

Science.gov (United States)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

Total dose hardening of buried insulator in implanted silicon-on-insulator structures

International Nuclear Information System (INIS)

Mao, B.Y.; Chen, C.E.; Pollack, G.; Hughes, H.L.; Davis, G.E.

1987-01-01

Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants

Two-dimensional numerical simulation of boron diffusion for pyramidally textured silicon

International Nuclear Information System (INIS)

Ma, Fa-Jun; Duttagupta, Shubham; Shetty, Kishan Devappa; Meng, Lei; Hoex, Bram; Peters, Ian Marius; Samudra, Ganesh S.

2014-01-01

Multidimensional numerical simulation of boron diffusion is of great relevance for the improvement of industrial n-type crystalline silicon wafer solar cells. However, surface passivation of boron diffused area is typically studied in one dimension on planar lifetime samples. This approach neglects the effects of the solar cell pyramidal texture on the boron doping process and resulting doping profile. In this work, we present a theoretical study using a two-dimensional surface morphology for pyramidally textured samples. The boron diffusivity and segregation coefficient between oxide and silicon in simulation are determined by reproducing measured one-dimensional boron depth profiles prepared using different boron diffusion recipes on planar samples. The established parameters are subsequently used to simulate the boron diffusion process on textured samples. The simulated junction depth is found to agree quantitatively well with electron beam induced current measurements. Finally, chemical passivation on planar and textured samples is compared in device simulation. Particularly, a two-dimensional approach is adopted for textured samples to evaluate chemical passivation. The intrinsic emitter saturation current density, which is only related to Auger and radiative recombination, is also simulated for both planar and textured samples. The differences between planar and textured samples are discussed

Gate Tunable Transport in Graphene/MoS2/(Cr/Au Vertical Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Ghazanfar Nazir

2017-12-01

Full Text Available Two-dimensional materials based vertical field-effect transistors have been widely studied due to their useful applications in industry. In the present study, we fabricate graphene/MoS2/(Cr/Au vertical transistor based on the mechanical exfoliation and dry transfer method. Since the bottom electrode was made of monolayer graphene (Gr, the electrical transport in our Gr/MoS2/(Cr/Au vertical transistors can be significantly modified by using back-gate voltage. Schottky barrier height at the interface between Gr and MoS2 can be modified by back-gate voltage and the current bias. Vertical resistance (Rvert of a Gr/MoS2/(Cr/Au transistor is compared with planar resistance (Rplanar of a conventional lateral MoS2 field-effect transistor. We have also studied electrical properties for various thicknesses of MoS2 channels in both vertical and lateral transistors. As the thickness of MoS2 increases, Rvert increases, but Rplanar decreases. The increase of Rvert in the thicker MoS2 film is attributed to the interlayer resistance in the vertical direction. However, Rplanar shows a lower value for a thicker MoS2 film because of an excess of charge carriers available in upper layers connected directly to source/drain contacts that limits the conduction through layers closed to source/drain electrodes. Hence, interlayer resistance associated with these layers contributes to planer resistance in contrast to vertical devices in which all layers contribute interlayer resistance.

Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

Science.gov (United States)

Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

2017-07-01

Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

Review on analog/radio frequency performance of advanced silicon MOSFETs

Science.gov (United States)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

International Nuclear Information System (INIS)

Lee, Youngmin; Lee, Sejoon; Im, Hyunsik; Hiramoto, Toshiro

2015-01-01

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

Energy Technology Data Exchange (ETDEWEB)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik [Department of Semiconductor Science, Dongguk University-Seoul, Seoul 100-715 (Korea, Republic of); Hiramoto, Toshiro [Institute of Industrial Science, University of Tokyo, Tokyo 153-8505 (Japan)

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

A mm-wave planar microcavity structure for electron linear accelerator system

International Nuclear Information System (INIS)

Kang, Y.W.; Kustom, R.; Mills, F.; Mavrogenes, G.; Henke, H.

1993-01-01

The muffin-tin cavity structure is planar and well suited for mm-wave accelerator with silicon etching techniques. A constant impedance traveling-wave structure is considered for design simplicity. The RF parameters are calculated and the shunt impedance is compared with the shunt impedance of a disk loaded cylindrical structure

An improved PIN photodetector with integrated JFET on high-resistivity silicon

International Nuclear Information System (INIS)

Dalla Betta, Gian-Franco; Piemonte, Claudio; Boscardin, Maurizio; Gregori, Paolo; Zorzi, Nicola; Fazzi, Alberto; Pignatel, Giorgio U.

2006-01-01

We report on a PIN photodetector integrated with a Junction Field Effect Transistor (JFET) on a high-resistivity silicon substrate. Owing to a modified fabrication technology, the electrical and noise characteristics of the JFET transistor have been enhanced with respect to the previous versions of the device, allowing the performance to be significantly improved. In this paper, the main design and technological aspects relevant to the proposed structure are addressed and experimental results from the electrical characterization are discussed

Feasibility studies of microelectrode silicon detectors with integrated electronics

International Nuclear Information System (INIS)

Dalla Betta, G.-F.; Batignani, G.; Bettarini, S.; Boscardin, M.; Bosisio, L.; Carpinelli, M.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Lusiani, A.; Manghisoni, M.; Pignatel, G.U.; Rama, M.; Ratti, L.; Re, V.; Sandrelli, F.; Speziali, V.; Svelto, F.; Zorzi, N.

2002-01-01

We describe our experience on design and fabrication, on high-resistivity silicon substrates, of microstrip detectors and integrated electronics, devoted to high-energy physics experiments and medical/industrial imaging applications. We report on the full program of our collaboration, with particular regards to the tuning of a new fabrication process, allowing for the production of good quality transistors, while keeping under control the basic detector parameters, such as leakage current. Experimental results on JFET and bipolar transistors are presented, and a microstrip detector with an integrated JFET in source-follower configuration is introduced

Group IV nanotube transistors for next generation ubiquitous computing

KAUST Repository

Fahad, Hossain M.

2014-06-04

Evolution in transistor technology from increasingly large power consuming single gate planar devices to energy efficient multiple gate non-planar ultra-narrow (< 20 nm) fins has enhanced the scaling trend to facilitate doubling performance. However, this performance gain happens at the expense of arraying multiple devices (fins) per operation bit, due to their ultra-narrow dimensions (width) originated limited number of charges to induce appreciable amount of drive current. Additionally arraying degrades device off-state leakage and increases short channel characteristics, resulting in reduced chip level energy-efficiency. In this paper, a novel nanotube device (NTFET) topology based on conventional group IV (Si, SiGe) channel materials is discussed. This device utilizes a core/shell dual gate strategy to capitalize on the volume-inversion properties of an ultra-thin (< 10 nm) group IV nanotube channel to minimize leakage and short channel effects while maximizing performance in an area-efficient manner. It is also shown that the NTFET is capable of providing a higher output drive performance per unit chip area than an array of gate-all-around nanowires, while maintaining the leakage and short channel characteristics similar to that of a single gate-all-around nanowire, the latter being the most superior in terms of electrostatic gate control. In the age of big data and the multitude of devices contributing to the internet of things, the NTFET offers a new transistor topology alternative with maximum benefits from performance-energy efficiency-functionality perspective. © (2014) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

Single-event burnout hardening of planar power MOSFET with partially widened trench source

Science.gov (United States)

Lu, Jiang; Liu, Hainan; Cai, Xiaowu; Luo, Jiajun; Li, Bo; Li, Binhong; Wang, Lixin; Han, Zhengsheng

2018-03-01

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source). The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer (LET), which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to 0.7 pC/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications. Project supported by the National Natural Science Foundation of China (Nos. 61404161, 61404068, 61404169).

Transport properties of hydrogen passivated silicon nanotubes and silicon nanotube field effect transistors

KAUST Repository

Montes Muñ oz, Enrique; Schwingenschlö gl, Udo

2017-01-01

We investigate the electronic transport properties of silicon nanotubes attached to metallic electrodes from first principles, using density functional theory and the non-equilibrium Green's function method. The influence of the surface termination

Dithiopheneindenofluorene (TIF) Semiconducting Polymers with Very High Mobility in Field-Effect Transistors

KAUST Repository

Chen, Hu

2017-07-19

The charge-carrier mobility of organic semiconducting polymers is known to be enhanced when the energetic disorder of the polymer is minimized. Fused, planar aromatic ring structures contribute to reducing the polymer conformational disorder, as demonstrated by polymers containing the indacenodithiophene (IDT) repeat unit, which have both a low Urbach energy and a high mobility in thin-film-transistor (TFT) devices. Expanding on this design motif, copolymers containing the dithiopheneindenofluorene repeat unit are synthesized, which extends the fused aromatic structure with two additional phenyl rings, further rigidifying the polymer backbone. A range of copolymers are prepared and their electrical properties and thin-film morphology evaluated, with the co-benzothiadiazole polymer having a twofold increase in hole mobility when compared to the IDT analog, reaching values of almost 3 cm2 V−1 s−1 in bottom-gate top-contact organic field-effect transistors.

The use of large area silicon sensors for thermal neutron detection

International Nuclear Information System (INIS)

Schulte, R.L.; Swanson, F.; Kesselman, M.

1994-01-01

The use of large area planar silicon detectors coupled with gadolinium foils has been investigated to develop a thermal neutron detector having a large area-efficiency (Aε) product. Noise levels due to high detector capacitance limit the size of silicon detectors that can be utilized. Calculations using the Monte Carlo code, MCNP, have been made to determine the variation of intrinsic detection efficiency as a function of the discriminator threshold level required to eliminate the detector noise. Measurements of the noise levels for planar silicon detectors of various resistivities (400, 3000 and 5000 Ω cm) have been made and the optimal detector area-efficiency products have been determined. The response of a Si-Gd-Si sandwich detector with areas between 1 cm 2 and 10.5 cm 2 is presented and the effects of the detector capacitance and reverse current are discussed. ((orig.))

Hybrid light emitting transistors (Presentation Recording)

Science.gov (United States)

Muhieddine, Khalid; Ullah, Mujeeb; Namdas, Ebinazar B.; Burn, Paul L.

2015-10-01

Organic light-emitting diodes (OLEDs) are well studied and established in current display applications. Light-emitting transistors (LETs) have been developed to further simplify the necessary circuitry for these applications, combining the switching capabilities of a transistor with the light emitting capabilities of an OLED. Such devices have been studied using mono- and bilayer geometries and a variety of polymers [1], small organic molecules [2] and single crystals [3] within the active layers. Current devices can often suffer from low carrier mobilities and most operate in p-type mode due to a lack of suitable n-type organic charge carrier materials. Hybrid light-emitting transistors (HLETs) are a logical step to improve device performance by harnessing the charge carrier capabilities of inorganic semiconductors [4]. We present state of the art, all solution processed hybrid light-emitting transistors using a non-planar contact geometry [1, 5]. We will discuss HLETs comprised of an inorganic electron transport layer prepared from a sol-gel of zinc tin oxide and several organic emissive materials. The mobility of the devices is found between 1-5 cm2/Vs and they had on/off ratios of ~105. Combined with optical brightness and efficiencies of the order of 103 cd/m2 and 10-3-10-1 %, respectively, these devices are moving towards the performance required for application in displays. [1] M. Ullah, K. Tandy, S. D. Yambem, M. Aljada, P. L. Burn, P. Meredith, E. B. Namdas., Adv. Mater. 2013, 25, 53, 6213 [2] R. Capelli, S. Toffanin, G. Generali, H. Usta, A. Facchetti, M. Muccini, Nature Materials 2010, 9, 496 [3] T. Takenobu, S. Z. Bisri, T. Takahashi, M. Yahiro, C. Adachi, Y. Iwasa, Phys. Rev. Lett. 2008, 100, 066601 [4] H. Nakanotani, M. Yahiro, C. Adachi, K. Yano, Appl. Phys. Lett. 2007, 90, 262104 [5] K. Muhieddine, M. Ullah, B. N. Pal, P. Burn E. B. Namdas, Adv. Mater. 2014, 26,37, 6410

Pseudopotential-based electron quantum transport: Theoretical formulation and application to nanometer-scale silicon nanowire transistors

Energy Technology Data Exchange (ETDEWEB)

Fang, Jingtian, E-mail: jingtian.fang@utdallas.edu; Vandenberghe, William G.; Fu, Bo; Fischetti, Massimo V. [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, Texas 75080 (United States)

2016-01-21

We present a formalism to treat quantum electronic transport at the nanometer scale based on empirical pseudopotentials. This formalism offers explicit atomistic wavefunctions and an accurate band structure, enabling a detailed study of the characteristics of devices with a nanometer-scale channel and body. Assuming externally applied potentials that change slowly along the electron-transport direction, we invoke the envelope-wavefunction approximation to apply the open boundary conditions and to develop the transport equations. We construct the full-band open boundary conditions (self-energies of device contacts) from the complex band structure of the contacts. We solve the transport equations and present the expressions required to calculate the device characteristics, such as device current and charge density. We apply this formalism to study ballistic transport in a gate-all-around (GAA) silicon nanowire field-effect transistor with a body-size of 0.39 nm, a gate length of 6.52 nm, and an effective oxide thickness of 0.43 nm. Simulation results show that this device exhibits a subthreshold slope (SS) of ∼66 mV/decade and a drain-induced barrier-lowering of ∼2.5 mV/V. Our theoretical calculations predict that low-dimensionality channels in a 3D GAA architecture are able to meet the performance requirements of future devices in terms of SS swing and electrostatic control.

Self-consistent modeling of amorphous silicon devices

International Nuclear Information System (INIS)

Hack, M.

1987-01-01

The authors developed a computer model to describe the steady-state behaviour of a range of amorphous silicon devices. It is based on the complete set of transport equations and takes into account the important role played by the continuous distribution of localized states in the mobility gap of amorphous silicon. Using one set of parameters they have been able to self-consistently simulate the current-voltage characteristics of p-i-n (or n-i-p) solar cells under illumination, the dark behaviour of field-effect transistors, p-i-n diodes and n-i-n diodes in both the ohmic and space charge limited regimes. This model also describes the steady-state photoconductivity of amorphous silicon, in particular, its dependence on temperature, doping and illumination intensity

CHANNELING OF B-IONS IN SILICON

NARCIS (Netherlands)

VOS, M; MITCHELL, [No Value; SMULDERS, PJM

We present new results on the channeling of B ions in Si crystals. Standard surface barrier detectors have been used to record energy spectra for B ions backscattered from the near surface (approximately 1500 angstrom) of a silicon crystal, under perfect, and near axial and planar channeling

Device and material characterization and analytic modeling of amorphous silicon thin film transistors

Science.gov (United States)

Slade, Holly Claudia

Hydrogenated amorphous silicon thin film transistors (TFTs) are now well-established as switching elements for a variety of applications in the lucrative electronics market, such as active matrix liquid crystal displays, two-dimensional imagers, and position-sensitive radiation detectors. These applications necessitate the development of accurate characterization and simulation tools. The main goal of this work is the development of a semi- empirical, analytical model for the DC and AC operation of an amorphous silicon TFT for use in a manufacturing facility to improve yield and maintain process control. The model is physically-based, in order that the parameters scale with gate length and can be easily related back to the material and device properties. To accomplish this, extensive experimental data and 2D simulations are used to observe and quantify non- crystalline effects in the TFTs. In particular, due to the disorder in the amorphous network, localized energy states exist throughout the band gap and affect all regimes of TFT operation. These localized states trap most of the free charge, causing a gate-bias-dependent field effect mobility above threshold, a power-law dependence of the current on gate bias below threshold, very low leakage currents, and severe frequency dispersion of the TFT gate capacitance. Additional investigations of TFT instabilities reveal the importance of changes in the density of states and/or back channel conduction due to bias and thermal stress. In the above threshold regime, the model is similar to the crystalline MOSFET model, considering the drift component of free charge. This approach uses the field effect mobility to take into account the trap states and must utilize the correct definition of threshold voltage. In the below threshold regime, the density of deep states is taken into account. The leakage current is modeled empirically, and the parameters are temperature dependent to 150oC. The capacitance of the TFT can be

Analysis of Proton Radiation Effects on Gallium Nitride High Electron Mobility Transistors

Science.gov (United States)

2017-03-01

non - ionizing proton radiation damage effects at different energy levels on a GaN-on-silicon high electron mobility transistor...DISTRIBUTION CODE 13. ABSTRACT (maximum 200 words) In this work, a physics-based simulation of non - ionizing proton radiation damage effects at different...Polarization . . . . . . . . . . . . . . 6 2.3 Non - Ionizing Radiation Damage Effects . . . . . . . . . . . . . . . 10 2.4 Non - Ionizing Radiation Damage in

In-situ doped junctionless polysilicon nanowires field effect transistors for low-cost biosensors

Directory of Open Access Journals (Sweden)

Azeem Zulfiqar

2017-04-01

Full Text Available Silicon nanowire (SiNW field effect transistor based biosensors have already been proven to be a promising tool to detect biomolecules. However, the most commonly used fabrication techniques involve expensive Silicon-On-Insulator (SOI wafers, E-beam lithography and ion-implantation steps. In the work presented here, a top down approach to fabricate SiNW junctionless field effect biosensors using novel in-situ doped polysilicon is demonstrated. The p-type polysilicon is grown with an optimum boron concentration that gives a good metal-silicon electrical contact while maintaining the doping level at a low enough level to provide a good sensitivity for the biosensor. The silicon nanowires are patterned using standard photolithography and a wet etch method. The metal contacts are made from magnetron sputtered TiW and e-beam evaporation of gold. The passivation of electrodes has been done by sputtered Si3N4 which is patterned by a lift-off process. The characterization of the critical fabrication steps is done by Secondary Ion Mass Spectroscopy (SIMS and by statistical analysis of the measurements made on the width of the SiNWs. The electrical characterization of the SiNW in air is done by sweeping the back gate voltage while keeping the source drain potential to a constant value and surface characterization is done by applying liquid gate in phosphate buffered saline (PBS solution. The fabricated SiNWs sensors functionalized with (3-aminopropyltriethoxysilane (APTES have demonstrated good sensitivity in detecting different pH buffer solutions. Keywords: In-situ doped, Polysilicon nanowire, Field effect transistor, Biosensor

The free electron gas primary thermometer using an ordinary bipolar junction transistor approaches ppm accuracy

Science.gov (United States)

Mimila-Arroyo, J.

2017-06-01

In this paper, it is demonstrated that the free electron gas primary thermometer based on a bipolar junction transistor is able to provide the temperature with an accuracy of a few parts per million. Its simple functioning principle exploits the behavior of the collector current when properly biased to extract the temperature. Using general purpose silicon transistors at the water triple point (273.16 K) and gallium melting point (302.9146), an accuracy of a few parts per million has been reached, constituting the simplest and the easiest to operate primary thermometer, that might be considered even for the redefinition of Kelvin.

Biosensor properties of SOI nanowire transistors with a PEALD Al{sub 2}O{sub 3} dielectric protective layer

Energy Technology Data Exchange (ETDEWEB)

Popov, V. P., E-mail: popov@isp.nsc.ru; Ilnitskii, M. A.; Zhanaev, E. D. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation); Myakon’kich, A. V.; Rudenko, K. V. [Russian Academy of Sciences, Physical Technological Institute (Russian Federation); Glukhov, A. V. [Novosibirsk Semiconductor Device Plant and Design Bureau (Russian Federation)

2016-05-15

The properties of protective dielectric layers of aluminum oxide Al{sub 2}O{sub 3} applied to prefabricated silicon-nanowire transistor biochips by the plasma enhanced atomic layer deposition (PEALD) method before being housed are studied depending on the deposition and annealing modes. Coating the natural silicon oxide with a nanometer Al{sub 2}O{sub 3} layer insignificantly decreases the femtomole sensitivity of biosensors, but provides their stability in bioliquids. In deionized water, transistors with annealed aluminum oxide are closed due to the trapping of negative charges of <(1–10) × 10{sup 11} cm{sup −2} at surface states. The application of a positive potential to the substrate (V{sub sub} > 25 V) makes it possible to eliminate the negative charge and to perform multiple measurements in liquid at least for half a year.

Leakage and field emission in side-gate graphene field effect transistors

Energy Technology Data Exchange (ETDEWEB)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.; Cucolo, A. M. [Physics Department “E.R. Caianiello,” University of Salerno, via G. Paolo II, 84084 Fisciano (Italy); CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Giubileo, F. [CNR-SPIN Salerno, via G. Paolo II, 84084 Fisciano (Italy); Russo, S.; Unal, S. [Physics Department, University of Exeter, Stocker Road 6, Exeter, Devon EX4 4QL (United Kingdom); Passacantando, M.; Grossi, V. [Department of Physical and Chemical Sciences, University of L' Aquila, Via Vetoio, 67100 Coppito, L' Aquila (Italy)

2016-07-11

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current density as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Science.gov (United States)

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Effect of 1MeV electron beam on transistors and circuits

International Nuclear Information System (INIS)

Lee, Tae Hoon

1998-02-01

It has been known that semiconductor devices operating in a radiation environment exhibited significant alterations of their electrical responses. Since an electron beam bombardment produces lattice damage in Si and charged defects in SiO 2 , several electrical parameters of transistors exhibit significant changes. Those parameters are the current gain of BJT (Bipolar Junction Transistor) and the threshold voltage of MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The degradation of transistors brings about that of circuits. This paper presents the results of experiments and simulations performed to study the effects of 1MeV electron beam irradiation on selected silicon transistors and circuits. For BJTs, the current gains of npn (2N3904) and pnp (2N3906) linearly decreased as the irradiation dose increased, and from this result, the damage constants, Ks were obtained as 13.65 for 2N3904 and 22.52 for 2N3906 in MGy, indicating a more stable operation in the electron radiation environment for pnp than that for npn. The decrease of current gain was due to that of minority-carrier lifetime in the base region. For MOSFETs (CD4007s), the threshold voltages of NMOS and PMOS shifted to the lower values, which was resulted from the accumulation of charge in SiO 2 . The charges could be categorized into fixed oxide charge and interfacial trap charge. From experimental results, the amounts of the induced charges could be quantitatively estimated. These degradations of transistors brought about the decrease in the voltage gain of CE (Common Emitter) amplifier and the shifts in the inverting voltage of inverter. Additionally, PSpice simulations of these circuits were carried out by modeling of irradiated transistors. The comparison of simulation with experiment showed the relatively good agreement of simulation for the degradation of circuits after irradiation

The use of large area silicon sensors for thermal neutron detection

Energy Technology Data Exchange (ETDEWEB)

Schulte, R.L. (Research and Development Center, Mail Stop: A01-26, Grumman Aerospace Corporation, Bethpage, NY 11714 (United States)); Swanson, F. (Research and Development Center, Mail Stop: A01-26, Grumman Aerospace Corporation, Bethpage, NY 11714 (United States)); Kesselman, M. (Research and Development Center, Mail Stop: A01-26, Grumman Aerospace Corporation, Bethpage, NY 11714 (United States))

1994-12-30

The use of large area planar silicon detectors coupled with gadolinium foils has been investigated to develop a thermal neutron detector having a large area-efficiency (A[epsilon]) product. Noise levels due to high detector capacitance limit the size of silicon detectors that can be utilized. Calculations using the Monte Carlo code, MCNP, have been made to determine the variation of intrinsic detection efficiency as a function of the discriminator threshold level required to eliminate the detector noise. Measurements of the noise levels for planar silicon detectors of various resistivities (400, 3000 and 5000 [Omega] cm) have been made and the optimal detector area-efficiency products have been determined. The response of a Si-Gd-Si sandwich detector with areas between 1 cm[sup 2] and 10.5 cm[sup 2] is presented and the effects of the detector capacitance and reverse current are discussed. ((orig.))

Nanoelectronics-biology frontier: From nanoscopic probes for action potential recording in live cells to three-dimensional cyborg tissues

OpenAIRE

Duan, Xiaojie; Fu, Tian-Ming; Liu, Jia; Lieber, Charles M.

2013-01-01

Semiconductor nanowires configured as the active channels of field-effect transistors (FETs) have been used as detectors for high-resolution electrical recording from single live cells, cell networks, tissues and organs. Extracellular measurements with substrate supported silicon nanowire (SiNW) FETs, which have projected active areas orders of magnitude smaller than conventional microfabricated multielectrode arrays (MEAs) and planar FETs, recorded action potential and field potential signa...

Structures of Pt clusters on graphene doped with nitrogen, boron, and silicon: a theoretical study

Institute of Scientific and Technical Information of China (English)

Dai Xian-Qi; Tang Ya-Nan; Dai Ya-Wei; Li Yan-Hui; Zhao Jian-Hua; Zhao Bao; Yang Zong-Xian

2011-01-01

The structures of Pt clusters on nitrogen-, boron-, silicon- doped graphenes are theoretically studied using densityfunctional theory. These dopants (nitrogen, boron and silicon) each do not induce a local curvature in the graphene and the doped graphenes all retain their planar form. The formation energy of the silicon-graphene system is lower than those of the nitrogen-, boron-doped graphenes, indicating that the silicon atom is easier to incorporate into the graphene.All the substitutional impurities enhance the interaction between the Pt atom and the graphene. The adsorption energy of a Pt adsorbed on the silicon-doped graphene is much higher than those on the nitrogen- and boron-doped graphenes.The doped silicon atom can provide more charges to enhance the Pt-graphene interaction and the formation of Pt clusters each with a large size. The stable structures of Pt clusters on the doped-graphenes are dimeric, triangle and tetrahedron with the increase of the Pt coverage. Of all the studied structures, the tetrahedron is the most stable cluster which has the least influence on the planar surface of doped-graphene.

Radiation hardness of silicon detectors for collider experiments

International Nuclear Information System (INIS)

Golutvin, I.; Cheremukhin, A.; Fefelova, E.

1995-01-01

The silicon planar detectors before and after fast neutron irradiation ( n o> = 1.35 MeV) at room temperature have been investigated. Maximal neutron fluence has been 8 · 10 13 cm -2 . The detectors have been manufactured of the high resistivity (1 : 10 k Ohm · cm) n-type float-zone silicon (FZ-Si) with the orientation supplied by two different producers: WACKER CHEMITRONIC and Zaporojie Titanium-Magnesium Factory (ZTMF). The influence of fast neutron irradiation of the main parameters of the starting silicon before the technological high temperature treatment has been investigated as well. 30 refs., 17 figs., 5 tabs

A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

Science.gov (United States)

Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

2018-04-01

We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

KAUST Repository

Ghoneim, Mohamed T.

2015-04-24

A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol-gel coating cycles required (i.e., more cost-effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano-scale due to the larger feature size-to-depth aspect ratio (critical for ultra-high density non-volatile memory applications). Utilizing the inverse proportionality between substrate\\'s thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer-less manufacturable process into a flexible form that matches organic electronics\\' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

Ternary logic implemented on a single dopant atom field effect silicon transistor

NARCIS (Netherlands)

Klein, M.; Mol, J.A.; Verduijn, J.; Lansbergen, G.P.; Rogge, S.; Levine, R.D.; Remacle, F.

2010-01-01

We provide an experimental proof of principle for a ternary multiplier realized in terms of the charge state of a single dopant atom embedded in a fin field effect transistor (Fin-FET). Robust reading of the logic output is made possible by using two channels to measure the current flowing through

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

Science.gov (United States)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Extrinsic passivation of silicon surfaces for solar cells

OpenAIRE

Bonilla, R.S.; Reichel, C.; Hermle, M.; Martins, G.; Wilshaw, P.R.

2015-01-01

In the present work we study the extent to which extrinsic chemical and field effect passivation can improve the overall electrical passivation quality of silicon dioxide on silicon. Here we demonstrate that, when optimally applied, extrinsic passivation can produce surface recombination velocities below 1.2 cm/s in planar 1 Omega cm n-type Si. This is largely due to the additional field effect passivation component which reduces the recombination velocity below 2.13 cm/s. On textured surface...

Planar n-in-n quad module prototypes for the ATLAS ITk upgrade at HL-LHC

Science.gov (United States)

Gisen, A.; Altenheiner, S.; Burmeister, I.; Gößling, C.; Klingenberg, R.; Kröninger, K.; Lönker, J.; Weers, M.; Wizemann, F.

2017-12-01

In order to meet the requirements of the High Luminosity LHC (HL-LHC), it will be necessary to replace the current tracker of the ATLAS experiment. Therefore, a new all-silicon tracking detector is being developed, the so-called Inner Tracker (ITk). The use of quad chip modules is intended in its pixel region. These modules consist of a silicon sensor that forms a unit along with four read-out chips. The current ATLAS pixel detector consists of planar n-in-n silicon pixel sensors. Similar sensors and four FE-I4 read-out chips were assembled to first prototypes of planar n-in-n quad modules. The main focus of the investigation of these modules was the region between the read-out chips, especially the central area between all four read-out chips. There are special pixel cells placed on the sensor which cover the gap between the read-out chips. This contribution focuses on the characterization of a non-irradiated device, including important sensor characteristics, charge collection determined with radioactive sources as well as hit efficiency measurements, performed in the laboratory and at testbeams. In addition, first laboratory results of an irradiated device are presented.

Modeling of planar carbon nanotube field effect transistor and three dimensional simulation of current-voltage characteristics

International Nuclear Information System (INIS)

Dinh Sy Hien; Nguyen Thi Luong; Thi Tran Anh Tuan; Dinh Viet Nga

2009-01-01

We provide a CNTFET model with planar geometry. Planar CNTFETs constitute the majority of devices fabricated to date, mostly due to their relative simplicity and moderate compatibility with existing manufacturing technologies. We explore the possibilities of using non-equilibrium Green function method to get I-V characteristics for CNTFETs. This simulator also includes a graphic user interface (GUI) of Matlab that enables parameter entry, calculation control, intuitive display of calculation results, and in-situ data analysis methods. In this paper, we review the capabilities of simulator, and give examples of typical CNTFET 3D simulations. The I-V characteristics of CNTFET are also presented.

Optimizing pentacene thin-film transistor performance: Temperature and surface condition induced layer growth modification.

Science.gov (United States)

Lassnig, R; Hollerer, M; Striedinger, B; Fian, A; Stadlober, B; Winkler, A

2015-11-01

In this work we present in situ electrical and surface analytical, as well as ex situ atomic force microscopy (AFM) studies on temperature and surface condition induced pentacene layer growth modifications, leading to the selection of optimized deposition conditions and entailing performance improvements. We prepared p ++ -silicon/silicon dioxide bottom-gate, gold bottom-contact transistor samples and evaluated the pentacene layer growth for three different surface conditions (sputtered, sputtered + carbon and unsputtered + carbon) at sample temperatures during deposition of 200 K, 300 K and 350 K. The AFM investigations focused on the gold contacts, the silicon dioxide channel region and the highly critical transition area. Evaluations of coverage dependent saturation mobilities, threshold voltages and corresponding AFM analysis were able to confirm that the first 3-4 full monolayers contribute to the majority of charge transport within the channel region. At high temperatures and on sputtered surfaces uniform layer formation in the contact-channel transition area is limited by dewetting, leading to the formation of trenches and the partial development of double layer islands within the channel region instead of full wetting layers. By combining the advantages of an initial high temperature deposition (well-ordered islands in the channel) and a subsequent low temperature deposition (continuous film formation for low contact resistance) we were able to prepare very thin (8 ML) pentacene transistors of comparably high mobility.

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

Directory of Open Access Journals (Sweden)

Xiaojun Cheng

2014-05-01

Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

Novel vertical silicon photodiodes based on salicided polysilicon trenched contacts

International Nuclear Information System (INIS)

Kaminski, Yelena; Shauly, Eitan; Paz, Yaron

2015-01-01

The classical concept of silicon photodiodes comprises of a planar design characterized by heavily doped emitters. Such geometry has low collection efficiency of the photons absorbed close to the surface. An alternative, promising, approach is to use a vertical design. Nevertheless, realization of such design is technologically challenged, hence hardly explored. Herein, a novel type of silicon photodiodes, based on salicided polysilicon trenched contacts, is presented. These contacts can be prepared up to 10 μm in depth, without showing any leakage current associated with the increase in the contact area. Consequently, the trenched photodiodes revealed better performance than no-trench photodiodes. A simple two dimensional model was developed, allowing to estimate the conditions under which a vertical design has the potential to have better performance than that of a planar design. At large, the deeper the trench is, the better is the vertical design relative to the planar (up to 10 μm for silicon). The vertical design is more advantageous for materials characterized by short diffusion lengths of the carriers. Salicided polysilicon trenched contacts open new opportunities for the design of solar cells and image sensors. For example, these contacts may passivate high contact area buried contacts, by virtue of the conformity of polysilicon interlayer, thus lowering the via resistance induced recombination enhancement effect

Novel vertical silicon photodiodes based on salicided polysilicon trenched contacts

Energy Technology Data Exchange (ETDEWEB)

Kaminski, Yelena [Department of Chemical Engineering, Technion, Haifa (Israel); TowerJazz Ltd. Migdal Haemek (Israel); Shauly, Eitan [TowerJazz Ltd. Migdal Haemek (Israel); Paz, Yaron, E-mail: paz@tx.technion.ac.il [Department of Chemical Engineering, Technion, Haifa (Israel)

2015-12-07

The classical concept of silicon photodiodes comprises of a planar design characterized by heavily doped emitters. Such geometry has low collection efficiency of the photons absorbed close to the surface. An alternative, promising, approach is to use a vertical design. Nevertheless, realization of such design is technologically challenged, hence hardly explored. Herein, a novel type of silicon photodiodes, based on salicided polysilicon trenched contacts, is presented. These contacts can be prepared up to 10 μm in depth, without showing any leakage current associated with the increase in the contact area. Consequently, the trenched photodiodes revealed better performance than no-trench photodiodes. A simple two dimensional model was developed, allowing to estimate the conditions under which a vertical design has the potential to have better performance than that of a planar design. At large, the deeper the trench is, the better is the vertical design relative to the planar (up to 10 μm for silicon). The vertical design is more advantageous for materials characterized by short diffusion lengths of the carriers. Salicided polysilicon trenched contacts open new opportunities for the design of solar cells and image sensors. For example, these contacts may passivate high contact area buried contacts, by virtue of the conformity of polysilicon interlayer, thus lowering the via resistance induced recombination enhancement effect.

Ion-step method for surface potential sensing of silicon nanowires

NARCIS (Netherlands)

Chen, S.; van Nieuwkasteele, Jan William; van den Berg, Albert; Eijkel, Jan C.T.

2016-01-01

This paper presents a novel stimulus-response method for surface potential sensing of silicon nanowire (Si NW) field-effect transistors. When an "ion-step" from low to high ionic strength is given as a stimulus to the gate oxide surface, an increase of double layer capacitance is therefore expected.

arXiv Planar n-in-n quad module prototypes for the ATLAS ITk upgrade at HL-LHC

CERN Document Server

Gisen, A.; Burmeister, I.; Gößling, C.; Klingenberg, R.; Kröninger, K.; Lönker, J.; Weers, M.; Wizemann, F.

2017-12-15

In order to meet the requirements of the High Luminosity LHC (HL-LHC), it will be necessary to replace the current tracker of the ATLAS experiment. Therefore, a new all-silicon tracking detector is being developed, the so-called Inner Tracker (ITk). The use of quad chip modules is intended in its pixel region. These modules consist of a silicon sensor that forms a unit along with four read-out chips. The current ATLAS pixel detector consists of planar n-in-n silicon pixel sensors. Similar sensors and four FE-I4 read-out chips were assembled to first prototypes of planar n-in-n quad modules. The main focus of the investigation of these modules was the region between the read-out chips, especially the central area between all four read-out chips. There are special pixel cells placed on the sensor which cover the gap between the read-out chips. This contribution focuses on the characterization of a non-irradiated device, including important sensor characteristics, charge collection determined with radioactive so...

Improved Optics in Monolithic Perovskite/Silicon Tandem Solar Cells with a Nanocrystalline Silicon Recombination Junction

KAUST Repository

Sahli, Florent

2017-10-09

Perovskite/silicon tandem solar cells are increasingly recognized as promi­sing candidates for next-generation photovoltaics with performance beyond the single-junction limit at potentially low production costs. Current designs for monolithic tandems rely on transparent conductive oxides as an intermediate recombination layer, which lead to optical losses and reduced shunt resistance. An improved recombination junction based on nanocrystalline silicon layers to mitigate these losses is demonstrated. When employed in monolithic perovskite/silicon heterojunction tandem cells with a planar front side, this junction is found to increase the bottom cell photocurrent by more than 1 mA cm−2. In combination with a cesium-based perovskite top cell, this leads to tandem cell power-conversion efficiencies of up to 22.7% obtained from J–V measurements and steady-state efficiencies of up to 22.0% during maximum power point tracking. Thanks to its low lateral conductivity, the nanocrystalline silicon recombination junction enables upscaling of monolithic perovskite/silicon heterojunction tandem cells, resulting in a 12.96 cm2 monolithic tandem cell with a steady-state efficiency of 18%.

Improved Optics in Monolithic Perovskite/Silicon Tandem Solar Cells with a Nanocrystalline Silicon Recombination Junction

KAUST Repository

Sahli, Florent; Kamino, Brett A.; Werner, Jé ré mie; Brä uninger, Matthias; Paviet-Salomon, Bertrand; Barraud, Loris; Monnard, Raphaë l; Seif, Johannes Peter; Tomasi, Andrea; Jeangros, Quentin; Hessler-Wyser, Aï cha; De Wolf, Stefaan; Despeisse, Matthieu; Nicolay, Sylvain; Niesen, Bjoern; Ballif, Christophe

2017-01-01

Perovskite/silicon tandem solar cells are increasingly recognized as promi­sing candidates for next-generation photovoltaics with performance beyond the single-junction limit at potentially low production costs. Current designs for monolithic tandems rely on transparent conductive oxides as an intermediate recombination layer, which lead to optical losses and reduced shunt resistance. An improved recombination junction based on nanocrystalline silicon layers to mitigate these losses is demonstrated. When employed in monolithic perovskite/silicon heterojunction tandem cells with a planar front side, this junction is found to increase the bottom cell photocurrent by more than 1 mA cm−2. In combination with a cesium-based perovskite top cell, this leads to tandem cell power-conversion efficiencies of up to 22.7% obtained from J–V measurements and steady-state efficiencies of up to 22.0% during maximum power point tracking. Thanks to its low lateral conductivity, the nanocrystalline silicon recombination junction enables upscaling of monolithic perovskite/silicon heterojunction tandem cells, resulting in a 12.96 cm2 monolithic tandem cell with a steady-state efficiency of 18%.

Planar self-aligned ion implanted InP MISFETS for fast logic applications

International Nuclear Information System (INIS)

Cameron, D.C.; Irving, L.D.; Whitehouse, C.R.; Woodward, J.; Lee, D.

1983-01-01

The first successful use of ion implantation to fabricate truly self-aligned planar n-channel enhancement-mode indium phosphide MISFITS is reported. The transistors have been fabricated on iron-doped semi-insulating material using PECVD-deposited SiO 2 as the gate dielectric and molybdenum gate electrodes. The self-aligned source and drain contact regions were produced by Si 29 ion implantation using each gate stripe as an implant mask. The devices fabricated to date have exhibited channel mobilities up to value of 2400 cm 2 v -1 s -1 , with excellent uniformity and stability of the device characteristics also being observed. (author)

Efficiency measurements for 3D silicon strip detectors

Energy Technology Data Exchange (ETDEWEB)

Parzefall, Ulrich, E-mail: ulrich.parzefall@physik.uni-freiburg.d [Physikalisches Institut, Universitaet Freiburg, Hermann-Herder-Str. 3, D-79104 Freiburg (Germany); Dalla Betta, Gian-Franco [INFN Trento and Universita di Trento, via Sommarive 14, 38050 Povo di Trento (Italy); Boscardin, Maurizio [FBK-irst, Center for Materials and Microsystems, via Sommarive 18, 38050 Povo di Trento (Italy); Eckert, Simon [Physikalisches Institut, Universitaet Freiburg, Hermann-Herder-Str. 3, D-79104 Freiburg (Germany); Eklund, Lars; Fleta, Celeste [University of Glasgow, Department of Physics and Astronomy, Glasgow G12 8QQ (United Kingdom); Jakobs, Karl; Koehler, Michael; Kuehn, Susanne; Pahn, Gregor [Physikalisches Institut, Universitaet Freiburg, Hermann-Herder-Str. 3, D-79104 Freiburg (Germany); Parkes, Chris; Pennicard, David [University of Glasgow, Department of Physics and Astronomy, Glasgow G12 8QQ (United Kingdom); Ronchin, Sabina [FBK-irst, Center for Materials and Microsystems, via Sommarive 18, 38050 Povo di Trento (Italy); Zoboli, Andrea [INFN Trento and Universita di Trento, via Sommarive 14, 38050 Povo di Trento (Italy); Zorzi, Nicola [FBK-irst, Center for Materials and Microsystems, via Sommarive 18, 38050 Povo di Trento (Italy)

2010-11-01

Silicon strip detectors are widely used as part of the inner tracking layers in particle physics experiments. For applications at the luminosity upgrade of the Large Hadron Collider (LHC), the sLHC, silicon detectors with extreme radiation hardness are required. The 3D detector design, where electrodes are processed from underneath the strips into the silicon bulk material, provides a way to enhance the radiation tolerance of standard planar silicon strip detectors. Detectors with several innovative 3D designs that constitute a simpler and more cost-effective processing than the 3D design initially proposed were connected to read-out electronics from LHC experiments and subsequently tested. Results on the amount of charge collected, the noise and the uniformity of charge collection are given.

Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

Science.gov (United States)

Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

2010-01-01

Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

High-performance silicon nanowire bipolar phototransistors

Science.gov (United States)

Tan, Siew Li; Zhao, Xingyan; Chen, Kaixiang; Crozier, Kenneth B.; Dan, Yaping

2016-07-01

Silicon nanowires (SiNWs) have emerged as sensitive absorbing materials for photodetection at wavelengths ranging from ultraviolet (UV) to the near infrared. Most of the reports on SiNW photodetectors are based on photoconductor, photodiode, or field-effect transistor device structures. These SiNW devices each have their own advantages and trade-offs in optical gain, response time, operating voltage, and dark current noise. Here, we report on the experimental realization of single SiNW bipolar phototransistors on silicon-on-insulator substrates. Our SiNW devices are based on bipolar transistor structures with an optically injected base region and are fabricated using CMOS-compatible processes. The experimentally measured optoelectronic characteristics of the SiNW phototransistors are in good agreement with simulation results. The SiNW phototransistors exhibit significantly enhanced response to UV and visible light, compared with typical Si p-i-n photodiodes. The near infrared responsivities of the SiNW phototransistors are comparable to those of Si avalanche photodiodes but are achieved at much lower operating voltages. Compared with other reported SiNW photodetectors as well as conventional bulk Si photodiodes and phototransistors, the SiNW phototransistors in this work demonstrate the combined advantages of high gain, high photoresponse, low dark current, and low operating voltage.

Planar, Polysilazane?Derived Porous Ceramic Supports for Membrane and Catalysis Applications

OpenAIRE

Konegger, Thomas; Williams, Lee F.; Bordia, Rajendra K.

2015-01-01

Porous, silicon carbonitride?based ceramic support structures for potential membrane and catalysis applications were generated from a preceramic polysilazane precursor in combination with spherical, ultrahigh?molecular weight polyethylene microparticles through a sacrificial filler approach. A screening evaluation was used for the determination of the impact of both porogen content and porogen size on pore structure, strength, and permeability characteristics of planar specimens. By optimizin...

Optical properties of erbium-doped porous silicon waveguides

Energy Technology Data Exchange (ETDEWEB)

Najar, A. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B P. 80518, 22305 Lannion Cedex (France); Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Charrier, J. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B P. 80518, 22305 Lannion Cedex (France)]. E-mail: joel.charier@univ-rennes1.fr; Ajlani, H. [Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Lorrain, N. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B P. 80518, 22305 Lannion Cedex (France); Elhouichet, H. [Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Oueslati, M. [Laboratoire de Spectroscopie Raman, Faculte des Sciences de Tunis, 2092 ElManar, Tunis (Tunisia); Haji, L. [Laboratoire d' Optronique UMR 6082-FOTON, Universite de Rennes 1, 6 rue de Kerampont, B P. 80518, 22305 Lannion Cedex (France)

2006-12-15

Planar and buried channel porous silicon waveguides (WG) were prepared from p{sup +}-type silicon substrate by a two-step anodization process. Erbium ions were incorporated into pores of the porous silicon layers by an electrochemical method using ErCl{sub 3}-saturated solution. Erbium concentration of around 10{sup 20} at/cm{sup 3} was determined by energy-dispersive X-ray analysis performed on SEM cross-section. The luminescence properties of erbium ions in the IR range were determined and a luminescence time decay of 420 {mu}s was measured. Optical losses were studied on these WG. The increased losses after doping were discussed.

Effect of 50 MeV Li3+ ion irradiation on electrical characteristics of high speed NPN power transistor

International Nuclear Information System (INIS)

Dinesh, C.M.; Ramani; Radhakrishna, M.C.; Dutt, R.N.; Khan, S.A.; Kanjilal, D.

2008-01-01

Silicon NPN overlay RF power high speed commercial bipolar junction transistors (BJTs) find applications in military, space and communication equipments. Here we report the effect of 50 MeV Li 3+ ion irradiation in the fluence range 1 x 10 11 -1.8 x 10 12 ions cm -2 on NPN power transistor. The range (R), electronic energy loss (S e ), nuclear energy loss (S n ), total ionizing dose (TID) and total displacement damage (D d ) in the silicon target are calculated from TRIM Monte Carlo Code. Output resistance is 3.568 x 10 4 Ω for unirradiated device and it increases to 6 x 10 7 Ω as the fluence is increased from 1 x 10 11 to 1.8 x 10 12 ions cm -2 . The capacitance of the emitter-base junction of the transistor decreases and dielectric loss of the emitter-base junction increases with increase in ion fluence. The built in voltage of the unirradiated sample is 0.5 V and it shifts to 0.4 V after irradiation at fluence of 1.8 x 10 12 ions cm -2 and the corresponding doping density reduced to 5.758 x 10 16 cm -3 . The charge carrier removal rate varies linearly with the increase in ion fluence

Development of semiconductor electronics

International Nuclear Information System (INIS)

Bardeen, John.

1977-01-01

In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

Enhancement of the saturation mobility in a ferroelectric-gated field-effect transistor by the surface planarization of ferroelectric film

Energy Technology Data Exchange (ETDEWEB)

Kim, Woo Young, E-mail: semigumi@kaist.ac.kr [Department of Mechanical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of); Jeon, Gwang-Jae; Kang, In-Ku; Shim, Hyun Bin; Lee, Hee Chul [Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 373-1, Guseong-dong, Yuseong-gu, Daejeon 305-701 (Korea, Republic of)

2015-09-30

Ferroelectricity refers to the property of a dielectric material to undergo spontaneous polarization which originates from the crystalline phase. Hence, ferroelectric materials have a certain degree of surface roughness when they are formed as a thin film. A high degree of surface roughness may cause unintended phenomena when the ferroelectric material is used in electronic devices. Specifically, the quality of subsequently deposited film could be affected by the rough surface. The present study reports that the surface roughness of ferroelectric polymer film can be reduced by a double-spin-coating method of a solution, with control of the solubility of the solution. At an identical thickness of 350 nm, double-spin-coated ferroelectric film has a root-mean-square roughness of only 3 nm, while for single-spin-coated ferroelectric film this value is approximately 16 nm. A ferroelectric-gated field-effect transistor was fabricated using the proposed double-spin-coating method, showing a maximum saturation mobility as much as seven-fold than that of a transistor fabricated with single-spin-coated ferroelectric film. The enhanced saturation mobility could be explained by the Poole–Frenkel conduction mechanism. The proposed method to reduce the surface roughness of ferroelectric film would be useful for high performance organic electronic devices, including crystalline-phase dielectric film. - Highlights: • Single and double-layer solution-processed polymer ferroelectric films were obtained. • Adjusting the solvent solubility allows making double-layer ferroelectric (DF) films. • The DF film has a smoother surface than single-layer ferroelectric (SF) film. • DF-gated transistor has faster saturation mobility than SF-based transistor. • Solvent solubility adjustment led to higher performance organic devices.

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

Waveguide cores containing silicon nanocrystals as active spectral filters for silicon-based photonics

Czech Academy of Sciences Publication Activity Database

Pelant, Ivan; Ostatnický, T.; Valenta, J.; Luterová, Kateřina; Skopalová, Eva; Mates, Tomáš; Elliman, R. G.

2006-01-01

Roč. 83, - (2006), s. 87-91 ISSN 0946-2171 R&D Projects: GA ČR(CZ) GA202/03/0789; GA ČR(CZ) GP202/01/D030; GA AV ČR(CZ) IAA1010316; GA MŠk LC510 Institutional research plan: CEZ:AV0Z10100521 Keywords : silicon nanocrystals * planar waveguides * leaky modes Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 2.023, year: 2006

Doped Organic Transistors.

Science.gov (United States)

Lüssem, Björn; Keum, Chang-Min; Kasemann, Daniel; Naab, Ben; Bao, Zhenan; Leo, Karl

2016-11-23

Organic field-effect transistors hold the promise of enabling low-cost and flexible electronics. Following its success in organic optoelectronics, the organic doping technology is also used increasingly in organic field-effect transistors. Doping not only increases device performance, but it also provides a way to fine-control the transistor behavior, to develop new transistor concepts, and even improve the stability of organic transistors. This Review summarizes the latest progress made in the understanding of the doping technology and its application to organic transistors. It presents the most successful doping models and an overview of the wide variety of materials used as dopants. Further, the influence of doping on charge transport in the most relevant polycrystalline organic semiconductors is reviewed, and a concise overview on the influence of doping on transistor behavior and performance is given. In particular, recent progress in the understanding of contact doping and channel doping is summarized.

Beam test of a large area silicon drift detector

International Nuclear Information System (INIS)

Castoldi, A.; Chinnici, S.; Gatti, E.; Longoni, A.; Palma, F.; Sampietro, M.; Rehak, P.; Ballocchi, G.; Kemmer, J.; Holl, P.; Cox, P.T.; Giacomelli, P.; Vacchi, A.

1992-01-01

The results from the tests of the first large area (4 x 4 cm 2 ) planar silicon drift detector prototype in a pion beam are reported. The measured position resolution in the drift direction is (σ=40 ± 10)μm

Hybrid planar lightwave circuits for defense and aerospace applications

Science.gov (United States)

Zhang, Hua; Bidnyk, Serge; Yang, Shiquan; Balakrishnan, Ashok; Pearson, Matt; O'Keefe, Sean

2010-04-01

We present innovations in Planar Lightwave Circuits (PLCs) that make them ideally suited for use in advanced defense and aerospace applications. We discuss PLCs that contain no micro-optic components, no moving parts, pose no spark or fire hazard, are extremely small and lightweight, and are capable of transporting and processing a range of optical signals with exceptionally high performance. This PLC platform is designed for on-chip integration of active components such as lasers and detectors, along with transimpedance amplifiers and other electronics. These active components are hybridly integrated with our silica-on-silicon PLCs using fully-automated robotics and image recognition technology. This PLC approach has been successfully applied to the design and fabrication of multi-channel transceivers for aerospace applications. The chips contain hybrid DFB lasers and high-efficiency detectors, each capable of running over 10 Gb/s, with mixed digital and analog traffic multiplexed to a single optical fiber. This highlyintegrated functionality is combined onto a silicon chip smaller than 4 x 10 mm, weighing failures after extreme temperature cycling through a range of > 125 degC, and more than 2,000 hours operating at 95 degC ambient air temperature. We believe that these recent advancements in planar lightwave circuits are poised to revolutionize optical communications and interconnects in the aerospace and defense industries.

Organic Light-Emitting Transistors: Materials, Device Configurations, and Operations.

Science.gov (United States)

Zhang, Congcong; Chen, Penglei; Hu, Wenping

2016-03-09

Organic light-emitting transistors (OLETs) represent an emerging class of organic optoelectronic devices, wherein the electrical switching capability of organic field-effect transistors (OFETs) and the light-generation capability of organic light-emitting diodes (OLEDs) are inherently incorporated in a single device. In contrast to conventional OFETs and OLEDs, the planar device geometry and the versatile multifunctional nature of OLETs not only endow them with numerous technological opportunities in the frontier fields of highly integrated organic electronics, but also render them ideal scientific scaffolds to address the fundamental physical events of organic semiconductors and devices. This review article summarizes the recent advancements on OLETs in light of materials, device configurations, operation conditions, etc. Diverse state-of-the-art protocols, including bulk heterojunction, layered heterojunction and laterally arranged heterojunction structures, as well as asymmetric source-drain electrodes, and innovative dielectric layers, which have been developed for the construction of qualified OLETs and for shedding new and deep light on the working principles of OLETs, are highlighted by addressing representative paradigms. This review intends to provide readers with a deeper understanding of the design of future OLETs. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Neutron reflectivity studies of single lipid bilayers supported on planar substrates

International Nuclear Information System (INIS)

Krueger, S.; Orts, W.J.; Berk, N.F.; Majkrzak, C.F.; Koenig, B.W.

1994-01-01

Neutron reflectivity was used to probe the structure of single phosphatidylcholine (PC) lipid bilayers adsorbed onto a planar silicon surface in an aqueous environment. Fluctuations in the neutron scattering length density profiles perpendicular to the silicon/water interface were determined for different lipids as a function of the hydrocarbon chain length. The lipids were studied in both the gel and liquid crystalline phases by monitoring changes in the specularly-reflected neutron intensity as a function of temperature. Contrast variation of the neutron scattering length density was applied to both the lipid and the solvent. Scattering length density profiles were determined using both model-independent and model-dependent fitting methods. During the reflectivity measurements, a novel experimental set-up was implemented to decrease the incoherent background scattering due to the solvent. Thus, the reflectivity was measured to Q ∼ 0.3 Angstrom -1 , covering up to seven orders of magnitude in reflected intensity, for PC bilayers in D 2 O and silicon-matched (38% D 2 O/62% H 2 O) water. The kinetics of lipid adsorption at the silicon/water interface were also explored by observing changes in the reflectivity at low Q values under silicon-matched water conditions

Diamond deposition using a planar radio frequency inductively coupled plasma

Science.gov (United States)

Bozeman, S. P.; Tucker, D. A.; Stoner, B. R.; Glass, J. T.; Hooke, W. M.

1995-06-01

A planar radio frequency inductively coupled plasma has been used to deposit diamond onto scratched silicon. This plasma source has been developed recently for use in large area semiconductor processing and holds promise as a method for scale up of diamond growth reactors. Deposition occurs in an annulus which coincides with the area of most intense optical emission from the plasma. Well-faceted diamond particles are produced when the substrate is immersed in the plasma.

Planar silver nanowire, carbon nanotube and PEDOT:PSS nanocomposite transparent electrodes

Science.gov (United States)

Stapleton, Andrew J.; Yambem, Soniya D.; Johns, Ashley H.; Afre, Rakesh A.; Ellis, Amanda V.; Shapter, Joe G.; Andersson, Gunther G.; Quinton, Jamie S.; Burn, Paul L.; Meredith, Paul; Lewis, David A.

2015-04-01

Highly conductive, transparent and flexible planar electrodes were fabricated using interwoven silver nanowires and single-walled carbon nanotubes (AgNW:SWCNT) in a PEDOT:PSS matrix via an epoxy transfer method from a silicon template. The planar electrodes achieved a sheet resistance of 6.6 ± 0.0 Ω/□ and an average transmission of 86% between 400 and 800 nm. A high figure of merit of 367 Ω-1 is reported for the electrodes, which is much higher than that measured for indium tin oxide and reported for other AgNW composites. The AgNW:SWCNT:PEDOT:PSS electrode was used to fabricate low temperature (annealing free) devices demonstrating their potential to function with a range of organic semiconducting polymer:fullerene bulk heterojunction blend systems.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

Science.gov (United States)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Improved organic thin-film transistor performance using novel self-assembled monolayers

Science.gov (United States)

McDowell, M.; Hill, I. G.; McDermott, J. E.; Bernasek, S. L.; Schwartz, J.

2006-02-01

Pentacene-based organic thin-film transistors have been fabricated using a phosphonate-linked anthracene self-assembled monolayer as a buffer between the silicon dioxide gate dielectric and the active pentacene channel region. Vast improvements in the subthreshold slope and threshold voltage are observed compared to control devices fabricated without the buffer. Both observations are consistent with a greatly reduced density of charge trapping states at the semiconductor-dielectric interface effected by introduction of the self-assembled monolayer.

A bipolar analog front-end integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT ampersand T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Φ=10 14 protons/cm 2 have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process

Development of a diffuse element matrix in 'planar' technology. A particular application: logical gate with coupled emitter

International Nuclear Information System (INIS)

Rousseau, P.

1968-01-01

In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [fr

Channeling experiments at planar diamond and silicon single crystals with electrons from the Mainz Microtron MAMI

Science.gov (United States)

Backe, H.; Lauth, W.; Tran Thi, T. N.

2018-04-01

Line structures were observed for (110) planar channeling of electrons in a diamond single crystal even at a beam energy of 180 MeV . This observation motivated us to initiate dechanneling length measurements as function of the beam energy since the occupation of quantum states in the channeling potential is expected to enhance the dechanneling length. High energy loss signals, generated as a result of emission of a bremsstrahlung photon with about half the beam energy at channeling of 450 and 855 MeV electrons, were measured as function of the crystal thickness. The analysis required additional assumptions which were extracted from the numerical solution of the Fokker-Planck equation. Preliminary results for diamond are presented. In addition, we reanalyzed dechanneling length measurements at silicon single crystals performed previously at the Mainz Microtron MAMI at beam energies between 195 and 855 MeV from which we conclude that the quality of our experimental data set is not sufficient to derive definite conclusions on the dechanneling length. Our experimental results are below the predictions of the Fokker-Planck equation and somewhat above the results of simulation calculations of A. V. Korol and A. V. Solov'yov et al. on the basis of the MBN Explorer simulation package. We somehow conservatively conclude that the prediction of the asymptotic dechanneling length on the basis of the Fokker-Planck equation represents an upper limit.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Science.gov (United States)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

High total dose proton irradiation effects on silicon NPN rf power transistors

International Nuclear Information System (INIS)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana; Pushpa, N.

2014-01-01

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods

High total dose proton irradiation effects on silicon NPN rf power transistors

Energy Technology Data Exchange (ETDEWEB)

Bharathi, M. N.; Praveen, K. C.; Prakash, A. P. Gnana, E-mail: gnanaprakash@physics.uni-mysore.ac.in [Department of Studies in Physics, University of Mysore, Manasagangotri, Mysore-570006, Karnataka (India); Pushpa, N. [Department of PG Studies in Physics, JSS College, Ooty Road, Mysore-570025, Karnataka (India)

2014-04-24

The effects of 3 MeV proton irradiation on the I-V characteristics of NPN rf power transistors were studied in the dose range of 100 Krad to 100 Mrad. The different electrical characteristics like Gummel, current gain and output characteristics were systematically studied before and after irradiation. The recovery in the I-V characteristics of irradiated NPN BJTs were studied by isochronal and isothermal annealing methods.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors

Science.gov (United States)

2014-01-01

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing. PMID:25276107

Specific and reversible immobilization of histidine-tagged proteins on functionalized silicon nanowires

DEFF Research Database (Denmark)

Liu, Yi-Chi; Rieben, Nathalie Ines; Iversen, Lars

2010-01-01

Silicon nanowire (Si NW)-based field effect transistors (FETs) have shown great potential as biosensors (bioFETs) for ultra-sensitive and label-free detection of biomolecular interactions. Their sensitivity depends not only on the device properties, but also on the function of the biological reco...

Electrical Control of g-Factor in a Few-Hole Silicon Nanowire MOSFET.

Science.gov (United States)

Voisin, B; Maurand, R; Barraud, S; Vinet, M; Jehl, X; Sanquer, M; Renard, J; De Franceschi, S

2016-01-13

Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz.

High-concentration planar microtracking photovoltaic system exceeding 30% efficiency

Science.gov (United States)

Price, Jared S.; Grede, Alex J.; Wang, Baomin; Lipski, Michael V.; Fisher, Brent; Lee, Kyu-Tae; He, Junwen; Brulo, Gregory S.; Ma, Xiaokun; Burroughs, Scott; Rahn, Christopher D.; Nuzzo, Ralph G.; Rogers, John A.; Giebink, Noel C.

2017-08-01

Prospects for concentrating photovoltaic (CPV) power are growing as the market increasingly values high power conversion efficiency to leverage now-dominant balance of system and soft costs. This trend is particularly acute for rooftop photovoltaic power, where delivering the high efficiency of traditional CPV in the form factor of a standard rooftop photovoltaic panel could be transformative. Here, we demonstrate a fully automated planar microtracking CPV system 660× concentration ratio over a 140∘ full field of view. In outdoor testing over the course of two sunny days, the system operates automatically from sunrise to sunset, outperforming a 17%-efficient commercial silicon solar cell by generating >50% more energy per unit area per day in a direct head-to-head competition. These results support the technical feasibility of planar microtracking CPV to deliver a step change in the efficiency of rooftop solar panels at a commercially relevant concentration ratio.

A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

International Nuclear Information System (INIS)

Yuan, Yang; Yong, Gao; Peng-Liang, Gong

2008-01-01

A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Stable organic thin-film transistors

Science.gov (United States)

Jia, Xiaojia; Fuentes-Hernandez, Canek; Wang, Cheng-Yin; Park, Youngrak; Kippelen, Bernard

2018-01-01

Organic thin-film transistors (OTFTs) can be fabricated at moderate temperatures and through cost-effective solution-based processes on a wide range of low-cost flexible and deformable substrates. Although the charge mobility of state-of-the-art OTFTs is superior to that of amorphous silicon and approaches that of amorphous oxide thin-film transistors (TFTs), their operational stability generally remains inferior and a point of concern for their commercial deployment. We report on an exhaustive characterization of OTFTs with an ultrathin bilayer gate dielectric comprising the amorphous fluoropolymer CYTOP and an Al2O3:HfO2 nanolaminate. Threshold voltage shifts measured at room temperature over time periods up to 5.9 × 105 s do not vary monotonically and remain below 0.2 V in microcrystalline OTFTs (μc-OTFTs) with field-effect carrier mobility values up to 1.6 cm2 V−1 s−1. Modeling of these shifts as a function of time with a double stretched-exponential (DSE) function suggests that two compensating aging mechanisms are at play and responsible for this high stability. The measured threshold voltage shifts at temperatures up to 75°C represent at least a one-order-of-magnitude improvement in the operational stability over previous reports, bringing OTFT technologies to a performance level comparable to that reported in the scientific literature for other commercial TFTs technologies. PMID:29340301

Optimization and applications of planar silicon-based photonic crystal devices

DEFF Research Database (Denmark)

Borel, Peter Ingo; Frandsen, Lars Hagedorn; Burgos Leon, Juan

2005-01-01

such as topology optimization. We have also investigated a new device concept for coarse wavelength division de-multiplexing based on planar photonic crystal waveguides. The filtering of the wavelength channels has been realized by shifting the cut-off frequency of the fundamental photonic band gap mode...... in consecutive sections of the waveguide. Preliminary investigations show that this concepts allows coarse de-multiplexing to take place, but that optimization is required in order to reduce cross talk between adjacent channels and to increase the overall transmission. In this work the design, fabrication...

Gamma Irradiation Performance Tests of the Bipolar Junction Transistor (BJT) for Medical Dosimetry Purposes

International Nuclear Information System (INIS)

Nazififard, Mohammad; Suh, Kune Y.; Faghihi, Reyhaneh; Norov, Enkhbat

2014-01-01

Two basic radiation damage mechanisms may affect semiconductor devices which are Displacement damage and Ionization damage. In displacement damage mechanism, the incident radiation displaces silicon atoms from their lattice sites. The resulting defects alter the electronic characteristics of the crystal. In ionization damage mechanism, the absorbed energy by electronic ionization in insulating layers liberates charge carriers, which diffuse or drift to other locations where they are trapped, leading to unintended concentrations of charge and, as a consequence, parasitic fields. Both mechanisms are important in detectors, transistors and integrated circuits. Hardly a system is immune to either one phenomenon and most are sensitive to both. This paper investigates the behavior of Bipolar Junction Transistors (BJTs), exposed to radiation in order to establish their applicability in a radiation environment

Gamma Irradiation Performance Tests of the Bipolar Junction Transistor (BJT) for Medical Dosimetry Purposes

Energy Technology Data Exchange (ETDEWEB)

Nazififard, Mohammad; Suh, Kune Y. [PHILOSOPHIA, Inc., Seoul (Korea, Republic of); Faghihi, Reyhaneh [Kashan Univ. of Medical Science, Kashan (Iran, Islamic Republic of); Norov, Enkhbat [POSTECH, Pohang (Korea, Republic of)

2014-05-15

Two basic radiation damage mechanisms may affect semiconductor devices which are Displacement damage and Ionization damage. In displacement damage mechanism, the incident radiation displaces silicon atoms from their lattice sites. The resulting defects alter the electronic characteristics of the crystal. In ionization damage mechanism, the absorbed energy by electronic ionization in insulating layers liberates charge carriers, which diffuse or drift to other locations where they are trapped, leading to unintended concentrations of charge and, as a consequence, parasitic fields. Both mechanisms are important in detectors, transistors and integrated circuits. Hardly a system is immune to either one phenomenon and most are sensitive to both. This paper investigates the behavior of Bipolar Junction Transistors (BJTs), exposed to radiation in order to establish their applicability in a radiation environment.

Preparation and optical properties of nanocrystalline diamond coatings for infrared planar waveguides

Czech Academy of Sciences Publication Activity Database

Remeš, Zdeněk; Babchenko, Oleg; Varga, Marián; Stuchlík, Jiří; Jirásek, Vít; Prajzler, Václav; Nekvindová, P.; Kromka, Alexander

2016-01-01

Roč. 618, Nov (2016), s. 130-133 ISSN 0040-6090 R&D Projects: GA ČR(CZ) GA14-05053S Grant - others:AV ČR(CZ) MOST-15-04 Program:Bilaterální spolupráce Institutional support: RVO:68378271 Keywords : hydrogenated amorphous silicon * nanocrystalline diamond * planar waveguides Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 1.879, year: 2016

Qualification of a new supplier for silicon particle detectors

Energy Technology Data Exchange (ETDEWEB)

Dragicevic, M., E-mail: marko.dragicevic@cern.ch [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Bartl, U. [Infineon Technologies Austria AG, Villach (Austria); Bergauer, T.; Frühwirth, E. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Gamerith, S.; Hacker, J.; Kröner, F.; Kucher, E.; Moser, J.; Neidhart, T. [Infineon Technologies Austria AG, Villach (Austria); Schulze, H.-J. [Infineon Technologies AG, Munich (Germany); Schustereder, W. [Infineon Technologies Austria AG, Villach (Austria); Treberspurg, W. [Institute of High Energy Physics, Austrian Academy of Sciences, Vienna (Austria); Wübben, T. [Infineon Technologies Austria AG, Villach (Austria)

2013-12-21

Most modern particle physics experiments use silicon based sensors for their tracking systems. These sensors are able to detect particles generated in high energy collisions with high spatial resolution and therefore allow the precise reconstruction of particle tracks. So far only a few vendors are capable of producing silicon strip sensors with the quality needed in particle physics experiments. Together with the European semiconductor manufacturer Infineon Technologies Austria AG the Institute of High Energy Physics of the Austrian Academy of Sciences developed planar silicon strip sensors in p-on-n technology. This paper presents the development, production and results from the electrical characterisation of the first sensors produced by Infineon.

Unijunction transistors

International Nuclear Information System (INIS)

1981-01-01

The electrical characteristics of unijunction transistors can be modified by irradiation with electron beams in excess of 400 KeV and at a dose rate of 10 13 to 10 16 e/cm 2 . Examples are given of the effect of exposing the emitter-base junctions of transistors to such lattice defect causing radiation for a time sufficient to change the valley current of the transistor. (U.K.)

Low-energy ion beam synthesis of Ag endotaxial nanostructures in silicon

Science.gov (United States)

Nagarajappa, Kiran; Guha, Puspendu; Thirumurugan, Arun; Satyam, Parlapalli V.; Bhatta, Umananda M.

2018-06-01

Coherently, embedded metal nanostructures (endotaxial) are known to have potential applications concerning the areas of plasmonics, optoelectronics and thermoelectronics. Incorporating appropriate concentrations of metal atoms into crystalline silicon is critical for these applications. Therefore, choosing proper dose of low-energy ions, instead of depositing thin film as a source of metal atoms, helps in avoiding surplus concentration of metal atoms that diffuses into the silicon crystal. In this work, 30 keV silver negative ions are implanted into a SiO x /Si(100) at two different fluences: 1 × 1015 and 2.5 × 1015 Ag- ions/cm2. Later, the samples are annealed at 700 °C for 1 h in Ar atmosphere. Embedded silver nanostructures have been characterized using planar and cross-sectional TEM (XTEM) analysis. Planar TEM analysis shows the formation of mostly rectangular silver nanostructures following the fourfold symmetry of the substrate. XTEM analysis confirms the formation of prism-shaped silver nanostructures embedded inside crystalline silicon. Endotaxial nature of the embedded crystals has been discussed using selected area electron diffraction analysis.

MIS field effect transistor with barium titanate thin film as a gate insulator

Energy Technology Data Exchange (ETDEWEB)

Firek, P., E-mail: pfirek@elka.pw.edu.p [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Werbowy, A.; Szmidt, J. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland)

2009-11-25

The properties of barium titanate (BaTiO{sub 3}, BT) like, e.g. high dielectric constant and resistivity, allow it to find numerous applications in field of microelectronics. In this work silicon metal insulator semiconductor field effect transistor (MISFET) structures with BaTiO{sub 3} (containing La{sub 2}O{sub 3} admixture) thin films in a role of gate insulator were investigated. The films were produced by means of radio frequency plasma sputtering (RF PS) of sintered BaTiO{sub 3} + La{sub 2}O{sub 3} (2 wt.%) target. In the paper transfer and output current-voltage (I-V), transconductance and output conductance characteristics of obtained transistors are presented and discussed. Basic parameters of these devices like, e.g. threshold voltage (V{sub TH}), are determined and discussed.

Highly featured amorphous silicon nanorod arrays for high-performance lithium-ion batteries

International Nuclear Information System (INIS)

Soleimani-Amiri, Samaneh; Safiabadi Tali, Seied Ali; Azimi, Soheil; Sanaee, Zeinab; Mohajerzadeh, Shamsoddin

2014-01-01

High aspect-ratio vertical structures of amorphous silicon have been realized using hydrogen-assisted low-density plasma reactive ion etching. Amorphous silicon layers with the thicknesses ranging from 0.5 to 10 μm were deposited using radio frequency plasma enhanced chemical vapor deposition technique. Standard photolithography and nanosphere colloidal lithography were employed to realize ultra-small features of the amorphous silicon. The performance of the patterned amorphous silicon structures as a lithium-ion battery electrode was investigated using galvanostatic charge-discharge tests. The patterned structures showed a superior Li-ion battery performance compared to planar amorphous silicon. Such structures are suitable for high current Li-ion battery applications such as electric vehicles

Highly featured amorphous silicon nanorod arrays for high-performance lithium-ion batteries

Energy Technology Data Exchange (ETDEWEB)

Soleimani-Amiri, Samaneh; Safiabadi Tali, Seied Ali; Azimi, Soheil; Sanaee, Zeinab; Mohajerzadeh, Shamsoddin, E-mail: mohajer@ut.ac.ir [Thin Film and Nanoelectronics Lab, Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran 143957131 (Iran, Islamic Republic of)

2014-11-10

High aspect-ratio vertical structures of amorphous silicon have been realized using hydrogen-assisted low-density plasma reactive ion etching. Amorphous silicon layers with the thicknesses ranging from 0.5 to 10 μm were deposited using radio frequency plasma enhanced chemical vapor deposition technique. Standard photolithography and nanosphere colloidal lithography were employed to realize ultra-small features of the amorphous silicon. The performance of the patterned amorphous silicon structures as a lithium-ion battery electrode was investigated using galvanostatic charge-discharge tests. The patterned structures showed a superior Li-ion battery performance compared to planar amorphous silicon. Such structures are suitable for high current Li-ion battery applications such as electric vehicles.

The ATLAS Planar Pixel Sensor R and D project

International Nuclear Information System (INIS)

Beimforde, M.

2011-01-01

Within the R and D project on Planar Pixel Sensor Technology for the ATLAS inner detector upgrade, the use of planar pixel sensors for highest fluences as well as large area silicon detectors is investigated. The main research goals are optimizing the signal size after irradiations, reducing the inactive sensor edges, adjusting the readout electronics to the radiation induced decrease of the signal sizes, and reducing the production costs. Planar n-in-p sensors have been irradiated with neutrons and protons up to fluences of 2x10 16 n eq /cm 2 and 1x10 16 n eq /cm 2 , respectively, to study the collected charge as a function of the irradiation dose received. Furthermore comparisons of irradiated standard 300μm and thin 140μm sensors will be presented showing an increase of signal sizes after irradiation in thin sensors. Tuning studies of the present ATLAS front end electronics show possibilities to decrease the discriminator threshold of the present FE-I3 read out chips to less than 1500 electrons. In the present pixel detector upgrade scenarios a flat stave design for the innermost layers requires reduced inactive areas at the sensor edges to ensure low geometric inefficiencies. Investigations towards achieving slim edges presented here show possibilities to reduce the width of the inactive area to less than 500μm. Furthermore, a brief overview of present simulation activities within the Planar Pixel R and D project is given.

Insitu CCVD grown bilayer graphene transistors for applications in nanoelectronics

International Nuclear Information System (INIS)

Wessely, Pia Juliane; Schwalke, Udo

2014-01-01

We invented a method to fabricate graphene field effect transistors (GFETs) on oxidized silicon wafers in a Silicon CMOS compatible process. The graphene layers needed are grown in situ by means of a transfer-free catalytic chemical vapor deposition (CCVD) process directly on silicon dioxide. Depending on the process parameters the fabrication of single, double or multi-layer graphene FETs (GFETs) is possible. The produced graphene layers have been characterized by SEM, TEM, TEM-lattice analysis as well as Raman-Spectroscopy. Directly after growth, the fabricated GFETs are electrically functional and can be electrically characterized via the catalyst metals which are used as contact electrodes. In contrast to monolayer graphene FETs, the fabricated bilayer graphene FETs (BiLGFETs) exhibit unipolar p-type MOSFET behavior. Furthermore, the on/off current-ratio of 10 4 up to several 10 7 at room temperature of the fabricated BiLGFETs allows their use in digital logic applications [1]. In addition, a stable hysteresis of the GFETs enables their use as memory devices without the need of storage capacitors and therefore very high memory device-densities are possible. The whole fabrication process is fully Si-CMOS compatible, enabling the use of hybrid silicon/graphene electronics.

Recent achievements of the ATLAS upgrade Planar Pixel Sensors R and D project

International Nuclear Information System (INIS)

Casse, G

2014-01-01

The ATLAS upgrade Planar Pixel Sensors (PPS) project aims to prove the suitability of silicon detectors processed with planar technology to equip all layers of the pixel vertex detector proposed for the upgrade of the ATLAS experiment for the future High Luminosity LHC at CERN (HL-LHC). The detectors need to be radiation tolerant to the extreme fluences expected to be received during the experimental lifetime, with optimised geometry for full coverage and high granularity and affordable in term of cost, due to the relatively large area of the upgraded ATLAS detector system. Here several solutions for the detector geometry and results with radiation hard technologies (n-in-n, n-in-p) are discussed

Improved detection limits of bacterial endotoxins using new type of planar interdigital sensors

KAUST Repository

Syaifudin, A. R Mohd

2012-10-01

New types of planar interdigital sensors were fabricated by photolithography and etching techniques on a Silicon/Silicon Dioxide (Si/SiO2) wafer (single side polished). The sensors were then coated with APTES (3-aminopropyltrietoxysilane) a cross linker used to bind Polymyxin B (PmB) molecules on electrodes surface. PmB is an antimicrobial peptide produced by the Gram-positive bacterium-Bacillus which has specific binding properties to Lipopolysaccharide (LPS). This paper will discuss the fabrication process, coating and immobilization procedures and analysis of sensors\\' performance based on Impedance Spectroscopy method. The sensor sensitivity was compared to standard ToxinSensor Chromogenic LAL Endotoxin Assay Kit for verification. © 2012 IEEE.

Effect of proton and electron-irradiation intensity on radiation-induced damages in silicon bioolar transistors

International Nuclear Information System (INIS)

Bannikov, Yu.A.; Gorin, B.M.; Kozhevnikov, V.P.; Mikhnovich, V.V.; Gusev, L.I.

1981-01-01

The increase of radiation-induced damages of bipolar n-p-n transistors 8-12 times with the irradiation intensity decrease by protons from 4.07x1010 to 2.5x107 cm-2 x c-1 has been found experimentally. damages of p-n-p transistors vary in the opposite way - they are decreased 2-3 times with the irradiation intensity decrease within the same limits. the dependence of damages on intansity of proton irradiation occurs at the dose rate by three orders less than it has been observed for electron irradiation. the results obtained are explained by the dependence of radiation defectoformation reactions on charge state of defects with account for the role of formation of disordering regions upon proton irradiation [ru

Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO2 thin films

International Nuclear Information System (INIS)

Yurchuk, Ekaterina

2015-01-01

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO 2 ) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO 2 thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO 2 -based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

Neutron reflectivity studies of single lipid bilayers supported on planar substrates

Energy Technology Data Exchange (ETDEWEB)

Krueger, S.; Orts, W.J.; Berk, N.F.; Majkrzak, C.F. [National Inst. of Standards and Technology, Gaithersburg, MD (United States); Koenig, B.W. [National Inst. of Health, Bethesda, MD (United States)

1994-12-31

Neutron reflectivity was used to probe the structure of single phosphatidylcholine (PC) lipid bilayers adsorbed onto a planar silicon surface in an aqueous environment. Fluctuations in the neutron scattering length density profiles perpendicular to the silicon/water interface were determined for different lipids as a function of the hydrocarbon chain length. The lipids were studied in both the gel and liquid crystalline phases by monitoring changes in the specularly-reflected neutron intensity as a function of temperature. Contrast variation of the neutron scattering length density was applied to both the lipid and the solvent. Scattering length density profiles were determined using both model-independent and model-dependent fitting methods. During the reflectivity measurements, a novel experimental set-up was implemented to decrease the incoherent background scattering due to the solvent. Thus, the reflectivity was measured to Q {approx} 0.3{Angstrom}{sup -1}, covering up to seven orders of magnitude in reflected intensity, for PC bilayers in D{sub 2}O and silicon-matched (38% D{sub 2}O/62% H{sub 2}O) water. The kinetics of lipid adsorption at the silicon/water interface were also explored by observing changes in the reflectivity at low Q values under silicon-matched water conditions.

Ultrafast all-optical arithmetic logic based on hydrogenated amorphous silicon microring resonators

Science.gov (United States)

Gostimirovic, Dusan; Ye, Winnie N.

2016-03-01

For decades, the semiconductor industry has been steadily shrinking transistor sizes to fit more performance into a single silicon-based integrated chip. This technology has become the driving force for advances in education, transportation, and health, among others. However, transistor sizes are quickly approaching their physical limits (channel lengths are now only a few silicon atoms in length), and Moore's law will likely soon be brought to a stand-still despite many unique attempts to keep it going (FinFETs, high-k dielectrics, etc.). This technology must then be pushed further by exploring (almost) entirely new methodologies. Given the explosive growth of optical-based long-haul telecommunications, we look to apply the use of high-speed optics as a substitute to the digital model; where slow, lossy, and noisy metal interconnections act as a major bottleneck to performance. We combine the (nonlinear) optical Kerr effect with a single add-drop microring resonator to perform the fundamental AND-XOR logical operations of a half adder, by all-optical means. This process is also applied to subtraction, higher-order addition, and the realization of an all-optical arithmetic logic unit (ALU). The rings use hydrogenated amorphous silicon as a material with superior nonlinear properties to crystalline silicon, while still maintaining CMOS-compatibility and the many benefits that come with it (low cost, ease of fabrication, etc.). Our method allows for multi-gigabit-per-second data rates while maintaining simplicity and spatial minimalism in design for high-capacity manufacturing potential.

Investigation of silicon sensors for their use as antiproton annihilation detectors

Energy Technology Data Exchange (ETDEWEB)

Pacifico, N., E-mail: nicola.pacifico@cern.ch [University of Bergen, Institute of Physics and Technology, Allégaten 55, 5007 Bergen (Norway); Aghion, S. [Politecnico di Milano, Piazza Leonardo da Vinci 32, 20133 Milano (Italy); Istituto Nazionale di Fisica Nucleare, Sez. di Milano, Via Celoria 16, 20133 Milano (Italy); Ahlén, O. [European Organisation for Nuclear Research, Physics Department, 1211 Geneva 23 (Switzerland); Belov, A.S. [Institute for Nuclear Research of the Russian Academy of Sciences, Moscow 117312 (Russian Federation); Bonomi, G. [University of Brescia, Department of Mechanical and Industrial Engineering, Via Branze 38, 25133 Brescia (Italy); Istituto Nazionale di Fisica Nucleare, Sez. di Pavia, Via Agostino Bassi 6, 27100 Pavia (Italy); Bräunig, P. [Kirchhoff Institute for Physics, Im Neuenheimer Feld 227, 69120 Heidelberg (Germany); Bremer, J. [European Organisation for Nuclear Research, Physics Department, 1211 Geneva 23 (Switzerland); Brusa, R.S. [Department of Physics, University of Trento, via Sommarive 14, 38123 Povo, Trento (Italy); INFN-TIFPA, via Sommarive 14, 38123 Povo, Trento (Italy); Burghart, G. [European Organisation for Nuclear Research, Physics Department, 1211 Geneva 23 (Switzerland); Cabaret, L. [Laboratoire Aimé Cotton, CNRS, Université Paris Sud, ENS Cachan, Bâtiment 505, Campus d' Orsay, 91405 Orsay Cedex (France); Caccia, M. [University of Insubria, Dipartimento di Scienza ed Alta Tecnologia, via Valleggio 11, Como (Italy); Canali, C. [University of Zurich, Physics Institute, Winterthurerstrasse 190, 8057 Zurich (Switzerland); Caravita, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Genova, Via Dodecaneso 33, 16146 Genova (Italy); University of Genoa, Department of Physics, Via Dodecaneso 33, 16146 Genova (Italy); Castelli, F. [University of Milano, Department of Physics, Via Celoria 16, 20133 Milano (Italy); and others

2014-11-21

We present here a new application of silicon sensors aimed at the direct detection of antinucleons annihilations taking place inside the sensor's volume. Such detectors are interesting particularly for the measurement of antimatter properties and will be used as part of the gravity measurement module in the AEg{sup ¯}IS experiment at the CERN Antiproton Decelerator. One of the goals of the AEg{sup ¯}IS experiment is to measure the gravitational acceleration of antihydrogen with 1% precision. Three different silicon sensor geometries have been tested with an antiproton beam to investigate their properties as annihilation detection devices: strip planar, 3D pixels and monolithic pixel planar. In all cases we were successfully detecting annihilations taking place in the sensor and we were able to make a first characterization of the clusters and tracks.

Optimization of planar self-collimating photonic crystals.

Science.gov (United States)

Rumpf, Raymond C; Pazos, Javier J

2013-07-01

Self-collimation in photonic crystals has received a lot of attention in the literature, partly due to recent interest in silicon photonics, yet no performance metrics have been proposed. This paper proposes a figure of merit (FOM) for self-collimation and outlines a methodical approach for calculating it. Performance metrics include bandwidth, angular acceptance, strength, and an overall FOM. Two key contributions of this work include the performance metrics and identifying that the optimum frequency for self-collimation is not at the inflection point. The FOM is used to optimize a planar photonic crystal composed of a square array of cylinders. Conclusions are drawn about how the refractive indices and fill fraction of the lattice impact each of the performance metrics. The optimization is demonstrated by simulating two spatially variant self-collimating photonic crystals, where one has a high FOM and the other has a low FOM. This work gives optical designers tremendous insight into how to design and optimize robust self-collimating photonic crystals, which promises many applications in silicon photonics and integrated optics.

Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

NARCIS (Netherlands)

Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

2011-01-01

In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

International Nuclear Information System (INIS)

Li Lei; Zhou Wanting; Liu Huihua

2012-01-01

In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

Analysis of Co-Tunneling Current in Fullerene Single-Electron Transistor

Science.gov (United States)

KhademHosseini, Vahideh; Dideban, Daryoosh; Ahmadi, MohammadTaghi; Ismail, Razali

2018-05-01

Single-electron transistors (SETs) are nano devices which can be used in low-power electronic systems. They operate based on coulomb blockade effect. This phenomenon controls single-electron tunneling and it switches the current in SET. On the other hand, co-tunneling process increases leakage current, so it reduces main current and reliability of SET. Due to co-tunneling phenomenon, main characteristics of fullerene SET with multiple islands are modelled in this research. Its performance is compared with silicon SET and consequently, research result reports that fullerene SET has lower leakage current and higher reliability than silicon counterpart. Based on the presented model, lower co-tunneling current is achieved by selection of fullerene as SET island material which leads to smaller value of the leakage current. Moreover, island length and the number of islands can affect on co-tunneling and then they tune the current flow in SET.

High-mobility solution-processed copper phthalocyanine-based organic field-effect transistors

Directory of Open Access Journals (Sweden)

Nandu B Chaure, Andrew N Cammidge, Isabelle Chambrier, Michael J Cook, Markys G Cain, Craig E Murphy, Chandana Pal and Asim K Ray

2011-01-01

Full Text Available Solution-processed films of 1,4,8,11,15,18,22,25-octakis(hexyl copper phthalocyanine (CuPc6 were utilized as an active semiconducting layer in the fabrication of organic field-effect transistors (OFETs in the bottom-gate configurations using chemical vapour deposited silicon dioxide (SiO2 as gate dielectrics. The surface treatment of the gate dielectric with a self-assembled monolayer of octadecyltrichlorosilane (OTS resulted in values of 4×10−2 cm2 V−1 s−1 and 106 for saturation mobility and on/off current ratio, respectively. This improvement was accompanied by a shift in the threshold voltage from 3 V for untreated devices to -2 V for OTS treated devices. The trap density at the interface between the gate dielectric and semiconductor decreased by about one order of magnitude after the surface treatment. The transistors with the OTS treated gate dielectrics were more stable over a 30-day period in air than untreated ones.

A miniature microcontroller curve tracing circuit for space flight testing transistors.

Science.gov (United States)

Prokop, N; Greer, L; Krasowski, M; Flatico, J; Spina, D

2015-02-01

This paper describes a novel miniature microcontroller based curve tracing circuit, which was designed to monitor the environmental effects on Silicon Carbide Junction Field Effect Transistor (SiC JFET) device performance, while exposed to the low earth orbit environment onboard the International Space Station (ISS) as a resident experiment on the 7th Materials on the International Space Station Experiment (MISSE7). Specifically, the microcontroller circuit was designed to operate autonomously and was flown on the external structure of the ISS for over a year. This curve tracing circuit is capable of measuring current vs. voltage (I-V) characteristics of transistors and diodes. The circuit is current limited for low current devices and is specifically designed to test high temperature, high drain-to-source resistance SiC JFETs. The results of each I-V data set are transmitted serially to an external telemetered communication interface. This paper discusses the circuit architecture, its design, and presents example results.

Anomalous dose rate effects in gamma irradiated SiGe heterojunction bipolar transistors

International Nuclear Information System (INIS)

Banerjee, G.; Niu, G.; Cressler, J.D.; Clark, S.D.; Palmer, M.J.; Ahlgren, D.C.

1999-01-01

Low dose rate (LDR) cobalt-60 (0.1 rad(Si)/s) gamma irradiated Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) were studied. Comparisons were made with devices irradiated with 300 rad(Si)/s gamma radiation to verify if LDR radiation is a serious radiation hardness assurance (RHA) issue. Almost no LDR degradation was observed in this technology up to 50 krad(Si). The assumption of the presence of two competing mechanisms is justified by experimental results. At low total dose (le20 krad), an anomalous base current decrease was observed which is attributed to self-annealing of deep-level traps to shallower levels. An increase in base current at larger total doses is attributed to radiation induced generation-recombination (G/R) center generation. Experiments on gate-assisted lateral PNP transistors and 2D numerical simulations using MEDICI were used to confirm these assertions

New insights into fully-depleted SOI transistor response during total-dose irradiation

International Nuclear Information System (INIS)

Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.

1999-01-01

In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)

Polarization effects in silicon-clad optical waveguides

Science.gov (United States)

Carson, R. F.; Batchman, T. E.

1984-01-01

By changing the thickness of a semiconductor cladding layer deposited on a planar dielectric waveguide, the TE or TM propagating modes may be selectively attenuated. This polarization effect is due to the periodic coupling between the lossless propagating modes of the dielectric slab waveguide and the lossy modes of the cladding layer. Experimental tests involving silicon claddings show high selectivity for either polarization.

Perhydropolysilazane spin-on dielectrics for inter-layer-dielectric applications of sub-30 nm silicon technology

International Nuclear Information System (INIS)

Kim, Sam-Dong; Ko, Pil-Seok; Park, Kyoung-Seok

2013-01-01

Various material properties of the perhydropolysilazane spin-on dielectric (PHPS SOD) were examined and analyzed in this study as potential inter-layer dielectrics (ILDs) integrated for Si circuits of 30 nm technology or beyond. The spin-coated PHPS (18.5 wt%) layers converted at 650 °C showed comparable but less perfect thermal conversion to silica than the films converted at 1000 °C, however exhibiting excellent gap filling (15 nm gap opening, aspect ratio (AR) of ∼23) and planarization (degree of planarization (DOP) = ∼73% for 800 nm initial step height, cusp angle = ∼16°) sufficient for the Si integration. PHPS SOD layers cured at 650 °C were integrated ILDs in the 0.18 µm Si front-end-of-the-line process, and the estimated hot-carrier reliability of n-channel metal oxide semiconductor transistors (ten years at a drain voltage of 1.68 V) had no significant difference from that of the transistors integrated with the conventional borophosposilicate glass ILDs. A modified contact pre-cleaning scheme using N 2 O plasma treatment also produced uniform and stable contact chain resistances from the SOD ILDs. (paper)

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

International Nuclear Information System (INIS)

Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

2015-01-01

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

Energy Technology Data Exchange (ETDEWEB)

Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

2015-01-05

Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

Electrical characterisation of ferroelectric field effect transistors based on ferroelectric HfO{sub 2} thin films

Energy Technology Data Exchange (ETDEWEB)

Yurchuk, Ekaterina

2015-02-06

Ferroelectric field effect transistor (FeFET) memories based on a new type of ferroelectric material (silicon doped hafnium oxide) were studied within the scope of the present work. Utilisation of silicon doped hafnium oxide (Si:HfO{sub 2}) thin films instead of conventional perovskite ferroelectrics as a functional layer in FeFETs provides compatibility to the CMOS process as well as improved device scalability. The influence of different process parameters on the properties of Si:HfO{sub 2} thin films was analysed in order to gain better insight into the occurrence of ferroelectricity in this system. A subsequent examination of the potential of this material as well as its possible limitations with the respect to the application in non-volatile memories followed. The Si:HfO{sub 2}-based ferroelectric transistors that were fully integrated into the state-of-the-art high-k metal gate CMOS technology were studied in this work for the first time. The memory performance of these devices scaled down to 28 nm gate length was investigated. Special attention was paid to the charge trapping phenomenon shown to significantly affect the device behaviour.

Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project

Science.gov (United States)

Ellinger, Frank; Mikolajick, Thomas; Fettweis, Gerhard; Hentschel, Dieter; Kolodinski, Sabine; Warnecke, Helmut; Reppe, Thomas; Tzschoppe, Christoph; Dohl, Jan; Carta, Corrado; Fritsche, David; Tretter, Gregor; Wiatr, Maciej; Detlef Kronholz, Stefan; Mikalo, Ricardo Pablo; Heinrich, Harald; Paulo, Robert; Wolf, Robert; Hübner, Johannes; Waltsgott, Johannes; Meißner, Klaus; Richter, Robert; Michler, Oliver; Bausinger, Markus; Mehlich, Heiko; Hahmann, Martin; Möller, Henning; Wiemer, Maik; Holland, Hans-Jürgen; Gärtner, Roberto; Schubert, Stefan; Richter, Alexander; Strobel, Axel; Fehske, Albrecht; Cech, Sebastian; Aßmann, Uwe; Pawlak, Andreas; Schröter, Michael; Finger, Wolfgang; Schumann, Stefan; Höppner, Sebastian; Walter, Dennis; Eisenreich, Holger; Schüffny, René

2013-07-01

An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 μm CMOS; solar cell efficiencies above 19% at cars Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

Science.gov (United States)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

Science.gov (United States)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Single-electron transistors fabricated with sidewall spacer patterning

Science.gov (United States)

Park, Byung-Gook; Kim, Dae Hwan; Kim, Kyung Rok; Song, Ki-Whan; Lee, Jong Duk

2003-09-01

We have implemented a sidewall spacer patterning method for novel dual-gate single-electron transistor (DGSET) and metal-oxide-semiconductor-based SET (MOSET) based on the uniform SOI wire, using conventional lithography and processing technology. A 30 nm wide silicon quantum wire is defined by a sidewall spacer patterning method, and depletion gates for two tunnel junctions of the DGSET are formed by the doped polycrystalline silicon sidewall. The fabricated DGSET and MOSET show clear single-electron tunneling phenomena at liquid nitrogen temperature and insensitivity of the Coulomb oscillation period to gate bias conditions. On the basis of the phase control capability of the sidewall depletion gates, we have proposed a complementary self-biasing method, which enables the SET/CMOS hybrid multi-valued logic (MVL) to operate perfectly well at high temperature, where the peak-to-valley current ratio of Coulomb oscillation severely decreases. The suggested scheme is evaluated by SPICE simulation with an analytical DGSET model, and it is confirmed that even DGSETs with a large Si island can be utilized efficiently in the multi-valued logic.

Etched ion tracks in silicon oxide and silicon oxynitride as charge injection or extraction channels for novel electronic structures

International Nuclear Information System (INIS)

Fink, D.; Petrov, A.V.; Hoppe, K.; Fahrner, W.R.; Papaleo, R.M.; Berdinsky, A.S.; Chandra, A.; Chemseddine, A.; Zrineh, A.; Biswas, A.; Faupel, F.; Chadderton, L.T.

2004-01-01

The impact of swift heavy ions onto silicon oxide and silicon oxynitride on silicon creates etchable tracks in these insulators. After their etching and filling-up with highly resistive matter, these nanometric pores can be used as charge extraction or injection paths towards the conducting channel in the underlying silicon. In this way, a novel family of electronic structures has been realized. The basic characteristics of these 'TEMPOS' (=tunable electronic material with pores in oxide on silicon) structures are summarized. Their functionality is determined by the type of insulator, the etch track diameters and lengths, their areal densities, the type of conducting matter embedded therein, and of course by the underlying semiconductor and the contact geometry. Depending on the TEMPOS preparation recipe and working point, the structures may resemble gatable resistors, condensors, diodes, transistors, photocells, or sensors, and they are therefore rather universally applicable in electronics. TEMPOS structures are often sensitive to temperature, light, humidity and organic gases. Also light-emitting TEMPOS structures have been produced. About 37 TEMPOS-based circuits such as thermosensors, photosensors, humidity and alcohol sensors, amplifiers, frequency multipliers, amplitude modulators, oscillators, flip-flops and many others have already been designed and successfully tested. Sometimes TEMPOS-based circuits are more compact than conventional electronics

Design and characterization of integrated front-end transistors in a micro-strip detector technology

International Nuclear Information System (INIS)

Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; U. Pignatel, G.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

2002-01-01

We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures

The Integration and Applications of Organic Thin Film Transistors and Ferroelectric Polymers

Science.gov (United States)

Hsu, Yu-Jen

Organic thin film transistors and ferroelectric polymer (polyvinylidene difluoride) sheet material are integrated to form various sensors for stress/strain, acoustic wave, and Infrared (heat) sensing applications. Different from silicon-based transistors, organic thin film transistors can be fabricated and processed in room-temperature and integrated with a variety of substrates. On the other hand, polyvinylidene difluoride (PVDF) exhibits ferroelectric properties that are highly useful for sensor applications. The wide frequency bandwidth (0.001 Hz to 10 GHz), vast dynamic range (100n to 10M psi), and high elastic compliance (up to 3 percent) make PVDF a more suitable candidate over ceramic piezoelectric materials for thin and flexible sensor applications. However, the low Curie temperature may have impeded its integration with silicon technology. Organic thin film transistors, however, do not have the limitation of processing temperature, hence can serve as transimpedance amplifiers to convert the charge signal generated by PVDF into current signal that are more measurable and less affected by any downstream parasitics. Piezoelectric sensors are useful for a range of applications, but passive arrays suffer from crosstalk and signal attenuation which have complicated the development of array-based PVDF sensors. We have used organic field effect transistors, which are compatible with the low Curie temperature of a flexible piezoelectric polymer,PVDF, to monolithically fabricate transimpedance amplifiers directly on the sensor surface and convert the piezoelectric charge signal into a current signal which can be detected even in the presence of parasitic capacitances. The device couples the voltage generated by the PVDF film under strain into the gate of the organic thin film transistors (OFET) using an arrangement that allows the full piezoelectric voltage to couple to the channel, while also increasing the charge retention time. A bipolar detector is created by

Ultrahigh-frequency surface acoustic wave generation for acoustic charge transport in silicon

NARCIS (Netherlands)

Büyükköse, S.; Vratzov, B.; van der Veen, Johan (CTIT); Santos, P.V.; van der Wiel, Wilfred Gerard

2013-01-01

We demonstrate piezo-electrical generation of ultrahigh-frequency surface acoustic waves on silicon substrates, using high-resolution UV-based nanoimprint lithography, hydrogen silsequioxane planarization, and metal lift-off. Interdigital transducers were fabricated on a ZnO layer sandwiched between

Electrical characteristics of vapor deposited amorphous MoS2 two-terminal structures and back gate thin film transistors with Al, Au, Cu and Ni-Au contacts

International Nuclear Information System (INIS)

Kouvatsos, Dimitrios N.; Papadimitropoulos, Georgios; Spiliotis, Thanassis; Vasilopoulou, Maria; Davazoglou, Dimitrios; Barreca, Davide; Gasparotto, Alberto

2015-01-01

Amorphous molybdenum sulphide (a-MoS 2 ) thin films were deposited at near room temperature on oxidized silicon substrates and were electrically characterized with the use of two-terminal structures and of back-gated thin film transistors utilizing the substrate silicon as gate. Current-voltage characteristics were extracted for various metals used as pads, showing significant current variations attributable to different metal-sulphide interface properties and contact resistances, while the effect of a forming gas anneal was determined. With the use of heavily doped silicon substrates and aluminum backside deposition, thin film transistor (TFT) structures with the a-MoS 2 film as active layer were fabricated and characterized. Transfer characteristics showing a gate field effect, despite a leakage often present, were extracted for these devices, indicating that high mobility devices can be fabricated. SEM and EDXA measurements were also performed in an attempt to clarify issues related to material properties and fabrication procedures, so as to achieve a reliable and optimized a-MoS 2 TFT fabrication process. (copyright 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Thin-film transistors with a channel composed of semiconducting metal oxide nanoparticles deposited from the gas phase

International Nuclear Information System (INIS)

Busch, C.; Schierning, G.; Theissmann, R.; Nedic, A.; Kruis, F. E.; Schmechel, R.

2012-01-01

The fabrication of semiconducting functional layers using low-temperature processes is of high interest for flexible printable electronics applications. Here, the one-step deposition of semiconducting nanoparticles from the gas phase for an active layer within a thin-film transistor is described. Layers of semiconducting nanoparticles with a particle size between 10 and 25 nm were prepared by the use of a simple aerosol deposition system, excluding potentially unwanted technological procedures like substrate heating or the use of solvents. The nanoparticles were deposited directly onto standard thin-film transistor test devices, using thermally grown silicon oxide as gate dielectric. Proof-of-principle experiments were done deploying two different wide-band gap semiconducting oxides, tin oxide, SnO x , and indium oxide, In 2 O 3 . The tin oxide spots prepared from the gas phase were too conducting to be used as channel material in thin-film transistors, most probably due to a high concentration of oxygen defects. Using indium oxide nanoparticles, thin-film transistor devices with significant field effect were obtained. Even though the electron mobility of the investigated devices was only in the range of 10 −6 cm 2V−1s−1 , the operability of this method for the fabrication of transistors was demonstrated. With respect to the possibilities to control the particle size and layer morphology in situ during deposition, improvements are expected.

Research Update: Nanoscale electrochemical transistors in correlated oxides

Directory of Open Access Journals (Sweden)

Teruo Kanki

2017-04-01

Full Text Available Large reversible changes of the electronic transport properties of solid-state oxide materials induced by electrochemical fields have received much attention as a new research avenue in iontronics. In this research update, dramatic transport changes in vanadium dioxide (VO2 nanowires were demonstrated by electric field-induced hydrogenation at room temperature through the nanogaps separated by humid air in a field-effect transistor structure with planar-type gates. This unique structure allowed us to investigate hydrogen intercalation and diffusion behavior in VO2 channels with respect to both time and space. Our results will contribute to further strategic researches to examine fundamental chemical and physical properties of devices and develop iontronic applications, as well as offering new directions to explore emerging functions for sensing, energy, and neuromorphologic devices combining ionic and electronic behaviors in solid-state materials.

Dielectric properties of DNA oligonucleotides on the surface of silicon nanostructures

Energy Technology Data Exchange (ETDEWEB)

Bagraev, N. T., E-mail: bagraev@mail.ioffe.ru [St. Petersburg Polytechnic University (Russian Federation); Chernev, A. L. [Russian Academy of Sciences, St. Petersburg Academic University—Nanotechnology Research and Education Center (Russian Federation); Klyachkin, L. E. [St. Petersburg Polytechnic University (Russian Federation); Malyarenko, A. M. [Russian Academy of Sciences, Ioffe Physical–Technical Institute (Russian Federation); Emel’yanov, A. K.; Dubina, M. V. [Russian Academy of Sciences, St. Petersburg Academic University—Nanotechnology Research and Education Center (Russian Federation)

2016-10-15

Planar silicon nanostructures that are formed as a very narrow silicon quantum well confined by δ barriers heavily doped with boron are used to study the dielectric properties of DNA oligonucleotides deposited onto the surface of the nanostructures. The capacitance characteristics of the silicon nanostructures with oligonucleotides deposited onto their surface are determined by recording the local tunneling current–voltage characteristics by means of scanning tunneling microscopy. The results show the possibility of identifying the local dielectric properties of DNA oligonucleotide segments consisting of repeating G–C pairs. These properties apparently give grounds to correlate the segments with polymer molecules exhibiting the properties of multiferroics.

The effect of fluorine in low thermal budget polysilicon emitters for SiGe heterojunction bipolar transistors

International Nuclear Information System (INIS)

Schiz, F.J.W.

1999-03-01

This thesis investigates the behaviour of fluorine in two types of polysilicon emitter. In the first type the emitter is deposited at 610 deg. C as polycrystalline silicon (p-Si). In the second type the emitter is deposited at 560 deg. C as amorphous silicon (α-Si). The amorphous silicon 1 then regrows to polysilicon during subsequent high temperature anneals. Remarkably different behaviour of fluorine is seen in as-deposited α-Si and as-deposited p-Si emitter bipolar transistors. In the most extreme case, fluorine-implanted as-deposited p-Si devices show a base current increase by a factor of 1.5 and equivalent α-Si devices a base current decrease by a factor of 10.0 compared to unimplanted devices. Cross-section TEM observations are made to study the structure of the polysilicon/silicon interface and SIMS measurements to study the distribution of the fluorine in the polysilicon. The TEM results correlate well with the electrical results and show that fluorine accelerates interfacial oxide breakup. Furthermore, they show that for a given thermal budget, more interfacial oxide breakup and thus more epitaxial regrowth is obtained for transistors with p-Si polysilicon emitters. This results in a lower emitter resistance, for example as low as 12Ωμm 2 for as-deposited p-Si devices. The base current suppression for as-deposited α-Si devices is explained by fluorine passivation of trapping states at the interface. Analysis of the fluorine SIMS profiles suggests that they do not resemble normal diffusion profiles, but are due to fluorine trapped at defects. It is shown that a reciprocal relationship exists between the fluorine dose in the bulk polysilicon layer and the fluorine dose at the interface. In as-deposited α-Si devices, there is more fluorine trapped at defects in the bulk polysilicon layer, so less is available to diffuse to the interface. As a result there is less interfacial oxide breakup and more passivation in the as-deposited α-Si devices. These

Tailoring of silicon crystals for relativistic-particle channeling

International Nuclear Information System (INIS)

Guidi, V.; Antonini, A.; Baricordi, S.; Logallo, F.; Malagu, C.; Milan, E.; Ronzoni, A.; Stefancich, M.; Martinelli, G.; Vomiero, A.

2005-01-01

In the last years, the research on channeling of relativistic particles has progressed considerably. A significant contribution has been provided by the development of techniques for quality improvement of the crystals. In particular, a planar etching of the surfaces of the silicon crystals proved useful to remove the superficial layer, which is a region very rich in imperfections, in turn leading to greater channeling efficiency. Micro-fabrication techniques, borrowed from silicon technology, may also be useful: micro-indentation and deposition of tensile or compressive layers onto silicon samples allow one to impart an even curvature to the samples. In this way, different topologies may be envisaged, such as a bent crystal for deflection of protons and ions or an undulator to force coherent oscillations of positrons and electrons

Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

Directory of Open Access Journals (Sweden)

Jia Ge

2014-01-01

Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

Dual-Mode Gas Sensor Composed of a Silicon Nanoribbon Field Effect Transistor and a Bulk Acoustic Wave Resonator: A Case Study in Freons

Directory of Open Access Journals (Sweden)

Ye Chang

2018-01-01

Full Text Available In this paper, we develop a novel dual-mode gas sensor system which comprises a silicon nanoribbon field effect transistor (Si-NR FET and a film bulk acoustic resonator (FBAR. We investigate their sensing characteristics using polar and nonpolar organic compounds, and demonstrate that polarity has a significant effect on the response of the Si-NR FET sensor, and only a minor effect on the FBAR sensor. In this dual-mode system, qualitative discrimination can be achieved by analyzing polarity with the Si-NR FET and quantitative concentration information can be obtained using a polymer-coated FBAR with a detection limit at the ppm level. The complementary performance of the sensing elements provides higher analytical efficiency. Additionally, a dual mixture of two types of freons (CFC-113 and HCFC-141b is further analyzed with the dual-mode gas sensor. Owing to the small size and complementary metal-oxide semiconductor (CMOS-compatibility of the system, the dual-mode gas sensor shows potential as a portable integrated sensing system for the analysis of gas mixtures in the future.

Fabrication of combinatorial nm-planar electrode array for high throughput evaluation of organic semiconductors

International Nuclear Information System (INIS)

Haemori, M.; Edura, T.; Tsutsui, K.; Itaka, K.; Wada, Y.; Koinuma, H.

2006-01-01

We have fabricated a combinatorial nm-planar electrode array by using photolithography and chemical mechanical polishing processes for high throughput electrical evaluation of organic devices. Sub-nm precision was achieved with respect to the average level difference between each pair of electrodes and a dielectric layer. The insulating property between the electrodes is high enough to measure I-V characteristics of organic semiconductors. Bottom-contact field-effect-transistors (FETs) of pentacene were fabricated on this electrode array by use of molecular beam epitaxy. It was demonstrated that the array could be used as a pre-patterned device substrate for high throughput screening of the electrical properties of organic semiconductors

The LHCb Silicon Inner Tracker

International Nuclear Information System (INIS)

Sievers, P.

2002-01-01

A silicon strip detector has been adopted as baseline technology for the LHCb Inner Tracker system. It consists of nine planar stations covering a cross-shaped area around the LHCb beam pipe. Depending on the final layout of the stations the sensitive surface of the Inner Tracker will be of the order of 14 m 2 . Ladders have to be 22 cm long and the pitch of the sensors should be as large as possible in order to reduce costs of the readout electronics. Major design criteria are material budget, short shaping time and a moderate spatial resolution of about 80 μm. After an introduction on the requirements of the LHCb Inner Tracker we present a description and characterization of silicon prototype sensors. First, laboratory and test beam results are discussed

Fabrication and characteristics of magnetic field sensors based on nano-polysilicon thin-film transistors

International Nuclear Information System (INIS)

Zhao Xiaofeng; Wen Dianzhong; Zhuang Cuicui; Cao Jingya; Wang Zhiqiang

2013-01-01

A magnetic field sensor based on nano-polysilicon thin films transistors (TFTs) with Hall probes is proposed. The magnetic field sensors are fabricated on 〈100〉 orientation high resistivity (ρ > 500 Ω·cm) silicon substrates by using CMOS technology, which adopt nano-polysilicon thin films with thicknesses of 90 nm and heterojunction interfaces between the nano-polysilicon thin films and the high resistivity silicon substrates as the sensing layers. The experimental results show that when V DS = 5.0 V, the magnetic sensitivities of magnetic field sensors based on nano-polysilicon TFTs with length—width ratios of 160 μm/80 μm, 320 μm/80 μm and 480 μm/80 μm are 78 mV/T, 55 mV/T and 34 mV/T, respectively. Under the same conditions, the magnetic sensitivity of the obtained magnetic field sensor is significantly improved in comparison with a Hall magnetic field sensor adopting silicon as the sensing layers. (semiconductor technology)

Various aspects of ionic machining applied to metallic systems in microwave dipolar transistors

International Nuclear Information System (INIS)

Pestie, J.P.; Dumontet, H.; Andrieu, J.P.

1974-01-01

The positive benefit of ion bombardment machining in fabricating bipolar microwave transistors is shown. Ion cleaning, especially for P type silicon with high boron concentration allows reproducible surface resistivities to be reached 10 -6 ohms/cm 2 ) and the spurious resistance of the basis to be minimized. Ionic etching of metallic layers allowed 1μm stepped geometric structures to be realized. The multilayer Ti-Pt-Au system was associated to the finest geometries through a finite number of operations [fr

Copper atomic-scale transistors.

Science.gov (United States)

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Fabrication of 3D Silicon Sensors

Energy Technology Data Exchange (ETDEWEB)

Kok, A.; Hansen, T.E.; Hansen, T.A.; Lietaer, N.; Summanwar, A.; /SINTEF, Oslo; Kenney, C.; Hasi, J.; /SLAC; Da Via, C.; /Manchester U.; Parker, S.I.; /Hawaii U.

2012-06-06

Silicon sensors with a three-dimensional (3-D) architecture, in which the n and p electrodes penetrate through the entire substrate, have many advantages over planar silicon sensors including radiation hardness, fast time response, active edge and dual readout capabilities. The fabrication of 3D sensors is however rather complex. In recent years, there have been worldwide activities on 3D fabrication. SINTEF in collaboration with Stanford Nanofabrication Facility have successfully fabricated the original (single sided double column type) 3D detectors in two prototype runs and the third run is now on-going. This paper reports the status of this fabrication work and the resulted yield. The work of other groups such as the development of double sided 3D detectors is also briefly reported.

Electrically tunable sign of capacitance in planar W-doped vanadium dioxide micro-switches

Directory of Open Access Journals (Sweden)

Mohammed Soltani, Mohamed Chaker and Joelle Margot

2011-01-01

Full Text Available Negative capacitance (NC in a planar W-doped VO2 micro-switch was observed at room temperature in the low-frequency range 1 kHz–10 MHz. The capacitance changed from positive to negative values as the W-doped VO2 active layer switched from semiconducting to metallic state under applied voltage. In addition, a capacitance–voltage hysteresis was observed as the applied voltage was cycled from −35 to 35 V. These observations suggest that NC results from the increase of the electrically induced conductivity in the active layer. This NC phenomenon could be exploited in advanced multifunctional devices including ultrafast switches, field-effect transistors and memcapacitive systems.

Electrical characterization of thin edgeless N-on-p planar pixel sensors for ATLAS upgrades

International Nuclear Information System (INIS)

Bomben, M; Calderini, G; Chauveau, J; Marchiori, G; Bagolini, A; Boscardin, M; Giacomini, G; Zorzi, N; Bosisio, L; Rosa, A La

2014-01-01

In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulation results, a complete overview of the electrical characterization of the produced devices will be given

Development of a miniaturized watch-type dosimeter using a silicon printed-circuit board

International Nuclear Information System (INIS)

Ishikura, Takeshi; Sakamaki, Tsuyoshi; Matsumoto, Iwao; Aoyama, Kei; Nakamura, Takashi

2008-01-01

The electrical personal dosimeter using a silicon semiconductor sensor has the advantage of real time response and alarm function, which can prevent unexpected over-exposure. We tried to develop a miniaturized watch-type dosimeter by incorporating the silicon semiconductor sensor on a silicon printed-circuit board. Thin film resistors, capacitors and wiring patterns are formed on a downsized printed-circuit board. Electronic parts including transistors are mounted by soldering on the silicon printed-circuit board. The dosimeter is further miniaturized by downsizing the amplifier circuit, the semiconductor radiation sensor, the power supply circuit, setting parts and alarm part. The performance of the developed dosimeter was evaluated with respect to the gamma-ray spectra, angular dependence and linearity to dose equivalent rate, and it was confirmed that this dosimeter has the performance equivalent to a commercially available electrical personal dosimeter. (author)

Biomolecule detection using a silicon nanoribbon: accumulation mode versus inversion mode

International Nuclear Information System (INIS)

Elfstroem, Niklas; Linnros, Jan

2008-01-01

Silicon nanoribbons were fabricated using standard optical lithography from silicon on insulator material with top silicon layer thicknesses of 100, 60 and 45 nm. Electrically these work as Schottky-barrier field-effect transistors and, depending on the substrate voltage, electron or hole injection is possible. The current through the nanoribbon is extremely sensitive to charge changes at the oxidized top surface and can be used for biomolecule detection in a liquid. We show that for detection of streptavidin molecules the response is larger in the accumulation mode than in the inversion mode, although not leading to higher detection sensitivity due to increased noise. The effect is attributed to the location in depth of the conducting channel, which for holes is closer to the screened surface charges of the biomolecules. Furthermore, the response increases for decreasing silicon thickness in both the accumulation mode and the inversion mode. The results are verified qualitatively and quantitatively through a two-dimensional simulation model on a cross section along the nanoribbon device

Graphene as a transparent electrode for amorphous silicon-based solar cells

International Nuclear Information System (INIS)

Vaianella, F.; Rosolen, G.; Maes, B.

2015-01-01

The properties of graphene in terms of transparency and conductivity make it an ideal candidate to replace indium tin oxide (ITO) in a transparent conducting electrode. However, graphene is not always as good as ITO for some applications, due to a non-negligible absorption. For amorphous silicon photovoltaics, we have identified a useful case with a graphene-silica front electrode that improves upon ITO. For both electrode technologies, we simulate the weighted absorption in the active layer of planar amorphous silicon-based solar cells with a silver back-reflector. The graphene device shows a significantly increased absorbance compared to ITO-based cells for a large range of silicon thicknesses (34.4% versus 30.9% for a 300 nm thick silicon layer), and this result persists over a wide range of incidence angles

Graphene as a transparent electrode for amorphous silicon-based solar cells

Science.gov (United States)

Vaianella, F.; Rosolen, G.; Maes, B.

2015-06-01

The properties of graphene in terms of transparency and conductivity make it an ideal candidate to replace indium tin oxide (ITO) in a transparent conducting electrode. However, graphene is not always as good as ITO for some applications, due to a non-negligible absorption. For amorphous silicon photovoltaics, we have identified a useful case with a graphene-silica front electrode that improves upon ITO. For both electrode technologies, we simulate the weighted absorption in the active layer of planar amorphous silicon-based solar cells with a silver back-reflector. The graphene device shows a significantly increased absorbance compared to ITO-based cells for a large range of silicon thicknesses (34.4% versus 30.9% for a 300 nm thick silicon layer), and this result persists over a wide range of incidence angles.

Graphene as a transparent electrode for amorphous silicon-based solar cells

Energy Technology Data Exchange (ETDEWEB)

Vaianella, F., E-mail: Fabio.Vaianella@umons.ac.be; Rosolen, G.; Maes, B. [Micro- and Nanophotonic Materials Group, Faculty of Science, University of Mons, 20 place du Parc, B-7000 Mons (Belgium)

2015-06-28

The properties of graphene in terms of transparency and conductivity make it an ideal candidate to replace indium tin oxide (ITO) in a transparent conducting electrode. However, graphene is not always as good as ITO for some applications, due to a non-negligible absorption. For amorphous silicon photovoltaics, we have identified a useful case with a graphene-silica front electrode that improves upon ITO. For both electrode technologies, we simulate the weighted absorption in the active layer of planar amorphous silicon-based solar cells with a silver back-reflector. The graphene device shows a significantly increased absorbance compared to ITO-based cells for a large range of silicon thicknesses (34.4% versus 30.9% for a 300 nm thick silicon layer), and this result persists over a wide range of incidence angles.

Hybridization of active and passive elements for planar photonic components and interconnects

Science.gov (United States)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Isolation and Identification of Post-Transcriptional Gene Silencing-Related Micro-RNAs by Functionalized Silicon Nanowire Field-effect Transistor

Science.gov (United States)

Chen, Kuan-I.; Pan, Chien-Yuan; Li, Keng-Hui; Huang, Ying-Chih; Lu, Chia-Wei; Tang, Chuan-Yi; Su, Ya-Wen; Tseng, Ling-Wei; Tseng, Kun-Chang; Lin, Chi-Yun; Chen, Chii-Dong; Lin, Shih-Shun; Chen, Yit-Tsong

2015-11-01

Many transcribed RNAs are non-coding RNAs, including microRNAs (miRNAs), which bind to complementary sequences on messenger RNAs to regulate the translation efficacy. Therefore, identifying the miRNAs expressed in cells/organisms aids in understanding genetic control in cells/organisms. In this report, we determined the binding of oligonucleotides to a receptor-modified silicon nanowire field-effect transistor (SiNW-FET) by monitoring the changes in conductance of the SiNW-FET. We first modified a SiNW-FET with a DNA probe to directly and selectively detect the complementary miRNA in cell lysates. This SiNW-FET device has 7-fold higher sensitivity than reverse transcription-quantitative polymerase chain reaction in detecting the corresponding miRNA. Next, we anchored viral p19 proteins, which bind the double-strand small RNAs (ds-sRNAs), on the SiNW-FET. By perfusing the device with synthesized ds-sRNAs of different pairing statuses, the dissociation constants revealed that the nucleotides at the 3‧-overhangs and pairings at the terminus are important for the interactions. After perfusing the total RNA mixture extracted from Nicotiana benthamiana across the device, this device could enrich the ds-sRNAs for sequence analysis. Finally, this bionanoelectronic SiNW-FET, which is able to isolate and identify the interacting protein-RNA, adds an additional tool in genomic technology for the future study of direct biomolecular interactions.

Report on the results of research and development under a consignment from NEDO on deca-nano quantum integrating transistor substrate technologies; 1997 nendo sangyo kagaku gijutsu kenkyu kaihatsu jigyo Shin energy Sangyo Gijutsu Sogo Kaihatsu Kiko itaku. Deca-nano ryoshi shusekika soshi kiban gijutsu no kenkyu kaihatsu seika hokokusho

Energy Technology Data Exchange (ETDEWEB)

NONE

1998-03-01

Researches have been conducted on deca-nano quantum integrating transistor substrate technologies, and developments were made on a three-dimensional device simulator which can be used in deca-nano domains, and a circuit simulator to have quantifying function transistors coexist with silicon semiconductor integrated circuits. The researches were intended to develop a simulator capable of analyzing properties of very small silicon and compound semiconductor devices in deca-nano domains. The researches discussed the applicability of conventional simulators, calculated quantum levels in a three-dimensional hetero structure, and resulted in development of an electron wave propagation simulator in optional two-dimensional shapes, a quantum Monte Carlo simulator, and a three-dimensional semiconductor device simulator with quantum correction. On the other hand, in order to estimate characteristics of a hybrid circuit in which single electron transistors coexist with conventional transistors such as CMOS transistors, a single electron hybrid circuit simulator was developed. The development indicated that a CMOS-SET fused memory is promising as a future LSI memory. 22 refs., 116 figs., 3 tabs.

Superconducting transistor

International Nuclear Information System (INIS)

Gray, K.E.

1978-01-01

A three film superconducting tunneling device, analogous to a semiconductor transistor, is presented, including a theoretical description and experimental results showing a current gain of four. Much larger current gains are shown to be feasible. Such a development is particularly interesting because of its novelty and the striking analogies with the semiconductor junction transistor

Modulation-doped β-(Al0.2Ga0.8)2O3/Ga2O3 field-effect transistor

Science.gov (United States)

Krishnamoorthy, Sriram; Xia, Zhanbo; Joishi, Chandan; Zhang, Yuewei; McGlone, Joe; Johnson, Jared; Brenner, Mark; Arehart, Aaron R.; Hwang, Jinwoo; Lodha, Saurabh; Rajan, Siddharth

2017-07-01

Modulation-doped heterostructures are a key enabler for realizing high mobility and better scaling properties for high performance transistors. We report the realization of a modulation-doped two-dimensional electron gas (2DEG) at the β-(Al0.2Ga0.8)2O3/Ga2O3 heterojunction by silicon delta doping. The formation of a 2DEG was confirmed using capacitance voltage measurements. A modulation-doped 2DEG channel was used to realize a modulation-doped field-effect transistor. The demonstration of modulation doping in the β-(Al0.2Ga0.8)2O3/Ga2O3 material system could enable heterojunction devices for high performance electronics.

A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

International Nuclear Information System (INIS)

Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi

2011-01-01

A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.

Tuning the threshold voltage of carbon nanotube transistors by n-type molecular doping for robust and flexible complementary circuits

Science.gov (United States)

Wang, Huiliang; Wei, Peng; Li, Yaoxuan; Han, Jeff; Lee, Hye Ryoung; Naab, Benjamin D.; Liu, Nan; Wang, Chenggong; Adijanto, Eric; Tee, Benjamin C.-K.; Morishita, Satoshi; Li, Qiaochu; Gao, Yongli; Cui, Yi; Bao, Zhenan

2014-01-01

Tuning the threshold voltage of a transistor is crucial for realizing robust digital circuits. For silicon transistors, the threshold voltage can be accurately controlled by doping. However, it remains challenging to tune the threshold voltage of single-wall nanotube (SWNT) thin-film transistors. Here, we report a facile method to controllably n-dope SWNTs using 1H-benzoimidazole derivatives processed via either solution coating or vacuum deposition. The threshold voltages of our polythiophene-sorted SWNT thin-film transistors can be tuned accurately and continuously over a wide range. Photoelectron spectroscopy measurements confirmed that the SWNT Fermi level shifted to the conduction band edge with increasing doping concentration. Using this doping approach, we proceeded to fabricate SWNT complementary inverters by inkjet printing of the dopants. We observed an unprecedented noise margin of 28 V at VDD = 80 V (70% of 1/2VDD) and a gain of 85. Additionally, robust SWNT complementary metal−oxide−semiconductor inverter (noise margin 72% of 1/2VDD) and logic gates with rail-to-rail output voltage swing and subnanowatt power consumption were fabricated onto a highly flexible substrate. PMID:24639537

Timing performances and edge effects of detectors worked from 6-in. silicon slices

International Nuclear Information System (INIS)

Aiello, S.; Anzalone, A.; Cardella, G.; Cavallaro, Sl.; De Filippo, E.; Di Pietro, A.; Femino, S.; Geraci, M.; Giustolisi, F.; Guazzoni, P.; Iacono Manno, M.; Lanzalone, G.; Lanzano, G.; Lo Nigro, S.; Musumarra, A.; Pagano, A.; Papa, M.; Pirrone, S.; Politi, G.; Porto, F.; Rizzo, F.; Sambataro, S.; Sperduto, M.L.; Sutera, C.; Zetta, L.

1997-01-01

Prototypes of new passivated implanted planar silicon detectors, obtained for the first time from 6 in. silicon slices, have been tested. The time and energy resolutions have been studied as a function of the type and energy of the detected particles, in order to test the performances of these detectors for time of flight measurements in the Chimera project. Some problems arising from edge effects observed in double-pad detectors have been solved by using a guard ring. (orig.)

Epitaxy - a new technology for fabrication of advanced silicon radiation detectors

International Nuclear Information System (INIS)

Kemmer, J.; Wiest, F.; Pahlke, A.; Boslau, O.; Goldstrass, P.; Eggert, T.; Schindler, M.; Eisele, I.

2005-01-01

Twenty five years after the introduction of the planar process to the fabrication of silicon radiation detectors a new technology, which replaces the ion implantation doping by silicon epitaxy is presented. The power of this new technique is demonstrated by fabrication of silicon drift detectors (SDDs), whereby both the n-type and p-type implants are replaced by n-type and p-type epi-layers. The very first SDDs ever produced with this technique show energy resolutions of 150 eV for 55 Fe at -35 deg C. The area of the detectors is 10 mm 2 and the thickness 300 μm. The high potential of epitaxy for future detectors with integrated complex electronics is described

High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

KAUST Repository

Sevilla, Galo T.

2016-02-29

Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

Accelerating the life of transistors

International Nuclear Information System (INIS)

Qi Haochun; Lü Changzhi; Zhang Xiaoling; Xie Xuesong

2013-01-01

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object, the test of accelerating life is conducted in constant temperature and humidity, and then the data are statistically analyzed with software developed by ourselves. According to degradations of such sensitive parameters as the reverse leakage current of transistors, the lifetime order of transistors is about more than 10 4 at 100 °C and 100% relative humidity (RH) conditions. By corrosion fracture of transistor outer leads and other failure modes, with the failure truncated testing, the average lifetime rank of transistors in different distributions is extrapolated about 10 3 . Failure mechanism analyses of degradation of electrical parameters, outer lead fracture and other reasons that affect transistor lifetime are conducted. The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation. (semiconductor devices)

Effects of neutral particle beam on nano-crystalline silicon thin films, with application to thin film transistor backplane for flexible active matrix organic light emitting diodes

International Nuclear Information System (INIS)

Jang, Jin Nyoung; Song, Byoung Chul; Lee, Dong Hyeok; Yoo, Suk Jae; Lee, Bonju; Hong, MunPyo

2011-01-01

A novel deposition process for nano-crystalline silicon (nc-Si) thin films was developed using neutral beam assisted chemical vapor deposition (NBaCVD) technology for the application of the thin film transistor (TFT) backplane of flexible active matrix organic light emitting diode (AMOLED). During the formation of a nc-Si thin film, the energetic particles enhance nano-sized crystalline rather microcrystalline Si in thin films. Neutral Particle Beam (NPB) affects the crystallinity in two ways: (1) NPB energy enhances nano-crystallinity through kinetic energy transfer and chemical annealing, and (2) heavier NPB (such as Ar) induces damage and amorphization through energetic particle impinging. Nc-Si thin film properties effectively can be changed by the reflector bias. As increase of NPB energy limits growing the crystalline, the performance of TFT supports this NPB behavior. The results of nc-Si TFT by NBaCVD demonstrate the technical potentials of neutral beam based processes for achieving high stability and reduced leakage in TFT backplanes for AMOLEDs.

Thermal Molding of Organic Thin-Film Transistor Arrays on Curved Surfaces.

Science.gov (United States)

Sakai, Masatoshi; Watanabe, Kento; Ishimine, Hiroto; Okada, Yugo; Yamauchi, Hiroshi; Sadamitsu, Yuichi; Kudo, Kazuhiro

2017-12-01

In this work, a thermal molding technique is proposed for the fabrication of plastic electronics on curved surfaces, enabling the preparation of plastic films with freely designed shapes. The induced strain distribution observed in poly(ethylene naphthalate) films when planar sheets were deformed into hemispherical surfaces clearly indicated that natural thermal contraction played an important role in the formation of the curved surface. A fingertip-shaped organic thin-film transistor array molded from a real human finger was fabricated, and slight deformation induced by touching an object was detected from the drain current response. This type of device will lead to the development of robot fingers equipped with a sensitive tactile sense for precision work such as palpation or surgery.

Construction and evaluation of photovoltaic power generation and power storage system using SiC field-effect transistor inverter

International Nuclear Information System (INIS)

Oku, Takeo; Matsumoto, Taisuke; Ohishi, Yuya; Hiramatsu, Koichi; Yasuda, Masashi; Shimono, Akio; Takeda, Yoshikazu; Murozono, Mikio

2016-01-01

A power storage system using spherical silicon (Si) solar cells, maximum power point tracking charge controller, lithium-ion battery and a direct current-alternating current (DC-AC) inverter was constructed. Performance evaluation of the DC-AC inverter was carried out, and the DC-AC conversion efficiencies of the SiC field-effect transistor (FET) inverter was improved compared with those of the ordinary Si-FET based inverter

Construction and evaluation of photovoltaic power generation and power storage system using SiC field-effect transistor inverter

Energy Technology Data Exchange (ETDEWEB)

Oku, Takeo, E-mail: oku@mat.usp.ac.jp; Matsumoto, Taisuke; Ohishi, Yuya [Department of Materials Science, The University of Shiga Prefecture, 2500 Hassaka, Hikone, Shiga 522-8533 (Japan); Hiramatsu, Koichi; Yasuda, Masashi [Collaborative Research Center, The University of Shiga Prefecture, 2500 Hassaka, Hikone, Shiga 522-8533 (Japan); Shimono, Akio; Takeda, Yoshikazu [Kyoshin Electric Co. Ltd., 18, Goshonouchi-Nishimachi, Shichijo, Shimogyou-ku, Kyoto 600-8865 (Japan); Murozono, Mikio [Clean Venture 21 Co., 38 Ishihara Douno-Ushirocho, Kissyouin, Minami-ku, Kyoto 601-8355 (Japan)

2016-02-01

A power storage system using spherical silicon (Si) solar cells, maximum power point tracking charge controller, lithium-ion battery and a direct current-alternating current (DC-AC) inverter was constructed. Performance evaluation of the DC-AC inverter was carried out, and the DC-AC conversion efficiencies of the SiC field-effect transistor (FET) inverter was improved compared with those of the ordinary Si-FET based inverter.

Développement de résonateurs électromécaniques en technologie Silicon On Nothing, à détection capacitive et amplifiée par transistor MOS, en vue d'une co-intégration permettant d'adresser une application de référence de temps

OpenAIRE

Durand , Cédric

2009-01-01

Due to good performances, small size, or either integration possibilities very close to transistors, electromechanical resonators offer a strong potential for quartz replacement in time reference applications.In this context, we propose to develop electromechanical resonators in a perspective of a front-end integration, for the realization of integrated oscillators. The fabricated demonstrators are based on the Silicon On Nothing CMOS technology, under R&D at STMicroelectronics. Due to the sm...

A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

Science.gov (United States)

2015-07-21

Hybrid Biosensor Jieun Lee1,2, Jaeman Jang1, Bongsik Choi1, Jinsu Yoon1, Jee-Yeon Kim3, Yang-Kyu Choi3, Dong Myong Kim1, Dae Hwan Kim1 & Sung-Jin Choi1...This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response...of field-effect-transistor (FET)-based biosensors . The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential

1980, a revolution in silicon detectors, from energy spectrometer to radiation imager: Some technical and historical details

International Nuclear Information System (INIS)

Heijne, Erik H.M.

2008-01-01

Silicon nuclear particle detectors were introduced just 50 years ago, after single crystal manufacturing was mastered. A major change took place around 1980 when the 'planar' Metal Oxide Semiconductor (MOS) technology developed in microelectronics was systematically applied also in detector construction. With the simultaneous introduction of matched readout chips this eventually would lead to pixelized matrix detectors that function as radiation imaging devices. The critical contributions to this revolution by Josef Kemmer and Paul Burger are described. Performance of the segmented planar technology detectors improved significantly in comparison with the earlier spectrometric diodes. With efficient industrial support the use of silicon detectors in many new applications has become possible and detector systems with a sensitive area of several tens to >100m 2 have been constructed recently

Influence of the narrow {111} planes on axial and planar ion channeling.

Science.gov (United States)

Motapothula, M; Dang, Z Y; Venkatesan, T; Breese, M B H; Rana, M A; Osman, A

2012-05-11

We report channeling patterns where clearly resolved effects of the narrow {111} planes are observed in axial and planar alignments for 2 MeV protons passing through a 55 nm [001] silicon membrane. At certain axes, such as and , the offset in atomic rows forming the narrow {111} planes results in shielding from the large potential at the wide {111} planes, producing a region of shallow, asymmetric potential from which axial channeling patterns have no plane of symmetry. At small tilts from such axes, different behavior is observed from the wide and narrow {111} planes. At planar alignment, distinctive channeling effects due to the narrow planes are observed. As a consequence of the shallow potential well at the narrow planes, incident protons suffer dechanneled trajectories which are excluded from channeling within the wide planes, resulting in an anomalously large scattered beam at {111} alignment.

Silicon Carbide Junction Field Effect Transistor Digital Logic Gates Demonstrated at 600 deg. C

Science.gov (United States)

Neudeck, Philip G.

1998-01-01

The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.

High-performance vertical organic transistors.

Science.gov (United States)

Kleemann, Hans; Günther, Alrun A; Leo, Karl; Lüssem, Björn

2013-11-11

Vertical organic thin-film transistors (VOTFTs) are promising devices to overcome the transconductance and cut-off frequency restrictions of horizontal organic thin-film transistors. The basic physical mechanisms of VOTFT operation, however, are not well understood and VOTFTs often require complex patterning techniques using self-assembly processes which impedes a future large-area production. In this contribution, high-performance vertical organic transistors comprising pentacene for p-type operation and C60 for n-type operation are presented. The static current-voltage behavior as well as the fundamental scaling laws of such transistors are studied, disclosing a remarkable transistor operation with a behavior limited by injection of charge carriers. The transistors are manufactured by photolithography, in contrast to other VOTFT concepts using self-assembled source electrodes. Fluorinated photoresist and solvent compounds allow for photolithographical patterning directly and strongly onto the organic materials, simplifying the fabrication protocol and making VOTFTs a prospective candidate for future high-performance applications of organic transistors. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Self-aligned BCB planarization method for high-frequency signal injection in a VCSEL with an integrated modulator

Science.gov (United States)

Marigo-Lombart, Ludovic; Doucet, Jean-Baptiste; Lecestre, Aurélie; Reig, Benjamin; Rousset, Bernard; Thienpont, Hugo; Panajotov, Krassimir; Almuneau, Guilhem

2016-04-01

The huge increase of datacom capacities requires lasers sources with more and more bandwidth performances. Vertical-Cavity Surface-Emitting Lasers (VCSEL) in direct modulation is a good candidate, already widely used for short communication links such as in datacenters. Recently several different approaches have been proposed to further extend the direct modulation bandwidth of these devices, by improving the VCSEL structure, or by combining the VCSEL with another high speed element such as lateral slow light modulator or transistor/laser based structure (TVCSEL). We propose to increase the modulation bandwidth by vertically integrating a continuous-wave VCSEL with a high-speed electro-modulator. This vertical structure implies multiple electrodes with sufficiently good electrical separation between the different input electrical signals. This high frequency modulation requires both good electrical insulation between metal electrodes and an optimized design of the coplanar lines. BenzoCyclobutene (BCB) thanks to its low dielectric constant, low losses, low moisture absorption and good thermal stability, is often used as insulating layer. Also, BCB planarization offers the advantages of simpler and more reliable technological process flow in such integrated VCSEL/modulator structures with important reliefs. As described by Burdeaux et al. a degree of planarization (DOP) of about 95% can be achieved by simple spin coating whatever the device thickness. In most of the cases, the BCB planarization process requires an additional photolithography step in order to open an access to the mesa surface, thus involving a tight mask alignment and resulting in a degraded planarization. In this paper, we propose a self-aligned process with improved BCB planarization by combining a hot isostatic pressing derived from nanoimprint techniques with a dry plasma etching step.

Simulation of thermo-mechanical effect in bulk-silicon FinFETs

OpenAIRE

Burenkov, Alex; Lorenz, Jürgen

2016-01-01

The thermo-mechanical effect in bulk-silicon FinFETs of the 14 nm CMOS technology node is studied by means of numerical simulation. The electrical performance of such devices is significantly enhanced by the intentional introduction of mechanical stress during the device processing. The thermo-mechanical effect modifies the mechanical stress distribution in active regions of the transistors when they are heated. This can lead to a modification of the electrical performance. Numerical simulati...

GaN-on-Silicon - Present capabilities and future directions

Science.gov (United States)

Boles, Timothy

2018-02-01

Gallium Nitride, in the form of epitaxial HEMT transistors on various substrate materials, is the newest and most promising semiconductor technology for high performance devices in the RF, microwave, and mmW arenas. This is particularly true for GaN-on-Silicon based devices and MMIC's which enable both state-of-the-art high frequency functionality and the ability to scale production into large wafer diameter CMOS foundries. The design and development of GaN-on-Silicon structures and devices will be presented beginning with the basic material parameters, growth of the required epitaxial construction, and leading to the fundamental operational theory of high frequency, high power HEMTs. In this discussion comparisons will be made with alternative substrate materials with emphasis on contrasting the inherent advantages of a silicon based system. Theory of operation of microwave and mmW high power HEMT devices will be presented with special emphasis on fundamental limitations of device performance including inherent frequency limiting transit time analysis, required impedance transformations, internal and external parasitic reactance, thermal impedance optimization, and challenges improved by full integration into monolithic MMICs. Lastly, future directions for implementing GaN-on-Silicon into mainstream CMOS silicon semiconductor technologies will be discussed.

Skin electronics from scalable fabrication of an intrinsically stretchable transistor array.

Science.gov (United States)