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Sample records for pixel front-end prototype

  1. Pixel front-end development in 65 nm CMOS technology

    CERN Document Server

    Havránek, M; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.

  2. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  3. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  4. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  5. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  6. Data acquisition at the front-end of the Mu3e pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

    2016-07-01

    The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

  7. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

    Science.gov (United States)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-02-01

    This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

  8. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  9. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  10. HDI flexible front-end hybrid prototype for the PS module of the CMS tracker upgrade

    Science.gov (United States)

    Kovacs, M.; Blanchot, G.; Gadek, T.; Honma, A.; Koliatos, A.

    2017-02-01

    The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with high-density interconnection flexible circuits that are wire bonded to silicon strip and pixel-strip sensors. The Front-End hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit technology and the parameters of the hybrids. This paper presents the Pixel-Strip (PS) mock-up hybrid in terms of testing, interconnection, fold-over, thermal properties and layout feasibility. Plans for circuit testing at operating temperature (-30o) are also presented.

  11. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  12. A Bulk Control Circuit for Open-Loop Front-Ends for X-Ray Pixel Detectors

    Science.gov (United States)

    Grande, A.; Fiorini, C.; Fischer, P.; Porro, M.

    2017-06-01

    In this paper, we present a bulk control circuit to correct the chip-to-chip process variations of an open-loop nonlinear front-end (FE) for X-ray pixel detectors. Our study was carried out in the framework of the Depfet sensor with signal compression detector development for the European X-ray free electron laser. The presented circuit is capable to stabilize the FE response in presence of threshold voltage variations, acting on the bulk voltages of the FE's transistors and exploiting the body effect. The control circuit does not affect the noise performances of the FE. The working principle of the proposed control circuit and the first experimental results obtained with a first prototype realized in the 130-nm IBM technology are presented in this work.

  13. Irradiation Tests of the Pixel Front-End Readout Electronics for the ALICE Experiment at LHC

    CERN Document Server

    Riggi, F; Barbera, R; Palmeri, A; Pappalardo, G S; Di Liberto, S; Meddi, F; Cavagnoli, A; Morando, M; Scarlassara, F; Segato, G F; Soramel, F; Vannucci, Luigi

    2002-01-01

    The problem of radiation damage for the electronics of the pixel detectors in the Inner Tracking System of the ALICE experiment is discussed. Simulations allowed to estimate the cumulated doses andparticle fluences during a ten year operational period. Several irradiation tests have been carried out on the various prototypes of the readout chips. The results obtained so far point out that the recent prototypes will retain their functionality up to doses and neutron fluences well above those expected in ALICE.

  14. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  15. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  16. Study of the performance of ATLAS prototype detectors using analogue LHC front-end electronics

    CERN Document Server

    Riedler, P; Kaplon, J; Weilhammer, Peter

    2002-01-01

    The silicon strip detectors in the ATLAS experiment at LHC will be exposed to very high hadron fluences. In order to study the radiation damage effects ATLAS prototype detectors and small test detectors were irradiated to a fluence of 3 * 10/sup 14/ 24 GeV protons/cm/sup 2/. After irradiation, the detectors were annealed at 25 degrees C to simulate the damage foreseen after 10 years of ATLAS operation. The detectors were then connected to the SCT32A analogue front-end chips and tested with a /sup 106/Ru source. The performance of the irradiated detectors was compared to non-irradiated detectors from the same batch. The charge collection efficiency is discussed taking into account the electronic response of the readout chip and the ballistic deficit. (10 refs).

  17. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  18. Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

    Science.gov (United States)

    Monteil, E.; Demaria, N.; Pacher, L.; Rivetti, A.; Da Rocha Rolo, M.; Rotondo, F.; Leng, C.

    2016-03-01

    The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

  19. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  20. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  1. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using...

  2. Evaluation of 65nm technology for CLIC pixel front-end

    CERN Document Server

    Valerio, P; Ballabriga, R; Campbell, M; Llopart, X

    2011-01-01

    The CLIC vertex detector design requires a high single point resolution (~ 3 μm) and a precise time stamp (≤ 10 ns). In order to achieve this spatial resolution, small pixels (in the order of 20 μm pitch) must be used, together with the measurement of the charge deposition of neighbouring channels. Designing such small pixels requires the use of a deep downscaled CMOS technology. This note describes the design and characterisation of suitable building blocks implemented in a commercial 65 nm process. The characterisation included an evaluation of the radiation hardness of the blocks.

  3. A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

    Science.gov (United States)

    Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

    2017-06-01

    A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

  4. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  5. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  6. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  7. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  8. SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    Science.gov (United States)

    Bouchel, M.; Callier, S.; Dulucq, F.; Fleury, J.; Jaeger, J.-J.; de La Taille, C.; Martin-Chassard, G.; Raux, L.

    2011-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC (International Linear Collider) prototype of hadronic calorimeter using Silicon photomultiplier (SiPM) or Multi-Pixel Photon Counters (MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2010. SPIROC is an evolution of FLC-SiPM used for the ILC Analogue HCAL physics prototype. The first prototype of SPIROC was submitted in June 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 μm SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, dual gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2,000 photoelectron and the time with a 100 ps accurate Time-to-digital Converter (TDC). An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson Analogue-to-digital Converter (ADC) has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 Kbytes RAM. A very complex digital part has been integrated to manage all these features and to transfer the data to the DAQ which is described in Dulucq et al. After an exhaustive description, the extensive measurement results of this new front-end chip are presented.

  9. Prototype specification of antenna and radio front-end schemes for PAN devices

    DEFF Research Database (Denmark)

    Wang, Yu; Nguyen, Hung Tuan; johansson, Anders

    2007-01-01

    This document provides antenna system specifications for the MAGNET Beyond prototype. Requirements on selecting antenna elements and diversity antenna systems are presented. A number of antenna elements and diversity systems suitable for MAGNET systems are specified. Presented antennas can be imp...

  10. How Experiments in the Fuzzy Front End Using Prototyping Generates New Options

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2017-01-01

    , the analysis demonstrates that prototyping can be considered as a punctuation device, as it offers those involved the option of opting out of ongoing processes, routines and engage in playful behavior by allowing for a freer experimentation with materials, processes, methods to challenge existing knowledge...... and explore potential solutions. In science, by contrast, experimentation generally is carried out to support, refute, or validate a hypothesis, in other words it seems to be associated with testing options rather than creating them....

  11. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter

    CERN Document Server

    Dressnandt, N; Rescia, S; Vernon, E

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at the Large Hadron Collider upgrade (sLHC). IBM’s 8WL 130nm SiGe process was chosen for it’s radiation tolerance, low noise bipolar NPN devices, wide voltage rand and potential use in other sLHC detector subsystems. Although the requirements for the final design can not be set at this time, the prototype was designed to accommodate a 16 bit dynamic range. This was accomplished by using a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of the Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier which eases the input voltage noise requirement on the shaper. Each shaper stage is designed as a cascaded differential operational amplifier doublet with a common...

  12. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  13. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  14. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  15. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii

    2013-07-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

  16. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  17. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    Science.gov (United States)

    Li, H. S.; Jiang, X. S.; Liu, G.; Wang, N.; Sheng, H. Y.; Zhuang, B. A.; Zhao, J. W.

    2012-03-01

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  18. Small-Scale Readout Systems Prototype for the STAR PIXEL Detector

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal A.; Besson, Auguste; Colledani, Claude; Dorokhov, Andrei; Dulinski, Wojciech; Greiner, Leo C.; Himmi, Abdelkader; Hu, Christine; Matis, Howard S.; Ritter, Hans Georg; Rose, Andrew; Shabetai, Alexandre; Stezelberger, Thorsten; Sun, Xiangming; Thomas, Jim H.; Valin, Isabelle; Vu, Chinh Q.; Wieman, Howard H.; Winter, Marc

    2008-10-01

    A prototype readout system for the STAR PIXEL detector in the Heavy Flavor Tracker (HFT) vertex detector upgrade is presented. The PIXEL detector is a Monolithic Active Pixel Sensor (MAPS) based silicon pixel vertex detector fabricated in a commercial CMOS process that integrates the detector and front-end electronics layers in one silicon die. Two generations ofMAPS prototypes designed specifically for the PIXEL are discussed. We have constructed a prototype telescope system consisting of three small MAPS sensors arranged in three parallel and coaxial planes with a readout system based on the readout architecture for PIXEL. This proposed readout architecture is simple and scales to the size required to readout the final detector. The real-time hit finding algorithm necessary for data rate reduction in the 400 million pixel detector is described, and aspects of the PIXEL system integration into the existing STAR framework are addressed. The complete system has been recently tested and shown to be fully functional.

  19. Total Ionising Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00439451

    2016-01-01

    The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the LV current, produced by the FE-I4 chip, was observed. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations. This report presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

  20. Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

    Science.gov (United States)

    Kleczek, Rafal

    2017-01-01

    The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

  1. Performance of a resistive plate chamber equipped with a new prototype of amplified front-end electronics

    CERN Document Server

    Marchisone, Massimiliano

    2016-01-01

    ALICE is the LHC experiment dedicated to the study of heavy-ion collisions. At forward rapidity a muon spectrometer detects muons from low mass mesons, quarkonia, open heavy-flavor hadrons as well as weak bosons. A muon selection based on transverse momentum is made by a trigger system composed of 72 resistive plate chambers (RPCs). For the LHC Run 1 and the ongoing Run 2 the RPCs have been equipped with a non-amplified FEE called ADULT. However, in view of an increase in luminosity expected for Run 3 (2021-2023) the possibility to use an amplified FEE has been explored in order to improve the counting rate limitation and to prevent the aging of the detector, by reducing the charge per hit. A prototype of this new electronics (FEERIC) has been developed and tested first with cosmic rays before equipping one RPC in the ALICE cavern with it. In this talk the most important performance indicators - efficiency, dark current, dark rate, cluster size and total charge - of an RPC equipped with this new FEE will be r...

  2. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  3. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2007-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  4. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  5. The next generation CBM MVD front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Wiebusch, Michael; Michel, Jan; Klaus, Philipp; Stroth, Joachim [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    The Micro Vertex Detector (MVD) for the CBM experiment is a highly granular precision tracking device. Due to the ambitious requirements regarding spatial resolution, radiation hardness, read-out speed and material budget, monolithic active pixel sensors (MAPS) are the most suited detector technology for this purpose. A full read-out chain for these sensors was designed and prototyped, comprising a multi-purpose FPGA platform and specialized front-end electronics. During the last year an updated version of the front-end electronics was produced and successfully commissioned. The current front-end electronics incorporate additional configuration and monitoring capabilities which shall be used to optimize the concept of biasing and routing critical analog signals to the sensor. Tests regarding these issues are ongoing. Recent efforts aim at building a quarter of an MVD station with more than a dozen individual MAPS sensors. This requires the adaption of the front-end electronics to the spacial constraints of the set-up. Also the schematics have to be streamlined based on the insights from the abovementioned tests. This contribution presents the outcomes of the adaption and optimization procedures.

  6. Design of the front end electronics for the infrared camera of JEM-EUSO, and manufacturing and verification of the prototype model

    Science.gov (United States)

    Maroto, Oscar; Diez-Merino, Laura; Carbonell, Jordi; Tomàs, Albert; Reyes, Marcos; Joven-Alvarez, Enrique; Martín, Yolanda; Morales de los Ríos, J. A.; del Peral, Luis; Rodríguez-Frías, M. D.

    2014-07-01

    The Japanese Experiment Module (JEM) Extreme Universe Space Observatory (EUSO) will be launched and attached to the Japanese module of the International Space Station (ISS). Its aim is to observe UV photon tracks produced by ultra-high energy cosmic rays developing in the atmosphere and producing extensive air showers. The key element of the instrument is a very wide-field, very fast, large-lense telescope that can detect extreme energy particles with energy above 1019 eV. The Atmospheric Monitoring System (AMS), comprising, among others, the Infrared Camera (IRCAM), which is the Spanish contribution, plays a fundamental role in the understanding of the atmospheric conditions in the Field of View (FoV) of the telescope. It is used to detect the temperature of clouds and to obtain the cloud coverage and cloud top altitude during the observation period of the JEM-EUSO main instrument. SENER is responsible for the preliminary design of the Front End Electronics (FEE) of the Infrared Camera, based on an uncooled microbolometer, and the manufacturing and verification of the prototype model. This paper describes the flight design drivers and key factors to achieve the target features, namely, detector biasing with electrical noise better than 100μV from 1Hz to 10MHz, temperature control of the microbolometer, from 10°C to 40°C with stability better than 10mK over 4.8hours, low noise high bandwidth amplifier adaptation of the microbolometer output to differential input before analog to digital conversion, housekeeping generation, microbolometer control, and image accumulation for noise reduction. It also shows the modifications implemented in the FEE prototype design to perform a trade-off of different technologies, such as the convenience of using linear or switched regulation for the temperature control, the possibility to check the camera performances when both microbolometer and analog electronics are moved further away from the power and digital electronics, and

  7. A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

    Science.gov (United States)

    Monteil, E.; Pacher, L.; Paternò, A.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.

    2016-12-01

    This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

  8. A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

    Science.gov (United States)

    Paternò, A.; Pacher, L.; Monteil, E.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.

    2017-02-01

    This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

  9. New Front End Technology

    Energy Technology Data Exchange (ETDEWEB)

    Pennington, D; Jovanovic, I; Comaskey, B J

    2001-02-01

    The next generation of Petawatt class lasers will require the development of new laser technology. Optical parametric chirped pulse amplification (OPCPA) holds a potential to increase the peak power level to >10 PW with existing grating technology through ultrashort pulses. Furthermore, by utilizing a new type of front-end system based on optical parametric amplification, pulses can be produced with substantially higher contrast than with Ti:sapphire regenerative amplifier technology. We performed extensive study of OPCPA using a single crystal-based OPA. We developed a replacement for Ti:sapphire regenerative amplifier for high peak power lasers based on OPCPA, with an output of 30 mJ, at 10 Hz repetition rate and 16.5 nm spectral bandwidth. We developed a 3D numerical model for OPCPA and we performed a theoretical study of influences of pump laser beam quality on optical parametric amplification. Our results indicate that OPCPA represents a valid replacement for Ti:sapphire in the front end of high energy short pulse lasers.

  10. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    CERN Document Server

    Bourrion, O; Grignon, C; Richer, J P; Guillaudin, O; Mayet, F; Billard, J; Santos, D

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i.e. decoded coordinates of hit tracks and corresponding energy measurements. The electronic designs, acquisition software and the results obtained are presented.

  11. EXCALIBUR: a small-pixel photon counting area detector for coherent X-ray diffraction - Front-end design, fabrication and characterisation

    Science.gov (United States)

    Marchal, J.; Horswell, I.; Willis, B.; Plackett, R.; Gimenez, E. N.; Spiers, J.; Ballard, D.; Booker, P.; Thompson, J. A.; Gibbons, P.; Burge, S. R.; Nicholls, T.; Lipp, J.; Tartoni, N.

    2013-03-01

    Coherent X-ray diffraction experiments on synchrotron X-ray beamlines require detectors with high spatial resolution and large detection area. The read-out chip developed by the MEDIPIX3 collaboration offers a small pixel size of 55 microns resulting in a very high spatial resolution when coupled to a direct X-ray conversion segmented silicon sensor. MEDIPIX3 assemblies present also the advantages of hybrid pixel detectors working in single photon counting mode: noiseless imaging, large dynamic range, extremely high frame rate. The EXCALIBUR detector is under development for the X-ray Coherence and Imaging Beamline I13 of the Diamond Light Source. This new detector consists of three modules, each with 16 MEDIPIX3 chips which can be read-out at 100 frames per second in continuous mode or 1000 frames per second in burst mode. In each module, the sensor is a large single silicon die covering 2 rows of 8 individual MEDIPIX3 read-out chips and provides a continuous active detection region within a module. Each module includes 1 million solder bumps connecting the 55 microns pixels of the silicon sensor to the 55 microns pixels of the 16 MEDIPIX3 read-out chips. The detection area of the 3-module EXCALIBUR detector is 115 mm × 100 mm with a small 6.8 mm wide inactive region between modules. Each detector module is connected to 2 FPGA read-out boards via a flexi-rigid circuit to allow a fully parallel read-out of the 16 MEDIPIX3 chips. The 6 FPGA read-out boards used in the EXCALIBUR detector are interfaced to 6 computing nodes via 10Gbit/s fibre-optic links to maintain the very high frame-rate capability. The standard suite of EPICS control software is used to operate the detector and to integrate it with the Diamond Light Source beamline software environment. This article describes the design, fabrication and characterisation of the MEDIPIX3-based modules composing the EXCALIBUR detector.

  12. Design of the Front End Electronics for the Infrared Camera of JEM-EUSO, and manufacturing and verification of the prototype model

    CERN Document Server

    Maroto, Oscar; Carbonell, Jordi; Tomàs, Albert; Reyes, Marcos; Joven, Enrique; Martín, Yolanda; Ríos, J A Morales de los; Del Peral, Luis; Frías, M D Rodríguez

    2015-01-01

    The Japanese Experiment Module (JEM) Extreme Universe Space Observatory (EUSO) will be launched and attached to the Japanese module of the International Space Station (ISS). Its aim is to observe UV photon tracks produced by ultra-high energy cosmic rays developing in the atmosphere and producing extensive air showers. The key element of the instrument is a very wide-field, very fast, large-lense telescope that can detect extreme energy particles with energy above $10^{19}$ eV. The Atmospheric Monitoring System (AMS), comprising, among others, the Infrared Camera (IRCAM), which is the Spanish contribution, plays a fundamental role in the understanding of the atmospheric conditions in the Field of View (FoV) of the telescope. It is used to detect the temperature of clouds and to obtain the cloud coverage and cloud top altitude during the observation period of the JEM-EUSO main instrument. SENER is responsible for the preliminary design of the Front End Electronics (FEE) of the Infrared Camera, based on an unco...

  13. Radiation tolerance of prototype BTeV pixel detector readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Gabriele Chiodini et al.

    2002-07-12

    High energy and nuclear physics experiments need tracking devices with increasing spatial precision and readout speed in the face of ever-higher track densities and increased radiation environments. The new generation of hybrid pixel detectors (arrays of silicon diodes bump bonded to arrays of front-end electronic cells) is the state of the art technology able to meet these challenges. We report on irradiation studies performed on BTeV pixel readout chip prototypes exposed to a 200 MeV proton beam at Indiana University Cyclotron Facility. Prototype pixel readout chip preFPIX2 has been developed at Fermilab for collider experiments and implemented in standard 0.25 micron CMOS technology following radiation tolerant design rules. The tests confirmed the radiation tolerance of the chip design to proton total dose up to 87 MRad. In addition, non destructive radiation-induced single event upsets have been observed in on-chip static registers and the single bit upset cross section has been extensively measured.

  14. SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Callier, S.; Fleury, J.; Dulucq, F.; De la Taille, C.; Chassard, G. Martin; Raux, L.; Seguin-Moreau, N.

    2013-01-01

    For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

  15. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  16. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  17. FAZIA front-end electronics

    OpenAIRE

    Salomon F.; Edelbruck P.; Brulin G.; Boiano A.; Tortone G.; Ordine A.; Bini M.; Barlini S.; Valdré S.

    2015-01-01

    FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  18. FAZIA front-end electronics

    Directory of Open Access Journals (Sweden)

    Salomon F.

    2015-01-01

    Full Text Available FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  19. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  20. FRIB Front End Design Status

    CERN Document Server

    Pozdeyev, E; Machicoane, G; Morgan, G; Rao, X; Zhao, Q; Stovall, J; Vorozhtsov, S; Sun, L

    2013-01-01

    The Facility for Rare Isotope Beams (FRIB) will provide a wide range of primary ion beams for nuclear physics research with rare isotope beams. The FRIB SRF linac will be capable of accelerating medium and heavy ion beams to energies beyond 200 MeV/u with a power of 400 kW on the fragmentation target. This paper presents the status of the FRIB Front End designed to produce uranium and other medium and heavy mass ion beams at world-record intensities. The paper describes the FRIB high performance superconducting ECR ion source, the beam transport designed to transport two-charge state ion beams and prepare them for the injection in to the SRF linac, and the design of a 4-vane 80.5 MHz RFQ. The paper also describes the integration of the front end with other accelerator and experimental systems.

  1. Development and validation of a 64 channel front end ASIC for 3D directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the {\\mu}TPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the "Time Over Threshold" information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400MHz by eight LVDS serial links. Eight ASIC were validated on a 2x256 strips of pixels prototype.

  2. Hit efficiency study of CMS prototype forward pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Dongwook; /Johns Hopkins U.

    2006-01-01

    In this paper the author describes the measurement of the hit efficiency of a prototype pixel device for the CMS forward pixel detector. These pixel detectors were FM type sensors with PSI46V1 chip readout. The data were taken with the 120 GeV proton beam at Fermilab during the period of December 2004 to February 2005. The detectors proved to be highly efficient (99.27 {+-} 0.02%). The inefficiency was primarily located near the corners of the individual pixels.

  3. Fabrication of ATLAS pixel detector prototypes at IRST

    CERN Document Server

    Boscardin, M; Gregori, P; Zen, M; Zori, N

    2001-01-01

    We report on the development of a fabrication technology for n-on-n silicon pixel detectors oriented to the ATLAS experiment at LHC. The main processing issues and some selected results from the electrical characterization of detector prototypes and related test structures are presented and discussed. (5 refs).

  4. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    Energy Technology Data Exchange (ETDEWEB)

    Richer, J.P.; Bosson, G. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Bourrion, O., E-mail: olivier.bourrion@lpsc.in2p3.f [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Grignon, C.; Guillaudin, O.; Mayet, F.; Santos, D. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France)

    2010-08-21

    A front end ASIC (BiCMOS-SiGe 0.35{mu}m) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous {mu}TPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips of pixels are monitored.

  5. A prototype hybrid pixel detector ASIC for the CLIC experiment

    CERN Document Server

    Valerio, P; Arfaoui, S; Ballabriga, R; Benoit, M; Bonacini, S; Campbell, M; Dannheim, D; De Gaspari, M; Felici, D; Kulis, S; Llopart, X; Nascetti, A; Poikela, T; Wong, W S

    2014-01-01

    A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64x64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measure- ment of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

  6. ALMA North American Integration Center Front-End Test System

    CERN Document Server

    Ediss, Geoffrey A; Crady, Kirk; Gaines, Erik; McLeod, Morgan; Morris, Greg; Williams, Rick; Perfetto, Antonio; Webber, John; 10.1007/s10762-010-9688-y

    2010-01-01

    The Atacama Large Millimeter/submillimeter (ALMA) Array Front End (FE) system is the first element in a complex chain of signal receiving, conversion, processing and recording. 70 Front Ends will be required for the project. The Front End is designed to receive signals in ten different frequency bands. In the initial phase of operations, the antennas will be fully equipped with six bands. These are Band 3 (84-116 GHz), Band 4 (125-163 GHz), Band 6 (211-275 GHz), Band 7 (275-373 GHz), Band 8 (385-500 GHz) and Band 9 (602-720 GHz). It is planned to equip the antennas with the missing bands at a later stage of ALMA operations, with a few Band 5 (163-211 GHz) and Band 10 (787-950 GHz) receivers in use before the end of the construction project. The ALMA Front End is far superior to any existing receiver systems; spin-offs of the ALMA prototypes are leading to improved sensitivities in existing millimeter and submillimeter observatories. The Front End units are comprised of numerous elements, produced at different...

  7. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  8. Muon front end for the neutrino factory

    CERN Document Server

    Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

    2013-01-01

    In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  9. Intrinsic Pixel Size Variation in an LSST Prototype Sensor

    CERN Document Server

    Baumer, Michael

    2015-01-01

    The ambitious science goals of the Large Synoptic Survey Telescope (LSST) have motivated a search for new and unexpected sources of systematic error in the LSST camera. Flat-field images are a rich source of data on sensor anomalies, although such effects are typically dwarfed by shot noise in a single flat field. After combining many ($\\sim 500$) such images into `ultraflats' to reduce the impact of shot noise, we perform photon transfer analysis on a pixel-by-pixel basis and observe no spatial structure in pixel linearity or gain at light levels of 100 ke$^-$ and below. At 125 ke$^-$, a columnar structure is observed in the gain map--we attribute this to a flux-dependent charge transfer inefficiency. We also probe small-scale variations in effective pixel size by analyzing pixel-neighbor correlations in ultraflat images, where we observe clear evidence of intrinsic variation in effective pixel size in an LSST prototype sensor near the $\\sim .3\\%$ level.

  10. Characterisation of pixel sensor prototypes for the ALICE ITS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Reidt, Felix [CERN (Switzerland); Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: ALICE-Collaboration

    2014-07-01

    ALICE is preparing a major upgrade of its experimental apparatus to be installed in the second long LHC shutdown (LS2) in the years 2018-2019. A key element of the upgrade is the replacement of the Inner Tracking System (ITS) deploying Monolithic Active Pixel Sensors (MAPS). The upgraded ITS will have a reduced material budget while increasing the pixel density and readout rate capabilities. The novel design leads to higher pointing and momentum resolution as well as a p{sub T} acceptance extended to lower values. The corresponding sensor prototypes were qualified in laboratory measurements and beam tests with respect to their radiation tolerance and detection efficiency. This talk summarises recent results on the characterisation of prototypes belonging to the ALPIDE family.

  11. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bourrion, O; Grignon, C; Guillaudin, O; Mayet, F; Santos, D

    2009-01-01

    A front end ASIC (BiCMOS-SiGe 0.35 um) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (keV) tracks with a gazeous uTPC. The development of this front end ASIC is a key point in this project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronic. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips are monitored.

  12. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  13. Optimizing emergency department front-end operations.

    Science.gov (United States)

    Wiler, Jennifer L; Gentle, Christopher; Halfpenny, James M; Heins, Alan; Mehrotra, Abhi; Mikhail, Michael G; Fite, Diana

    2010-02-01

    As administrators evaluate potential approaches to improve cost, quality, and throughput efficiencies in the emergency department (ED), "front-end" operations become an important area of focus. Interventions such as immediate bedding, bedside registration, advanced triage (triage-based care) protocols, physician/practitioner at triage, dedicated "fast track" service line, tracking systems and whiteboards, wireless communication devices, kiosk self check-in, and personal health record technology ("smart cards") have been offered as potential solutions to streamline the front-end processing of ED patients, which becomes crucial during periods of full capacity, crowding, and surges. Although each of these operational improvement strategies has been described in the lay literature, various reports exist in the academic literature about their effect on front-end operations. In this report, we present a review of the current body of academic literature, with the goal of identifying select high-impact front-end operational improvement solutions.

  14. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  15. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  16. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  17. UNIX NSW Front End Enhancements. Volume I.

    Science.gov (United States)

    1981-06-01

    Implementation UNIX MSG is implemented in the programming language C (D.M. Ritchie, S.C. Johnson, M.E. Lesk, and B.W. Kernighan , "The C Programming Language...8URC-0062 UNCLASSIFIED B BN4b I VOL-1 RADC-TR-81-lbA VOL-1 NL fRADCTR-81-164, Vol I (of two) Final Technical Report June 1981 .. UNIX NSW FRONT END...ABSTRACT (Conti--- on re0-r8. side If necessary and idenfify by block number) The effort to develop a UNIX NSW Front End is part of the National Software

  18. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Energy Technology Data Exchange (ETDEWEB)

    Noy, M., E-mail: matthew.noy@cern.ch [CERN, CH-1211 Geneva 23 (Switzerland); Aglieri Rinella, G.; Ceccucci, A. [CERN, CH-1211 Geneva 23 (Switzerland); Dellacasa, G. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Fiorini, M. [CERN, CH-1211 Geneva 23 (Switzerland); Garbolino, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Jarron, P. [CERN, CH-1211 Geneva 23 (Switzerland); INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Kaplon, J.; Kluge, A. [CERN, CH-1211 Geneva 23 (Switzerland); Marchetto, F. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Martin, E. [Universite Catholique de Louvain 1, Place de l' Universite BE-1348 Louvain-la-Neuve (Belgium); Mazza, G.; Martoiu, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Morel, M.; Perktold, L. [CERN, CH-1211 Geneva 23 (Switzerland); Rivetti, A. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Tiuraniemi, S. [CERN, CH-1211 Geneva 23 (Switzerland)

    2011-06-15

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16cm{sup 2} active area made of an assembly of 10 readout ASICs bump bonded to a 200{mu}m thick pixel silicon sensor, comprising 18000 pixels of 300{mu}mx300{mu}m. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5Mhit s{sup -1}mm{sup -2} together with an extreme time resolution of 100ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4ns, with a planar silicon sensor operating up to 300V over depletion. Moreover, the radiation level is severe, 2x10{sup 14}1MeVn{sub eq.}cm{sup -2} per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X{sub 0} to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  19. FRED, a Front End for Databases.

    Science.gov (United States)

    Crystal, Maurice I.; Jakobson, Gabriel E.

    1982-01-01

    FRED (a Front End for Databases) was conceived to alleviate data access difficulties posed by the heterogeneous nature of online databases. A hardware/software layer interposed between users and databases, it consists of three subsystems: user-interface, database-interface, and knowledge base. Architectural alternatives for this database machine…

  20. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    . The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

  1. Passive front-ends for wideband millimeter wave electronic warfare

    Science.gov (United States)

    Jastram, Nathan Joseph

    This thesis presents the analysis, design and measurements of novel passive front ends of interest to millimeter wave electronic warfare systems. However, emerging threats in the millimeter waves (18 GHz and above) has led to a push for new systems capable of addressing these threats. At these frequencies, traditional techniques of design and fabrication are challenging due to small size, limited bandwidth and losses. The use of surface micromachining technology for wideband direction finding with multiple element antenna arrays for electronic support is demonstrated. A wideband tapered slot antenna is first designed and measured as an array element for the subsequent arrays. Both 18--36 GHz and 75--110 GHz amplitude only and amplitude/phase two element direction finding front ends are designed and measured. The design of arrays using Butler matrix and Rotman lens beamformers for greater than two element direction finding over W band and beyond using is also presented. The design of a dual polarized high power capable front end for electronic attack over an 18--45 GHz band is presented. To combine two polarizations into the same radiating aperture, an orthomode transducer (OMT) based upon a new double ridge waveguide cross section is developed. To provide greater flexibility in needed performance characteristics, several different turnstile junction matching sections are tested. A modular horn section is proposed to address flexible and ever changing operational requirements, and is designed for performance criteria such as constant gain, beamwidth, etc. A multi-section branch guide coupler and low loss Rotman lens based upon the proposed cross section are also developed. Prototyping methods for the herein designed millimeter wave electronic warfare front ends are investigated. Specifically, both printed circuit board (PCB) prototyping of micromachined systems and 3D printing of conventionally machined horns are presented. A 4--8 GHz two element array with

  2. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  3. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  4. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  5. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  6. SR front ends of VEPP-4M storage ring

    CERN Document Server

    Fedotov, M G; Kuz'minykh, V S; Mironenko, L A; Mishnev, S I; Panchenko, V E; Protopopov, I Ya; Rachkova, V V; Rukhlyada, L P; Selivanov, A N

    2001-01-01

    The VEPP-4M storage ring system of SR front ends is described. SR is released by means of 14 front ends. Eleven of them are intended for beamlines of experimental stations. One front end is technical. For the permanent stabilization of an orbit of a beam with respect to a coordinate and angle in the vertical direction, two monitoring front ends are used. They take out SR from emission regions, which are at a large distance from one another.

  7. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  8. IV and CV curves for irradiated prototype BTeV silicon pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Maria R. Coluccia et al.

    2002-07-16

    The authors present IV and CV curves for irradiated prototype n{sup +}/n/p{sup +} silicon pixel sensors, intended for use in the BTeV experiment at Fermilab. They tested pixel sensors from various vendors and with two pixel isolation layouts: p-stop and p-spray. Results are based on exposure with 200 MeV protons up to 6 x 10{sup 14} protons/cm{sup 2}.

  9. Silicon pixel detector prototyping in SOI CMOS technology

    Science.gov (United States)

    Dasgupta, Roma; Bugiel, Szymon; Idzik, Marek; Kapusta, Piotr; Kucewicz, Wojciech; Turala, Michal

    2016-12-01

    The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

  10. Small-Scale Readout System Prototype for the STAR PIXEL Detector

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal; Anderssen, Eric; Greiner, Leo; Matis, Howard; Ritter, Hans Georg; Stezelberger, Thorsten; Sun, Xiangming; Thomas, James; Vu, Chinh; Wieman, Howard

    2008-10-10

    Development and prototyping efforts directed towards construction of a new vertex detector for the STAR experiment at the RHIC accelerator at BNL are presented. This new detector will extend the physics range of STAR by allowing for precision measurements of yields and spectra of particles containing heavy quarks. The innermost central part of the new detector is a high resolution pixel-type detector (PIXEL). PIXEL requirements are discussed as well as a conceptual mechanical design, a sensor development path, and a detector readout architecture. Selected progress with sensor prototypes dedicated to the PIXEL detector is summarized and the approach chosen for the readout system architecture validated in tests of hardware prototypes is discussed.

  11. Electrical characterization of irradiated prototype silicon pixel sensors for BTeV

    Energy Technology Data Exchange (ETDEWEB)

    Maria Rita Coluccia et al.

    2002-11-13

    The pixel detector in the BteV experiment at the Tevatron (Fermi Laboratory) is an important detector component for high-resolution tracking and vertex identification. For this task the hybrid pixel detector has to work in a very harsh radiation environment with up to 10{sup 14} minimum ionizing particles/cm{sup 2}/year. Radiation hardness of prototype n{sup +}/n/p{sup +} silicon pixel sensors has been investigated. We present Electrical characterization curves for irradiated prototype n{sup +}/n/p{sup +} sensors, intended for use in the BTeV experiment. We tested pixel sensors from various vendors and with two pixel isolation techniques: p-stop and p-spray. Results are based on irradiation with 200 MeV protons up to 6 x 10{sup 14} protons/cm{sup 2}.

  12. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  13. Implementation of a 66 MHz analog memory as a front end for LHC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Munday, D.J.; Parker, M.A. (Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE (United Kingdom)); Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Gros, J.; Jarron, P.; Heijne, E.H.M.; Meddeler, G.; Pollet, L.; Santiard, J.C.; Verweij, H. (CERN, CH-1211 Geneva 23 (Switzerland)); Goessling, C.; Lisowsky, B. (Institut fuer Physik, Universitaet Dortmund, D-4600 Dortmund (Germany)); Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; La Marra, D.; Wu, X. (DPNC, Geneva University, CH-1211, Geneva 4 (Switzerland)); Moorhead, G. (School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia)); Weidberg, A. (Department of Nuclear Physics, Oxford University, Oxford (United Kingdom)); Campbell, D.; Murray, P.; Seller, P.; Stevens, R. (Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)); Beuville, E.; Rouger, M.; Teiger, J. (Centre d' Etudes Nucleaires de Saclay, F-91191 Gif-sur-Yvette (France))

    1992-02-05

    We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

  14. A generic readout environment for prototype pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Turqueti, Marcos, E-mail: turqueti@fnal.go [Fermi National Accelerator Laboratory, Kirk and Wilson Road, 60510-500 (United States); Rivera, Ryan; Prosser, Alan; Kwan, Simon [Fermi National Accelerator Laboratory, Kirk and Wilson Road, 60510-500 (United States)

    2010-11-01

    Pixel detectors for experimental particle physics research have been implemented with a variety of readout formats and potentially generate massive amounts of data. Examples include the PSI46 device for the Compact Muon Solenoid (CMS) experiment which implements an analog readout, the Fermilab FPIX2.1 device with a digital readout, and the Fermilab Vertically Integrated Pixel device. The Electronic Systems Engineering Department of the Computing Division at the Fermi National Accelerator Laboratory has developed a data acquisition system flexible and powerful enough to meet the various needs of these devices to support laboratory test bench as well as test beam applications. The system is called CAPTAN (Compact And Programmable daTa Acquisition Node) and is characterized by its flexibility, versatility and scalability by virtue of several key architectural features. These include a vertical bus that permits the user to stack multiple boards, a gigabit Ethernet link that permits high speed communications to the system and a core group of boards that provide specific processing and readout capabilities for the system. System software based on distributed computing techniques supports an expandable network of CAPTANs. In this paper, we describe the system architecture and give an overview of its capabilities.

  15. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  16. A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

    Science.gov (United States)

    Furuta, M.; Okuni, H.; Hosoya, M.; Sai, A.; Matsuno, J.; Saigusa, S.; Itakura, T.

    2014-03-01

    This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.

  17. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  18. Synchrotron beam test of a photon counting pixel prototype based on Double-SOI technology

    Science.gov (United States)

    Zhou, Y.; Lu, Y.; Hashimoto, R.; Nishimura, R.; Kishimoto, S.; Arai, Y.; Ouyang, Q.

    2017-01-01

    The overall noise performances and first synchrotron beam measurement results of CPIXETEG3b, the first counting type Silicon-On-Insulator (SOI) pixel sensor prototype without crosstalk issue, are reported. The prototype includes a 64 × 64 pixel matrix with 50 μm pitch size. Each pixel consists of an N-in-P charge collection diode, a charge sensitive preamplifier, a shaper, a discriminator with thresholds adjustable by an in-pixel 4-bit DAC, and a 6-bit counter. The study was performed using the beam line 14A at KEK Photon Factory (KEK-PF) . The homogeneous response of the prototype, including charging-sharing effects between pixels were studied. 16 keV and 8 keV monochromatic small size (~ 10 μm diameter) X-ray beams were used for the charge sharing study, and a flat-field was added for homogenous response investigation. The overall detector homogeneity and the influence of basic detector parameters on charge sharing between pixels has been investigated.

  19. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  20. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

  1. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  2. Self-calibrating quadrature mixing front-end for SDR

    CSIR Research Space (South Africa)

    De Witt, JJ

    2008-01-01

    Full Text Available A quadrature mixing front-end is well-suited toward software define radio (SDR) applications, due to its low complexity and the inherent flexibility that it affords the radio front-end. Its performance is, however, severely affected by gain...

  3. Circuit techniques for cognitive radio receiver front-ends

    Science.gov (United States)

    Sadhu, Bodhisatwa

    This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit implementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks. A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor-capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, measurements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range. In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Transform): an RF front-end channelizer for software defined

  4. Low noise pixel detectors based on gated geiger mode avalanche photodiodes

    OpenAIRE

    Vilella Figueras, Eva; Comerma Montells, Albert; Alonso Casanovas, Oscar; Diéguez Barrientos, Àngel

    2011-01-01

    The gated operation is proposed as an effective method to reduce the noise in pixel detectors based on Geiger mode avalanche photodiodes. A prototype with the sensor and the front-end electronics monolithically integrated has been fabricated with a conventional HV-CMOS process. Experimental results demonstrate the increase of the dynamic range of the sensor by applying this technique.

  5. DESIGN & IMPLEMENTATION OF RECONFIGURABLE FRONT END FOR MIMO-OFDM

    Directory of Open Access Journals (Sweden)

    VEENA M.B.

    2011-02-01

    Full Text Available This paper focuses on design, implement and optimization of digital front end module of Multiple Input Multiple Output (MIMO-Orthogonal Frequency Division Multiplexing (OFDM system on FPGA employing Alamouti Technique (Space Time Block coding. MIMO-OFDM can very effectively be used to achieve higher data rate’s and higher reliability and this is going to be the Key for 4G Technology. MIMO -OFDM designed in this work consists of Input/Output Memory, 16 QAM Modulator, MIMO Encoder (Space Time Encoder, Wireless Channel Model, MIMO Decoder Space Time Decoder and 16 QAM Demodulator. This paper has resulted in the development of a hardware prototype of a MIMO Transmitter, Receiver and channel, which is implemented on a Spartan-3 FPGA board. As the number format adopted is floating point,there was a need to develop a separate function which will show the equivalent real numbers for the corresponding floating point number. This made the task of debugging a lot easier. Test benches for individual model were developed and tested it for its correct functionality. The functional simulation was carried out for the entire design. The entire design was mapped on to FPGA. The results were compared with the MATLAB results and were found to be the same.

  6. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  7. Front-End electronics configuration system for CMS

    CERN Document Server

    Gras, P; Funk, W; Gross, L; Vintache, D

    2001-01-01

    The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has bee...

  8. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  9. Prototypes and system test stands for the Phase1 upgrade of the CMS pixel detector

    CERN Document Server

    Hasegawa, Satoshi

    2015-01-01

    The CMS pixel phase-1 upgrade project replaces the current pixel detector with an upgraded system with faster readout electronics during the extended year-end technical stop of 2016/17. New electronics prototypes for the system have been developed, and tests in a realistic environment for a comprehensive evaluation are needed. A full readout test stand with either the same hardware as used in the current CMS pixel detector or the latest prototypes of upgrade electronics has been built. The setup enables the observation and investigation of a jitter increase in the data line as the trigger rate increase. This increase is due to the way in which the clock and trigger distribution is implemented in CMS. A new prototype of the electronics with a PLL based on a voltage controlled quartz crystal oscillator (QPLL), which works as jitter filter, in the clock distribution path was produced. With the test stand, it was confirmed that the jitter increase is not seen with the prototype, and also good performance was conf...

  10. Prototypes and system test stands for the Phase 1 upgrade of the CMS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Hasegawa, S., E-mail: satoshi@fnal.gov

    2016-09-21

    The CMS pixel phase-1 upgrade project replaces the current pixel detector with an upgraded system with faster readout electronics during the extended year-end technical stop of 2016/2017. New electronics prototypes for the system have been developed, and tests in a realistic environment for a comprehensive evaluation are needed. A full readout test stand with either the same hardware as used in the current CMS pixel detector or the latest prototypes of upgrade electronics has been built. The setup enables the observation and investigation of a jitter increase in the data line associated with trigger rate increases. This effect is due to the way in which the clock and trigger distribution is implemented in CMS. A new prototype of the electronics with a PLL based on a voltage controlled quartz crystal oscillator (QPLL), which works as jitter filter, in the clock distribution path was produced. With the test stand, it was confirmed that the jitter increase is not seen with the prototype, and also good performance was confirmed at the expected detector operation temperature (−20 °C).

  11. Prototypes and system test stands for the Phase 1 upgrade of the CMS pixel detector

    Science.gov (United States)

    Hasegawa, S.

    2016-09-01

    The CMS pixel phase-1 upgrade project replaces the current pixel detector with an upgraded system with faster readout electronics during the extended year-end technical stop of 2016/2017. New electronics prototypes for the system have been developed, and tests in a realistic environment for a comprehensive evaluation are needed. A full readout test stand with either the same hardware as used in the current CMS pixel detector or the latest prototypes of upgrade electronics has been built. The setup enables the observation and investigation of a jitter increase in the data line associated with trigger rate increases. This effect is due to the way in which the clock and trigger distribution is implemented in CMS. A new prototype of the electronics with a PLL based on a voltage controlled quartz crystal oscillator (QPLL), which works as jitter filter, in the clock distribution path was produced. With the test stand, it was confirmed that the jitter increase is not seen with the prototype, and also good performance was confirmed at the expected detector operation temperature (-20 °C).

  12. Muon capture for the front end of a muon collider

    CERN Document Server

    Neuffer, D

    2011-01-01

    We discuss the design of the muon capture front end for a \\mu+-\\mu- Collider. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then cooled and accelerated to high energy into a storage ring for high-energy high luminosity collisions. Our initial design is based on the somewhat similar front end of the International Design Study (IDS) neutrino factory.

  13. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  14. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  15. Microwave integrated circuit radiometer front-ends for the Push Broom Microwave Radiometer

    Science.gov (United States)

    Harrington, R. F.; Hearn, C. P.

    1982-01-01

    Microwave integrated circuit front-ends for the L-band, S-band and C-band stepped frequency null-balanced noise-injection Dicke-switched radiometer to be installed in the NASA Langley airborne prototype Push Broom Microwave Radiometer (PBMR) are described. These front-ends were developed for the fixed frequency of 1.413 GHz and the variable frequencies of 1.8-2.8 GHz and 3.8-5.8 GHz. Measurements of the noise temperature of these units were made at 55.8 C, and the results of these tests are given. While the overall performance was reasonable, improvements need to be made in circuit losses and noise temperatures, which in the case of the C-band were from 1000 to 1850 K instead of the 500 K specified. Further development of the prototypes is underway to improve performance and extend the frequency range.

  16. Evaluation of Compton gamma camera prototype based on pixelated CdTe detectors

    OpenAIRE

    Y Calderón; Chmeissani, M.; Kolstein, M.; De Lorenzo, G.

    2014-01-01

    A proposed Compton camera prototype based on pixelated CdTe is simulated and evaluated in order to establish its feasibility and expected performance in real laboratory tests. The system is based on module units containing a 2×4 array of square CdTe detectors of 10×10 mm2 area and 2 mm thickness. The detectors are pixelated and stacked forming a 3D detector with voxel sizes of 2 × 1 × 2 mm3. The camera performance is simulated with Geant4-based Architecture for Medicine-Oriented Simulations(G...

  17. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  18. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  19. A contextual classifier that only requires one prototype pixel for each class

    DEFF Research Database (Denmark)

    Maletti, Gabriela Mariel; Ersbøll, Bjarne Kjær; Conradsen, Knut

    2001-01-01

    A three stage scheme for classification of multi-spectral images is proposed. In each stage, statistics of each class present in the image are estimated. The user is required to provide only one prototype pixel for each class to be seeded into a homogeneous region. The algorithm starts by generat......A three stage scheme for classification of multi-spectral images is proposed. In each stage, statistics of each class present in the image are estimated. The user is required to provide only one prototype pixel for each class to be seeded into a homogeneous region. The algorithm starts...... constructed with experimental data is used in this stage. The algorithm was tested with the Kappa coefficient k on synthetical images and compared with K-means (k~=0.41) and a similar scheme that uses spectral means (k~=0.75) instead of histograms (k~=0.90). Results are shown on a dermatological image...

  20. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  1. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  2. Indico front-end: From spaghetti to lasagna

    CERN Document Server

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  3. Development and characterization of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Kohrs, Robert

    2008-09-15

    For the future TeV-scale linear collider ILC (International Linear Collider) a vertex detector of unprecedented performance is needed to fully exploit its physics potential. By incorporating a field effect transistor into a fully depleted sensor substrate the DEPFET (Depleted Field Effect Transistor) sensor combines radiation detection and in-pixel amplification. For the operation at a linear collider the excellent noise performance of DEPFET pixels allows building very thin detectors with a high spatial resolution and a low power consumption. With this thesis a prototype system consisting of a 64 x 128 pixels sensor, dedicated steering and readout ASICs and a data acquisition board has been developed and successfully operated in the laboratory and under realistic conditions in beam test environments at DESY and CERN. A DEPFET matrix has been successfully read out using the on-chip zero-suppression of the readout chip CURO 2. The results of the system characterization and beam test results are presented. (orig.)

  4. A VME MXI-II Based Setup for Testing ALICE Pixel Readout Prototypes

    CERN Document Server

    Chochula, P; CERN. Geneva

    2000-01-01

    Abstract One of the possible readout scenarios for ALICE ITS pixel layers counts on in- situ zero suppression, performed by Pilot control chip. Preprocessed event will be then serialized and sent out via about 50 m long copper cable for further processing. The VME prototypes of Pilot chip and link (called "SHORTLINK") were developed in the frames of Alice collaboration. Here we describe the VME test system, developed to test the modules.

  5. Pixel readout chip for the ATLAS experiment

    CERN Document Server

    Ackers, M; Blanquart, L; Bonzom, V; Comes, G; Fischer, P; Keil, M; Kühl, T; Meuser, S; Delpierre, P A; Treis, J; Raith, B A; Wermes, N

    1999-01-01

    Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4*10/sup 8/ individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector. Consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported. (6 refs).

  6. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  7. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  8. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  9. A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

    Science.gov (United States)

    Zhou, Zhijun; Warr, Paul A

    2016-12-01

    Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

  10. Readout chip for the CMS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Rossini, Marco, E-mail: marco.rossini@phys.ethz.ch

    2014-11-21

    For the CMS experiment a new pixel detector is planned for installation during the extended shutdown in winter 2016/2017. Among the changes of the detector modified front end electronics will be used for higher efficiency at peak luminosity of the LHC and faster readout. The first prototype versions of the new readout chip have been designed and produced. The results of qualification and calibration for the new chip are presented in this paper.

  11. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  12. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  13. CMS ECAL Front-End boards the XFEST project

    CERN Document Server

    Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N; Romanteau, T

    2005-01-01

    The Front-End (FE) boards are part of the On-detector electronics system of the CMS electromagnetic calorimeter (ECAL). Their digital functionalities and properties are tested by a dedicated test bench located at Laboratoire Leprince-Ringuet, prior to the board integration in the CMS detector at CERN. XFEST, acronym for eXtended Front-End System Test, is designed to perform tests that can last several hours, on up to 12 FE boards in parallel. The system is designed to deliver 80 tested boards per week. This contribution presents the XFEST set-up and the results of the measurements on FE boards.

  14. The National Ignition Facility front-end laser system

    Energy Technology Data Exchange (ETDEWEB)

    Burkhart, S.C.; Beach, R.J.; Crane, J.H.; Davin, J.M.; Perry, M.D.; Wilcox, R.B.

    1995-07-07

    The proposed National Ignition Facility is a 192 beam Nd:glass laser system capable of driving targets to fusion ignition by the year 2005. A key factor in the flexibility and performance of the laser is a front-end system which provides a precisely formatted beam to each beamline. Each of the injected beams has individually controlled energy, temporal pulseshape, and spatial shape to accommodate beamline-to-beamline variations in gain and saturation. This flexibility also gives target designers the options for precisely controlling the drive to different areas of the target. The design of the Front-End laser is described, and initial results are discussed.

  15. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  16. arXiv The FoCal prototype - an extremely fine-grained electromagnetic calorimeter using CMOS pixel sensors

    CERN Document Server

    Nooren, G.; Peitzmann, T.; Reicher, M.; Rocco, E.; Roehrich, D.; Ullaland, K.; van den Brink, A.; van Leeuwen, M.; Wang, H.; Yang, S.; Zhang, C.

    A prototype of a Si-W EM calorimeter was built with Monolithic Active Pixel Sensors as the active elements. With a pixelsize of 30 $\\mu$m it allows digital calorimetry, i.e. the particles' energy is determined by counting pixels, not by measuring the energy deposited. Although of modest size, only 4 Moliere radii wide, it has 39 million pixels. We describe the construction and tuning of the prototype and present results from beam tests and compare them with predictions of GEANT-based Monte Carlo simulations. We show the shape of showers caused by electrons in unprecedented detail. Results for energy and position resolution will also be given.

  17. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  18. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  19. A socio-interactive framework for the fuzzy front end

    NARCIS (Netherlands)

    Smulders, Frido E.; Broek, van den Egon L.; Voort, van der Mascha C.

    2007-01-01

    This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary sociointeractive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive framework

  20. Business modelling in the fuzzy front end of innovation

    NARCIS (Netherlands)

    Limonard, A.J.P.; Berkers, F.T.H.M.; Niamut, O.A.; Bachet, T.T.; Reuver, M. de

    2011-01-01

    In this paper we address the techno-economic dilemma in the fuzzy front end of R&D consortia: how to bridge the gap between the lack of knowledge on future demand for a technology and the need to make design decisions. The problem in these types of collaborations that the business interests to devel

  1. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  2. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  3. Single Front-End MIMO Architecture with Parasitic Antenna Elements

    Science.gov (United States)

    Yoshida, Mitsuteru; Sakaguchi, Kei; Araki, Kiyomichi

    In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

  4. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  5. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  6. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  7. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  8. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    of the staging of inno-vation processes, which focuses on the content and framing of ideas at the front end. The understanding sensitises hereby towards con-cerns of path-dependency and translations, inclu-ding trade-offs and potentialities involved in su-stainning or reframing matters of significance as part...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

  9. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  10. Holographic optical receiver front end for wireless infrared indoor communications.

    Science.gov (United States)

    Jivkova, S; Kavehrad, M

    2001-06-10

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver's small size, light weight, and low cost make the receiver front end a promising candidate for a user's portable equipment in broadband indoor wireless multimedia access.

  11. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  12. A PFM based digital pixel with off-pixel residue measurement for 15μm pitch MWIR FPAs

    Science.gov (United States)

    Abbasi, Shahbaz; Shafique, Atia; Galioglu, Arman; Ceylan, Omer; Yazici, Melik; Gurbuz, Yasar

    2016-05-01

    Digital pixels based on pulse frequency modulation (PFM) employ counting techniques to achieve very high charge handling capability compared to their analog counterparts. Moreover, extended counting methods making use of leftover charge (residue) on the integration capacitor help improve the noise performance of these pixels. However, medium wave infrared (MWIR) focal plane arrays (FPAs) having smaller pixel pitch are constrained in terms of pixel area which makes it difficult to add extended counting circuitry to the pixel. Thus, this paper investigates the performance of digital pixels employing off-pixel residue measurement. A circuit prototype of such a pixel has been designed for 15μm pixel pitch and fabricated in 90nm CMOS. The prototype is composed of a pixel front-end based on a PFM loop. The frontend is a modified version of conventional design providing a means for buffering the signal that needs to be converted to a digital value by an off-pixel ADC. The pixel has an integration phase and a residue measurement phase. Measured integration performance of the pixel has been reported in this paper for various detector currents and integration times.

  13. Evaluation of Compton gamma camera prototype based on pixelated CdTe detectors.

    Science.gov (United States)

    Calderón, Y; Chmeissani, M; Kolstein, M; De Lorenzo, G

    2014-06-01

    A proposed Compton camera prototype based on pixelated CdTe is simulated and evaluated in order to establish its feasibility and expected performance in real laboratory tests. The system is based on module units containing a 2×4 array of square CdTe detectors of 10×10 mm(2) area and 2 mm thickness. The detectors are pixelated and stacked forming a 3D detector with voxel sizes of 2 × 1 × 2 mm(3). The camera performance is simulated with Geant4-based Architecture for Medicine-Oriented Simulations(GAMOS) and the Origin Ensemble(OE) algorithm is used for the image reconstruction. The simulation shows that the camera can operate with up to 10(4) Bq source activities with equal efficiency and is completely saturated at 10(9) Bq. The efficiency of the system is evaluated using a simulated (18)F point source phantom in the center of the Field-of-View (FOV) achieving an intrinsic efficiency of 0.4 counts per second per kilobecquerel. The spatial resolution measured from the point spread function (PSF) shows a FWHM of 1.5 mm along the direction perpendicular to the scatterer, making it possible to distinguish two points at 3 mm separation with a peak-to-valley ratio of 8.

  14. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  15. New and Efficient Neutrino Factory Front-End Design

    CERN Document Server

    Gallardo, Juan C; Kirk, Harold G; Neuffer, David V; Palmer, Robert; Paul, Kevin; Scott Berg, J

    2005-01-01

    As part of the APS Joint Study on the Future of Neutrino Physics* we have carried out detailed studies of the Neutrino Factory front-end. A major goal of the new study was to achieve equal performance to our earlier feasibility studies** at reduced cost. The optimal channel design is described in this paper. New innovations included an adiabatic buncher for phase rotation and a simplified cooling channel with LiH absorbers. The linear channel is 295 m long and produces 0.17 muons per proton on target into the assumed accelerator transverse acceptance of 30 mm and longitudinal acceptance of 150 mm.

  16. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  17. New RPC front-end electronics for hades

    CERN Document Server

    Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

    2007-01-01

    Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

  18. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  19. Review of the Neutrino Factory Muon Front End

    CERN Document Server

    Rogers, C

    2011-01-01

    Three major facilities have been proposed for the precision study of neutrino oscillation parameters, the Neutrino Factory, the Betabeam and the Superbeam. Of these the Neutrino Factory offers high precision measurement of oscillations parameters. The Neutrino Factory generates neutrinos by firing protons onto a target in order to produce pions. The pions decay to muons which are captured before being accelerated to 25 GeV and stored in racetrack-shaped rings where they decay to neutrinos. In this note the pion decay channel, longitudinal drift, adiabatic buncher, phase rotation and ionisation cooling system that make up the Neutrino Factory muon front end are reviewed.

  20. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  1. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  2. Instrument Front-Ends at Fermilab During Run II

    CERN Document Server

    Meyer, Thomas; Voy, Duane; 10.1088/1748-0221/6/11/T11004

    2012-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  3. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  4. Front End Schaltung zur Online Auswertung von EKG-Signalen

    Directory of Open Access Journals (Sweden)

    E. Ayari

    2007-06-01

    Full Text Available Ein mobiles EKG-System zur Online Auswertung von EKG-Signalen wird dargestellt. Die Auswertung beruht auf ein energiesparendes Verfahren, das den Vorteil einer zulässigen Unterabtastung des Signals bietet und eine Interaktion zwischen der messenden Elektronik und dem funkgebundenen Auswertungsrechner ermöglicht. Diese Interaktion besteht darin, sowohl die Front End Schaltung im EKG-Sensor als auch den im ATmega8L eingebetteten A/D-Wandler vom Auswertungsrechner zu steuern und den Datenbedarf des Rechners dynamisch an die Erfordernisse des Analyseprogramms anzupassen. Das entwickelte EKG-System liefert erfolgreiche Charakterisierungen erfasster Elektrokardiogramme.

    A mobile ecg-system for an online analysis of electrocardiogram signals is presented. The analysis is based on an energy-saving procedure, which offers the advantage of an acceptable undersampling of the signal, and which allows an interaction between the measuring electronic and the radio-bound analysis-computer. In this interaction both the front-end circuit in the ecg-sensor and the A/D converter, which is embedded in the ATmega8L, are steered by the analysis computer. The data requirement of the computer is also dynamically adapted to the requirements of the analysis-program. The developed ecg-system supplies successful characterisations of measured electrocardiograms.

  5. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  6. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  7. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  8. FEC-CCS A common Front-End Controller card for the CMS detector electronics

    CERN Document Server

    Kloukinas, Kostas; Drouhin, F; Ljuslin, C; Marchioro, A; Murer, E; Paillard, C; Vlasov, E

    2007-01-01

    The FEC-CCS is a custom made 9U VME64x card for the CMS Off-Detector electronics. The FEC-CCS card is responsible for distributing the fast timing signals and the slow control data, through optical links, to the Front-End system. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS detectors namely the Tracker, ECAL, Preshower, PIXELs, RPCs and TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enable the common utilization by most of the CMS detectors. Results from the integration tests with the detector electronics subsystems and performance measurements will be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.

  9. A compact dual-band RF front-end and board design for vehicular platforms

    Science.gov (United States)

    Sharawi, Mohammad S.; Aloi, Daniel N.

    2012-03-01

    Modern vehicular platforms include several wireless systems that provide navigation, entertainment and road side assistance, among other services. These systems operate at different frequency bands and thus careful system-level design should be followed to minimise the interference between them. In this study, we present a compact dual-band RF front-end module for global positioning system (GPS) operating in the L1-band (1574.42-1576.42 MHz) and satellite digital audio radio system (SDARS) operating in the S-band (2320-2345 MHz). The module provides more than 26 dB of measured gain in both bands and low noise figure values of 0.9 and 1.2 dB in SDARS and GPS bands, respectively. The front-end has interference suppression capability from the advanced mobile phone system and personal communication service cellular bands. The module is designed on a low-cost FR-4 substrate material and occupies a small size of 62 × 29 × 1.3 mm3. It dissipates 235 mW in the SDARS section and 100 mW in the GPS section. Three prototypes have been built to verify a repeatable performance.

  10. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  11. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  12. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  13. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  14. Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications.

    Science.gov (United States)

    Chi, Baoyong; Yao, Jinke; Han, Shuguang; Xie, Xiang; Li, Guolin; Wang, Zhihua

    2007-07-01

    State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.

  15. First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

    CERN Document Server

    Alemi, M; Gys, Thierry; Mikulec, B; Piedigrossi, D; Puertolas, D; Rosso, E; Schomaker, R; Snoeys, W; Wyllie, Ken H

    2000-01-01

    We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface...

  16. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  17. Neural-network front ends in unsupervised learning.

    Science.gov (United States)

    Pedrycz, W; Waletzky, J

    1997-01-01

    Proposed is an idea of partial supervision realized in the form of a neural-network front end to the schemes of unsupervised learning (clustering). This neural network leads to an anisotropic nature of the induced feature space. The anisotropic property of the space provides us with some of its local deformation necessary to properly represent labeled data and enhance efficiency of the mechanisms of clustering to be exploited afterwards. The training of the network is completed based upon available labeled patterns-a referential form of the labeling gives rise to reinforcement learning. It is shown that the discussed approach is universal and can be utilized in conjunction with any clustering method. Experimental studies are concentrated on three main categories of unsupervised learning including FUZZY ISODATA, Kohonen self-organizing maps, and hierarchical clustering.

  18. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  19. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  20. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  1. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... of development. We will through an in-depth case study demonstrate how this constitution of development is enacted as best practice for development., making it difficult to bring forth radical ideas. Furthermore we will describe how navigation and (re)enactment of the constitution of development are practiced...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...

  2. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  3. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  4. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  5. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  6. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  7. A software-radio front-end for microwave applications

    Science.gov (United States)

    Streifinger, M.; Müller, T.; Luy, J.-F.; Biebl, E. M.

    2003-05-01

    In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  8. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    CERN Document Server

    Impiombato, D; Mineo, T; Catalano, O; Gargano, C; La Rosa, G; Russo, F; Sottile, G; Billotta, S; Bonanno, G; Garozzo, S; Grillo, A; Marano, D; Romeo, G

    2015-01-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  9. A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

    Energy Technology Data Exchange (ETDEWEB)

    Fan Mngjun; Ren Junyan; Shu Guanghua; Li Ning; Ye Fan; Xu Jun [State Key Laboratory of ASIC and Systems, Fudan University, Shanghai 201203 (China); Guo Yao, E-mail: 052052003@fudan.edu.cn [The Media Tek Inc., Beijing 100080 (China)

    2011-01-15

    A 12-Bit 40-MS/s pipelined analog-to-digital converter (ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-{mu}m CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noise-and-distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply. (semiconductor integrated circuits)

  10. A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique*

    Institute of Scientific and Technical Information of China (English)

    Fan Mingjun; Ren Junyan; Shu Guanghua; Guo Yao; Li Ning; Ye Fan; Xu Jun

    2011-01-01

    A 12-Bit 40-MS/s pipelined analog-to-digital converter (ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noiseand-distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.

  11. The ToPiX v4 prototype for the triggerless readout of the PANDA silicon pixel detector

    Science.gov (United States)

    Mazza, G.; Calvo, D.; De Remigis, P.; Mignone, M.; Olave, J.; Rivetti, A.; Wheadon, R.; Zotti, L.

    2015-01-01

    ToPiX v4 is the prototype for the readout of the silicon pixel sensors for the Micro Vertex Detector of the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming particles and is designed for the triggerless environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100 × 100 μm2, a 160 MHz time stamp distribution circuit to measure both particle arrival time and released energy (via ToT technique) and the full control logic. The ASIC is designed in a 0.13 μm CMOS technology with SEU protection techniques for the digital parts.

  12. Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

    Science.gov (United States)

    Demaria, N.; Barbero, M. B.; Fougeron, D.; Gensolen, F.; Godiot, S.; Menouni, M.; Pangaud, P.; Rozanov, A.; Wang, A.; Bomben, M.; Calderini, G.; Crescioli, F.; Le Dortz, O.; Marchiori, G.; Dzahini, D.; Rarbi, F. E.; Gaglione, R.; Gonella, L.; Hemperek, T.; Huegging, F.; Karagounis, M.; Kishishita, T.; Krueger, H.; Rymaszewski, P.; Wermes, N.; Ciciriello, F.; Corsi, F.; Marzocca, C.; De Robertis, G.; Loddo, F.; Licciulli, F.; Andreazza, A.; Liberali, V.; Shojaii, S.; Stabile, A.; Bagatin, M.; Bisello, D.; Mattiazzo, S.; Ding, L.; Gerardin, S.; Giubilato, P.; Neviani, A.; Paccagnella, A.; Vogrig, D.; Wyss, J.; Bacchetta, N.; De Canio, F.; Gaioni, L.; Nodari, B.; Manghisoni, M.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Vacchi, C.; Beccherle, R.; Bellazzini, R.; Magazzu, G.; Minuti, M.; Morsani, F.; Palla, F.; Poulios, S.; Fanucci, L.; Rizzi, A.; Saponara, S.; Androsov, K.; Bilei, G. M.; Menichelli, M.; Conti, E.; Marconi, S.; Passeri, D.; Placidi, P.; Della Casa, G.; Mazza, G.; Rivetti, A.; Da Rocha Rolo, M. D.; Monteil, E.; Pacher, L.; Gajanana, D.; Gromov, V.; Hessey, N.; Kluit, R.; Zivkovic, V.; Havranek, M.; Janoska, Z.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Kafka, V.; Sicho, P.; Vrba, V.; Vila, I.; Lopez-Morillo, E.; Aguirre, M. A.; Palomo, F. R.; Muñoz, F.; Abbaneo, D.; Christiansen, J.; Dannheim, D.; Dobos, D.; Linssen, L.; Pernegger, H.; Valerio, P.; Alipour Tehrani, N.; Bell, S.; Prydderch, M. L.; Thomas, S.; Christian, D. C.; Fahim, F.; Hoff, J.; Lipton, R.; Liu, T.; Zimmerman, T.; Garcia-Sciveres, M.; Gnani, D.; Mekkaoui, A.; Gorelov, I.; Hoeferkamp, M.; Seidel, S.; Toms, K.; De Witt, J. N.; Grillo, A.; Paternò, A.

    2016-12-01

    This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5-800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. The collaboration is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.

  13. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    CERN Document Server

    Boek, J; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2013-01-01

    inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University ofWuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

  14. Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Trimpl, M.

    2005-12-15

    The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

  15. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  16. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    INSPIRE-00399968

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  17. Highly scalable digital front end architectures for digital printing

    Science.gov (United States)

    Staas, David

    2011-01-01

    HP's digital printing presses consume a tremendous amount of data. The architectures of the Digital Front Ends (DFEs) that feed these large, very fast presses have evolved from basic, single-RIP (Raster Image Processor) systems to multirack, distributed systems that can take a PDF file and deliver data in excess of 3 Gigapixels per second to keep the presses printing at 2000+ pages per minute. This paper highlights some of the more interesting parallelism features of our DFE architectures. The high-performance architecture developed over the last 5+ years can scale up to HP's largest digital press, out to multiple mid-range presses, and down into a very low-cost single box deployment for low-end devices as appropriate. Principles of parallelism pervade every aspect of the architecture, from the lowest-level elements of jobs to parallel imaging pipelines that feed multiple presses. From cores to threads to arrays to network teams to distributed machines, we use a systematic approach to move bottlenecks. The ultimate goals of these efforts are: to take the best advantage of the prevailing hardware options at our disposal; to reduce power consumption and cooling requirements; and to ultimately reduce the cost of the solution to our customers.

  18. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  19. Digital Front End for Wide-Band VLBI Science Receiver

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Navarro, Robert; Goodhart, Charles; Rogstad, Steve; Chandra, Kumar; Finley, Sue; Trinh, Joseph; Soriano, Melissa; White, Les; hide

    2006-01-01

    An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

  20. Front-end electronics and trigger systems - status and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-08-21

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described.

  1. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  2. Performance study of new pixel hybrid photon detector prototypes for the LHCb RICH counters

    CERN Document Server

    Moritz, M; Allebone, L; Campbell, M; Gys, Thierry; Newby, C; Pickford, A; Piedigrossi, D; Wyllie, K

    2004-01-01

    A pixel Hybrid Photon Detector was developed according to the specific requirements of the LHCb ring imaging Cerenkov counters. This detector comprises a silicon pixel detector bump-bonded to a binary readout chip to achieve a 25 ns fast readout and a high signal-to-noise ratio. The detector performance was characterized by varying the pixel threshold, the tube high voltage, the silicon bias voltage and by the determination of the photoelectron detection efficiency. Furthermore accelerated aging and high pixel occupancy tests were performed to verify the long term stability. The results were obtained using Cerenkov light and a fast pulsed light emitting diode. All measurements results are within the expectations and fulfill the design goals. (8 refs).

  3. An Enhanced Front-End Algorithm for Reducing Channel Change Time in DVB-T System

    Science.gov (United States)

    Joe, Inwhee; Choi, Jongsung

    To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

  4. Towards third generation pixel readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@lbl.gov; Mekkaoui, A.; Ganani, D.

    2013-12-11

    We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130 nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC design generic so that different experiments can configure it to meet significantly different requirements, without the need for everybody to develop their own ASIC from the ground up. In terms of target technology, a demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in 65 nm CMOS and irradiated with protons in December 2011 and May 2012.

  5. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  6. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  7. Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon, E-mail: barbero@physik.uni-bonn.de [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Arutinov, David [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Beccherle, Roberto; Darbo, Giovanni [INFN Genova, via Dodecaseno 33, IT-16146 Genova (Italy); Dube, Sourabh; Elledge, David; Fleury, Julien [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Fougeron, Denis [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Garcia-Sciveres, Maurice [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Gensolen, Fabrice [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Gnani, Dario [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Gromov, Vladimir [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); Jensen, Frank [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Hemperek, Tomasz; Karagounis, Michael [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Kluit, Ruud [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); Kruth, Andre [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Mekkaoui, Abderrezak [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Menouni, Mohsine [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Schipper, Jan David [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); and others

    2011-09-11

    A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25{mu}m CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80x336 pixels, each 50x250{mu}m{sup 2}, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.

  8. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  9. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    AUTHOR|(CDS)2069646; Abbas, M.; Abbrescia, M.; Abdelalim, A.A.; Abi Akl, M.; Aboamer, O.; Acosta, D.; Ahmad, A.; Ahmed, W.; Ahmed, W.; Aleksandrov, A.; Aly, R.; Altieri, P.; Asawatangtrakuldee, C.; Aspell, P.; Assran, Y.; Awan, I.; Bally, S.; Ban, Y.; Banerjee, S.; Barashko, V.; Barria, P.; Bencze, G.; Beni, N.; Benussi, L.; Bhopatkar, V.; Bianco, S.; Bos, J.; Bouhali, O.; Braghieri, A.; Braibant, S.; Buontempo, S.; Calabria, C.; Caponero, M.; Caputo, C.; Cassese, F.; Castaneda, A.; Cauwenbergh, S.; Cavallo, F.R.; Celik, A.; Choi, M.; Choi, S.; Christiansen, J.; Cimmino, A.; Colafranceschi, S.; Colaleo, A.; Conde Garcia, A.; Czellar, S.; Dabrowski, M.M.; De Lentdecker, G.; De Oliveira, R.; de Robertis, G.; Dildick, S.; Dorney, B.; Elmetenawee, W.; Endroczi, G.; Errico, F.; Fenyvesi, A.; Ferry, S.; Furic, I.; Giacomelli, P.; Gilmore, J.; Golovtsov, V.; Guiducci, L.; Guilloux, F.; Gutierrez, A.; Hadjiiska, R.M.; Hassan, A.; Hauser, J.; Hoepfner, K.; Hohlmann, M.; Hoorani, H.; Iaydjiev, P.; Jeng, Y.G.; Kamon, T.; Karchin, P.; Korytov, A.; Krutelyov, S.; Kumar, A.; Kim, H.; Lee, J.; Lenzi, T.; Litov, L.; Madorsky, A.; Maerschalk, T.; Maggi, M.; Magnani, A.; Mal, P.K.; Mandal, K.; Marchioro, A.; Marinov, A.; Masod, R.; Majumdar, N.; Merlin, J.A.; Mitselmakher, G.; Mohanty, A.K.; Mohamed, S.; Mohapatra, A.; Molnar, J.; Muhammad, S.; Mukhopadhyay, S.; Naimuddin, M.; Nuzzo, S.; Oliveri, E.; Pant, L.M.; Paolucci, P.; Park, I.; Passeggio,G.; Pavlov, B.; Philipps, B.; Piccolo, D.; Postema, H.; Puig Baranac, A.; Radi, A.; Radogna, R.; Raffone, G.; Ranieri, A.; Rashevski, G.; Riccardi, C.; Rodozov, M.; Rodrigues, A.; Ropelewski, L.; RoyChowdhury, S.; Ryu, G.; Ryu, M.S.; Safonov, A.; Salva, S.; Saviano, G.; Sharma, A.; Sharma, A.; Sharma, R.; Shah, A.H.; Shopova, M.; Sturdy, J.; Sultanov, G.; Swain, S.K.; Szillasi, Z.; Talvitie, J.; Tamma, C.; Tatarinov, A.; Tuuva, T.; Tytgat, M.; Vai, I.; Van Stenis, M.; Venditti, R.; Verhagen, E.; Verwilligen, P.; Vitulo, P.; Volkov, S.; Vorobyev, A.; Wang, D.; Wang, M.; Yang, U.; Yang, Y.; Yonamine, R.; Zaganidis, N.; Zenoni, F.; Zhang, A.

    2016-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  10. Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

    Science.gov (United States)

    Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

    2012-07-01

    There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

  11. The Front-End to Google for Teachers' Online Searching

    Science.gov (United States)

    Seyedarabi, Faezeh

    2006-01-01

    This paper reports on an ongoing work in designing and developing a personalised search tool for teachers' online searching using Google search engine (repository) for the implementation and testing of the first research prototype.

  12. Design and Testing of a Prototype Pixellated CZT Detector and Shield for Hard X-Ray Astronomy

    OpenAIRE

    Bloser, P. F.; Grindlay, J.E.; Narita, T; Jenkins, J. A.

    1999-01-01

    We report on the design and laboratory testing of a prototype imaging CZT detector intended for balloon flight testing in April 2000. The detector tests several key techniques needed for the construction of large-area CZT arrays, as required for proposed hard X-ray astronomy missions. Two 10 mm x 10 mm x 5 mm CZT detectors, each with a 4 x 4 array of 1.9 mm pixels on a 2.5 mm pitch, will be mounted in a ``flip-chip'' fashion on a printed circuit board carrier card; the detectors will be place...

  13. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  14. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of Innov

  15. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  16. PHYSICS RESULTS OF THE NSLS-II LINAC FRONT END TEST STAND

    Energy Technology Data Exchange (ETDEWEB)

    Fliller R. P.; Gao, F.; Yang, X.; Rose, J.; Shaftan, T.; Piel, C

    2012-05-20

    The Linac Front End Test Stand (LFETS) was installed at the Source Development Laboratory (SDL) in the fall of 2011 in order to test the Linac Front End. The goal of these tests was to test the electron source against the specifications of the linac. In this report, we discuss the results of these measurements and the effect on linac performance.

  17. Conceptual Design of Front Ends for the Advanced Photon Source Multi-bend Achromats Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Jaski, Y.; Westferro, F.; Lee, S. H.; Yang, B.; Abliz, M.; Ramanathan, M.

    2016-07-27

    The proposed Advanced Photon Source (APS) upgrade from a double-bend achromats (DBA) to multi-bend achromats (MBA) lattice with ring energy change from 7 GeV to 6 GeV and beam current from 100 mA to 200 mA poses new challenges for front ends. All front ends must be upgraded to fulfill the following requirements: 1) handle the high heat load from two insertion devices in either inline or canted configuration, 2) include a clearing magnet in the front end to deflect and dump any electrons in case the electrons escape from the storage ring during swap-out injection with the safety shutters open, 3) incorporate the next generation x-ray beam position monitors (XBPMs) into the front end to meet the new stringent beam stability requirements. This paper presents the evaluation of the existing APS front ends and standardizes the insertion device (ID) front ends into two types: one for the single beam and one for the canted beams. The conceptual design of high heat load front end (HHLFE) and canted undulator front end (CUFE) for APS MBA upgrade is presented.

  18. First prototypes of two-tier avalanche pixel sensors for particle detection

    Science.gov (United States)

    Pancheri, L.; Brogi, P.; Collazuol, G.; Dalla Betta, G.-F.; Ficorella, A.; Marrocchesi, P. S.; Morsani, F.; Ratti, L.; Savoy-Navarro, A.

    2017-02-01

    In this paper, we present the implementation and preliminary evaluation of a new type of silicon sensor for charged particle detection operated in Geiger-mode. The proposed device, formed by two vertically-aligned pixel arrays, exploits the coincidence between two simultaneous avalanche events to discriminate between particle-triggered detections and dark counts. A proof-of-concept two-layer sensor with per-pixel coincidence circuits was designed and fabricated in a 150 nm CMOS process and vertically integrated through bump bonding. The sensor includes a 48×16 pixel array with 50 μ m × 75 μ m pixels. This work describes the sensor architecture and reports a selection of results from the characterization of the avalanche detectors in the two layers. Detectors with an active area of 43 × 45 μ m2 have a median dark count rate of 3 kHz at 3.3 V excess bias and a breakdown voltage non-uniformity lower than 20 mV.

  19. Testbeam results of irradiated ams H18 HV-CMOS pixel sensor prototypes

    CERN Document Server

    INSPIRE-00211411; Braccini, S.; Casse, G.; Chen, H.; Chen, K.; Di Bello, F.A.; Ferrere, D.; Golling, T.; Gonzalez-Sevilla, S.; Iacobucci, G.; Kiehn, M.; Lanni, F.; Liu, H.; Meng, L.; Merlassino, C.; Miucci, A.; Muenstermann, D.; Nessi, M.; Okawa, H.; Peric, I.; Rimoldi, M.; Ristic, B.; Vicente Barrero Pinto, M.; Vossebeld, J.; Weber, M.; Weston, T.; Wu, W.; Xu, L.; Zaffaroni, E.

    2016-01-01

    HV-CMOS pixel sensors are a promising option for the tracker upgrade of the ATLAS experiment at the LHC, as well as for other future tracking applications in which large areas are to be instrumented with radiation-tolerant silicon pixel sensors. We present results of testbeam characterisations of the $4^{\\mathrm{th}}$ generation of Capacitively Coupled Pixel Detectors (CCPDv4) produced with the ams H18 HV-CMOS process that have been irradiated with different particles (reactor neutrons and 18 MeV protons) to fluences between $1\\cdot 10^{14}$ and $5\\cdot 10^{15}$ 1-MeV-n$_\\textrm{eq}$/cm$^2$. The sensors were glued to ATLAS FE-I4 pixel readout chips and measured at the CERN SPS H8 beamline using the FE-I4 beam telescope. Results for all fluences are very encouraging with all hit efficiencies being better than 97% for bias voltages of $85\\,$V. The sample irradiated to a fluence of $1\\cdot 10^{15}$ n$_\\textrm{eq}$/cm$^2$ - a relevant value for a large volume of the upgraded tracker - exhibited 99.7% average hit ...

  20. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  1. Development of hybrid photon detectors with integrated silicon pixel readout for the RICH counters of LHCb

    CERN Document Server

    Alemi, M; Formenti, F; Gys, Thierry; Piedigrossi, D; Puertolas, D; Rosso, E; Snoeys, W; Wyllie, Ken H

    1999-01-01

    We report on the ongoing work towards a hybrid photon detector with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment at the Large Hadron Collider at CERN. The photon detector is based $9 on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a fast, binary readout chip with matching pixel electronics. The $9 performance of a half-scale prototype is presented, together with the developments and tests of a full-scale tube with large active area. Specific requirements for pixel front-end and readout electronics in LHCb are outlined, and $9 recent results obtained from pixel chips applicable to hybrid photon detector design are summarized.

  2. Characterization of proton irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A., E-mail: alessandro.larosa@cern.ch [CERN, Geneva 23, CH-1211 (Switzerland); Boscardin, M. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Cobal, M. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Dalla Betta, G.-F. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Da Via, C. [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom); Darbo, G. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Gallrapp, C. [CERN, Geneva 23, CH-1211 (Switzerland); Gemme, C. [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Huegging, F.; Janssen, J. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Micelli, A. [Universita degli Studi di Udine and INFN Trieste, Gruppo Collegato di Udine, Via delle Scienze 208, I-33100 Udine (Italy); Pernegger, H. [CERN, Geneva 23, CH-1211 (Switzerland); Povoli, M. [DISI, Universita degli Studi di Trento and INFN Padova, Gruppo Collegato d Trento, Via Sommarive 14, I-38123 Trento (Italy); Wermes, N. [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany); Zorzi, N. [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

    2012-07-21

    In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non-optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 Multiplication-Sign 10{sup 15}n{sub eq}cm{sup -2}, while requiring bias voltages in the order of 100 V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

  3. Characterization of proton irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

    CERN Document Server

    La Rosa, A; Cobal, M; Betta, G -F Dalla; Da Via, C; Darbo, G; Gallrapp, C; Gemme, C; Huegging, F; Janssen, J; Micelli, A; Pernegger, H; Povoli, M; Wermes, N; Zorzi, N

    2012-01-01

    In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Some assemblies of these sensors featuring different columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FEI3 read-out chip were irradiated up to large proton fluences and tested in laboratory with radioactive sources. In spite of the non optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 x 10**15 neq/cm2, while requiring bias voltages in the order of 100 V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

  4. Functional characterization of irradiated 3D-DDTC pixel sensor prototypes fabricated at FBK

    CERN Document Server

    La Rosa, A; Cobal, M; Da Viá, C; Betta, G F Dalla; Darbo, G; Gallrapp, C; Gemme, C; Huegging, F; Janssen, J; Micelli, A; Pernegger, H; Povoli, M; Wermes, N; Zorzi, N

    2011-01-01

    In this paper we discuss results relevant to 3D Double-Side Double Type Column (3D-DDTC) pixel sensors fabricated at FBK (Trento, Italy) and oriented to the ATLAS upgrade. Several assemblies of these sensors featuring various columnar electrode configurations (2, 3, or 4 columns per pixel) and coupled to the ATLAS FE-I3 read-out chip were irradiated up to large particle fluences and tested in laboratory with radioactive sources. In spite of the non optimized columnar electrode overlap, sensors exhibit reasonably good charge collection properties up to an irradiation fluence of 2 10**15 neq/cm2 while requiring bias voltages of at most 160V. Sensor operation is further investigated by means of TCAD simulations which can effectively explain the basic mechanisms responsible for charge loss after irradiation.

  5. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  6. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  7. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  8. Front-end ASIC for pixilated wide bandgap detectors

    Science.gov (United States)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  9. The high dynamic range pixel array detector (HDR-PAD): Concept and design

    Energy Technology Data Exchange (ETDEWEB)

    Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.; Becker, Julian; Tate, Mark W. [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Gruner, Sol M., E-mail: smg26@cornell.edu [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States)

    2016-07-27

    Experiments at storage ring light sources as well as at next-generation light sources increasingly require detectors capable of high dynamic range operation, combining low-noise detection of single photons with large pixel well depth. XFEL sources in particular provide pulse intensities sufficiently high that a purely photon-counting approach is impractical. The High Dynamic Range Pixel Array Detector (HDR-PAD) project aims to provide a dynamic range extending from single-photon sensitivity to 10{sup 6} photons/pixel in a single XFEL pulse while maintaining the ability to tolerate a sustained flux of 10{sup 11} ph/s/pixel at a storage ring source. Achieving these goals involves the development of fast pixel front-end electronics as well as, in the XFEL case, leveraging the delayed charge collection due to plasma effects in the sensor. A first prototype of essential electronic components of the HDR-PAD readout ASIC, exploring different options for the pixel front-end, has been fabricated. Here, the HDR-PAD concept and preliminary design will be described.

  10. Front-end ASICs for high-energy astrophysics in space

    Science.gov (United States)

    Gevin, O.; Limousin, O.; Meuris, A.

    2016-07-01

    In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a

  11. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  12. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  13. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  14. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  15. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  16. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    Abstract: Most industries face continuing pressures from rising R&D costs, shortening product lifecycles and global competition. These challenges have increased the focus on shortening development times, which again puts pressure on the efficiency of front end innovation (FEI). In the attempt...... to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...

  17. Design and Testing of a Prototype Pixellated CZT Detector and Shield for Hard X-Ray Astronomy

    CERN Document Server

    Bloser, P F; Narita, T; Jenkins, J A

    1999-01-01

    We report on the design and laboratory testing of a prototype imaging CZT detector intended for balloon flight testing in April 2000. The detector tests several key techniques needed for the construction of large-area CZT arrays, as required for proposed hard X-ray astronomy missions. Two 10 mm x 10 mm x 5 mm CZT detectors, each with a 4 x 4 array of 1.9 mm pixels on a 2.5 mm pitch, will be mounted in a ``flip-chip'' fashion on a printed circuit board carrier card; the detectors will be placed 0.3 mm apart in a tiled configuration such that the pixel pitch is preserved across both crystals. One detector is eV Products high-pressure Bridgman CZT, and the other is IMARAD horizontal Bridgman material. Both detectors are read out by a 32-channel VA-TA ASIC controlled by a PC/104 single-board computer. A passive shield/collimator surrounded by plastic scintillator surrounds the detectors on five sides and provides a ~45 deg field of view. The background spectrum recorded by this instrument will be compared to that...

  18. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  19. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken into acco...... into account. The accuracy of the expressions has been verified by using Touchstone simulator. The agreement between the calculated and simulated front end performances is very good....

  20. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  1. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  2. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    OpenAIRE

    Bin You; Bo Yang; Xuan Wen; Liangyu Qu

    2013-01-01

    A new ultrahigh frequency radio frequency identification (UHF RFID) reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS) circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both th...

  3. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N...... in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates....

  4. Experience from design, prototyping and production of a DC-DC conversion powering scheme for the CMS Phase-1 Pixel Upgrade

    CERN Document Server

    Feld, Lutz Werner; Klein, Katja; Lipinski, Martin; Preuten, Marius; Rauch, Max Philip; Schmitz, Stefan Antonius; Wlochal, Michael

    2016-01-01

    The CMS pixel detector will be exchanged during the technical stop 2016/2017. To allow the new pixel detector to be powered with the legacy cable plant and power supplies, a novel powering scheme based on DC-DC conversion is employed. After the successful conclusion of an extensive development and prototyping phase, mass production of 1800 DC-DC converters as well as motherboards and other power PCBs has now been completed. This contribution reviews the lessons learned from the development of the power system for the Phase-1 pixel detector, and summarizes the experience from the production phase.

  5. Experience from design, prototyping and production of a DC-DC conversion powering scheme for the CMS Phase-1 Pixel Upgrade

    Science.gov (United States)

    Feld, Lutz; Karpinski, Waclaw; Klein, Katja; Lipinski, Martin; Preuten, Marius; Rauch, Max; Schmitz, Stefan; Wlochal, Michael

    2017-02-01

    The CMS pixel detector will be replaced during the technical stop 2016/2017. To allow the new pixel detector to be powered with the legacy cable plant and power supplies, a novel powering scheme based on DC-DC conversion will be employed. After the successful conclusion of an extensive development and prototyping phase, mass production of 1800 DC-DC converters as well as motherboards and other power PCBs has now been completed. This contribution reviews the lessons learned from the development of the power system for the Phase-1 pixel detector, and summarizes the experience gained from the production phase.

  6. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  7. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  8. The FE-I4 Pixel Readout Chip and the IBL Module

    CERN Document Server

    Barbero, Marlon; Backhaus, Malte; Fang, Xiaochao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Krueger, Hans; Kruth, Andre; Wermes, Norbert; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Sasha; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; Garcia-Sciveres, Maurice; Jensen, Frank; Lu, Yunpeng; Mekkaoui, Abderrezak; Gromov, Vladimir; Kluit, Ruud; Schipper, Jan David; Zivkovic, Vladimir; Grosse-Knetter, Joern; Weingarten; Kocian, Martin

    2011-01-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the “Insertable B-Layer” project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  9. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  10. A radiation hard bipolar monolithic front-end readout

    CERN Document Server

    Baschirotto, A; Cappelluti, I; Castello, R; Cermesoni, M; Gola, A; Pessina, G; Pistolesi, E; Rancoita, P G; Seidman, A

    1999-01-01

    A fast bipolar monolithic charge sensitive preamplifier (CSP), implemented in the monolithic 2 mu m BiCMOS technology (called HF2CMOS) was designed and built in a quad monolithic chip. Studies of radiation effects in the CSP $9 performance, from non-irradiated and up to neutron irradiation of 5.3*10/sup 14/ n/cm/sup 2/, have confirmed that the use of bipolar npn transistors is suitable for the radiation level of the future LHC collider environment. The CSP $9 presents a new circuit solution for obtaining adequate slew rate performances which results in an integral linearity better than 0.8554330n 5 V at 20 ns of shaping time, regardless of the bias current selected for the CSP. This way $9 the bias current of the CSP can be set for optimizing the power dissipation with respect to series and parallel noise, especially useful when the CSP is put in a radiation environment. A prototype test with a novel monolithic 20 ns $9 time constant RC-CR shaper, capable to sum up four inputs has been also realized, featurin...

  11. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    Science.gov (United States)

    Ceresa, D.; Kaplon, J.; Francisco, R.; Caratelli, A.; Kloukinas, K.; Marchioro, A.

    2016-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC . The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100 mW/cm2. The choice of a 65 nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40 MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100 μm × 1446 μm, providing 7.65 mm2 of segmented active area. Measurements of the analog front-end characteristics closely match the simulations and confirm the consumption of < 30 μA per pixel. Front-end characterization and irradiation results up to 150 MRad are also reported.

  12. A new Data Acquisition System for the CMS Phase 1 Pixel Detector

    CERN Document Server

    Kornmayer, Andreas

    2016-01-01

    A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ s...

  13. A new data acquisition system for the CMS Phase 1 pixel detector

    Science.gov (United States)

    Kornmayer, A.

    2016-12-01

    A new pixel detector will be installed in the CMS experiment during the extended technical stop of the LHC at the beginning of 2017. The new pixel detector, built from four layers in the barrel region and three layers on each end of the forward region, is equipped with upgraded front-end readout electronics, specifically designed to handle the high particle hit rates created in the LHC environment. The DAQ back-end was entirely redesigned to handle the increased number of readout channels, the higher data rates per channel and the new digital data format. Based entirely on the microTCA standard, new front-end controller (FEC) and front-end driver (FED) cards have been developed, prototyped and produced with custom optical link mezzanines mounted on the FC7 AMC and custom firmware. At the same time as the new detector is being assembled, the DAQ system is set up and its integration into the CMS central DAQ system tested by running the pilot blade detector already installed in CMS. This work describes the DAQ system, integration tests and gives an outline for the activities up to commissioning the final system at CMS in 2017.

  14. Construction and testing of a large scale prototype of a silicon tungsten electromagnetic calorimeter for a future lepton collider

    CERN Document Server

    Rouëné,J

    2013-01-01

    The CALICE collaboration is preparing large scale prototypes of highly granular calorimeters for detectors to be operated at a future linear electron positron collider. After several beam campaigns at DESY, CERN and FNAL, the CALICE collaboration has demonstrated the principle of highly granular electromagnetic calorimeters with a first prototype called physics prototype. The next prototype, called technological prototype, addresses the engineering challenges which come along with the realisation of highly granular calorimeters. This prototype will comprise 30 layers where each layer is composed of four 9_9 cm2 silicon wafers. The front end electronics is integrated into the detector layers. The size of each pixel is 5_5 mm2. This prototype enter sits construction phase. We present results of the first layers of the technological prototype obtained during beam test campaigns in spring and summer 2012. According to these results the signal over noise ratio of the detector exceeds the R&D goal of10:1.

  15. Custom single-photon avalanche diode with integrated front-end for parallel photon timing applications.

    Science.gov (United States)

    Cammi, C; Panzeri, F; Gulinatti, A; Rech, I; Ghioni, M

    2012-03-01

    Emerged as a solid state alternative to photo multiplier tubes (PMTs), single-photon avalanche diodes (SPADs) are nowadays widely used in the field of single-photon timing applications. Custom technology SPADs assure remarkable performance, in particular a 10 counts/s dark count rate (DCR) at low temperature, a high photon detection efficiency (PDE) with a 50% peak at 550 nm and a 30 ps (full width at half maximum, FWHM) temporal resolution, even with large area devices, have been obtained. Over the past few years, the birth of novel techniques of analysis has led to the parallelization of the measurement systems and to a consequent increasing demand for the development of monolithic arrays of detectors. Unfortunately, the implementation of a multidimensional system is a challenging task from the electrical point of view; in particular, the avalanche current pick-up circuit, used to obtain the previously reported performance, has to be modified in order to enable high parallel temporal resolution, while minimizing the electrical crosstalk probability between channels. In the past, the problem has been solved by integrating the front-end electronics next to the photodetector, in order to reduce the parasitic capacitances and consequently the filtering action on the current signal of the SPAD, leading to an improvement of the timing jitter at higher threshold. This solution has been implemented by using standard complementary metal-oxide-semiconductor (CMOS) technologies, which, however, do not allow a complete control on the SPAD structure; for this reason the intrinsic performance of CMOS SPADs, such as DCR, PDE, and afterpulsing probability, are worse than those attainable with custom detectors. In this paper, we propose a pixel architecture, which enables the development of custom SPAD arrays in which every channel maintains the performance of the best single photodetector. The system relies on the integration of the timing signal pick-up circuit next to the

  16. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr

    CERN Document Server

    Rescia, S; Newcomer, F M; Dressnandt, N

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper with a (RC)2 – CR response to replace the existing ATLAS Liquid Argon readout for use at SLHC. IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished by utilization of a single stage, low noise, wide dynamic range preamp connected to a dual range shaper. The low noise of the preamp (~.01nA / √Hz) is achieved by utilizing the process Silicon Germanium bipolar transistors. The relatively high voltage rating of the npn transistors is exploited to allow a gain of 650V/A. With this gain the equivalent input voltage noise requirement on the shaper to about 2.2nV/ √Hz. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. The shaper outputs are designed to be compatible with the 130nm CMOS ADC being develo...

  17. AMIC: an expandable integrated analog front-end for light distribution moments analysis

    Energy Technology Data Exchange (ETDEWEB)

    Spaggiari, M; Herrero, V; Lerche, C W; Aliaga, R; Monzo, J M; Gadea, R, E-mail: michele.spaggiari@gmail.com [Instituto de Instrumentacion para Imagen Molecular (I3M), Universidad Politecnica de Valencia, Camino de Vera, 46022, Valencia (Spain)

    2011-01-15

    In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector's outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented.

  18. A 4 μW/Ch analog front-end module with moderate inversion and power-scalable sampling operation for 3-D neural microsystems.

    Science.gov (United States)

    Al-Ashmouny, Khaled M; Chang, Sun-Il; Yoon, Euisik

    2012-10-01

    We report an analog front-end prototype designed in 0.25 μm CMOS process for hybrid integration into 3-D neural recording microsystems. For scaling towards massive parallel neural recording, the prototype has investigated some critical circuit challenges in power, area, interface, and modularity. We achieved extremely low power consumption of 4 μW/channel, optimized energy efficiency using moderate inversion in low-noise amplifiers (K of 5.98 × 10⁸ or NEF of 2.9), and minimized asynchronous interface (only 2 per 16 channels) for command and data capturing. We also implemented adaptable operations including programmable-gain amplification, power-scalable sampling (up to 50 kS/s/channel), wide configuration range (9-bit) for programmable gain and bandwidth, and 5-bit site selection capability (selecting 16 out of 128 sites). The implemented front-end module has achieved a reduction in noise-energy-area product by a factor of 5-25 times as compared to the state-of-the-art analog front-end approaches reported to date.

  19. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  20. Exploiting jump-resonance hysteresis in silicon auditory front-ends for extracting speaker discriminative formant trajectories.

    Science.gov (United States)

    Aono, Kenji; Shaga, Ravi K; Chakrabartty, Shantanu

    2013-08-01

    Jump-resonance is a phenomenon observed in non-linear circuits where the amplitude of the output signal exhibits an abrupt jump when the frequency of the input signal is varied. For [Formula: see text] filters used in the design of analog auditory front-ends (AFEs), jump-resonance is generally considered to be undesirable and several techniques have been proposed in literature to avoid or alleviate this artifact. In this paper we explore the use of jump-resonance based hysteresis in [Formula: see text] band-pass filters for encoding speech formant trajectories. Using prototypes of silicon AFEs fabricated in a 0.5 μm CMOS process, we demonstrate the benefits of the proposed approach for extracting speaker discriminative features. These benefits are validated using speaker recognition experiments where consistent improvements in equal-error-rates (EERs) are achieved using the jump-resonance based features as compared to conventional features.

  1. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  2. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  3. Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements.

    Science.gov (United States)

    Smith, William A; Mogen, Brian J; Fetz, Eberhard E; Sathe, Visvesh S; Otis, Brian P

    2016-12-01

    Electrocorticography (ECoG) is an important area of research for Brain-Computer Interface (BCI) development. ECoG, along with some other biopotentials, has spectral characteristics that can be exploited for more optimal front-end performance than is achievable with conventional techniques. This paper optimizes noise performance of such a system and discusses an equalization technique that reduces the analog-to-digital converter (ADC) dynamic range requirements and eliminates the need for a variable gain amplifier (VGA). We demonstrate a fabricated prototype in 1p9m 65 nm CMOS that takes advantage of the presented findings to achieve high-fidelity, full-spectrum ECoG recording. It requires 1.08 μW over a 150 Hz bandwidth for the entire analog front end and only 7 bits of ADC resolution.

  4. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    Science.gov (United States)

    Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

    2016-12-01

    The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  5. Implementasi Analog Front End pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-03-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi  analog  front  end pada  pengaturan  kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  6. Design of the NSLS-II Linac Front End Test Stand

    Energy Technology Data Exchange (ETDEWEB)

    Fliller III, R.; Johanson, M.; Lucas, M.; Rose, J.; Shaftan, T.

    2011-03-28

    The NSLS-II operational parameters place very stringent requirements on the injection system. Among these are the charge per bunch train at low emittance that is required from the linac along with the uniformity of the charge per bunch along the train. The NSLS-II linac is a 200 MeV linac produced by Research Instruments Gmbh. Part of the strategy for understanding to operation of the injectors is to test the front end of the linac prior to its installation in the facility. The linac front end consists of a 100 kV electron gun, 500 MHz subharmonic prebuncher, focusing solenoids and a suite of diagnostics. The diagnostics in the front end need to be supplemented with an additional suite of diagnostics to fully characterize the beam. In this paper we discuss the design of a test stand to measure the various properties of the beam generated from this section. In particular, the test stand will measure the charge, transverse emittance, energy, energy spread, and bunching performance of the linac front end under all operating conditions of the front end.

  7. Prediction and control of front-end curvature in hot finish rolling process

    Directory of Open Access Journals (Sweden)

    Kyunghun Lee

    2015-11-01

    Full Text Available The purpose of this study is to predict the front-end curvature in hot strip finishing mills and to prevent it by controlling the rolling conditions. A theoretical model based on the slab method is developed for predicting the front-end curvature by taking into account the entrance angle of the strip, the friction condition and the back tension. To validate the developed theoretical model, the theoretically obtained curvature value is compared with the results of finite element analysis. Consequently, it is shown that the calculation results of the theoretical model are in good agreement with the measured results of the finite element analysis. Furthermore, a curvature control model based on geometrical and mathematical approaches that can reduce the front-end curvature by the control of the roll speed ratio of the upper to lower rolls is proposed. The proposed curvature control model is verified by finite element analysis, and it is shown that the front-end curvature can be reduced considerably using the proposed model. Therefore, it is concluded that the proposed control model for reducing the front-end curvature in a hot strip finishing mill can be used to improve the quality of the rolled product.

  8. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    Energy Technology Data Exchange (ETDEWEB)

    Prior, G. [Canterbury U.; Efthymiopoulos, I. [CERN; Stratakis, D. [Brookhaven; Neuffer, D. [Fermilab; Snopok, P. [Fermilab; Rogers, C. [Rutherford

    2013-06-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the front-end channel performance where the magnetic field direction has been altered compared to the baseline.

  9. Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

    CERN Document Server

    Kishishita, T; Hemperek, T; Lemarenko, M; Koch, M; Gronewald, M; Wermes, N

    2013-01-01

    This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via 40 cm Kapton flex and 12–15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output dat...

  10. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

  11. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... and tendencies in formal R&D partnering relations. This paper, however, focuses on collaboration between independent companies prior to such formal agreements as joint ventures or other contractual agreements. This first phase of the innovation process is often referred to as the Fuzzy Front-End (FFE......) and is traditionally seen as an intra-organizational process (Jongbae & David 2002;Kim & Wilemon 2002e;Qingyu & William 2001;Reid & de Brentani 2004a). As the innovation process becomes an interfirm-collaboration the management of the Fuzzy Front-End also changes and calls for new ways of collaboration...

  12. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  13. Preparation for the upgrade of CMS Hadron Endcap Calorimeter front-end

    Science.gov (United States)

    Bychkova, O. V.; Popova, E. V.; Parygin, P. P.; Bunin, P. D.; Kalinin, A. Yu

    2017-01-01

    The hadron endcap (HE) calorimeter is one of the major sections of CMS detector, used for measurement of the hadrons energy. Phase1 upgrade of the front-end electronics components in the HE calorimeter is being prepared, in particular to improve ability to handle increased pile-up and mitigate radiation damage of optical system in the high eta region. Tests of Phase1 HE Front-end system including new photo-sensors, silicon photomultipliers (SiPM), as well as new charge integrator encoder (QIE11) were performed in the Burn-in station in b904 at CERN. In this note, analysis and measurement results for the new generation front-end electronics components are presented.

  14. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  15. Front-end Electronics Test for the LHCb Muon Wire Chambers

    CERN Document Server

    Nobrega, R; Carboni, G; Massafferri, A; Santovetti, E

    2007-01-01

    This document describes the apparatus and procedures implemented to test Multi Wire Proportional Chambers (MWPC) after front-end assembly for the LHCb Muon Detector. Results of measurements of key noise parameters are also described. Given a fully equipped chamber, this system is able to diagnose every channel performing an analysis of front-end output drivers’ response and noise rate versus threshold. Besides, it allows to assess if the noise rate at the experiment threshold region is within appropriate limits. Aiming at an automatic, fast and user-friendly system for mass production tests of MWPC, the project has foreseen as well electronic identification of every chamber and front-end board, and data archiving in such a way to make it available to the Experiment Control System (ECS) while in operation.

  16. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  17. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS Design of an analog front-end for ambulatory biopotential measurement systems

    Science.gov (United States)

    Jiazhen, Wang; Jun, Xu; Lirong, Zheng; Junyan, Ren

    2010-10-01

    A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms (0.48-2000 Hz). The chip is fabricated via a SMIC 0.18 μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

  19. ALPIDE, the Monolithic Active Pixel Sensor for the ALICE ITS upgrade

    Science.gov (United States)

    Mager, M.

    2016-07-01

    A new 10 m2 inner tracking system based on seven concentric layers of Monolithic Active Pixel Sensors will be installed in the ALICE experiment during the second long shutdown of LHC in 2019-2020. The monolithic pixel sensors will be fabricated in the 180 nm CMOS Imaging Sensor process of TowerJazz. The ALPIDE design takes full advantage of a particular process feature, the deep p-well, which allows for full CMOS circuitry within the pixel matrix, while at the same time retaining the full charge collection efficiency. Together with the small feature size and the availability of six metal layers, this allowed a continuously active low-power front-end to be placed into each pixel and an in-matrix sparsification circuit to be used that sends only the addresses of hit pixels to the periphery. This approach led to a power consumption of less than 40 mWcm-2, a spatial resolution of around 5 μm, a peaking time of around 2 μs, while being radiation hard to some 1013 1 MeVneq /cm2, fulfilling or exceeding the ALICE requirements. Over the last years of R & D, several prototype circuits have been used to verify radiation hardness, and to optimize pixel geometry and in-pixel front-end circuitry. The positive results led to a submission of full-scale (3 cm×1.5 cm) sensor prototypes in 2014. They are being characterized in a comprehensive campaign that also involves several irradiation and beam tests. A summary of the results obtained and prospects towards the final sensor to instrument the ALICE Inner Tracking System are given.

  20. Muon capture in the front end of the IDS neutrino factory

    CERN Document Server

    Neuffer, D.; Prior, G.; Rogers, C.; Yoshikawa, C.

    2010-01-01

    We discuss the design of the muon capture front end of the neutrino factory International Design Study. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. For the International Design Study (IDS), a baseline design must be developed and optimized for an engineering and cost study. The design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  1. Alternative Muon Front-end for the International Design Study (IDS)

    CERN Document Server

    Alekou, A; Martini, M; Prior, G; Rogers, C; Stratakis, D; Yoshikawa, C; Zisman, M

    2010-01-01

    We discuss alternative designs of the muon capture front end of the Neutrino Factory International Design Study (IDS). In the front end, a proton bunch on a target creates secondary pions that drift into a capture channel, decaying into muons. A sequence of RF cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. This design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  2. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    Directory of Open Access Journals (Sweden)

    Bin You

    2013-01-01

    Full Text Available A new ultrahigh frequency radio frequency identification (UHF RFID reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both the sensitivity and detection range compared to the conventional designs.

  3. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...... be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  4. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...... be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  5. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture...... with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...

  6. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  7. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Energy Technology Data Exchange (ETDEWEB)

    Gevin, O.; Lemaire, O.; Lugiez, F. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Michalowska, A., E-mail: alicja.michalowska@cea.fr [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Baron, P. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Limousin, O. [CEA, Irfu, Service d' Astrophysique, Bat. 709 Orme des Merisiers, F-91191 Gif-sur-Yvette (France); Delagnes, E. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France)

    2012-12-11

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16 Multiplication-Sign 16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 {mu}m CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 {mu}W per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 {mu}s peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 Degree-Sign C.

  8. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Science.gov (United States)

    Gevin, O.; Lemaire, O.; Lugiez, F.; Michalowska, A.; Baron, P.; Limousin, O.; Delagnes, E.

    2012-12-01

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  9. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    CERN Document Server

    Sekiya, H; Kubo, H; Miuchi, K; Nagayoshi, T; Nishimura, H; Okada, Y; Orito, R; Takada, A; Takeda, A; Tanimori, T; Ueno, K

    2006-01-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of $6\\times6\\times20{\\rm mm}^3$ which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to readout every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of $^{137}$Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  10. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Science.gov (United States)

    Sekiya, H.; Hattori, K.; Kubo, H.; Miuchi, K.; Nagayoshi, T.; Nishimura, H.; Okada, Y.; Orito, R.; Takada, A.; Takeda, A.; Tanimori, T.; Ueno, K.

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6×6×20 mm3 which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6 mm) was clearly resolved by flood field irradiation of 137Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  11. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Energy Technology Data Exchange (ETDEWEB)

    Sekiya, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)]. E-mail: sekiya@cr.scphys.kyoto-u.ac.jp; Hattori, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Kubo, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Miuchi, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Nagayoshi, T. [Advanced Research Institute for Science and Engineering, Waseda University, 17 Kikui-cho, Shinjuku, Tokyo 162-0044 (Japan); Nishimura, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Okada, Y. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Orito, R. [Department of Physics, Graduate School of Science and Technology, Kobe University, 1-1 Rokkoudai, Nada, Kobe 657-8501 (Japan); Takada, A. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Takeda, A. [Kamioka Observatory, ICRR, University of Tokyo, 456 Higasi-mozumi, Hida-shi, Gifu 506-1205 (Japan); Tanimori, T. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Ueno, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6x6x20mm{sup 3} which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of {sup 137}Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  12. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which...

  13. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  14. Practices of a "green" front end of innovation; A gateway to environmental innovation

    NARCIS (Netherlands)

    Hassi, L.; Wever, R.

    2010-01-01

    Activities in the fuzzy front end of the innovation process (FFE) are the root of success for any company hoping to compete on the basis of innovations. Considering the importance of the FFE, it would seem logical to bring the environmental considerations already to the activities of the early stage

  15. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; Van Engelen, Jo; Achterkamp, Madolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to supp

  16. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, A.D.

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition o

  17. Managing inter-firm collaboration in the fuzzy front-end

    DEFF Research Database (Denmark)

    Jørgensen, Jacob; Bergenholtz, Carsten; Goduscheit, René Chester

    2011-01-01

    organisations in an innovation network are somewhat neglected in the literature. The aim of this paper is hence to address the challenges that an organisation faces when integrating a plurality of suppliers, customers and other organisations into the Fuzzy Front End of the innovation process....

  18. Understanding Managers Decision Making Process for Tools Selection in the Core Front End of Innovation

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.

    2011-01-01

    New product development (NPD) describes the process of bringing a new product or service to the market. The Fuzzy Front End (FFE) of Innovation is the term describing the activities happening before the product development phase of NPD. In the FFE of innovation, several tools are used to facilitate...

  19. Advances ,n Digital Front-End and Software RF Processing: Part I

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    One of the biggest technology trends in wireless broadband, radar, sonar, and broadcasting systems is software radio frequency processing and digital front-end. This trend encompasses a broad range of topics, from circuit design and signal processing to system integration. It includes digital up-conversion (DUC) and down-conversion (DDC), digital predistortion (DPD),

  20. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J.A.; Kooijman, P.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  1. Radiation hardness improvement of analog front-end microelectronic devices for particle accelerator

    Science.gov (United States)

    Miroshnichenko, A. G.; Rodin, A. S.; Bakerenkov, A. S.; Felitsyn, V. A.

    2016-10-01

    Series of schematic techniques for increasing radiation hardness of the current mirrors is developed. These techniques can be used for the design of analog front-end microelectronic devices based on the operational amplifiers. The circuit simulation of radiation degradation of current transmission coefficients was performed for various circuit solutions in LTSpice software.

  2. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  3. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  4. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo;

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing...

  5. Extracting whole short rotation trees with a skidder and a front-end loader

    Science.gov (United States)

    R. Spinelli; B.R. Hartsough

    2001-01-01

    We time-studied a Caterpillar 950F front-end loader and a Caterpillar 528 grapple skidder used to extract bunched whole trees to a landing in a short rotation Eucalyptus plantation. The loader was 40-60% more productive than the grapple skidder, depending on extraction distance. Alternatively, the single loader could both extract trees and handle the landing duties,...

  6. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Science.gov (United States)

    Chunhua, Wang; Minglin, Ma; Jingru, Sun; Sichun, Du; Xiaorong, Guo; Haizhen, He

    2011-02-01

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

  7. 2 MV Injector as the Elise Front-End and as an Experimental Facility

    Energy Technology Data Exchange (ETDEWEB)

    Yu, S S; Eylon, S; Henestroza, E; Peters, C; Reginato, L; Tauschwitz, A; Grote, D; Deadrick, F

    1999-12-07

    We report on progress in the preparation of the 2 MV Injector at LBNL as the front-end of Elise, and as a multi-purpose experimental facility for Heavy Ion Fusion beam dynamics studies. Recent advances on the performance and understanding of the injector are described, and some of the on-going experimental activities are summarized.

  8. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study aim

  9. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  10. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  11. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  12. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  13. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  14. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  15. Front-end XY-slits assembly for the SPring-8 undulator beamlines.

    Science.gov (United States)

    Oura, M; Sakurai, Y; Kitamura, H

    1998-05-01

    A front-end XY-slits assembly has been designed for the SPring-8 undulator beamlines. This assembly can handle the high heat flux from the undulator, its grazing-incidence L-shaped configuration employing an enhanced heat-transfer technology.

  16. Commissioning and operation of the FNAL front end injection line and ion sources

    Science.gov (United States)

    Karns, Patrick R.

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  17. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, Alberto

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition

  18. Performance of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon Pixel readout for Cherenkov ring detection

    CERN Document Server

    Alemi, M; Bibby, J H; Campbell, M; Duane, A; Easo, S; Gys, Thierry; Halley, A W; Piedigrossi, D; Puertolas, D; Rosso, E; Simmons, B; Snoeys, W; Websdale, David M; Wotton, S A; Wyllie, Ken H

    1999-01-01

    We report on the first test beam performance of a hybrid photon detector prototype, using binary readout electronics, intended for use in the ring imaging Cherenkov detectors of the LHCb experiment at the CERN Large Hadron Collider. The photon detector is based on a cross-focussed image intensifier tube geometry. The anode consists of a silicon pixel array bump-bonded to a binary readout chip with matching pixel electronics. The detector has been installed in a quarter-scale prototype vessel of the LHCb ring imaging Cherenkov system. Focussed ring images produced by 120 GeV/c negative pions traversing an air radiator have been recorded. The observed light yield and Cherenkov angle resolution are discussed.

  19. Performance of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout for Cherenkov ring detection

    Energy Technology Data Exchange (ETDEWEB)

    Alemi, M.; Barber, G.; Bibby, J.; Campbell, M.; Duane, A.; Easo, S.; Gys, T.; Halley, A.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Simmons, B.; Snoeys, W.; Websdale, D.; Wotton, S.; Wyllie, K

    1999-08-01

    We report on the first test beam performance of a hybrid photon detector prototype, using binary readout electronics, intended for use in the ring imaging Cherenkov detectors of the LHCb experiment at the CERN Large Hadron Collider. The photon detector is based on a cross-focussed image intensifier tube geometry. The anode consists of a silicon pixel array bump-bonded to a binary readout chip with matching pixel electronics. The detector has been installed in a quarter-scale prototype vessel of the LHCb ring imaging Cherenkov system. Focussed ring images produced by 120 GeV/c negative pions traversing an air radiator have been recorded. The observed light yield and Cherenkov angle resolution are discussed.

  20. Suppression of FM-to-AM modulation by polarizing fiber front end for high-power lasers.

    Science.gov (United States)

    Qiao, Zhi; Wang, Xiaochao; Fan, Wei; Li, Xuechun; Jiang, Youen; Li, Rao; Huang, Canhong; Lin, Zunqi

    2016-10-10

    FM-to-AM modulation is an important effect in the front end of high-power lasers that influences the temporal profile. Various methods have been implemented in standard-fiber and polarization-maintaining (PM)-fiber front ends to suppress the FM-to-AM modulation. To analyze the modulation in the front end, a theoretical model is established and detailed simulations carried out that show that the polarizing (PZ) fiber, whose fast axis has a large loss, can successfully suppress the modulation. Moreover, the stability of the FM-to-AM modulation can be improved, which is important for the front end to obtain a stable output. To verify the model, a PZ fiber front end is constructed experimentally. The FM-to-AM modulation, without any compensation, is less than 4%, whereas that of the PM fiber front end with the same structure is nearly 20%. The stability of the FM-to-AM modulation depth is analyzed experimentally and the peak-to-peak and standard deviation (SD) are 2% and 0.38%, respectively, over 3 h. The experimental results agree with the simulation results and both prove that the PZ fiber front end can successfully suppress the FM-to-AM conversion. The PZ fiber front end is a promising alternative for improving the performance of the front end in high-power laser facilities.

  1. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  2. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  3. CARIOCA : A Fast Binary Front-End Implemented in 0.25Pm CMOS using a Novel Current-Mode Technique for the LHCb Muon Detector

    CERN Multimedia

    2000-01-01

    The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF.

  4. The front-end electronics of the Spectrometer Telescope for Imaging X-Rays (STIX) on the ESA Solar Orbiter satellite

    Science.gov (United States)

    Grimm, O.; Bednarzik, M.; Commichau, V.; Graczyk, R.; Gröbelbauer, H. P.; Hurford, G.; Krucker, S.; Limousin, O.; Meuris, A.; Orleański, P.; Przepiórka, A.; Seweryn, K.; Skup, K.; Viertel, G.

    2012-12-01

    Solar Orbiter is an ESA mission to study the heliosphere in proximity to the Sun, scheduled for launch in January 2017. It carries a suite of ten instruments for comprehensive remote-sensing and in-situ measurements. The Spectrometer Telescope for Imaging X-Rays (STIX), one of the remote sensing instruments, images X-rays between 4 and 150keV using an Fourier technique. The angular resolution is 7 arcsec and the spectral resolution 1keV full-width-half-maximum at 6keV. X-ray detection uses pixelized Cadmium Telluride crystals provided by the Paul Scherrer Institute. The crystals are bonded to read-out hybrids developed by CEA Saclay, called Caliste-SO, incorporating a low-noise, low-power analog front-end ASIC IDeF-X HD. The crystals are cooled to -20°C to obtain very low leakage currents of less than 60pA per pixel, the prerequisite for obtaining the required spectral resolution. This article briefly describes the mission goals and then details the front-end electronics design and main challenges, resulting in part from the allocation limit in mass of 7kg and in power of 4W. Emphasis is placed on the design influence of the cooling requirement within the warm environment of a mission approaching the Sun to within the orbit of Mercury. The design for the long-term in-flight energy calibration is also explained.

  5. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  6. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  7. Development of a front end controller/heap manager for PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Allen, M.D.; Musrock, M.S.; Walker, J.W.; Britton, C.L. Jr.; Wintenberg, A.L.; Young, G.R.

    1996-12-31

    A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

  8. A MEMS-Based Power-Scalable Hearing Aid Analog Front End.

    Science.gov (United States)

    Deligoz, I; Naqvi, S R; Copani, T; Kiaei, S; Bakkaloglu, B; Sang-Soo Je; Junseok Chae

    2011-06-01

    A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.

  9. FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

    1989-05-01

    The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.

  10. Muon capture in the front end of the IDS neutrino factory

    CERN Document Server

    Neuffer, D; Prior, G; Rogers, C; Yoshikawa, C

    2012-01-01

    We discuss the design of the muon capture front end of the neutrino factory International Design Study. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then accelerated to high energy where their decays provide neutrino beams. For the International Design Study (IDS), a baseline design must be developed and optimized for an engineering and cost study. We present a baseline design that can be used to establish the scope of a future neutrino Factory facility.

  11. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  12. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing

    Directory of Open Access Journals (Sweden)

    Lin Hu

    2016-11-01

    Full Text Available The cognitive radio wireless sensor network (CR-WSN has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  13. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing.

    Science.gov (United States)

    Hu, Lin; Ma, Hong; Zhang, Hua; Zhao, Wen

    2016-11-25

    The cognitive radio wireless sensor network (CR-WSN) has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF) front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC) algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  14. A-3 dBm RF transmitter front-end for 802.11g application

    Institute of Scientific and Technical Information of China (English)

    Zhao Jinxin; Yan Jun; Shi Yin

    2013-01-01

    A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is-3 dBm while the corresponding EVM is-27 dB which is necessary for the 802.11 g standard of EVM at-25 dB.With the adopted gain control strategy the output power changes from-14.3 to-3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.

  15. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  16. Improvement of EEG Signal Acquisition: An Electrical Aspect for State of the Art of Front End

    Directory of Open Access Journals (Sweden)

    Ali Bulent Usakli

    2010-01-01

    Full Text Available The aim of this study is to present some practical state-of-the-art considerations in acquiring satisfactory signals for electroencephalographic signal acquisition. These considerations are important for users and system designers. Especially choosing correct electrode and design strategy of the initial electronic circuitry front end plays an important role in improving the system's measurement performance. Considering the pitfalls in the design of biopotential measurement system and recording session conditions creates better accuracy. In electroencephalogram (EEG recording electrodes, system electronics including filtering, amplifying, signal conversion, data storing, and environmental conditions affect the recording performance. In this paper, EEG electrode principles and main points of electronic noise reduction methods in EEG signal acquisition front end are discussed, and some suggestions for improving signal acquisition are presented.

  17. Software-defined radio with flexible RF front end for satellite maritime radio applications

    Science.gov (United States)

    Budroweit, Jan

    2016-09-01

    This paper presents the concept of a software-defined radio with a flexible RF front end. The design and architecture of this system, as well as possible application examples will be explained. One specific scenario is the operation in maritime frequency bands. A well-known service is the Automatic Identification System (AIS), which has been captured by the DLR mission AISat, and will be chosen as a maritime application example. The results of an embedded solution for AIS on the SDR platform are presented in this paper. Since there is an increasing request for more performance on maritime radio bands, services like AIS will be enhanced by the International Association of Marine Aids to Navigation and Lighthouse Authorities (IALA). The new VHF Data Exchange Service (VDES) shall implement a dedicated satellite link. This paper describes that the SDR with a flexible RF front end can be used as a technology demonstration platform for this upcoming data exchange service.

  18. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  19. General-Purpose Front End for Real-Time Data Processing

    Science.gov (United States)

    James, Mark

    2007-01-01

    FRONTIER is a computer program that functions as a front end for any of a variety of other software of both the artificial intelligence (AI) and conventional data-processing types. As used here, front end signifies interface software needed for acquiring and preprocessing data and making the data available for analysis by the other software. FRONTIER is reusable in that it can be rapidly tailored to any such other software with minimum effort. Each component of FRONTIER is programmable and is executed in an embedded virtual machine. Each component can be reconfigured during execution. The virtual-machine implementation making FRONTIER independent of the type of computing hardware on which it is executed.

  20. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999......, Steven & Burly, 2003, and Vernorn et al., 2008) and that innovation strategies play a central role in optimization of innovation (Clark & Wheelwright, 1995; Cottam et al., 2001; Morgan & Berthon, 2008). Innovation strategies are suggested in literature (e.g. Page, 1993; Oke, 2002; Adams et al., 2006......; Igartua, 2010) as a facilitator of innovation and may therefore also be targeted at FEI support. The pharmaceutical industry has experienced a worldwide decline in the number of applications for new molecular entities to regulatory agencies since 1997. Therefore high pressures are put on pharmaceutical...

  1. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  2. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  3. Common front end systems for Space Shuttle and Space Station control centers at Johnson Space Center

    Science.gov (United States)

    Uljon, Linda; Muratore, John

    1993-03-01

    In the beginning of the fiscal year 1992, the development organizations of Johnson Space Center (JSC) were poised to begin two major projects: the Space Station Control Center and the refurbishment of the telemetry processing area of the Space Shuttle Mission Control Center. A study team established that a common front end concept could be used and could reduce development costs for both projects. A standard processor was defined to support most of the front end functions of both control centers and supports a consolidation of control positions which effectively reduces operations cost. This paper defines that common concept and describes the progress that has been made in development of the Consolidated Communications Facility (CCF) during the past year.

  4. All-Dielectric Photonic-Assisted Radio Front-End Technology

    Science.gov (United States)

    Ayazi, Hossein Ali

    The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

  5. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  6. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  7. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  8. A Simplified and Accurate Front-End Electronics Chain for Timing RPCs

    CERN Document Server

    Blanco, A; Fonte, Paulo J R; Ferreira-Marques, R; Gobbi, A; Policarpo, Armando

    2000-01-01

    Recent advances in electronics and construction techniques have pushed the timing resolution of Resistive Plate Chambers below 50 ps sigma with detection efficienciesclose to 99% for MIPs. In this paper we describe a new front-end electronics chain for accurate time and charge measurement in these devices, having in view a possibleapplication in ALICE's T0 counter.(Abstract only available, full text to follow).

  9. The analog front-end section of the BaBar silicon vertex tracker readout IC

    Energy Technology Data Exchange (ETDEWEB)

    Manfredi, P.F.; Leona, A.; Mandelli, E.; Re, V.; Svelto, F. [Pavia Univ. (Italy). Dipartimento di Elettronica]|[INFN, Sezione di Pavia, Via Bassi 6, 27100 Pavia (Italy); Kipnis, I.; Luo, L.; Momayezi, M.; Nyman, M.; Pedrali-Noy, M.; Roe, N. [E.O. Lawrence Berkeley National Laboratory, Berkeley, CA 94720 (United States)

    1998-02-01

    This paper describes the evolution in the analog section of the vertex detector readout chip for the BaBar experiment. In order to optimize its behaviour, an intermediate chip reproducing the analog part alone was developed and tested. It provided some useful design hints that provided the basis for the final conception of the analog front-end as it is now operational in the complete BaBar chip. (orig.). 6 refs.

  10. A front-end automation tool supporting design, verification and reuse of SOC

    Institute of Scientific and Technical Information of China (English)

    严晓浪; 余龙理; 王界兵

    2004-01-01

    This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

  11. Compensation of impedance meters when using an external front-end amplifier

    OpenAIRE

    Torrents Dolz, Josep M.; Pallàs Areny, Ramon

    2002-01-01

    Four-terminal impedance meters based on pseudo-bridges yield unexpected uncertainties when using high-contact-impedance electrodes. Adding a front-end amplifier to the impedance meter and rearranging the connection of the meter terminals overcome the contact impedance problem. However, because the compensation provisions in the instrument are meant to compensate only impedance residuals of test fixtures, by either an open/short or an open/short/load correction procedure, the external fr...

  12. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    CERN Document Server

    Simi, G; Batignani, G; Bettarini, S; Bondioli, M; Boscardin, M; Bosisio, L; Dalla Betta, Gian Franco; Dittongo, S; Forti, F; Giorgi, M; Gregori, P; Manghisoni, M; Morganti, M; Ratti, L; Re, V; Rizzo, G; Speziali, V; Zorzi, N

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

  13. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  14. Trends in the design of front-end systems for room temperature solid state detectors

    OpenAIRE

    Manfredi, Pier F.; Re, Valerio

    2003-01-01

    The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor...

  15. An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

    OpenAIRE

    Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

    2015-01-01

    An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the D...

  16. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  17. Web-based DAQ systems: connecting the user and electronics front-ends

    Science.gov (United States)

    Lenzi, Thomas

    2016-12-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  18. Implementing method of optimum front-end conditioner based on Butterworth filter

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The front-end conditioner is an essential part of digital systems of nuclear spectrometer, which functions in two ways: (1) prevents saturation of the subsequent ADC; (2) limits the bandwidth of frequency to realize anti-aliasing. To realize the above-mentioned functions, an optimum front-end conditioner for a resistive feedback charge-sensitive preamplifier is designed. In the conditioner, the pole-zero compensation (P/Z compensation) technique was used to effectively filter signals from the preamplifier. The Butterworth filter was improved after the pole-zero position was optimally set up to shape the wave of output, which tallied with the whole system. The front-end conditioner can resolve the aberration of waveform of nuclear signals in a regular Butterworth filter. Compared with the traditional triple-pole filtering circuitry, the circuitry of this conditioner is more compact and flexible.Moreover, its output waveform is more symmetrical and the signal-to-noise ratio (SNR) is higher. The improvement in the resolution of spectrometer is also significant.

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  20. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  1. Front-end electronics for accurate energy measurement of double beta decays

    Energy Technology Data Exchange (ETDEWEB)

    Gil, A., E-mail: alejandro.gil@ific.uv.es [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Diaz, J.; Gomez-Cadenas, J.J. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Herrero, V. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Rodriguez, J.; Serra, L. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Toledo, J.; Esteve, R.; Monzo, J.M. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Monrabal, F.; Yahlali, N. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain)

    2012-12-11

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-{beta} decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  2. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  3. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  4. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Ye, J; The ATLAS collaboration

    2010-01-01

    Optical data links are used in detector front-end electronics readout systems of experiments in the Tevatron and the LHC. Optical links in high energy particle physics experiments usually have special requirements such as radiation tolerance, ultra high reliability and low power dissipation. These requirements are often not met by commercial components which are designed for applications in non-radiation, accessible (for maintenance) environment, and for multi-vendor systems so the parts must comply with certain standards. Future HEP experiments such as the upgrades for the sLHC call for optical links with ultra high data bandwidth, higher radiation tolerance and ultra low power dissipation. To meet these challenges and in particular those in the upgrade for the ATLAS Liquid Argon Calorimeter readout that calls for an optical link system of 100 Gbps for each front-end board, we adopted a full custom front-end electronics system design based on application specific integrated circuits. Reported here are the de...

  5. FBI Fingerprint Image Capture System High-Speed-Front-End throughput modeling

    Energy Technology Data Exchange (ETDEWEB)

    Rathke, P.M.

    1993-09-01

    The Federal Bureau of Investigation (FBI) has undertaken a major modernization effort called the Integrated Automated Fingerprint Identification System (IAFISS). This system will provide centralized identification services using automated fingerprint, subject descriptor, mugshot, and document processing. A high-speed Fingerprint Image Capture System (FICS) is under development as part of the IAFIS program. The FICS will capture digital and microfilm images of FBI fingerprint cards for input into a central database. One FICS design supports two front-end scanning subsystems, known as the High-Speed-Front-End (HSFE) and Low-Speed-Front-End, to supply image data to a common data processing subsystem. The production rate of the HSFE is critical to meeting the FBI`s fingerprint card processing schedule. A model of the HSFE has been developed to help identify the issues driving the production rate, assist in the development of component specifications, and guide the evolution of an operations plan. A description of the model development is given, the assumptions are presented, and some HSFE throughput analysis is performed.

  6. Anode Front-End Electronics for the Cathode Strip Chambers of the CMS Endcap Muon Detector

    CERN Document Server

    Ferguson, Thomas; Vorobev, I; Bondar, Nikolai; Golyash, Alexander; Sedov, Vladislav

    2001-01-01

    The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3 x 2.5 m2) and for the large input capacitance (up to 200 pf). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2 - 3 ns). The del ay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This note presents the anode front-end electro...

  7. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  8. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  9. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226662; The ATLAS collaboration

    2016-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  10. Effects of vehicle impact velocity, vehicle front-end shapes on pedestrian injury risk.

    Science.gov (United States)

    Han, Yong; Yang, Jikuang; Mizuno, Koji; Matsui, Yasuhiro

    2012-09-01

    This study aimed at investigating the effects of vehicle impact velocity, vehicle front-end shape, and pedestrian size on injury risk to pedestrians in collisions with passenger vehicles with various frontal shapes. A series of parametric studies was carried out using 2 total human model for safety (THUMS) pedestrian models (177 and 165 cm) and 4 vehicle finite element (FE) models with different front-end shapes (medium-size sedan, minicar, one-box vehicle, and sport utility vehicle [SUV]). The effects of the impact velocity on pedestrian injury risk were analyzed at velocities of 20, 30, 40, and 50 km/h. The dynamic response of the pedestrian was investigated, and the injury risk to the head, chest, pelvis, and lower extremities was compared in terms of the injury parameters head injury criteria (HIC), chest deflection, and von Mises stress distribution of the rib cage, pelvis force, and bending moment diagram of the lower extremities. Vehicle impact velocity has the most significant influence on injury severity for adult pedestrians. All injury parameters can be reduced in severity by decreasing vehicle impact velocities. The head and lower extremities are at greater risk of injury in medium-size sedan and SUV collisions. The chest injury risk was particularly high in one-box vehicle impacts. The fracture risk of the pelvis was also high in one-box vehicle and SUV collisions. In minicar collisions, the injury risk was the smallest if the head did not make contact with the A-pillar. The vehicle impact velocity and vehicle front-end shape are 2 dominant factors that influence the pedestrian kinematics and injury severity. A significant reduction of all injuries can be achieved for all vehicle types when the vehicle impact velocity is less than 30 km/h. Vehicle designs consisting of a short front-end and a wide windshield area can protect pedestrians from fatalities. The results also could be valuable in the design of a pedestrian-friendly vehicle front-end shape

  11. Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

    Science.gov (United States)

    Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

    2011-02-01

    This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

  12. Front-end chip for Silicon Photomultiplier detectors with pico-second Time-of-Flight resolution

    Science.gov (United States)

    Stankova, V.; Briggl, K.; Chen, H.; Gil, A.; Harion, T.; Munwes, Y.; Shen, W.; Schultz-Coulon, H.-C.

    2016-07-01

    A mixed-mode readout Application Specific Integrated Circuit (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM) for medical imaging and particle physics applications. The STiC3 is a 64-channel chip, with fully differential analog front-end for cross-talk and electronic noise immunity. The time and charge information from the SiPM signals are encrypted into two time stamps generated by integrated Time to Digital Converter (TDC) modules with 50 ps time binning. The TDC data is stored in an internal memory and transferred to a PC via a 160 MBit/s serial link using an 8/10 bit encoding. The chip provides an input bias tuning in a range of 0-900 mV to compensate the breakdown voltage variation of individual SiPMs. The TDC jitter together with the digital part is around 37 ps. A Coincidence Time Resolution (CTR) of 213.6 ps FWHM has been obtained with 3.1 × 3.1 × 15m2 LYSO:Ce scintillator crystals and Hamamatsu SiPM matrices (S12643-050CN(X)). Characterization measurements with the chip and its integration into the external plate of the EndoTOFPET-US prototype are presented.

  13. An ultrafast front-end ASIC for APD array detectors in X-ray time-resolved experiments

    Science.gov (United States)

    Zhou, Yang-Fan; Li, Qiu-Ju; Liu, Peng; Fan, Lei; Xu, Wei; Tao, Ye; Li, Zhen-Jie

    2017-06-01

    An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain output driver. A prototype chip has been designed and fabricated using 0.13 μm CMOS technology with a chip size of 1.3 mm × 1.9 mm. The electrical characterizations of the circuit demonstrate a very good intrinsic time resolution (rms) on the output pulse leading edge, with the test result better than 30 ps for high input signal charges (> 75 fC) and better than 100 ps for low input signal charges (30-75 fC), while keeping a low power consumption of 5 mW per complete channel. Supported by the National Natural Science Foundation of China (11605227), High Energy Photon Source-Test Facility Project, and the State Key Laboratory of Particle Detection and Electronics. This research used resources of the BSRF.

  14. The Shunt-LDO regulator to power the upgraded ATLAS pixel detector

    CERN Document Server

    Gonella, L; Hügging, F; Krüger, H; Wermes, N

    2012-01-01

    The shunt-LDO regulator is a new regulator concept which combines a shunt and a Low Drop-Out (LDO) regulator. Designed as an improved shunt regulator to match the needs of serially powered detector systems, it can also be used as a pure LDO regulator for general application in powering schemes requiring linear regulation. The flexibility of the design makes the shunt-LDO regulator a good candidate for use in the powering schemes envisaged for the upgrades of the ATLAS pixel detector. Two shunt-LDO regulators integrated in the prototype of the next ATLAS pixel front-end chip, the FE-I4A, are used to demonstrate the feasibility of the proposed powering solutions.

  15. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland)

    2015-07-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  16. THz semiconductor-based front-end receiver technology for space applications

    Science.gov (United States)

    Mehdi, Imran; Siegel, Peter

    2004-01-01

    Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

  17. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  18. A wide dynamics neutron monitor with BF3 and logarithmic amplifier based front-end electronics

    OpenAIRE

    2010-01-01

    In this paper a wide dynamics neutron monitor based on BF3 neutron detector is described. The detector is used in current mode, and a front-end electronics based on a logarithmic amplifier is used in order to have a measurement capability ranging over many decades. The system has been calibrated at Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamics ranging ov...

  19. Balancing research and organizational capacity building in front-end project design

    DEFF Research Database (Denmark)

    Hjortsø, Carsten Nico Portefée; Meilby, Henrik

    2013-01-01

    phase of RCB partnerships and examine how they influence the balance between performing collaborative research and developing general organizational capacity. Data collection was based on a survey (n = 25), and individual interviews and focus group discussions with 17 Danish project managers from...... is more complex. We identify 11 specific factors influencing front-end project management related to structure, process and relationship, and we theorize about how these factors influence the choice between research and more general capacity development activities. Copyright © 2013 John Wiley & Sons, Ltd...

  20. SYSTEMATIC METHOD TO GENERATE NEW IDEAS IN FUZZY FRONT END USING TRIZ

    Institute of Scientific and Technical Information of China (English)

    TAN Runhua; MA Lihui; YANG Bojun; SUN Jianguang

    2008-01-01

    The obstacle for idea generation in fuzzy front end (FFE) is difficult to apply knowledge in different fields for designers. Theory of inventive problem solving TRIZ and computer-aided innovation systems (CAIs) which are TRIZ-base software systems with a knowledge base provide a framework for knowledge application in different fields. The major methods in TRIZ are selected, which have four types. The problems to be solved for each method are summarized and mapping from the problems to the methods is given. Systematic method with eight paths to integrate the methods and problems is formed. A case study shows the idea generation in FFE using the integrated method step by step.

  1. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    This paper addresses the design, implementation and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design comprises commercial-of-the-shelf modules and newly purpose-built components at a centre frequency of 435 MHz with 20......% relative bandwidth. The transmitter uses two amplifiers combined in parallel to generate more than >128 W peak power, with system >60% PAE and 47 dB in-band to out-of-band signal ratio. The four channel receiver features digitally controlled variable gain to achieve more than 100 dB dynamic range, 2.4 d...

  2. HTS filter and front-end subsystem for GSM1800 wireless base station

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    The first HTS front-end subsystem for wireless base station in China was developed. This demonstration system, which aims at the application in GSM1800 mobile communication base station, consists of a single RF path, i.e. one filter and one LNA, integrated with the pulse tube cooler. The subsystem works at a pass band of 1710-1785 MHz with a gain of 18 dB and at a temperature of 70 K. The accomplishment of such a demonstration subsystem can boost the development of HTS commercial subsystem.

  3. Effect of vehicle front end profiles leading to pedestrian secondary head impact to ground.

    Science.gov (United States)

    Gupta, Vishal; Yang, King H

    2013-11-01

    Most studies of pedestrian injuries focus on reducing traumatic injuries due to the primary impact between the vehicle and the pedestrian. However, based on the Pedestrian Crash Data Study (PCDS), some researchers concluded that one of the leading causes of head injury for pedestrian crashes can be attributed to the secondary impact, defined as the impact of the pedestrian with the ground after the primary impact of the pedestrian with the vehicle. The purpose of this study is to understand if different vehicle front-end profiles can affect the risk of pedestrian secondary head impact with the ground and thus help in reducing the risk of head injury during secondary head impact with ground. Pedestrian responses were studied using several front-end profiles based off a mid-size vehicle and a SUV that have been validated previously along with several MADYMO pedestrian models. Mesh morphing is used to explore changes to the bumper height, bonnet leading-edge height, and bonnet rear reference-line height. Simulations leading up to pedestrian secondary impact with ground are conducted at impact speeds of 40 and 30 km/h. In addition, three pedestrian sizes (50th, 5th and 6yr old child) are used to enable us to search for a front-end profile that performs well for multiple sizes of pedestrians, not just one particular size. In most of the simulations, secondary ground impact with pedestrian head/neck/shoulder region occurred. However, there were some front-end profiles that promoted secondary ground impact with pedestrian lower extremities, thus avoiding pedestrian secondary head impact with ground. Previous pedestrian safety research work has suggested the use of active safety methods, such as 'pop up hood', to reduce pedestrian head injury during primary impact. Accordingly, we also conducted simulations using a model with the hood raised to capture the effect of a pop-up hood. These simulations indicated that even though pop-up hood helped reducing the head injury

  4. Investigation of characteristics and radiation hardness of the Beetle 1.0 front-end chip

    CERN Document Server

    Van Bakel, N; Jans, E; Klous, S; Verkooijen, H

    2001-01-01

    Noise characteristics of the Beetle 1.0 front-end chip have been investigated as a function of input capacitance. Values for the equivalent noise charge and ballastic deficit have been extracted. Amplification and pulse shape have been studied by varying the bias settings over a wide range. Results are compared with simulations that include realistic impedances at the input and output. The chip has been subjected to 10 Mrad of radiation. Subsequently, its behaviour is measured again and compared to that preceeding the irradiation. Observed radiation damage effects are discussed.

  5. A front-end ASIC design for non-uniformity correction

    Science.gov (United States)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  6. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  7. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

    DEFF Research Database (Denmark)

    di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere;

    2016-01-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point......). The designs that minimally satisfy the specifications are based on an 8-b 30-MSPS Nyquist converter and a single-bit third-order 240-MSPS modulator, with an SNR for the LNA in both cases equal to 64 dB. The mean lateral FWHM and CR are 2.4% and 7.1% lower for the architecture compared with the Nyquistrate one...

  8. Noise limits in a front-end system based on time-over-threshold signal processing

    CERN Document Server

    Manfredi, P F; Mandelli, E; Perazzo, A; Re, V

    2000-01-01

    An analog signal processor based on the Time-over-Threshold (ToT) range compression is employed in the front-end section of the readout chip of the microstrip vertex detector for the BaBar experiment. The paper, after describing the circuit solutions that have been adopted to optimize the ToT operation, focuses on the noise aspects of the ToT processor. Comparisons are made between the signal-to-noise ratio in the linear processor preceding the ToT circuit and that obtained at the output of the entire analog channel including the ToT function.

  9. Simulation of wind power with front-end converter into interconnected grid system

    Directory of Open Access Journals (Sweden)

    Sharad W. Mohod

    2009-09-01

    Full Text Available In the growing electricity supply industry and open access market for electricity worldwide, renewable sources are getting added into the grid system. This affects the grid power quality. To assess the impact on grid due to wind energy integration, the knowledge of electrical characteristic of wind turbine and associated control equipments are required. The paper presents a simulation set-up for wind turbine in MATLAB / SIMULINK, with front end converter and interconnected system. The presented control scheme provides the wind power flow to the grid through a converter. The injected power in the system at the point of common coupling is ensured within the power quality norms.

  10. Testing of the front-end hybrid circuits for the CMS Tracker upgrade

    Science.gov (United States)

    Gadek, T.; Blanchot, G.; Honma, A.; Kovacs, M.; Raymond, M.; Rose, P.

    2017-01-01

    The upgrade of the CMS Tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high-density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  11. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  12. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  13. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Science.gov (United States)

    Lombigit, L.; Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-01

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  14. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  15. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions.

  16. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    OpenAIRE

    al., H. Albrecht et

    2004-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns...

  17. Impact of Spectral Filter on Phase Modulation Pulse in Fiber Front End System

    Institute of Scientific and Technical Information of China (English)

    LI Jing; JING Feng; WANG Jian-Jun; XU Dang-Peng; LIN Hong-Huan; GENG Yuan-Chao; LI Ming-Zhong; DENG Ying; ZHU Na; ZHANG Rui

    2011-01-01

    The transmission characteristics of phase modulation pulse transmitted through the filter in the power amplifier are investigated theoretically and experimentally. The narrow bandpass filter can induce large temporal modula-tion depth for the phase modulation pulse and induce double amplitude modulation(AM)if the frequency shift is lower than half bandwidth of the signal spectrum. We should choose a wider bandwidth filter to minimize the impact of the filter on the output pulse and suppress the amplified spontaneous emission(ASE) for the power fiber amplifier. These results are of benefit to the design of the fiber front end system.

  18. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  19. Compact Agile Antenna Concept Utilizing Reconfigurable Front End for Wireless Communications

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Jagielski, Ole; Svendsen, Simon

    2014-01-01

    that separates the Tx and Rx chain throughout the front end (FE). The complexity of the FE is reduced dramatically by replacing the duplex filters with tunable filters and closely integrating the tunable antennas in the FE, providing filtering which can be used to lower requirements for the tunable filters....... For this purpose, very small narrow-band antennas are designed, which can cover 1710–2170 MHz by using tunable capacitors. Simulations and measurements of the antenna concept are carried out in the proposed FE architecture, serving as a proof of concept....

  20. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2016-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  1. Development of ATLAS Liquid Argon Calorimeter front-end electronics for the HL-LHC

    Science.gov (United States)

    Liu, T.

    2017-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5–7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter cells at 40–80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented in this paper.

  2. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    Liu, Tiankuan; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  3. Architectural modeling of pixel readout chips Velopix and Timepix3

    NARCIS (Netherlands)

    Poikela, T.; Plosila, J.; Westerlund, T.; Buytaert, J.; Campbell, M.; Llopart, X.; Plackett, R.; Wyllie, K.; van Beuzekom, M.; Gromov, V.; Kluit, R.; Zappon, F.; Zivkovic, V.; Brezina, C.; Desch, K.; Fang, X.; Kruth, A.

    2012-01-01

    We examine two digital architectures for front end pixel readout chips, Velopix and Timepix3. These readout chips are developed for tracking detectors in future high energy physics experiments. They must incorporate local intelligence in pixels for time-over-threshold measurement and sparse readout.

  4. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  5. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  6. Unified analytical expressions for calculating resonant frequencies, transimpedances, and equivalent input noise current densities of tuned receiver front ends

    OpenAIRE

    1992-01-01

    Unified analytical expressions have been derived for calculating the resonant frequencies, transimpedance and equivalent input noise current densities of the four most widely used tuned optical receiver front ends built with FETs and p-i-n diodes. A more accurate FET model has been used to improve the accuracy of the analysis. The Miller capacitance has been taken into account, and its impact on the performances of the tuned front ends has been demonstrated. The accuracy of the expressions ha...

  7. Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

    Science.gov (United States)

    2016-09-01

    PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION by Chew K. Tan...PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION 5. FUNDING NUMBERS 6. AUTHOR... ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION Chew K. Tan Military Expert 6, Republic of Singapore Navy B.E. (Hons), University of New

  8. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet...

  9. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicate

  10. Numerical study of a magnetically insulated front-end channel for a neutrino factory

    Directory of Open Access Journals (Sweden)

    Diktys Stratakis

    2011-01-01

    Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

  11. Top Ten Reasons for DEOX as a Front End to Pyroprocessing

    Energy Technology Data Exchange (ETDEWEB)

    B.R. Westphal; K.J. Bateman; S.D. Herrmann

    2007-11-01

    A front end step is being considered to augment chopping during the treatment of spent oxide fuel by pyroprocessing. The front end step, termed DEOX for its emphasis on decladding via oxidation, employs high temperatures to promote the oxidation of UO2 to U3O8 via an oxygen carrier gas. During oxidation, the spent fuel experiences a 30% increase in lattice structure volume resulting in the separation of fuel from cladding with a reduced particle size. A potential added benefit of DEOX is the removal of fission products, either via direct release from the broken fuel structure or via oxidation and volatilization by the high temperature process. Fuel element chopping is the baseline operation to prepare spent oxide fuel for an electrolytic reduction step. Typical chopping lengths range from 1 to 5 mm for both individual elements and entire assemblies. During electrolytic reduction, uranium oxide is reduced to metallic uranium via a lithium molten salt. An electrorefining step is then performed to separate a majority of the fission products from the recoverable uranium. Although DEOX is based on a low temperature oxidation cycle near 500oC, additional conditions have been tested to distinguish their effects on the process.[1] Both oxygen and air have been utilized during the oxidation portion followed by vacuum conditions to temperatures as high as 1200oC. In addition, the effects of cladding on fission product removal have also been investigated with released fuel to temperatures greater than 500oC.

  12. Instrumentation of a Track Trigger with Double Buffer Front-End Architecture

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The planned high luminosity upgrade for the LHC (SLHC), will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. We describe a possible design which splits the level-1 trigger into a two-level system, where the first level, using only calorimetry and muon chambers, defines regions of interest in the tracker from which to extract information for a second, refined trigger. The use of a two-buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency will be s...

  13. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  14. Characterization of RF front-ends by long-tail pulse response

    Science.gov (United States)

    Mazzaro, Gregory J.; Ranney, Kenneth I.

    2010-04-01

    The recognition of unauthorized communications devices at the entry-point of a secure location is one way to guard against the compromise of sensitive information by wireless transmission. Such recognition may be achieved by backscatter x-ray and millimeter-wave imaging; however, implementation of these systems is expensive, and the ability to image the contours of the human body has raised privacy concerns. In this paper, we present a cheaper and less-invasive radio-frequency (RF) alternative for recognizing wireless communications devices. Characterization of the device-under-test (DUT) is accomplished using a stepped-frequency radar waveform. Single-frequency pulses excite resonance in the device's RF front-end. Microsecond periods of zero-signal are placed between each frequency transition to listen for the resonance. The stepped-frequency transmission is swept through known communications bands. Reception of a long-tail decay response between active pulses indicates the presence of a narrowband filter and implies the presence of a front-end circuit. The frequency of the received resonance identifies its communications band. In this work, cellular-band and handheld-radio filters are characterized.

  15. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  16. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  17. Towards a smart Holter system with high performance analogue front-end and enhanced digital processing.

    Science.gov (United States)

    Du, Leilei; Yan, Yan; Wu, Wenxian; Mei, Qiujun; Luo, Yu; Li, Yang; Wang, Lei

    2013-01-01

    Multiple-lead dynamic ECG recorders (Holter) play an important role in the earlier detection of various cardiovascular diseases. In this paper, we present the first several steps towards a 12-lead Holter system with high-performance AFE (Analogue Front-End) and enhanced digital processing. The system incorporates an analogue front-end chip (ADS1298 from TI), which has not yet been widely used in most commercial Holter products. A highly-efficient data management module was designated to handle the data exchange between the ADS1298 and the microprocessor (STM32L151 from ST electronics). Furthermore, the system employs a Field Programmable Gate Array (Spartan-3E from Xilinx) module, on which a dedicated real-time 227-step FIR filter was executed to improve the overall filtering performance, since the ADS1298 has no high-pass filtering capability and only allows limited low-pass filtering. The Spartan-3E FPGA is also capable of offering further on-board computational ability for a smarter Holter. The results indicate that all functional blocks work as intended. In the future, we will conduct clinical trials and compare our system with other state-of-the-arts.

  18. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  19. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  20. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    Science.gov (United States)

    Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

    1995-02-01

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

  1. An ultra low-power front-end IC for wearable health monitoring system.

    Science.gov (United States)

    Yu-Pin Hsu; Zemin Liu; Hella, Mona M

    2016-08-01

    This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

  2. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo

    2014-11-21

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  3. An instrumentation amplifier as a front-end for a four-electrode bioimpedance measurement.

    Science.gov (United States)

    Zagar, T; Krizaj, D

    2007-08-01

    The performance of a monolithic instrumentation amplifier used as an interface for a four-electrode bioimpedance measurement is examined with a commercially available impedance meter based on an auto-balancing bridge. The errors due to particularities in the input stage of the impedance meter, when used without a front-end, were several orders of magnitude higher than the measured quantity. The analysis was performed on an electrical circuit model of the skin and electrodes over a frequency range of 20 Hz to 1 MHz. The achieved accuracy with balanced electrode impedances for the frequencies up to 100 kHz can be below 0.2% for impedance magnitude and 0.1 degrees for impedance phase, which is within the specified basic accuracy range of the LCR-meter used for the measurements. At frequencies above 100 kHz the errors are increasing and are higher than the LCR-meter's basic accuracy. This study indicates that use of an instrumentation amplifier as a front-end with the particular LCR-meter can significantly improve the measurement accuracy of the four-electrode bioimpedance measurement at low frequencies.

  4. BORA a front end board, with local intelligence, for the RICH detector of the Compass collaboration

    CERN Document Server

    Baum, G; Bradamante, Franco; Bressan, A; Colavita, A A; Crespo, M; Costa, S; Dalla Torre, S; Fauland, P; Finger, M H; Fratnik, Fabio; Giorgi, M A; Gobbo, B; Grasso, A; Lamanna, M; Martin, A; Menon, G I; Panzieri, D; Schiavon, R P; Tessarotto, F; Zanetti, A M

    1999-01-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as to be part of a computer network that connects several similar boards of the detector with a PC...

  5. Implementation of re-configurable Digital front end module of MIMO-OFDM module using NCO

    Directory of Open Access Journals (Sweden)

    Veena M.B.

    2011-09-01

    Full Text Available This paper focuses on FPGA implementation of Reconfigurable Digital Front end MIMO-OFDM module. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. Unlike the conventional OFDM based systems, the Numerically Controlled Oscillators (NCO is used for mapping modulated data onto the sub carriers. The use of NCO in the MIMO-OFDM system reduces the resource utilization of the design on FPGA along with reduced power consumption. The major modules that were designed, which constitute the digital front end module, are Quadrature Phase Shift Keying (QPSK modulator/demodulator, 16-Quadrature Amplitude Modulation (QAM modulator/demodulator and NCOs. Each of the modules was tested for their functionality by developing corresponding test benches. In order to achieve real time reconfigurability of the proposed architecture, the proposed approach is realized on FPGAs optimizing area, power and speed. Reconfigurability of the proposed approach is dependent upon user requirement. Hence the proposed approach can support future generation communication technologies that are based on MIMO-OFDM.

  6. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    Science.gov (United States)

    Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

    2008-08-01

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector.

  7. The next generation Front-End Controller for the Phase-I Upgrade of the CMS Hadron Calorimeters

    Science.gov (United States)

    Costanza, F.; Behrens, U.; Campbell, A.; Karakaya, T.; Martens, I.; Melzer-Pellmann, I. A.; Sahin, M. O.

    2017-03-01

    The next generation Front-End Controller (ngFEC) is the system responsible for slow and fast control within the Phase-I Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μTCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the front-end electronics through six GBT links. The latency of the fast control signals is fixed across power cycles. Even if the direct link to a front-end module is broken, a redundancy scheme ensures a successful communication using the link to the neighboring front-end module. Thanks to the ngFEC all front-end modules can be remotely programmed using the JTAG standard protocol. The CCM server software interfaces the ngFEC to the Detector Control System which constantly monitors voltages and temperatures on the front-end electronics. This document reviews the characteristics and the development status of the ngFEC.

  8. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement

  9. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-09-02

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  10. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  11. ATLAS ITk Pixel detector

    CERN Document Server

    Gemme, Claudia; The ATLAS collaboration

    2016-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

  12. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  13. Studies toward a Candidate IDS Neutrino Factory Front-End Configuration

    CERN Document Server

    Neuffer, David

    2012-01-01

    A front end scenario for the IDS neutrino factory is presented. The scenario is based on the Study 2A example for capture, bunching and phase-energy rotation of muons from a proton source for a neutrino factory, and the goal is the capture of a maximal number of muons in a string of 201.25 MHz rf bunches. We present a candidate release scenario that is somewhat shorter than the Study 2A example and its parameters are optimized for smaller magnetic fields and gradients. We consider the variation of performance with achievable gradient, obtaining acceptable capture with reduced gradients. We also consider variation in production target performance, and develop the specifications toward the practical requirements of the cost study.

  14. An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

    Institute of Scientific and Technical Information of China (English)

    WANG Min; ZHANG Xiao; ZHANG Chun-feng; CAO Mao-yong; LI Cai-fang; KONG Hui-min; QIN Feng-ju; YAN Yu-qin

    2007-01-01

    Abstract.Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here,a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end ( AFE), while a computer ( Pentium Ⅲ ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

  15. Front-end signal analysis of the transverse feedback system for SSRF

    Institute of Scientific and Technical Information of China (English)

    HAN Lifeng; YUAN Renxian; YU Luyang; YE Kairong

    2008-01-01

    Multi-bunch instabilities degrade beam quality through increased beam emittance, energy spread and even cause beam loss. A feedback system is used to suppress multi-bunch instabilities associated with resistive wall of the beam ducts, cavity-like structures, and trapped ions. A digital TFS (Transverse Feedback System) is in construction at the SSRF (Shanghai Synchrotron Radiation Facility), which is based on the latest generation of FPGA (Field Programmable Gate Array) processor. Before we get such FPGA digital board, investigation and simulation of the front-end were done in the first place. The signal flow was analyzed by SystemView. Construction and optimization of the entire system is our next goal.

  16. Key differences and similarities in ways of managing and supporting radical pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2015-01-01

    The purpose of this paper is to explore how Front End Innovation (FEI) is supported and managed among companies of different nationality within the context of pharmaceutical R&D. The present study is carried out in order to contribute to the development of a clearer understanding of active...... of the Danish and US based pharmaceutical company, H. Lundbeck A/S, and a comparative study including five European and American pharmaceutical companies. The findings from the study reveal a number of similarities and differences in innovation management and FEI support of radical projects and among...... the different nationalities. This presents propositions of important aspects to consider in facilitation of radical FEI in general and in multinational pharmaceutical companies. In addition, proposals are made for a global study of innovation management and FEI support including Chinese and other Asian...

  17. Thermal analysis of the first canted-undulator front-end components at SSRF

    Energy Technology Data Exchange (ETDEWEB)

    Xu, Zhongmin, E-mail: xuzhongmin@sinap.ac.cn; Feng, Xinkang; Wang, Naxiu; Wu, Guanyuan; Zhang, Min; Wang, Jie

    2015-02-21

    The performance of three kinds of masks: pre-mask, splitter mask and fixed mask-photon shutter, used for the first canted-undulator front end under heat loads at SSRF, is studied. Because these components are shared with two beamlines, the X-rays from both dual undulators and bending magnets can strike on them. Under these complicated conditions, they will absorb much more thermal power than when they operate in usual beamline. So thermal and stress analysis is indispensable for their mechanical design. The method of applying the non-uniform power density using Ansys is presented. During thermal stress analysis, the normal operation or the worst possible case is considered. The finite element analyses results, such as the maximum temperature of the body and the cooling wall and the maximum stress of these components, show the design of them is reasonable and safe.

  18. Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

    Science.gov (United States)

    Kleczek, Rafal

    2016-12-01

    The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

  19. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N......-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients....... A non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study...

  20. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  1. A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

    Science.gov (United States)

    Singh, Harjit; Loach, James; Poon, Alan

    2012-10-01

    One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.

  2. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  3. Review of input stages used in front end electronics for particle detectors

    CERN Document Server

    Kaplon, J

    2015-01-01

    In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

  4. Understanding the Front-end of Large-scale Engineering Programs

    DEFF Research Database (Denmark)

    Lucae, Sebastian; Rebentisch, Eric; Oehmen, Josef

    2014-01-01

    from large cost overruns. Significant problems in program execution can be traced back to practices performed, or more frequently not performed, in the so-called “fuzzy front end” of the program. The lack of sufficient and effective efforts in the early stages of a program can result in unstable......, to propose a model for the front-end of large-scale engineering programs based on a review of existing, suitable models in literature and to better understand the complexity drivers that are impeding reliable planning and common planning mistakes made in large-scale engineering programs......., unclear and incomplete requirements, unclear roles and responsibilities within the program organization, insufficient planning, and unproductive tensions between program management and systems engineering. This study intends to clarify the importance of up-front planning to improve program performance...

  5. ANALOG FRONT-END ELECTRONICS FOR BEAM POSITION MEASUREMENT ON THE BEAM HALO MEASUREMENT

    Energy Technology Data Exchange (ETDEWEB)

    R.B. SHURTER; T.J. COTE; J.D. GILPATRICK

    2001-06-01

    Enhancements have been made to the log-ratio analog front-end electronics based on the Analog Devices 8307 logarithmic amplifier as used on the LEDA accelerator. The dynamic range of greater than 85 dB, has been extended to nearly the full capability of the AD8307 from the previous design of approximately 65 dB through the addition of a 350 MHz band-pass filter, careful use of ground and power plane placement, signal routing, and power supply bypassing. Additionally, selection of high-isolation RF switches (55dB) has been an integral part of a new calibration technique, which is fully described in another paper submitted to this conference. Provision has also been made for insertion of a first-stage low-noise amplifier for using the circuit under low-signal conditions.

  6. ANALOG FRONT-END ELECTRONICS FOR BEAM POSITION MEASUREMENT ON THE BEAM HALO MEASUREMENT

    Energy Technology Data Exchange (ETDEWEB)

    Shurter, R. B. (Robert B.); Cote, T. J. (Thomas J.); Gilpatrick, J. D. (John Douglas)

    2001-01-01

    Enhancements have been made to the log-ratio analog front-end electronics based on the Analog Devices 8307 logarithmic amplifier as used on the LEDA accelerator. The dynamic range of greater than 85 dB, has been extended to nearly the full capability of the AD8307 from the previous design of approximately 65 dB through the addition of a 350 MHz band-pass filter, careful use of ground and power plane placement, signal routing, and power supply bypassing. Additionally, selection of high-isolation RF switches (55dB) has been an integral part of a new calibration technique, which is fully described in another paper submitted to this conference. Provision has also been made for insertion of a first-stage low-noise amplifier for using the circuit under low-signal conditions.

  7. Multi-channel front-end board for SiPM readout

    Science.gov (United States)

    Auger, M.; Ereditato, A.; Goeldi, D.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Weber, M. S.

    2016-10-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias for the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The signal-to-noise ratio of 12 is attained for the first photo-electron peak. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  8. Ionization Readout Electronics for SuperCDMS SNOLAB Employing a HEMT Front-End

    Science.gov (United States)

    Partridge, R.

    2014-09-01

    The SuperCDMS SNOLAB experiment seeks to deploy 200 kg of cryogenic Ge detectors employing phonon and ionization readout to identify dark matter interactions. One of the design challenges for the experiment is to provide amplification of the high impedance ionization signal while minimizing power dissipation and noise. This paper describes the design and expected performance of the ionization readout being developed for an engineering model of the SuperCDMS SNOLAB Ge Tower System. The readout features the use of a low-noise HEMT front end transistor operating at 4 K to achieve a power dissipation of 100 W per channel, local grounding to minimize noise injection, and biasing circuitry that allows precise control of the HEMT operating point.

  9. An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

    Institute of Scientific and Technical Information of China (English)

    LIU Dong-sheng; ZOU Xue-cheng; YANG Qiu-ping; XIONG Ting-wen

    2006-01-01

    The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) transponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD)protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

  10. Developments for the upgrade of the CMS HCAL front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Baden, D [Univ. of Maryland, College Park, MD 20742 (United States); Frahm, E; Mans, J [Univ. of Minnesota, Minneapolis, MN 55455 (United States); Freeman, J; Grassi, T; Los, S; Shaw, T; Whitmore, J; Zimmerman, T [FERMILAB, Batavia, IL 60510 (United States); Tully, C, E-mail: tullio.grassi@cern.c [Princeton University, Princeton NJ 08544 (United States)

    2010-11-15

    We present a scheme to upgrade the CMS HCAL front-end electronics in 2015-16. The HCAL upgrade is required to handle a major luminosity increase of LHC which is expected for 2017. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy in a harsh environment which is constrained by the existing system. The proposed solutions span from chip level to system level. They include the development of a new ADC ASIC, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design and improvements in the overall architecture.

  11. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  12. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Acqua, A.; Hansen, M.; Lofstedt, B.; Vanuxem, J.P. (CERN, Geneva (Switzerland)); Svensson, C.; Yuan, J. (Univ. of Linkoeping (Sweden). Dept. of Physics and Measurement Technology); Hentzell, H. (Univ. of Linkoeping (Sweden). Center for Industrial Microelectronics and Materials Technology); Alippi, C.; Breveglieri, L.; Dadda, L.; Piuri, V.; Salice, F.; Sami, M.; Stefanelli, R. (Sezione INFN, Pavia, Milano (Italy). Dept. di Ellettronica); Cattaneo, P.; Fumagalli, G.; Goggi, V.G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Fisica Nucleare); Brigati, S.; Gatti, U.; Maloberti, F.; Torelli, G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Electronica); Carlson, P.; Fuglesang, C.; Kerek, A. (Manne Siegbahn Inst. of Physics, Stockholm (Sweden)); Appelquist, G.; Berglund, S.; Bohm, C.; Yamdagni, N. (Univ. of Stockholm (Sweden)); Sundblad, R. (SiCon AB, Linkoeping (Sweden))

    1993-08-01

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.

  13. Harmonic Mitigated Front End Three Level Diode Clamped High Frequency Link Inverter by Using MCI Technique

    Directory of Open Access Journals (Sweden)

    Sreedhar Madichetty

    2014-02-01

    Full Text Available In this paper it proposes a high efficient soft-switching scheme based on zero-voltage-switching (ZVS and zero-current-switching(ZCS principle operated with a simple auxiliary circuit extended range for the front-end isolated DC-AC-DC-AC high power converter with an three phase three level diode clamped multi level inverter by using Minority Charge Carrier inspired optimization technique (MCI with Total Harmonic Distortion(THD,Switching losses, Selective harmonic elimination maintaining with its fundamental as an objective function. Input to the inverter is obtained by the photo voltaic cells and with battery bank. The switching scheme is optimized by MCI technique, analyzed and executed in Matlab and implemented with a digital signal processor (DSP .Experimental results with different loads have observed and shows its effectives, robustness of the applied technique.

  14. A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

    Directory of Open Access Journals (Sweden)

    Eric Bharucha

    2014-11-01

    Full Text Available When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

  15. Single-current-sensor-based active front-end-converter-fed four quadrants induction motor drive

    Indian Academy of Sciences (India)

    JOSEPH KIRAN BANDA; AMIT KUMAR JAIN

    2017-08-01

    Induction motor (IM) is a workhorse of the industry, whose dynamics can be modified close to that of a separately excited DC machine by field-oriented control technique, which is commonly known as vector control of induction machine. This paper presents a complete performance of the field-oriented control of IM drive in all four quadrants with a single-current-sensor-based active front end converter whose work is to regulate DC link voltage, draw pure sinusoidal currents at unity power factor and to facilitate bi-directional power flow between the grid and the drive. The entire system is completely modelled in MATLAB/SIMULINK and the results are discussed in detail. The vector control analogy of the back to back converters is highlighted along with the experimental results of field-oriented control of induction machine using a dsPIC30F6010A digital signal controller.

  16. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  17. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  18. Conductive Cooling of SDD and SSD Front-End Chips for ALICE

    CERN Document Server

    Van den Brink, A; Daudo, F; Feofilov, G A; Godisov, O N; Giraudo, G; Igolkin, S N; Kuijer, P; Nooren, G J L; Swichev, A; Tosello, F

    2001-01-01

    We present analysis, technology developments and test results of the heat drain system of the SDD and SSD front-end electronics for the ALICE Inner Tracker System (ITS). Application of super thermoconductive carbon fibre thin plates provides a practical solution for the development of miniature motherboards for the FEE chips situated inside the sensitive ITS volume. Unidirectional carbon fibre motherboards of 160 -300 micron thickness ensure the mounting of the FEE chips and an efficient heat sink to the cooling arteries. Thermal conductivity up to 1.3 times better than copper is achieved while preserving a negligible multiple scattering contribution by the material (less than 0.15 percent of X/Xo).

  19. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  20. NOVEL ELECTRONIC TUNER USING VARACTORS FOR TUNABLE RF FRONT-ENDS

    Institute of Scientific and Technical Information of China (English)

    Li Liang; Liu Taijun; Ye Yan; Zhang Haili; Hui Ming; Li Jun; Wen Huafeng

    2013-01-01

    This paper presents a novel electronic tuner with high power handling capability utilizing varactors based on the asymmetric bilateral coupled microstrip transmission line.Through varying the bias voltage of the varactor at the Ultra High Frequency (UHF) band,the performance of the tuner is demonstrated according to simulated and measured results from several cases with the return loss (S11)below-20 dB and the insertion loss (S21) within ±0.5 dB.Compared with tuners using π and T network,electronic tuner of this paper shows superior frequency agility as well as wide impendence coverage.Advanced biasing structure has been developed to improve power handling for high power level applications.It is expected that the novel tuner would be part of intelligent Radio Frequency (RF)front-ends system and cognitive wireless system in the future.

  1. First commissioning experience with the LINAC4 3 MeV front-end at CERN

    CERN Document Server

    Lallement, J B; Bellodi, G; Comblin, J F; Dimov, V A; Granemann Souza, E; Lettry, J; Lombardi, A M; Midttun, O; Ovalle, E; Raich, U; Roncarolo, F; Rossi, C; Sanchez Alvarez, R; Scrivens, C A; Valerio-Lizarraga, C A; Vretenar, M; Yarmohammadi Satri, M

    2013-01-01

    Linac4 is a normal-conducting 160 MeV H- linear accelerator presently under construction at CERN. It will replace the present 50 MeV Linac2 as injector of the proton accelerator complex as part of a project to increase the LHC luminosity. The Linac front-end, composed of a 45 keV ion source, a Low Energy Beam Transport (LEBT), a 352.2 MHz Radio Frequency Quadrupole (RFQ) and a Medium Energy Beam Transport (MEBT) housing a beam chopper, have been commissioned at the 3 MeV test stand during the first half of 2013. The status of the installation and the results of the first commissioning stage are presented in this paper.

  2. Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications

    Science.gov (United States)

    Venkatesan, Jaikrishna; Mysoor, Narayan R.; Hashemi, Hassein; Aflatouni, Firooz

    2010-01-01

    A fully integrated, front-end Ka-band monolithic microwave integrated circuit (MMIC) was developed that houses an LNA (low noise amplifier) stage, a down-conversion stage, and output buffer amplifiers. The MMIC design employs a two-step quadrature down-conversion architecture, illustrated in the figure, which results in improved quality of the down-converted IF quadrature signals. This is due to the improved sensitivity of this architecture to amplitude and phase mismatches in the quadrature down-conversion process. Current sharing results in reduced power consumption, while 3D-coupled inductors reduce the chip area. Improved noise figure is expected over previous SiGe-based, frontend designs

  3. System considerations and RF front-end design for integration of satellite navigation and mobile standards

    Directory of Open Access Journals (Sweden)

    A. Miskiewicz

    2009-05-01

    Full Text Available The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF, and 1dB compression point (P1dB of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

  4. Fuzzy Decision Support for Tools Selection in the Core Front End Activities of New Product Development

    DEFF Research Database (Denmark)

    Achiche, S.; Appio, F.P.; McAloone, Tim C.

    2013-01-01

    , an economic evaluation of the cost of tool usage is critical, and there is furthermore a need to characterize them in terms of their influence on the FE. This paper focuses on decision support for managers/ designers in their process of assessing the cost of choosing/using tools in the core front end (CFE...... models (FDSM) of the discovered relationships. The decision support focuses upon the estimated investment needed for the use of tools during the CFE. The generation of FDSMs is carried out automatically using a specialized genetic algorithm, applied to learning data obtained from five experienced...... in CFE activities can vary a lot and hence largely influence their financial performances later on in the NPD process....

  5. Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

    DEFF Research Database (Denmark)

    Song, Zhanfeng; Tian, Yanjun; Chen, Wei;

    2016-01-01

    of optimal duty cycles is made by predicting the effect of duty cycles on instantaneous current variations and minimizing the cost function. Due to the adoption of behavior prediction, the proposed controller inherits the excellent dynamic characteristics of predictive controllers. Moreover, the application......This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...... of optimal duty cycles determined by cost function minimization automatically ensures optimum operations of converters within each sampling period. Improved transient and steady-state features of the proposed strategy are confirmed by experimental validations and in-depth comparisons with linear controllers...

  6. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

    2011-09-11

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  7. The front-end chip of the SuperB SVT detector

    Energy Technology Data Exchange (ETDEWEB)

    Giorgi, F., E-mail: giorgi@bo.infn.it [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università degli Studi di Bergamo (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pavia (Italy); Fabbri, L.; Gabrielli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Pellegrini, G.; Sbarra, C. [Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Berra, A.; Lietti, D.; Prest, M. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Wilson, F. [STFC Rutherford Appleton Laboratory, Harwell Oxford, Didcot OX11 0QX (United Kingdom); Beck, G.; Morris, J. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); and others

    2013-08-01

    The asymmetric e{sup +}e{sup −} collider SuperB is designed to deliver a high luminosity, greater than 10{sup 36}cm{sup −2}s{sup −1}, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  8. Low-Cost Ratiometric Front-End for Industrial PRT Applications

    Science.gov (United States)

    Smorgon, D.; Fernicola, V. C.; Coslovi, L.

    2011-12-01

    Cost, size, speed, and measurement range limitations make the resistance bridge not always suitable for temperature measurements with platinum resistance thermometers (PRTs) in industrial applications. However, high-accuracy resistance thermometer systems are often needed in many industrial applications, where measurement performances comparable to resistance bridges are often needed at a lower cost and size. A tiny, portable, ratiometric front-end exploiting a 24-bit analog-to-digital converter (ADC) with Σ Δ modulator is described. It was designed to measure the resistance ratio between a 100 Ω industrial PRT (IPRT) and a reference resistor with repeatability to within a few parts in 106. Its small size makes it ideal for integration in the stem-handle assembly of a thermometric probe, enabling an early transmission of measurement data in digital form. The ADC-based system design, development, and performance testing are discussed. The system was investigated in the resistance ratio range from about 4 × 10-3 to 5 × 10-2. Furthermore, a comparison between the system performance and a commercial AC resistance bridge was carried out and the results reported in this paper. An accurate thermometer for industrial applications resulted from the above developments. The compactness of the devices enabled an implementation of the `smart sensor' concept in the measurement chain, where the front-end electronics was placed inside the IPRT handle together with an integrated memory to hold device identification, calibration coefficients, and the associated uncertainty. All data are transmitted to the readout module and are available to the user at a 5 Hz update rate for further analysis.

  9. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe.

    Science.gov (United States)

    Di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere; Jorgensen, Ivan Harald Holger; Jensen, Jorgen Arendt

    2016-11-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point spread function is simulated in Field II from 10 to 160 mm using a convex array transducer. A noise analysis is performed, and the minimum signal-to-noise ratio (SNR) requirements are derived for the low-noise amplifiers (LNAs) and A/D converters (ADCs) to fulfill the design specifications of a dynamic range of 60 dB and a penetration depth of 160 mm in the B-mode image. Six front-end implementations are compared using Nyquist-rate and Σ∆ modulator ADCs. The image quality is evaluated as a function of the depth in terms of lateral full-width at half-maximum (FWHM) and -12-dB cystic resolution (CR). The designs that minimally satisfy the specifications are based on an 8-b 30-MSPS Nyquist converter and a single-bit third-order 240-MSPS Σ∆ modulator, with an SNR for the LNA in both cases equal to 64 dB. The mean lateral FWHM and CR are 2.4% and 7.1% lower for the Σ∆ architecture compared with the Nyquist-rate one. However, the results generally show minimal differences between equivalent architectures. Advantages and drawbacks are finally discussed for the two families of converters.

  10. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  11. Light prototype support using micro-channel technology as high efficiency system for silicon pixel detector cooling

    Energy Technology Data Exchange (ETDEWEB)

    Bosi, F., E-mail: filippo.bosi@pi.infn.it [INFN Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy); Balestri, G.; Ceccanti, M.; Mammini, P.; Massa, M.; Petragnani, G.; Ragonesi, A.; Soldani, A. [INFN Pisa, Largo B. Pontecorvo 3, 56127 Pisa (Italy)

    2011-09-11

    The development of micro-scale mechanical systems has been moving rapidly, allowing an opportunity to the semiconductor detectors to have ever more power located on the active region. Miniaturization associated with micro-channel technologies allows the design of micro-system structures that are able to cool silicon pixel detectors with power of the order of some W/cm{sup 2} with thickness less than 0.3% of radiation length. We present the design and thermo-hydraulic test results for low material budget support and cooling obtained through forced liquid convection in micro-channels, developed for the innermost layer (Layer 0) of SuperB silicon vertex tracker.

  12. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  13. Analysis of test-beam data with hybrid pixel detector prototypes for the Compact LInear Collider (CLIC) vertex detectors

    CERN Document Server

    Pequegnot, Anne-Laure

    2013-01-01

    The LHC is currently the most powerful accelerator in the world. This proton-proton collider is now stoppped to increase significantly its luminosity and energy, which would provide a larger discovery potential in 2014 and beyond. A high-energy $e^{+}e^{-}$ collider, such as CLIC, is an option to complement and to extend the LHC physics programme. Indeed, a lepton collider gives access to additional physics processes, beyond those observable at the LHC, and therefore provides new discovery potential. It can also provide complementary and/or more precise information about new physics uncovered at the LHC. Many essential features of a detector are required to deliver the full physics potential of this CLIC machine. In this present report, I present my work on the vertex detector R\\&D for this future linear collider, which aims at developping highly granular and ultra-thin position sensitive detection devices with very low power consumption and fast time-stamping capability. We tested here thin silicon pixel...

  14. Development and characterisation of Monolithic Active Pixel Sensor prototypes for the upgrade of the ALICE Inner Tracking System

    CERN Document Server

    Collu, Alberto

    ALICE (A Large Ion Collider Experiment) is dedicated to the study and characterisation of the Quark-­‐Gluon Plasma (QGP), exploiting the unique potential of ultrarelativistic heavy-­‐ion collisions at the CERN Large Hadron Collider (LHC). The increase of the LHC luminosity leading up to about 50 kHz Pb-­‐Pb interaction rate after the second long shutdown (in 2018-­‐2019) will offer the possibility to perform high precision measurements of rare probes over a wide range of momenta. These measurements are statistically limited or not even possible with the present experimental set up. For this reason, an upgrade strategy for several ALICE detectors is being pursued. In particular, it is foreseen to replace the Inner Tracking System (ITS) by a new detector which will significantly improve the tracking and vertexing capabilities of ALICE in the upgrade scenario. The new ITS will have a barrel geometry consisting of seven layers of Monolithic Active Pixel Sensors (MAPS) with high granularity, which will...

  15. A 2D smart pixel detector for time-resolved protein crystallography

    Energy Technology Data Exchange (ETDEWEB)

    Beuville, E.; Cork, C.; Earnest, T. [and others

    1995-10-01

    A smart pixel detector is being developed for Time Resolved Crystallography for biological and material science applications. Using the Pixel detector presented here, the Laue method will enable the study of the evolution of structural changes that occur within the protein as a function of time. The x-ray pixellated detector is assembled to the integrated circuit through a bump bonding process. Within a pixel size of 150 x 150 {mu}m{sup 2}, a low noise preamplifier-shaper, a discriminator, a 3 bit counter and the readout logic are integrated. The readout, based on the Column Architecture principle, will accept hit rates above 5x10{sup 8}/cm{sup 2}/s with a maximum hit rate per pixel of 1 MHz. This detector will allow time resolved Laue crystallography to be performed in a frameless operation mode, without dead time. Target specifications, architecture, and preliminary results on the 8 x 8 front-end prototype and column readout are presented.

  16. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C. J.; Müller, W. F. J.

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  17. Inter-firm collaboration in the Fuzzy Front-End of the innovation process - Exploring New Forms of Collaboration

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholz, Carsten

    2007-01-01

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... and tendencies in formal R&D partnering relations. This paper, however, focuses on collaboration between independent companies prior to such formal agreements as joint ventures or other contractual agreements. This first phase of the innovation process is often referred to as the Fuzzy Front-End (FFE......) and is traditionally seen as an intra-organizational process (Jongbae & David 2002;Kim & Wilemon 2002e;Qingyu & William 2001;Reid & de Brentani 2004a). As the innovation process becomes an interfirm-collaboration the management of the Fuzzy Front-End also changes and calls for new ways of collaboration...

  18. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

    Science.gov (United States)

    Alessio, F.; Caplan, C.; Gaspar, C.; Jacobsson, R.; Wyllie, K.

    2015-02-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  19. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Document Server

    Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  20. Influence Of Tools Input/Output Requirements On Managers Core Front End Activities In New Product Development

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; Minin, Alberto Di

    2011-01-01

    The object of analysis of this explorative research is the Fuzzy Front End of Innovation in Product Development, described by those activities going from the opportunity identification to the concept definition. Business scholars have shown that confusion in terms of goals and different ideas about...... opportunities; make this early phase of the innovation process uncertain and extremely risky. Literature suggests that the understanding, selection and use of appropriate tools/techniques to support decision making are instrumental for a less fuzzy front end of innovation. This paper considers the adoption...

  1. One size does not fit all - understanding the front-end and back-ens of business model innovation

    DEFF Research Database (Denmark)

    Günzel, Franziska; Holm, Anna B.

    2013-01-01

    understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...... production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance...

  2. Reconfigurable and Wideband Receiver Components for System-on-Chip Millimetre-Wave Radiometer Front-Ends

    OpenAIRE

    Reyaz, Shakila Bint

    2015-01-01

    This thesis presents solutions and studies related to the design of reconfigurable and wideband receiver circuits for system-on-chip (SoC) radiometer front-ends within the millimetre-wave (mm-wave) range. Whereas many of today’s mm-wave front-ends are bulky and costly due to having discrete RF components, single-chip receiver modules could potentially result in a wider use for emerging applications such as wireless communication, short range radar and passive imaging security sensors if reali...

  3. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  4. The Virtual Learning Commons: Supporting the Fuzzy Front End of Scientific Research with Emerging Technologies

    Science.gov (United States)

    Pennington, D. D.; Gandara, A.; Gris, I.

    2012-12-01

    The Virtual Learning Commons (VLC), funded by the National Science Foundation Office of Cyberinfrastructure CI-Team Program, is a combination of Semantic Web, mash up, and social networking tools that supports knowledge sharing and innovation across scientific disciplines in research and education communities and networks. The explosion of scientific resources (data, models, algorithms, tools, and cyberinfrastructure) challenges the ability of researchers to be aware of resources that might benefit them. Even when aware, it can be difficult to understand enough about those resources to become potential adopters or re-users. Often scientific data and emerging technologies have little documentation, especially about the context of their use. The VLC tackles this challenge by providing mechanisms for individuals and groups of researchers to organize Web resources into virtual collections, and engage each other around those collections in order to a) learn about potentially relevant resources that are available; b) design research that leverages those resources; and c) develop initial work plans. The VLC aims to support the "fuzzy front end" of innovation, where novel ideas emerge and there is the greatest potential for impact on research design. It is during the fuzzy front end that conceptual collisions across disciplines and exposure to diverse perspectives provide opportunity for creative thinking that can lead to inventive outcomes. The VLC integrates Semantic Web functionality for structuring distributed information, mash up functionality for retrieving and displaying information, and social media for discussing/rating information. We are working to provide three views of information that support researchers in different ways: 1. Innovation Marketplace: supports users as they try to understand what research is being conducted, who is conducting it, where they are located, and who they collaborate with; 2. Conceptual Mapper: supports users as they organize their

  5. The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

    Science.gov (United States)

    Aguilar, J. A.; Bilnik, W.; Borkowski, J.; Cadoux, F.; Christov, A.; della Volpe, D.; Favre, Y.; Heller, M.; Kasperek, J.; Lyard, E.; Marszałek, A.; Moderski, R.; Montaruli, T.; Porcelli, A.; Prandini, E.; Rajda, P.; Rameez, M.; Schioppa, E.; Troyano Pujadas, I.; Ziȩtara, K.; Błocki, J.; Bogacz, L.; Bulik, T.; Curyło, M.; Dyrda, M.; Frankowski, A.; Grudniki, Ł.; Grudzińska, M.; Idźkowski, B.; Jamrozy, M.; Janiak, M.; Lalik, K.; Mach, E.; Mandat, D.; Michałowski, J.; Neronov, A.; Niemiec, J.; Ostrowski, M.; Paśsko, P.; Pech, M.; Schovanek, P.; Seweryn, K.; Skowron, K.; Sliusar, V.; Sowiński, M.; Stawarz, Ł.; Stodulska, M.; Stodulski, M.; Toscano, S.; Walter, R.; Wiȩcek, M.; Zagdański, A.; Żychowski, P.

    2016-09-01

    The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented.

  6. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  7. BPM Analog front-end electronics based on the AD8307 log amplifier

    Science.gov (United States)

    Shurter, R. B.; Gilpatrick, J. D.; Power, J.

    2000-11-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is "detected" by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5 V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  8. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  9. FPGA-Based Front-End Electronics for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Dewitt, Don; McDougald, Wendy; Lewellen, Thomas K; Miyaoka, Robert; Hauck, Scott

    2009-02-22

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanners. Our laboratory is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this next generation scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper two such processes, sub-clock rate pulse timing and event localization, will be discussed in detail. We show that timing performed in the FPGA can achieve a resolution that is suitable for small-animal scanners, and will outperform the analog version given a low enough sampling period for the ADC. We will also show that the position of events in the scanner can be determined in real time using a statistical positioning based algorithm.

  10. A Time-Based Front End Readout System for PET & CT

    CERN Document Server

    Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

    2007-01-01

    In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

  11. Demonstration of an RF front-end based on GaN HEMT technology

    Science.gov (United States)

    Ture, Erdin; Musser, Markus; Hülsmann, Axel; Quay, Rüdiger; Ambacher, Oliver

    2017-05-01

    The effectiveness of the developed front-end on blocking the communication link of a commercial drone vehicle has been demonstrated in this work. A jamming approach has been taken in a broadband fashion by using GaN HEMT technology. Equipped with a modulated-signal generator, a broadband power amplifier, and an omni-directional antenna, the proposed system is capable of producing jamming signals in a very wide frequency range between 0.1 - 3 GHz. The maximum RF output power of the amplifier module has been software-limited to 27 dBm (500 mW), complying to the legal spectral regulations of the 2.4 GHz ISM band. In order to test the proof of concept, a real-world scenario has been prepared in which a commercially-available quadcopter UAV is flown in a controlled environment while the jammer system has been placed in a distance of about 10 m from the drone. It has been proven that the drone of interest can be neutralized as soon as it falls within the range of coverage (˜3 m) which endorses the promising potential of the broadband jamming approach.

  12. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  13. The MYRRHA ADS Project in Belgium Enters the Front End Engineering Phase

    Science.gov (United States)

    De Bruyn, Didier; Abderrahim, Hamid Aït; Baeten, Peter; Leysen, Paul

    The MYRRHA project started in 1998 by SCK•CEN. MYRRHA is a MTR, based on the ADS concept, for material and fuel research, for studying the feasibility of transmutation of Minor Actinides and Long-Lived Fission Products arising from radioactive waste reprocessing and finally for demonstrating at a reasonable power scale the principle of the ADS. The MYRRHA design has progressed through various framework programmes of the European Commission in the context of Partitioning and Transmutation. The design has now entered into the Front End Engineering Phase (FEED) covering the period 2012-2015. The engineering company, which will handle this phase, has been selected and the works have begun in the late 2013. In the mean time we have made some refinements in both primary systems and plant layout, including reactor building design. In this paper, we present the most recent developments of the MYRRHA design in terms of reactor building and plant layout as existing today as well as a preliminary study concerning the spent fuel building of the facility. During the oral presentation we add some preliminary results of the interaction with the FEED contractor and the most recent version of the primary systems.

  14. The front-end electronics of the LSPE-SWIPE experiment

    Science.gov (United States)

    Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

    2016-07-01

    The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

  15. The dielectric-filled parabola - A new millimeter/submillimeter wavelength receiver/transmitter front end

    Science.gov (United States)

    Siegel, Peter H.; Dengler, Robert J.

    1991-01-01

    A design is presented for a semi-integrated millimeter/submillimeter wavelength receiver/transmitter front end incorporating a planar antenna and a solid-state device in an efficient feed structure which can be matched directly to high f-number optical systems. The feed system combines the simplicity and robustness of a dielectric substrate lens with the high gain of a parabolic reflector in a single structure that is termed a dielectric-filled parabola. The same fundamental unit can be configured as either a heterodyne or direct detection mode receiver, a power transmitter or a frequency multiplier by changing out the solid-state device and/or the integrated antenna. The structure can also be used with a small integrated antenna array in a multibeam or imaging arrangement. Design and fabrication details for the feed system are given. These are followed by beam pattern and impedance measurements taken on a microwave model when dipole, bow-tie, log-periodic, and log-spiral antennas are used as the integrated feed elements.

  16. BPM ANALOG FRONT-END ELECTRONICS BASED ON THE AD8307 LOG AMPLIFIER

    Energy Technology Data Exchange (ETDEWEB)

    R. SHURTER; ET AL

    2000-06-01

    Beam position monitor (BPM) signal-processing electronics utilizing the Analog Devices AD8307 logarithmic amplifier has been developed for the Low Energy Demonstration Accelerator (LEDA), part of the Accelerator Production of Tritium (APT) project at Los Alamos. The low-pass filtered 350 MHz fundamental signal from each of the four microstrip electrodes in a BPM is ''detected'' by an AD8307 log amp, amplified and scaled to accommodate the 0 to +5V input of an analog-to-digital (A/D) converter. The resultant four digitized signals represent a linear power relationship to the electrode signals, which are in turn related to beam current and position. As the AD8307 has a potential dynamic range of approximately 92 dB, much attention must be given to noise reduction, sources of which can be digital signals on the same board, power supplies, inter-channel coupling, stray RF and others. This paper will describe the operational experience of this particular analog front-end electronic circuit design.

  17. Readout Control Specifications for the Front-End and Back-End of the LHCb Upgrade

    CERN Document Server

    Alessio, F

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system [1] in order to run at between five and ten times the initial design luminosity. The various sub-systems in the readout architecture will need to be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. The development of a new readout control system for the upgraded LHCb readout system was investigated already in 2008 [2]. This work has evolved into a detailed system-level specification of the entire timing and readout control system [3]. In this paper, we specify in detail the functionalities that must be supported by the Front-End and the Back-End electronics to comply with the timing requirements and the readout scheme, and the necessary control and monitoring capabilities in order to validate, commission and operate the upgraded experiment efficiently and with sufficient flexibility. The document focuses entirely on the readout control aspects of the FE and BE, and the ECS inter...

  18. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  19. Irradiation Studies of Multimode Fibres for use in ATLAS Front-end Links

    CERN Document Server

    Mahout, G; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, RJ; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Pearce, M; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, AR; Wilson, J A; Ye, J

    1999-01-01

    The radiation tolerance of three multimode optical fibres has been investigatedto establish their suitability for use in the front-end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of $\\sim$0.05~dB/mat 330~kGy(Si) and 1$\\times$10$^{15}$~n(1~MeV~Si)/cm$^{2}$ and is suitablefor use with the inner detector links which operate at 40-80~Mb/s. A graded-indexfibre with a predominantly germanium doped core exhibits an induced attenuation of $\\sim$0.1~dB/mat 800~Gy(Si) and 2$\\times$10$^{13}$~n(1~MeV~Si)/cm$^{2}$ and is suitable for the calorimeterlinks which operate at 1.6~Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower.

  20. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...