WorldWideScience

Sample records for performance microprocessor designs

  1. Designs and performance of three new microprocessor-controlled knee joints.

    Science.gov (United States)

    Thiele, Julius; Schöllig, Christina; Bellmann, Malte; Kraft, Marc

    2018-02-09

    A crossover design study with a small group of subjects was used to evaluate the performance of three microprocessor-controlled exoprosthetic knee joints (MPKs): C-Leg 4, Plié 3 and Rheo Knee 3. Given that the mechanical designs and control algorithms of the joints determine the user outcome, the influence of these inherent differences on the functional characteristics was investigated in this study. The knee joints were evaluated during level-ground walking at different velocities in a motion analysis laboratory. Additionally, technical analyses using patents, technical documentations and X-ray computed tomography (CT) for each knee joint were performed. The technical analyses showed that only C-Leg 4 and Rheo Knee 3 allow microprocessor-controlled adaptation of the joint resistances for different gait velocities. Furthermore, Plié 3 is not able to provide stance extension damping. The biomechanical results showed that only if a knee joint adapts flexion and extension resistances by the microprocessor all known advantages of MPKs can become apparent. But not all users may benefit from the examined functions: e.g. a good accommodation to fast walking speeds or comfortable stance phase flexion. Hence, a detailed comparison of user demands and performance of the designated knee joint is mandatory to ensure a maximum in user outcome.

  2. Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

    Directory of Open Access Journals (Sweden)

    Ching-Hwa Cheng

    2013-01-01

    Full Text Available The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar microprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor's performance. However, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most past architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function units. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the instruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard prevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the start of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and less power consumption compared to the conventional hazard prevention technique.

  3. Microprocessor system design a practical introduction

    CERN Document Server

    Spinks, Michael J

    2013-01-01

    Microprocessor System Design: A Practical Introduction describes the concepts and techniques incorporated into the design of electronic circuits, particularly microprocessor boards and their peripherals. The book reviews the basic building blocks of the electronic systems composed of digital (logic levels, gate output circuitry) and analog components (resistors, capacitors, diodes, transistors). The text also describes operational amplifiers (op-amp) that use a negative feedback technique to improve the parameters of the op-amp. The design engineer can use programmable array logic (PAL) to rep

  4. Design of microprocessor-based hardware for number theoretic transform implementation

    Energy Technology Data Exchange (ETDEWEB)

    Anwar Ahmed Shamim

    1985-01-01

    The Winograd (1976) Fourier Transform algorithm (WFTA) was implemented on a TMS9900 microprocessor to compute NTTs. Since multiplication conducted modulo m is very time consuming a special purpose external hardware modular multiplier was designed, constructed and interfaced with the TMS9900 microprocessor. This external hardware modular multiplier allowed an improvement in the transform execution time. Computation time may further be reduced by employing several microprocessors. Taking advantage of the inherent parallelism of the WFTA, a dedicated parallel microprocessor system was designed and constructed to implement a 15-point WFTA in parallel. Benchmark programs were written to choose a suitable microprocessor for the parallel microprocessor system. A master or a host microprocessor is used to control the parallel microprocessor system and provides an interface to the outside world. An analogue to digital (a/d) and a digital to analogue (d/a) converter allows real time digital signal processing.

  5. Design analysis and microprocessor based control of a nuclear reactor

    International Nuclear Information System (INIS)

    Sabbakh, N.J.

    1988-01-01

    The object of this thesis is to design and test a microprocessor based controller, to a simulated nuclear reactor system. The mathematical model that describes the dynamics of a typical nuclear reactor of one group of delayed neutrons approximations with temperature feedback was chosen. A digital computer program has been developed for the design and analysis of a simulated model based on the concept of state-variable feedback in order to meet a desired system response with maximum overshoot of 3.4% and setting time of 4 sec. The state variable feedback coefficients are designed for the continuous system, then an approximation is used to obtain in the state variable feedback vector for the discrete system. System control was implemented utilizing Direct Digital Control (DDC) of a nuclear reactor simulated model through a control algorithm that was performed by means of a microprocessor based system. The controller performance was satisfactorily tested by exciting the reactor system with a transient reactivity disturbance and by a step change in power demand. Direct digital control, when implemented on a microprocessor adds versatility, flexibility in system design with the added advantage of possible use of optimal control algorithms. 6 tabs.; 30 figs.; 46 refs.; 6 apps

  6. A new design approach for control circuits of pipelined single-flux-quantum microprocessors

    International Nuclear Information System (INIS)

    Yamanashi, Y; Akimoto, A; Yoshikawa, N; Tanaka, M; Kawamoto, T; Kamiya, Y; Fujimaki, A; Terai, H; Yorozu, S

    2006-01-01

    A novel method of design for controllers of pipelined microprocessors using single-flux-quantum (SFQ) logic has been proposed. The proposed design approach is based on one hot encoding and is very suitable for designing a finite state machine using SFQ logic circuits, where each internal state of the microprocessor is represented by a flip-flop. In this approach, decoding of the internal state can be performed instantaneously, in contrast to the case in the conventional method using a binary state register. Moreover, pipelining is effectively implemented without increasing the circuit size because no pipeline registers are required in the one hot encoding. By using this method, we have designed a controller for our new SFQ microprocessors, which employs pipelining. The number of Josephson junctions of the newly designed controller is 1067, while the previous version without pipelining contains 1721 Josephson junctions. These results indicate that the proposed design approach is very effective for pipelined SFQ microprocessors. We have implemented a new controller using the NEC 2.5 kA cm -2 Nb standard process and confirmed its correct operation experimentally

  7. Architectural and compiler techniques for energy reduction in high-performance microprocessors

    Science.gov (United States)

    Bellas, Nikolaos

    1999-11-01

    The microprocessor industry has started viewing power, along with area and performance, as a decisive design factor in today's microprocessors. The increasing cost of packaging and cooling systems poses stringent requirements on the maximum allowable power dissipation. Most of the research in recent years has focused on the circuit, gate, and register-transfer (RT) levels of the design. In this research, we focus on the software running on a microprocessor and we view the program as a power consumer. Our work concentrates on the role of the compiler in the construction of "power-efficient" code, and especially its interaction with the hardware so that unnecessary processor activity is saved. We propose techniques that use extra hardware features and compiler-driven code transformations that specifically target activity reduction in certain parts of the CPU which are known to be large power and energy consumers. Design for low power/energy at this level of abstraction entails larger energy gains than in the lower stages of the design hierarchy in which the design team has already made the most important design commitments. The role of the compiler in generating code which exploits the processor organization is also fundamental in energy minimization. Hence, we propose a hardware/software co-design paradigm, and we show what code transformations are necessary by the compiler so that "wasted" power in a modern microprocessor can be trimmed. More specifically, we propose a technique that uses an additional mini cache located between the instruction cache (I-Cache) and the CPU core; the mini cache buffers instructions that are nested within loops and are continuously fetched from the I-Cache. This mechanism can create very substantial energy savings, since the I-Cache unit is one of the main power consumers in most of today's high-performance microprocessors. Results are reported for the SPEC95 benchmarks in the R-4400 processor which implements the MIPS2 instruction

  8. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  9. An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor

    Science.gov (United States)

    Karaki, Nobuo; Nanmoto, Takashi; Inoue, Satoshi

    This paper presents an asynchronous design technique, an enabler for the emerging technology of flexible microelectronics that feature low-temperature processed polysilicon (LTPS) thin-film transistors (TFT) and surface-free technology by laser annealing/ablation (SUFTLA®). The first design instance chosen is an 8-bit microprocessor. LTPS TFTs are good for realizing displays having integrated VLSI circuit at lower costs. However, LTPS TFTs have drawbacks, including substantial deviations in characteristics and the self-heating phenomenon. To solve these problems, the authors adopted the asynchronous circuit design technique and developed an asynchronous design language called Verilog+, which is based on a subset of Verilog HDL® and includes minimal primitives used for describing the communications between modules, and the dedicated tools including a translator called xlator and a synthesizer called ctrlsyn. The flexible 8-bit microprocessor stably operates at 500kHz, drawing 180μA from a 5V power source. The microprocessor's electromagnetic emissions are 21dB less than those of the synchronous counterpart.

  10. Microprocessor hardware reliability

    Energy Technology Data Exchange (ETDEWEB)

    Wright, R I

    1982-01-01

    Microprocessor-based technology has had an impact in nearly every area of industrial electronics and many applications have important safety implications. Microprocessors are being used for the monitoring and control of hazardous processes in the chemical, oil and power generation industries, for the control and instrumentation of aircraft and other transport systems and for the control of industrial machinery. Even in the field of nuclear reactor protection, where designers are particularly conservative, microprocessors are used to implement certain safety functions and may play increasingly important roles in protection systems in the future. Where microprocessors are simply replacing conventional hard-wired control and instrumentation systems no new hazards are created by their use. In the field of robotics, however, the microprocessor has opened up a totally new technology and with it has created possible new and as yet unknown hazards. The paper discusses some of the design and manufacturing techniques which may be used to enhance the reliability of microprocessor based systems and examines the available reliability data on lsi/vlsi microcircuits. 12 references.

  11. Microprocessor controller for phasing the accelerator

    International Nuclear Information System (INIS)

    Howry, S.K.; Wilmunder, A.R.

    1977-03-01

    A microprocessor controller is being developed to perform automatic phasing of the SLAC accelerator. It will replace the existing relay/analog boxes which are ten years old. The new system is all solid state except for the stepping motors that drive the phase shifters. A description is given of the components of the system, the control algorithm, microprocessor hardware and software design and development, and interaction with SLAC's computer control system

  12. Microprocessors principles and applications

    CERN Document Server

    Debenham, Michael J

    1979-01-01

    Microprocessors: Principles and Applications deals with the principles and applications of microprocessors and covers topics ranging from computer architecture and programmed machines to microprocessor programming, support systems and software, and system design. A number of microprocessor applications are considered, including data processing, process control, and telephone switching. This book is comprised of 10 chapters and begins with a historical overview of computers and computing, followed by a discussion on computer architecture and programmed machines, paying particular attention to t

  13. Design and Implementation of O/C relay using Microprocessor

    Directory of Open Access Journals (Sweden)

    Dr.Abdul-Sattar H. Jasim

    2012-03-01

    Full Text Available This work presents the design and implementation of a versatile digital overcurrent (O/C relay using a single microprocessor. The relay is implemented by a combination of a look-up table and a counter. The software development and hardware testing are done using a microcomputer module based on a 8-bit microprocessor. The digital processing of measured currents enables a separate setting of operating values selection of all types of inverse or constant time characteristics overcurrent protection. This protection provides reasonably fast tripping, even at terminal close to the power source were the most serve faults can occur excluding the transient condition. So this method has an excellent compromise between accuracy hardware and speed

  14. Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

    Science.gov (United States)

    Baez, A. N.

    1985-01-01

    Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

  15. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  16. Practical design of digital circuits basic logic to microprocessors

    CERN Document Server

    Kampel, Ian

    1983-01-01

    Practical Design of Digital Circuits: Basic Logic to Microprocessors demonstrates the practical aspects of digital circuit design. The intention is to give the reader sufficient confidence to embark upon his own design projects utilizing digital integrated circuits as soon as possible. The book is organized into three parts. Part 1 teaches the basic principles of practical design, and introduces the designer to his """"tools"""" - or rather, the range of devices that can be called upon. Part 2 shows the designer how to put these together into viable designs. It includes two detailed descriptio

  17. Real-time fetal ECG system design using embedded microprocessors

    Science.gov (United States)

    Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

    2016-05-01

    The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

  18. Microprocessors

    CERN Document Server

    Cornillie, O A R

    1985-01-01

    Microprocessors presents an overview of the state of the art in the field of microprocessors and illustrates, with the aid of patents, its utilization and application. Organized into six parts, the book begins with an introduction to the microprocessor, microcomputer, and software. Parts I-III focus on program control, digital control, and electrical motor control. Subsequent parts show the medical applications, measuring instruments, and treatment of data in microprocessors.

  19. Microprocessor based systems for the higher technician

    CERN Document Server

    Vears, RE

    2013-01-01

    Microprocessor Based Systems for the Higher Technician provides coverage of the BTEC level 4 unit in Microprocessor Based Systems (syllabus U80/674). This book is composed of 10 chapters and concentrates on the development of 8-bit microcontrollers specifically constructed around the Z80 microprocessor. The design cycle for the development of such a microprocessor based system and the use of a disk-based development system (MDS) as an aid to design are both described in detail. The book deals with the Control Program Monitor (CP/M) operating system and gives background information on file hand

  20. A microarchitecture for resource-limited superscalar microprocessors

    Science.gov (United States)

    Basso, Todd David

    1999-11-01

    Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined

  1. The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jensen, P.; Korger, P.

    1998-01-01

    This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

  2. A light-powered sub-threshold microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Liu Ming; Chen Hong; Zhang Chun; Li Changmeng; Wang Zhihua, E-mail: lium02@mails.tsinghua.edu.cn [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2010-11-15

    This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode. With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW, dynamic power of 385 nW - 165 kHz, EDP 13 pJ/inst and the operating voltage of 350 mV are achieved. Under a light of about 150 kLux, the microprocessor can run at a rate of up to 500 kHz. The microprocessor can be used for wireless-sensor-network nodes.

  3. Evaluation of the performance of microprocessor-based colorimeter

    OpenAIRE

    Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

    1992-01-01

    Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood ...

  4. Low cost design of microprocessor EDAC circuit

    International Nuclear Information System (INIS)

    Hao Li; Yu Lixin; Peng Heping; Zhuang Wei

    2015-01-01

    An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)

  5. Evaluation of the performance of microprocessor-based colorimeter.

    Science.gov (United States)

    Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

    1992-01-01

    Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

  6. Microprocessor interfacing

    CERN Document Server

    Vears, R E

    2014-01-01

    Microprocessor Interfacing provides the coverage of the Business and Technician Education Council level NIII unit in Microprocessor Interfacing (syllabus U86/335). Composed of seven chapters, the book explains the foundation in microprocessor interfacing techniques in hardware and software that can be used for problem identification and solving. The book focuses on the 6502, Z80, and 6800/02 microprocessor families. The technique starts with signal conditioning, filtering, and cleaning before the signal can be processed. The signal conversion, from analog to digital or vice versa, is expl

  7. Microprocessorized message multiplexer

    International Nuclear Information System (INIS)

    Ejzman, S.; Guglielmi, L.; Jaeger, J.J.

    1980-07-01

    The 'Microprocessorized Message Multiplexer' is an elementary development tool used to create and debug the software of a target microprocessor (User Module: UM). It connects together four devices: a terminal, a cassette recorder, the target microprocessor and a host computer where macro and editor for the M 6800 microprocessor are resident [fr

  8. Microprocessor control of a wind turbine generator

    Science.gov (United States)

    Gnecco, A. J.; Whitehead, G. T.

    1978-01-01

    This paper describes a microprocessor based system used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

  9. CFD-simulation of radiator for air cooling of microprocessors in a limitided space

    Directory of Open Access Journals (Sweden)

    Trofimov V. E.

    2016-12-01

    Full Text Available One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal contact with the microprocessor housing designed for cooler installation. On the hot surface of the module a radiator is mounted. The radiator dissipates the cumulative heat flow from both the microprocessor and the module. High density PCB layout, the requirement of free access to the jumpers and interfaces, and the presence of numerous sensors limit the space for radiator mounting and require the use of an extremely compact radiator, especially in air cooling conditions. One of the possible solutions for this problem may reduce the area of the radiator heat-transfer surfaces due to a sharp growth of the heat transfer coefficient without increasing the air flow rate. To ensure a sharp growth of heat transfer coefficient on the heat-transfer surface one should make in the surface one or more dead-end cavities into which the impact air jets would flow. CFD simulation of this type of radiator has been conducted. The heat-aerodynamic characteristics and design recommendations for removing heat from microprocessors in a limited space have been determined.

  10. A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

    Science.gov (United States)

    Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

    2011-10-01

    In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

  11. Microprocessor aided data acquisition at VEDAS

    International Nuclear Information System (INIS)

    Ziem, P.; Drescher, B.; Kapper, K.; Kowallik, R.

    1985-01-01

    Three microprocessor systems have been developed to support data acquisition in nuclear physics multiparameter experiments. A bit-slice processor accumulates up to 256 1-dim spectra and 16 2-dim spectra. A microprocessor, based on the AM 29116 ALU, performs a fast consistency check on the coincidence data. A VME-Bus double-processor displays a colored scatterplot

  12. G-cueing microcontroller (a microprocessor application in simulators)

    Science.gov (United States)

    Horattas, C. G.

    1980-01-01

    A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

  13. Radiation-hardened bulk Si-gate CMOS microprocessor family

    International Nuclear Information System (INIS)

    Stricker, R.E.; Dingwall, A.G.F.; Cohen, S.; Adams, J.R.; Slemmer, W.C.

    1979-01-01

    RCA and Sandia Laboratories jointly developed a radiation-hardened bulk Si-gate CMOS technology which is used to fabricate the CDP-1800 series microprocessor family. Total dose hardness of 1 x 10 6 rads (Si) and transient upset hardness of 5 x 10 8 rads (Si)/sec with no latch up at any transient level was achieved. Radiation-hardened parts manufactured to date include the CDP-1802 microprocessor, the CDP-1834 ROM, the CDP-1852 8-bit I/O port, the CDP-1856 N-bit 1 of 8 decoder, and the TCC-244 256 x 4 Static RAM. The paper is divided into three parts. In the first section, the basic fundamentals of the non-hardened C 2 L technology used for the CDP-1800 series microprocessor parts is discussed along with the primary reasons for hardening this technology. The second section discusses the major changes in the fabrication sequence that are required to produce radiation-hardened devices. The final section details the electrical performance characteristics of the hardened devices as well as the effects of radiation on device performance. Also included in this section is a discussion of the TCC-244 256 x 4 Static RAM designed jointly by RCA and Sandia Laboratories for this application

  14. Microprocessor engineering

    CERN Document Server

    Holdsworth, B

    2013-01-01

    Microprocessor Engineering provides an insight in the structures and operating techniques of a small computer. The book is comprised of 10 chapters that deal with the various aspects of computing. The first two chapters tackle the basic arithmetic and logic processes. The third chapter covers the various memory devices, both ROM and RWM. Next, the book deals with the general architecture of microprocessor. The succeeding three chapters discuss the software aspects of machine operation, while the last remaining three chapters talk about the relationship of the microprocessor with the outside wo

  15. Automated mixed traffic transit vehicle microprocessor controller

    Science.gov (United States)

    Marks, R. A.; Cassell, P.; Johnston, A. R.

    1981-01-01

    An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

  16. The micro-processor controlled process radiation monitoring system for reactor safety systems

    International Nuclear Information System (INIS)

    Mizuno, K.; Noguchi, A.; Kumagami, S.; Gotoh, Y.; Kumahara, T.; Arita, S.

    1986-01-01

    Digital computers are soon expected to be applied to various real-time safety and safety-related systems in nuclear power plants. Hitachi is now engaged in the development of a micro-processor controlled process radiation monitoring system, which operates on digital processing methods employed with a log ratemeter. A newly defined methodology of design and test procedures is being applied as a means of software program verification for these safety systems. Recently implemented micro-processor technology will help to achieve an advanced man-machine interface and highly reliable performance. (author)

  17. A microprocessor based on a two-dimensional semiconductor

    Science.gov (United States)

    Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

    2017-04-01

    The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

  18. Radiation hardened COTS-based 32-bit microprocessor

    International Nuclear Information System (INIS)

    Haddad, N.; Brown, R.; Cronauer, T.; Phan, H.

    1999-01-01

    A high performance radiation hardened 32-bit RISC microprocessor based upon a commercial single chip CPU has been developed. This paper presents the features of radiation hardened microprocessor, the methods used to radiation harden this device, the results of radiation testing, and shows that the RAD6000 is well-suited for the vast majority of space applications. (authors)

  19. Design and implementation of a microprocessor based room ...

    African Journals Online (AJOL)

    This paper describes the development of a microprocessor based room illumination control system that offers advantage of improved efficiency in the use of electrical energy and reduced cost of electricity over manually controlled lighting systems. This system is developed to regulate the intensity of light from direct current ...

  20. Newnes microprocessor pocket book

    CERN Document Server

    Money, Steve

    2014-01-01

    Newnes Microprocessor Pocket Book explains the basic hardware operation of a microprocessor and describes the actions of the various types of instruction that can be executed. A summary of the characteristics of many of the popular microprocessors is presented. Apart from the popular 8- and 16-bit microprocessors, some details are also given of the popular single chip microcomputers and of the reduced instruction set computer (RISC) type processors such as the Transputer, Novix FORTH processor, and Acorn ARM processor.Comprised of 15 chapters, this book discusses the principles involved in bot

  1. Recent applications of microprocessor-based instruments in nuclear power stations

    International Nuclear Information System (INIS)

    Cash, N.R.; Dennis, U.E.

    1988-01-01

    The incorporation of microprocessors in the design of nuclear power plant instrumentation has led to levels of measurement and control not available previously. In addition to the expected expansion of functional (system) capability, numerous desirable features now are possible. The added ability to both self-calibrate and perform compensation algorithms has led to dramatic improvements in accuracies, response times, and noise rejection. Automated performance checking and self-testing simplify troubleshooting and required periodic surveillance. Alphanumeric displays allow both menu-driven operation and user-prompting, which, in turn, contribute to mistake avoidance. New features of these microprocessor-based instruments are of specific benefit in nuclear power reactors, were safety is of prime concern. Greater reliability and accuracy can be provided. Shortened calibration, surveillance, and repair times reduce the exposure to unnecessary challenges of the plant's protection systems that can arise from spurious noise signals

  2. Architecture of 32 bit CISC (Complex Instruction Set Computer) microprocessors

    International Nuclear Information System (INIS)

    Jove, T.M.; Ayguade, E.; Valero, M.

    1988-01-01

    In this paper we describe the main topics about the architecture of the best known 32-bit CISC microprocessors; i80386, MC68000 family, NS32000 series and Z80000. We focus on the high level languages support, operating system design facilities, memory management, techniques to speed up the overall performance and program debugging facilities. (Author)

  3. Microprocessor monitored Auger spectrometer

    International Nuclear Information System (INIS)

    Sapin, Michel; Ghaleb, Dominique; Pernot, Bernard.

    1982-05-01

    The operation of an Auger spectrometer, used for studying surface impurity diffusion, has been fully automatized with the help of a microprocessor. The characteristics, performance and practical use of the system are described together with the main advantage for the experimentator [fr

  4. Microprocessors in automatic chemical analysis

    International Nuclear Information System (INIS)

    Goujon de Beauvivier, M.; Perez, J.-J.

    1979-01-01

    Application of microprocessors to programming and computing of solutions chemical analysis by a sequential technique is examined. Safety, performances reliability are compared to other methods. An example is given on uranium titration by spectrophotometry [fr

  5. Microprocessor event analysis in parallel with Camac data acquisition

    International Nuclear Information System (INIS)

    Cords, D.; Eichler, R.; Riege, H.

    1981-01-01

    The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a Camac System (GEC-ELLIOTT System Crate) and shares the Camac access with a Nord-1OS computer. Interfaces have been designed and tested for execution of Camac cycles, communication with the Nord-1OS computer and DMA-transfer from Camac to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-1OS computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the result of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-1OS buffer will be reset and the event omitted from further processing. (orig.)

  6. Microprocessor event analysis in parallel with CAMAC data acquisition

    CERN Document Server

    Cords, D; Riege, H

    1981-01-01

    The Plessey MIPROC-16 microprocessor (16 bits, 250 ns execution time) has been connected to a CAMAC System (GEC-ELLIOTT System Crate) and shares the CAMAC access with a Nord-10S computer. Interfaces have been designed and tested for execution of CAMAC cycles, communication with the Nord-10S computer and DMA-transfer from CAMAC to the MIPROC-16 memory. The system is used in the JADE data-acquisition-system at PETRA where it receives the data from the detector in parallel with the Nord-10S computer via DMA through the indirect-data-channel mode. The microprocessor performs an on-line analysis of events and the results of various checks is appended to the event. In case of spurious triggers or clear beam gas events, the Nord-10S buffer will be reset and the event omitted from further processing. (5 refs).

  7. CFD-simulation of radiator for air cooling of microprocessors in a limitided space

    OpenAIRE

    Trofimov V. E.; Pavlov A. L.; Mokrousova E. A.

    2016-01-01

    One of the final stages of microprocessors development is heat test. This procedure is performed on a special stand, the main element of which is the switching PCB with one or more mounted microprocessor sockets, chipsets, interfaces, jumpers and other components which provide various modes of microprocessor operation. The temperature of microprocessor housing is typically changed using thermoelectric module. The cold surface of the module with controlled temperature is in direct thermal c...

  8. Model based design introduction: modeling game controllers to microprocessor architectures

    Science.gov (United States)

    Jungwirth, Patrick; Badawy, Abdel-Hameed

    2017-04-01

    We present an introduction to model based design. Model based design is a visual representation, generally a block diagram, to model and incrementally develop a complex system. Model based design is a commonly used design methodology for digital signal processing, control systems, and embedded systems. Model based design's philosophy is: to solve a problem - a step at a time. The approach can be compared to a series of steps to converge to a solution. A block diagram simulation tool allows a design to be simulated with real world measurement data. For example, if an analog control system is being upgraded to a digital control system, the analog sensor input signals can be recorded. The digital control algorithm can be simulated with the real world sensor data. The output from the simulated digital control system can then be compared to the old analog based control system. Model based design can compared to Agile software develop. The Agile software development goal is to develop working software in incremental steps. Progress is measured in completed and tested code units. Progress is measured in model based design by completed and tested blocks. We present a concept for a video game controller and then use model based design to iterate the design towards a working system. We will also describe a model based design effort to develop an OS Friendly Microprocessor Architecture based on the RISC-V.

  9. General-purpose microprocessor-based control chassis

    International Nuclear Information System (INIS)

    Halbig, J.K.; Klosterbuer, S.F.; Swenson, D.A.

    1979-12-01

    The objective of the Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory is to develop the technology to build smaller, less expensive, and more reliable proton linear accelerators for medical applications. For this program, a powerful, simple, inexpensive, and reliable control and data acquisition system was developed. The system has a NOVA 3D computer with a real time disk-operating system (RDOS) that communicates with distributed microprocessor-based controllers which directly control data input/output chassis. At the heart of the controller is a microprocessor crate which was conceived at the Fermi National Accelerator Laboratory. This idea was applied to the design of the hardware and software of the controller

  10. Dynamic instruction set extension of microprocessors with embedded FPGAs

    OpenAIRE

    Bauer, Heiner

    2017-01-01

    Increasingly complex applications and recent shifts in technology scaling have created a large demand for microprocessors which can perform tasks more quickly and more energy efficient. Conventional microarchitectures exploit multiple levels of parallelism to increase instruction throughput and use application specific instruction sets or hardware accelerators to increase energy efficiency. Reconfigurable microprocessors adopt the same principle of providing application specific hardware, how...

  11. Software tools for microprocessor based systems

    International Nuclear Information System (INIS)

    Halatsis, C.

    1981-01-01

    After a short review of the hardware and/or software tools for the development of single-chip, fixed instruction set microprocessor-based sytems we focus on the software tools for designing systems based on microprogrammed bit-sliced microprocessors. Emphasis is placed on meta-microassemblers and simulation facilties at the register-transfer-level and architecture level. We review available meta-microassemblers giving their most important features, advantages and disadvantages. We also make extentions to higher-level microprogramming languages and associated systems specifically developed for bit-slices. In the area of simulation facilities we first discuss the simulation objectives and the criteria for chosing the right simulation language. We consertrate to simulation facilities already used in bit-slices projects and discuss the gained experience. We conclude by describing the way the Signetics meta-microassembler and the ISPS simulation tool have been employed in the design of a fast microprogrammed machine, called MICE, made out of ECL bit-slices. (orig.)

  12. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    Science.gov (United States)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

  13. Fermilab advanced computer program multi-microprocessor project

    International Nuclear Information System (INIS)

    Nash, T.; Areti, H.; Biel, J.

    1985-06-01

    Fermilab's Advanced Computer Program is constructing a powerful 128 node multi-microprocessor system for data analysis in high-energy physics. The system will use commercial 32-bit microprocessors programmed in Fortran-77. Extensive software supports easy migration of user applications from a uniprocessor environment to the multiprocessor and provides sophisticated program development, debugging, and error handling and recovery tools. This system is designed to be readily copied, providing computing cost effectiveness of below $2200 per VAX 11/780 equivalent. The low cost, commercial availability, compatibility with off-line analysis programs, and high data bandwidths (up to 160 MByte/sec) make the system an ideal choice for applications to on-line triggers as well as an offline data processor

  14. Microprocessor based mobile radiation survey system

    International Nuclear Information System (INIS)

    Gilbert, R.W.; McCormack, W.D.

    1983-12-01

    A microprocessor-based system has been designed and constructed to enhance the performance of routine radiation surveys on roads within the Hanford site. This device continually monitors system performance and output from four sodium iodide detectors mounted on the rear bumper of a 4-wheel drive truck. The gamma radiation count rate in counts-per-second is monitored, and a running average computed, with the results compared to predefined limits. If an abnormal instantaneous or average count rate is detected, an alarm is sounded with responsible data displayed on a liquid crystal panel in the cab of the vehicle. The system also has the capability to evaluate detector output using multiple time constants and to perform more complex tests and comparison of the data. Data can be archived for later analysis on conventional chart recorders or stored in digital form on magnetic tape or other digital storage media. 4 figures

  15. Microprocessors applications in the nuclear industry

    International Nuclear Information System (INIS)

    Ethridge, C.D.

    1980-01-01

    Microprocessors in the nuclear industry, particularly at the Los Alamos Scientific Laboratory, have been and are being utilized in a wide variety of applications ranging from data acquisition and control for basic physics research to monitoring special nuclear material in long-term storage. Microprocessor systems have been developed to support weapons diagnostics measurements during underground weapons testing at the Nevada Test Site. Multiple single-component microcomputers are now controlling the measurement and recording of nuclear reactor operating power levels. The CMOS microprocessor data-acquisition instrumentation has operated on balloon flights to monitor power plant emissions. Target chamber mirror-positioning equipment for laser fusion facilities employs microprocessors

  16. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  17. OS Friendly Microprocessor Architecture

    Science.gov (United States)

    2017-04-01

    NOTES Patrick La Fratta is now affiliated with Micron Technology, Inc., Boise, Idaho. 14. ABSTRACT We present an introduction to the patented ...Operating System Friendly Microprocessor Architecture (OSFA). The software framework to support the hardware-level security features is currently patent ...Army is assignee. OS Friendly Microprocessor Architecture. United States Patent 9122610. 2015 Sep. 2. Jungwirth P, inventor; US Army is assignee

  18. Design of microprocessor data acquisition system for pedestrian portal SNM monitor

    International Nuclear Information System (INIS)

    Zhang Wenliang

    2003-01-01

    The paper introduces the hardware structure and composition of data acquisition system for pedestrian portal special nuclear material (SNM) monitor. The hardware and software of single chip microprocessor AT89C52, LCM, keyboard and serial communication interface software are also discussed. (authors)

  19. MicroShell Minimalist Shell for Xilinx Microprocessors

    Science.gov (United States)

    Werne, Thomas A.

    2011-01-01

    MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is

  20. LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

    Energy Technology Data Exchange (ETDEWEB)

    Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

    1984-01-01

    Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

  1. Multichannel analyzer based on microprocessors

    International Nuclear Information System (INIS)

    Soares, M.

    1983-06-01

    A multichannel analyser for nuclear spectrometry, that would attend the needs of research laboratories and could be industrialized in Brazil, was developed. The design was based on INTEL 8080/85 microprocessors; other processors were also used to implement specific functions, such as shared busbar using direct memory access. A prototype was developed and tested through simulation, using a nuclear spectrometry chain. The results were fully satisfactory. (Author) [pt

  2. Microprocessor-controlled CAMAC data link module

    International Nuclear Information System (INIS)

    Potter, J.M.

    1978-05-01

    Communication between the central control computer and remote, satellite data-acquisition/control stations at the Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC-based Data Link modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor. 13 figures

  3. Guidelines for design and development of computer/microprocessor based systems in research and power reactors

    International Nuclear Information System (INIS)

    Dhodapkar, S.D.; Chandra, A.K.

    1993-01-01

    Computer systems are being used in Indian research reactors and nuclear power plants in the areas of data acquisition, process monitoring and control, alarm annunciation and safety. The design and evaluation of these systems requires a special approach particularly due to the unique nature of the software which is an essential constituent of these systems. It was decided to evolve guidelines for designing and review of computer/microprocessor based systems for use in nuclear power plants in India. The present document tries to address various issues and presents guidelines which are as comprehensive as possible and cover all issues relating to the design and development of computer based systems. These guidelines are expected to be useful to the specifiers, designers and reviewers of such systems. (author). 6 refs., 1 fig

  4. A peek into the world of chip design

    CERN Document Server

    CERN. Geneva; Marquina, Miguel Angel

    2005-01-01

    This lecture will give some insight into how the Microprocessor Design Group approaches the daunting task of the design of a lead microprocessor as complex as the Pentium IV while under very specific schedule constraints. For a historical perspective, we will start with a quick comparison of the complexity/performance of the Willamette and Prescott (Pentium IV) class of microprocessor with the generations before the Pentium IV (Bob was a member of the design teams for a number of lead microprocessor projects including the 486DX2, Pentium Pr

  5. A microprocessor-based gamma-ray spectrometer with gain stabilized single-channel analyzers

    International Nuclear Information System (INIS)

    Borg, P.J.; Huppert, P.; Phillips, P.L.; Waddington, P.J.

    1985-01-01

    The design and performance of a self-contained microprocessor-based gamma-ray spectrometer for use in geophysical measurements using nuclear techniques is described. The instrument uses single-channel analyzers which are inherently simpler and faster than the Wilkinson or successive approximation ADC. A novel technique of gain stabilization together with a simple means of energy calibration has been developed. The modular design of the equipment makes it suitable for multidetector usage, required in a number of nucleonic gauges for the quantitative measurement of chemical constituents. (orig.)

  6. Mold heating and cooling microprocessor conversion

    Science.gov (United States)

    Hoffman, D. P.

    1995-07-01

    Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessor board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.

  7. Microprocessor protection relays: new prospects or new problems?

    OpenAIRE

    Gurevich, Vladimir

    2006-01-01

    The internal architecture and principles of operation of microprocessor-based devices including so-called "microprocessor protective relays" have little in common with devices called "electric relays". But microprocessor-based relay protection devices are gradually driving out the traditional electromechanical and even electronic relay protection of virtually from all fields of power and electrical engineering. Advantages of microprocessor-based protection means over traditional ones are far ...

  8. An INTEL 8080 microprocessor development system

    International Nuclear Information System (INIS)

    Horne, P.J.

    1977-01-01

    The INTEL 8080 has become one of the two most widely used microprocessors at CERN, the other being the MOTOROLA 6800. Even thouth this is the case, there have been, to date, only rudimentary facilities available for aiding the development of application programs for this microprocessor. An ideal development system is one which has a sophisticated editing and filing system, an assembler/compiler, and access to the microprocessor application. In many instances access to a PROM programmer is also required, as the application may utilize only PROMs for program storage. With these thoughts in mind, an INTEL 8080 microprocessor development system was implemented in the Proton Synchrotron (PS) Division. This system utilizes a PDP 11/45 as the editing and file-handling machine, and an MSC 8/MOD 80 microcomputer for assembling, PROM programming and debugging user programs at run time. The two machines are linked by an existing CAMAC crate system which will also provide the means of access to microprocessor applications in CAMAC and the interface of the development system to any other application. (Auth.)

  9. A technique of building a value function at the stage of conceptual design of microprocessor systems

    Directory of Open Access Journals (Sweden)

    B. N. Chugaev

    2017-01-01

    Full Text Available The aim of this study is to formalize the selection of optimal technical solutions early in the design of microprocessor-based systems, which allows developers to analyze the recommended solutions, and has, in comparison with the traditional «intuitive» approach, at least two undeniable merits. First, the accepted assumptions and limitations are clearly formed. Secondly, it is defined precisely, in what sense the decision is optimal. When designing microprocessor systems (systems hereafter, several characteristics have to be taken into account at the same time. In general, when n properties are taken into account for each of the compared systems, then the solution of the task of choosing “the best” system depends on choosing a function-criterion. Such function is called a value function in the article. A simple quadratic function is suggested as the value function, it can be interpreted as the distance in Euclidean space of systems technical data. The system, which corresponds to the point nearest to the point characterizing the master system with “limiting” characteristics, is considered the best one. This function approximates the designer’s system of preferences signifi cantly better than a “classical” linear value function. In conclusion, note that the developed recommendations allow the designer of complex technical systems to analyze the proposed solutions in the early stages of design and, in case of disagreement with them, to indicate the reasons why he considers them inadequate. The designed machine optimization of technical solutions in conjunction with the traditional engineering approach should allow more reasonable choosing the structure of systems at the stage of systems conceptual design.

  10. Optimization of Reciprocals and Square Roots on the i860 Microprocessor

    DEFF Research Database (Denmark)

    Sinclair, Robert

    1996-01-01

    The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance.......The i860 microprocessor lacks both a divide and a square root instruction. The consequences of this for code involving many reciprocal square roots, such as many-body simulations involving Coulomb-like potentials, are discussed with a particular emphasis on high performance....

  11. Microprocessor Control Design for a Low-Head Crossflow Turbine.

    Science.gov (United States)

    1985-03-01

    Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

  12. A microprocessor based mobile radiation survey system

    International Nuclear Information System (INIS)

    Gilbert, R.W.; McCormack, W.D.

    1984-01-01

    A microprocessor-based system has been designed and constructed to enhance the performance of routine radiation surveys on roads within the Hanford site. This device continually monitors system performance and output from four sodium iodide detectors mounted on the rear bumper of a 4-wheel drive truck. The gamma radiation count rate in counts-per-second is monitored, and a running average computed, with the results compared to predefined limits. If an abnormal instantaneous or average count rate is detected, an alarm is sounded with responsible data displayed on a liquid crystal panel in the cab of the vehicle. The system also has the capability to evaluate detector output using multiple time constants and to perform more complex tests and comparison of the data. Data can be archived for later analysis on conventional chart recorders or stored in digital form on magnetic tape or other digital storage media

  13. Microprocessor-based stepping motor driver

    International Nuclear Information System (INIS)

    Halbig, J.K.; Klosterbuer, S.F.

    1979-09-01

    The Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory requires a versatile stepping motor driver to do beam diagnostic measurements. A driver controlled by a microprocessor that can move eight stepping motors simultaneously was designed. The driver can monitor and respond to clockwise- and counterclockwise-limit switches, and it can monitor a 0- to 10-V dc position signal. The software controls start and stop ramping and maximum stepping rates. 2 figures, 1 table

  14. Microprocessor-controlled data-acquisition instrument for neutron-activation measurements

    International Nuclear Information System (INIS)

    Jones, B.A.

    1981-01-01

    This paper describes a microprocessor controlled data acquisition instrument designed at Lawrence Livermore National Laboratory to provide experimenters with a diagnostic tool for measuring the performance of laser imploded fusion targets via neutron activation techniques. This instrument features the ability to count four independent inputs simultaneously while providing a front panel readout of these inputs, plus a time of day clock. A hardcopy printout of the data is also provided by a built-in thermal printer. All running modes and parameters are user selectable via a front panel keypad, and a complete set of internal self-testing diagnostics are available for debug

  15. Small private key MQPKS on an embedded microprocessor.

    Science.gov (United States)

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-03-19

    Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

  16. Small Private Key PKS on an Embedded Microprocessor

    Science.gov (United States)

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-01-01

    Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

  17. Fermilab ACP multi-microprocessor project

    International Nuclear Information System (INIS)

    Gaines, I.; Areti, H.; Biel, J.; Bracker, S.; Case, G.; Fischler, M.; Husby, D.; Nash, T.

    1984-08-01

    We report on the status of the Fermilab Advanced Computer Program's project to provide more cost-effective computing engines for the high energy physics community. The project will exploit the cheap, but powerful, commercial microprocessors now available by constructing modular multi-microprocessor systems. A working test bed system as well as plans for the next stages of the project are described

  18. Energy conservation applications of microprocessors

    Energy Technology Data Exchange (ETDEWEB)

    Shih, James Y.

    1979-07-01

    A survey of the application of microprocessors for industrial and commercial energy conservation has been made. Microprocessor applications for HVAC, chiller control, and automotive equipment are discussed. A case study of successful replacement of a conventional cooling plant control is recounted. The rapid advancement of microelectronic technology will affect efficient energy control, more sophisticated control methodology, and more investment in controls.

  19. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  20. Neutron beam irradiation study of workload dependence of SER in a microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Michalak, Sarah E [Los Alamos National Laboratory; Graves, Todd L [Los Alamos National Laboratory; Hong, Ted [STANFORD; Ackaret, Jerry [IBM; Sonny, Rao [IBM; Subhasish, Mitra [STANFORD; Pia, Sanda [IBM

    2009-01-01

    It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

  1. Small Private Key MQPKS on an Embedded Microprocessor

    Directory of Open Access Journals (Sweden)

    Hwajeong Seo

    2014-03-01

    Full Text Available Multivariate quadratic (MQ cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011, a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

  2. A realtime feedback microprocessor for the TEVATRON

    International Nuclear Information System (INIS)

    Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

    1993-01-01

    A feedback microprocessor has been built for the TEVATRON. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor includes a finite state machine. Each state corresponds to a specific TEVATRON operation. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime correction. The authors also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. This talk will describe use of this device to control the TEVATRON tunes and discuss other uses

  3. Multiple microprocessor based nuclear reactor power monitor

    International Nuclear Information System (INIS)

    Lewis, P.S.; Ethridge, C.D.

    1979-01-01

    The reactor power monitor is a portable multiple-microprocessor controlled data acquisition device being built for the International Atomic Energy Association. Its function is to measure and record the hourly integrated operating thermal power level of a nuclear reactor for the purpose of detecting unannounced plutonium production. The monitor consists of a 3 He proportional neutron detector, a write-only cassette tape drive and control electronics based on two INTEL 8748 microprocessors. The reactor power monitor operates from house power supplied by the plant operator, but has eight hours of battery backup to cover power interruptions. Both the hourly power levels and any line power interruptions are recorded on tape and in memory. Intermediate dumps from the memory to a data terminal or strip chart recorder can be performed without interrupting data collection

  4. Microprocessor controller for stepping motors

    International Nuclear Information System (INIS)

    Strait, B.G.; Thuot, M.E.

    1977-01-01

    A new concept for digital computer control of multiple stepping motors which operate in a severe electromagnetic pulse environment is presented. The motors position mirrors in the beam-alignment system of a 100-kJ CO 2 laser. An asynchronous communications channel of a computer is used to send coded messages, containing the motor address and stepping-command information, to the stepping-motor controller in a bit serial format over a fiber-optics communications link. The addressed controller responds by transmitting to the computer its address and other motor information, thus confirming the received message. Each controller is capable of controlling three stepping motors. The controller contains the fiber-optics interface, a microprocessor, and the stepping-motor driven circuits. The microprocessor program, which resides in an EPROM, decodes the received messages, transmits responses, performs the stepping-motor sequence logic, maintains motor-position information, and monitors the motor's reference switch. For multiple stepping-motor application, the controllers are connected in a daisy chain providing control of many motors from one asynchronous communications channel of the computer

  5. The microprocessor boom

    International Nuclear Information System (INIS)

    Anon.

    1979-01-01

    The applications of microprocessors in high energy physics experiments are discussed. Many benefits are predicted for data acquisition and handling systems and for control and monitoring functions. (W.D.L.).

  6. FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

    International Nuclear Information System (INIS)

    Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve

    2014-01-01

    Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

  7. FPGAs Emulate Microprocessors-A Successful Case for HFC NPP Digital I and C Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Hsu, Allen; Crow, Ivan; Reese, Carl; Kim, Jong; Yang, Steve [Doosan HF Controls Corp, Carrollton (United States)

    2014-08-15

    Field Programmable Gate Arrays (FPGAs), as programmable logic devices (PLDs) have gained a great deal of interests for implementing safety I and C applications in nuclear power plants (NPPs) largely owing to the FPGAs'potential advantage over the currently more common microprocessor-based digital I and C applications. First of all, FPGAs have adequate capabilities for most digital I and C applications in NPPs. Secondly, FPGAs provide products with longer lifetime, improve testability, and reduce the drift which occurs in analog-based systems, from hardware perspective. Thirdly, FPGAs, from software perspective, can be made simpler, less reliant on complex software such as operating systems, which should make FPGAs easier to qualify for nuclear safety applications. Fourthly, FPGAs are less vulnerable to cyber attacks when FPGAs implement the I and C systems that do not contain high-level, general purpose software that may be easily subjected to malicious modifications. Finally, FPGAs can bring cost reduction in an I and C digital upgrade because FPGAs can provide simpler licensing process than microprocessor-based digital I and C, and FPGAs can be implemented more efficiently. This paper will present one successful case for YGN Unit I and C upgrade using FPGA-based components to replace the obsolete Intel 8085 Microprocessor-based controllers. In this case, FPGAs emulated the process of the existing microprocessors and interpreted the execution of CPU processing. More than 160 of the FPGA-based SBC-01 controllers replacing the Intel 8085 Microprocessor-based Printed Circuit Boards have been installed and running successfully for safety I and C applications over the last five years. In this upgrade, the new FPGA-based controller board SBC-01 emulated the functions of Intel 8085 microprocessor correctly. It is a successful and cost-effective upgrade.vIn this paper, lifecycle design and implementation process and rigorous V and V activities that were used in the

  8. Microprocessor based beam loss monitor system for the AGS

    International Nuclear Information System (INIS)

    Witkover, R.L.

    1979-01-01

    An array of 120 long radiation monitors (LRM) have been installed around the AGS. Each monitor is an extended coaxial ion chamber, 5 meters long, made from hollow core coaxial transmission cable pressured with argon. The LRM's are each connected to a low current preamplifier and voltage-to-frequency converter (VFC). The digital output of each channel is fed to a 16 bit counter chip which bridges the bus of an 8085 microprocessor. This circuit is connected to the AGS PD-10 for data taking or may function as a stand-alone unit. Various operating modes can be selected for data readout. System design and operating performance are described

  9. Microprocessor architectures RISC, CISC and DSP

    CERN Document Server

    Heath, Steve

    1995-01-01

    'Why are there all these different processor architectures and what do they all mean? Which processor will I use? How should I choose it?' Given the task of selecting an architecture or design approach, both engineers and managers require a knowledge of the whole system and an explanation of the design tradeoffs and their effects. This is information that rarely appears in data sheets or user manuals. This book fills that knowledge gap.Section 1 provides a primer and history of the three basic microprocessor architectures. Section 2 describes the ways in which the architectures react with the

  10. A feedback microprocessor for hadron colliders

    International Nuclear Information System (INIS)

    Herrup, D.A.; Chapman, L.; Franck, A.; Groves, T.; Lublinsky, B.

    1992-12-01

    A feedback microprocessor has been built for the TEVATRON. It has been constructed to be applicable to hadron colliders in general. Its inputs are realtime accelerator measurements, data describing the state of the TEVATRON, and ramp tables. The microprocessor software includes a finite state machine. Each state corresponds to a specific TEVATRON operation and has a state-specific TEVATRON model. Transitions between states are initiated by the global TEVATRON clock. Each state includes a cyclic routine which is called periodically and where all calculations are performed. The output corrections are inserted onto a fast TEVATRON-wide link from which the power supplies will read the realtime corrections. We also store all of the input data and output corrections in a set of buffers which can easily be retrieved for diagnostic analysis. In this paper we will describe this device and its use to control the TEVATRON tunes as well as other possible applications

  11. Use of a microprocessor in a remote working level monitor

    International Nuclear Information System (INIS)

    Keffe, D.J.; McDowell, W.P.; Groer, P.G.

    1975-01-01

    A remote working level monitor was designed to measure short-lived radon-daughter concentrations in sealed chambers having potentially high radiation levels (up to 2000 WL). The system is comprised of surface barrier detectors, multiplexer and buffers, microprocessor and teletype

  12. Microprocessor controlled dual parameter ADC system with a CAMAC interface

    Energy Technology Data Exchange (ETDEWEB)

    Perry, D G; Nickell, Jr, J D [Los Alamos Scientific Lab., NM (USA)

    1978-09-01

    Presented here is the design of a dual parameter ADC system which is controlled by a microprocessor and also interfaced to CAMAC. The system was designed to be mobile in that it may work wherever there is a CAMAC crate. In such cases where the CAMAC system is inoperative, the system may operate in a stand-alone mode.

  13. Microprocessorized NMR measurement

    International Nuclear Information System (INIS)

    Rijllart, A.

    1984-01-01

    An MC68000 CAMAC microprocessor system for fast and accurate NMR signal measurement will be presented. A stand-alone CAMAC microprocessor system (MC68000 STAC) with a special purpose interface sweeps a digital frequency synthesizer and digitizes the NMR signal with a 16-bit ADC of 17 μs conversion time. It averages the NMR signal data over many sweeps and then transfers it through CAMAC to a computer for calculation of the signal parameters. The computer has full software control over the timing and sweep settings of this signal averager, and thus allows optimization of noise suppression. Several of these processor systems can be installed in the same crate for parallel processing, and the flexibility of the STAC also allows easy adaptation to other applications such as transient recording or phase-sensitive detection. (orig.)

  14. Multi-core Microprocessors

    Indian Academy of Sciences (India)

    Based on empirical data, Gordon Moore .... there are numerous models of the same Intel microprocessor such as Pentium. 3). ... returns. The limit on instruction and thread-level processing coupled with ..... This style of parallel programming is.

  15. Microprocessor multi-task monitor

    International Nuclear Information System (INIS)

    Ludemann, C.A.

    1983-01-01

    This paper describes a multi-task monitor program for microprocessors. Although written for the Intel 8085, it incorporates features that would be beneficial for implementation in other microprocessors used in controlling and monitoring experiments and accelerators. The monitor places permanent programs (tasks) arbitrarily located throughout ROM in a priority ordered queue. The programmer is provided with the flexibility to add new tasks or modified versions of existing tasks, without having to comply with previously defined task boundaries or having to reprogram all of ROM. Scheduling of tasks is triggered by timers, outside stimuli (interrupts), or inter-task communications. Context switching time is of the order of tenths of a milllisecond

  16. Microprocessor Protection of Power Reducing Transformers

    OpenAIRE

    F. A. Romanuk; S. P. Korolev; M. S. Loman

    2011-01-01

    The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

  17. ''NICRO'' microprogramming language for sectional microprocessors

    International Nuclear Information System (INIS)

    Semenov, Yu.A.; Chudakov, V.N.

    1982-01-01

    ''MICRO'' microprogramming input language developed for sectional microprocessors is described. The structure of micromanual, purpose of particular fields, the corresponding mne-- mocodes and requirements they have to meet are considered. Program for integer division with a sign written in the ''MICRO'' language is given as an example. The possibilities of modif ying the translator for its adaptation to different types of processor and microprocessor sets are analyzed

  18. Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

    Science.gov (United States)

    Delaat, J. C.; Soeder, J. F.

    1983-01-01

    High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

  19. Microprocessors in detectors and analysis

    International Nuclear Information System (INIS)

    Siskind, E.J.

    1982-01-01

    The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led to the examination of the use of microprocessors in various aspects of HEP computing. A brief (and admittedly somewhat biased) review is given of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

  20. Microprocessors in detectors and analysis

    International Nuclear Information System (INIS)

    Siskind, E.J.

    1982-01-01

    The increasing need in high energy physics experiments for computation power for both online and offline applications, coupled with the current microprocessor revolution, has led us to examine the use of microprocessors in various aspects of HEP computing. The following article is a brief (and admittedly somewhat biased) review of current hardware products, the costs of developing and producing hardware systems, and the costs of providing appropriate software support tools which allow one to make effective use of physicists' time, and the applicability of certain systems to the various needs of HEP computing

  1. Microprocessor Protection of Power Reducing Transformers

    Directory of Open Access Journals (Sweden)

    F. A. Romanuk

    2011-01-01

    Full Text Available The paper contains analysis of advantages and disadvantages of existing differential protection terminals of power reducing transformers. The paper shows that there are good reasons to develop microprocessor protection of power reducing transformer which contains required functions and settings and which is based on Belarusian principles of relay protection system construction. The paper presents functional structure of microprocessor terminal of power reducing transformer which is developed. 

  2. Introduction to 6800/6802 microprocessor systems hardware, software and experimentation

    CERN Document Server

    Simpson, Robert J

    1987-01-01

    Introduction to 6800/6802 Microprocessor Systems: Hardware, Software and Experimentation introduces the reader to the features, characteristics, operation, and applications of the 6800/6802 microprocessor and associated family of devices. Many worked examples are included to illustrate the theoretical and practical aspects of the 6800/6802 microprocessor.Comprised of six chapters, this book begins by presenting several aspects of digital systems before introducing the concepts of fetching and execution of a microprocessor instruction. Details and descriptions of hardware elements (MPU, RAM, RO

  3. Process control by microprocessors

    Energy Technology Data Exchange (ETDEWEB)

    Arndt, W [ed.

    1978-12-01

    Papers from the workshop Process Control by Microprocessors being organized by the Karlsruhe Nuclear Research Center, Project PDV, together with the VDI/VDE-Gesellschaft fuer Mess- und Regelungstechnik are presented. The workshop was held on December 13 and 14, 1978 at the facilities of the Nuclear Research Center. The papers are arranged according to the topics of the workshop; one chapter deals with today's state of the art of microprocessor hardware and software technology; 5 chapters are dedicated to applications. The report also contains papers which will not be presented at the workshop. Both the workshop and the report are expected to improve and distribute the know-how about this modern technology.

  4. Microprocessor Controlled Maximum Power Point Tracker for Photovoltaic Application

    International Nuclear Information System (INIS)

    Jiya, J. D.; Tahirou, G.

    2002-01-01

    This paper presents a microprocessor controlled maximum power point tracker for photovoltaic module. Input current and voltage are measured and multiplied within the microprocessor, which contains an algorithm to seek the maximum power point. The duly cycle of the DC-DC converter, at which the maximum power occurs is obtained, noted and adjusted. The microprocessor constantly seeks for improvement of obtained power by varying the duty cycle

  5. CAMAC based computer--computer communications via microprocessor data links

    International Nuclear Information System (INIS)

    Potter, J.M.; Machen, D.R.; Naivar, F.J.; Elkins, E.P.; Simmonds, D.D.

    1976-01-01

    Communications between the central control computer and remote, satellite data acquisition/control stations at The Clinton P. Anderson Meson Physics Facility (LAMPF) is presently accomplished through the use of CAMAC based Data Link Modules. With the advent of the microprocessor, a new philosophy for digital data communications has evolved. Data Link modules containing microprocessor controllers provide link management and communication network protocol through algorithms executed in the Data Link microprocessor

  6. SNOOP module CAMAC interface to the 168/E microprocessor

    International Nuclear Information System (INIS)

    Bernstein, D.; Carroll, J.T.; Mitnick, V.H.; Paffrath, L.; Parker, D.B.

    1979-10-01

    A pair of 168/E microprocessors will be used to meet the realtime computing requirements of the SLAC Hybrid Facility. A SNOOP module and 168/E Interface provide the link between the host computer and the microprocessors. By eavesdropping on normal CAMAC read operations, the SNOOP provides a direct data transfer from CAMAC to microprocessor memory. The host computer controls the processors using standard CAMAC programmed I/O to the SNOOP

  7. The use of distributed microprocessors for control devices

    International Nuclear Information System (INIS)

    Lejon, J.C.

    1978-01-01

    The use of distributed individual microprocessors provided the basis for the development of the μZ system, which is a modular numerical control device which in its main part contains no elements whatever with multiple functions. With this system, total availability of control is achieved and the failure of any individual element causes loss of automatic control only over one actuator or over a small group of interdependent actuators. The human operator, who cannot be omitted even with an inherently safe control system, can operate the single faulty channel manually. The microprocessors have a free-format with which all possible algorithms within the limits of the memory size of the various cards can be performed. This program can be loaded either in random access memory (RAM) or in read-only memory (ROM). The configuration is made either by assembling software modules in a hard-copy dialogue without any knowledge of data processing being necessary, or from a program written in Fortran. If the user does not have a configurator he can use read-only memories supplied by the manufacter either in the standard form or in a requested design. The parameters are loaded by means of a portable microconsole whose keyboard and displays can be used for a hard-copy dialogue with the regulating cards. Manual control and indications can be carried out from three completely independent configurations which can be used separately or in parallel: individual station, multiple-function station or cathode colour console. (author)

  8. System architecture for microprocessor based protection system

    International Nuclear Information System (INIS)

    Gallagher, J.M. Jr.; Lilly, G.M.

    1976-01-01

    This paper discusses the architectural design features to be employed by Westinghouse in the application of distributed digital processing techniques to the protection system. While the title of the paper makes specific reference to microprocessors, this is only one (and the newest) of the building blocks which constitutes a distributed digital processing system. The actual system structure (as realized through utilization of the various building blocks) is established through considerations of reliability, licensability, and cost. It is the intent of the paper to address these considerations licenstions as they relate to the architectural design features. (orig.) [de

  9. Extended performance electric propulsion power processor design study. Volume 2: Technical summary

    Science.gov (United States)

    Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

    1977-01-01

    Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

  10. Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

    Energy Technology Data Exchange (ETDEWEB)

    Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh [Institute of Materials Science, Vietnam Academy of Science and Technology, 18 Hoang Quoc Viet Road, Cau Giay District, Hanoi (Viet Nam)], E-mail: minhpn@ims.vast.ac.vn

    2009-09-01

    One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

  11. Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

    Science.gov (United States)

    Thang, Bui Hung; Hong, Phan Ngoc; Khoi, Phan Hong; Minh, Phan Ngoc

    2009-09-01

    One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5°C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

  12. Application of multiwall carbon nanotubes for thermal dissipation in a micro-processor

    International Nuclear Information System (INIS)

    Bui Hung Thang; Phan Ngoc Hong; Phan Hong Khoi; Phan Ngoc Minh

    2009-01-01

    One of the most valuable properties of the carbon nanotubes materials is its high thermal conductivity with 2000 W/m.K (compared to thermal conductivity of Ag 419 W/m.K). It suggested an approach in applying the CNTs in thermal dissipation media to improve the performance of computer processors and other high power electronic devices. In this research, the multiwall carbon nanotubes (MWCNTs) made by thermal chemical vapour deposition (CVD) at our laboratory was employed as the heat dissipation media in a microprocessor a Personal Computer with configuration: Intel Pentium IV 3.066 GHz, 512Mb of RAM and Windows XP Service Pack 2 Operating System. We directly measured the temperature of the microprocessor during the operation of the computer in two modes: 100% usage CPU mode and over-clocking mode. The measured results showed that when using our thermal dissipation media (a mixture of the mentioned commercial thermal compound and 2 wt.%. MWCNTs), the temperature of the microprocessor decreased 5 deg. C, and the time for increasing the temperature of the microprocessor was three times longer than that when using commercial thermal compound. In over-clocking mode, the processor speed reached 3.8 GHz with 165 MHz of system bus clock speed; it was 1.24 times higher than that in non over-clocking mode. The results confirmed a promising way of using MWCNTs as the thermal dissipation media for microprocessor and high power electronic devices.

  13. API testing program - calibration of microprocessor based flowmeters for integrated metering systems

    Energy Technology Data Exchange (ETDEWEB)

    Elliot, Kenneth D. [Omni Flow Computers, Inc., Stafford, TX (United States)

    2005-07-01

    Microprocessor based flowmeter technologies for liquids, such as Coriolis mass meters, and Ultrasonic flowmeters hold great promise. These technologies offer many advantages, such as no rotating parts, self-diagnostic checks, which can help anticipate and warn of impending failures before they have a major impact on the measurement. These meters are substantially different though than other primary devices due to their heavy reliance on the accompanying secondary electronics. One method to prove that they are accurate would be proving the flowmeter, using a pipe prover or small volume prover (SVP), but these proving methods are designed to count 'real time' pulses from a turbine or PD meter between a known volume, they are not designed to count 'time delayed' 'manufactured pulses' from a microprocessor. There are limitations of the manufactured pulse train and it affects the ability of the flowmeter to be proved using current proving technology. The author of this paper, a chairman of an American Petroleum Institute working group, investigated how the 'microprocessor generated pulses' produced by these types of flowmeters, interacted with the existing measurement technologies in use today. Several microprocessor based flowmeter technologies have been tested, including; Ultrasonic, Coriolis, and Helical Turbine with pulse multiplying preamplifier. Wherever possible, flowmeters of various sizes, and from several vendors have been tested. A significant amount of data has been collected which sheds light into why these types of flowmeters are sometimes difficult to prove. This paper describes the API testing program, and the methodology behind it. It presents results and findings, and offers specific recommendations that may eventually be incorporated into API documents and/or standards in the future. (author)

  14. Microprocessor controlled digital period meter

    International Nuclear Information System (INIS)

    Keefe, D.J.; McDowell, W.P.; Rusch, G.K.

    1980-01-01

    A microprocessor controlled digital period meter has been developed and tested operationally on a reactor at Argonne National Laboratory. The principle of operation is the mathematical relationship between asymptotic periods and pulse counting circuitry. This relationship is used to calculate and display the reactor periods over a range of /plus or minus/1 second to /plus or minus/999 seconds. The time interval required to update each measurement automatically varies from 8 seconds at the lowest counting rates to 2 seconds at higher counting rates. The paper will describe hardware and software design details and show the advantages of this type of Period Meter over the conventional circuits. 1 ref

  15. Microprocessor-controlled scanning densitometer system

    International Nuclear Information System (INIS)

    Shurtliff, R.W.

    1980-04-01

    An Automated Scanning Densitometer System has been developed by uniting a microprocessor with a low energy x-ray densitometer system. The microprocessor controls the detector movement, provides self-calibration, compensates raw readings to provide time-linear output, controls both data storage and the host computer interface, and provides measurement output in engineering units for immediate reading. The densitometer, when used in a scanning mode, is a precision reference instrument that provides chordal average density measurements over the cross section of a pipe under steady-state flow conditions. Results have shown an improvement over the original densitometer in reliability and repeatability of the system, an a factor-of-five improvement in accuracy

  16. A microprocessor based multiscaling data acquisition system for moessbauer spectroscopy

    International Nuclear Information System (INIS)

    Bohm, C.; Ekdahl, T.

    1985-01-01

    A microprocessor based data acquisition system is described, which was developed for use in Moessbauer spectroscopy. It is designed to record two spectra simultaneously, one of which could be a calibration spectrum. It is autonomous, but uses a host computer for initialization and permanent storage of data. The host communication software is also described. (Author)

  17. The engineering of microprocessor systems guidelines on system development

    CERN Document Server

    1979-01-01

    The Engineering of Microprocessor Systems: Guidelines on System Development provides economical and technical guidance for use when incorporating microprocessors in products or production processes and assesses the alternatives that are available. This volume is part of Project 0251 undertaken by The Electrical Research Association, which aims to give managers and development engineers advice and comment on the development process and the hardware and software needed to support the engineering of microprocessor systems. The results of Phase 1 of the five-phase project are contained in this fir

  18. Microprocessor based data acquisition system for Moessbauer spectrometer

    International Nuclear Information System (INIS)

    Patwardhan, P.K.; Indurkar, V.S.

    1981-01-01

    A data acquisition system, for Moessbauer spectrometer and other probability distribution spectrum is described. This utilizes the advantages of incorporating a microcomputer for providing a flexible analytical capability and speed of hard wired MCS unit updating channel contents in DMA. Holbourn, Player and Woodhams have recently described a microprocessor controlled Moessbauer spectrometer where microprocessor performs the task of updating channel contents, requiring about 60 micro seconds in interrupt mode. This imposes restrictions on increasing the channel number and on increasing the velocity scan frequency in order to cover higher velocity ranges. The system described in this article performs data acquisition in faster direct memory access. It is a two module system, (1) MCS module (2) Microcomputer module, arranged around a common address, data and control buses. The microcomputer module has an access to the system data during flyback periods and can be programmed for the task of monitor on progess of experiment and as a manipulator of various control operations needed during experiment. The system firmware includes: (1) MONITOR (2) BLOCK-TRANSFER (3) DATA-SMOOTHING (4) DECIMAL-CONVERTER (5) MATH. The scope of this firmware is briefly described. (author)

  19. Microprocessor tester for the treat upgrade reactor trip system

    International Nuclear Information System (INIS)

    Lenkszus, F.R.; Bucher, R.G.

    1984-01-01

    The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations

  20. High speed serial link for UA1 microprocessor network

    CERN Document Server

    Cittolin, S; Zurfluh, E

    1981-01-01

    The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

  1. High speed serial link for UA1 microprocessor network

    CERN Document Server

    Cittolin, Sergio; Zurfluh, E

    1981-01-01

    The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment test/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system, it is running as an ancillary serial loop-link between microprocessors, like data acquisition crate controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI computer language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. ...

  2. Leak detection system with distributed microprocessor in the primary containment vessel

    International Nuclear Information System (INIS)

    Inahara, K.; Yoshioka, K.; Tomizawa, T.

    1980-01-01

    Responding to the demand for greater improvements of the safety monitoring system, less public radiation exposure, and increase of plant availability, measuring and control systems in nuclear power plants have undergone many improvements. Leak detection systems are also required to give earlier warning, additional accuracy, and continuous monitoring function. This paper describes the drywell sump leakage detection system utilizing a distributed microprocessor, which is a successful application owing to its versatile function and ease of installation. The microprocessor performs various functions such as a rate of level change computation, conversion to leakage flow rate, initiation of alarm, and sump pump control. This system has already been applied to three operating BWR plants that demonstrate its efficiency. (auth)

  3. Adapting to change: influence of a microprocessor-controlled prosthetic knee on gait adaptations

    NARCIS (Netherlands)

    Prinsen, Erik Christiaan

    2016-01-01

    Advancement in prosthetic knee design have led to the introduction of microprocessor-controlled prosthetic knees (MPKs). MPKs incorporate sensors that are able to measure prosthetic loading, the knee angle, and knee angular velocity. Based on the sensor information, MPKs determine the optimal level

  4. Application of microprocessor based controller in the Breeder Reactor Program

    International Nuclear Information System (INIS)

    Messick, N.C.; Lukas, M.P.

    1985-01-01

    This paper treats Argonne National Laboratory's experience using microprocessor based controllers presently in use on several control loops within the EBR-II reactor facility as well as tests being performed by these controllers. Also included is a discussion of the expandability, modularity, range of capabilities and higher level functions possible using such equipment

  5. Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

    Directory of Open Access Journals (Sweden)

    Jakub Dolata

    2018-06-01

    Full Text Available MicroRNAs are small molecules (∼21 nucleotides long that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1, the zinc finger protein Serrate (SE, and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1. Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2 and phosphatases (CPL1 and PP4. Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3 that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

  6. Application of microprocessors to radiation protection measurements

    International Nuclear Information System (INIS)

    Zappe, D.; Meldes, C.

    1982-01-01

    In radiation protection measurements signals from radiation detectors or dosemeters have to be transformed into quantities relevant to radiation protection. In most cases this can only be done by taking into account various parameters (e.g. the quality factor). Moreover, the characteristics of the statistical laws of nuclear radiation emission have to be considered. These problems can properly be solved by microprocessors. After reviewing the main properties of microprocessors, some typical examples of applying them to problems of radiation protection measurement are given. (author)

  7. High speed serial link for UA1 microprocessor network

    International Nuclear Information System (INIS)

    Cittolin, S.; Loefstedt, B.; Zurfluh, E.

    1981-01-01

    The UA1 data acquisition system consists of a set of distributed microprocessor units. An interprocessor link, independent of the CAMAC data readout, has been developed in order to have continuous remote control and run-time data handling, e.g. transmission of calibration programs/parameters, equipment rest/status and histogram accumulation. The data transmission system is designed to be used in a loop configuration equipped with transceivers for twisted pair cables (RS-422). As an economical system it is running as an ancillary serial loop-link between microprocessors Like Data Acquisition Crate Controllers and systems with distributed intelligence. The software driver consists of a loop-controller package, which may run in a BAMBI Computer Language environment and a fully interrupt controlled program for all other secondary stations. A special single-character mode provides a handy link for remote debugging in a pseudo-full-duplex mode. The format is based on the HDLC protocol without sequence numbering. The Chip MC-6854 from Motorola, Inc. enables an implementation with few components. (orig.)

  8. The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

    Science.gov (United States)

    2017-09-01

    motion and active power , will translate into improved functional performance, ambulatory safety (risk of falls) and quality of life in trans-tibial...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power , will...contact over a 6 month period of time and receive physical therapy training to minimize deviations resulting from habit or lack of training, education

  9. A microprocessor based picture analysis system for automatic track measurements

    International Nuclear Information System (INIS)

    Heinrich, W.; Trakowski, W.; Beer, J.; Schucht, R.

    1982-01-01

    In the last few years picture analysis became a powerful technique for measurements of nuclear tracks in plastic detectors. For this purpose rather expensive commercial systems are available. Two inexpensive microprocessor based systems with different resolution were developed. The video pictures of particles seen through a microscope are digitized in real time and the picture analysis is done by software. The microscopes are equipped with stages driven by stepping motors, which are controlled by separate microprocessors. A PDP 11/03 supervises the operation of all microprocessors and stores the measured data on its mass storage devices. (author)

  10. Microprocessors in physics experiments at SLAC

    International Nuclear Information System (INIS)

    Rochester, L.S.

    1981-01-01

    The increasing size and complexity of high energy physics experiments is changing the way data are collected. To implement a trigger or event filter requires complex logic which may have to be modified as the experiment proceeds. Simply to monitor a detector, large amounts of data must be processed online. The use of microprocessors or other programmable devices can help to achieve these ends flexibly and economically. At SLAC, a number of microprocessor-based systems have been built and are in use in experimental setups, and others are now being developed. This talk is a review of existing systems and their use in experiments, and of developments in progress and future plans. (orig.)

  11. Microprocessors in physics experiments at SLAC

    International Nuclear Information System (INIS)

    Rochester, L.S.

    1981-04-01

    The increasing size and complexity of high energy physics experiments is changing the way data are collected. To implement a trigger or event filter requires complex logic which may have to be modified as the experiment proceeds. Simply to monitor a detector, large amounts of data must be processed on line. The use of microprocessors or other programmable devices can help to achieve these ends flexibly and economically. At SLAC, a number of microprocessor-based systems have been built and are in use in experimental setups, and others are now being developed. This talk is a review of existing systems and their use in experiments, and of developments in progress and future plans

  12. Microprocessor based techniques at CESR

    International Nuclear Information System (INIS)

    Giannini, G.; Cornell Univ., Ithaca, NY

    1981-01-01

    Microprocessor based systems succesfully used in connection with the High Energy Physics experimental program at the Cornell Electron Storage Ring are described. The multiprocessor calibration system for the CUSB calorimeter is analyzed in view of present and future applications. (orig.)

  13. A microprocessor controlled read out system for drift chambers

    CERN Document Server

    Centro, Sandro; Cittolin, Sergio; Dreesen, P; Petrolo, E; Rubbia, Carlo; Schinzel, D

    1981-01-01

    Summary form only given, as follows. A General Purpose Microprocessor Controller GPMC has been developed for applications where CAMAC modules with complex control functions are needed. Each application requires an appropriate Interface Module (IM) to be connected to the GPMC. The GPMC consists of a 6800 Microprocessor, 16K EPROM, 2K RAM, CAMAC I/O ports and interface, a RS 232C serial interface, an Advanced Data Link controller and a port for controlling the IM, GPMC and IM are housed in a 2-U wide CAMAC module. A special IM has been designed, which has 1K bute of RAM with its own control and which allows autonomous setting and reading analog voltages through a DAC and ADC. The GPMC can take control of the IM memory and set new voltages. This system is used to control pedestals and gains of a driftchamber readout system, which is housed in a 5-U wide CAMAC module, holding 24 data cards corresponding to 24 sense wires. The data card receives pulses from the left and right end of a sense wire, amplifies and int...

  14. Microprocessor-based data acquisition systems for Hera experiments

    International Nuclear Information System (INIS)

    Haynes, W.J.

    1989-09-01

    Sophisticated multi-microprocessor configurations are envisaged to cope with the technical challenges of the HERA electron-proton collider and the high data rates from the two large experiments H1 and ZEUS. These lecture notes concentrate on many of the techniques employed, with much emphasis being placed on the use of the IEEE standard VMEbus as a unifying element. The role of modern 32-bit CISC and RISC microprocessors, in the handling of data and the filtering of physics information, is highlighted together with the integration of personal computer stations for monitoring and control. (author)

  15. AFRRI's conversion to a microprocessor-based reactor instrumentation and control system

    International Nuclear Information System (INIS)

    Moore, Mark L.; Hodgdon, Kenneth M.

    1986-01-01

    The Armed Forces Radiobiology Research Institute (AFRRI) is procuring a state-of- the-art microprocessor-based instrumentation and control system to operate AFRRI's 1 MW (steady-state), 3000 MW (pulse) TRIGA Mark-F reactor. This system will replace the current control console while improving or maintaining the existing operational capabilities and safety characteristics. The new unit will have a 15-year design life using state-of-the-art components

  16. Microprocessor-controlled surface testing

    Energy Technology Data Exchange (ETDEWEB)

    Droscha, H

    1982-09-01

    For the quality inspection on continuous flow material webs with transverse scanning laser beam, the microprocessor control, realized now for the first time in combination with appropriate units, shows a considerable progress. Thanks to the here used electronics, surface errors can be localized within the web according to their x-y-position, quantitative analysis can be carried out and automatic sorting and registration functions can be used.

  17. Real time computer system with distributed microprocessors

    International Nuclear Information System (INIS)

    Heger, D.; Steusloff, H.; Syrbe, M.

    1979-01-01

    The usual centralized structure of computer systems, especially of process computer systems, cannot sufficiently use the progress of very large-scale integrated semiconductor technology with respect to increasing the reliability and performance and to decreasing the expenses especially of the external periphery. This and the increasing demands on process control systems has led the authors to generally examine the structure of such systems and to adapt it to the new surroundings. Computer systems with distributed, optical fibre-coupled microprocessors allow a very favourable problem-solving with decentralized controlled buslines and functional redundancy with automatic fault diagnosis and reconfiguration. A fit programming system supports these hardware properties: PEARL for multicomputer systems, dynamic loader, processor and network operating system. The necessary design principles for this are proved mainly theoretically and by value analysis. An optimal overall system of this new generation of process control systems was established, supported by results of 2 PDV projects (modular operating systems, input/output colour screen system as control panel), for the purpose of testing by apllying the system for the control of 28 pit furnaces of a steel work. (orig.) [de

  18. A fastbus master based on a risc microprocessor

    International Nuclear Information System (INIS)

    Cerrito, L.; Chorowicz, V.; Lebbolo, H.; Vallereau, A.

    1990-01-01

    SISIFUS is a general purpose Fastbus Master and Slave able to perform any operation on both Fastbus segments. Master operations are directed either by the processor or by two fast sequencers. A Block Mover function is implemented allowing direct data block transfers between two Slaves. SISIFUS uses the AM 29000 RISC microprocessor which can execute every assembler instruction in 40ns. The on-board monitor/debugger allows programs to be written in assembler from a terminal connected to the module or written in C and cross compiled on a host computer (PC)

  19. Cross software for microprocessor program development at CERN

    International Nuclear Information System (INIS)

    Eicken, H. von; Montuelle, J.; Willers, I.; Blake, J.

    1981-01-01

    Programs for a variety of microprocessors (including Intel 8080; Motorola 6800 and 6809 and 68000; and Texas Instruments 9900) can be prepared on different host computers (such as IBM 370, CDC 6000, and Nord 10) using portable programs developed at CERN. The range of cross software consists of: an assembler for each target microprocessor, a single linkage editor, a single object module librarian, and a variety of pre-loaders which convert object modules from CERN's format (CUFOM) into manufacturers' formats. The programs are written in BCPL and PASCAL, programming languages which are available on a wide range of computers. (orig.)

  20. Microprocessor system to recover data from a self-scanning photodiode array

    International Nuclear Information System (INIS)

    Koppel, L.N.; Gadd, T.J.

    1975-01-01

    A microprocessor system developed at Lawrence Livermore Laboratory has expedited the recovery of data describing the low energy x-ray spectra radiated by laser-fusion targets. An Intel microprocessor controls the digitization and scanning of the data stream of an x-ray-sensitive self-scanning photodiode array incorporated in a crystal diffraction spectrometer

  1. Single event effect testing of the Intel 80386 family and the 80486 microprocessor

    International Nuclear Information System (INIS)

    Moran, A.; LaBel, K.; Gates, M.; Seidleck, C.; McGraw, R.; Broida, M.; Firer, J.; Sprehn, S.

    1996-01-01

    The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored

  2. The European Logarithmic Microprocessor

    Czech Academy of Sciences Publication Activity Database

    Coleman, J. N.; Softley, C. I.; Kadlec, Jiří; Matoušek, R.; Tichý, Milan; Pohl, Zdeněk; Heřmánek, Antonín; Benschop, N. F.

    2008-01-01

    Roč. 57, č. 4 (2008), s. 532-546 ISSN 0018-9340 Grant - others:Evropská komise(BE) ESPRIT 33544 Institutional research plan: CEZ:AV0Z10750506 Source of funding: R - rámcový projekt EK Keywords : Processor architecture * arithmetic unit * logarithmic arithmetic Subject RIV: JC - Computer Hardware ; Software Impact factor: 2.611, year: 2008 http://library.utia.cas.cz/separaty/2008/ZS/kadlec-the%20european%20logarithmic%20microprocessor.pdf

  3. A microprocessor based area monitor system for neutron and gamma radiation

    International Nuclear Information System (INIS)

    Wilhelm, R.; Heusser, G.

    1980-01-01

    The conventional electronics of the area monitors at the MPI-Heidelberg accelerators have been replaced by a microprocessor system consisting of individual detector-microprocessors and a central microcomputer. The detector microprocessors convert the count rates of BF3 and GM counter tubes into dose rates and control three different radiation thresholds (failure, low and high level). Different warning signals are operated directly by the detector processors, whereas the dose rates are transferred to the central microcomputer. Here the data are processed for recording on tape and displaying on TV monitors. The detector as well as the central processors have been developed on the basis of a 16-bit microprocessor. In the control rooms the dose rates of the individual monitors are displayed and on an indicator board showing the different locations, the high radiation level and the state of the doors (open, locked, and closed, locked but open) are sianaled by different LED. If a high radiation threshold is surpassed, the doors adjacent to that area can be locked either by switches on the indicator board or automatically. Within the experimental area, the low and high radiation level is indicated by acoustic and light signals. The whole concept permits keeping the absorbed doses of the personnel as low as possible without affecting the flexibility of the experimental operations. The independence of the microprocessor driven area monitors guarantees a high reliability. Compared to conventional electronics the advantages of the system are its reliability and cost. (Author)

  4. Autonomous controller (JCAM 10) for CAMAC crate with 8080 (INTEL) microprocessor

    International Nuclear Information System (INIS)

    Gallice, P.; Mathis, M.

    1975-01-01

    The CAMAC crate autonomous controller JCAM-10 is designed around an INTEL 8080 microprocessor in association with a 5K RAM and 4K REPROM memory. The concept of the module is described, in which data transfers between CAMAC modules and the memory are optimised from software point of view as well as from execution time. In fact, the JCAM-10 is a microcomputer with a set of 1000 peripheral units represented by the CAMAC modules commercially available

  5. Integration in a nuclear physics experiment of a visualization unit managed by a microprocessor

    International Nuclear Information System (INIS)

    Lefebvre, M.

    1976-01-01

    A microprocessor (Intel 8080) is introduced in the equipment controlling the (e,e'p) experiment that will take place at the linear accelerator operating in the premises of CEA (Orme des Merisiers, Gif-sur-Yvette, France). The purpose of the microprocessor is to handle the visualization tasks that are necessary to have a continuous control of the experiment. By doing so more time and more memory will be left for data processing by the calculator unit. In a forward version of the system, the controlling of the level of helium in the target might also be in charge of the microprocessor. This work is divided into 7 main parts: 1) a presentation of the linear accelerator and its experimental facilities, 2) the Intel 8080 micro-processor and its programming, 3) the implementation of the micro-processor in the electronic system, 4) the management of the memory, 5) data acquisition, 6) the keyboard, and 7) the visualization unit [fr

  6. Concept report: Microprocessor control of electrical power system

    Science.gov (United States)

    Perry, E.

    1977-01-01

    An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

  7. Microprocessing in European High Energy Physics Experiments - ECFA Working Group on Data Processing Standards - Report of the Microprocessor Subgroup May 1982

    CERN Document Server

    European Committee for Future Accelerators (ECFA)

    1982-01-01

    This document contains two reports on the use of microprocessors in European High-Energy Physics experiments. The first is a presentation of data collected by a sub-group of the ECFA working group on data procesing standards. The working group is organised by E. Lillestol, University of Bergen and E.M. Rimmer, CERN, DD Division; the Microprocessor sub-group organiser is L.O. Hertzberger, NIKHEF, Amsterdam. Data are given from projects numbered 81 - 194, and some CERN projects are included. Even though there is some duplication of information, a second report has been appended which covers a wider range of CERN projects. This was the result of a microprocessor survey made at CERN by P. Scharff-Hansen, DD Division, at the request of E. Gabthuler. The ECFA working group intends to have reports for all the sub-groups (10 in number) available in machine-readable form at the CERN computer centre. However, it was felt that the information herein is most valuable to designers and users of microprocessors, and that it...

  8. Auxiliary/Master microprocessor CAMAC Crate Controller applications

    International Nuclear Information System (INIS)

    Barsotti, E.

    1975-01-01

    The need for further sophistication of an already complex serial CAMAC control system at Fermilab led to the development of an Auxilary/Master CAMAC Crate Controller. The controller contains a Motorola 6800 microprocessor, 2K bytes of RAM, and 8K bytes of PROM memory. Bussed dataway lines are time shared with CAMAC signals to provide memory expansion and direct addressing of peripheral devices without the need of external cabling. The Auxiliary/Master Crate Controller (A/MCC) can function as either a Master, i.e., stand alone, crate controller or as an Auxiliary controller to Fermilab's Serial Crate Controller (SCC). Two modules, one single- and one double-width, make up an A/MCC. The microprocessor has one nonmaskable and one maskable vectored interrupt. Time sharing the dataway between SCC programmed and block transfer generated dataway cycles and A/MCC operations still allows a 99 percent microprocessor CPU busy time. Since the conception of the A/MCC, there has been an increasing number of control system-related projects proposed which would not have been possible or would have been very difficult to implement without such a device. The first such application now in use at Fermilab is a stand-alone control system for a mass spectrometer experiment in the Main Ring Internal Target Area. This application in addition to other proposed A/MCC applications, both stand-alone and auxiliary, is discussed

  9. Instrument for bone mineral measurement using a microprocessor as the control and arithmetic element

    International Nuclear Information System (INIS)

    Alberi, J.L.; Hardy, W.H. II.

    1975-11-01

    A self-contained instrument for the determination of bone mineral content by photon absorptometry is described. A high-resolution detection system allows measurements to be made at up to 16 photon energies. Control and arithmetic functions are performed by a microprocessor. Analysis capability and limitations are discussed

  10. An SEU rate prediction method for microprocessors of space applications

    International Nuclear Information System (INIS)

    Gao Jie; Li Qiang

    2012-01-01

    In this article,the relationship between static SEU (Single Event Upset) rate and dynamic SEU rate in microprocessors for satellites is studied by using process duty cycle concept and fault injection technique. The results are compared to in-orbit flight monitoring data. The results show that dynamic SEU rate by using process duty cycle can estimate in-orbit SEU rate of microprocessor reasonable; and the fault injection technique is a workable method to estimate SEU rate. (authors)

  11. Microprocessor control unit of thyristor regulator of microhydroelectric power station ballast load

    International Nuclear Information System (INIS)

    Nomokonova, Yu; Bogdanov, E

    2014-01-01

    The operational principle of microhydroelectric power station ballast load is presented. The comparative overview of the mathematical modeling methods is performed. The ranges of thyristors optimal work are shown as a result of the regulator regimes analysis. Shows the necessity of regulation the ballast load in microhydroelectric power station with help of developed algorithm of the program for microprocessor control

  12. Use of a microprocessor in the CAMAC standard. The dedicated microcomputer: JCAM-10

    International Nuclear Information System (INIS)

    Gallice, Pierre.

    1978-01-01

    The general purpose minicomputers and dedicated crate controllers currently used in small CAMAC systems are now being superseded by autonomous crate controllers with built-in microprocessor such as the JCAM-10, which is in fact a CAMAC dedicated microcomputer. This controller has been designed around the INTEL-8080 microprocessor and employs a semiconductor memory. The very much reduced price and smaller packaging of this module, and the relatively large potential market of CAMAC systems justify the tremendous efforts required for the study of its complete system as well in hardware than in software. After a short description of the CAMAC standard this paper will describe the principle of the microcomputer JCAM-10, and its complementary system: hardware (peripheral modules) and software (TTY command processor, Input Output, Control system, interrupt system, text editor, local macro-assembler, LP and BASICAM local compilers). As application examples, an autonomous counting system and a distributed intelligence system will be described [fr

  13. Application of a microprocessor system to stream monitoring

    International Nuclear Information System (INIS)

    Oakes, T.W.; Shank, K.E.

    1978-01-01

    Low-level liquid wastes originating from the Oak Ridge National Laboratory (ORNL) are discharged, after treatment, into White Oak Creek, which is a small tributary of the Clinch River located in East Tennessee. Samples of White Oak Creek discharges are collected at White Oak Dam by a continuous digital proportional water sampler and analyzed weekly for radioactivity. The sampler contains a control system with a microprocessor that has been programmed to solve nonlinear weir equations. This system was designed and installed at ORNL by the Instrumentation and Controls Division and was tested by the Environmental Surveillance and Evaluation Section of the Industrial Safety and Applied Health Physics Division. The control system was designed to measure water flow rates from 0 to 334 ft 3 /sec to within 0.1%. Results of our test program and possible applications to other liquid sampling needs are discussed

  14. Microprocessor-controlled system for automatic acquisition of potentiometric data and their non-linear least-squares fit in equilibrium studies.

    Science.gov (United States)

    Gampp, H; Maeder, M; Zuberbühler, A D; Kaden, T A

    1980-06-01

    A microprocessor-controlled potentiometric titration apparatus for equilibrium studies is described. The microprocessor controls the stepwise addition of reagent, monitors the pH until it becomes constant and stores the constant value. The data are recorded on magnetic tape by a cassette recorder with an RS232 input-output interface. A non-linear least-squares program based on Marquardt's modification of the Newton-Gauss method is discussed and its performance in the calculation of equilibrium constants is exemplified. An HP 9821 desk-top computer accepts the data from the magnetic tape recorder. In addition to a fully automatic fitting procedure, the program allows manual adjustment of the parameters. Three examples are discussed with regard to performance and reproducibility.

  15. Monitoring with new microprocessor cuts cost of control system

    Energy Technology Data Exchange (ETDEWEB)

    Maehling, K L

    1985-08-01

    Programmable logic controllers (PLC) were originally developed as an alternative to relays, counters and timers for sequential and interlock control systems. They are now also used as part of distributive control systems which include diagnostic monitoring functions. The paper describes how a wiring scheme can be simplified and installation costs reduced by incorporating a newly-developed microprocessor-based monitoring device as an interface between remote devices and a PLC. An industrial application, the 400 tph coal handling facility at Bowater Southern Paper Co's mill in Calhoun, Tennessee, is considered. The control system design is outlined, the micro-monitor is described and the benefits of simplicity are stated in the paper.

  16. A Fault-tolerant RISC Microprocessor for Spacecraft Applications

    Science.gov (United States)

    Timoc, Constantin; Benz, Harry

    1990-01-01

    Viewgraphs on a fault-tolerant RISC microprocessor for spacecraft applications are presented. Topics covered include: reduced instruction set computer; fault tolerant registers; fault tolerant ALU; and double rail CMOS logic.

  17. Cardiac output measurement instruments controlled by microprocessors

    International Nuclear Information System (INIS)

    Spector, M.; Barritault, L.; Boeri, C.; Fauchet, M.; Gambini, D.; Vernejoul, P. de

    The nuclear medicine and biophysics laboratory of the Necker-Enfants malades University Hospital Centre has built a microprocessor controlled Cardiac flowmetre. The principle of the cardiac output measurement from a radiocardiogram is well established. After injection of a radioactive indicator upstream from the heart cavities the dilution curve is obtained by the use of a gamma-ray precordial detector. This curve normally displays two peaks due to passage of the indicator into the right and left sides of the heart respectively. The output is then obtained from the stewart Hamilton principle once recirculation is eliminated. The graphic method used for the calculation however is long and tedious. The decreasing fraction of the dilution curve is projected in logarithmic space in order to eliminate recirculation by determining the mean straight line from which the decreasing exponential is obtained. The principle of the use of microprocessors is explained (electronics, logics) [fr

  18. A microprocessor-controlled assay for the estimation of human placental lactogen

    International Nuclear Information System (INIS)

    Adam, T.; Roulston, J.E.; Bagshawe, K.D.

    1979-01-01

    A radioimmunoassay for human placental lactogen (HPL) is described using the KEMTEK 3000, which is a modular radioimmunoassay apparatus controlled by a microprocessor. Operation of the KEMTEK 3000 is largely automatic and it requires minimal intervention from the operator. It is capable of 300 reactions per hour so that a large number of estimations can readily be performed. HPL was assayed by a double antibody method on serum samples from pregnant women and patients with trophoblastic tumours. (Auth.)

  19. TRIESTE: College on Microprocessors

    International Nuclear Information System (INIS)

    Anon.

    1981-01-01

    The International Centre for Theoretical Physics, set up at Trieste in 1964, has as its major task the provision of a stimulating intellectual environment for physicists from developing countries. This goal is furthered by a varied programme of courses for visiting scientists. Not all the courses remain in the rarefied atmosphere of theory and in September a very successful 'College on Microprocessors: Technology and Applications in Physics' was held. It was a prime example of the efforts being made to spread important modern technology into the developing countries

  20. Microprocessor Activity Controls Differential miRNA Biogenesis In Vivo

    Directory of Open Access Journals (Sweden)

    Thomas Conrad

    2014-10-01

    Full Text Available In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression.

  1. Proceedings of the meeting on applications of microprocessors in accelerator controls and physics experiments, Tsukuba, March 15, 1978

    International Nuclear Information System (INIS)

    Shibata, Shinkichi; Katoh, Tadahiko

    1978-05-01

    The microprocessor was first made public in 1971. In the ensuing few years, its performance has risen, cost lowered and interface more in IC, so it is now easily incorporated in instrumentation and control. Since it is used as electronic component unlike the case of a minicomputer, it has so much larger influence. It differs from the conventional electronic components in that software is required. In the National Laboratory for High Energy Physics, microprocessors are used for performance improvements of the measuring and control instruments and for labor saving. For new component not to induce new other problems, support system and standardization are proceeding for utilization development etc. The present meeting was intended for discussions by people in the field of usage, planning, and means of joint uses for software and hardware. (Mori, K.)

  2. Microprocessors: From basic chips to complete systems

    International Nuclear Information System (INIS)

    Dobinson, R.W.

    1985-01-01

    These lectures aim to present and explain in general terms some of the characteristics of microprocessor chips and associated components. They show how systems are synthesized from the basic integrated circuit building blocks which are currently available; processor, memory, input-output (I/0) devices, etc. (orig./HSI)

  3. Microprocessor Controlled Capacitor Bank Switching System for ...

    African Journals Online (AJOL)

    In this work, analysis and development of a microprocessor controlled capacitor bank switching system for deployment in a smart distribution network was carried out. This system was implemented by the use of discreet components such as resistors, capacitors, transistor, diode, automatic voltage regulator, with the ...

  4. High-speed multiple-channel analog to digital data-acquisition module for microprocessor systems

    International Nuclear Information System (INIS)

    Ethridge, C.D.

    1977-01-01

    Intelligent data acquisition and instrumentation systems established by the incorporation of microprocessor technology require high-speed analog to digital conversion of multiple-channel input signals. Sophisticated data systems or subsystems are enabled by the microprocessor software flexibility to establish adaptive input data procedures. These adaptive procedures are enhanced by versatile interface circuitry which is software controlled

  5. Microprocessors control of fermentation process

    Energy Technology Data Exchange (ETDEWEB)

    Fawzy, A S; Hinton, O R

    1980-01-01

    This paper presents three schemes for the solution of the optimal control of fermentation process. It also shows the advantages of using microprocessors in controlling and monitoring this process. A linear model of the system is considered. An optimal feedback controller is determined which maintains the states (substrate and organisms concentration) at desired values when the system is subjected to disturbances in the influent substrate and organisms concentration. Simulation results are presented for the three cases.

  6. The HXR80M-balloon experiment: a microprocessor-controlled transatlantic payload

    International Nuclear Information System (INIS)

    Ubertini, P.; Bazzano, A.; Boccaccini, L.

    1980-01-01

    Following the results obtained from the succesful transatlantic flight launched during the summer 1976 from the CNR Milo Base, Sicily, the Laboratorio di Astrofisica Spaziale has started a new program in the hard X-ray astronomy field. It basically consists in the development of high resolution large area Multiwire Proportional Chambers to be employed in long duration balloon flights to study and monitor galactic and extragalactic sources. This note will describe the flight configuration and performances of the HXR80M payload. The experiment is expected to fly during July 1980 from the Milo Base in the framework of the CNR experimental balloon campaign. The note will analyze the main characteristics of the detectors employed, of the data handling electronics and in particular of the hardware and the software of the on-board microprocessor controlled multichannel analyzer. In fact the limitation due to the low bit rate HF link (1.2kbit/s) and the long flight duration (about one week) make imperative the use of an on-board microprocessor system to handle and select in real time the scientific data and to control the housekeeping and the telecommand systems

  7. Microprocessor protection devices: The present and the future

    Directory of Open Access Journals (Sweden)

    Gurevich Vladimir

    2008-01-01

    Full Text Available Paper presents the analysis of the basic constructive disadvantages of the present day microprocessor-based protective devices (MBR and offers the basic principles for creating a new MBR that can be used in newly constructed devices.

  8. The Microprocessor controls the activity of mammalian retrotransposons

    DEFF Research Database (Denmark)

    Heras, Sara R.; Macias, Sara; Plass, Mireya

    2013-01-01

    RNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions...

  9. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    Science.gov (United States)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  10. SEU simulation and testing of resistor-hardened D-latches in the SA3300 microprocessor

    International Nuclear Information System (INIS)

    Sexton, F.W.; Corbett, W.T.; Treece, R.K.; Hass, K.J.; Axness, C.L.; Hash, G.L.; Shaneyfelt, M.R.; Wunsch, T.F.; Hughes, K.L.

    1991-01-01

    In this paper the SEU tolerance of the SA3300 microprocessor with feedback resistors is presented and compared to the SA3300 without feedback resistors and to the commercial version (NS32016). Upset threshold at room temperature increased from 23 MeV-cm 2 /mg and 180 MeV-cm 2 /mg with feedback resistors of 50 kΩ and 160 kΩ, respectively. The performance goal of 10 MHz over the full temperature range of -55 degrees C to +125 degrees C is exceeded for feedback resistors of 160 kΩ and less. Error rate calculations for this design predict that the error rate is less than once every 100 years when 50 kΩ feedback resistors are used in the D-latch design. Analysis of the SEU response using a lumped-parameter circuit simulator imply a charge collection depth of 4.5 μm. This is much deeper than the authors would expect for prompt collection in the epi and funnel regions and has been explained in terms of diffusion current in the heavily doped substrate

  11. Microprocessor-controlled portable neutron spectrometer

    International Nuclear Information System (INIS)

    Hunt, G.F.; Kaifer, R.C.; Slaughter, D.R.; Strout, R.E. II; Rueppel, D.W.

    1979-01-01

    A neutron spectrometer that acquires and unfolds data in the field has been developed for use in the energy range from 1 to 20 MeV. The system includes an NE213 organic scintillation detector, automatic gain stabilization, automatically stabilized pulseshape discrimination, an LSl-11 microprocessor for control and data reduction, and a multichannel analyzer for data acquisition. The system, with the exception of the multichannel analyzer, is mounted in a suitcase 47 by 66 by 23.5 cm. The mass is 23.5 kg

  12. Microprocessor-based integrated LMFBR core surveillance

    International Nuclear Information System (INIS)

    Gmeiner, L.

    1984-06-01

    This report results from a joint study of KfK and INTERATOM. The aim of this study is to explore the advantages of microprocessors and microelectronics for a more sophisticated core surveillance, which is based on the integration of separate surveillance techniques. Due to new developments in microelectronics and related software an approach to LMFBR core surveillance can be conceived that combines a number of measurements into a more intelligent decision-making data processing system. The following techniques are considered to contribute essentially to an integrated core surveillance system: - subassembly state and thermal hydraulics performance monitoring, - temperature noise analysis, - acoustic core surveillance, - failure characterization and failure prediction based on DND- and cover gas signals, and - flux tilting techniques. Starting from a description of these techniques it is shown that by combination and correlation of these individual techniques a higher degree of cost-effectiveness, reliability and accuracy can be achieved. (orig./GL) [de

  13. Automatic local beam steering systems for NSLS x-ray storage ring: Design and implementation

    International Nuclear Information System (INIS)

    Singh, O.V.; Nawrocky, R.; Flannigan, J.

    1991-01-01

    Recently, two local automatic steering systems, controlled by microprocessors, have been installed and commissioned in the NSLS X- Ray storage ring. In each system, the position of the electron beam is stabilized at two locations by four independent servo systems. This paper describes three aspects of the local feedback program: design; commissioning; and limitation. The system design is explained by identifying major elements such as beam position detectors, signal processors, compensation amplifiers, ratio amplifiers, trim equalizers and microprocessor feedback controllers. System commissioning involves steps such as matching trim compensation, determination of local orbit bumps, measurement of open loop responses and design of servo circuits. Several limitations of performance are also discussed. 7 refs., 2 figs

  14. Hardware math for the 6502 microprocessor

    Science.gov (United States)

    Kissel, R.; Currie, J.

    1985-01-01

    A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

  15. The specifications a multichannel analyser using microprocessor

    International Nuclear Information System (INIS)

    Pontes, E.W.

    The idea of a small nuclear data acquisition system (stand - alone CAMAC system) used for spectroscopy, is presented. The system is composed by an autonomous controller with microprocessor with one fast programable unit (1-2 μsec/CAMAC instructions) and with modulus of general functions as: CAMAC memory, interface for video, interface for analogy to digital converter and temporizing. (E.G.) [pt

  16. Some software algorithms for microprocessor ratemeters

    International Nuclear Information System (INIS)

    Savic, Z.

    1991-01-01

    After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.)

  17. Some software algorithms for microprocessor ratemeters

    Energy Technology Data Exchange (ETDEWEB)

    Savic, Z. (Military Technical Inst., Belgrade (Yugoslavia))

    1991-03-15

    After a review of the basic theoretical ratemeter problem and a general discussion of microprocessor ratemeters, a short insight into their hardware organization is given. Three software algorithms are described: the old ones the quasi-exponential and floating mean algorithm, and a new weighted moving average algorithm. The equations for statistical characterization of the new algorithm are given and an intercomparison is made. It is concluded that the new algorithm has statistical advantages over the old ones. (orig.).

  18. A low cost, microprocessor-based battery charge controller

    Energy Technology Data Exchange (ETDEWEB)

    Pulfrey, D L; Hacker, J [Pulfrey Solar Inc., Vancouver, BC (Canada)

    1990-01-01

    This report describes the design, construction, testing, and evaluation of a microprocessor-based battery charge controller that uses charge integration as the method of battery state-of-charge estimation. The controller is intended for use in medium-size (100-1000W) photovoltaic systems that employ 12V lead-acid batteries for charge storage. The controller regulates the charge flow to the battery and operates in three, automatically-determined modes, namely: charge, equalize, and float. The prototype controller is modular in nature and can handle charge/discharge currents of magnitude up to 80A, depending on the number of circuit boards employed. Evaluation tests and field trials have shown the controller to be very accurate and reliable. Based on the cost of the prototype, it appears that an original equipment manufacturer's selling price of $400 for a 40A (500W) unit may be realistic. 18 figs., 2 tabs.

  19. Nonconformance in electromechanical output relays of microprocessor-based protection devices under actual operating conditions

    OpenAIRE

    Gurevich, Vladimir

    2006-01-01

    Microprocessor-based protection relays are gradually driving out traditional electromechanical and even electronic protection devices from virtually all fields of power and electrical engineering. In this paper, one of many problems of microprocessor-based relays is discussed: nonconformance of miniature electromechanical output relays under actual operation conditions: switching inductive loads (with tripping CB coils or lockout relay coils) at 220 VDC, and "dry" switching of some control ci...

  20. Application of a 16-bit microprocessor to the digital control of machine tools

    International Nuclear Information System (INIS)

    Issaly, Alain

    1979-01-01

    After an overview of machine tools (various types, definition standardization, associated technologies for motors and position sensors), this research thesis describes the principles of computer-based digital control: classification of machine tool command systems, machining programming, programming languages, dialog function, interpolation function, servo-control function, tool compensation function. The author reports the application of a 16-bit microprocessor to the computer-based digital control of a machine tool: feasibility, selection of microprocessor, hardware presentation, software development and description, machining mode, translation-loading mode

  1. Microprocessor, Setx, Xrn2, and Rrp6 Co-operate to Induce Premature Termination of Transcription by RNAPII

    NARCIS (Netherlands)

    Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

    2012-01-01

    Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 30-50 exoribonuclease,

  2. Microprocessor-based accelerating power level detector

    Energy Technology Data Exchange (ETDEWEB)

    Nagpal, M.; Zarecki, W.; Albrecht, J.C.

    1994-01-01

    An accelerating power level detector was built using state-of-the-art microprocessor technology at Powertech Labs Inc. The detector will monitor the real power flowing in two 300 kV transmission lines out of Kemano Hydroelectric Generating Station and will detect any sudden loss of load due to a fault on either line under certain pre-selected power flow conditions. This paper discusses the criteria of operation for the detector and its implementation details, including digital processing, hardware, and software.

  3. Microprocessor-controlled, programmable ramp voltage generator

    International Nuclear Information System (INIS)

    Hopwood, J.

    1978-11-01

    A special-purpose voltage generator has been developed for driving the quadrupole mass filter of a residual gas analyzer. The generator is microprocessor-controlled with desired ramping parameters programmed by setting front-panel digital thumb switches. The start voltage, stop voltage, and time of each excursion are selectable. A maximum of five start-stop levels may be pre-selected for each program. The ramp voltage is 0 to 10 volts with sweep times from 0.1 to 999.99 seconds

  4. Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

    Directory of Open Access Journals (Sweden)

    Archana Shenoy

    2009-09-01

    Full Text Available The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript.To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8.We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

  5. Microprocessor controlled pulse charge and testing of batteries

    International Nuclear Information System (INIS)

    Kerezov, A.; Gishin, S.; Ivanov, Ratcho; Savov, S.

    2002-01-01

    The principle of the developed new method for pulse charge of batteries with microprocessor control of the electrochemical processes is the use of current pulses with microprocessor control of the period and the amplitude according to the dynamically changing state of the electrochemical system. In order to realize the method described above a programmable current source was developed. It is connected with a Personal Computer via RS232 standard serial interface in order to control the electrochemical processes. The parameters to be set, the graphical presentation of the pulse current and tension, the used quantity of electricity and electrical energy for every pulse and for the process as a hole are shown on the PC display. In order to test dry-charged and wet-charged batteries a specialized current generator was developed. It is connected also with a Personal Computer via R5232 standard serial interface in order to con-trol the testing of the starting capability of the batteries according to the requirements of the Bulgarian State Standard Ell 60095-1. (Author)

  6. Microprocessor-controlled wide-range streak camera

    Science.gov (United States)

    Lewis, Amy E.; Hollabaugh, Craig

    2006-08-01

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

  7. Microprocessor-controlled, wide-range streak camera

    International Nuclear Information System (INIS)

    Amy E. Lewis; Craig Hollabaugh

    2006-01-01

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized

  8. Trust versus confidence: Microprocessors and personnel monitoring

    International Nuclear Information System (INIS)

    Chiaro, P.J. Jr.

    1993-01-01

    Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to ''false alarms''. This is especially true when monitoring for alpha contamination. What is a ''false alarm''? Do these machines and their algorithms that we put our trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

  9. Trust versus confidence: Microprocessors and personnel monitoring

    International Nuclear Information System (INIS)

    Chiaro, P.J. Jr.

    1994-01-01

    Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to ''false alarms''. This is especially true when monitoring for alpha contamination. What is a ''false alarm''? Do these machines and their algorithms that they put their trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

  10. Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

    Science.gov (United States)

    Darcy, Eric; Davies, Frank

    2009-01-01

    Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.

  11. Future microprocessor farms: Offline and online

    International Nuclear Information System (INIS)

    Areti, H.

    1990-01-01

    Microprocessor farms have been successfully employed in high energy physics for both offline analysis and online triggers. As the experiments continue to grow in size, so do the demands for processing power. The preliminary indications are that the large collider experiments will require at least a million VAX-11/780 equivalents of processing power for online trigger decisions and offline event reconstruction. This paper examines the current technology trends and projects the processing power that may be expected with the current farm architectures. 3 refs., 6 figs

  12. Stair ascent with an innovative microprocessor-controlled exoprosthetic knee joint.

    Science.gov (United States)

    Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

    2012-12-01

    Climbing stairs can pose a major challenge for above-knee amputees as a result of compromised motor performance and limitations to prosthetic design. A new, innovative microprocessor-controlled prosthetic knee joint, the Genium, incorporates a function that allows an above-knee amputee to climb stairs step over step. To execute this function, a number of different sensors and complex switching algorithms were integrated into the prosthetic knee joint. The function is intuitive for the user. A biomechanical study was conducted to assess objective gait measurements and calculate joint kinematics and kinetics as subjects ascended stairs. Results demonstrated that climbing stairs step over step is more biomechanically efficient for an amputee using the Genium prosthetic knee than the previously possible conventional method where the extended prosthesis is trailed as the amputee executes one or two steps at a time. There is a natural amount of stress on the residual musculoskeletal system, and it has been shown that the healthy contralateral side supports the movements of the amputated side. The mechanical power that the healthy contralateral knee joint needs to generate during the extension phase is also reduced. Similarly, there is near normal loading of the hip joint on the amputated side.

  13. Data acquisition and command system for use with a microprocessor-based control chassis

    International Nuclear Information System (INIS)

    Halbig, J.K.; Klosterbuer, S.F.; Martinez, V.A. Jr.

    1980-01-01

    The Pion Generation for Medical Irradiations (PIGMI) program at the Los Alamos Scientific Laboratory is developing the technology to build smaller, less expensive, and more reliable proton linear accelerators for medical applications, and has designed a powerful, simple, inexpensive, and reliable control and data acquisition system that is central to the program development. The system is a NOVA-3D minicomputer interfaced to several outlying microprocessor-based controllers, which accomplish control and data acquisition through data I/O chasis. The equipment interface chassis, which can issue binary commands, read binary data, issue analog commands, and read timed and untimed analog data is described

  14. Fuzzy Concurrent Object Oriented Expert System for Fault Diagnosis in 8085 Microprocessor Based System Board

    OpenAIRE

    Mr.D. V. Kodavade; Dr. Mrs.S.D.Apte

    2014-01-01

    With the acceptance of artificial intelligence paradigm, a number of successful artificial intelligence systems were created. Fault diagnosis in microprocessor based boards needs lot of empirical knowledge and expertise and is a true artificial intelligence problem. Research on fault diagnosis in microprocessor based system boards using new fuzzy-object oriented approach is presented in this paper. There are many uncertain situations observed during fault diagnosis. These uncertain situations...

  15. Failure analysis on false call probe pins of microprocessor test equipment

    Science.gov (United States)

    Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

    2017-09-01

    A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

  16. Development of a microprocessor controller for stand-alone photovoltaic power systems

    Science.gov (United States)

    Millner, A. R.; Kaufman, D. L.

    1984-01-01

    A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

  17. A microprocessor based exchange data collection and analysis terminal application to A.E.A. PABX

    International Nuclear Information System (INIS)

    Mohammed, F.A.; Ezzat, A.K.; Ayad, N.M.A.

    1978-01-01

    The traffic data acquisition and analysis comprises micro-processer based data collection, terminals (MBDCT) and a centralized computer. The MBDCT's can communicate with the computer through a data set system. Each (MBDCT) remote terminal is connected to about two hundreds subscriber lines. It scans the trunk lines to detect the on/off hook states and to calculate the call time and the called number. If the called subscriber is not from the 200 local lines, its status should be detected though the computer communication with the two terminals. The data collected by the terminal can be slightly analysed using the microprocessor programming capability. More-over short quality performance reports can be printed on a printer interfaced to the microprocessor. Also, data can be transmitted to the central computer for further data traffic investigation. The analysis outcome can be utilized for telephone line maintenance and reorganization. This report is concerned with the terminal details as applied to the A-E-A. PABX. It consists mainly of five external lines and about 300 internal lines

  18. Environmental qualification and functional issues for microprocessor-based reactor protection systems

    International Nuclear Information System (INIS)

    Korsah, K.; Kisner, R.; Wood, R.T.; Antonescu, C.

    1992-01-01

    Issues of obsolescence and lack of intrastructural support in (analog) spare parts, coupled with the potential benefits of digital systems, are driving the nuclear industry to retrofit analog instrumentation and control (I ampersand C) systems with digital and microprocessor-based systems. This movement away from analog can be expected to increase in advanced light-water reactors (ALWRs), which will make extensive use of fiber optic transmission, multiplexing techniques, and microprocessor-based technology. Although these technologies have several advantages and, in fact, have been in widespread use in the non-nuclear industry for several years, their application to safety-related systems in nuclear power plants raises key issues relating to the systems' environmental and functional reliability. For example, does the new hardware introduce additional system aging degradation mechanisms that could adversely impact the safety of the plant? Do the systems introduce the possibility of new and different malfunction scenarios or increase the probability of common-mode failures that could reduce the reliability of the safety system?. Are current environmental qualification standards adequate for microprocessor-based I ampersand C systems? Accordingly in 1991 the Nuclear Regulatory Commission (NRC) initiated the qualification of advanced Instrumentation and Control Systems program at ORNL to investigate issues that may arise with the use of advanced digital I ampersand C in ALWRs. The results of our studies to date are summarized in this paper

  19. A microprocessor based monitoring system for a small nuclear reactor facility

    International Nuclear Information System (INIS)

    Miller, G.E.; DeKeyser, C.F.

    1980-01-01

    An inexpensive microprocessor based system has been designed and constructed for our 250 kilowatt TRIGA reactor facility. The system, which is beginning operational testing, can monitor on a continuous basis the status of up to 54 devices and maintain a record of events. These devices include fixed radiation monitors, pool water level trips, security alarms and an access control unit. In the latter case, the unit permits selection of different levels of access permission based on the time of day. The system can alert security and other personnel in the event of abnormalities. Because of the inclusion of this in the security system, special reliability and failure mode operation. The unit must also be simple to install, program and operate. (author)

  20. Total dose and dose rate radiation characterization of EPI-CMOS radiation hardened memory and microprocessor devices

    International Nuclear Information System (INIS)

    Gingerich, B.L.; Hermsen, J.M.; Lee, J.C.; Schroeder, J.E.

    1984-01-01

    The process, circuit discription, and total dose radiation characteristics are presented for two second generation hardened 4K EPI-CMOS RAMs and a first generation 80C85 microprocessor. Total dose radiation performance is presented to 10M rad-Si and effects of biasing and operating conditions are discussed. The dose rate sensitivity of the 4K RAMs is also presented along with single event upset (SEU) test data

  1. Distributed microprocessor automation network for synthesizing radiotracers used in positron emission tomography

    International Nuclear Information System (INIS)

    Russell, J.A.G.; Alexoff, D.L.; Wolf, A.P.

    1984-01-01

    This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. 20 refs. (DT)

  2. A measurement of cosmic-ray LET-spectra using a microprocessor supported microscope

    International Nuclear Information System (INIS)

    Beer, J.; Heinrich, W.

    1982-01-01

    A microprocessor supported semi-automatic system for measurements of nuclear tracks in plastic detectors is presented. It consists of a microscope and a stepping motor driven stage. A Motorola microprocessor MC 6800 controls the measurement. It accepts the co-ordinates of the stage as well as the position of the focus and computes cone length and dip angle from the three-dimensional co-ordinates. LET-spectra were measured from two cellulose nitrate foils of the Biostack III experiment flown with the Apollo-Soyus-Test-Project in 1975. One of these foils was shielded by 3 g/cm 2 and the other one by 15 g/cm 2 . The two spectra show no statistically significant decrease of intensity. (author)

  3. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Science.gov (United States)

    2010-01-01

    ... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17...: END-USER AND END-USE BASED § 744.17 Restrictions on certain exports and reexports of general purpose microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the...

  4. Technology transfer of military space microprocessor developments

    Science.gov (United States)

    Gorden, C.; King, D.; Byington, L.; Lanza, D.

    1999-01-01

    Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

  5. Microprocessor-controlled, wide-range streak camera

    Energy Technology Data Exchange (ETDEWEB)

    Amy E. Lewis, Craig Hollabaugh

    2006-09-01

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera’s user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

  6. A high resolution wire scanner beam profile monitor with a microprocessor data acquisition system

    International Nuclear Information System (INIS)

    Cutler, R.I.; Mohr, D.L.; Whittaker, J.K.; Yoder, N.R.

    1983-01-01

    A beam profile monitor has been constructed for the NBS-LANL Racetrack Microtron. The monitor consists of two perpendicular 30 μm diameter carbon wires that are driven through an electron beam by a pneumatic actuator. A long-lifetime, electroformed nickel bellows is used for the linear-motion vacuum feedthrough. Secondary emission current from the wires and a signal from a transducer measuring the position of the wires are simultaneously digitized by a microprocessor to yield beam current density profiles in two dimensions. The wire scanner is designed for use with both pulsed and cw beams

  7. Equipment calibration with a microprocessor connected to a time-sharing system

    International Nuclear Information System (INIS)

    Fontaine, G.; Guglielmi, L.; Jaeger, J.J.; Szafran, S.

    1981-01-01

    In H.E.P., it is common practice to test and calibrate equipment at different stages (design, construction checks, setting up and running periods) with a dedicated mini or micro-computer (such as CERN CAVIAR). An alternative solution has been developed in which such tasks are split between a microprocessor (Motorola 6800), and a host computer; this allows an easy and cheap multiplication of independant testing set-ups. The local processor is limited to CAMAC data acquisition, histogramming and simple processing, but its computing power is enhanced by a connection to a host time-sharing system via a MUMM multiplexor described in a separate paper. It is thus possible to perform sophisticated computations (fits etc...) and to use the host disk space to store calibration results for later use. In spite of the use of assembly language, a software structure has been devised to ease the constitution of an application program. This is achieved by the interplay of three levels of facilities: macro-instructions, library of subroutines, and Patchy controlled pieces of programs. A comprehensive collection of these is kept in the form of PAM files on the host computer. This system has been used to test calorimeter modules for the UA 1 experiment. (orig.)

  8. Microprocessor-based, on-line decision aid for resolving conflicting nuclear reactor instrumentation

    International Nuclear Information System (INIS)

    Alesso, H.P.

    1981-01-01

    We describe one design for a microprocessor-based, on-line decision aid for identifying and resolving false, conflicting, or misleading instrument indications resulting from certain systems interactions for a pressurized water reactor. The system processes sensor signals from groups of instruments that track together under nominal transient and certain accident conditions, and alarms when they do not track together. We examine multiple-casualty systems interaction and formulate a trial grouping of variables that track together under specified conditions. A two-of-three type redundancy check of key variables provides alarm and indication of conflicting information when one signal suddenly tracks in opposition due to multiple casualty, instrument failure, and/or locally abnormal conditions. Since a vote count of two of three variables in conflict as inconclusive evidence, the system is not designed to provide tripping or corrective action, but improves the operator/instrument interface by providing additional and partially digested information

  9. Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

    Science.gov (United States)

    Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

    1984-09-01

    This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

  10. Trust versus confidence: Microprocessors and personnel monitoring

    International Nuclear Information System (INIS)

    Chiaro, P.J. Jr.

    1993-01-01

    Due to recent technological advances, substantial improvements have been made in personnel contamination monitoring. In all likelihood, these advances will close out the days of manually frisking personnel for radioactive contamination. Unfortunately, as microprocessor-based monitors become more widely used, not only at commercial power reactors but also at government facilities, questions concerning their trustworthiness arise. Algorithms make decisions that were previously made by technicians. Trust is placed not in technicians but in machines. In doing this it is assumed that the machine never misses. Inevitably, this trust drops, due largely to open-quotes false alarms.close quotes This is especially true when monitoring for alpha contamination. What is a open-quotes false alarm?close quotes Do these machines and their algorithms that we put our trust in make mistakes? An analysis was performed on half-body and hand-and-foot monitors at Oak Ridge National Laboratory (ORNL) in order to justify the suggested confidence level used for alarm point determination. Sources used in this analysis had activities approximating ORNL's contamination limits

  11. Tests of microprocessor-based relay protection devices: Problems and solutions

    Directory of Open Access Journals (Sweden)

    Gurevich Vladimir

    2009-01-01

    Full Text Available Usually, the operational condition of relay protection devices is checked with specific settings used for the relay operation in a certain network point. In the author's opinion in order to verify the proper operation of complex multifunctional microprocessor-based protection devices (MPD at their inspection, start-up after repairs or during periodic tests there is no need to use the actual settings at which the relay is to be operated in a certain network's point. It should be tested for proper operation at several of its most critical preset characteristic points as well as in several preset characteristics constituting its most complicated (combined operation modes, including the dynamic operation modes with preset transition processes specific for standard power networks (not necessarily for a specific point. The proposed set of actions for the unification of software platforms of the modern, microprocessor-based relay protection test systems will enable examination of modern MPD in an absolutely new way. .

  12. Dual photon absorptiometer utilizing a HpGe detector and microprocessor controller

    International Nuclear Information System (INIS)

    Ellis, K.J.; Vartsky, D.; Pearlstein, T.B.; Alberi, J.L.; Cohn, S.H.

    1978-01-01

    The analysis of bone mineral content (BMC) using a single energy-photon beam assumes that there are only two materials present, bone mineral and a uniform soft tissue component. Uncertainty in the value of BMC increases with different adipose tissue components in the transmitted beam. These errors, however, are reduced by the dual energy technique. Also, extension to additional energies further identifies the separate constituents of the soft tissue component. A multi-energy bone scanning apparatus with data acquisition and analysis capability sufficient to perform multi-energy analysis of bone mineral content was designed and developed. The present work reports on the development of device operated in the dual energy mode. The high purity germanium (HpGe) detector is an integral component of the scanner. Errors in BMC due to multiple small angle scatters are reduced due to the excellent energy resolution of the detector (530 eV at 60 keV). Also, the need to filter the source or additional collimation on the detector is eliminated. A new dual source holder was designed using 200 mCi 125 I and 100 mCi 241 Am. The active areas of the two source capsules are aligned on a common axis. The congruence of the dual source was verified by measuring the collimator response function. This new holder design insures that the same tissue mass simultaneously attenuates both sources. The controller portion of the microprocessor allows for variation in total scan length, step size, and counting time per step. These options allow for multiple measurements without changes in the detector, source, or collimator. The system has been successfully used to determine the BMC content of different bones

  13. GPS/MEMS IMU/Microprocessor Board for Navigation

    Science.gov (United States)

    Gender, Thomas K.; Chow, James; Ott, William E.

    2009-01-01

    A miniaturized instrumentation package comprising a (1) Global Positioning System (GPS) receiver, (2) an inertial measurement unit (IMU) consisting largely of surface-micromachined sensors of the microelectromechanical systems (MEMS) type, and (3) a microprocessor, all residing on a single circuit board, is part of the navigation system of a compact robotic spacecraft intended to be released from a larger spacecraft [e.g., the International Space Station (ISS)] for exterior visual inspection of the larger spacecraft. Variants of the package may also be useful in terrestrial collision-detection and -avoidance applications. The navigation solution obtained by integrating the IMU outputs is fed back to a correlator in the GPS receiver to aid in tracking GPS signals. The raw GPS and IMU data are blended in a Kalman filter to obtain an optimal navigation solution, which can be supplemented by range and velocity data obtained by use of (l) a stereoscopic pair of electronic cameras aboard the robotic spacecraft and/or (2) a laser dynamic range imager aboard the ISS. The novelty of the package lies mostly in those aspects of the design of the MEMS IMU that pertain to controlling mechanical resonances and stabilizing scale factors and biases.

  14. The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

    CERN Document Server

    Becam, C; Delanghe, J; Fest, H M; Lecoq, J; Martin, H; Mencik, M; MerkeI, B; Meyer, J M; Perrin, M; Plothow, H; Rampazzo, J P; Schittly, A

    1981-01-01

    The bit slice micro-processor GESPRO is a CAMAC module plugged into a standard Elliot system crate via which it communicates as a slave with its host computer. It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine with multi-mode memory addressing capacity of 64K words. The micro-processor structure uses 5 buses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2K (RAM) words of 48 bits each. A special hardwired module allows floating point, as well as integer, multiplication of 24*24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: (a) online data reduction, i.e. to read DURANDAL, process the information resulting in accepting or rejecting the event; (b) readout and analysis of the accepted data; (c) preprocess the data. The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hard...

  15. Microprocessor-based integrated LMFBR core surveillance. Pt. 2

    International Nuclear Information System (INIS)

    Elies, V.

    1985-12-01

    This report is the result of the KfK part of a joint study of KfK and INTERATOM. The aim of this study is to explore the advantages of microprocessors and microelectronics for a more sophisticated core surveillance, which is based on the integration of separate surveillance techniques. After a description of the experimental results gained with the different surveillance techniques so far, it is shown which kinds of correlation can be done using the evaluation results obtained from the single surveillance systems. The main part of this report contains the systems analysis of a microcomputer-based system integrating different surveillance methods. After an analysis of the hardware requirements a hardware structure for the integrated system is proposed. The software structure is then described for the subsystem performing the different surveillance algorithms as well as for the system which does the correlation thus deriving additional information from the single results. (orig.) [de

  16. Microprocessor system for data acquisition and processing for the Flora device

    International Nuclear Information System (INIS)

    Klimov, V.M.

    1986-01-01

    ''VEhFORMIKA'' microprocessor system for data collection and processing when conducting experiments at the ''Flora'' device is described, its application is grounded. The complex allows one to conduct investigations using multichannel methods and exercise the device electrophysical control

  17. Advances in Sensors-Centric Microprocessors and System-on-Chip

    Directory of Open Access Journals (Sweden)

    Juan A. Gómez-Pulido

    2012-04-01

    Full Text Available Sensors-based systems are nowadays an extended technology for many markets due to their great potential in the collection of data from the environment and the processing of such data for different purposes. A typical example is the wireless sensor devices, where the outer temperature, humidity, luminosity and many other parameters can be acquired, measured and processed in order to build useful and fascinating applications that contribute to human welfare. In this scenario, the processing architectures of the sensors-based systems play a very important role. The requirements that are necessary for many such applications (real-time processing, low-power consumption, reduced size, reliability, security and many others means that research on advanced architectures of Microprocessors and System-on-Chips (SoC is needed to design and implement a successful product. In this sense, there are many challenges and open questions in this area that need to be addressed. [...

  18. Design of a family of integrated parallel co-processors for images processing

    International Nuclear Information System (INIS)

    Court, Thierry

    1991-01-01

    The design of parallel image processing Systems joining in a same architecture, sophisticated microprocessors and specialised operators is a difficult task, because of the various problems to be taken into account. The current study identifies a certain way of realizing and interfacing such dedicated operators to a central unit with microprocessor type. The two guide lines of this work are the search for polyvalent specialized and re-configurated operators as well as their connections to a System bus, and not to specialized video buses. This research work proposes a certain architecture of circuits dedicated to image processing and two realization proposals of them. One of them was be realized in this study by using silicon compiler tools. This work belongs to a more important project, whose aim is the development of an industrial image processing System, high performing, modular, based on the parallelization, in MIMD structures, of an elementary, autonomous image processing unit integrating a microprocessor equipped with a parallel coprocessor suited to image processing. (author) [fr

  19. Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

    Science.gov (United States)

    Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

    2018-03-01

    We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

  20. CAMAC multipurpose microprocessor controller

    International Nuclear Information System (INIS)

    Belyakova, M.P.; Nemesh, T.; Buj Zoan Chong.

    1978-01-01

    The use of CAMAC controllers in an autonomous system of data acquisition and measurement is considered. The system consists of a control intelligence controller, memory modules, and user modules in the CAMAC standard. The controller and all the modules have an output into the highway and this permits to exchange data among them without using special external cables. To increase the servicing rate, an auxiliary controller which has direct access to memory and controls the user modules, is additionally connected to the data acquisition and measurement system. In this case, the intelligence controller is passive. The system of data acquisition can be realized in the form of a multiple system with branch usage. The controller module width is three units, and the controller incorporates the Intel-8080-type microprocessor and the following interfaces: of CAMAC highways, of interruption, of memory bootstrap, and of data sequence channel

  1. Small Private Key PKS on an Embedded Microprocessor

    OpenAIRE

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-01-01

    Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor...

  2. Sectional microprocessor based microcomputer and its application to express analysis using interactive language

    International Nuclear Information System (INIS)

    Lang, I.; Leveleki, L.; Salai, M.; Turani, D.

    1984-01-01

    Sectional microprocessor TPA-L/128H based mini-computer being a part of the TPA-8 computer family is developed. A substantial increase of the computer operation rate is attained at the expense of microprogram monitoring. The central processor is constructed on the base of the AM2900 sectional microprocessor elements. The TPA-L/128H computer is program compatible with TPA-8 computer, perfectly equipped with software: high level languages as well as OS/L, COS/H, RTS/H, PAL/128, WPS, TEASYS-8 and IL 128 ensuring statistical data processing, physical experiments automation and interactive experimental data processing. The real time basis problems and CAMAC devices monitoring are efficiently solved

  3. A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

    Directory of Open Access Journals (Sweden)

    Diego González

    2012-09-01

    Full Text Available This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA and NIOS II microprocessor applying a C to Hardware (C2H acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

  4. Advanced Transport Operating System (ATOPS) color displays software description microprocessor system

    Science.gov (United States)

    Slominski, Christopher J.; Plyler, Valerie E.; Dickson, Richard W.

    1992-01-01

    This document describes the software created for the Sperry Microprocessor Color Display System used for the Advanced Transport Operating Systems (ATOPS) project on the Transport Systems Research Vehicle (TSRV). The software delivery known as the 'baseline display system', is the one described in this document. Throughout this publication, module descriptions are presented in a standardized format which contains module purpose, calling sequence, detailed description, and global references. The global reference section includes procedures and common variables referenced by a particular module. The system described supports the Research Flight Deck (RFD) of the TSRV. The RFD contains eight cathode ray tubes (CRTs) which depict a Primary Flight Display, Navigation Display, System Warning Display, Takeoff Performance Monitoring System Display, and Engine Display.

  5. Front-end data processing using the bit-sliced microprocessor

    International Nuclear Information System (INIS)

    Machen, D.R.

    1979-01-01

    A state-of-the-art computing device, based upon the high-speed bit-sliced microprocessor, was developed into hardware for front-end data processing in both control and experiment applications at the Los Alamos Scientific Laboratory. The CAMAC Instrumentation Standard provides the framework for the high-speed hardware, allowing data acquisition and processing to take place at the data source in a CAMAC crate. 5 figures

  6. Overview of real-time operating systems on microprocessor platforms

    International Nuclear Information System (INIS)

    Luong, T.T.

    1994-01-01

    This paper attempts to overview the real-time operating systems on microprocessor platforms in the field of experimental physics facility controls. The key issues regarding operating systems as well as standards and development environment are discussed. As an illustration, some current industrial products are indicated. Also, real-time systems operating in some institutes of the EPS/EPCS inter divisional group are reviewed. (author). 3 refs., 4 figs

  7. New Design Concept for Universal CCD Controller

    Directory of Open Access Journals (Sweden)

    Wonyong Han

    1994-06-01

    Full Text Available Currently, the CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However according to the recent technical advances, new large format CCDs are rapidly developed which have better performances with higher quantum efficiency and sensitivity. In many cases, some microprocessors have been adopted to deal with necessary digital logic for a CCD imaging system. This could often lack the flexibility of a system for a user to upgrade with new devices, especially of it is a commercial product. A new design concept has been explored which could provide the opportunity to deal with any format of devices from ant manufactures effectively for astronomical purposes. Recently available PLD (Programmable Logic Devices technology makes it possible to develop such digital circuit design, which can be integrated into a single component, instead of using microprocessors. The design concept could dramatically increase the efficiency and flexibility of a CCD imaging system, particularly when new or large format devices are available and to upgrade the performance of a system. Some variable system control parameters can be selected by a user with a wider range of choice. The software can support such functional requirements very conveniently. This approach can be applied not only to astronomical purpose, but also to some related fields, such as remote sensing and industrial applications.

  8. Contribution to the automatic command in robotics - Application to the command by microprocessors of the articulated systems

    International Nuclear Information System (INIS)

    Al Mouhamed, Mayez

    1982-01-01

    The first part of the present paper deals with the main methods of changing the coordinates for a general articulated system. After a definition of the coordinates changing, we propose a coordination system designed for easy programming of the movements. Its characteristic is to permit the action anywhere on the manipulated object. The second part deals with the force regulation problem. For this purpose we have developed a general force sensor. The informations delivered by the sensor are used by force regulators which are intended for the automatic assembly of subsystems. In the third part the dynamic problem of the articulated systems is exposed. We present a new method which allows to determine dynamic parameters from appropriate motions of the robot. These parameters are then used to implement the dynamic control. Several applications, using the powerful microprocessor INTEL 8086 and its arithmetic coprocessor 8087, are presented, in order to demonstrate the performances gained. (author) [fr

  9. Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs

    Directory of Open Access Journals (Sweden)

    Victoria A. Church

    2017-09-01

    Full Text Available The cellular abundance of mature microRNAs (miRNAs is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor’s differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb. When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association.

  10. A microprocessor-based power control data acquisition system

    International Nuclear Information System (INIS)

    Greenberg, S.

    1982-10-01

    The project reported deals with one of the aspects of power plant control and management. In order to perform optimal distribution of power and load switching, one has to solve a specific optimization problem. In order to solve this problem one needs to collect current and power expenditure data from a large number of channels and have them processed. This particular procedure is defined as data acquisition and it constitutes the main topic of this project. A microprocessor-based data acquisition system for power management is investigated and developed. The current and power data of about 100 analog channels are sampled and collected in real-time. These data are subsequently processed to calculate the power factor (cos phi) for each channel and the maximum demand. The data is processed by an AMD 9511 Arithmetic Processing Unit and the whole system is controlled by an Intel 8080A CPU. All this information is then transfered to a universal computer through a synchronized communication channel. The optimization computations would be performed by the high level computer. Different ways of performing the search of data over a large number of channels have been investigated. A particular solution to overcome the gain and offset drift of the A/D converter, using software, has been proposed. The 8080A supervises the collection and routing of data in real time, while the 9511 performs calculation, using these data. (Author)

  11. Digital Fractional Order Controllers Realized by PIC Microprocessor: Experimental Results

    OpenAIRE

    Petras, I.; Grega, S.; Dorcak, L.

    2003-01-01

    This paper deals with the fractional-order controllers and their possible hardware realization based on PIC microprocessor and numerical algorithm coded in PIC Basic. The mathematical description of the digital fractional -order controllers and approximation in the discrete domain are presented. An example of realization of the particular case of digital fractional-order PID controller is shown and described.

  12. Applications of microprocessors in upgrading of accelerator controls

    International Nuclear Information System (INIS)

    Mallory, K.B.

    1977-03-01

    Experience at SLAC demonstrates that the criteria for selection and use of microprocessors in modifying an existing control system may differ from the criteria that apply during installation of the control system of a new accelerator. Considerations such as cost of individual projects, progressive installation without disruption of operations and training of on-board personnel can outweigh ''obvious'' goals such as standardization of hardware, uniformity of software, or even a rigid specification of link protocols with the main computer system

  13. The design and performance of the parallel multiprocessor nuclear physics data acquisition system, DAPHNE

    International Nuclear Information System (INIS)

    Welch, L.C.; Moog, T.H.; Daly, R.T.; Videbaek, F.

    1987-05-01

    The ever increasing complexity of nuclear physics experiments places severe demands on computerized data acquisition systems. A natural evolution of these systems, taking advantages of the independent nature of ''events,'' is to use identical parallel microcomputers in a front end to simultaneously analyze separate events. Such a system has been developed at Argonne to serve the needs of the experimental program of ATLAS, a new superconducting heavy-ion accelerator and other on-going research. Using microcomputers based on the National Semiconductor 32016 microprocessor housed in a Multibus I cage, CPU power equivalent to several VAXs is obtained at a fraction of the cost of one VAX. The front end interfacs to a VAX 11/750 on which an extensive user friendly command language based on DCL resides. The whole system, known as DAPHNE, also provides the means to reply data using the same command language. Design concepts, data structures, performance, and experience to data are discussed

  14. The use of microprocessors at TRIUMF in the control of radiation safety interlock systems

    International Nuclear Information System (INIS)

    King, L.

    1988-01-01

    At TRIUMF the cyclotron vault, all primary beam lines, and each experimental area has a dedicated control unit to manage the safety interlock control of the area lockup sequence, beam blocker drive and area access. Typically each area has 24 devices which are monitored to control 16 outputs. These control units (Area Safety Units) were first implemented through the use of relay logic. The relay logic was reliable but difficult to modify to incorporate changes to the areas. In 1979 it was decided to use microprocessors in the form of single board computers to control the Area Safety Units. The details of the hardware and software is discussed as well as the advantages of microprocessor control

  15. Reliability of microprocessor-based relay protection devices: Myths and reality

    Directory of Open Access Journals (Sweden)

    Gurevich Vladimir

    2009-01-01

    Full Text Available The article examines four basic theses about the ostensibly extremely high reliability of microprocessor-based relay protection (MP touted by supporters of MP. Through detailed analysis based on many references it is shown that the basis of these theses are widespread myths, and actually MP reliability is lower than the reliability of electromechanical and electronic protective relays on discrete components.

  16. Unified microprocessor CAMAC module for preliminary data processing

    International Nuclear Information System (INIS)

    Zaushitsin, V.L.; Kulik, O.V.; Repin, V.M.

    1984-01-01

    The UP-80 unified active module is described. It is made in the CAMAC standard on the base of the K580IK80 microprocessor allowing to increase the rate of large-volume experimental spectroscopic data processing by an order. Loading of 5 different programs for data processing is possible. Data from the operative storage with 1K capacity (8 bits) are recorded and read out trhough the CAMAC line (the regime of unit exchange is possible) or through the joint of the external line

  17. Integrating existing radiation monitors into a microprocessor-based display system

    International Nuclear Information System (INIS)

    Kalita, R, S.; Bartucci, C.M.; Mason, R.G.; Greaves, C.

    1992-01-01

    Plantwide digital radiation monitoring systems (RMSs) have been generally installed as part of the original design for newer nuclear reactors. For older plants, area and process radiation monitors were either analog or a combination of analog and digital but were not part of an integrated system design. At some plants, individual monitors have been replaced or modified, resulting in a rainbow of different monitors and vendors being represented at the plant. Usually at some point, consideration is given to replacing these monitors with a state-of-the-art RMS to improve overall reliability and achieve the benefits of sound human factors engineering. This can be a very costly project in terms of expenditures for engineering, equipment, construction, startup, and time. When human engineering deficiencies (HEDs) became an issue at Zion station, Commonwealth Edison elected to install a computer-based radiation monitoring display system (RMDS) that would interface existing raidation monitors. After reviewing the existing as-built RMS configuration and internal circuits of the various monitors, it was concluded that a microprocessor-based RMDS could be successfully designed and installed that would solve the HEDs and would tie the older analog channels into a system configuration. Although in many cases, internal modifications were made to existing RMS monitors, the RMDS upgrade allowed the existing RMS monitors to retain their original functionality and location

  18. Microprocessor control and data acquisition at the LLNL 100-MeV accelerator

    International Nuclear Information System (INIS)

    Mendonca, M.L.

    1981-01-01

    A distributed microprocessor control and data acquisition network has been designed for implementation on the Lawrence Livermore National Laboratory 100 MeV electron/positron accelerator (LINAC). The system has been designed to be as transparent to the user as possible by stressing responsiveness, reliability, and relevance of data presented to the user. Implementation of the network will take place in modular fashion in three stages, so as to minimize disruption of normal operations. The first elements to be installed will be the beam transport system controls, beam set-up time. Beam diagnostic equipment is now being position monitors, and accelerator operating status monitors. These units will reduce beam set-up time. Beam diagnostic equipment is now being designed that will be used in a second stage implementation. This stage will concentrate on determining beam parameters and allowing the user to optimize the beam for a given parameter. The final stage will be to install experimenter data acquisition equipment. The equipment will augment the presently existing data acquisition system. The completed network will allow a more efficient operation of the LINAC, resulting in reduced experiment costs, and more controllable beam parameters, both of which are major concerns of experimenters

  19. FPGA Design Methodologies Applicable to Nuclear Power Plants

    International Nuclear Information System (INIS)

    Kwong, Yongil; Jeong, Choongheui

    2013-01-01

    In order to solve the above problem, NPPs in some countries such as the US, Canada and Japan have already applied FPGA-based equipment which has advantages as follows: It is easier to verify the performance because it needs only HDL code to configure logic circuits without other software, compared to microprocessor-based equipment, It is much cheaper than ASIC in a small quantity, Its logic circuits are re configurable, It has enough resources like logic blocks and memory blocks to implement I and C functions, Multiple functions can be implemented in a FPGA chip, It is stronger with respect to carboy security than microprocessor-based equipment because its configuration cannot be changed by external access, It is simple to replace it with new one when it is obsolete, Its power consumption is lower. However, FPGA-based equipment does not have only the merits. There are some issues on its application to NPPs. First of all, the experiences in applying it to NPPs are much less than to other industries, and international standards or guidelines are also very few. And there is the small number of FPGA platforms for I and C systems. Finally, the specific guidelines on FPGA design are required because the design has both hardware and software characteristics. In order to handle the above issues, KINS(Korea Institute of Nuclear Safety) built a test platform last year and have developed regulatory guidelines for FPGA-application in NPPs. I and C systems of NPPs have been increasingly using FPGA-based equipment as an alternative of microprocessor-based equipment which is not simple to be evaluated for safety due to its complexity. This paper explained the FPGA design flow and design guidelines. Those methodologies can be used as the guidelines on FPGA verification for safety of I and C systems

  20. Satisfying STEM Education Using the Arduino Microprocessor in C Programming

    Science.gov (United States)

    Hoffer, Brandyn M.

    There exists a need to promote better Science Technology Engineering and Math (STEM) education at the high school level. To satisfy this need a series of hands-on laboratory assignments were created to be accompanied by 2 educational trainers that contain various electronic components. This project provides an interdisciplinary, hands-on approach to teaching C programming that meets several standards defined by the Tennessee Board of Education. Together the trainers and lab assignments also introduce key concepts in math and science while allowing students hands-on experience with various electronic components. This will allow students to mimic real world applications of using the C programming language while exposing them to technology not currently introduced in many high school classrooms. The developed project is targeted at high school students performing at or above the junior level and uses the Arduino Mega open-source Microprocessor and software as the primary control unit.

  1. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2011-01-01

    This Fourth Revised Edition of Computer Organization and Design includes a complete set of updated and new exercises, along with improvements and changes suggested by instructors and students. Focusing on the revolutionary change taking place in industry today--the switch from uniprocessor to multicore microprocessors--this classic textbook has a modern and up-to-date focus on parallelism in all its forms. Examples highlighting multicore and GPU processor designs are supported with performance and benchmarking data. As with previous editions, a MIPS processor is the core used to pres

  2. Microprocessors & their operating systems a comprehensive guide to 8, 16 & 32 bit hardware, assembly language & computer architecture

    CERN Document Server

    Holland, R C

    1989-01-01

    Provides a comprehensive guide to all of the major microprocessor families (8, 16 and 32 bit). The hardware aspects and software implications are described, giving the reader an overall understanding of microcomputer architectures. The internal processor operation of each microprocessor device is presented, followed by descriptions of the instruction set and applications for the device. Software considerations are expanded with descriptions and examples of the main high level programming languages (BASIC, Pascal and C). The book also includes detailed descriptions of the three main operatin

  3. Tools for developing software for different types of microprocessors, to be used, in particular, for the acquisition and processing of nuclear data

    International Nuclear Information System (INIS)

    Maloeuvre, Michel.

    1982-04-01

    It is difficult to imagine the realization of a system with a microprocessor without the use of an adapted development system. As these systems are prohibitively expensive, it is difficult for a laboratory to acquire them. A computer, such as the Multi 20 is provided with programme generating tools and supervisors to put the computer's ressources at the microprocessor's disposal. An electronic crate assures interface functions with the computer, the emulation of the microprocessor and the loading of EROM and the live memory lank in order to execute the different units integrated into the crate, enables the crate to be used as a portable repair and maintenance outfit for the materials installed. In the first part of the text, we present the principles of the development tools showing how they are used to realize microprocessor equipment. In the second part, the software is optimized together with the choice of materials in order to define a low cost development system [fr

  4. The design, creation, and performance of the parallel multiprocessor nuclear physics data acquisition system, DAPHNE

    International Nuclear Information System (INIS)

    Welch, L.C.; Moog, T.H.; Daly, R.T.; Videbaek, F.

    1986-01-01

    The ever increasing complexity of nuclear physics experiments places severe demands on computerized data acquisition systems. A natural evolution of these system, taking advantage of the independent nature of ''events'', is to use identical parallel microcomputers in a front end to simultaneously analyze separate events. Such a system has been developed at Argonne to serve the needs of the experimental program of ATLAS, a new superconducting heavy-ion accelerator and other on-going research. Using microcomputers based on the National Semiconductor 32016 microprocessor housed in a Multibus I cage, multi-VAX cpu power is obtained at a fraction of the cost of one VAX. The front end interfaces to a VAX 750 on which an extensive user friendly command language based on DCL resides. The whole system, known as DAPHNE, also provides the means to replay data using the same command language. Design concepts, data structures, performance, and experience to data are discussed. 5 refs., 2 figs

  5. Performing Performance Design Anglonationally

    DEFF Research Database (Denmark)

    2016-01-01

    Video recording of pecha kucha style bricolage aural enactment of an international version of performance design......Video recording of pecha kucha style bricolage aural enactment of an international version of performance design...

  6. Microprocessor system for data acquisition processing and display for Auger electrons spectrometer

    International Nuclear Information System (INIS)

    Pawlowski, Z.; Cudny, W.; Hildebrandt, S.; Marzec, J.; Walentek, J.; Zaremba, K.

    1984-01-01

    Data acquisition system for Auger electron spectrometry is developed. The system is used for chemical and structural analysis of materials and consists of a cylindrical mirror analyzer being a measuring spectrometer device, CAMAC unit and control unit. The control unit comprises a microcomputer based on INTEL 8080 microprocessor and display

  7. Microprocessor based image processing system

    International Nuclear Information System (INIS)

    Mirza, M.I.; Siddiqui, M.N.; Rangoonwala, A.

    1987-01-01

    Rapid developments in the production of integrated circuits and introduction of sophisticated 8,16 and now 32 bit microprocessor based computers, have set new trends in computer applications. Nowadays the users by investing much less money can make optimal use of smaller systems by getting them custom-tailored according to their requirements. During the past decade there have been great advancements in the field of computer Graphics and consequently, 'Image Processing' has emerged as a separate independent field. Image Processing is being used in a number of disciplines. In the Medical Sciences, it is used to construct pseudo color images from computer aided tomography (CAT) or positron emission tomography (PET) scanners. Art, advertising and publishing people use pseudo colours in pursuit of more effective graphics. Structural engineers use Image Processing to examine weld X-rays to search for imperfections. Photographers use Image Processing for various enhancements which are difficult to achieve in a conventional dark room. (author)

  8. Different microprocessor controlled devices for ITU TRIGA Mark II reactor

    International Nuclear Information System (INIS)

    Can, B.; Omuz, S.; Uzun, S.; Apan, H.

    1990-01-01

    In this paper the design of a period meter and multichannel thermometer, which are controlled by a microprocessor, in order to be used at ITU TRIGA Mark-II Reactor is presented. The system works as a simple microcomputer, which includes a CPU, a EPROM, a RAM, a CTC, a PIO, a PIA a keyboard and displays, using the assembly language. The period meter can work either with pulse signal or with analog signal depending on demand of the user. The period is calculated by software and its range is -99,9 sec, to +2.1 sec. When the period drops +3 sec, the system gives alarm illuminating a LED. The multichannel thermometer has eight temperature channels. Temperature channels can manually or automatically be selected. The channel selection time can be adjusted. The thermometer gives alarm illuminating a LED, when the temperature rises to 600 C. Temperature data is stored in the RAM and is shown on a display. This system provides us to use four spare thermocouples in the reactor. (orig.)

  9. Microprocessor system for temperature regulation and stabilization

    International Nuclear Information System (INIS)

    Nguyen Nhi Dien; Rodionov, K.G.

    1989-01-01

    Microprocessor based system for temperature regulation and stabilization of an operation external object is described. The system has the direct current amplifier working according to modulator-demodulator principle. The overal gain is 100, 1000, 2000. The maximum output signal is ±10 V. The power amplifier is a thyristor one and its line voltage is 220 V, 50 Hz. The output power is 0-2 kVA. The microcontroller has a remote display terminal. Data input is 8 and data output is one. Input and output voltage is ±(0-10) V. The preselection time for stabilization is within 1 s - 18 h. The program algorithm is given. 5 figs.; 1 tab

  10. Microprocessor-controlled time domain reflectometer for dynamic shock position measurements

    International Nuclear Information System (INIS)

    Virchow, C.F.; Conrad, G.E.; Holt, D.M.; Hodson, E.K.

    1980-01-01

    Time-domain reflectometry is used in a novel way to measure dynamically shock propagation in various media. The primary component in this measurement system is a digital time domain reflectometer, which uses local intelligence, a Motorola 6800 microprocessor, to make the unit adaptable and versatile. The recorder, its operating theory and its method of implementation are described and typical data are reviewed. Applications include nuclear explosion yield estimates and explosive energy flow measurements

  11. The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

    International Nuclear Information System (INIS)

    Becam, C.; Bernaudin, P.; Delanghe, J.; Mencik, M.; Merkel, B.; Plothow, H.; Fest, H.M.; Lecoq, J.; Martin, H.; Meyer, J.M.

    1981-01-01

    The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

  12. A CAMAC-resident microprocessor for the monitoring of polarimeter spin states

    International Nuclear Information System (INIS)

    Reid, D.; DuPlantis, D.; Yoder, N.; Dale, D.

    1992-01-01

    A CAMAC module for the reporting of polarimeter spin states is being developed using a resident microcontroller. The module will allow experimenters at the Indiana University Cyclotron Facility to monitor spin states and correlate spin information with other experimental data. The use of a microprocessor allows for adaptation of the module as new requirements ensue without change to the printed circuit board layout. (author)

  13. Microprocessor-based control for independently-phased RF linac cavities

    International Nuclear Information System (INIS)

    Dawson, J.W.

    1979-01-01

    A microprocessor based system has been built to control the RF amplifiers associated with independently phased linac cavities. The system has an 8080A at each amplifier station, together with associated ROM, RAM, I/O, etc. At a central NOVA 3 computer an additional 8080A system is incorporated in the interface to the NOVA I/O bus. The NOVA interface is connected by a bus of eighteen twisted pairs to each amplifier station, providing bilateral transmission between each station and the NOVA. The system architecture, bus protocol, and operating characteristics are described

  14. Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

    International Nuclear Information System (INIS)

    Korsah, K.

    2001-01-01

    This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I and C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I and C system upgrades of present-day nuclear power plants, as well as I and C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current, analog-based I and C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in

  15. How to design electrical systems with central control capability for industrial plants

    Energy Technology Data Exchange (ETDEWEB)

    Cigolini, S.; Galati, G.; Lionetto, P.F.; Stiz, M. (Siemens, Milan (Italy) Centro Elettrotecnico Sperimentale Italiano, Milan (Italy))

    1991-12-01

    The modern centralized control system, incorporating microprocessors, constitutes an extremely efficacious instrument for the management of an industrial plant's electrical system and provides the performance, reliability, flexibility and safety features required by today's technologically advanced plant processes. The use of intelligent centralized control systems, capable of autonomous operation and dialoguing with industrial plant electrical systems, simplifies the design of the overall plant. This paper reviews the main design criteria for the automated systems and gives examples of some suitable commercially available intelligent systems.

  16. Use of a microprocessor in a remote working level monitor

    International Nuclear Information System (INIS)

    Keefe, D.J.; McDowell, W.P.; Groer, P.G.

    1976-01-01

    The instrument described measures the short-lived 222 Rn-daughter concentrations and the Working Level (WL) in sealed ''hot chambers'' located in uranium mines. Radiation-induced pulses from two separate sensors are transmitted through 500 ft. cables to a microprocessor, which processes the pulses and controls the operation of the system. A read-only memory stores a fixed program which is used to calculate the desired concentrations. The results are printed as pCi/l (Rn-daughter concentrations) and WL

  17. Performance Aided Design

    DEFF Research Database (Denmark)

    Parigi, Dario

    2014-01-01

    paradigm where the increasing integration of parametric tools and performative analysis is changing the way we learn and design. The term Performance Aided Architectural Design (PAD) is proposed at the Master of Science of Architecture and Design at Aalborg University, with the aim of extending a tectonic...... tradition of architecture with computational tools, preparing the basis for the creation of the figure of a modern master builder, sitting at the boundary of the disciplines of architecture and engineering. Performance Aided Design focuses on the role of performative analysis, embedded tectonics......, and computational methods tools to trigger creativity and innovative understanding of relation between form material and a increasingly wide range of performances in architectural design. The ultimate goal is to pursue a design approach that aims at embracing rather than excluding the complexity implicit...

  18. Microprocessor-assisted calibration for a remote working level monitor

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

    1977-01-01

    A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

  19. Microprocessor-assisted calibration for a remote working level monitor

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Groer, P.G.; Witek, R.T.

    1976-01-01

    A method is described for calibrating a Remote Working Level Monitor, an instrument which measures Working Level and Rn-daughter concentrations in the atmosphere. The method makes use of a microprocessor to calculate beta efficiencies for RaB and RaC from the counts accumulated in the RaA, Ra(B + C) and RaC' channels of the instrument. Both the alpha spectroscopic and total-alpha methods are used to determine the Rn-daughter concentrations. These methods require the processor to solve systems of linear equations with several unknowns. No assumptions about Rn-daughter equilibrium are made

  20. Microprocessor-controlled inhalation system for repeated exposure of animals to aerosols

    International Nuclear Information System (INIS)

    Carpenter, R.L.; Barr, F.P.; Leydig, R.L.; Rajala, R.E.

    1979-01-01

    A microprocessor-controlled inhalation exposure system (MCIES) has been built to automate aerosol generation and sampling while controlling exposure time for animal toxicity studies. The system has a time resolution of 0.1 s and automatically sequences the exposure events from initiation to temination of the exposure. The operator is required to preset all airflows, read in a paper tape containing the time sequence of events, and initiate the automatic sequence by closing a switch

  1. A monitoring and protective system for mine hoists using a microprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Jianlin, Zhu

    1981-11-01

    In view of the existing problems of depth indicators and tachometers currently used in mine hoists, a measuring technique using a 'wire cable magnetic stripe' and a tentative proposal for a monitoring system with a microprocessor are described. The system can be used for measuring and indicating the depth, speed of the hoisting system, and can provide protection against overwinding, overspeeding and slack rope as well as monitoring the direction of hoisting. (In Chinese)

  2. Supply system with microprocessor control for electron gun

    International Nuclear Information System (INIS)

    Duplin, N.I.; Sergeev, N.N.

    1988-01-01

    Precision supply system for electron gun used in Auger-spectrometer is described. The supply system consists of control and high-voltage parts, made as separate units. Supply high-voltage unit includes system supply module, filament module to supply electron gun cathode and 6 high-volt modules to supply accelerating, modulating and three focusing electrodes of the gun. High-voltage modules have the following characteristics: U-(100-1000)V output voltage, 5x10 -5 U stability, 10 -5 xU pulsation amplitude, J-(0-5)A filament current change range at 10 -4 xJ stability. Control unit including microprocessor, timer and storage devices forms control voltage for all modules and regulates voltage and current of filament at electrodes

  3. Microprocessor Card for Cuban Series polarimeters Laserpol

    International Nuclear Information System (INIS)

    Arista Romeu, E.; Mora Mazorra, W.

    2012-01-01

    We present the design consists of a card based on a micro-processor 8-bit adds new software components and their basic living, which allow to deliver new services and expand the possibilities for use in other applications of the polarimeter LASERPOL series, as the polarimetric detection. Given the limitations of the original card it was necessary to introduce a series of changes that would allow to address new user requirements, and expand the possible applications of the instruments. This was done the expansion of the capacity of the EPROM and RAM memory, the decoder circuit was implemented memory map using a programmable integrated circuit, and introduced a real time clock with nonvolatile RAM, these features are exploited to the introduction of new features such as the realization of the polarimeter calibration by the user from a sample pattern or a calibration pattern used as a reference, and the incorporation of the time and date to the reports of measurements required industry for quality control processes. Card that is achieved along with the rest of the components is compatible with polarimeters LASERPOL 101M Series, 3M and LP4, pin to pin, which facilitates their incorporation into the polarimeters in operation in the industry 'in situ' replacement cards from previous models, allowing to extend the possibilities of statistical processing, precision and accuracy of the instruments. Improved measurements in the industry, resulting in significant savings by elimination of losses in production and raw materials. The improved response speed of reading the polarimeters LASERPOL Use and polarimetric detectors. (Author)

  4. Thermal treatment system of hazardous residuals in three heating zones based on a microprocessor

    International Nuclear Information System (INIS)

    Luna H, C.L.

    1997-01-01

    Thermal treatment system consists of a high power electric oven of three heating zones where each zone works up to 1200 Centigrades; it has the capacity of rising the central zone temperature up to 1000 Centigrades in 58 minutes approximately. This configuration of three zones could be programmed to different temperatures and they will be digitally controlled by a control microprocessor, which has been controlled by its own assembler language, in function of the PID control. There are also other important controls based on this microprocessor, as a signal amplification, starting and shutdown of high power step relays, activation and deactivation of both analogic/digital and digital/analogic convertors, port activation and basic data storage of the system. Two main characteristics were looked for this oven design; the first was the possibility of controlling the three zone temperature and the second was to reduce the rising and stabilization operation time and its digitized control. The principal function of the three zone oven is to accelerate the degradation of hazardous residuals by an oxidation instead combustion, through relatively high temperatures (minimum 800 Centigrades and maximum 1200 Centigrades); this process reduces the ash and volatile particulate production. The hazardous residuals will be pumped into the degradation system and after atomized through a packaged column; this step will avoid the direct contact of the residuals with the oven cores. These features make this system as closed process, which means that the residuals can not leak to the working area, reducing the exposure risk to the personnel. This three step oven system is the first stage of the complete hazardous residuals degradation system; after this, the flow will go into a cold plasma region where the process is completed, making a closed system. (Author)

  5. New concept of microprocessor protective devices design

    Directory of Open Access Journals (Sweden)

    Gurevich Vladimir

    2010-01-01

    Full Text Available Transition from electromechanical to digital protective relays is accompanied with serious technical problems. The author offers a new approach in designing the digital relays capable of solving these problems. It is proposed to construct digital relays in the form of standard modules from which it would be possible to assemble the digital relay in the same way as now a personal computer.

  6. How to harness the performance potential of current multi-core processors

    International Nuclear Information System (INIS)

    Jarp, Sverre; Lazzaro, Alfio; Leduc, Julien; Nowak, Andrzej

    2011-01-01

    Leakage currents have put a stop to the semiconductor industry's ability to increase processor frequency in order to enhance the performance of new microprocessors. Instead, we observe a slew of changes inside the micro-architecture with an aim of enhancing the performance. Several of these changes, however, do not translate into automatic speed improvements for the software. This paper discusses the increased complexity of modern microprocessors by separating out into dimensions each feature that impacts performance and mentions briefly ways of improving software, in particular that of the High Energy Physics community, to take full advantage.

  7. A HW-SW Co-Designed System for the Lunar Lander Hazard Detection and Avoidance Breadboarding

    Science.gov (United States)

    Palomo, Pedro; Latorre, Antonio; Valle, Carlos; Gomez de Aguero, Sergio; Hagenfeldt, Miguel; Parreira, Baltazar; Lindoso, Almudena; Portela, Marta; Garcia, Mario; San Millan, Enrique; Zharikov, Yuri; Entrena, Luis

    2014-08-01

    This paper presents the HW-SW co-design approach followed to tackle the design of the Hazard Detection and Avoidance (HDA) system breadboarding for the Lunar Lander ESA mission, undertaken given the fact that novel GNC technologies used to promote autonomous systems demand processing capabilities that current (and forthcoming) space processors are not able to satisfy. The paper shows how the current system design has been performed in a process in which the original HDA functionally validated design has been partitioned between SW (deemed for execution in a microprocessor) and HW algorithms (to be executed in an FPGA), considering the performance requirements and resorting to a deep analysis of the algorithms in view of their adequacy to HW or SW implementation.

  8. Use of a Microprocessor to Implement an ADCCP Protocol (Federal Standard 1003).

    Science.gov (United States)

    1980-07-01

    results of other studies, to evaluate the operational and economic impact of incorporating various options in Federal Standard 1003. The effort...the LSI interface and the microprocessor; the LSI chip deposits bytes in its buffer as the producer, and the MPU reads this data as the consumer...on the interface between the MPU and the LSI protocol chip. This requires two main processes to be running at the same time--transmit and receive. The

  9. Data acquisition and processing system of energy dispersive X-ray spectrometer with microprocessor

    International Nuclear Information System (INIS)

    Horkay, G.; Kis-Varga, M.; Lakatos, T.; Molnar, J.; Zsurzs, M.

    1984-01-01

    For quantitative analysis of chemical elements by the method of X-ray spectroscopy a multichannel analyzer on the base of minicomputer with the INTEL 8080 A microprocessor is developed. The data acquisition and data processing systems which comprise a central processor, memory unit, ADC and display are described. Major system subprograms are enumerated. An example of Pb concentration determinating in a bronze specimen is given

  10. INVESTIGATION OF MICROPROCESSOR CURRENT PROTECTION LINES WITH IMPROVED INDICES OF TECHNICAL PERFECTION

    Directory of Open Access Journals (Sweden)

    E. V. Buloichyk

    2014-01-01

    Full Text Available Technical perfection improvement of microprocessor current protection of distribution networks lines is provided by introduction of asymmetrical fault mode determination and fault location functions in the algorithm of its functioning. As a result of computing experiment the basic indices of the technical perfection of current protection have been obtained in the paper. The paper proves high efficiency of the proposed methods that ensure selective and proper operation in the different modes of the controlled line.

  11. Introduction to embedded system design using field programmable gate arrays

    CERN Document Server

    Dubey, Rahul

    2009-01-01

    Offers information on the use of field programmable gate arrays (FPGAs) in the design of embedded systems. This text considers a hypothetical robot controller as an embedded application and weaves around it related concepts of FPGA-based digital design. It is suitable for both students and designers who have worked with microprocessors.

  12. A fail-safe microprocessor-based protection system utilising low-level multiplexed sensor signals

    International Nuclear Information System (INIS)

    Orme, S.; Evans, N.J.; Wey, B.O.

    1985-01-01

    The paper describes a fail-safe reactor protection system, called the individual sub-assembly temperature monitoring system (ISAT). It is being developed for the commercial demonstration fast reactor. The system incorporates recent advances in solid-state electronics and in particular microprocessors to implement time-shared data acquisition techniques to obtain and process data from around 1400 fast response thermocouples whilst meeting the required levels for reliability and availability. (author)

  13. Performance Design

    DEFF Research Database (Denmark)

    Svabo, Connie

    Contribution to conference: Art and Presence The emerging field of Performance Design is unfolded as a bastard form of research/art/design/practice, with shapeshifting, monstruous, hybrid and transformational qualities. The potential for presencing, which emerges out of momentarily transgressing...

  14. Fault-tolerant design of adaptive digital control systems for power plant components

    International Nuclear Information System (INIS)

    Parlos, A.G.; Menon, S.K.

    1992-01-01

    An adaptive controller has been designed for the water level of a Westinghouse type U-tube steam generator, and its operation has been demonstrated in the entire power range via computer simulations. The proposed design exhibits improved performance, at low operating powers, a,s compared to existing controller types. The continuous-time controller design is performed systematically via the Linear Quadratic Gaussian/Loop Transfer Recovery method, followed by gain adaptation allowing controller operation in the entire power range. Digital implementation of the controller is accomplished by a digital redesign which results in matching the digital and continuous-time system and controller states. It is only at this stage of the control system design process that issues such as microprocessor induced quantization effects are taken into account. The use of computer-aided-design software greatly expedites the design cycle, allowing the designer to maximize the controller stability robustness to uncertainties via numerous iterations. This inherent controller robustness can be exploited to tolerate incipient plant faults, such as deteriorating U-tube heat transfer properties, without significant loss of controller performance

  15. Electric protections based in microprocessors in power plants; Protecciones electricas basadas en microprocesadores en centrales generadoras

    Energy Technology Data Exchange (ETDEWEB)

    Libreros, Domitilo; Castanon Jimenez, Jose Ismael [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1988-12-31

    This article is centered around the substitution of the conventional electric protections of a power plant in connection type unit for protections based in microprocessors. A general model of conventional protection of a power plant is described and the number of analogic and digital signals that intervene in that model are quantified. A model is setup for power plant protection with microprocessors, analyzing each one of the modules that would form it. Finally, the algorithms to carry on such protection are presented. [Espanol] Este articulo se centra en torno a la sustitucion de las protecciones electricas convencionales de una central generadora en conexion tipo unidad por protecciones basadas en microprocesadores. Se describe el modelo general de proteccion convencional de una central generadora y se cuantifica el numero de senales analogicas y digitales que interviene en dicho modelo. Se propone un modelo para proteccion de centrales generadoras mediante microprocesadores, analizandose cada uno de los modulos que lo conformarian. Finalmente, se presentan los algoritmos para realizar dicha proteccion.

  16. Electric protections based in microprocessors in power plants; Protecciones electricas basadas en microprocesadores en centrales generadoras

    Energy Technology Data Exchange (ETDEWEB)

    Libreros, Domitilo; Castanon Jimenez, Jose Ismael [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1987-12-31

    This article is centered around the substitution of the conventional electric protections of a power plant in connection type unit for protections based in microprocessors. A general model of conventional protection of a power plant is described and the number of analogic and digital signals that intervene in that model are quantified. A model is setup for power plant protection with microprocessors, analyzing each one of the modules that would form it. Finally, the algorithms to carry on such protection are presented. [Espanol] Este articulo se centra en torno a la sustitucion de las protecciones electricas convencionales de una central generadora en conexion tipo unidad por protecciones basadas en microprocesadores. Se describe el modelo general de proteccion convencional de una central generadora y se cuantifica el numero de senales analogicas y digitales que interviene en dicho modelo. Se propone un modelo para proteccion de centrales generadoras mediante microprocesadores, analizandose cada uno de los modulos que lo conformarian. Finalmente, se presentan los algoritmos para realizar dicha proteccion.

  17. Microprocessor-based data acquisition system for extensive air shower studies

    International Nuclear Information System (INIS)

    Mazumdar, G.K.D.; Kalita, P.M.; Bordoloi, T.C.; Pathak, K.M.

    1989-01-01

    Studies on electromagnetic radiation from large extensive air showers (Esub(p) ≥> 10 16 eV) have been of recent importance in the investigation of properties of EAS in problems involving mass composition, arrival time, radio emission. Cerenkov radiation etc. Such studies need fast electronic circuitry preferably for digitisation. A microprocessor based data acquisition system having scintillation counters, PA, MA, Pd, S/H and control unit has been developed and is being used in the EAS studies at Gauhati University Cosmic Ray Research Laboratory. Description of the different units along with their functioning and method of standardisation is presented in this paper. (author). 3 figs

  18. Automated analysis and design of complex structures

    International Nuclear Information System (INIS)

    Wilson, E.L.

    1977-01-01

    This paper discusses the following: 1. The relationship of analysis to design. 2. New methods of analysis. 3. Improved finite elements. 4. Effect of minicomputer on structural analysis methods. 5. The use of system of microprocessors for nonlinear structural analysis. 6. The role of interacting graphics systems in future analysis and design. The discussion focusses on the impact of new inexpensive computer hardware on design and analysis methods. (Auth.)

  19. PASSOLAR - user handbook for microprocessors. Calculations in the planning stage of solar systems. PASSOLAR - Benutzer-Handbuch fuer Mikrocomputer. Berechnungen bei der Planung von passiven Sonnenenergie-Systemen

    Energy Technology Data Exchange (ETDEWEB)

    Graeff, R.W.; Martin, N.H.; Lovy, D.; Lawton, L.

    1983-01-01

    PASSOLAR is an interactive program for microprocessors permitting to carry through a computer evaluation of parts of buildings designed for passive solar energy use. It follows the methods described in the 'Passive Solar Design Handbook, Volume Three' (7). Users are to be enabled to calculate the monthly values for the heating load, its solar fraction and the auxiliary heating load as easily as possible. These calculations are not only possible for 94 different types of solar energy supply systems in winter gardens and by direct and indirect solar radiation but also for many other systems varying more or less from the supply systems. (orig./BWI).

  20. Performative Urban Design

    DEFF Research Database (Denmark)

    Performative Urban Design seeks to identify emerging trends in urban design as they are reflected in the city's architecture and spatial design. A “cultural grafting” of the inner city is taking place; architecture and art are playing a crucial, catalytic role in urban development. On the one hand...... these issues through three perspectives: •Sense Architecture; •Place-Making; and •Urban Catalysts. The articles in this volume identify relevant theoretical positions within architecture, art, and urban strategies while demonstrating relevant concepts and methodological approaches drawn from practical......, this development has been rooted in massive investments in “corporate architecture.” On the other, cities themselves have invested heavily in new cultural centers and performative urban spaces that can fulfil the growing desire for entertainment and culture. The anthology Performative Urban Design addresses...

  1. ITRA 084 - a microprocessor controlled rapid analyzer in mining and metallurgy

    International Nuclear Information System (INIS)

    Kliem, V.; Kreher, M.; Boy, N.

    1986-01-01

    A new rapid analyzer of the ITRA series has been developed at the Freiberg Research Institute of Non-Ferrous Metals for single and multi-element analysis in mining and non-ferrous metallurgy. INTRA-08 represents an efficient microprocessor-controlled on-line X-ray fluorescence analyzer based on the main principles utilized with success hitherto in device engineering (isotope excitation, four-channel modification, balance filter method). A U880 single-chip microcomputer provides the central control of the device including the execution of an extensive program for the matrix correction. The efficiency of the analyzer is demonstrated taking measured values as a basis

  2. Wide-bandwidth low-voltage PLL for powerPC(sup TM) microprocessors

    Science.gov (United States)

    Alvarez, Jose; Sanchez, Hector; Gerosa, Gianfranco; Countryman, Roger

    1995-04-01

    A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 micron CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC(sup TM) microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 mu s, PLL power dissipation below 10mW as well as phase error and jitter below +/- 100 ps have been measured. The total area of the PLL is 0.52 mm(exp 2).

  3. Multichannel analyzer with real-time correction of counting losses based on a fast 16/32 bit microprocessor

    International Nuclear Information System (INIS)

    Westphal, G.P.; Kasa, T.

    1984-01-01

    It is demonstrated that from a modern microprocessor with 32 bit architecture and from standard VLSI peripheral chips a multichannel analyzer with real-time correction of counting losses may be designed in a very flexible yet cost-effective manner. Throughput rates of 100,000 events/second are a good match even for high-rate spectroscopy systems and may be further enhanced by the use of already available CPU chips with higher clock frequency. Low power consumption and a very compact form factor make the design highly recommendable for portable applications. By means of a simple and easily reproducible rotating sample device the dynamic response of the VPG counting loss correction method have been tested and found to be more than sufficient for conceivable real-time applications. Enhanced statistical accuracy of correction factors may be traded against speed of response by the mere change of one preset value which lends itself to the simple implementation of self-adapting systems. Reliability as well as user convenience is improved by self-calibration of pulse evolution time in the VPG counting loss correction unit

  4. Detector simulation needs for detector designers

    International Nuclear Information System (INIS)

    Hanson, G.G.

    1987-11-01

    Computer simulation of the components of SSC detectors and of the complete detectors will be very important for the designs of the detectors. The ratio of events from interesting physics to events from background processes is very low, so detailed understanding of detector response to the backgrounds is needed. Any large detector for the SSC will be very complex and expensive and every effort must be made to design detectors which will have excellent performance and will not have to undergo major rebuilding. Some areas in which computer simulation is particularly needed are pattern recognition in tracking detectors and development of shower simulation code which can be trusted as an aid in the design and optimization of calorimeters, including their electron identification performance. Existing codes require too much computer time to be practical and need to be compared with test beam data at energies of several hundred GeV. Computer simulation of the processing of the data, including electronics response to the signals from the detector components, processing of the data by microprocessors on the detector, the trigger, and data acquisition will be required. In this report we discuss the detector simulation needs for detector designers

  5. Commercialization issues and funding opportunities for high-performance optoelectronic computing modules

    Science.gov (United States)

    Hessenbruch, John M.; Guilfoyle, Peter S.

    1997-01-01

    Low power, optoelectronic integrated circuits are being developed for high speed switching and data processing applications. These high performance optoelectronic computing modules consist of three primary components: vertical cavity surface emitting lasers, diffractive optical interconnect elements, and detector/amplifier/laser driver arrays. Following the design and fabrication of an HPOC module prototype, selected commercial funding sources will be evaluated to support a product development stage. These include the formation of a strategic alliance with one or more microprocessor or telecommunications vendors, and/or equity investment from one or more venture capital firms.

  6. Status and design of the Advanced Photon Source control system

    International Nuclear Information System (INIS)

    McDowell, W.; Knott, M.; Lenkszus, F.; Kraimer, M.; Arnold, N.; Daly, R.

    1993-01-01

    This paper presents the current status of the Advanced Photon Source (APS) control system. It will discuss the design decisions which led us to use industrial standards and collaborations with other laboratories to develop the APS control system. The system uses high performance graphic workstations and the X-windows Graphical User Interface (GUI) at the operator interface level. It connects to VME/VXI-based microprocessors at the field level using TCP/IP protocols over high performance networks. This strategy assures the flexibility and expansibility of the control system. A defined interface between the system components will allow the system to evolve with the direct addition of future, improved equipment and new capabilities

  7. Microprocessor-controlled tester for evaluation of the Self-Energized Credential System (SECS)

    International Nuclear Information System (INIS)

    Corlis, N.E.

    1980-03-01

    The Self-Energized Credential System (SECS) was developed for use in the Plutonium Protection System (PPS) installed at Hanford, Washington. Evaluation and development of the SECS system was enhanced by the use of a microprocessor-controlled portal tester. This tester used infrared (ir) beam sensors to provide information on the direction of travel of the credential wearer and to detect inoperative credentials. A printed record of the portal number, actual code read, time, and direction of the credential passage provided information essential to an assessment of the operability of the SECS

  8. Flexible nanoscale high-performance FinFETs

    KAUST Repository

    Sevilla, Galo T.; Ghoneim, Mohamed T.; Fahad, Hossain M.; Rojas, Jhonathan Prieto; Hussain, Aftab M.; Hussain, Muhammad Mustafa

    2014-01-01

    With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show

  9. Design of a cardiac monitor in terms of parameters of QRS complex.

    Science.gov (United States)

    Chen, Zhen-cheng; Ni, Li-li; Su, Ke-ping; Wang, Hong-yan; Jiang, Da-zong

    2002-08-01

    Objective. To design a portable cardiac monitor system based on the available ordinary ECG machine and works on the basis of QRS parameters. Method. The 80196 single chip microcomputer was used as the central microprocessor and real time electrocardiac signal was collected and analyzed [correction of analysized] in the system. Result. Apart from the performance of an ordinary monitor, this machine possesses also the following functions: arrhythmia analysis, HRV analysis, alarm, freeze, and record of automatic papering. Convenient in carrying, the system is powered by AC or DC sources. Stability, low power and low cost are emphasized in the hardware design; and modularization method is applied in software design. Conclusion. Popular in usage and low cost made the portable monitor system suitable for use under simple conditions.

  10. Microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Agoritsas, V.; Beck, F.; Benincasa, G.P.; Bovigny, J.P.

    1986-06-01

    This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

  11. Emulation of MS DOS Operational System on the Autonomous Crate-Controller with I8086 microprocessor

    International Nuclear Information System (INIS)

    Hons, Z.; Cizek, P.; Streit, V.

    1988-01-01

    KM-DOS operating system for CAMAC autonomous crate-controller based on Intel 8086/8087 microprocessor connected with Pravec-16 IBM PC is described. The KM-DOS system fully emulates the MS DOS environment on the CAMAC controller. Thus ASSEMBLER, FORTRAN, C and PASCAL programs compiled and linked on IBM PC and compatible can be run on the CAMAC controller and parall work of both computers is enabled

  12. Preparation of Engineering Students for Capstone Design Experience through a Microprocessors Course

    Directory of Open Access Journals (Sweden)

    Mohammed El-Abd

    2017-11-01

    Full Text Available This paper presents the outcomes of a developed methodology to handle the project component in a higher-level undergraduate course. The approach relies on providing the students the freedom to choose their own project area as well as the utilized technology. At the same time, the students have to follow certain regulation to allow for the creation of a semi-capstone experience. We illustrate how this approach has a positive effect, not only on the project outcomes at the course level, but also on the students’ performances in subsequent capstone courses. Data collected, over five consecutive course offerings, shows that this approach is an effective method to prepare engineering students for their senior design capstone courses.

  13. A Forth interpreter and compiler's study for computer aided design

    International Nuclear Information System (INIS)

    Djebbar, F. Zohra Widad

    1986-01-01

    The wide field of utilization of FORTH leads us to develop an interpreter. It has been implemented on a MC 68000 microprocessor based computer, with ASTERIX, a UNIX-like operating system (real time system written by C.E.A.). This work has been done in two different versions: - The first one, fully written in C language, assures a good portability on a wide variety of microprocessors. But the performance estimations show off excessive execution times, and lead to a new optimized version. - This new version is characterized by the compilation of the most frequently used words of the FORTH basis. This allows us to get an interpreter with good performances and an execution speed close to the resulting one of the C compiler. (author) [fr

  14. Software support for Motorola 68000 microprocessor at CERN. M68MIL cross macro assembler

    International Nuclear Information System (INIS)

    Eicken, H. von.

    1983-01-01

    This document is a user's guide for programming the Motorola 68000 microprocessor in assembly language. It describes the programming model, addressing modes and instruction set of the M 68000 as well as the use of the M68mil cross macro assembler. Version 3.6 of the assembler has been installed at CERN on CDC, DEC VAX, IBM, Norsk Data and Siemens computers. The source code of the assembler is available from CERN on request. (orig.)

  15. Design of control system based on SCM music fountain

    Science.gov (United States)

    Li, Biqing; Li, Zhao; Jiang, Suping

    2018-06-01

    The design of the design of a microprocessor controlled by simple circuit, introduced this design applied to the components, and draw the main flow chart presentation. System is the use of an external music source, the intensity of the input audio signal lights will affect the light off, the fountain spray of water level will be based on changes in the lantern light off. This design uses a single-chip system is simple, powerful, good reliability and low cost.

  16. Microprocessor isotope gauges for measurement of coating thickness and of air dust pollution

    International Nuclear Information System (INIS)

    Machaj, B.; Zrudelny, F.; Sikora, A.; Jaszczuk, J.

    1986-01-01

    The article describes a coating thickness gauge based on measurement of backscattered beta particles, and an air dust pollution gauge based on measurement of dust deposited from known volume of ambient air passed through a filter, by attenuation of beta radiation. In both cases to control the gauges and to process head signals microcomputer system based on Intel 8080 microprocessor is employed. Algorithms for processing and control of the gauges and corresponding flow charts are presented. Block diagram of microcomputer system used is presented, as well as the manner of operation of the gauges. (author)

  17. Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

    Science.gov (United States)

    Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

    2018-02-01

    The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

  18. A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

    Science.gov (United States)

    Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

    1986-06-01

    This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

  19. MONICA - a programmable microprocessor for track recognition in an e+e- experiment at PETRA

    International Nuclear Information System (INIS)

    Schildt, P.; Stuckenberg, H.J.; Wermes, N.

    1981-01-01

    The microprocessor device MONICA is used in the TASSO experiment at PETRA. Its task is to reconstruct events in the cylindrical driftchamber on-line. Used as an event filter MONICA provides a 2 prong trigger without any further requirements. The speed of the processor (event reconstruction times must be in the order of 1 ms) is achieved by a 4 x 4 bit slice processor in ECL technology, content addressable memories and table look up. The track finding efficiency is 80%. (orig.)

  20. A Fourier transform with speed improvements for microprocessor applications

    Science.gov (United States)

    Lokerson, D. C.; Rochelle, R.

    1980-01-01

    A fast Fourier transform algorithm for the RCA 1802microprocessor was developed for spacecraft instrument applications. The computations were tailored for the restrictions an eight bit machine imposes. The algorithm incorporates some aspects of Walsh function sequency to improve operational speed. This method uses a register to add a value proportional to the period of the band being processed before each computation is to be considered. If the result overflows into the DF register, the data sample is used in computation; otherwise computation is skipped. This operation is repeated for each of the 64 data samples. This technique is used for both sine and cosine portions of the computation. The processing uses eight bit data, but because of the many computations that can increase the size of the coefficient, floating point form is used. A method to reduce the alias problem in the lower bands is also described.

  1. Design issues on using FPGA-based I and C systems in nuclear reactors

    Energy Technology Data Exchange (ETDEWEB)

    Farias, Marcos S.; Carvalho, Paulo Victor R. de; Santos, Isaac Jose A.L. dos; Lacerda, Fabio de, E-mail: msantana@ien.gov.br, E-mail: paulov@ien.gov.br, E-mail: luquetti@ien.gov.br, E-mail: acerda@ien.gov.br [Instituto de Engenharia Nuclear (IEN/CNEN-RJ), Rio de Janeiro, RJ (Brazil). Div. de Engenharia Nuclear

    2015-07-01

    The FPGA (field programmable gate array) is widely used in various fields of industry. FPGAs can be used to perform functions that are safety critical and require high reliability, like in automobiles, aircraft control and assistance and mission-critical applications in the aerospace industry. With these merits, FPGAs are receiving increased attention worldwide for application in nuclear plant instrumentation and control (I and C) systems, mainly for Reactor Protection System (RPS). Reasons for this include the fact that conventional analog electronics technologies are become obsolete. I and C systems of new Reactors have been designed to adopt the digital equipment such as PLC (Programmable Logic Controller) and DCS (Distributed Control System). But microprocessors-based systems may not be simply qualified because of its complex characteristics. For example, microprocessor cores execute one instruction at a time, and an operating system is needed to manage the execution of programs. In turn, FPGAs can run without an operating system and the design architecture is inherently parallel. In this paper we aim to assess these and other advantages, and the limitations, on FPGA-based solutions, considering the design guidelines and regulations on the use of FPGAs in Nuclear Plant I and C Systems. We will also examine some circuit design techniques in FPGA to help mitigate failures and provide redundancy. The objective is to show how FPGA-based systems can provide cost-effective options for I and C systems in modernization projects and to the RMB (Brazilian Multipurpose Reactor), ensuring safe and reliable operation, meeting licensing requirements, such as separation, redundancy and diversity. (author)

  2. Proposal for the award of a blanket order contract for the supply of microprocessor-based protection and control devices for the CERN HV distribution network

    CERN Document Server

    2004-01-01

    This document concerns the award of a blanket contract for the supply of microprocessor-based protection and control devices for the CERN HV distribution network. The Finance Committee is invited to agree to the negotiation of a blanket order contract with SCHNEIDER ELECTRIC (PT), the lowest technically acceptable bidder after realignment, for the supply of microprocessor-based protection and control devices for the CERN HV distribution network for a total amount of 1 900 000 euros (2 924 128 Swiss francs), subject to revision for inflation after 1 January 2007. The rate of exchange used is that stipulated in the tender

  3. Performative Urban Design

    DEFF Research Database (Denmark)

    Samson, Kristine

    2011-01-01

    visitors and participants to engage and interact with the city. Inspired by Lefebvre statement that "the most beautiful cities were those where festivals were not planned in advance” (Lefebvre 1987:36), I will discuss how urban designers can design engaging spaces, where the potentials of the city can...... unfold. Is it, for instance, the formal aesthetics of the design or rather the socio-cultural codes of the existing urban space that engage people? The paper engages in three urban performance designs: 1) The 10th Avenue Plaza at the Highline in New York 2) The temporary installations at Boble Plads......Urban design has come to mean many things. From the architectural masterplans to the informal urban design in temporary spaces and event designs. The paper will focus on urban designs engaging urban designs. Engaging urban design can broadly be understood as temporary design installations inviting...

  4. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  5. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  6. Analog circuit design designing high performance amplifiers

    CERN Document Server

    Feucht, Dennis

    2010-01-01

    The third volume Designing High Performance Amplifiers applies the concepts from the first two volumes. It is an advanced treatment of amplifier design/analysis emphasizing both wideband and precision amplification.

  7. Front end embedded microprocessors in the JET computer-based control system, past, present and future

    International Nuclear Information System (INIS)

    Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

    1987-01-01

    A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

  8. Design and evaluation of a multithreaded many-core architecture

    NARCIS (Netherlands)

    Lankamp, M.

    2015-01-01

    Performance improvements for microprocessors have traditionally been achieved by increasing their clock frequency. However, this technique has reached a point where further scaling is impractical. This thesis describes and evaluates a novel System-on-Chip architecture that focuses on exploiting all

  9. Performative Computation-aided Design Optimization

    Directory of Open Access Journals (Sweden)

    Ming Tang

    2012-12-01

    Full Text Available This article discusses a collaborative research and teaching project between the University of Cincinnati, Perkins+Will’s Tech Lab, and the University of North Carolina Greensboro. The primary investigation focuses on the simulation, optimization, and generation of architectural designs using performance-based computational design approaches. The projects examine various design methods, including relationships between building form, performance and the use of proprietary software tools for parametric design.

  10. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2009-01-01

    The classic textbook for computer systems analysis and design, Computer Organization and Design, has been thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, compu

  11. Design and fabrication of micro-nano enhanced surfaces for controlling Leidenfrost point

    OpenAIRE

    Grøstad, Eivind

    2016-01-01

    The technological revolution has driven the need for faster microprocessors. In order to fabricate faster microprocessors the trend has been to increase the amount of transistors and increase the clock speed. Microprocessor clock speed reached a point of saturation in 2006 because of the thermal challenges related to the transistors. As microprocessor power densities are increasing beyond air cooling limits, liquid cooling will become necessary. Spray cooling turn out to be the best candidate...

  12. Mechanical Engineering Design Project report: Enabler control systems

    Science.gov (United States)

    Cullen, Christian; Delvecchio, Dave; Scarborough, Alan; Havics, Andrew A.

    1992-01-01

    The Controls Group was assigned the responsibility for designing the Enabler's control system. The requirement for the design was that the control system must provide a simple user interface to control the boom articulation joints, chassis articulation joints, and the wheel drive. The system required controlling hydraulic motors on the Enabler by implementing 8-bit microprocessor boards. In addition, feedback to evaluate positions and velocities must be interfaced to provide the operator with confirmation as well as control.

  13. High-performance computing for airborne applications

    International Nuclear Information System (INIS)

    Quinn, Heather M.; Manuzatto, Andrea; Fairbanks, Tom; Dallmann, Nicholas; Desgeorges, Rose

    2010-01-01

    Recently, there has been attempts to move common satellite tasks to unmanned aerial vehicles (UAVs). UAVs are significantly cheaper to buy than satellites and easier to deploy on an as-needed basis. The more benign radiation environment also allows for an aggressive adoption of state-of-the-art commercial computational devices, which increases the amount of data that can be collected. There are a number of commercial computing devices currently available that are well-suited to high-performance computing. These devices range from specialized computational devices, such as field-programmable gate arrays (FPGAs) and digital signal processors (DSPs), to traditional computing platforms, such as microprocessors. Even though the radiation environment is relatively benign, these devices could be susceptible to single-event effects. In this paper, we will present radiation data for high-performance computing devices in a accelerated neutron environment. These devices include a multi-core digital signal processor, two field-programmable gate arrays, and a microprocessor. From these results, we found that all of these devices are suitable for many airplane environments without reliability problems.

  14. Area overhead analysis of SEF: A design methodology for tolerating SEU

    International Nuclear Information System (INIS)

    Blaquiere, Y.; Savaria, Y.

    1987-01-01

    Soft-Error filtering (SEF) is a design methodology proposed recently for implementing machines tolerant to SEU. This paper deals mainly with the evaluation and the reduction of the area overhead brought by SEF. A new shift register filtering latch configuration is proposed. The use of this latch, optimized for minimum area, reduces the area overhead by a factor of 2.6, when compared with latches optimized for time performance. A detailed analysis of the area overhead with SEF implemented on two relatively complex machines produced the following results: a SEF version of the 6800 microprocessor would require an area overhead varying between 12% and 69% depending on the SEF latch used and, a SEF version of the RISCII microprocessor would result in a 38.8% area overhead. An analysis of the cost of implementing the Hamming error correcting code on a register array is presented and this cost is compared with that of implementing SEU tolerance directly with SEF. Finally, a hybrid approach is proposed where a large register array is protected by an error correcting code whereas the isolated latches are replaced by filtering latches. This hybrid approach reduces the area overhead to 18.8% for the RISCII architecture

  15. An exploration of neuromorphic systems and related design issues/challenges in dark silicon era

    Science.gov (United States)

    Chandaliya, Mudit; Chaturvedi, Nitin; Gurunarayanan, S.

    2018-03-01

    The current microprocessors has shown a remarkable performance and memory capacity improvement since its innovation. However, due to power and thermal limitations, only a fraction of cores can operate at full frequency at any instant of time irrespective of the advantages of new technology generation. This phenomenon of under-utilization of microprocessor is called as dark silicon which leads to distraction in innovative computing. To overcome the limitation of utilization wall, IBM technologies explored and invented neurosynaptic system chips. It has opened a wide scope of research in the field of innovative computing, technology, material sciences, machine learning etc. In this paper, we first reviewed the diverse stages of research that have been influential in the innovation of neurosynaptic architectures. These, architectures focuses on the development of brain-like framework which is efficient enough to execute a broad set of computations in real time while maintaining ultra-low power consumption as well as area considerations in mind. We also reveal the inadvertent challenges and the opportunities of designing neuromorphic systems as presented by the existing technologies in the dark silicon era, which constitute the utmost area of research in future.

  16. Co-design for an SoC embedded network controller

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system's throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.

  17. Experience in installing a microprocessor-based protection system on a UK nuclear power plant

    International Nuclear Information System (INIS)

    Jones, C.D.; Smith, I.C.

    1993-01-01

    This paper describes a recently completed project to install a microprocessor-based reactor protection system on a twin reactor station in the United Kingdom. This represented the first application of digital technology as part of such a system in the UK. The background of the application and details of the chosen solution are provided. The experience gained during the installation, commissioning and early operation of the equipment is reviewed by the operators. Interactions between the utility and the regulatory body are outlined and the impact of the regulatory process on the utility's resources and the project timescales are discussed

  18. The Use of a Microprocessor-Controlled, Video Output Atomic Absorption Spectrometer as an Educational Tool in a Two-Year Technical Curriculum.

    Science.gov (United States)

    Kerfoot, Henry B.

    Based on instructional experiences at Charles County Community College, Maryland, this report examines the pedagogical advantage of teaching atomic absorption (AA) spectroscopy with an AA spectrophotometer that is equipped with a microprocessor and video output mechanism. The report first discusses the growing importance of AA spectroscopy in…

  19. EOSCOR: a light weight, microprocessor controlled solar neutron detector

    International Nuclear Information System (INIS)

    Koga, R.; Albats, P.; Frye, G.M. Jr.; Schindler, S.M.; Denehy, B.V.; Hopper, V.D.; Mace, O.B.

    1979-01-01

    A light weight high energy neutron detector with vertical detection efficiency of 0.005 at 40 MeV and 1.4 m 2 sensitive area has been developed for long duration super-pressure balloon flight observations of solar neutrons and gamma rays. It consists of two sets of four plastic scintillator hodoscopes separated by a 1 m time-of-flight path to observe n-p, C(n,p), and C(n,d) interactions. The neutron interactions are separated from gamma ray events through TOF measurements. For a large flare, the signal from solar neutrons is expected to be an order of magnitude greater than that of the atmospheric background. The microprocessor controls the data acquisition, accumulation of histograms, and the encoding of data for the telemetry systems. A test flight of the detector was made with a zero-pressure balloon. The expected many-week duration of a super-pressure balloon flight would significantly increase the probability of observing 20-150 MeV neutrons from a medium or large flare. (Auth.)

  20. System and method for leveraging human physiological traits to control microprocessor frequency

    Energy Technology Data Exchange (ETDEWEB)

    Shye, Alex; Pan, Yan; Scholbrock, Benjamin; Miller, J. Scott; Memik, Gokhan; Dinda, Peter A; Dick, Robert P

    2014-03-25

    A system and method for leveraging physiological traits to control microprocessor frequency are disclosed. In some embodiments, the system and method may optimize, for example, a particular processor-based architecture based on, for example, end user satisfaction. In some embodiments, the system and method may determine, for example, whether their users are satisfied to provide higher efficiency, improved reliability, reduced power consumption, increased security, and a better user experience. The system and method may use, for example, biometric input devices to provide information about a user's physiological traits to a computer system. Biometric input devices may include, for example, one or more of the following: an eye tracker, a galvanic skin response sensor, and/or a force sensor.

  1. Nuclear criticality evacuation with telemonitoring and microprocessors

    International Nuclear Information System (INIS)

    Fergus, R.W.; Moe, H.J. Sr.

    1979-01-01

    At Argonne National Laboratory, criticality alarms are required at widely separated locations to evacuate personnel in case of accident while emergency teams or maintenance personnel respond from a central location. The system functions have been divided in a similar manner. The alarm site hardware can independently detect a criticality and sound the evacuation signal while general monitoring and routine tests are handled by a communication link to a central monitoring station. The radiation detectors and evacuation sounders at each site are interconnected by a common two conductor cable in a unique telemonitoring format. This format allows both control and data information to be received or transmitted at any point on the cable which can be up to 3000 meters total length. The site microprocessor maintains a current data table, detects several faults, drives a printer, and communicates with the central telemonitoring station. The radiation detectors are made with plastic scintillators and photomultiplier tubes operated in a constant current mode with a 4 decade measurement range. The detectors also respond within microseconds to the criticality radiation burst. These characteristics can be tested with an internal light emitting diode either completely with a manual procedure or routinely with a system test initiated by the central monitoring station. Although the system was developed for a criticality alarm which requires reliable and redundant features, the basic techniques are useable for other monitoring and instrumentation applications

  2. Biosorption of gold from computer microprocessor leachate solutions using chitin.

    Science.gov (United States)

    Côrtes, Letícia N; Tanabe, Eduardo H; Bertuol, Daniel A; Dotto, Guilherme L

    2015-11-01

    The biosorption of gold from discarded computer microprocessor (DCM) leachate solutions was studied using chitin as a biosorbent. The DCM components were leached with thiourea solutions, and two procedures were tested for recovery of gold from the leachates: (1) biosorption and (2) precipitation followed by biosorption. For each procedure, the biosorption was evaluated considering kinetic, equilibrium, and thermodynamic aspects. The general order model was able to represent the kinetic behavior, and the equilibrium was well represented by the BET model. The maximum biosorption capacities were around 35 mg g(-1) for both procedures. The biosorption of gold on chitin was a spontaneous, favorable, and exothermic process. It was found that precipitation followed by biosorption resulted in the best gold recovery, because other species were removed from the leachate solution in the precipitation step. This method enabled about 80% of the gold to be recovered, using 20 g L(-1) of chitin at 298 K for 4 h. Copyright © 2015 Elsevier Ltd. All rights reserved.

  3. A procedure for solving the neutron diffusion equation on a parallel micro-processor; modifications to the nodal expansion codes RECNEC and HEXNEC to implement the procedure

    International Nuclear Information System (INIS)

    Putney, J.M.

    1983-05-01

    The characteristics of a simple parallel micro-processor (PMP) are reviewed and its software requirements discussed. One of the more immediate applications is the multi-spatial simulation of a nuclear reactor station. This is of particular interest because 3D reactor simulation might then be possible as part of operating procedure for PFR and CDFR. A major part of a multi-spatial reactor simulator is the solution of the neutron diffusion equation. A procedure is described for solving the equation on a PMP, which is applied to the nodal expansion method with modifications to the nodal expansion codes RECNEC and HEXNEC. Estimations of the micro-processor requirements for the simulation of both PFR and CDFR are given. (U.K.)

  4. MHTGR thermal performance envelopes: Reliability by design

    International Nuclear Information System (INIS)

    Etzel, K.T.; Howard, W.W.; Zgliczynski, J.B.

    1992-05-01

    This document discusses thermal performance envelopes which are used to specify steady-state design requirements for the systems of the Modular High Temperature Gas-Cooled Reactor to maximize plant performance reliability with optimized design. The thermal performance envelopes are constructed around the expected operating point accounting for uncertainties in actual plant as-built parameters and plant operation. The components are then designed to perform successfully at all points within the envelope. As a result, plant reliability is maximized by accounting for component thermal performance variation in the design. The design is optimized by providing a means to determine required margins in a disciplined and visible fashion

  5. Use of a Microprocessor to Implement an ADCCP Protocol (Federal Std-1003) Operating in the Unbalanced Normal Mode.

    Science.gov (United States)

    1980-05-01

    andcoptrpormigfrteublne nra ls fpoeue nacrac with Federal Standard 1003 fTelecommunications: Synchronous Bit Oriented Data Link Control Procedures...and the higher level user. The solution to the producer/consumer problem involves the use of PASS and SICHAL primitives and event variables or... semaphores . The event variables have been defined for the LS-microprocessor interface as part of I-1 the internal registers that are included in the F6856

  6. Software support for Motorola 68000 microprocessor at CERN. CERN convention for programming the MC68000 family

    International Nuclear Information System (INIS)

    Cailliau, R.; Carpenter, B.

    1984-01-01

    The CERN convention for programming the MC68000 family of microprocessors gives a set of rules describing the layout of the memory and stack frames used by routines as they should appear before and after their calling sequences. It does not deal with the instructions used to achieve these states. The aim of the convention is to allow programming language mixing as well as debugging of programs built from units written in different languages. It is to be followed by programmers and programming-language compilers. (orig.)

  7. Designing performativity for mixed reality installations

    Directory of Open Access Journals (Sweden)

    Andrew Morrison

    2010-07-01

    Full Text Available This article takes up the concept of performativity prevalent in the humanities and applies it to the design of installation arts in mixed reality mode. Based on the design, development and public access to two specific works, the concept is related to a form of research by design. We argue that the concept of performativity may be further usefully employed in investigations (design and research, artistic and public into digital arts where complex intersections between concepts, technologies, dramaturgy, media and participant actions are in flux and together constitute the emergence and experience of a work. Theories of performativity are related to these two works in an argument that further suggests there is room in research by design to also include ‘performative design’. The article is the result of a wide-ranging interdisciplinary collaboration and aims to convey some sense of that in its reporting style, content and analysis.

  8. Roots of Performance - Aided Design in Utzon´s design principles

    DEFF Research Database (Denmark)

    Parigi, Dario

    2014-01-01

    on paper, to an evolving paradigm where the increasing integration of parametric tools, performative analysis and computational methods is changing the way we learn and design. Its constitutive factors are: 1) embedded tectonics, 2) performance simulation 3) computational methods.......This paper discuss an emerging paradigm here identified as PAD, acronym of Performance-Aided Design, that aims at embracing complexity in the design process, and tackling it with digital tools. Computer Aided Design tools are gradually shifting from the mere translation of the work once carried...

  9. Environmental dose measurement with microprocessor based portable TLD reader

    International Nuclear Information System (INIS)

    Deme, S.; Apathy, I.; Feher, I.

    1996-01-01

    Application of TL method for environmental gamma-radiation dosimetry involves uncertainty caused by the dose collected during the transport from the point of annealing to the place of exposure and back to the place of evaluation. Should an accident occur read out is delayed due to the need to transport to a laboratory equipped with a TLD reader. A portable reader capable of reading out the TL dosemeter at the place of exposure ('in situ TLD reader') eliminates the above mentioned disadvantages. We have developed a microprocessor based portable TLD reader for monitoring environmental gamma-radiation doses and for on board reading out of doses on space stations. The first version of our portable, battery operated reader (named Pille - 'butterfly') was made at the beginning of the 80s. These devices used CaSO 4 bulb dosemeters and the evaluation technique was based on analogue timing circuits and analogue to digital conversion of the photomultiplier current with a read out precision of 1 μGy and a measuring range up to 10 Gy. The measured values were displayed and manually recorded. The version with an external power supply was used for space dosimetry as an onboard TLD reader

  10. Automated microprocessor-controlled atomic absorption analysis of natural water for arsenic and selenium

    International Nuclear Information System (INIS)

    Morrow, R.W.; Futrell, T.L.; Adams, T.T.

    1978-08-01

    An automated, dual-channel atomic absorption spectrophotometer for the simultaneous determination of arsenic and selenium in natural water is now in operation. The instrument was constructed from commercially available optical components, spectral sources, and a sample changer. Automation was achieved by using an in-house-fabricated and programmed microprocessor. The instrument will analyze samples at a rate of 37 per hour, and a quantitative determination of arsenic and selenium to 0.2 μg/l (ppB) can be achieved. Arsenic can be determined with a precision of 19% at 1 μg/l and 6% at 10 μg/l, while selenium can be determined with a precision of 17% at 1 μg/l and 4% at 10 μg/l

  11. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  12. The first IA-64 microprocessor

    CERN Document Server

    Rusu, S

    2000-01-01

    The first implementation of the IA-64 architecture achieves high performance by using a highly parallel execution core, while maintaining binary compatibility with the IA-32 instruction set. Explicitly parallel instruction computing (EPIC) design maximizes performance through hardware and software synergy. The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18- mu m CMOS process with six metal layers and packaged in a 1012-pad organic land grid array using C4 (flip chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache. (6 refs).

  13. Design of intelligent gateway control system based on AllJoyn and FC-3180

    Directory of Open Access Journals (Sweden)

    Chen Yanzhong

    2017-02-01

    Full Text Available To simplify interconnection of distributed household equipment,this design creates a spontaneous,movable,safe and configurable equipment management system and smart home layout with the open-source software framework AllJoyn,the embedded microprocessor FC-3180,the low power wireless transmission network ZigBee and mobile application platform Android.

  14. Ways of Telecommunications Interaction Arrangement for Microprocessor Devices of Different Types in Composition of Multi-Motor Electric Drives

    Science.gov (United States)

    Shpenst, V. A.; Vasiliev, B. Y.; Kalashnikov, O. V.; Oleynikova, A. M.

    2018-05-01

    The article covers a consideration of various state-of-the-art industrial data transfer protocols, e.g. Modbus, Profibus, Industrial Ethernet and CAN. Their pros and cons are analyzed and conclusions made on advisability of the use of each protocol. It is shown that for the arrangement of effective telecommunication interaction of microprocessor devices of different types in the composition of multi-motor electric drives, it is advisable to use highlevel CAN-protocols, such as CANopen and DeviceNet.

  15. Thermal performance envelopes for MHTGRs - Reliability by design

    International Nuclear Information System (INIS)

    Etzel, K.T.; Howard, W.W.; Zgliczynski, J.

    1992-01-01

    Thermal performance envelopes are used to specify steady-state design requirements for the systems of the modular high-temperature gas-cooled reactor (MHTGR) to maximize plant performance reliability with optimized design. The thermal performance envelopes are constructed around the expected operating point to account for uncertainties in actual plant as-built parameters and plant operation. The components are then designed to perform successfully at all points within the envelope. As a result, plant reliability is maximized by accounting for component thermal performance variation in the design. The design is optimized by providing a means to determine required margins in a disciplined and visible fashion. This is accomplished by coordinating these requirements with the various system and component designers in the early stages of the design, applying the principles of total quality management. The design is challenged by the more complex requirements associated with a range of operating conditions, but in return, high probability of delivering reliable performance throughout the plant life is ensured

  16. A Westinghouse designed distributed mircroprocessor based protection and control system

    International Nuclear Information System (INIS)

    Bruno, J.; Reid, J.B.

    1980-01-01

    For approximately five years, Westinghouse has been involved in the design and licensing of a distributed microprocessor based system for the protection and control of a pressurized water reactor nuclear steam supply system. A 'top-down' design methodology was used, in which the system global performance objectives were specified, followed by increasingly more detailed design specifications which ultimately decomposed the system into its basic hardware and software elements. The design process and design decisions were influenced by the recognition that the final product would have to be verified to ensure its capability to perform the safety-related functions of a class 1E protection system. The verification process mirrored the design process except that it was 'bottom-up' and thus started with the basic elements and worked upwards through the system in increasingly complex blocks. A number of areas which are of interest in a distributed system are disucssed, with emphasis on two systems. The first, the Integrated Protection System is primarily responsible for processing signals from field mounted sensors to provide for reactor trips and the initiation of the Engineered Safety Features. The Integrated Control System, which is organized in a parallel manner, processes other sensor signals and generates the necessary analog and on-off signals to maintain the plant parameters within specified limits. Points covered include system structure, systems partitioning strategies, communications techniques, software design concepts, reliability and maintainability, commercial component availability, interference susceptibility, licensing issues, and applicability. (LL)

  17. DPL/Daedalus design environment (for VLSI)

    Energy Technology Data Exchange (ETDEWEB)

    Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

    1981-01-01

    The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

  18. Performance-based Pareto optimal design

    NARCIS (Netherlands)

    Sariyildiz, I.S.; Bittermann, M.S.; Ciftcioglu, O.

    2008-01-01

    A novel approach for performance-based design is presented, where Pareto optimality is pursued. Design requirements may contain linguistic information, which is difficult to bring into computation or make consistent their impartial estimations from case to case. Fuzzy logic and soft computing are

  19. Nuclear fuel elements design, fabrication and performance

    CERN Document Server

    Frost, Brian R T

    1982-01-01

    Nuclear Fuel Elements: Design, Fabrication and Performance is concerned with the design, fabrication, and performance of nuclear fuel elements, with emphasis on fast reactor fuel elements. Topics range from fuel types and the irradiation behavior of fuels to cladding and duct materials, fuel element design and modeling, fuel element performance testing and qualification, and the performance of water reactor fuels. Fast reactor fuel elements, research and test reactor fuel elements, and unconventional fuel elements are also covered. This volume consists of 12 chapters and begins with an overvie

  20. Use of a bipolar microprocessor in a multi-window discriminator for a system studying reactor fuel pins

    International Nuclear Information System (INIS)

    Frueh, J.

    1977-01-01

    An automatic evaluation system for non-destructive reactor fuel rod analysis is described. The characteristic γ radiation of certain radioisotopes is measured, and the isotope concentration is derived from this. To determine the radioisotope concentration, a digital multi-window discriminator is installed in the system to isolate the desired γ lines from the total spectrum; in addition, background subtraction is carried out. The multi-window discriminator was constructed of bipolar bit-slice microprocessor modules. A microinstruction set of 4 basic commands was defined by which the functional sequences in the instrument were programmed. (orig.) [de

  1. Design of a continuous duty cryopump

    International Nuclear Information System (INIS)

    Sedgley, D.W.

    1985-05-01

    A continuous duty cryopump system was designed and developed that comprises a self-contained cryopump for installation into a vacuum chamber, and a microprocessor controller for automatic operation. This deuterium pump has two units in a single housing, arranged so that one is pumping while the other is being regenerated. Liquid helium-cooled, finned sections in each unit pump deuterium by condensation, and a third pump integral within the cryopump housing collects the regenerated gas. A microprocessor unit controls distribution of liquid and gaseous helium, used for conditioning the pumping units, and operates remote actuators for the regeneration. Software provides fully automatic, timed sequencing of the repetitive cryopump events which include: cooldown of the pumping units, opening of the louvers isolating the unit from the vacuum chamber, closing of the louvers, and warming up of the unit for regeneration. Default values in the software can be reprogrammed by the operator through the keyboard in response to prompts displayed on the computer. An override allows the operator to control the cryopump manually by activating switches on a control panel. Interlocks to prevent cryogen lockup are included in the software

  2. Design of a Tritium-in-air-monitor using field programmable gate arrays

    International Nuclear Information System (INIS)

    McNelles, Phillip; Lu, Lixuan

    2015-01-01

    Field Programmable Gate Arrays (FPGAs) have recently garnered significant interest for certain applications within the nuclear field. Some applications of these devices include Instrumentation and Control (I and C) systems, pulse measurement systems, particle detectors and health physics purposes. In CANada Deuterium Uranium (CANDU) nuclear power plants, the use of heavy water (D2O) as the moderator leads to the increased production of Tritium, which poses a health risk and must be monitored by Tritium-In-Air Monitors (TAMs). Traditional TAMs are mostly designed using microprocessors. More recent studies show that FPGAs could be a potential alternative to implement the electronic logic used in radiation detectors, such as the TAM, more effectively. In this paper, an FPGA-based TAM is designed and constructed in a laboratory setting using an FPGA-based cRIO system. New functionalities, such as the detection of Carbon-14 and the addition of noble gas compensation are incorporated into a new FPGA-based TAM. Additionally, all of the standard functions included in the original microprocessor-based TAM, such as tritium detection, gamma compensation, pump and air flow control, and background and thermal drift corrections were also implemented. The effectiveness of the new design is demonstrated through simulations as well as laboratory testing on the prototype system. (author)

  3. A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

    Science.gov (United States)

    Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

    2009-01-01

    For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

  4. Software/firmware design specification for 10-MWe solar-thermal central-receiver pilot plant

    Energy Technology Data Exchange (ETDEWEB)

    Ladewig, T.D.

    1981-03-01

    The software and firmware employed for the operation of the Barstow Solar Pilot Plant are completely described. The systems allow operator control of up to 2048 heliostats, and include the capability of operator-commanded control, graphic displays, status displays, alarm generation, system redundancy, and interfaces to the Operational Control System, the Data Acquisition System, and the Beam Characterization System. The requirements are decomposed into eleven software modules for execution in the Heliostat Array Controller computer, one firmware module for execution in the Heliostat Field Controller microprocessor, and one firmware module for execution in the Heliostat Controller microprocessor. The design of the modules to satisfy requirements, the interfaces between the computers, the software system structure, and the computers in which the software and firmware will execute are detailed. The testing sequence for validation of the software/firmware is described. (LEW)

  5. Microprocessor based beam intensity and efficiency display system for the Fermilab accelerator

    International Nuclear Information System (INIS)

    Biwer, R.

    1979-01-01

    The Main Accelerator display system for the Fermilab accelerator gathers charge data and displays it including processed transfer efficiencies of each of the accelerators. To accomplish this, strategically located charge converters monitor the circulating internal beam of each of the Fermilab accelerators. Their outputs are processed via an asynchronously triggered, multiplexed analog-to-digital converter. The data is converted into a digital byte containing address code and data, then stores it into two 16-bit memories. One memory outputs the interleaved data as a data pulse train while the other interfaces directly to a local host computer for further analysis. The microprocessor based display unit synchronizes displayed data during normal operation as well as special storage modes. The display unit outputs data to the fron panel in the form of a numeric value and also makes digital-to-analog conversions of displayed data for external peripheral devices. 5 refs

  6. A CAMAC-resident microprocessor used for field control of a dipole magnet

    International Nuclear Information System (INIS)

    Sharp, F.J.; Greiner, B.F.

    1990-01-01

    An inexpensive, self-contained microprocessor supporting an on-chip BASIC interpreter has been incorporated into a CAMAC auxiliary-crate controller, with an EEPROM and a terminal port. Used with an ASCII computer terminal, the intelligent auxiliary controller is a self-contained program-development system. One application for the intelligent auxiliary controller is closed-loop control of the analyzing dipoles at the negative-ion injector of the TASCC (tandem accelerator superconducting cyclotron) heavy-ion accelerators. A BASIC program stored in the EEPROM runs on power-up of the controller. The program reads control numbers from a CAMAC mailbox, converts the ASCII character string from a precision Hall-probe teslameter to a digital field reading, and writes a control number to the dipole controller. The program iterates until the dipole reaches the demand field, while updating another CAMAC mailbox with a field readback for the main control system. (orig.)

  7. A low-cost high-performance embedded platform for accelerator controls

    International Nuclear Information System (INIS)

    Cleva, Stefano; Bogani, Alessio Igor; Pivetta, Lorenzo

    2012-01-01

    Over the last years the mobile and hand-held device market has seen a dramatic performance improvement of the microprocessors employed for these systems. As an interesting side effect, this brings the opportunity of adopting these microprocessors to build small low-cost embedded boards, featuring lots of processing power and input/output capabilities. Moreover, being capable of running a full featured operating system such as Gnu/Linux, and even a control system toolkit such as Tango, these boards can also be used in control systems as front-end or embedded computers. In order to evaluate the feasibility of this idea, an activity has started at Elettra to select, evaluate and validate a commercial embedded device able to guarantee production grade reliability, competitive costs and an open source platform. The preliminary results of this work are presented. (author)

  8. Médicarte software developed for the Quebec microprocessor health card project.

    Science.gov (United States)

    Lavoie, G; Tremblay, L; Durant, P; Papillon, M J; Bérubé, J; Fortin, J P

    1995-01-01

    The Quebec Patient Smart Card Project is a Provincial Government initiative under the responsibility of the Rgie de l'assurance-maladie du Québec (Quebec Health Insurance Board). Development, implementation, and assessment duties were assigned to a team from Université Laval, which in turn joined a group from the Direction de la santé publique du Bas-St-Laurent in Rimouski, where the experiment is taking place. The pilot project seeks to evaluate the use and acceptance of a microprocessor card as a way to improve the exchange of clinical information between card users and various health professionals. The card can be best described as a résumé containing information pertinent to an individual's health history. It is not a complete medical file; rather, it is a summary to be used as a starting point for a discussion between health professionals and patients. The target population is composed of persons 60 years and over, pregnant women, infants under 18 months, and the residents of a small town located in the target area, St-Fabien, regardless of age. The health professionals involved are general practitioners, specialists, pharmacists, nurses, and ambulance personnel. Participation in the project is on a voluntary basis. Each health care provider participating in the project has a personal identification number (PIN) and must use both an access card and a user card to access information. This prevents unauthorized access to a patient's card and allows the staff to sign and date information entered onto the patient card. To test the microprocessor card, we developed software based on a problem-oriented approach integrating diagnosis, investigations, treatments, and referrals. This software is not an expert system that constrains the clinician to a particular decisional algorithm. Instead, the software supports the physician in decision making. The software was developed with a graphical interface (Windows 3.1) to maximize its user friendliness. A version of the

  9. Computer-aided orbital welding reaches a new level of performance

    International Nuclear Information System (INIS)

    Galloway, J.G.; Maak, P.Y.Y.; McNabb, S.C.

    1993-01-01

    This article documents the development of a custom-built microprocessor controller which overcomes the major shortcomings of existing commercially available pipe welding systems. This unique control design effectively extends the one-knob-control concept of the power source industry to the control of a complete mechanized welding system. Magnatech, East Granby, Conn., a manufacturer of orbital welding equipment, will be commercializing this technology into its Pipeliner welding system in the near future. Ontario Hydro Research Div. purchased a commercial pipe welding system for both laboratory welding development and field trials. Its applications were targeted for pressure piping in both nuclear power and fossil fuel fired electricity generating plants. They demonstrated the feasibility of using a mechanized continuous wire welding process to weld the fill passes of carbon steel piping to stringent inspection standards of nuclear pressure piping. They also concluded that significant improvements to commercial pipe welding systems can be achieved through the use of microprocessor controls

  10. Designing and Implementing Performance Technology for Teachers

    Directory of Open Access Journals (Sweden)

    Joi L. Moore

    2004-06-01

    Full Text Available This paper synthesizes research findings from a performance analysis of teacher tasks and the implementation of performance technology. These findings are aligned with design and implementation theories to provide understanding of the complex factors and events that occur during the implementation process. The article describes the necessary elements and conditions for designing and implementing performance tools in school environments that will encourage usage, efficient performance, and positive attitudes. Two models provide a visual representation of causal relationships between the implementation factors and the technology user. Although the implementation process can become complex because of the simultaneous events and phases, it can be properly managed through good communication and strategic involvement of teachers during the design and development process. The models may be able to assist technology designers and advocates with presenting innovations to teachers who are frequently asked to try technical solutions for performance support or improvement.

  11. Design of verification platform for wireless vision sensor networks

    Science.gov (United States)

    Ye, Juanjuan; Shang, Fei; Yu, Chuang

    2017-08-01

    At present, the majority of research for wireless vision sensor networks (WVSNs) still remains in the software simulation stage, and the verification platforms of WVSNs that available for use are very few. This situation seriously restricts the transformation from theory research of WVSNs to practical application. Therefore, it is necessary to study the construction of verification platform of WVSNs. This paper combines wireless transceiver module, visual information acquisition module and power acquisition module, designs a high-performance wireless vision sensor node whose core is ARM11 microprocessor and selects AODV as the routing protocol to set up a verification platform called AdvanWorks for WVSNs. Experiments show that the AdvanWorks can successfully achieve functions of image acquisition, coding, wireless transmission, and obtain the effective distance parameters between nodes, which lays a good foundation for the follow-up application of WVSNs.

  12. Design of the RISC-V Instruction Set Architecture

    OpenAIRE

    Waterman, Andrew Shell

    2016-01-01

    The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary. A free and open ISA standard has the potential to increase innovation in microprocessor design, reduce computer system cost, and, as Moore’s law wanes, ease the transition to more specialized computational devices.In this d...

  13. THE METHOD OF SELECTION OF THE SETPOINT HIGH SPEED FEEDER SWITCH OF 3,3KV DC WITH MICROPROCESSOR-BASED PROTECTION SYSTEMS

    Directory of Open Access Journals (Sweden)

    P. Ye. Mykhalichenko

    2009-10-01

    Full Text Available In the article a new procedure of choice of minimum current jump for action of fast-acting switches of 3.3 kV DC traction substations intended for the use in the microprocessor protection system of feeders is described. This procedure is more perfect than existing one on the current increment and uses the results of mathematical simulation of the traction electric supply system.

  14. Multi performance option in direct displacement based design

    Directory of Open Access Journals (Sweden)

    Muljati Ima

    2017-01-01

    Full Text Available Compare to traditional method, direct displacement based design (DDBD offers the more rational design choice due to its compatibility with performance based design which is controlled by the targeted displacement in design. The objectives of this study are: 1 to explore the performance of DDBD for design Level-1, -2 and -3; 2 to determine the most appropriate design level based on material efficiency and damage risk; and 3 to verify the chosen design in order to check its performance under small-, moderate- and severe earthquake. As case study, it uses regular concrete frame structures consists of fourand eight-story with typical plan, located in low- and high-risk seismicity area. The study shows that design Level-2 (repairable damage is the most appropriate choice. Nonlinear time history analysis is run for each case study in order to verify their performance based on parameter: story drift, damage indices, and plastic mechanism. It can be concluded that DDBD performed very well in predicting seismic demand of the observed structures. Design Level-2 can be chosen as the most appropriate design level. Structures are in safe plastic mechanism under all level of seismicity although some plastic hinges formed at some unexpected locations.

  15. Design and implementation of data acquisition, communication and monitoring system for photovoltaic power station in microgrid

    Energy Technology Data Exchange (ETDEWEB)

    Deng, Wei; Pei, Wei; Qi, Zhiping; Kong, Li [Institute of Electrical Engineering, CAS, Beijing (China)

    2008-07-01

    This paper presents the design and realization of data acquisition, communication and monitoring system for photovoltaic power station. The data acquisition module including filter algorithm and signal modulation circuit uses the digital signal processor (DSP) as the main processor, it can realize accurate real-time data acquisition; The data communication module uses Ethernet as communication network between PV system and MicroGrid. The gateway using ARM microprocessor can realize protocol conversion and bidirectional communication between CAN Bus and Ethernet; The monitoring unit with friendly human-machine interface keeps real-time performance monitoring of PV system to realize automation control. The results of experiment show that the system is practicable and effective. (orig.)

  16. Design-for-variety, postponement, and operational performance

    DEFF Research Database (Denmark)

    Boer, Henrike Engele Elisabeth

    2015-01-01

    Design for variety (DFV) practices such as product modularization, platform thinking and design for manufacturing/assembly have been suggested to yield considerable operational performance benefits. Some of these performance effects can be expected in all manufacturing settings, including the pos...

  17. Design, fabrication and characterisation of nano-imprinted single mode waveguide structures for intra-chip optical communications

    NARCIS (Netherlands)

    Justice, J.; Khan, U.; Korhonen, T.; Boersma, A.; Wiegersma, S.; Karppinen, M.; Corbett, B.

    2015-01-01

    In the Information and Communications Technology (ICT) sector, the demands on bandwidth continually grow due to increased microprocessor performance and the need to access ever increasing amounts of stored data. The introduction of optical data transmission (e.g. glass fiber) to replace electronic

  18. The effects of environmental factors and experimental method on the results of low dose rate microprocessor irradiation tests

    Energy Technology Data Exchange (ETDEWEB)

    Laviron, A; Gerard, G [Commissariat a l' Energie Atomique, IPSN, Centre d' Etudes de Valduc, Is-sur-Tille (France); Gauthier, G; Henry, J Y; Le Meur, M [Commissariat a l' Energie Atomique, IPSN, Fontenay-aux-Roses (France)

    1992-02-01

    As part of the safety studies of nuclear facilities, a series of experiments have been in progress over a number of years to determine the principal parameters for which allowance needs to be made in the testing of microprocessors in low dose rate nuclear irradiation environments. This paper contains a brief description of the results already published, followed by a review of the latest results obtained, specifically as concerns the effects of temperature, the origin of the batch, the angle of incidence of the radiation and the test routine used. (author)

  19. Immediate effects of a new microprocessor-controlled prosthetic knee joint: a comparative biomechanical evaluation.

    Science.gov (United States)

    Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

    2012-03-01

    To investigate the immediate biomechanical effects after transition to a new microprocessor-controlled prosthetic knee joint. Intervention cross-over study with repeated measures. Only prosthetic knee joints were changed. Motion analysis laboratory. Men (N=11; mean age ± SD, 36.7±10.2y; Medicare functional classification level, 3-4) with unilateral transfemoral amputation. Two microprocessor-controlled prosthetic knee joints: C-Leg and a new prosthetic knee joint, Genium. Static prosthetic alignment, time-distance parameters, kinematic and kinetic parameters, and center of pressure. After a half-day training and an additional half-day accommodation, improved biomechanical outcomes were demonstrated by the Genium: lower ground reaction forces at weight acceptance during level walking at various velocities, increased swing phase flexion angles during walking on a ramp, and level walking with small steps. Maximum knee flexion angle during swing phase at various velocities was nearly equal for Genium. Step-over-step stair ascent with the Genium knee was more physiologic as demonstrated by a more equal load distribution between the prosthetic and contralateral sides and a more natural gait pattern. When descending stairs and ramps, knee flexion moments with the Genium tended to increase. During quiet stance on a decline, subjects using Genium accepted higher loading of the prosthetic side knee joint, thus reducing same side hip joint loading as well as postural sway. In comparision to the C-Leg, the Genium demonstrated immediate biomechanical advantages during various daily ambulatory activities, which may lead to an increase in range and diversity of activity of people with above-knee amputations. Results showed that use of the Genium facilitated more natural gait biomechanics and load distribution throughout the affected and sound musculoskeletal structure. This was observed during quiet stance on a decline, walking on level ground, and walking up and down ramps and

  20. Solar energy system performance evaluation: Honeywell OTS 41, Shenandoah (Newman), Georgia

    Science.gov (United States)

    Mathur, A. K.; Pederson, S.

    1982-08-01

    The operation and technical performance of the Solar Operational Test Site (OTS 41) located at Shenandoah, Georgia, are described, based on the analysis of the data collected between January and August 1981. The following topics are discussed: system description, performance assessment, operating energy, energy savings, system maintenance, and conclusions. The solar energy system at OTS 41 is a hydronic heating and cooling system consisting of 702 square feet of liquid-cooled flat-plate collectors; a 1000-gallon thermal storage tank; a 3-ton capacity organic Rankine-cycle-engine-assisted air conditioner; a water-to-are heat exchanger for solar space heating; a finned-tube coil immersed in the storage tank to preheat water for a gas-fired hot water heater; and associated piping, pumps, valves, and controls. The solar system has six basic modes of operation and several combination modes. The system operation is controlled automatically by a Honeywell-designed microprocessor-based control system, which also provides diagnostics.

  1. The Performance of Step-Wise Group Screening Designs

    Directory of Open Access Journals (Sweden)

    M.M. Manene

    2005-06-01

    Full Text Available In this paper we evaluate the performance of step-wise group screening designs in which group-factors contain an equal number of factors in the initial step.  A usual assumption in group screening designs is that the directions of possible effects are known a-priori. In practice, however, this assumption is unreasonable. We shall examine step-wise group screening designs without errors in observations when this assumption is relaxed. We shall consider cancellations of effects within group-factors. The performance of step-wise group-screening designs shall then be compared with the performance of multistage group screening designs.

  2. Portable regional cerebral blood flow system based on IBM PC/AT and microprocessor electronics

    International Nuclear Information System (INIS)

    Mun, S.K.; Mun, I.K.; Petite, J.; Cohan, S.L.; Fahey, F.H.

    1986-01-01

    A portable 16-channel reginal cerebral blood flow (rCBF) measuring system has been developed using an IBM PC/AT and new microelectronics to improve processing speed and portability. The detector electronics were developed by Scan Detectronics A/S of Denmark. The counter module contains 18 16-bit counters, each programmable in four different modes. The rate meter has three independent microprocessor controllers for rate meter functions, window controller, and channel controller. The detector electronics and detection parameters can be fully controlled by the host PC/AT. The menu-driven system (Better Basic) assists the operator at each step. The collected data from 16 channels can be processed automatically or postprocessed using more flexible and sophisticated techniques within 20 minutes. The headgear holding 16 sodium iodide detectors is fabricated by modifying a motorcycle helmet

  3. An integrated high performance Fastbus slave interface

    International Nuclear Information System (INIS)

    Christiansen, J.; Ljuslin, C.

    1993-01-01

    A high performance CMOS Fastbus slave interface ASIC (Application Specific Integrated Circuit) supporting all addressing and data transfer modes defined in the IEEE 960 - 1986 standard is presented. The FAstbus Slave Integrated Circuit (FASIC) is an interface between the asynchronous Fastbus and a clock synchronous processor/memory bus. It can work stand-alone or together with a 32 bit microprocessor. The FASIC is a programmable device enabling its direct use in many different applications. A set of programmable address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/sec to Fastbus can be obtained using an internal FIFO in the FASIC to buffer data between the two buses during block transfers. Message passing from Fastbus to a microprocessor on the slave module is supported. A compact (70 mm x 170 mm) Fastbus slave piggy back sub-card interface including level conversion between ECL and TTL signal levels has been implemented using surface mount components and the 208 pin FASIC chip

  4. Containment design, performance criteria and research needs for advanced reactor designs

    International Nuclear Information System (INIS)

    Bagdi, G.; Ali, S.; Costello, J

    2004-01-01

    This paper points out some important shifts in the basic expectations in the performance requirements for containment structures and discusses the areas where the containment structure design requirements and acceptance criteria can be integrated with ultimate test based insights. Although there has not been any new reactor construction in the United States for over thirty years, several designs of evolutionary and advanced reactors have already been certified. Performance requirements for containment structures under design basis and severe accident conditions and explicit consideration of seismic margins have been used in the design certification process. In the United States, the containment structure design code is the American Society of Mechanical Engineers, Boiler and Pressure Vessel Code, Section III, Division 1, Subsection NE-Class MC for the steel containment and Section III, Division 2 for reinforced and prestressed concrete reactor vessels and containments. This containment design code was based on the early concept of applying design basis internal pressure and associated load combinations that included the operating basis and safe shutdown earthquake ground motion. These early design criteria served the nuclear industry and the regulatory authorities in maintaining public health and safety. However, these early design criteria do not incorporate the performance criteria related to containment function in an integrated fashion. Research in large scale model testing of containment structures to failure from over pressurization and shake table testing using simulated ground motion, have produced insights related to failure modes and material behavior at failure. The results of this research provide the opportunity to integrate these observations into design and acceptance criteria. This integration process would identify 'gaps' in the present knowledge and future research needs. This knowledge base is important for gleaning risk-informed insights into

  5. Resilient architecture design for voltage variation

    CERN Document Server

    Reddi, Vijay Janapa

    2013-01-01

    Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe

  6. Modification and Actuator Minimization of the Hip Leg Joint in a Bipedal Robot: A Proposed Design

    Directory of Open Access Journals (Sweden)

    Nirmalya Tripathi

    2014-12-01

    Full Text Available In recent times, there have been numeric applications of Biped Robots. In this paper, a proposed upper leg hip design of a biped was developed taking cost reduction and optimization as factors for consideration. The proposed system introduces a novel method which consists of a vibration reduction (VR DC stepper motor, microcontroller, microprocessor and gearing arrangement. The program in the microprocessor is so designed that it gives a fixed number of cycles/steps to the VR DC stepper motor in clockwise and thereafter in anti-clockwise direction. This turning movement can then be transmitted to the gearing system which precisely moves one upper leg when the VR DC stepper motor moves in clockwise direction, while the other upper leg remains static, and vice-versa. It has been observed that this new proposed system may reduce the cost overhead, weight and the energy consumption incurred by working on a single VR DC stepper motor while conventionally two stepper motors are used to give the motion of the two upper legs in a biped.

  7. Overview of Performance Based Practical Design

    Science.gov (United States)

    2018-03-01

    DOI: https://doi.org/10.13023/KTC.RR.2018.03 State transportation agencies (STAs) have increasingly turned to practical design and performance based practical design(PBPD) to inform project development and implementation and to reduce project cos...

  8. Scientific Performance Analysis of the SYZ Telescope Design versus the RC Telescope Design

    Science.gov (United States)

    Ma, Donglin; Cai, Zheng

    2018-02-01

    Recently, Su et al. propose an innovative design, referred as the “SYZ” design, for China’s new project of a 12 m optical-infrared telescope. The SYZ telescope design consists of three aspheric mirrors with non-zero power, including a relay mirror below the primary mirror. SYZ design yields a good imaging quality and has a relatively flat field curvature at Nasmyth focus. To evaluate the science-compatibility of this three-mirror telescope, in this paper, we thoroughly compare the performance of SYZ design with that of Ritchey–Chrétien (RC) design, a conventional two-mirror telescope design. Further, we propose the Observing Information Throughput (OIT) as a metric for quantitatively evaluating the telescopes’ science performance. We find that although a SYZ telescope yields a superb imaging quality over a large field of view, a two-mirror (RC) telescope design holds a higher overall throughput, a better diffraction-limited imaging quality in the central field of view (FOV < 5‧) which is better for the performance of extreme Adaptive Optics (AO), and a generally better scientific performance with a higher OIT value. D. Ma & Z. Cai contributed equally to this paper.

  9. Bionic Design, Materials and Performance of Bone Tissue Scaffolds

    Directory of Open Access Journals (Sweden)

    Tong Wu

    2017-10-01

    Full Text Available Design, materials, and performance are important factors in the research of bone tissue scaffolds. This work briefly describes the bone scaffolds and their anatomic structure, as well as their biological and mechanical characteristics. Furthermore, we reviewed the characteristics of metal materials, inorganic materials, organic polymer materials, and composite materials. The importance of the bionic design in preoperative diagnosis models and customized bone scaffolds was also discussed, addressing both the bionic structure design (macro and micro structure and the bionic performance design (mechanical performance and biological performance. Materials and performance are the two main problems in the development of customized bone scaffolds. Bionic design is an effective way to solve these problems, which could improve the clinical application of bone scaffolds, by creating a balance between mechanical performance and biological performance.

  10. Optical design applications for enhanced illumination performance

    Science.gov (United States)

    Gilray, Carl; Lewin, Ian

    1995-08-01

    Nonimaging optical design techniques have been applied in the illumination industry for many years. Recently however, powerful software has been developed which allows accurate simulation and optimization of illumination devices. Wide experience has been obtained in using such design techniques for practical situations. These include automotive lighting where safety is of greatest importance, commercial lighting systems designed for energy efficiency, and numerous specialized applications. This presentation will discuss the performance requirements of a variety of illumination devices. It will further cover design methodology and present a variety of examples of practical applications for enhanced system performance.

  11. Software Performs Complex Design Analysis

    Science.gov (United States)

    2008-01-01

    Designers use computational fluid dynamics (CFD) to gain greater understanding of the fluid flow phenomena involved in components being designed. They also use finite element analysis (FEA) as a tool to help gain greater understanding of the structural response of components to loads, stresses and strains, and the prediction of failure modes. Automated CFD and FEA engineering design has centered on shape optimization, which has been hindered by two major problems: 1) inadequate shape parameterization algorithms, and 2) inadequate algorithms for CFD and FEA grid modification. Working with software engineers at Stennis Space Center, a NASA commercial partner, Optimal Solutions Software LLC, was able to utilize its revolutionary, one-of-a-kind arbitrary shape deformation (ASD) capability-a major advancement in solving these two aforementioned problems-to optimize the shapes of complex pipe components that transport highly sensitive fluids. The ASD technology solves the problem of inadequate shape parameterization algorithms by allowing the CFD designers to freely create their own shape parameters, therefore eliminating the restriction of only being able to use the computer-aided design (CAD) parameters. The problem of inadequate algorithms for CFD grid modification is solved by the fact that the new software performs a smooth volumetric deformation. This eliminates the extremely costly process of having to remesh the grid for every shape change desired. The program can perform a design change in a markedly reduced amount of time, a process that would traditionally involve the designer returning to the CAD model to reshape and then remesh the shapes, something that has been known to take hours, days-even weeks or months-depending upon the size of the model.

  12. The dark side of silicon energy efficient computing in the dark silicon era

    CERN Document Server

    Liljeberg, Pasi; Hemani, Ahmed; Jantsch, Axel; Tenhunen, Hannu

    2017-01-01

    This book presents the state-of-the art of one of the main concerns with microprocessors today, a phenomenon known as "dark silicon". Readers will learn how power constraints (both leakage and dynamic power) limit the extent to which large portions of a chip can be powered up at a given time, i.e. how much actual performance and functionality the microprocessor can provide. The authors describe their research toward the future of microprocessor development in the dark silicon era, covering a variety of important aspects of dark silicon-aware architectures including design, management, reliability, and test. Readers will benefit from specific recommendations for mitigating the dark silicon phenomenon, including energy-efficient, dedicated solutions and technologies to maximize the utilization and reliability of microprocessors. Enables readers to understand the dark silicon phenomenon and why it has emerged, including detailed analysis of its impacts; Presents state-of-the-art research, as well as tools for mi...

  13. Experience in the installation of a microprocessor system for controlling converter units of the Vyborg substation

    International Nuclear Information System (INIS)

    Gusakovskii, K. B.; Zmaznov, E. Yu.; Katantsev, S. V.; Mazurenko, A. K.; Mestergazi, V. A.; Prochan, G. G.; Funtikova, S. F.

    2006-01-01

    The experience in the installation of modern digital systems for controlling converter units at the Vyborg converter substation on the basis of advanced microprocessor devices is considered. It is shown that debugging of a control and protection system on mathematical and physical models does not guarantee optimum control of actual converter devices. Examples of advancing the control and protection system are described, the necessity for which has become obvious in tests of actual equipment. Comparison of oscillograms of processes before optimization of the control system and after its optimization and adjustment shows that the digital control system makes it possible to improve substantially the algorithms of control and protection in the short term and without changing the hardware component

  14. LEARNING STYLES AND STUDENTS’ PERFORMANCE IN DESIGN PROBLEM SOLVING

    Directory of Open Access Journals (Sweden)

    Elçin Tezel

    2010-07-01

    Full Text Available Design curricula and all core design studio courses are prepared for performance attainment by giving theoretical and professional training. However students’ performance may be affected by both the constraints set on a design problem, and their learning styles. This study explores the performance of interior architectural students in relation to their learning styles (as proposed by Kolb’s Experiential Learning Theory, and different types of constraints set on design problems. Design performance, measured as conceptual development, form and spatial configuration, structural innovation and ergonomics, and craftsmanship, was found to change throughout the two bipolar continuum of the learning cycle with regard to two design conditions characterized by different types of constraint use.

  15. Preliminary design and off-design performance analysis of an Organic Rankine Cycle for geothermal sources

    International Nuclear Information System (INIS)

    Hu, Dongshuai; Li, Saili; Zheng, Ya; Wang, Jiangfeng; Dai, Yiping

    2015-01-01

    Highlights: • A method for preliminary design and performance prediction is established. • Preliminary data of radial inflow turbine and plate heat exchanger are obtained. • Off-design performance curves of critical components are researched. • Performance maps in sliding pressure operation are illustrated. - Abstract: Geothermal fluid of 90 °C and 10 kg/s can be exploited together with oil in Huabei Oilfield of China. Organic Rankine Cycle is regarded as a reasonable method to utilize these geothermal sources. This study conducts a detailed design and off-design performance analysis based on the preliminary design of turbines and heat exchangers. The radial inflow turbine and plate heat exchanger are selected in this paper. Sliding pressure operation is applied in the simulation and three parameters are considered: geothermal fluid mass flow rate, geothermal fluid temperature and condensing pressure. The results indicate that in all considered conditions the designed radial inflow turbine has smooth off-design performance and no choke or supersonic flow are found at the nozzle and rotor exit. The lager geothermal fluid mass flow rate, the higher geothermal fluid temperature and the lower condensing pressure contribute to the increase of cycle efficiency and net power. Performance maps are illustrated to make system meet different load requirements especially when the geothermal fluid temperature and condensing pressure deviate from the design condition. This model can be used to provide basic data for future detailed design, and predict off-design performance in the initial design phase

  16. Development of a hard microcontroller

    International Nuclear Information System (INIS)

    Measel, P.R.; Sivo, L.L.; Quilitz, W.E.; Davidson, T.K.

    1976-01-01

    The applicability of commercially available microprocessors to certain systems requiring radiation survival was assessed. A microcontroller was designed and built to perform a monitor and control function of military operational ground equipment, and demonstrated to exceed the radiation hardness goal. The preparation of the microcontroller module required hardware and software design, selection of LSI and other piece part types, development of piece part and module electrical and radiation test techniques, and the performance of radiation tests on the LSI piece parts and the completed module. The microcontroller has a 16-bit central processor unit, a 4096 word read only memory, and a 256 word read-write memory. The module has circumvention circuitry, including a PIN diode radiation detector. The processor device used was the MMI 6701 T 2 L Schottky bipolar 4-bit slice. Electrical exerciser circuits were developed for in-situ electrical testing of microprocessors and memories during irradiation. A test program was developed for a Terradyne J283 microcircuit tester for more complete electrical characterization of the MMI 6701 microprocessor. A simple self-test algorithm was used in the microcontroller for performance testing during irradiation. For the operational demonstration of the microcontroller a TI 960A minicomputer was used to provide the required complex inputs to the module and verify the module outputs

  17. RTOD- RADIAL TURBINE OFF-DESIGN PERFORMANCE ANALYSIS

    Science.gov (United States)

    Glassman, A. J.

    1994-01-01

    The RTOD program was developed to accurately predict radial turbine off-design performance. The radial turbine has been used extensively in automotive turbochargers and aircraft auxiliary power units. It is now being given serious consideration for primary powerplant applications. In applications where the turbine will operate over a wide range of power settings, accurate off-design performance prediction is essential for a successful design. RTOD predictions have already illustrated a potential improvement in off-design performance offered by rotor back-sweep for high-work-factor radial turbines. RTOD can be used to analyze other potential performance enhancing design features. RTOD predicts the performance of a radial turbine (with or without rotor blade sweep) as a function of pressure ratio, speed, and stator setting. The program models the flow with the following: 1) stator viscous and trailing edge losses; 2) a vaneless space loss between the stator and the rotor; and 3) rotor incidence, viscous, trailing-edge, clearance, and disk friction losses. The stator and rotor viscous losses each represent the combined effects of profile, endwall, and secondary flow losses. The stator inlet and exit and the rotor inlet flows are modeled by a mean-line analysis, but a sector analysis is used at the rotor exit. The leakage flow through the clearance gap in a pivoting stator is also considered. User input includes gas properties, turbine geometry, and the stator and rotor viscous losses at a reference performance point. RTOD output includes predicted turbine performance over a specified operating range and any user selected flow parameters. The RTOD program is written in FORTRAN IV for batch execution and has been implemented on an IBM 370 series computer with a central memory requirement of approximately 100K of 8 bit bytes. The RTOD program was developed in 1983.

  18. Architectural design and energy performance; Conception architecturale et performance energetique

    Energy Technology Data Exchange (ETDEWEB)

    Beaud, Ph. [Agence de l' Environnement et de la Maitrise de l' Energie, (ADEME), 06 - Valbonne (France); Pouget, A. [Bureau Etude Thermique, 75 - Paris (France); Sesolis, B. [TRIBU, 75 - Paris (France)] [and others

    2000-07-01

    This day was organized around the energy performance of the architecture in three parts. A first time dealt with the design of new buildings and private houses. Simulation tools for the energy optimization and practice of design are discussed. The second part was devoted to the new 2000 regulation with an open discussion on the regulatory costs. The last part forecasted the evolution until 2015 taking into account the french program of fight against the greenhouse effect, the limitation of the air conditioning consumption and the definition of a quality label concerning the energy performances. (A.L.B.)

  19. Aerodynamic Optimization Design of a Multistage Centrifugal Steam Turbine and Its Off-Design Performance Analysis

    Directory of Open Access Journals (Sweden)

    Hui Li

    2017-01-01

    Full Text Available Centrifugal turbine which has less land occupation, simple structure, and high aerodynamic efficiency is suitable to be used as small to medium size steam turbines or waste heat recovery plant. In this paper, one-dimensional design of a multistage centrifugal steam turbine was performed by using in-house one-dimensional aerodynamic design program. In addition, three-dimensional numerical simulation was also performed in order to analyze design and off-design aerodynamic performance of the proposed centrifugal steam turbine. The results exhibit reasonable flow field and smooth streamline; the aerodynamic performance of the designed turbine meets our initial expectations. These results indicate that the one-dimensional aerodynamic design program is reliable and effective. The off-design aerodynamic performance of centrifugal steam turbine was analyzed, and the results show that the mass flow increases with the decrease of the pressure ratio at a constant speed, until the critical mass flow is reached. The efficiency curve with the pressure ratio has an optimum efficiency point. And the pressure ratio of the optimum efficiency agrees well with that of the one-dimensional design. The shaft power decreases as the pressure ratio increases at a constant speed. Overall, the centrifugal turbine has a wide range and good off-design aerodynamic performance.

  20. Passive Solar Construction--Design and Performance.

    Science.gov (United States)

    Conservation and Renewable Energy Inquiry and Referral Service (DOE), Silver Spring, MD.

    Presented is a list of books and reports intended to serve as technical sources of information for the building professional interested in energy conservation. These publications are grouped under these headings: (1) energy-conserving building design; (2) passive systems/design; (3) passive systems/performance; and (4) proceedings (of the American…

  1. Embedded Design Research of Iris Information Acquisition System

    Directory of Open Access Journals (Sweden)

    Huiyan Xu

    2014-09-01

    Full Text Available In view of the limitation of traditional identification, it is easy to lose and copy keys, cards or ID cards, and it is easy to forget the password, so we designed an embedded application system based on the iris identification technology, which can realize the functions of gathering, inputting, and registering the iris information and identification. The hardware circuit was designed by using advanced RISC machines (ARM embedded microprocessor as the core. The iris sensor was used to gather the iris information, and the development of software was accomplished with the embedded OS Windows CE. The system can be used on the company entrance guard system, customs security of airport and criminal identification.

  2. ANL small-sample calorimeter system design and operation

    International Nuclear Information System (INIS)

    Roche, C.T.; Perry, R.B.; Lewis, R.N.; Jung, E.A.; Haumann, J.R.

    1978-07-01

    The Small-Sample Calorimetric System is a portable instrument designed to measure the thermal power produced by radioactive decay of plutonium-containing fuels. The small-sample calorimeter is capable of measuring samples producing power up to 32 milliwatts at a rate of one sample every 20 min. The instrument is contained in two packages: a data-acquisition module consisting of a microprocessor with an 8K-byte nonvolatile memory, and a measurement module consisting of the calorimeter and a sample preheater. The total weight of the system is 18 kg

  3. Primer on hardware prefetching

    CERN Document Server

    Falsafi, Babak

    2014-01-01

    Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the "Memory Wall."To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, whi

  4. High Performance Computing in Science and Engineering '02 : Transactions of the High Performance Computing Center

    CERN Document Server

    Jäger, Willi

    2003-01-01

    This book presents the state-of-the-art in modeling and simulation on supercomputers. Leading German research groups present their results achieved on high-end systems of the High Performance Computing Center Stuttgart (HLRS) for the year 2002. Reports cover all fields of supercomputing simulation ranging from computational fluid dynamics to computer science. Special emphasis is given to industrially relevant applications. Moreover, by presenting results for both vector sytems and micro-processor based systems the book allows to compare performance levels and usability of a variety of supercomputer architectures. It therefore becomes an indispensable guidebook to assess the impact of the Japanese Earth Simulator project on supercomputing in the years to come.

  5. Aerodynamic Optimization Design of a Multistage Centrifugal Steam Turbine and Its Off-Design Performance Analysis

    OpenAIRE

    Hui Li; Dian-Gui Huang

    2017-01-01

    Centrifugal turbine which has less land occupation, simple structure, and high aerodynamic efficiency is suitable to be used as small to medium size steam turbines or waste heat recovery plant. In this paper, one-dimensional design of a multistage centrifugal steam turbine was performed by using in-house one-dimensional aerodynamic design program. In addition, three-dimensional numerical simulation was also performed in order to analyze design and off-design aerodynamic performance of the pro...

  6. Performance Design as Education of Desire

    DEFF Research Database (Denmark)

    Pedersen, Michael Haldrup; Petersen, Franziska Bork

    a discipline. Such a utopian PD would be an institution without borders. A mobilized and mobilizing institution enjoying an unruly, symbiotic or even parasitic metabolism with academic faculties (art, Geisteswissenschaft, technology, science) and sites for performance (bodies, home, workplace, city, planet......Confronted with the ubiquitous presence of preprogramed desires we propose Performance Design as a utopian institution for the education of desire. The utopian education of desire offers a potential and systematic creation of spaces that enable us “to imagine wanting something else, something...... qualitatively different” (Levitas 2013: 113). PD is uniquely suited to such an educational task, because it can function as a framework for not only designing alternative ways of being through affective interventions and estrangements, but also playing them out in performance. A modus operandi rather than...

  7. Flexible nanoscale high-performance FinFETs

    KAUST Repository

    Sevilla, Galo T.

    2014-10-28

    With the emergence of the Internet of Things (IoT), flexible high-performance nanoscale electronics are more desired. At the moment, FinFET is the most advanced transistor architecture used in the state-of-the-art microprocessors. Therefore, we show a soft-etch based substrate thinning process to transform silicon-on-insulator (SOI) based nanoscale FinFET into flexible FinFET and then conduct comprehensive electrical characterization under various bending conditions to understand its electrical performance. Our study shows that back-etch based substrate thinning process is gentler than traditional abrasive back-grinding process; it can attain ultraflexibility and the electrical characteristics of the flexible nanoscale FinFET show no performance degradation compared to its rigid bulk counterpart indicating its readiness to be used for flexible high-performance electronics.

  8. Designing Second Language Performance Assessments. Technical Report.

    Science.gov (United States)

    Norris, John M.; Brown, James Dean; Hudson, Thom; Yoshioka, Jim

    This technical report focuses on the decision-making potential provided by second language performance assessments. First, performance assessment is situated within the broader discussion of alternatives in language assessment and in educational assessment in general. Next, issues in performance assessment design, implementation, reliability, and…

  9. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  10. KIPT accelerator-driven system design and performance

    International Nuclear Information System (INIS)

    Gohar, Y.; Bolshinsky, I.; Karnaukhov, I.

    2015-01-01

    Argonne National Laboratory (ANL) of the US is collaborating with the Kharkov Institute of Physics and Technology (KIPT) of Ukraine to develop and construct a neutron source facility. The facility is planned to produce medical isotopes, train young nuclear professionals, support Ukraine's nuclear industry and provide capability to perform reactor physics, material research, and basic science experiments. It consists of a subcritical assembly with low-enriched uranium fuel driven with an electron accelerator. The target design utilises tungsten or natural uranium for neutron production through photonuclear reactions from the Bremsstrahlung radiation generated by 100-MeV electrons. The accelerator electron beam power is 100 KW. The neutron source intensity, spectrum, and spatial distribution have been studied as a function of the electron beam parameters to maximise the neutron yield and satisfy different engineering requirements. Physics, thermal-hydraulics, and thermal-stress analyses were performed and iterated to maximise the neutron source strength and to minimise the maximum temperature and the thermal stress in the target materials. The subcritical assembly is designed to obtain the highest possible neutron flux intensity with an effective neutron multiplication factor of <0.98. Different fuel and reflector materials are considered for the subcritical assembly design. The mechanical design of the facility has been developed to maximise its utility and minimise the time for replacing the target, fuel, and irradiation cassettes by using simple and efficient procedures. Shielding analyses were performed to define the dose map around the facility during operation as a function of the heavy concrete shield thickness. Safety, reliability and environmental considerations are included in the facility design. The facility is configured to accommodate future design upgrades and new missions. In addition, it has unique features relative to the other international

  11. Real-time embedded systems design principles and engineering practices

    CERN Document Server

    Fan, Xiaocong

    2015-01-01

    This book integrates new ideas and topics from real time systems, embedded systems, and software engineering to give a complete picture of the whole process of developing software for real-time embedded applications. You will not only gain a thorough understanding of concepts related to microprocessors, interrupts, and system boot process, appreciating the importance of real-time modeling and scheduling, but you will also learn software engineering practices such as model documentation, model analysis, design patterns, and standard conformance. This book is split into four parts to help you

  12. Conceptual Designs for the Performance Improvement of APR1400 SIT and Preliminary Performance Evaluation

    International Nuclear Information System (INIS)

    Chu, In-Cheol; Kwon, Tae-Soon; Song, Chul-Hwa

    2008-01-01

    Some evolutionary type PWRs such as APR1400 and APWR adopt advanced safety injection tank (SIT). The SIT of APR1400 has a fluidic device (FD) which passively controls ECC water injection flow rate into reactor coolant system during refill and reflood phases of LB-LOCA (i.e., a high injection flow rate during the refill phase and a low injection flow rate during the reflood phase). The benefit of the FD is the elimination of the function of low pressure safety injection pump from the safety injection system. The flow controlling performance of the APR1400 FD was evaluated using a prototypical full-scale test facility, called VAPER (Valve Performance Evaluation Rig). Even though the performance of the APR1400 FD satisfied major design and licensing requirements, further improvement of the performance is expected such as the extension of total injection period, the delay of nitrogen gas discharge. Several conceptual designs have been being drawn out in order to improve the performance of the APR1400 SIT. The performance of some designs was evaluated using a small scale SIT test rig. The present paper introduces some of the conceptual designs and shows the performance evaluation experimental results

  13. Testing and Performance Validation of a Shielded Waste Segregation and Clearance Monitor Designed for the Measurement of Low Level Waste-13043

    International Nuclear Information System (INIS)

    Mason, John A.; Burke, Kevin J.; Towner, Antony C.N.; Beaven, Graham; Spence, Robert

    2013-01-01

    This paper describes the development, testing and validation of a shielded waste segregation and clearance monitor designed for the measurement of low-density low-level waste (LLW). The monitor is made of a measurement chamber surrounded by detectors and a shielded outer frame. The shielded chamber consists of a steel frame, which contains typically 1.5 inches (3.81 cm) of lead and 0.5 inches (1.27 cm) of steel shielding. Inside the shielding are plastic scintillator panels, which serve as gross gamma ray detectors. The detector panels, with embedded photomultipliers, completely surround the internal measurement chamber on all 6 sides. Care has been taken to distribute the plastic scintillator detectors in order to optimise both the efficiency for gamma ray detection and at the same time achieve a volumetric sensitivity, which is as uniform as possible. A common high voltage power supply provides the bias voltage for each of the six photomultipliers. The voltage signals arising from the detectors and photomultipliers are amplified by six sensitive amplifiers. Each amplifier incorporates a single channel analyser with both upper and lower thresholds and the digitised counts from each detector are recorded on six scalars. Operation of the device is by means of a microprocessor from which the scalars are controlled. An internal load cell linked to the microprocessor determines the weight of the waste object, and this information is used to calculate the specific activity of the waste. The monitor makes background measurements when the shielded door is closed and a sample, usually a bag of low-density waste, is not present in the measurement chamber. Measurements of the minimum detectable activity (MDA) of an earlier large volume prototype instrument are reported as part of the development of the Waste Segregation and Clearance Monitor (WSCM) described in the paper. For the optimised WSCM a detection efficiency of greater than 32% was measured using a small Cs-137

  14. Monolithic silicon photonics in a sub-100nm SOI CMOS microprocessor foundry: progress from devices to systems

    Science.gov (United States)

    Popović, Miloš A.; Wade, Mark T.; Orcutt, Jason S.; Shainline, Jeffrey M.; Sun, Chen; Georgas, Michael; Moss, Benjamin; Kumar, Rajesh; Alloatti, Luca; Pavanello, Fabio; Chen, Yu-Hsin; Nammari, Kareem; Notaros, Jelena; Atabaki, Amir; Leu, Jonathan; Stojanović, Vladimir; Ram, Rajeev J.

    2015-02-01

    We review recent progress of an effort led by the Stojanović (UC Berkeley), Ram (MIT) and Popović (CU Boulder) research groups to enable the design of photonic devices, and complete on-chip electro-optic systems and interfaces, directly in standard microelectronics CMOS processes in a microprocessor foundry, with no in-foundry process modifications. This approach allows tight and large-scale monolithic integration of silicon photonics with state-of-the-art (sub-100nm-node) microelectronics, here a 45nm SOI CMOS process. It enables natural scale-up to manufacturing, and rapid advances in device design due to process repeatability. The initial driver application was addressing the processor-to-memory communication energy bottleneck. Device results include 5Gbps modulators based on an interleaved junction that take advantage of the high resolution of the sub-100nm CMOS process. We demonstrate operation at 5fJ/bit with 1.5dB insertion loss and 8dB extinction ratio. We also demonstrate the first infrared detectors in a zero-change CMOS process, using absorption in transistor source/drain SiGe stressors. Subsystems described include the first monolithically integrated electronic-photonic transmitter on chip (modulator+driver) with 20-70fJ/bit wall plug energy/bit (2-3.5Gbps), to our knowledge the lowest transmitter energy demonstrated to date. We also demonstrate native-process infrared receivers at 220fJ/bit (5Gbps). These are encouraging signs for the prospects of monolithic electronics-photonics integration. Beyond processor-to-memory interconnects, our approach to photonics as a "More-than- Moore" technology inside advanced CMOS promises to enable VLSI electronic-photonic chip platforms tailored to a vast array of emerging applications, from optical and acoustic sensing, high-speed signal processing, RF and optical metrology and clocks, through to analog computation and quantum technology.

  15. Transient Performance Improvement Circuit (TPIC)s for DC-DC converter applications

    Science.gov (United States)

    Lim, Sungkeun

    Gordon Moore famously predicted the exponential increase in transistor integration and computing power that has been witnessed in recent decades [1]. In the near future, it is expected that more than one billion transistors will be integrated per chip, and advanced microprocessors will require clock speeds in excess of several GHz. The increasing number of transistors and high clock speeds will necessitate the consumption of more power. By 2014, it is expected that the maximum power consumption of the microprocessor will reach approximately 150W, and the maximum load current will be around 150A. Today's trend in power and thermal management is to reduce supply voltage as low as possible to reduce delivered power. It is anticipated that the Intel cores will operate on 0.8V of supply voltage by 2014 [2]. A significant challenge in Voltage Regulator Module (VRM) development for next generation microprocessors is to regulate the supply voltage within a certain tolerance band during high slew rate load transitions, since the required supply voltage tolerance band will be much narrower than the current requirement. If VR output impedance is maintained at a constant value from DC to high frequency, large output voltage spikes can be avoided during load cur- rent transients. Based on this, the Adaptive Voltage Position (AVP) concept was developed to achieve constant VR output impedance to improve transient response performance [3]. However, the VR output impedance can not be made constant over the entire frequency range with AVP design, because the AVP design makes the VR output impedance constant only at low frequencies. To make the output impedance constant at high frequencies, many bulk capacitors and ceramic capacitors are required. The tight supply voltage tolerance for the next generation of microprocessors during high slew rate load transitions requires fast transient response power supplies. A VRM can not follow the high slew rate load current transients, because

  16. ExaSAT: An exascale co-design tool for performance modeling

    International Nuclear Information System (INIS)

    Unat, Didem; Chan, Cy; Zhang, Weiqun; Williams, Samuel; Bachan, John

    2015-01-01

    One of the emerging challenges to designing HPC systems is understanding and projecting the requirements of exascale applications. In order to determine the performance consequences of different hardware designs, analytic models are essential because they can provide fast feedback to the co-design centers and chip designers without costly simulations. However, current attempts to analytically model program performance typically rely on the user manually specifying a performance model. Here we introduce the ExaSAT framework that automates the extraction of parameterized performance models directly from source code using compiler analysis. The parameterized analytic model enables quantitative evaluation of a broad range of hardware design trade-offs and software optimizations on a variety of different performance metrics, with a primary focus on data movement as a metric. Finally, we demonstrate the ExaSAT framework’s ability to perform deep code analysis of a proxy application from the Department of Energy Combustion Co-design Center to illustrate its value to the exascale co-design process. ExaSAT analysis provides insights into the hardware and software trade-offs and lays the groundwork for exploring a more targeted set of design points using cycle-accurate architectural simulators.

  17. System design and installation for RS600 programmable control system for solar heating and cooling

    Science.gov (United States)

    1978-01-01

    Procedures for installing, operating, and maintaining a programmable control system which utilizes a F8 microprocessor to perform all timing, control, and calculation functions in order to customize system performance to meet individual requirements for solar heating, combined heating and cooling, and/or hot water systems are described. The manual discusses user configuration and options, displays, theory of operation, trouble-shooting procedures, and warranty and assistance. Wiring lists, parts lists, drawings, and diagrams are included.

  18. The Curvilinear Association between Performance Measurement System Design and Strategic Performance

    DEFF Research Database (Denmark)

    Schneider, Melanie L.; Mahlendorf, Matthias D.; Schäffer, Utz

    This paper reconciles prior research regarding beneficial and detrimental effects of performance measurement system (PMS) design on performance by arguing for a curvilinear association. By taking the too-much-of-a-good-thing effect as a starting point, we challenge the assumption of a linear...

  19. Performance of a solar chimney by varying design parameters

    CSIR Research Space (South Africa)

    Kumirai, T

    2015-08-01

    Full Text Available the design of solar chimneys to ensure optimal performance. The purpose of this chapter is to discuss the performance of an example solar chimney by varying the design parameters and examining their effects on the interior ventilation performance... chimney by varying design parameters Tichaona Kumirai, Researcher, Built Environment CSIR Jan-Hendrik Grobler, DPSS CSIR Dr D.C.U. Conradie, Senior researcher, Built Environment CSIR 1 Introduction Trombe walls and solar chimneys are not widely...

  20. Radiation Tolerant Embedded Memory

    National Research Council Canada - National Science Library

    Smith, Brian

    2003-01-01

    ... event effects, and will scale to smaller geometries to provide the same performance. we then designed arrays of that memory to build up blocks to be used in complex Cool-RAD(tm) parts such as microprocessors and digital signal processors.

  1. High performance APCS conceptual design and evaluation scoping study

    International Nuclear Information System (INIS)

    Soelberg, N.; Liekhus, K.; Chambers, A.; Anderson, G.

    1998-02-01

    This Air Pollution Control System (APCS) Conceptual Design and Evaluation study was conducted to evaluate a high-performance (APC) system for minimizing air emissions from mixed waste thermal treatment systems. Seven variations of high-performance APCS designs were conceptualized using several design objectives. One of the system designs was selected for detailed process simulation using ASPEN PLUS to determine material and energy balances and evaluate performance. Installed system capital costs were also estimated. Sensitivity studies were conducted to evaluate the incremental cost and benefit of added carbon adsorber beds for mercury control, specific catalytic reduction for NO x control, and offgas retention tanks for holding the offgas until sample analysis is conducted to verify that the offgas meets emission limits. Results show that the high-performance dry-wet APCS can easily meet all expected emission limits except for possibly mercury. The capability to achieve high levels of mercury control (potentially necessary for thermally treating some DOE mixed streams) could not be validated using current performance data for mercury control technologies. The engineering approach and ASPEN PLUS modeling tool developed and used in this study identified APC equipment and system performance, size, cost, and other issues that are not yet resolved. These issues need to be addressed in feasibility studies and conceptual designs for new facilities or for determining how to modify existing facilities to meet expected emission limits. The ASPEN PLUS process simulation with current and refined input assumptions and calculations can be used to provide system performance information for decision-making, identifying best options, estimating costs, reducing the potential for emission violations, providing information needed for waste flow analysis, incorporating new APCS technologies in existing designs, or performing facility design and permitting activities

  2. Enhancing human performance in ship operations by modifying global design factors at the design stage

    International Nuclear Information System (INIS)

    Montewka, Jakub; Goerlandt, Floris; Innes-Jones, Gemma; Owen, Douglas; Hifi, Yasmine; Puisa, Romanas

    2017-01-01

    Usually the improvements of human performance in the course of ship design process is carried out by modifying local ergonomics, like electronic visualisation and information display systems on the bridge or in the engine control room, stair or hatch covers design. However, the effect of global design factors (GDFs), such as ship motion, whole body vibration and noise, on human performance has not been given attention before. Such knowledge would allow the improvements of human performance by effective design modification on very early stage of ship design process. Therefore, in this paper we introduce probabilistic models linking the effect of GDFs with the human performance suitable for ship design process. As a theoretical basis for modelling human performance the concept of Attention Management is utilized, which combines the theories described by Dynamic Adaptability Model, Cognitive Control Model and Malleable Attentional Resources Theory. Since the analysed field is characterised by a high degree of uncertainty, we adopt a specific modelling technique along with a validation framework that allows uncertainty treatment and helps the potential end-users to gain confidence in the models and the results that they yield. The proposed models are developed with the use Bayesian Belief Networks, which allows systematic translation of the available background knowledge into a coherent network and the uncertainty assessment and treatment. The obtained results are promising as the models are responsive to changes in the GDF nodes as expected. The models may be used as intended by naval architects and vessel designers, to facilitate risk-based ship design. - Highlights: • Models linking the effect of GDFs with the human performance are established. • Three global design factors (GDFs) are considered: ship motion, body vibration, noise. • Attention Management concept as theoretical base is modelled with Bayesian Networks. • Two models are developed that can be

  3. Comparative performance of conventional OPC concrete and HPC designed by densified mixture design algorithm

    Science.gov (United States)

    Huynh, Trong-Phuoc; Hwang, Chao-Lung; Yang, Shu-Ti

    2017-12-01

    This experimental study evaluated the performance of normal ordinary Portland cement (OPC) concrete and high-performance concrete (HPC) that were designed by the conventional method (ACI) and densified mixture design algorithm (DMDA) method, respectively. Engineering properties and durability performance of both the OPC and HPC samples were studied using the tests of workability, compressive strength, water absorption, ultrasonic pulse velocity, and electrical surface resistivity. Test results show that the HPC performed good fresh property and further showed better performance in terms of strength and durability as compared to the OPC.

  4. Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

    Science.gov (United States)

    2015-03-10

    efficiency of on-chip storage units implemented with superconductor Reciprocal Quantum Logic (RQL) using our RQL VHDL cell library tuned to the MIT...processor prototype implemented with the AIST/ISTEC 10 kA/cm sq. fabrication process. Our team has developed complete logical and physical designs of five...of key components of a 30 GHz 16-bit RSFQ processor prototype implemented with the AIST/ISTEC 10 kA/cm sq. fabrication process. Our team has

  5. New trends in designing NPP control boards

    International Nuclear Information System (INIS)

    Kondrat'ev, V.V.

    1981-01-01

    A short analytical summary of the latest developments and future trends in designing NPP control boards is given. The designs of the Westinghause and the Hynkley-Point NPP control boards are described in detail. The essence of the advanced control board concept consists , firstly, in expanded use of computer-controlled displays for the sake of reducing the content of unimportant information presented to an operator, and, secondary, in better account of human possibilities to convert the NPP operation information into a more suitable form. An enlarged use of the direct digital reactor control utilizing microprocessors is expected. Besides, the employment of full-scale control board mock-ups and information desks as well as testing newly-developed control boards at computer reactor simulators are concluded to be used at all-growing rate [ru

  6. Performance Driven Design Systems In Practice

    OpenAIRE

    Joyce, Sam

    2015-01-01

    This thesis is concerned with the application of computation in the context of professional architectural practice and specifically towards defining complex buildingsthat are highly integrated with respect to design and engineering performance.The thesis represents applied research undertaken whilst in practice at Foster + Partners.It reviews the current state of the art of computational design techniques to quickly but flexibly model and analyse building options. The application of parametri...

  7. Business School's Performance Management System Standards Design

    Science.gov (United States)

    Azis, Anton Mulyono; Simatupang, Togar M.; Wibisono, Dermawan; Basri, Mursyid Hasan

    2014-01-01

    This paper aims to compare various Performance Management Systems (PMS) for business school in order to find the strengths of each standard as inputs to design new model of PMS. There are many critical aspects and gaps notified for new model to improve performance and even recognized that self evaluation performance management is not well…

  8. A high performance electrometer amplifier of hybrid design

    International Nuclear Information System (INIS)

    Rao, N.V.; Nazare, C.K.

    1979-01-01

    A high performance, reliable, electrometer amplifier of hybrid design for low current measurements in mass spectrometers has been developed. The short term instability with a 5 x 10 11 ohms input resistor is less than 1 x 10sup(-15) Amp. The drift is better than 1 mV/hour. The design steps are illustrated with a typical amplifier performance details. (auth.)

  9. Standards and the design of the Advanced Photon Source control system

    International Nuclear Information System (INIS)

    McDowell, W.P.; Knott, M.J.; Lenkszus, F.R.; Kraimer, M.R.; Daly, R.T.; Arnold, N.D.; Anderson, M.D.; Anderson, J.B.; Zieman, R.C.; Cha, Ben-Chin K.; Vong, F.C.; Nawrocki, G.J.; Gunderson, G.R.; Karonis, N.T.; Winans, J.R.

    1991-01-01

    The Advanced Photon Source (APS), now under construction at Argonne National Laboratory is a 7 GeV positron storage ring dedicated to research facilities using synchrotron radiation. This ring, along with its injection accelerators is to be controlled and monitored with a single, flexible, and expandable control system. In the conceptual stage the control system design group faced the challenges that face all control system designers: to force the machine designers to quantify and codify the system requirements, to protect the investment in hardware and software from rapid obsolescence, and to find methods of quickly incorporating new generations of equipment and replace of obsolete equipment without disrupting the exiting system. To solve these and related problems, the APS control system group made an early resolution to use standards in the design of the system. This paper will cover the present status of the APS control system as well as discuss the design decisions which led us to use industrial standards and collaborations with other laboratories whenever possible to develop a control system. It will explain the APS control system and illustrate how the use of standards has allowed APS to design a control system whose implementation addresses these issues. The system will use high performance graphic workstations using an X-Windows Graphical User Interface at the operator interface level. It connects to VME-based microprocessors at the field level using TCP/IP protocols over high performance networks. This strategy assures the flexibility and expansibility of the control system. A defined interface between the system components will allow the system to evolve with the direct addition of future, improved equipment and new capabilities

  10. FFTF fuel pin design bases and performance

    International Nuclear Information System (INIS)

    Cox, C.M.; Hanson, J.E.; Roake, W.E.; Slember, R.J.; Weber, C.E.; Millunzi, A.C.

    1975-04-01

    The FFTF fuel pin was conservatively designed to meet thermal and structural performance requirements in the categories normal operation, upset events, emergency events, and hypothetical, faulted events. The fuel pin operating limits consistent with these requirements were developed from a strong fuel pin irradiation testing program scoped to define the performance capability under relevant steady state and transient conditions. Comparison of the results of the irradiation testing program with design requirements indicates that the FFTF fuel pin can exceed its goal burnup of 80,000 MWd/MTM. (U.S.)

  11. An integrated high performance fastbus slave interface

    International Nuclear Information System (INIS)

    Christiansen, J.; Ljuslin, C.

    1992-01-01

    A high performance Fastbus slave interface ASIC is presented. The Fastbus slave integrated circuit (FASIC) is a programmable device, enabling its direct use in many different applications. The FASIC acts as an interface between Fastbus and a 'standard' processor/memory bus. It can work stand-alone or together with a microprocessor. A set of address mapping windows can map Fastbus addresses to convenient memory addresses and at the same time act as address decoding logic. Data rates of 100 MBytes/s to Fastbus can be obtained using an internal FIFO buffer in the FASIC. (orig.)

  12. RISC Processors and High Performance Computing

    Science.gov (United States)

    Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

    1995-01-01

    This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

  13. Safety performance of preliminary KALIMER conceptual design

    Energy Technology Data Exchange (ETDEWEB)

    Hahn Dohee; Kim Kyoungdoo; Kwon Youngmin; Chang Wonpyo; Suk Soodong [Korea atomic Energy Resarch Inst., Taejon (Korea)

    1999-07-01

    The Korea Atomic Energy Research Institute (KAERI) is developing KALIMER (Korea Advanced Liquid Metal Reactor), which is a sodium cooled, 150 MWe pool-type reactor. The safety design of KALIMER emphasizes accident prevention by using passive processes, which can be accomplished by the safety design objectives including the utilization of inherent safety features. In order to assess the effectiveness of the inherent safety features in achieving the safety design objectives, a preliminary evaluation of ATWS performance for the KALIMER design has been performed with SSC-K code, which is a modified version of SSC-L code. KAERI's modification of the code includes development of reactivity feedback models for the core and a pool model for KALIMER reactor vessel. This paper describes the models for control rod driveline expansion, gas expansion module and the thermal hydraulic model for reactor pool and the results of preliminary analyses for unprotected loss of flow and loss o heat sink. (author)

  14. Safety performance of preliminary KALIMER conceptual design

    International Nuclear Information System (INIS)

    Hahn Dohee; Kim Kyoungdoo; Kwon Youngmin; Chang Wonpyo; Suk Soodong

    1999-01-01

    The Korea Atomic Energy Research Institute (KAERI) is developing KALIMER (Korea Advanced Liquid Metal Reactor), which is a sodium cooled, 150 MWe pool-type reactor. The safety design of KALIMER emphasizes accident prevention by using passive processes, which can be accomplished by the safety design objectives including the utilization of inherent safety features. In order to assess the effectiveness of the inherent safety features in achieving the safety design objectives, a preliminary evaluation of ATWS performance for the KALIMER design has been performed with SSC-K code, which is a modified version of SSC-L code. KAERI's modification of the code includes development of reactivity feedback models for the core and a pool model for KALIMER reactor vessel. This paper describes the models for control rod driveline expansion, gas expansion module and the thermal hydraulic model for reactor pool and the results of preliminary analyses for unprotected loss of flow and loss o heat sink. (author)

  15. Total System Performance Assessment: Enhanced Design Alternative V

    International Nuclear Information System (INIS)

    N. Erb; S. Miller; V. Vallikat

    1999-01-01

    This calculation documents the total system performance assessment modeling of Enhanced Design Analysis (EDA) V. EDA V is based on the TSPA-VA base design which has been modified with higher thermal loading, a quartz sand invert, and line loading with 21 PWR waste packages that have 2-cm thick titanium grade 7 corrosion resistance material (CRM) drip shields placed over dual-layer waste packages composed of 'inside out' VA reference material (CRWMS M and O 1999a). This document details the changes and assumptions made to the VA reference Performance Assessment Model (CRWMS M and O 1998a) to incorporate the design changes detailed for EDA V. The performance measure for this evaluation is expected value dose-rate history. Time histories of dose rate are presented for EDA V and a Defense in Depth (DID) analysis base on EDA V. Additional details concerning the Enhanced Design Alternative II are provided in the 'LADS 3-12 Requests' interoffice correspondence (CRWMS M and O 1999a)

  16. Nova chain design and performance

    International Nuclear Information System (INIS)

    Simmons, W.W.; Glaze, J.A.; Trenholme, J.B.; Hagen, W.F.

    1980-01-01

    During the past year design of the Nova laser has undergone significant change as a result of developments in our laser glass and optical coating evaluation programs. Two notable aspects of the glass development program deserve emphasis. First, vendor qualification for production of fluorophosphate laser glass is progressing satisfactorily. There is a reasonable expectation that vendors can meet fluorophosphate glass specifications within Nova schedule constraints. Secondly, recent gain saturation measurements have shown that the saturation fluence of the fluorophosphate glass is larger than previously supposed (approx. 5.5 J/cm 2 ) and in fact is somewhat larger than Shiva silicate glasses. Hence, performance of Nova for pulses in the 3 ns and longer range should be satisfactory. For pulses in the 1 ns regime, of course, the fluorophosphate chain will have superior performance to that of silicate because of its low nonlinear index of refraction (approx. 30% that of silicate). These and other considerations have led us to choose a chain design based upon the use of fluorophosphate glass in our amplifiers

  17. Design aspects of PHWR for improved performance

    International Nuclear Information System (INIS)

    Das, M.

    1989-01-01

    The PHWR fuel bundle is elegantly simple in design consisting of only six components. The unique features of the design include high density natural UO 2 pellets, collapsible zircaloy cladding, no gas plenums and short (50 cm), simple bundle configuration. Over the last 20 years, considerable efforts have been expended and still being continued on development of analytical tools and computer codes generation of technical specifications tests and experimental studies type tests on prototype bundles irradiation of special documented fuel bundles in power reactors and monitoring and analysis of fuel performance. The knowledge thus gained has helped us to modify design requirements, relax technical specifications and to evolve new, improved designs. The PHWR fuel technology in India can now be considered as well proven but there is considerable scope for further improvements both in design and manufacturing. For example, in design, use of thinner wall cladding (to improve burn up) bundle design with graded elements, double dished pellet, improved coatings, use of MOX fuel etc. are being explored. On the manufacturing side emphasis need to be given on maintaining the quality, improvement on production and process control. The use of automation and advances in machine control techniques, for example, using micro processors can effectively contribute to improvements in quality, productivity and lowering of fuel fabrication costs. In this paper, the PHWR fuel design features, different fuel designs evolved, fuel specifications, influence of fabrication variables and future direction in improved fuel performance are discussed. (author) 9 refs., 7 figs

  18. A Modified Design of a Thermocouple Based Digital Temperature Indicator with Opto-Isolation

    Directory of Open Access Journals (Sweden)

    S. C. BERA

    2008-01-01

    Full Text Available In the conventional thermocouple based digital temperature indicator the millivolt signal obtained from a thermocouple is first amplified and then converted into a digital signal by using analog-to-digital converter (ADC. This digital signal is then indicated as digital display of temperature using digital counter circuit or microprocessor/microcontroller based circuitry. In the present paper a modified AD conversion technique along with opto-isolation is used to indicate digitally the temperature without using any conventional analog-to-digital converter. The theory and design of the measuring technique are described in the paper. The non-linearity of thermocouple is eliminated by using look-up table within software program. The performance of the circuit has been experimentally tested by using mV input signal instead of a thermocouple as well as using a K-type thermocouple. The experimental results are reported in the paper.

  19. High Performance Design of 100Gb/s DPSK Optical Transmitter

    DEFF Research Database (Denmark)

    Das, Bhagwan; Abdullah, M.F.L; Shah, Nor Shahihda Mohd

    2016-01-01

    and optical transmitter have taken plenty of time for transmitting signal. When proposed design is operated at 1 GHz, 5 GHz, 10 GHz and 20 GHz using time constraint technique, it is observed that among all these frequencies, at 10 GHz high performance output is achieved for designed optical transmitter....... This high performance design of optical transmitter has zero timing error, low timing score and high slack time due to synchronization between input data and clock frequency. It is also determined that 99% timing score is reduced in comparison with 1 GHz frequency that has high jitters, high timing error......, high time score and low slack time. The high performance design is realized without disturbing actual bandwidth, power consumption and other parameters of the design. The proposed high performance design of 100Gb/s optical transmitter can be used with existing optical communication system to develop...

  20. The software and hardware design of a 16 channel online dose rate monitoring system

    International Nuclear Information System (INIS)

    Tang Wenjuan; Yan Yonghong; Yang Shiming; Li Xiaonan; Min Jian

    2011-01-01

    The software and hardware design of a 16 channel online dose rate monitoring system is presented. After being amplified and A/D converted, the output signal of the sensors was sent to a microprocessor through an FPGA, where the low-frequency filter, calculation, temperature compensation and pedestal deduction were accomplished. Such steps corrected the variation of dark current dependent on temperature fluctuations in a effective way, and finally the instantaneous dose rate results with enough precise were obtained. (authors)

  1. Design and performance analysis of delay insensitive multi-ring structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Staunstrup, Jørgen

    1993-01-01

    A set of simple design and performance analysis techniques that have been successfully used to design a number of nontrivial delay insensitive circuits is described. Examples are building blocks for digital filters and a vector multiplier using a serial-parallel multiply and accumulate algorithm....... The vector multiplier circuit has been laid out, submitted for fabrication and successfully tested. Throughout the analysis elements from this design are used to illustrate the design and performance analysis techniques. The design technique is based on a data flow approach using pipelines and rings...... that are composed into larger multiring structures by joining and forking of signals. By limiting to this class of structures, it is possible, even for complex designs, to analyze the performance and establish an understanding of the bottlenecks....

  2. Design of a Cognitive Tool to Enhance Problemsolving Performance

    Science.gov (United States)

    Lee, Youngmin; Nelson, David

    2005-01-01

    The design of a cognitive tool to support problem-solving performance for external representation of knowledge is described. The limitations of conventional knowledge maps are analyzed in proposing the tool. The design principles and specifications are described. This tool is expected to enhance learners problem-solving performance by allowing…

  3. Anti-Hassle Chip

    Science.gov (United States)

    1998-01-01

    With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

  4. Technical basis for environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

    International Nuclear Information System (INIS)

    Korsah, K.; Wood, R.T.; Hassan, M.; Tanaka, T.J.

    1998-01-01

    This document presents the results of studies sponsored by the Nuclear Regulatory Commission (NRC) to provide the technical basis for environmental qualification of computer-based safety equipment in nuclear power plants. The studies were conducted by Oak Ridge National Laboratory (ORNL), Sandia National Laboratories (SNL), and Brookhaven National Laboratory (BNL). The studies address the following: (1) adequacy of the present test methods for qualification of digital I and C systems; (2) preferred (i.e., Regulatory Guide-endorsed) standards; (3) recommended stressors to be included in the qualification process during type testing; (4) resolution of need for accelerated aging for equipment to be located in a benign environment; and (5) determination of an appropriate approach for addressing the impact of smoke in digital equipment qualification programs. Significant findings from the studies form the technical basis for a recommended approach to the environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

  5. Technical basis for environmental qualification of microprocessor-based safety-related equipment in nuclear power plants

    Energy Technology Data Exchange (ETDEWEB)

    Korsah, K.; Wood, R.T. [Oak Ridge National Lab., TN (United States); Hassan, M. [Brookhaven National Lab., Upton, NY (United States); Tanaka, T.J. [Sandia National Labs., Albuquerque, NM (United States)

    1998-01-01

    This document presents the results of studies sponsored by the Nuclear Regulatory Commission (NRC) to provide the technical basis for environmental qualification of computer-based safety equipment in nuclear power plants. The studies were conducted by Oak Ridge National Laboratory (ORNL), Sandia National Laboratories (SNL), and Brookhaven National Laboratory (BNL). The studies address the following: (1) adequacy of the present test methods for qualification of digital I and C systems; (2) preferred (i.e., Regulatory Guide-endorsed) standards; (3) recommended stressors to be included in the qualification process during type testing; (4) resolution of need for accelerated aging for equipment to be located in a benign environment; and (5) determination of an appropriate approach for addressing the impact of smoke in digital equipment qualification programs. Significant findings from the studies form the technical basis for a recommended approach to the environmental qualification of microprocessor-based safety-related equipment in nuclear power plants.

  6. Performance Based Plastic Design of Concentrically Braced Frame attuned with Indian Standard code and its Seismic Performance Evaluation

    Directory of Open Access Journals (Sweden)

    Sejal Purvang Dalal

    2015-12-01

    Full Text Available In the Performance Based Plastic design method, the failure is predetermined; making it famous throughout the world. But due to lack of proper guidelines and simple stepwise methodology, it is not quite popular in India. In this paper, stepwise design procedure of Performance Based Plastic Design of Concentrically Braced frame attuned with the Indian Standard code has been presented. The comparative seismic performance evaluation of a six storey concentrically braced frame designed using the displacement based Performance Based Plastic Design (PBPD method and currently used force based Limit State Design (LSD method has also been carried out by nonlinear static pushover analysis and time history analysis under three different ground motions. Results show that Performance Based Plastic Design method is superior to the current design in terms of displacement and acceleration response. Also total collapse of the frame is prevented in the PBPD frame.

  7. Thermal treatment system of hazardous residuals in three heating zones based on a microprocessor; Sistema de tratamiento termico de residuos peligrosos en tres zonas de calentamiento a base de un microcontrolador.

    Energy Technology Data Exchange (ETDEWEB)

    Luna H, C L

    1997-12-01

    Thermal treatment system consists of a high power electric oven of three heating zones where each zone works up to 1200 Centigrades; it has the capacity of rising the central zone temperature up to 1000 Centigrades in 58 minutes approximately. This configuration of three zones could be programmed to different temperatures and they will be digitally controlled by a control microprocessor, which has been controlled by its own assembler language, in function of the PID control. There are also other important controls based on this microprocessor, as a signal amplification, starting and shutdown of high power step relays, activation and deactivation of both analogic/digital and digital/analogic convertors, port activation and basic data storage of the system. Two main characteristics were looked for this oven design; the first was the possibility of controlling the three zone temperature and the second was to reduce the rising and stabilization operation time and its digitized control. The principal function of the three zone oven is to accelerate the degradation of hazardous residuals by an oxidation instead combustion, through relatively high temperatures (minimum 800 Centigrades and maximum 1200 Centigrades); this process reduces the ash and volatile particulate production. The hazardous residuals will be pumped into the degradation system and after atomized through a packaged column; this step will avoid the direct contact of the residuals with the oven cores. These features make this system as closed process, which means that the residuals can not leak to the working area, reducing the exposure risk to the personnel. This three step oven system is the first stage of the complete hazardous residuals degradation system; after this, the flow will go into a cold plasma region where the process is completed, making a closed system. (Author).

  8. Performance indices and evaluation of algorithms in building energy efficient design optimization

    International Nuclear Information System (INIS)

    Si, Binghui; Tian, Zhichao; Jin, Xing; Zhou, Xin; Tang, Peng; Shi, Xing

    2016-01-01

    Building energy efficient design optimization is an emerging technique that is increasingly being used to design buildings with better overall performance and a particular emphasis on energy efficiency. To achieve building energy efficient design optimization, algorithms are vital to generate new designs and thus drive the design optimization process. Therefore, the performance of algorithms is crucial to achieving effective energy efficient design techniques. This study evaluates algorithms used for building energy efficient design optimization. A set of performance indices, namely, stability, robustness, validity, speed, coverage, and locality, is proposed to evaluate the overall performance of algorithms. A benchmark building and a design optimization problem are also developed. Hooke–Jeeves algorithm, Multi-Objective Genetic Algorithm II, and Multi-Objective Particle Swarm Optimization algorithm are evaluated by using the proposed performance indices and benchmark design problem. Results indicate that no algorithm performs best in all six areas. Therefore, when facing an energy efficient design problem, the algorithm must be carefully selected based on the nature of the problem and the performance indices that matter the most. - Highlights: • Six indices of algorithm performance in building energy optimization are developed. • For each index, its concept is defined and the calculation formulas are proposed. • A benchmark building and benchmark energy efficient design problem are proposed. • The performance of three selected algorithms are evaluated.

  9. Planetary Suit Hip Bearing Model for Predicting Design vs. Performance

    Science.gov (United States)

    Cowley, Matthew S.; Margerum, Sarah; Harvil, Lauren; Rajulu, Sudhakar

    2011-01-01

    Designing a planetary suit is very complex and often requires difficult trade-offs between performance, cost, mass, and system complexity. In order to verifying that new suit designs meet requirements, full prototypes must eventually be built and tested with human subjects. Using computer models early in the design phase of new hardware development can be advantageous, allowing virtual prototyping to take place. Having easily modifiable models of the suit hard sections may reduce the time it takes to make changes to the hardware designs and then to understand their impact on suit and human performance. A virtual design environment gives designers the ability to think outside the box and exhaust design possibilities before building and testing physical prototypes with human subjects. Reductions in prototyping and testing may eventually reduce development costs. This study is an attempt to develop computer models of the hard components of the suit with known physical characteristics, supplemented with human subject performance data. Objectives: The primary objective was to develop an articulating solid model of the Mark III hip bearings to be used for evaluating suit design performance of the hip joint. Methods: Solid models of a planetary prototype (Mark III) suit s hip bearings and brief section were reverse-engineered from the prototype. The performance of the models was then compared by evaluating the mobility performance differences between the nominal hardware configuration and hardware modifications. This was accomplished by gathering data from specific suited tasks. Subjects performed maximum flexion and abduction tasks while in a nominal suit bearing configuration and in three off-nominal configurations. Performance data for the hip were recorded using state-of-the-art motion capture technology. Results: The results demonstrate that solid models of planetary suit hard segments for use as a performance design tool is feasible. From a general trend perspective

  10. Implementation of the Two-Point Angular Correlation Function on a High-Performance Reconfigurable Computer

    Directory of Open Access Journals (Sweden)

    Volodymyr V. Kindratenko

    2009-01-01

    Full Text Available We present a parallel implementation of an algorithm for calculating the two-point angular correlation function as applied in the field of computational cosmology. The algorithm has been specifically developed for a reconfigurable computer. Our implementation utilizes a microprocessor and two reconfigurable processors on a dual-MAP SRC-6 system. The two reconfigurable processors are used as two application-specific co-processors. Two independent computational kernels are simultaneously executed on the reconfigurable processors while data pre-fetching from disk and initial data pre-processing are executed on the microprocessor. The overall end-to-end algorithm execution speedup achieved by this implementation is over 90× as compared to a sequential implementation of the algorithm executed on a single 2.8 GHz Intel Xeon microprocessor.

  11. Robust design principles for reducing variation in functional performance

    DEFF Research Database (Denmark)

    Christensen, Martin Ebro; Howard, Thomas J.

    2016-01-01

    This paper identifies, describes and classifies a comprehensive collection of variation reduction principles (VRP) that can be used to increase the robustness of a product and reduce its variation in functional performance. Performance variation has a negative effect on the reliability and percei......This paper identifies, describes and classifies a comprehensive collection of variation reduction principles (VRP) that can be used to increase the robustness of a product and reduce its variation in functional performance. Performance variation has a negative effect on the reliability...... and perceived quality of a product and efforts should be made to minimise it. The design principles are identified by a systematic decomposition of the Taguchi Transfer Function in combination with the use of existing literature and the authors’ experience. The paper presents 15 principles and describes...... their advantages and disadvantages along with example cases. Subsequently, the principles are classified based on their applicability in the various development and production stages. The VRP are to be added to existing robust design methodologies, helping the designer to think beyond robust design tool and method...

  12. Realization of two-dimensional transformations by the arithmetical module of an intelligent graphics terminal

    International Nuclear Information System (INIS)

    Leich, A.; Polyntsev, A.D.

    1982-01-01

    The structure and software of the arithmetical module for the multi-microprocessor intelligent graphics terminal designed for realization of the world coordinate two-dimensional transformation are described. The module performs the operations like coordinate system displacement, scaling and rotation as well as transformations for window/viewport separation

  13. Influence of Design Variations on Systems Performance

    Science.gov (United States)

    Tumer, Irem Y.; Stone, Robert B.; Huff, Edward M.; Norvig, Peter (Technical Monitor)

    2000-01-01

    High-risk aerospace components have to meet very stringent quality, performance, and safety requirements. Any source of variation is a concern, as it may result in scrap or rework. poor performance, and potentially unsafe flying conditions. The sources of variation during product development, including design, manufacturing, and assembly, and during operation are shown. Sources of static and dynamic variation during development need to be detected accurately in order to prevent failure when the components are placed in operation. The Systems' Health and Safety (SHAS) research at the NASA Ames Research Center addresses the problem of detecting and evaluating the statistical variation in helicopter transmissions. In this work, we focus on the variations caused by design, manufacturing, and assembly of these components, prior to being placed in operation (DMV). In particular, we aim to understand and represent the failure and variation information, and their correlation to performance and safety and feed this information back into the development cycle at an early stage. The feedback of such critical information will assure the development of more reliable components with less rework and scrap. Variations during design and manufacturing are a common source of concern in the development and production of such components. Accounting for these variations, especially those that have the potential to affect performance, is accomplished in a variety ways, including Taguchi methods, FMEA, quality control, statistical process control, and variation risk management. In this work, we start with the assumption that any of these variations can be represented mathematically, and accounted for by using analytical tools incorporating these mathematical representations. In this paper, we concentrate on variations that are introduced during design. Variations introduced during manufacturing are investigated in parallel work.

  14. Analog circuit design automation for performance

    NARCIS (Netherlands)

    Ning, Zhen-Qiu; Ning, Zhen-Qiu; Kole, Marq; Kole, M.E.; Mouthaan, A.J.; Wallinga, Hans

    1992-01-01

    This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Analog circuit Synthesis), in which an approach for selection of alternatives based on the evaluation of mutation values is developed, and design automafion for high performance comparators is covered.

  15. PLAST: parallel local alignment search tool for database comparison

    Directory of Open Access Journals (Sweden)

    Lavenier Dominique

    2009-10-01

    Full Text Available Abstract Background Sequence similarity searching is an important and challenging task in molecular biology and next-generation sequencing should further strengthen the need for faster algorithms to process such vast amounts of data. At the same time, the internal architecture of current microprocessors is tending towards more parallelism, leading to the use of chips with two, four and more cores integrated on the same die. The main purpose of this work was to design an effective algorithm to fit with the parallel capabilities of modern microprocessors. Results A parallel algorithm for comparing large genomic banks and targeting middle-range computers has been developed and implemented in PLAST software. The algorithm exploits two key parallel features of existing and future microprocessors: the SIMD programming model (SSE instruction set and the multithreading concept (multicore. Compared to multithreaded BLAST software, tests performed on an 8-processor server have shown speedup ranging from 3 to 6 with a similar level of accuracy. Conclusion A parallel algorithmic approach driven by the knowledge of the internal microprocessor architecture allows significant speedup to be obtained while preserving standard sensitivity for similarity search problems.

  16. Integrated cost estimation methodology to support high-performance building design

    Energy Technology Data Exchange (ETDEWEB)

    Vaidya, Prasad; Greden, Lara; Eijadi, David; McDougall, Tom [The Weidt Group, Minnetonka (United States); Cole, Ray [Axiom Engineers, Monterey (United States)

    2007-07-01

    Design teams evaluating the performance of energy conservation measures (ECMs) calculate energy savings rigorously with established modelling protocols, accounting for the interaction between various measures. However, incremental cost calculations do not have a similar rigor. Often there is no recognition of cost reductions with integrated design, nor is there assessment of cost interactions amongst measures. This lack of rigor feeds the notion that high-performance buildings cost more, creating a barrier for design teams pursuing aggressive high-performance outcomes. This study proposes an alternative integrated methodology to arrive at a lower perceived incremental cost for improved energy performance. The methodology is based on the use of energy simulations as means towards integrated design and cost estimation. Various points along the spectrum of integration are identified and characterized by the amount of design effort invested, the scheduling of effort, and relative energy performance of the resultant design. It includes a study of the interactions between building system parameters as they relate to capital costs. Several cost interactions amongst energy measures are found to be significant.The value of this approach is demonstrated with alternatives in a case study that shows the differences between perceived costs for energy measures along various points on the integration spectrum. These alternatives show design tradeoffs and identify how decisions would have been different with a standard costing approach. Areas of further research to make the methodology more robust are identified. Policy measures to encourage the integrated approach and reduce the barriers towards improved energy performance are discussed.

  17. Robust Multivariable Optimization and Performance Simulation for ASIC Design

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

  18. Design and implementation of an automatic pressure-control system for a mobile sprayer for greenhouse applications

    Energy Technology Data Exchange (ETDEWEB)

    Gonzalez, R.; Pawlowski, A.; Rodriguez, C.; Guzman, J. L.; Sanchez-Hermosilla, J.

    2012-07-01

    This article presents the design and development of an embedded automatic pressure-control system for a mobile sprayer working in greenhouses. The pressure system is mounted on a commercial vehicle, it is composed of two on/off electro valves and one proportional electro valve. The hardware developed is based on an embedded microprocessor and provides a low-cost and robust solution. The resulting embedded system has been tested on a spraying system mounted on a manned vehicle. Furthermore, an easy-tuning non-linear PI (Proportional Integral) controller to achieve the desired pressure profile is designed and implemented in the embedded system. Many physical experiments show the best performance of such controller compared with a typical PI controller. Experiments covering the pressure range from 2 to 14 bar obtained a mean error less than 0.3 bar. Summing up, a low-cost automatic pressure-control system is developed, it ensures a uniform decomposition of the liquid sprayed on plants, and it works properly over a wide variable-pressure range. (Author) 17 refs.

  19. Design of MPU based process monitoring instrument

    International Nuclear Information System (INIS)

    Ahmed, Z.; Qamar, R.; Majid, B.

    1995-03-01

    A display sub-system (DSS) for a process variable like flow is designed around Intel 8088 microprocessor. It displays the current value of a process variable but average and accumulated value display is manually selectable. The display consists of 6 units of seven segment display and accuracy up to 2 nd place of decimal is achieved. The engineering units are indicated by the LEDs. The control software is developed in assembler and burnt in a EPROM. The maximum value of the display is 9999.99 K. liter and that of time is 99 days 23 hours and 59 minutes. Sampling period is 1 second. Data acquisition is done using Polling technique. (author)

  20. Energy Design Guidelines for High Performance Schools: Tropical Island Climates

    Energy Technology Data Exchange (ETDEWEB)

    2004-11-01

    The Energy Design Guidelines for High Performance Schools--Tropical Island Climates provides school boards, administrators, and design staff with guidance to help them make informed decisions about energy and environmental issues important to school systems and communities. These design guidelines outline high performance principles for the new or retrofit design of your K-12 school in tropical island climates. By incorporating energy improvements into their construction or renovation plans, schools can significantly reduce energy consumption and costs.

  1. Cache and memory hierarchy design a performance directed approach

    CERN Document Server

    Przybylski, Steven A

    1991-01-01

    An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of ca

  2. Working group 4B - human intrusion: Design/performance requirements

    International Nuclear Information System (INIS)

    Channell, J.

    1993-01-01

    There is no summary of the progress made by working group 4B (Human Intrusion: Design/performance Requirements) during the Electric Power Research Institute's EPRI Workshop on the technical basis of EPA HLW Disposal Criteria, March 1993. This group was to discuss the waste disposal standard, 40 CFR Part 191, in terms of the design and performance requirements of human intrusion. Instead, because there were so few members, they combined with working group 4A and studied the three-tier approach to evaluating postclosure performance

  3. Journal of Agriculture, Science and Technology - Vol 14, No 2 (2012)

    African Journals Online (AJOL)

    Effect of rain water harvesting and drip irrigation on crop performance in an arid and ... Design and implementation of a microprocessor based room illumination control system ... A prototype parabolic trough solar concentrators for steam production ... The effect of pumping water from wells in an aquifer · EMAIL FULL TEXT ...

  4. Belt design central to conveyor performance

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2007-07-15

    While a conveyor system comprises a complex range of components, it is the belt design which ultimately dictates its core performance and reliability. The complexity of modern systems can be seen by the recent contract awarded to ThyssenKrupp Foerdertechnik (TKF) to supply systems for a new steel plant (including a coking plant and a power plant) to be built in Sepetiba Bay in Brazil. Phoenix has designed the Phoenotec system to protect steel cord conveyor belts. Fenner Dunlop has developed Fenaplast belting with nylon or polyester load-bearing warp and weft yarns for good impact resistance. 2 photos.

  5. 14th annual Results and Review Workshop on High Performance Computing in Science and Engineering

    CERN Document Server

    Nagel, Wolfgang E; Resch, Michael M; Transactions of the High Performance Computing Center, Stuttgart (HLRS) 2011; High Performance Computing in Science and Engineering '11

    2012-01-01

    This book presents the state-of-the-art in simulation on supercomputers. Leading researchers present results achieved on systems of the High Performance Computing Center Stuttgart (HLRS) for the year 2011. The reports cover all fields of computational science and engineering, ranging from CFD to computational physics and chemistry, to computer science, with a special emphasis on industrially relevant applications. Presenting results for both vector systems and microprocessor-based systems, the book allows readers to compare the performance levels and usability of various architectures. As HLRS

  6. Nd:YAG Laser Firmware Design under RTOS Operation

    Energy Technology Data Exchange (ETDEWEB)

    Kim, B. G.; Kim, W. Y.; Park, G. R.; Moon, D. S.; Hong, J. H.; Kim, H. J.; Cho, J. S. [Pusan National University (Korea)

    2000-07-01

    A pulsed Nd:YAG laser is used widely for materials processing and medical instrument. It's very important to control the laser energy density in those fields using a pulsed Nd:YAG laser. A pulse repetition rate and a pulse width are regarded as the most dominant factors to control the energy density of laser beam. In this paper, the alternating charge and discharge system was designed to adjust a pulse repetition rate. This system is controlled by microprocessor and allows to replace an expensive condenser for high frequency to cheap one of low frequency. In addition, The microcontroller monitors the flow of cooling water, short circuit, and miss firing and so on. We designed Nd:YAG laser firmware with smart microcontroller, and want to explain general matters about the firmware from now. (author). 8 refs., 6 figs.

  7. Expression levels of the microRNA maturing microprocessor complex component DGCR8 and the RNA-induced silencing complex (RISC) components argonaute-1, argonaute-2, PACT, TARBP1, and TARBP2 in epithelial skin cancer.

    Science.gov (United States)

    Sand, Michael; Skrygan, Marina; Georgas, Dimitrios; Arenz, Christoph; Gambichler, Thilo; Sand, Daniel; Altmeyer, Peter; Bechara, Falk G

    2012-11-01

    The microprocessor complex mediates intranuclear biogenesis of precursor microRNAs from the primary microRNA transcript. Extranuclear, mature microRNAs are incorporated into the RNA-induced silencing complex (RISC) before interaction with complementary target mRNA leads to transcriptional repression or cleavage. In this study, we investigated the expression profiles of the microprocessor complex subunit DiGeorge syndrome critical region gene 8 (DGCR8) and the RISC components argonaute-1 (AGO1), argonaute-2 (AGO2), as well as double-stranded RNA-binding proteins PACT, TARBP1, and TARBP2 in epithelial skin cancer and its premalignant stage. Patients with premalignant actinic keratoses (AK, n = 6), basal cell carcinomas (BCC, n = 15), and squamous cell carcinomas (SCC, n = 7) were included in the study. Punch biopsies were harvested from the center of the tumors (lesional), from healthy skin sites (intraindividual controls), and from healthy skin sites in a healthy control group (n = 16; interindividual control). The DGCR8, AGO1, AGO2, PACT, TARBP1, and TARBP2 mRNA expression levels were detected by quantitative real-time reverse transcriptase polymerase chain reaction. The DGCR8, AGO1, AGO2, PACT, and TARBP1 expression levels were significantly higher in the AK, BCC, and SCC groups than the healthy controls (P  0.05). This study indicates that major components of the miRNA pathway, such as the microprocessor complex and RISC, are dysregulated in epithelial skin cancer. Copyright © 2011 Wiley Periodicals, Inc.

  8. Effects of combat training on visuomotor performance in children aged 9 to 12 years - an eye-tracking study.

    Science.gov (United States)

    Ju, Yan-Ying; Liu, Yen-Hsiu; Cheng, Chih-Hsiu; Lee, Yu-Lung; Chang, Shih-Tsung; Sun, Chi-Chin; Cheng, Hsin-Yi Kathy

    2018-02-07

    Data on visuomotor performance in combat training and the effects of combat training on visuomotor performance are limited. This study aimed to investigate the effects of a specially designed combat sports (CS) training program on the visuomotor performance levels of children. A pre-post comparative design was implemented. A total of 26 students aged 9-12 years underwent 40-min CS training sessions twice a week for 8 weeks during their physical education classes. The CS training program was designed by a karate coach and a motor control specialist. The other 30 students continued their regular activities and were considered as a control group. Each student's eye movement was monitored using an eye tracker, whereas the motor performance was measured using a target hitting system with a program-controlled microprocessor. The measurements were taken 8 weeks before (baseline), 1 day before (pretest), and 1 week after (posttest) the designated training program. The task used for evaluating these students was hitting or tracking random illuminated targets as rapidly as possible. A two-way analysis of variance [group(2) × time(3)] with repeated measures of time was performed for statistical analysis. For the children who received combat training, although the eye response improvement was not significant, both the primary and secondary saccade onset latencies were significantly earlier compared to the children without combat training. Both groups of students exhibited improvement in their hit response times during the target hitting tasks. The current finding supported the notion that sports training efforts essentially enhance visuomotor function in children aged 9-12 years, and combat training facilitates an earlier secondary saccade onset.

  9. Feed-pump hydraulic performance and design improvement, Phase I: research program design. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Brown, W.H.; Gopalakrishnan, S.; Fehlau, R.; Thompson, W.E.; Wilson, D.G.

    1982-03-01

    As a result of prior EPRI-sponsored studies, it was concluded that a research program should be designed and implemented to provide an improved basis for the design, procurement, testing, and operation of large feed pumps with increased reliability and stability over the full range of operating conditions. This two-volume report contains a research plan which is based on a review of the present state of the art and which defines the necessary R and D program and estimates the benefits and costs of the program. The recommended research program consists of 30 interrelated tasks. It is designed to perform the needed research; to verify the results; to develop improved components; and to publish computer-aided design methods, pump specification guidelines, and a troubleshooting manual. Most of the technology proposed in the research plan is applicable to nuclear power plants as well as to fossil-fired plants. This volume discusses the design, performance and failures of feed pumps, and recommendations for research on pump dynamics, design, and specifications.

  10. Design Elements and Electrical Performance of a Bifacial BIPV Module

    Directory of Open Access Journals (Sweden)

    Jun-Gu Kang

    2016-01-01

    Full Text Available Bifacial BIPV systems have great potential when applied to buildings given their use of a glass-to-glass structure. However, the performance of bifacial solar cells depends on a variety of design factors. Therefore, in order to apply bifacial solar cells to buildings, a bifacial PV module performance analysis should be carried out, including consideration of the various design elements and reflecting a wide range of installation conditions. This study focuses on the performance of a bifacial BIPV module applied to a building envelope. The results here show that the design elements of reflectivity and the transparent space ratio have the greatest impact on performance levels. The distance between the module and the wall had less of an impact on performance. The bifacial BIPV module produced output up to 30% greater than the output of monofacial PV modules, depending on the design elements. Bifacial BIPV modules themselves should have transparent space ratios of at least 30%. When a dark color is used on the external wall with reflectivity of 50% or less, bifacial BIPV modules with transparent space ratios of 40% and above should be used. In order to achieve higher performance through the installation of bifacial BIPV modules, design conditions which facilitate reflectivity exceeding 50% and a transparent space ratio which exceeds 30% must be met.

  11. A Perspective on Computational Human Performance Models as Design Tools

    Science.gov (United States)

    Jones, Patricia M.

    2010-01-01

    The design of interactive systems, including levels of automation, displays, and controls, is usually based on design guidelines and iterative empirical prototyping. A complementary approach is to use computational human performance models to evaluate designs. An integrated strategy of model-based and empirical test and evaluation activities is particularly attractive as a methodology for verification and validation of human-rated systems for commercial space. This talk will review several computational human performance modeling approaches and their applicability to design of display and control requirements.

  12. ITER in-vessel system design and performance

    Science.gov (United States)

    Parker, R. R.

    2000-03-01

    The article reviews the design and performance of the in-vessel components of ITER as developed for the Engineering Design Activities (EDA) Final Design Report. The double walled vacuum vessel is the first confinement boundary and is designed to maintain its integrity under all normal and off-normal conditions, e.g. the most intense vertical displacement events (VDEs) and seismic events. The shielding blanket consists of modules connected to a toroidal backplate by flexible connectors which allow differential displacements due to temperature non-uniformities. Breeding blanket modules replace the shield modules for the Enhanced Performance Phase. The divertor concept is based on a cassette structure which is convenient for remote installation and removal. High heat flux (HHF) components are mechanically attached and can be removed and replaced in the hot cell. Operation of the divertor is based on achieving partially detached plasma conditions along and near the separatrix. Nominal heat loads of 5-10 MW/m2 are expected on the target. These are accommodated by HHF technology developed during the EDA. Disruptions and VDEs can lead to melting of the first wall armour but no damage to the underlying structure. Stresses in the main structural components remain within allowable ranges for all postulated disruption and seismic events.

  13. ITER in-vessel system design and performance

    International Nuclear Information System (INIS)

    Parker, R.R.

    2000-01-01

    The article reviews the design and performance of the in-vessel components of ITER as developed for the Engineering Design Activities (EDA) Final Design Report. The double walled vacuum vessel is the first confinement boundary and is designed to maintain its integrity under all normal and off-normal conditions, e.g. the most intense vertical displacement events (VDEs) and seismic events. The shielding blanket consists of modules connected to a toroidal backplate by flexible connectors which allow differential displacements due to temperature non-uniformities. Breeding blanket modules replace the shield modules for the Enhanced Performance Phase. The divertor concept is based on a cassette structure which is convenient for remote installation and removal. High heat flux (HHF) components are mechanically attached and can be removed and replaced in the hot cell. Operation of the divertor is based on achieving partially detached plasma conditions along and near the separatrix. Nominal heat loads of 5-10 MW/m 2 are expected on the target. These are accommodated by HHF technology developed during the EDA. Disruptions and VDEs can lead to melting of the first wall armour but no damage to the underlying structure. Stresses in the main structural components remain within allowable ranges for all postulated disruption and seismic events. (author)

  14. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  15. Design of net-gate based on S3C4510B and it's application

    International Nuclear Information System (INIS)

    Wang Yanyu; Li Xiaoqiang; Huang Jijiang; Wang Xiaoyin; Lin Feiyu; Chinese Academy of Sciences, Beijing

    2008-01-01

    This paper introduces a solution of the net-gate module. It is based on the high-performance micro-processor-S3C4510B with the 32/16 bit RISC ARM7TDMI core. The module is used the free uClinux as its OS, which support multi-task, FTP and TELNET functions. It can be used to transfer the mass data from Ethernet to RS485 and build the high speed DCS. (authors)

  16. Performance Assessment Strategies: A computational framework for conceptual design of large roofs

    Directory of Open Access Journals (Sweden)

    Michela Turrin

    2014-01-01

    Full Text Available Using engineering performance evaluations to explore design alternatives during the conceptual phase of architectural design helps to understand the relationships between form and performance; and is crucial for developing well-performing final designs. Computer aided conceptual design has the potential to aid the design team in discovering and highlighting these relationships; especially by means of procedural and parametric geometry to support the generation of geometric design, and building performance simulation tools to support performance assessments. However, current tools and methods for computer aided conceptual design in architecture do not explicitly reveal nor allow for backtracking the relationships between performance and geometry of the design. They currently support post-engineering, rather than the early design decisions and the design exploration process. Focusing on large roofs, this research aims at developing a computational design approach to support designers in performance driven explorations. The approach is meant to facilitate the multidisciplinary integration and the learning process of the designer; and not to constrain the process in precompiled procedures or in hard engineering formulations, nor to automatize it by delegating the design creativity to computational procedures. PAS (Performance Assessment Strategies as a method is the main output of the research. It consists of a framework including guidelines and an extensible library of procedures for parametric modelling. It is structured on three parts. Pre-PAS provides guidelines for a design strategy-definition, toward the parameterization process. Model-PAS provides guidelines, procedures and scripts for building the parametric models. Explore-PAS supports the solutions-assessment based on numeric evaluations and performance simulations, until the identification of a suitable design solution. PAS has been developed based on action research. Several case studies

  17. Performance of the Westinghouse WWER-1000 fuel design

    International Nuclear Information System (INIS)

    Hoglund, J.; Riznychenko, O.; Latorre, R.; Lashevych, P.

    2011-01-01

    In 2005 six (6) Westinghouse WWER-1000 Lead Test Assemblies (LTAs) were loaded in the South Ukraine Unit 3. This design has demonstrated full compatibility with resident fuel designs and all associated fuel handling and reactor components. Operations have further demonstrated adequacy of performance margins and the reliability requirements for multiple cycles of operation. The LTA's have now been discharged after completing the planned four cycles of operation and having reached an average assembly burnup in excess of 43 MWd/kgU. Post Irradiation Examinations were performed after completion of each cycle. The final LTA inspection program at end of Cycle 20 in 2010 yielded satisfactory results on all counts, and it was concluded that the 6 Westinghouse LTA's performed as expected during their operational regimes. Very good performance was demonstrated in the WWER-1000 reactor environment for the Zr-1%Nb as grid material, and ZIRLO fuel cladding and structural components. Control Rod Assemblies drop times and drag forces were all within the accepted values. The LTA program demonstrated that this fuel design is suitable for full core applications. However, the topic of fuel assembly distortion resistance was re-visited and Westinghouse therefore considered operational experience and design features from multiple development programs to enhance the basic Westinghouse WWER-1000 fuel design for Ukrainian reactors. The design now includes features that further mitigate assembly bow while at the same time improving the fuel cycle economy. This paper describes briefly the development of the Westinghouse WWER-1000 fuel design and how test results and operational experiences from multiple sources have been utilized to produce a most suitable fuel design. Early in 2011 a full region of the Westinghouse WWER-1000 design completed another full cycle of operation at South Ukraine Unit 3, all with excellent results. All 42 fuel assemblies were examined for visible damage or non

  18. Development of microprocessor based ionization gauge controller for variable energy cyclotron project [Paper No.:P5

    International Nuclear Information System (INIS)

    Srilakshmi, B.R.; Rao, M.K.V.

    1993-01-01

    The ion gauge uses energetic electrons to ionize gas molecules, the magnitude of ion current thus produced is a measure of the molecular density or the pressure which is the most commonly measured parameter in vacuum technology. The relationship between ion current (I p ) and pressure (P) is given by the equation P=I p /(I E .S.G) where S = sensitivity of a particular gauge head, G = gas constant depending on the nature of the gas appearing in the system. I E = emission current. Hence P becomes directly proportional to I p if I E is maintained constant. The present scheme incorporates a microprocessor based circuit for automatic display of pressure in the mantissa and exponent form. While the exponent is displayed through a look up table stored in the EPROM, the mantissa is computed by the processor after multiple sampling, conversion through ADC and averaging technique. (author). 2 refs., 1 fig

  19. Performance Prediction of Constrained Waveform Design for Adaptive Radar

    Science.gov (United States)

    2016-11-01

    the famous Woodward quote, having a ubiquitous feeling for all radar waveform design (and performance prediction) researchers , that is found at the end...discuss research that develops performance prediction models to quantify the impact on SINR when an amplitude constraint is placed on a radar waveform...optimize the radar perfor- mance for the particular scenario and tasks. There have also been several survey papers on various topics in waveform design for

  20. Design methodology to enhance high impedance surfaces performances

    Directory of Open Access Journals (Sweden)

    M. Grelier

    2014-04-01

    Full Text Available A methodology is introduced for designing wideband, compact and ultra-thin high impedance surfaces (HIS. A parametric study is carried out to examine the effect of the periodicity on the electromagnetic properties of an HIS. This approach allows designers to reach the best trade-off for HIS performances.

  1. A Probabilistic Design Methodology for a Turboshaft Engine Overall Performance Analysis

    Directory of Open Access Journals (Sweden)

    Min Chen

    2014-05-01

    Full Text Available In reality, the cumulative effect of the many uncertainties in engine component performance may stack up to affect the engine overall performance. This paper aims to quantify the impact of uncertainty in engine component performance on the overall performance of a turboshaft engine based on Monte-Carlo probabilistic design method. A novel probabilistic model of turboshaft engine, consisting of a Monte-Carlo simulation generator, a traditional nonlinear turboshaft engine model, and a probability statistical model, was implemented to predict this impact. One of the fundamental results shown herein is that uncertainty in component performance has a significant impact on the engine overall performance prediction. This paper also shows that, taking into consideration the uncertainties in component performance, the turbine entry temperature and overall pressure ratio based on the probabilistic design method should increase by 0.76% and 8.33%, respectively, compared with the ones of deterministic design method. The comparison shows that the probabilistic approach provides a more credible and reliable way to assign the design space for a target engine overall performance.

  2. Development of a Wiimote-based Gesture Recognizer in a Microprocessor Laboratory Course

    Directory of Open Access Journals (Sweden)

    Alberto Lorente Leal

    2011-03-01

    Full Text Available This gesture recognizer, developed by students in a third-year microprocessor-based laboratory course, takes Wii remote (Wiimote as an input device to estimate the movements of the user and to compare the detected trajectory with the previously learnt movements, in order to carry out the associated actions. Such a cheap state-of-the-art wireless user interface is very attractive for the students and can be used in many interactive applications, from robotics to virtual reality and multimedia presentations. By combining commercially-available hardware, pattern-matching techniques and programming skills, we are able to foster students' interest on developing innovative potentially-marketable systems. This freeware project, implemented as a configurable publicly-available library, can be adapted to the needs of any course or student. In our laboratory this open-source DLL is used for remotely controlling a robot (based on an open-hardware Arduino platform, using a PC and the Wiimote, although the DLL can be integrated in any C, C++, Java or C# project. A GUI application (based on a Model-View-Presenter paradigm is also provided and can be used as a template for new applications or just for debugging purposes. Although the developed application only uses data from the accelerometers, data from the infrared camera and buttons of the Wiimote is also available.

  3. Off-design performance analysis of a solar-powered organic Rankine cycle

    International Nuclear Information System (INIS)

    Wang, Jiangfeng; Yan, Zhequan; Zhao, Pan; Dai, Yiping

    2014-01-01

    Highlights: • Solar-powered organic Rankine cycle with CPC and thermal storage unit is studied. • Off-design performances encountering the changes of key parameters are examined. • Off-design performance is analyzed over a whole day and in different months. - Abstract: Performance evaluation of a thermodynamic system under off-design conditions is very important for reliable and cost-effective operation. In this study, an off-design model of an organic Rankine cycle driven by solar energy is established with compound parabolic collector (CPC) to collect the solar radiation and thermal storage unit to achieve the continuous operation of the overall system. The system off-design behavior is examined under the change in environment temperature, as well as thermal oil mass flow rates of vapor generator and CPC. In addition, the off-design performance of the system is analyzed over a whole day and in different months. The results indicate that a decrease in environment temperature, or the increases in thermal oil mass flow rates of vapor generator and CPC could improve the off-design performance. The system obtains the maximum average exergy efficiency in December and the maximum net power output in June or in September. Both the net power output and the average exergy efficiency reach minimum values in August

  4. Ultra wideband antennas design, methodologies, and performance

    CERN Document Server

    Galvan-Tejada, Giselle M; Jardón Aguilar, Hildeberto

    2015-01-01

    Ultra Wideband Antennas: Design, Methodologies, and Performance presents the current state of the art of ultra wideband (UWB) antennas, from theory specific for these radiators to guidelines for the design of omnidirectional and directional UWB antennas. Offering a comprehensive overview of the latest UWB antenna research and development, this book:Discusses the developed theory for UWB antennas in frequency and time domainsDelivers a brief exposition of numerical methods for electromagnetics oriented to antennasDescribes solid-planar equivalen

  5. The Effect of School Design on Student Performance

    Science.gov (United States)

    Ariani, Mohsen Ghasemi; Mirdad, Fatemeh

    2016-01-01

    The present study aims at exploring the influence of school design on student performance. The participants consisted of 150 students who studied at two Iranian public school and private school in Mashhad City. School Design and Planning Laboratory (SDPL) model of Georgia University (and Tanner (2009)) was used as an appraisal indicator of school…

  6. Design of JMTR high-performance fuel element

    International Nuclear Information System (INIS)

    Sakurai, Fumio; Shimakawa, Satoshi; Komori, Yoshihiro; Tsuchihashi, Keiichiro; Kaminaga, Fumito

    1999-01-01

    For test and research reactors, the core conversion to low-enriched uranium fuel is required from the viewpoint of non-proliferation of nuclear weapon material. Improvements of core performance are also required in order to respond to recent advanced utilization needs. In order to meet both requirements, a high-performance fuel element of high uranium density with Cd wires as burnable absorbers was adopted for JMTR core conversion to low-enriched uranium fuel. From the result of examination of an adaptability of a few group constants generated by a conventional transport-theory calculation with an isotropic scattering approximation to a few group diffusion-theory core calculation for design of the JMTR high-performance fuel element, it was clear that the depletion of Cd wires was not able to be predicted accurately using group constants generated by the conventional method. Therefore, a new generation method of a few group constants in consideration of an incident neutron spectrum at Cd wire was developed. As the result, the most suitable high-performance fuel element for JMTR was designed successfully, and that allowed extension of operation duration without refueling to almost twice as long and offer of irradiation field with constant neutron flux. (author)

  7. High-Performance Computing Paradigm and Infrastructure

    CERN Document Server

    Yang, Laurence T

    2006-01-01

    With hyperthreading in Intel processors, hypertransport links in next generation AMD processors, multi-core silicon in today's high-end microprocessors from IBM and emerging grid computing, parallel and distributed computers have moved into the mainstream

  8. Conceptual design of a digital control system for nuclear criticality experiments

    International Nuclear Information System (INIS)

    Rojas, S.P.

    1994-04-01

    Nuclear criticality is a concern in many areas of nuclear engineering including waste management, nuclear weapons testing and design, basic nuclear research, and nuclear reactor design and analysis. As in many areas of science and engineering, experimental work conducted in this field has provided a wealth of data and insight essential to the formulation of theory and the advancement in knowledge of fissioning systems. In light of the many diverse applications of nuclear criticality, there is a continuing interest to learn and understand more about the fundamental physical processes through continued experimentation. This thesis addresses the problem of setting up and programming a microprocessor-based digital control system (PLC) for a proposed critical experiment using, among other devices, a stepper motor, a joystick control mechanism, and switches. This experiment represents a revised configuration to test cylindrical nuclear waste packages. A Monte Carlo numerical study for the proposed critical assembly has been performed in order to illustrate how results from numerical calculations are used in the process of assembling the control system and to corroborate previous experimental data. In summary, a control system utilizing some common devices necessary to perform a critical experiment (stepper motor, push-buttons, etc.) has been assembled. Control components were sized using the results of a probabilistic computer code (MCNP). Finally, a program was written that illustrates the coupling between the hardware and the devices being controlled in the new test fixture

  9. 40 CFR 63.2354 - What performance tests, design evaluations, and performance evaluations must I conduct?

    Science.gov (United States)

    2010-07-01

    ... evaluations, and performance evaluations must I conduct? 63.2354 Section 63.2354 Protection of Environment... tests, design evaluations, and performance evaluations must I conduct? (a)(1) For each performance test... procedures specified in subpart SS of this part. (3) For each performance evaluation of a continuous emission...

  10. Material and design considerations of FBGA reliability performance

    International Nuclear Information System (INIS)

    Lee, Teck Kheng; Ng, T.C.; Chai, Y.M.

    2004-01-01

    FBGA package reliability is usually assessed through the conventional approaches of die attach and mold compound material optimization. However, with the rapid changes and fast-moving pace of electronic packaging and the introduction of new soldermask and core materials, substrate design has also become a critical factor in determining overall package reliability. The purpose of this paper is to understand the impact design and soldermask material of a rigid substrate on overall package reliability. Three different soldermask patterns with a matrix of different die attach, mold compound, and soldermask materials are assessed using the moisture sensitivity test (MST). Package reliability is also assessed through the use of temperature cycling (T/C) at conditions 'B' and 'C'. For material optimization, three different mold compounds and die attach materials are used. Material adhesion between different die attach materials and soldermask materials are obtained through die shear performed at various temperatures and preset moisture conditions. A study correlating the different packaging material properties and their relative adhesion strengths with overall package reliability in terms of both MST and T/C performance was performed. Soldermask design under the die pads was found to affect package reliability. For example, locating vias at the edge of the die is not desirable because the vias acts as initiation point for delamination and moisture-induced failure. Through die shear testing, soldermask B demonstrated higher adhesion properties compared to soldermask A across several packaging materials and enhanced the overall package reliability in terms of both MST and T/C performance. Both MST JEDEC level 1 and the T/C of 'B' and 'C' at 1000 cycles have been achieved through design and package material optimization

  11. Community Design Parameters and the Performance of Residential Cogeneration Systems

    Directory of Open Access Journals (Sweden)

    Hazem Rashed-Ali

    2012-11-01

    Full Text Available The integration of cogeneration systems in residential and mixed-use communities has the potential of reducing their energy demand and harmful emissions and can thus play asignificant role in increasing their environmental sustainability. This study investigated the impact of selected planning and architectural design parameters on the environmental and economic performances of centralized cogeneration systems integrated into residential communities in U.S.cold climates. Parameters investigated include: 1 density, 2 use mix, 3 street configuration, 4 housing typology, 5 envelope and building systems’ efficiencies, and 6 passive solar energyutilization. The study integrated several simulation tools into a procedure to assess the impact of each design parameter on the cogeneration system performance. This assessment procedure included: developing a base-line model representing typical design characteristics of U.S. residential communities; assessing the cogeneration system’s performance within this model using three performance indicators: percentage of reduction in primary energy use, percentage of reduction in CO2 emissions; and internal rate of return; assessing the impact of each parameter on the system performance through developing 46 design variations of the base-line model representing potential changes in each parameter and calculating the three indicators for each variation; and finally, using a multi-attribute decision analysis methodology to evaluate the relative impact of each parameter on the cogeneration system performance. The study results show that planning parameters had a higher impact on the cogeneration system performance than architectural ones. Also, a significant correlation was found between design characteristics identified as favorable for the cogeneration system performance and those of sustainable residential communities. These include high densities, high use mix, interconnected street networks, and mixing of

  12. MIDA - Optimizing control room performance through multi-modal design

    International Nuclear Information System (INIS)

    Ronan, A. M.

    2006-01-01

    Multi-modal interfaces can support the integration of humans with information processing systems and computational devices to maximize the unique qualities that comprise a complex system. In a dynamic environment, such as a nuclear power plant control room, multi-modal interfaces, if designed correctly, can provide complementary interaction between the human operator and the system which can improve overall performance while reducing human error. Developing such interfaces can be difficult for a designer without explicit knowledge of Human Factors Engineering principles. The Multi-modal Interface Design Advisor (MIDA) was developed as a support tool for system designers and developers. It provides design recommendations based upon a combination of Human Factors principles, a knowledge base of historical research, and current interface technologies. MIDA's primary objective is to optimize available multi-modal technologies within a human computer interface in order to balance operator workload with efficient operator performance. The purpose of this paper is to demonstrate MIDA and illustrate its value as a design evaluation tool within the nuclear power industry. (authors)

  13. Investigating the Performance Impact of Newness from a Design Perspective

    DEFF Research Database (Denmark)

    Salomo, Søren; Talke, Katrin; Lutz, Antje

    2008-01-01

    and consumer research, we build an argument for why product innovativeness both from a design and technology perspective may impact sales performance of new products. In order to investigate these effects, we conducted a study based on a sample of 157 new car models launched in the German market between 1978...... innovativeness is very rarely assessed from a design perspective. This fact is surprising, especially when considering that in many markets new products are very similar in technological features, but compete on the product design (Veryzer, 1995). Drawing from different literature streams, such as design...... and 2006. For measuring both innovativeness dimensions, different data collection methods are combined, such as expert interviews, expert ratings, and document analyses. Responding to recent calls for more objective performance metrics (Sourescu et al., 2003), actual sales data are used as a performance...

  14. ITER in-vessel system design and performance

    International Nuclear Information System (INIS)

    Parker, R.R.

    1999-01-01

    This paper reviews the design and performance of the in-vessel components of ITER as developed for the EDA Final Design Report (FDR). The double-wall vessel is the first confinement boundary and is designed to maintain its integrity under all normal and off-normal conditions, e.g., the most intense VDE's and seismic events. The shielding blanket consists of modules connected to a toroidal backplate by flexible connectors which allow differential displacements due to temperature differences. Breeding blanket modules replace the shield modules for the Enhanced Performance Phase. The divertor is based on a cassette structure which is convenient for remote installation and removal. High heat flux (HHF) components are mechanically attached and can be removed and replaced in the hot cell. Operation of the divertor is based on achieving partially detached plasma conditions along and near the separatrix. Nominal heat loads of 5-10 MW/m 2 are expected and these are accommodated by HHF technology developed during the EDA. Disruptions and VDE's can lead to melting of the first wall armour but no damage to the underlying structure. Stresses in the main structural components remain within allowables for all postulated disruption and seismic events. (author)

  15. ITER in-vessel system design and performance

    International Nuclear Information System (INIS)

    Parker, R.R.

    2001-01-01

    This paper reviews the design and performance of the in-vessel components of ITER as developed for the EDA Final Design Report (FDR). The double-wall vessel is the first confinement boundary and is designed to maintain its integrity under all normal and off-normal conditions, e.g., the most intense VDE's and seismic events. The shielding blanket consists of modules connected to a toroidal backplate by flexible connectors which allow differential displacements due to temperature differences. Breeding blanket modules replace the shield modules for the Enhanced Performance Phase. The divertor is based on a cassette structure which is convenient for remote installation and removal. High heat flux (HHF) components are mechanically attached and can be removed and replaced in the hot cell. Operation of the divertor is based on achieving partially detached plasma conditions along and near the separatrix. Nominal heat loads of 5-10 MW/m 2 are expected and these are accommodated by HHF technology developed during the EDA. Disruptions and VDE's can lead to melting of the first wall armour but no damage to the underlying structure. Stresses in the main structural components remain within allowables for all postulated disruption and seismic events. (author)

  16. PHARAO laser source flight model: Design and performances

    Energy Technology Data Exchange (ETDEWEB)

    Lévèque, T., E-mail: thomas.leveque@cnes.fr; Faure, B.; Esnault, F. X.; Delaroche, C.; Massonnet, D.; Grosjean, O.; Buffe, F.; Torresi, P. [Centre National d’Etudes Spatiales, 18 avenue Edouard Belin, 31400 Toulouse (France); Bomer, T.; Pichon, A.; Béraud, P.; Lelay, J. P.; Thomin, S. [Sodern, 20 Avenue Descartes, 94451 Limeil-Brévannes (France); Laurent, Ph. [LNE-SYRTE, CNRS, UPMC, Observatoire de Paris, 61 avenue de l’Observatoire, 75014 Paris (France)

    2015-03-15

    In this paper, we describe the design and the main performances of the PHARAO laser source flight model. PHARAO is a laser cooled cesium clock specially designed for operation in space and the laser source is one of the main sub-systems. The flight model presented in this work is the first remote-controlled laser system designed for spaceborne cold atom manipulation. The main challenges arise from mechanical compatibility with space constraints, which impose a high level of compactness, a low electric power consumption, a wide range of operating temperature, and a vacuum environment. We describe the main functions of the laser source and give an overview of the main technologies developed for this instrument. We present some results of the qualification process. The characteristics of the laser source flight model, and their impact on the clock performances, have been verified in operational conditions.

  17. Co-verification of hardware and software for ARM SoC design

    CERN Document Server

    Andrews, Jason

    2004-01-01

    Hardware/software co-verification is how to make sure that embedded system software works correctly with the hardware, and that the hardware has been properly designed to run the software successfully -before large sums are spent on prototypes or manufacturing. This is the first book to apply this verification technique to the rapidly growing field of embedded systems-on-a-chip(SoC). As traditional embedded system design evolves into single-chip design, embedded engineers must be armed with the necessary information to make educated decisions about which tools and methodology to deploy. SoC verification requires a mix of expertise from the disciplines of microprocessor and computer architecture, logic design and simulation, and C and Assembly language embedded software. Until now, the relevant information on how it all fits together has not been available. Andrews, a recognized expert, provides in-depth information about how co-verification really works, how to be successful using it, and pitfalls to avoid. H...

  18. High performance hydraulic design techniques of mixed-flow pump impeller and diffuser

    International Nuclear Information System (INIS)

    Kim, Sung; Lee, Kyoung Yong; Kim, Joon Hyung; Kim, Jin Hyuk; Jung, Uk Hee; Choi, Young Seok

    2015-01-01

    In this paper, we describe a numerical study about the performance improvement of a mixed-flow pump by optimizing the design of the impeller and diffuser using a commercial computational fluid dynamics (CFD) code and design-of-experiments (DOE). The design variables of impeller and diffuser in the vane plane development were defined with a fixed meridional plane. The design variables were defined by the vane plane development, which indicates the blade-angle distributions and length of the impeller and diffuser. The vane plane development was controlled using the blade-angle in a fixed meridional plane. The blade shape of the impeller and diffuser were designed using a traditional method in which the inlet and exit angles are connected smoothly. First, the impeller optimum design was performed with impeller design variables. The diffuser optimum design was performed with diffuser design variables while the optimally designed impeller shape was fixed. The importance of the impeller and diffuser design variables was analyzed using 2 k factorial designs, and the design optimization of the impeller and diffuser design variables was determined using the response surface method (RSM). The objective functions were defined as the total head (Ht) and the total efficiency (ηt) at the design flow rate. The optimally designed model was verified using numerical analysis, and the numerical analysis results for both the optimum model and the reference model were compared to determine the reasons for the improved pump performance. A pump performance test was carried out for the optimum model, and its reliability was proved by a comparative analysis of the results of the numerical analysis and an experiment using the optimum model.

  19. Thermic diode performance characteristics and design manual

    Science.gov (United States)

    Bernard, D. E.; Buckley, S.

    1979-01-01

    Thermic diode solar panels are a passive method of space and hot water heating using the thermosyphon principle. Simplified methods of sizing and performing economic analyses of solar heating systems had until now been limited to passive systems. A mathematical model of the thermic diode including its high level of stratification has been constructed allowing its performance characteristics to be studied. Further analysis resulted in a thermic diode design manual based on the f-chart method.

  20. Research on performance-based seismic design criteria

    Institute of Scientific and Technical Information of China (English)

    谢礼立; 马玉宏

    2002-01-01

    The seismic design criterion adopted in the existing seismic design codes is reviewed. It is pointed out that the presently used seismic design criterion is not satisfied with the requirements of nowadays social and economic development. A new performance-based seismic design criterion that is composed of three components is presented in this paper. It can not only effectively control the economic losses and casualty, but also ensure the building(s function in proper operation during earthquakes. The three components are: classification of seismic design for buildings, determination of seismic design intensity and/or seismic design ground motion for controlling seismic economic losses and casualties, and determination of the importance factors in terms of service periods of buildings. For controlling the seismic human losses, the idea of socially acceptable casualty level is presented and the (Optimal Economic Decision Model( and (Optimal Safe Decision Model( are established. Finally, a new method is recommended for calculating the importance factors of structures by adjusting structures service period on the base of more important structure with longer service period than the conventional ones. Therefore, the more important structure with longer service periods will be designed for higher seismic loads, in case the exceedance probability of seismic hazard in different service period is same.

  1. A performance-oriented power transformer design methodology using multi-objective evolutionary optimization.

    Science.gov (United States)

    Adly, Amr A; Abd-El-Hafiz, Salwa K

    2015-05-01

    Transformers are regarded as crucial components in power systems. Due to market globalization, power transformer manufacturers are facing an increasingly competitive environment that mandates the adoption of design strategies yielding better performance at lower costs. In this paper, a power transformer design methodology using multi-objective evolutionary optimization is proposed. Using this methodology, which is tailored to be target performance design-oriented, quick rough estimation of transformer design specifics may be inferred. Testing of the suggested approach revealed significant qualitative and quantitative match with measured design and performance values. Details of the proposed methodology as well as sample design results are reported in the paper.

  2. Energy Design Guidelines for High Performance Schools: Arctic and Subarctic Climates

    Energy Technology Data Exchange (ETDEWEB)

    2004-11-01

    The Energy Design Guidelines for High Performance Schools--Arctic and Subarctic Climates provides school boards, administrators, and design staff with guidance to help them make informed decisions about energy and environmental issues important to school systems and communities. These design guidelines outline high performance principles for the new or retrofit design of your K-12 school in arctic and subarctic climates. By incorporating energy improvements into their construction or renovation plans, schools can significantly reduce energy consumption and costs.

  3. A general solution to the material performance index for bending strength design

    International Nuclear Information System (INIS)

    Burgess, S.C.; Pasini, D.; Smith, D.J.; Alemzadeh, K.

    2006-01-01

    This paper presents a general solution to the material performance index for the bending strength design of beams. In general, the performance index for strength design is ρ f q /ρ where σ f is the material strength, ρ is the material density and q is a function of the direction of scaling. Previous studies have only solved q for three particular cases: proportional scaling of width and height (q=2/3), constrained height (q=1) and constrained width (q=1/2). This paper presents a general solution to the exponent q for any arbitrary direction of scaling. The index is used to produce performance maps that rank relative material performance for particular design cases. The performance index and the performance maps are applied to a design case study

  4. Loudspeaker Design and Performance Evaluation

    Science.gov (United States)

    Mäkivirta, Aki Vihtori

    A loudspeaker comprises transducers converting an electrical driving signal into sound pressure, an enclosure working as a holder for transducers, front baffle and box to contain and eliminate the rear-radiating audio signal, and electronic components. Modeling of transducers as well as enclosures is treated in Chap. 32 of this handbook. The purpose of the present chapter is to shed light on the design choices and options for the electronic circuits conditioning the electrical signal fed into loudspeaker transducers in order to optimize the acoustic performance of the loudspeaker.

  5. Business Performer-Centered Design of User Interfaces

    Science.gov (United States)

    Sousa, Kênia; Vanderdonckt, Jean

    Business Performer-Centered Design of User Interfaces is a new design methodology that adopts business process (BP) definition and a business performer perspective for managing the life cycle of user interfaces of enterprise systems. In this methodology, when the organization has a business process culture, the business processes of an organization are firstly defined according to a traditional methodology for this kind of artifact. These business processes are then transformed into a series of task models that represent the interactive parts of the business processes that will ultimately lead to interactive systems. When the organization has its enterprise systems, but not yet its business processes modeled, the user interfaces of the systems help derive tasks models, which are then used to derive the business processes. The double linking between a business process and a task model, and between a task model and a user interface model makes it possible to ensure traceability of the artifacts in multiple paths and enables a more active participation of business performers in analyzing the resulting user interfaces. In this paper, we outline how a human-perspective is used tied to a model-driven perspective.

  6. Material and design considerations of FBGA reliability performance

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Teck Kheng; Ng, T.C.; Chai, Y.M

    2004-09-01

    FBGA package reliability is usually assessed through the conventional approaches of die attach and mold compound material optimization. However, with the rapid changes and fast-moving pace of electronic packaging and the introduction of new soldermask and core materials, substrate design has also become a critical factor in determining overall package reliability. The purpose of this paper is to understand the impact design and soldermask material of a rigid substrate on overall package reliability. Three different soldermask patterns with a matrix of different die attach, mold compound, and soldermask materials are assessed using the moisture sensitivity test (MST). Package reliability is also assessed through the use of temperature cycling (T/C) at conditions 'B' and 'C'. For material optimization, three different mold compounds and die attach materials are used. Material adhesion between different die attach materials and soldermask materials are obtained through die shear performed at various temperatures and preset moisture conditions. A study correlating the different packaging material properties and their relative adhesion strengths with overall package reliability in terms of both MST and T/C performance was performed. Soldermask design under the die pads was found to affect package reliability. For example, locating vias at the edge of the die is not desirable because the vias acts as initiation point for delamination and moisture-induced failure. Through die shear testing, soldermask B demonstrated higher adhesion properties compared to soldermask A across several packaging materials and enhanced the overall package reliability in terms of both MST and T/C performance. Both MST JEDEC level 1 and the T/C of 'B' and 'C' at 1000 cycles have been achieved through design and package material optimization.

  7. The Soft X-ray Telescope for Solar-A - Design evolution and lessons learned

    Science.gov (United States)

    Bruner, Marilyn E.

    1992-01-01

    The Japanese Solar-A satellite mission's Soft X-ray Telescope uses grazing-incidence optics, a CCD detector, and a pair of filter wheels for wavelength selection. A coaxially-mounted visible-light lens furnished sunspot and magnetic plage images, together with aspect information which aids in aligning the soft X-ray images with those from the satellite's Hard X-ray Telescope. Instrument electronics are microprocessor-based, and imbedded in a tightly integrated distributed system. Control software is divided between the instrument microprocessor and the spacecraft control computer.

  8. High-Performance Schools: Affordable Green Design for K-12 Schools; Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Plympton, P.; Brown, J.; Stevens, K.

    2004-08-01

    Schools in the United States spend $7.8 billion on energy each year-more than the cost of computers and textbooks combined, according to a 2003 report from the National Center for Education Statistics. The U.S. Department of Energy (DOE) estimates that these high utility bills could be reduced as much as 25% if schools adopt readily available high performance design principles and technologies. Accordingly, hundreds of K-12 schools across the country have made a commitment to improve the learning and teaching environment of schools while saving money and energy and protecting the environment. DOE and its public- and private-sector partners have developed Energy Design Guidelines for High Performance Schools, customized for nine climate zones in U.S. states and territories. These design guidelines provide information for school decision makers and design professionals on the advantages of energy efficiency and renewable energy designs and technologies. With such features as natural day lighting, efficient electric lights, water conservation, and renewable energy, schools in all types of climates are proving that school buildings, and the students and teachers who occupy them, are indeed high performers. This paper describes high performance schools from each of the nine climate zones associated with the Energy Design Guidelines. The nine case studies focus on the high performance design strategies implemented in each school, as well as the cost savings and benefits realized by students, faculty, the community, and the environment.

  9. Microeconomics of advanced process window control for 50-nm gates

    Science.gov (United States)

    Monahan, Kevin M.; Chen, Xuemei; Falessi, Georges; Garvin, Craig; Hankinson, Matt; Lev, Amir; Levy, Ady; Slessor, Michael D.

    2002-07-01

    Fundamentally, advanced process control enables accelerated design-rule reduction, but simple microeconomic models that directly link the effects of advanced process control to profitability are rare or non-existent. In this work, we derive these links using a simplified model for the rate of profit generated by the semiconductor manufacturing process. We use it to explain why and how microprocessor manufacturers strive to avoid commoditization by producing only the number of dies required to satisfy the time-varying demand in each performance segment. This strategy is realized using the tactic known as speed binning, the deliberate creation of an unnatural distribution of microprocessor performance that varies according to market demand. We show that the ability of APC to achieve these economic objectives may be limited by variability in the larger manufacturing context, including measurement delays and process window variation.

  10. Breeder design for enhanced performance and safety characteristics

    International Nuclear Information System (INIS)

    Fischer, G.J.; Atefi, B.; Yang, J.W.; Galperin, A.; Segev, M.

    1980-01-01

    A fast breeder reactor design has been created which offers a considerably extended fuel cycle and excellent performance characteristics. An example of a core designed to operate on a ten-year fuel cycle is described in some detail. Use of metal fuel along with a moderator such as beryllium oxide dispersed throughout the core provides both design flexibility and safety advantages such as a strong Doppler feedback and limited sodium void reactivity gain. Local power variations are small for the entire cycle; control requirements are also modest, and fuel cycle costs are low

  11. Design, Construction and Performance Evaluation of Multiple ...

    African Journals Online (AJOL)

    The complex casting machine has been designed to perform the following techniques: gravity casting, stir casting, squeeze casting, vacuum casting, compocasting and thixoforming. All these casting techniques have been integrated into this complex casting machine as different units which work with the help of automation.

  12. Energy-Performance-Based Design-Build Process: Strategies for Procuring High-Performance Buildings on Typical Construction Budgets: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Scheib, J.; Pless, S.; Torcellini, P.

    2014-08-01

    NREL experienced a significant increase in employees and facilities on our 327-acre main campus in Golden, Colorado over the past five years. To support this growth, researchers developed and demonstrated a new building acquisition method that successfully integrates energy efficiency requirements into the design-build requests for proposals and contracts. We piloted this energy performance based design-build process with our first new construction project in 2008. We have since replicated and evolved the process for large office buildings, a smart grid research laboratory, a supercomputer, a parking structure, and a cafeteria. Each project incorporated aggressive efficiency strategies using contractual energy use requirements in the design-build contracts, all on typical construction budgets. We have found that when energy efficiency is a core project requirement as defined at the beginning of a project, innovative design-build teams can integrate the most cost effective and high performance efficiency strategies on typical construction budgets. When the design-build contract includes measurable energy requirements and is set up to incentivize design-build teams to focus on achieving high performance in actual operations, owners can now expect their facilities to perform. As NREL completed the new construction in 2013, we have documented our best practices in training materials and a how-to guide so that other owners and owner's representatives can replicate our successes and learn from our experiences in attaining market viable, world-class energy performance in the built environment.

  13. Design and Implementation of a Digital Angular Rate Sensor

    Directory of Open Access Journals (Sweden)

    Zhen Peng

    2010-10-01

    Full Text Available With the aim of detecting the attitude of a rotating carrier, the paper presents a novel, digital angular rate sensor. The sensor consists of micro-sensing elements (gyroscope and accelerometer, signal processing circuit and micro-processor (DSP2812. The sensor has the feature of detecting three angular rates of a rotating carrier at the same time. The key techniques of the sensor, including sensing construction, sensing principles, and signal processing circuit design are presented. The test results show that the sensor can sense rolling, pitch and yaw angular rate at the same time and the measurement error of yaw (or pitch angular rate and rolling rate of the rotating carrier is less than 0.5%.

  14. Design of High Performance Permanent-Magnet Synchronous Wind Generators

    Directory of Open Access Journals (Sweden)

    Chun-Yu Hsiao

    2014-11-01

    Full Text Available This paper is devoted to the analysis and design of high performance permanent-magnet synchronous wind generators (PSWGs. A systematic and sequential methodology for the design of PMSGs is proposed with a high performance wind generator as a design model. Aiming at high induced voltage, low harmonic distortion as well as high generator efficiency, optimal generator parameters such as pole-arc to pole-pitch ratio and stator-slot-shoes dimension, etc. are determined with the proposed technique using Maxwell 2-D, Matlab software and the Taguchi method. The proposed double three-phase and six-phase winding configurations, which consist of six windings in the stator, can provide evenly distributed current for versatile applications regarding the voltage and current demands for practical consideration. Specifically, windings are connected in series to increase the output voltage at low wind speed, and in parallel during high wind speed to generate electricity even when either one winding fails, thereby enhancing the reliability as well. A PMSG is designed and implemented based on the proposed method. When the simulation is performed with a 6 Ω load, the output power for the double three-phase winding and six-phase winding are correspondingly 10.64 and 11.13 kW. In addition, 24 Ω load experiments show that the efficiencies of double three-phase winding and six-phase winding are 96.56% and 98.54%, respectively, verifying the proposed high performance operation.

  15. [The design of a cardiac monitoring and analysing system with low power consumption].

    Science.gov (United States)

    Chen, Zhen-cheng; Ni, Li-li; Zhu, Yan-gao; Wang, Hong-yan; Ma, Yan

    2002-07-01

    The paper deals with a portable analyzing monitor system with liquid crystal display (LCD), which is low in power consumption and suitable for China's specific conditions. Apart from the development of the overall scheme of the system, the paper introduces the design of the hardware and the software. The 80196 single chip microcomputer is used as the central microprocessor to process and real-time electrocardiac signal data. The system have the following functions: five types of arrhythmia analysis, alarm, freeze, and record of automatic paperfeeding. The portable system can be operated by alternate-current (AC) or direct-current (DC). Its hardware circuit is simplified and its software structure is optimized. Multiple low power consumption and LCD unit are adopted in its modular designs.

  16. Computer-Aided Chemical Product Design Framework: Design of High Performance and Environmentally Friendly Refrigerants

    DEFF Research Database (Denmark)

    Cignitti, Stefano; Zhang, Lei; Gani, Rafiqul

    properties and needs should carefully be selected for a given heat pump cycle to ensure that an optimum refrigerant is found? How can cycle performance and environmental criteria be integrated at the product design stage and not in post-design analysis? Computer-aided product design methods enable...... the possibility of designing novel molecules, mixtures and blends, such as refrigerants through a systematic framework (Cignitti et al., 2015; Yunus et al., 2014). In this presentation a computer-aided framework is presented for chemical product design through mathematical optimization. Here, molecules, mixtures...... and blends, are systematically designed through a decomposition based solution method. Given a problem definition, computer-aided molecular design (CAMD) problem is defined, which is formulated into a mixed integer nonlinear program (MINLP). The decomposed solution method then sequentially divides the MINLP...

  17. Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.

    Science.gov (United States)

    Cheng, Li-Fang; Chen, Tung-Chien; Chen, Liang-Gee

    2012-01-01

    Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures--using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 mW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.

  18. In search of design principles for developing digital learning & performance support for a student design task

    NARCIS (Netherlands)

    Bollen, Lars; Van der Meij, Hans; Leemkuil, Henny; McKenney, Susan

    2016-01-01

    A digital learning and performance support environment for university student design tasks was developed. This paper describes on the design rationale, process, and the usage results to arrive at a core set of design principles for the construction of such an environment. We present a collection of

  19. In search of design principles for developing digital learning & performance support for a student design task

    NARCIS (Netherlands)

    Bollen, Lars; van der Meij, Hans; Leemkuil, Hendrik H.; McKenney, Susan

    2015-01-01

    A digital learning and performance support environment for university student design tasks was developed. This paper describes on the design rationale, process, and the usage results to arrive at a core set of design principles for the construction of such an environment. We present a collection of

  20. Embedded Systems Design: Optimization Challenges

    DEFF Research Database (Denmark)

    Pop, Paul

    2005-01-01

    Summary form only given. Embedded systems are everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded systems. Over 99% of the microprocessors produced today are used in embedded systems, and recently the number of embedded systems...