WorldWideScience

Sample records for p-type silicon wafer

  1. Very low surface recombination velocities on p-type silicon wafers passivated with a dielectric with fixed negative charge

    Energy Technology Data Exchange (ETDEWEB)

    Agostinelli, G.; Delabie, A.; Dekkers, H.F.W.; De Wolf, S.; Beaucarne, G. [IMEC vzw, Kapeldreef 75, Leuven (Belgium); Vitanov, P.; Alexieva, Z. [CL SENES, Sofia (Bulgaria)

    2006-11-23

    Surface recombination velocities as low as 10cm/s have been obtained by treated atomic layer deposition (ALD) of Al{sub 2}O{sub 3} layers on p-type CZ silicon wafers. Low surface recombination is achieved by means of field induced surface passivation due to a high density of negative charges stored at the interface. In comparison to a diffused back surface field, an external field source allows for higher band bending, that is, a better performance. While this process yields state of the art results, it is not suited for large-scale production. Preliminary results on an industrially viable, alternative process based on a pseudo-binary system containing Al{sub 2}O{sub 3} are presented, too. With this process, surface recombination velocities of 500-1000cm/s have been attained on mc-Si wafers. (author)

  2. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    Science.gov (United States)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  3. Doping Silicon Wafers with Boron by Use of Silicon Paste

    Institute of Scientific and Technical Information of China (English)

    Yu Gao; Shu Zhou; Yunfan Zhang; Chen Dong; Xiaodong Pi; Deren Yang

    2013-01-01

    In this work we introduce recently developed silicon-paste-enabled p-type doping for silicon.Boron-doped silicon nanoparticles are synthesized by a plasma approach.They are then dispersed in solvents to form silicon paste.Silicon paste is screen-printed at the surface of silicon wafers.By annealing,boron atoms in silicon paste diffuse into silicon wafers.Chemical analysis is employed to obtain the concentrations of boron in silicon nanoparticles.The successful doping of silicon wafers with boron is evidenced by secondary ion mass spectroscopy (SIMS) and sheet resistance measurements.

  4. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers

    Directory of Open Access Journals (Sweden)

    Chun-You Wei

    2013-11-01

    Full Text Available Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  5. Piezoresistance in p-type silicon revisited

    DEFF Research Database (Denmark)

    Richter, Jacob; Pedersen, Jesper; Brandbyge, Mads;

    2008-01-01

    We calculate the shear piezocoefficient pi44 in p-type Si with a 6×6 k·p Hamiltonian model using the Boltzmann transport equation in the relaxation-time approximation. Furthermore, we fabricate and characterize p-type silicon piezoresistors embedded in a (001) silicon substrate. We find that the ...

  6. Review. Industrial silicon wafer solar cells. Status and trends

    Energy Technology Data Exchange (ETDEWEB)

    Aberle, Armin G.; Boreland, Matthew B.; Hoex, Bram; Mueller, Thomas [National Univ. of Singapore (Singapore). Solar Energy Research Institute of Singapore (SERIS)

    2012-11-01

    Crystalline silicon solar cells dominate today's global photovoltaic (PV) market. This paper presents the status and trends of the most important industrial silicon wafer solar cells, ranging from standard p-type homojunction cells to heterojunction cells on n-type wafers. Owing to ongoing technological innovations such as improved surface passivation and the use of increasingly thinner wafers, the trend towards higher cell efficiencies and lower dollar/watt costs is expected to continue during the next 10 years, making silicon wafer based PV modules a moving target for any competing PV technology. (orig.)

  7. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  8. Note: Near infrared interferometric silicon wafer metrology.

    Science.gov (United States)

    Choi, M S; Park, H M; Joo, K N

    2016-04-01

    In this investigation, two near infrared (NIR) interferometric techniques for silicon wafer metrology are described and verified with experimental results. Based on the transparent characteristic of NIR light to a silicon wafer, the fiber based spectrally resolved interferometry can measure the optical thickness of the wafer and stitching low coherence scanning interferometry can reconstruct entire surfaces of the wafer.

  9. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  10. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this one year research project, we propose to do the following four tasks;(1) Design the silicon wafer X-ray mirror demo unit and develop a ray-tracing code to...

  11. ISOTROPIC TEXTURING OF POLYCRYSTALLINE SILICON WAFERS

    Institute of Scientific and Technical Information of China (English)

    L. Wang; H. Shen; Y.F. Hu

    2005-01-01

    An isotropic etching technique of texturing silicon solar cells has been applied to polycrystalline silicon wafers with different acid concentrations. Optimal etching conditions have been determined by etching rate calculation, scanning electron microscope (SEM) image and reflectance measurement. The surface morphology of the textured wafers varies in accordance with the different etchant concentration which in turn leads to the dissimilarity of etching speed. Textured polycrystalline silicon wafer surfaces display randomly located etched pits which can reduce the surface reflection and enhance the light absorption. The special relationship between reflectivity and etching rate was studied. Reflectance measurements show that isotropic texturing is one of the suitable techniques for texturing polycrystalline silicon wafers and benefits solar cells performances.

  12. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this one year research project, we propose to do the following four tasks; (1) Design the silicon wafer X-ray mirror demo unit and develop a ray-tracing code to...

  13. SIMULATION OF HETEROJUNCTION SOLAR CELLS BASED ON p-TYPE SILICON WAFER%p型晶体硅异质结太阳电池光电特性模拟研究

    Institute of Scientific and Technical Information of China (English)

    程雪梅; 孟凡英; 汪建强; 李祥; 黄建华

    2012-01-01

    利用AFORS-HET软件模拟以p型晶体硅为衬底的异质结太阳电池的特性.太阳电池的基本结构为:TCO/n-a-Si∶ H/i-a-Si∶ H/p-c-Si/Ag,通过改变电池材料的特征参量,分析电池输出特性随相关参量变化的规律.结果表明,与ITO相比,以ZnO为透明导电极的电池在短波光和可见光波段光谱响应更强,短路电流密度和电池效率更高.此外,在所建立的电池模型中,限定掺杂型非晶硅层的厚度为10nm,改变本征非晶硅层厚度,模拟研究找到了电池的短路电流、开路电压、填充因子及光电转换效率随本征层厚度变化的规律和最优值,通过模拟研究发现有背场的双面电池比无背场电池的开路电压增加4.8%,最高转换效率达21.25%.%The performance of heterojunction solar cells was investigated in p-type silicon crystalline by using AFORS-HET. From the simulation results, it is found that comparing with using ITO as TCO, the absorption of solar cell with ZnO as its TCO is much stronger in visible light, and the short current(Jsc) is bigger than the former, so the efficiency(Eff) increase. After inserting a thin intrinsic amorphous silicon (a-Si) between the n a-Si and c-Si, the short current and the fill factor both increased rapidly, and the Eff raised. However, the thickness of the intrinsic layer must be strict controlled within 0. 1-1. 0nm in this model. The bifacial heterojunction solar cells with the structure ZnO(80nm)/a-Si n(10nm)/a-Si i(lnm)/c-Si p(0. 3cm)/a-Si i(lnm)/a-Si p+(10nm) was simulated, and the best performance of Eff is 21. 25% .

  14. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers

    OpenAIRE

    Chun-You Wei; Chu-Hsuan Lin; Hao-Tse Hsiao; Po-Chuan Yang; Chih-Ming Wang; Yen-Chih Pan

    2013-01-01

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency ...

  15. Comparing n- and p-type polycrystalline silicon absorbers in thin-film solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Deckers, J. [imec, Kapeldreef 75, B-3001 Heverlee, Leuven (Belgium); ESAT, KU Leuven, Kardinaal Mercierlaan 94, B-3001 Heverlee, Leuven (Belgium); Bourgeois, E. [Institute for Materials Research (IMO), Hasselt University, Wetenschapspark 1, B-3590 Diepenbeek (Belgium); IMOMEC, IMEC vzw, Wetenschapspark 1, B-3590 Diepenbeek (Belgium); Jivanescu, M. [Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200D, B-3001 Heverlee, Leuven (Belgium); Abass, A. [Photonics Research Group (INTEC), Ghent University-imec, Sint-Pietersnieuwstraat 41, B-9000 Ghent (Belgium); Van Gestel, D.; Van Nieuwenhuysen, K.; Douhard, B. [imec, Kapeldreef 75, B-3001 Heverlee, Leuven (Belgium); D' Haen, J.; Nesladek, M.; Manca, J. [Institute for Materials Research (IMO), Hasselt University, Wetenschapspark 1, B-3590 Diepenbeek (Belgium); IMOMEC, IMEC vzw, Wetenschapspark 1, B-3590 Diepenbeek (Belgium); Gordon, I.; Bender, H. [imec, Kapeldreef 75, B-3001 Heverlee, Leuven (Belgium); Stesmans, A. [Department of Physics and Astronomy, University of Leuven, Celestijnenlaan 200D, B-3001 Heverlee, Leuven (Belgium); Mertens, R.; Poortmans, J. [imec, Kapeldreef 75, B-3001 Heverlee, Leuven (Belgium); ESAT, KU Leuven, Kardinaal Mercierlaan 94, B-3001 Heverlee, Leuven (Belgium)

    2015-03-31

    We have investigated fine grained polycrystalline silicon thin films grown by direct chemical vapor deposition on oxidized silicon substrates. More specifically, we analyze the influence of the doping type on the properties of this model polycrystalline silicon material. This includes an investigation of defect passivation and benchmarking of minority carrier properties. In our investigation, we use a variety of characterization techniques to probe the properties of the investigated polycrystalline silicon thin films, including Fourier Transform Photoelectron Spectroscopy, Electron Spin Resonance, Conductivity Activation, and Suns-Voc measurements. Amphoteric silicon dangling bond defects are identified as the most prominent defect type present in these layers. They are the primary recombination center in the relatively lowly doped polysilicon thin films at the heart of the current investigation. In contrast with the case of solar cells based on Czochralski silicon or multicrystalline silicon wafers, we conclude that no benefit is found to be associated with the use of n-type dopants over p-type dopants in the active absorber of the investigated polycrystalline silicon thin-film solar cells. - Highlights: • Comparison of n- and p-type absorbers for thin-film poly-Si solar cells • Extensive characterization of the investigated layers' characteristics • Literature review pertaining the use of n-type and p-type dopants in silicon.

  16. p-Type Quasi-Mono Silicon Solar Cell Fabricated by Ion Implantation

    Directory of Open Access Journals (Sweden)

    Chien-Ming Lee

    2013-01-01

    Full Text Available The p-type quasi-mono wafer is a novel type of silicon material that is processed using a seed directional solidification technique. This material is a promising alternative to traditional high-cost Czochralski (CZ and float-zone (FZ material. Here, we evaluate the application of an advanced solar cell process featuring a novel method of ion implantation on p-type quasi-mono silicon wafer. The ion implantation process has simplified the normal industrial process flow by eliminating two process steps: the removal of phosphosilicate glass (PSG and the junction isolation process that is required after the conventional thermal POCl3 diffusion process. Moreover, the good passivation performance of the ion implantation process improves Voc. Our results show that, after metallization and cofiring, an average cell efficiency of 18.55% can be achieved using 156 × 156 mm p-type quasi-mono silicon wafer. Furthermore, the absolute cell efficiency obtained using this method is 0.47% higher than that for the traditional POCl3 diffusion process.

  17. Microhardness of carbon-doped (111) p-type Czochralski silicon

    Science.gov (United States)

    Danyluk, S.; Lim, D. S.; Kalejs, J.

    1985-01-01

    The effect of carbon on (111) p-type Czochralski silicon is examined. The preparation of the silicon and microhardness test procedures are described, and the equation used to determine microhardness from indentations in the silicon wafers is presented. The results indicate that as the carbon concentration in the silicon increases the microhardness increases. The linear increase in microhardness is the result of carbon hindering dislocation motion, and the effect of temperature on silicon deformation and dislocation mobility is explained. The measured microhardness was compared with an analysis which is based on dislocation pinning by carbon; a good correlation was observed. The Labusch model for the effect of pinning sites on dislocation motion is given.

  18. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  19. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  20. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers.

    Science.gov (United States)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Wood, Barry; Iacopi, Francesca

    2014-08-15

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

  1. Extraction of interface state density and resistivity of suspended p-type silicon nanobridges

    Institute of Scientific and Technical Information of China (English)

    Zhang Jiahong; Liu Qingquan; Ge Yixian; Gu Fang; Li Min; Mao Xiaoli; Cao Hongxia

    2013-01-01

    The evaluation of the influence of the bending deformation of silicon nanobridges on their electrical properties is crucial for sensing and actuating applications.A combined theory/experimental approach for determining the resistivity and the density of interface states of the bending silicon nanobridges is presented.The suspended p-type silicon nanobridge test structures were fabricated from silicon-on-insulator wafers by using a standard CMOS lithography and anisotropic wet etching release process.After that,we measured the resistance of a set of silicon nanobridges versus their length and width under different bias voltages.In conjunction with a theoretical model,we have finally extracted both the interface state density of and resistivity suspended silicon nanobridges under different bending deformations,and found that the resistivity of silicon nanobridges without bending was 9.45 mΩ·cm and the corresponding interface charge density was around 1.7445 × 1013 cm-2.The bending deformation due to the bias voltage slightly changed the resistivity of the silicon nanobridge,however,it significantly changed the distribution of interface state charges,which strongly depends on the intensity of the stress induced by bending deformation.

  2. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  3. The influence of wafer dimensions on the contact wave velocity in silicon wafer bonding

    DEFF Research Database (Denmark)

    Bengtsson, S.; Ljungberg, Karin; Vedde, Jan

    1996-01-01

    The contact wave velocity in silicon wafer bonding is experimentally found to decrease with wafer thickness and to be only weakly dependent on wafer diameter. Wafers of different thicknesses ranging from 270 to 5000 mu m, were dipped in HF:H2O before bonding to give the surfaces hydrophobic...... stored in the material is increased, and the contact wave velocity is decreased. (C) 1996 American Institute of Physics....

  4. Laser Enhanced Hydrogen Passivation of Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Lihui Song

    2015-01-01

    Full Text Available The application of lasers to enable advanced hydrogenation processes with charge state control is explored. Localised hydrogenation is realised through the use of lasers to achieve localised illumination and heating of the silicon material and hence spatially control the hydrogenation process. Improvements in minority carrier lifetime are confirmed in the laser hydrogenated regions using photoluminescence (PL imaging. However with inappropriate laser settings a localised reduction in minority carrier lifetime can result. It is observed that high illumination intensities and rapid cooling are beneficial for achieving improvements in minority carrier lifetimes through laser hydrogenation. The laser hydrogenation process is then applied to finished screen-printed solar cells fabricated on seeded-cast quasi monocrystalline silicon wafers. The passivation of dislocation clusters is observed with clear improvements in quantum efficiency, open circuit voltage, and short circuit current density, leading to an improvement in efficiency of 0.6% absolute.

  5. Wettability investigating on the wet etching textured multicrystalline silicon wafer

    Science.gov (United States)

    Liu, Xiangju; Niu, Yuchao; Zhai, Tongguang; Ma, Yuying; Zhen, Yongtai; Ma, Xiaoyu; Gao, Ying

    2016-02-01

    In order to investigate the wettability properties of multicrystalline silicon (mc-Si), the different surface structures were fabricated on the as-cut p-type multi-wire slurry sawn mc-Si wafers, such as as-cut, polished and etched in various acid solutions. The contact angles and the XRD spectra of these samples were measured. It was noted that both the surface structures and the use of surfactant, such as Tween 80, made a stronger effect on wettability of the Si wafer. Due to the lipophilic groups of Tween 80 combined with the Si atoms while the hydrophilic groups of it were outward, a lipophilic surface of Si changed into a hydrophilic one and the rougher the surface, the stronger the hydrophily. Thus, it is feasible to add an appropriate surfactant into the etching solution during black-Si wafer fabrication for solar cells. In addition, different crystal plains of Si had different dangling bond density, so that their surface energies were different. A surface with higher surface energy could attract more water atoms and its wettability was better. However, the effect of crystal plain on the surface wettability was much weaker than surface morphology.

  6. Electrochemical behaviors of silicon wafers in silica slurry

    Institute of Scientific and Technical Information of China (English)

    Xiaolan Song; Haiping Yang; Xunda Shi; Xi He; Guanzhou Qiu

    2008-01-01

    The electrochemical behaviors of n-type silicon wafers in silica-based slurry were investigated, and the influences of the pH value and solid content of the slurry on the corrosion of silicon wafers were studied by using electrochemical DC polarization and AC impedance techniques. The results revealed that these factors affected the corrosion behaviors of silicon wafers to different degrees and had their suitable parameters that made the maximum corrosion rate of the wafers. The corrosion potential of (100) surface was lower than that of (111), whereas the current density of (100) was much higher than that of (111).

  7. DLTS of p-type Czochralski Si wafers containing processing-induced macropores

    Science.gov (United States)

    Simoen, E.; Depauw, V.; Gordon, I.; Poortmans, J.

    2012-01-01

    The deep levels present in p-type Czochralski silicon with processing-induced macropores in the depletion region have been studied by the deep-level transient (DLT) spectroscopy technique. It is shown that a broad band is present for a bias pulse close to the interface with the Al Schottky contact, which exhibits anomalously slow hole capture and is ascribed to the internal interface states of the macropores. For depths beyond the pore region, other deep levels, associated with point defects—possibly metal contamination during the high-temperature annealing step under H2 ambient--have been observed. The impact of the observed defects on the lifetime of thin-film solar cells, fabricated using macropore-based layer transfer is discussed. Finally, it is shown that the presence of pores in the depletion region, which also affects the DLT-spectrum, alters the capacitance-voltage characteristics.

  8. Investigations of nanoreactors on the basis of p-type porous silicon: Electron structure and phase composition

    Energy Technology Data Exchange (ETDEWEB)

    Lenshin, A.S. [Voronezh State University, Solid State Physics and Nanostructures Department, Universitetskaya pl. 1, Voronezh 394006 (Russian Federation); Kashkarov, V.M., E-mail: kash@phys.vsu.ru [Voronezh State University, Solid State Physics and Nanostructures Department, Universitetskaya pl. 1, Voronezh 394006 (Russian Federation); Spivak, Yu. M. [SPbGETU ' LETI' , Department of Microelectronics (Russian Federation); Moshnikov, V.A., E-mail: vamoshnikov@mail.ru [SPbGETU ' LETI' , Department of Microelectronics (Russian Federation)

    2012-08-15

    Investigations of the electron structure and phase composition of the surface layers in porous silicon with a developed system of nanopores were made with the use of ultrasoft X-ray spectroscopy and X-ray photoelectron spectroscopy. The samples of porous silicon were obtained on the substrates with p-type conductivity under different modes of electrochemical etching. Porous surface layer represents a system of weakly connected pores oriented mainly perpendicular to the surface of silicon wafer. The mean transverse pore dimension is of {approx}50 nm. Silicon dioxide and sub-oxide were found in porous layer. We assume that these phases cover pores surface thus providing a possibility of the use of the structures as nanoreactors. -- Highlights: Black-Right-Pointing-Pointer Nanoporous silicon layers were obtained. Black-Right-Pointing-Pointer A system of weakly connected pores was detected. Black-Right-Pointing-Pointer Electron structure and phase composition of the surface layers in porous silicon were investigated.

  9. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  10. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Science.gov (United States)

    Bergauer, T.; Dragicevic, M.; König, A.; Hacker, J.; Bartl, U.

    2016-09-01

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  11. Precipitation of Cu and Ni in n- and p-type Czochralski-grown silicon characterized by photoluminescence imaging

    Science.gov (United States)

    Sun, Chang; Nguyen, Hieu T.; Rougieux, Fiacre E.; Macdonald, Daniel

    2017-02-01

    Photoluminescence (PL) images and micro-PL maps were taken on Cu- or Ni-doped monocrystalline silicon wafers, to investigate the distribution of the metal precipitates. Several n-type and p-type wafers were used in which Cu or Ni were introduced in the starting melt of the ingots and precipitated during the ingot cooling (as opposed to surface contamination). The micro-PL mapping allowed investigation of the metal precipitates with a higher spatial resolution. Markedly different precipitation patterns were observed in n- and p-type samples: in both Cu- and Ni-doped n-type samples, circular central regions and edge regions were observed. In these regions, particles were distributed randomly and homogeneously. In the p-type Cu-doped and Ni-doped samples, by contrast, the precipitates occurred in lines along orientations. The difference in the precipitation behaviour in n- and p-type samples is conjectured to be caused by different concentrations of self-interstitials and vacancies remaining in the crystal during the ingot cooling: there are more vacancies in the n-type ingots but more interstitials in the p-type ingots. The dopant effects on the intrinsic point defect concentrations in silicon crystals and possible precipitation mechanisms are discussed based on the findings in this work and the literature.

  12. P type porous silicon resistivity and carrier transport

    Energy Technology Data Exchange (ETDEWEB)

    Ménard, S., E-mail: samuel.menard@st.com [STMicroelectronics, 10, rue Thalès de Milet, 37071 Tours Cedex 2 (France); Fèvre, A. [STMicroelectronics, 10, rue Thalès de Milet, 37071 Tours Cedex 2 (France); Université François Rabelais de Tours, CNRS, CEA, INSA CVL, GREMAN UMR 7347, Tours (France); Billoué, J.; Gautier, G. [Université François Rabelais de Tours, CNRS, CEA, INSA CVL, GREMAN UMR 7347, Tours (France)

    2015-09-14

    The resistivity of p type porous silicon (PS) is reported on a wide range of PS physical properties. Al/PS/Si/Al structures were used and a rigorous experimental protocol was followed. The PS porosity (P{sub %}) was found to be the major contributor to the PS resistivity (ρ{sub PS}). ρ{sub PS} increases exponentially with P{sub %}. Values of ρ{sub PS} as high as 1 × 10{sup 9} Ω cm at room temperature were obtained once P{sub %} exceeds 60%. ρ{sub PS} was found to be thermally activated, in particular, when the temperature increases from 30 to 200 °C, a decrease of three decades is observed on ρ{sub PS}. Based on these results, it was also possible to deduce the carrier transport mechanisms in PS. For P{sub %} lower than 45%, the conduction occurs through band tails and deep levels in the tissue surrounding the crystallites. When P{sub %} overpasses 45%, electrons at energy levels close to the Fermi level allow a hopping conduction from crystallite to crystallite to appear. This study confirms the potential of PS as an insulating material for applications such as power electronic devices.

  13. Investigation on Adsorption State of Surface Adsorbate on Silicon Wafer

    Institute of Scientific and Technical Information of China (English)

    1999-01-01

    An adsorption kinetics model for adsorbate on the specularly polished silicon wafer was suggested. The mathematical model of preferential adsorption and the mechanism controlling the adsorption state of adsorbate were discussed.

  14. Effect of Etching Time on Optical and Thermal Properties of p-Type Porous Silicon Prepared by Electrical Anodisation Method

    Directory of Open Access Journals (Sweden)

    Kasra Behzad

    2012-01-01

    Full Text Available The porous silicon (PSi layers were formed on p-type silicon (Si wafer. The six samples were anodised electrically with 30 mA/cm2 fixed current density for different etching times. The structural, optical, and thermal properties of porous silicon on silicon substrates were investigated by photoluminescence (PL, photoacoustic spectroscopy (PAS, and UV-Vis-NIR spectrophotometer. The thickness and porosity of the layers were measured using the gravimetric method. The band gap of the samples was measured through the photoluminescence (PL peak and absorption spectra, then they were compared. It shows that band gap value increases by raising the porosity. Photoacoustic spectroscopy (PAS was carried out for measuring the thermal diffusivity (TD of the samples.

  15. Sheet resistance uniformity in drive-in step for different multi-crystalline silicon wafer dispositions

    Energy Technology Data Exchange (ETDEWEB)

    Moussi, A.; Bouhafs, D.; Mahiou, L. [Laboratoire des Cellules Photovoltaiques, Unite de Developpement de la Technologie du Silicium, 2 Bd, Frantz Fanon, B.P. 140, 7 Merveilles Alger (Algeria); Belkaid, M.S. [Dep. Electronique, Faculte de Genie Electrique et Informatique, UMMTO (Algeria)

    2009-09-15

    In this work, we present a study of emitters realized using different configurations of the silicon wafers in the quartz boat. The phosphorous liquid source is sprayed onto p-type multi-crystalline silicon substrates and the drive-in is made at high temperature in a muffle furnace. Three different configurations of the wafers in the boat are tested: separated, back to back and compact block of wafers. A fourth configuration is also used in source-receptor mode. The emitter phosphorous concentration profile is obtained by SIMS analysis. The resulting emitters are characterized by sheet resistance measurements and a comparison is made between the wafers within the same batch and from one batch to another. The uniformity and the standard deviation of the sheet resistance are calculated in each case. The emitter sheet resistance mapping of the wafer set in the middle of the boat for a given process gives a mean R{sub sq} 14.66 {omega}/sq with a standard deviation of 1.76% and uniformity of 18.7%. Standard deviations of 2.116% and 1.559% are obtained for wafers in the batch when using the spaced and compact configurations, respectively. The standard deviation is reduced to 0.68% when the wafers are used in source/receptor mode. A comparison is also made between wafers with different dilution of phosphorous source in ethanol. From these results we can conclude that the compact configuration offers better uniformity and lower standard deviation. Furthermore, when combined with the source-receptor configuration these parameters are significantly improved. This study allows the experimenter to identify the technological parameters of the solar cell emitter manufacturing and target precisely the desired values of the sheet resistance while limiting the number of rejected wafers. (author)

  16. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  17. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  18. Application of neutron transmutation doping method to initially p-type silicon material.

    Science.gov (United States)

    Kim, Myong-Seop; Kang, Ki-Doo; Park, Sang-Jun

    2009-01-01

    The neutron transmutation doping (NTD) method was applied to the initially p-type silicon in order to extend the NTD applications at HANARO. The relationship between the irradiation neutron fluence and the final resistivity of the initially p-type silicon material was investigated. The proportional constant between the neutron fluence and the resistivity was determined to be 2.3473x10(19)nOmegacm(-1). The deviation of the final resistivity from the target for almost all the irradiation results of the initially p-type silicon ingots was at a range from -5% to 2%. In addition, the burn-up effect of the boron impurities, the residual (32)P activity and the effect of the compensation characteristics for the initially p-type silicon were studied. Conclusively, the practical methodology to perform the neutron transmutation doping of the initially p-type silicon ingot was established.

  19. Microstructure studies of the grinding damage in monocrystalline silicon wafers

    Institute of Scientific and Technical Information of China (English)

    ZHANG Yinxia; KANG Renke; GUO Dongming; JIN Zhuji

    2007-01-01

    The depth and nature of the subsurface damage in a silicon wafer will limit the performance of IC components.Damage microstructures of the silicon wafers ground by the #325,#600, and #2000 grinding wheels was analyzed.The results show that many microcracks,fractures, and dislocation rosettes appear in the surface and subsurface of the wafer ground by the #325 grinding wheel.No obvious microstructure change exists.The amorphous layer with a thickness of about 100 nm,microcracks, high density dislocations,and polycrystalline silicon are observed in the subsurface of the wafer ground by the #600 grinding wheel.For the wafer ground by the #2000 grinding wheel,an amorphous layer of about 30 nm thickness,a polycrystalline silicon layer,a few dislocations,and an elastic deformation layer exist.In general,with the decrease in grit size,the material removal mode changes from micro-fracture mode to ductile mode gradually.

  20. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  1. Effective surface passivation of p-type crystalline silicon with silicon oxides formed by light-induced anodisation

    Energy Technology Data Exchange (ETDEWEB)

    Cui, Jie, E-mail: j.cui@unsw.edu.au [School of Photovoltaic and Renewable Energy Engineering, The University of New South Wales, Sydney 2052 (Australia); Grant, Nicholas [Centre for Sustainable Energy Systems, Australian National University, Canberra, A.C.T. 0200 (Australia); Lennon, Alison [School of Photovoltaic and Renewable Energy Engineering, The University of New South Wales, Sydney 2052 (Australia)

    2014-12-30

    Highlights: • The surface passivation by anodic SiO{sub 2} formed by light-induced anodisation is investigated. • The anodic SiO{sub 2} grows lower temperatures with shorter growth times. After annealing in oxygen and then forming gas the effective minority carrier lifetime is increased to 150 μs. • It shows a very low positive Q{sub eff} of 3.4 × 10{sup 11} cm{sup −2}, a moderate D{sub it} of 6 × 10{sup 11} eV{sup −1} cm{sup −2}. • It has a very low leakage current density suggesting its application in solar cell as a functional dielectric. - Abstract: Electronic surface passivation of p-type crystalline silicon by anodic silicon dioxide (SiO{sub 2}) was investigated. The anodic SiO{sub 2} was grown by light-induced anodisation (LIA) in diluted sulphuric acid at room temperature, a process that is significantly less-expensive than thermal oxidation which is widely-used in silicon solar cell fabrication. After annealing in oxygen and then forming gas at 400 °C for 30 min, the effective minority carrier lifetime of 3–5 Ω cm, boron-doped Czochralski silicon wafers with a phosphorus-doped 80 Ω/□ emitter and a LIA anodic SiO{sub 2} formed on the p-type surface was increased by two orders of magnitude to 150 μs. Capacitance–voltage measurements demonstrated a very low positive charge density of 3.4 × 10{sup 11} cm{sup −2} and a moderate density of interface states of 6 × 10{sup 11} eV{sup −1} cm{sup −2}. This corresponded to a silicon surface recombination velocity of 62 cm s{sup −1}, which is comparable with values reported for other anodic SiO{sub 2} films, which required higher temperatures and longer growth times, and significantly lower than oxides grown by chemical vapour deposition techniques. Additionally, a very low leakage current density of 3.5 × 10{sup −10} and 1.6 × 10{sup −9} A cm{sup −2} at 1 and −1 V, respectively, was measured for LIA SiO{sub 2} suggesting its potential application as insulation layer in

  2. Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

    Science.gov (United States)

    Green, Martin A.

    2014-03-01

    Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

  3. Multicrystalline silicon wafers prepared from upgraded metallurgical feedstock

    Energy Technology Data Exchange (ETDEWEB)

    Degoulange, J.; Trassy, C. [SIMAP UMR CNRS, INP Grenoble (France); Perichaud, I.; Martinuzzi, S. [TECSEN UMR CNRS-University Paul Cezanne-Aix, Marseille III (France)

    2008-10-15

    A solution to the problem of the shortage of silicon feedstock used to grow multicrystalline ingots can be the production of a feedstock obtained by the direct purification of upgraded metallurgical silicon by means of a plasma torch. It is found that the dopant concentrations in the material manufactured following this metallurgical route are in the 10{sup 17} cm{sup -3} range. Minority carrier diffusion lengths L{sub n} are close to 35 {mu}m in the raw wafers and increases up to 120 {mu}m after the wafers go through the standard processing steps needed to make solar cells: phosphorus diffusion, aluminium-silicon alloying and hydrogenation by deposition of a hydrogen-rich silicon nitride layer followed by an annealing. L{sub n} values are limited by the presence of residual metallic impurities, mainly slow diffusers like aluminium, and also by the high doping level. (author)

  4. Schottky Contact of Gallium on p-Type Silicon

    Directory of Open Access Journals (Sweden)

    B.P. Modi

    2011-01-01

    Full Text Available The evolution of barrier at Schottky contact and its stabilization to value characterized by the barrier height and unambiguous measurement is still being curiously perused as they hold the key control and manufacture of tailor made Schottky devices for a host of existing and potential for future applications in electronics, optoelectronics and microwave devices. In this context, gallium – silicon Schottky diode has been fabricated and analyzed.

  5. Light-induced degradation in compensated p- and n-type Czochralski silicon wafers

    Science.gov (United States)

    Geilker, Juliane; Kwapil, Wolfram; Rein, Stefan

    2011-03-01

    Light-induced degradation (LID) due to boron-oxygen complex formation seriously diminishes the minority carrier lifetime of p-type Czochralski-grown (Cz) wafers. Depending linearly on the boron concentration NA in uncompensated silicon, the boron-oxygen defect density was suggested to depend on the net doping concentration p0 = NA - ND in compensated p-type samples, containing similar amounts of boron and phosphorus [D. Macdonald, F. Rougieux, A. Cuevas, et al., Journal of Applied Physics 105, 093704 (2009)]. However, this dependency contradicts observations of LID in compensated n-type silicon wafers [T. Schutz-Kuchly, J. Veirman, S. Dubois, et al., Applied Physics Letters 96, 1 (2010)], which are confirmed in this study by investigating the boron-oxygen complex formation on a large variety of compensated p- and n-type samples. In spite of their high boron content, compensated n-type samples may show a less pronounced LID than p-type samples containing less boron. Our experiments indicate that in compensated silicon, the defect concentration is only a function of the compensation ratio RC = (NA + ND)/(NA - ND).

  6. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  7. Porous silicon damage enhanced phosphorus and aluminium gettering of p-type Czochralski silicon

    Energy Technology Data Exchange (ETDEWEB)

    Hassen, M. [Institut National de Recherche Scientifique et Technique, Laboratoire de Photovoltaique et des Semiconducteurs, PB 95 2050 Hammam-Lif (Tunisia); Ben Jaballah, A. [Institut National de Recherche Scientifique et Technique, Laboratoire de Photovoltaique et des Semiconducteurs, PB 95 2050 Hammam-Lif (Tunisia)]. E-mail: gadour2003@yahoo.fr; Hajji, M. [Institut National de Recherche Scientifique et Technique, Laboratoire de Photovoltaique et des Semiconducteurs, PB 95 2050 Hammam-Lif (Tunisia); Rahmouni, H. [Laboratoire de Physique des Semiconducteurs et des Composants Electroniques, Faculte des Sciences de Monastir, Rue de Kairouan, 5000 Monastir (Tunisia); Selmi, A. [Laboratoire de Physique des Semiconducteurs et des Composants Electroniques, Faculte des Sciences de Monastir, Rue de Kairouan, 5000 Monastir (Tunisia); Ezzaouia, H. [Institut National de Recherche Scientifique et Technique, Laboratoire de Photovoltaique et des Semiconducteurs, PB 95 2050 Hammam-Lif (Tunisia)

    2005-12-05

    In this work, porous silicon damage (PSD) is presented as a simple sequence for efficient external purification techniques. The method consists of using thin nanoporous p-type silicon on both sides of the silicon substrates with randomly hemispherical voids. Then, two main sample types are processed. In the first type, thin aluminium layers ({>=}1 {mu}m) are thermally evaporated followed by photo-thermal annealing treatments in N{sub 2} atmosphere at one of several temperatures ranging between 600 and 800 deg. C. In the second type, phosphorus is continually diffused in N{sub 2}/O{sub 2} ambient in a solid phase from POCl{sub 3} solution during heating at one of several temperatures ranging between 750 and 1000 deg. C for 1 h. Hall Effect and Van Der Pauw methods prove the existence of an optimum temperature in the case of phosphorus gettering at 900 deg. C yielding a Hall mobility of about 982 cm{sup 2} V{sup -1} s{sup -1}. However, in the case of aluminium gettering, there is no gettering limit in the as mentioned temperature range. Metal/Si Schottky diodes are elaborated to clarify these improvements. In this study, we demonstrate that enhanced metal solubility model cannot explain the gettering effect. The solid solubility of aluminium is higher than that of P atoms in silicon; however, the device yield confirms the effectiveness of phosphorus as compared to aluminium.

  8. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  9. The wettability between etching solutions and the surface of multicrystalline silicon wafer during metal-assisted chemical etching process

    Science.gov (United States)

    Niu, Y. C.; Liu, Z.; Liu, X. J.; Gao, Y.; Lin, W. L.; Liu, H. T.; Jiang, Y. S.; Ren, X. K.

    2017-01-01

    In order to investigate the wettability of multicrystalline silicon (mc-Si) with the etching solutions during metal-assisted chemical etching process, different surface structures were fabricated on the p-type multi-wire slurry sawn mc-Si wafers, such as as-cut wafers, polished wafers, and wafers etched in different solutions. The contact angles of different etching solutions on the surfaces of the wafers were measured. It was noted that all contact angles of etching solutions were smaller than the corresponding ones of deionized water, but the contact angles of different etching solutions were quite different. Among the contact angles of the etching solutions of AgNO3-HF, H2O2-HF, TMAH and HNO3-HF, the contact angle of TMAH solution was much larger than the others and that of HNO3-HF solution was much smaller. It is suggested that the larger contact angle may lead to an unevenly etching of silicon wafer due to the long retention of big bubbles on the wafers in the etching reaction, which should be paid attention to and overcome.

  10. Biocompatible silicon wafer bonding for biomedical microdevices

    Science.gov (United States)

    Hansford, Derek; Desai, Tejal A.; Tu, Jay K.; Ferrari, Mauro

    1998-03-01

    In this paper,several candidate bonding materials are reviewed for use in biomedical microdevices. These include poly propylmethacrylate (PPMA), poly methylmethacrylate (PMMA), a copolymer of poly methacrylate and two types of silicone gels. They were evaluated based on their cytotoxicity and bond strength, as well as several other qualitative assessments. The cytotoxicity was determined through a cell growth assay protocol in which cells were grown on the various substrate and their growth was compared to cells grown on control substrate. The adhesive strength was assessed by using a pressurized plate test in which the adhesive interface was pressurized to failure. All of the substrate were found to be non-cytotoxic in an inert manner except for the industrial silicone adhesive gel. The adhesive strengths of the various materials are compared to each other and to previously published adhesive strengths. All of the materials were found to have a sufficient bonding strength for biomedical applications, but several other factors were determined that limit the use of each material.

  11. Characterization of micro-strip detectors made with high resistivity n- and p-type Czochralski silicon

    Energy Technology Data Exchange (ETDEWEB)

    Macchiolo, A. [INFN and Universita degli Studi di Florence (Italy)]. E-mail: Anna.Macchiolo@fi.infn.it; Borrello, L. [INFN and Universita degli Studi di Pisa (Italy); Boscardin, M. [ITC-IRST Trento, Povo, Trento (Italy); Bruzzi, M. [INFN and Universita degli Studi di Florence (Italy); Creanza, D. [INFN and Dipartimento Interateneo di Fisica, Bari (Italy); Dalla Betta, G.-F. [ITC-IRST Trento, Povo, Trento (Italy); DePalma, M. [INFN and Dipartimento Interateneo di Fisica, Bari (Italy); Focardi, E. [INFN and Universita degli Studi di Florence (Italy); Manna, N. [INFN and Dipartimento Interateneo di Fisica, Bari (Italy); Menichelli, D. [INFN and Universita degli Studi di Florence (Italy); Messineo, A. [INFN and Universita degli Studi di Pisa (Italy); Piemonte, C. [ITC-IRST Trento, Povo, Trento (Italy); Radicci, V. [INFN and Dipartimento Interateneo di Fisica, Bari (Italy); Ronchin, S. [ITC-IRST Trento, Povo, Trento (Italy); Scaringella, M. [INFN and Universita degli Studi di Florence (Italy); Segneri, G. [INFN and Universita degli Studi di Pisa (Italy); Sentenac, D. [INFN and Universita degli Studi di Pisa (Italy); Zorzi, N. [ITC-IRST Trento, Povo, Trento (Italy)

    2007-04-01

    The results of the pre- and post-irradiation characterization of n- and p-type magnetic Czochralski silicon micro-strip sensors are reported. This work has been carried out within the INFN funded SMART project aimed at the development of radiation-hard semiconductor detectors for the luminosity upgrade of the large Hadron collider (LHC). The detectors have been fabricated at ITC-IRST (Trento, Italy) on 4 in wafers and the layout contains 10 mini-sensors. The devices have been irradiated with 24 GeV/c and 26 MeV protons in two different irradiation campaigns up to an equivalent fluence of 3.4x10{sup 15} 1-MeV n/cm{sup 2}. The post-irradiation results show an improved radiation hardness of the magnetic Czochralski mini-sensors with respect to the reference float-zone sample.

  12. Excellent Passivation and Low Reflectivity Al2O3/TiO2 Bilayer Coatings for n-Wafer Silicon Solar Cells: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Lee, B. G.; Skarp, J.; Malinen, V.; Li, S.; Choi, S.; Branz, H. M.

    2012-06-01

    A bilayer coating of Al2O3 and TiO2 is used to simultaneously achieve excellent passivation and low reflectivity on p-type silicon. This coating is targeted for achieving high efficiency n-wafer Si solar cells, where both passivation and anti-reflection (AR) are needed at the front-side p-type emitter. It could also be valuable for front-side passivation and AR of rear-emitter and interdigitated back contact p-wafer cells. We achieve high minority carrier lifetimes {approx}1 ms, as well as a nearly 2% decrease in absolute reflectivity, as compared to a standard silicon nitride AR coating.

  13. Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

    Science.gov (United States)

    Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.; Mehdi, Imran; Thomas, Bertrand

    2013-01-01

    Submillimeter heterodyne instruments play a critical role in addressing fundamental questions regarding the evolution of galaxies as well as being a crucial tool in planetary science. To make these instruments compatible with small platforms, especially for the study of the outer planets, or to enable the development of multi-pixel arrays, it is essential to reduce the mass, power, and volume of the existing single-pixel heterodyne receivers. Silicon micromachining technology is naturally suited for making these submillimeter and terahertz components, where precision and accuracy are essential. Waveguide and channel cavities are etched in a silicon bulk material using deep reactive ion etching (DRIE) techniques. Power amplifiers, multiplier and mixer chips are then integrated and the silicon pieces are stacked together to form a supercompact receiver front end. By using silicon micromachined packages for these components, instrument mass can be reduced and higher levels of integration can be achieved. A method is needed to assemble accurately these silicon pieces together, and a technique was developed here using etched pockets and silicon pins to align two wafers together.

  14. Kinetics of self-interstitials reactions in p-type silicon irradiated with alpha particles

    Energy Technology Data Exchange (ETDEWEB)

    Makarenko, L.F., E-mail: makarenko@bsu.by [Department of Applied Mathematics and Computer Science, Belarusian State University, Independence Ave. 4, 220030 Minsk (Belarus); Moll, M. [CERN, Geneva (Switzerland); Evans-Freeman, J.H. [University of Canterbury, Christchurch (New Zealand); Lastovski, S.B.; Murin, L.I.; Korshunov, F.P. [Scientific-Practical Materials Research Centre of NAS of Belarus, Minsk (Belarus)

    2012-08-01

    New findings on the self-interstitial migration in p-type silicon are presented. They are based on experimental studies of the formation kinetics of defects related to interstitial carbon after irradiation with alpha particles. The main parameters characterizing the interaction rate of silicon self-interstitials with substitutional carbon atoms have been determined. A preliminary interpretation of the experimental data is given. The interpretation takes into account different diffusivities of self-interstitials in their singly and doubly ionized states.

  15. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  16. Switchable static friction of piezoelectric composite—silicon wafer contacts

    Science.gov (United States)

    van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

    2013-04-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

  17. A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

    Science.gov (United States)

    Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

    2012-07-01

    We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

  18. Selected applications of photothermal and photoluminescence heterodyne techniques for process control in silicon wafer manufacturing

    Science.gov (United States)

    Ehlert, Andreas; Kerstan, Michael; Lundt, Holger; Huber, Anton; Helmreich, Dieter; Geiler, Hans-Dieter; Karge, Harald; Wagner, Matthias

    1997-02-01

    Two noncontact laser-based heterodyne techniques, photothermal heterodyne (PTH) and photoluminescence heterodyne (PLH), are introduced and applied to processing and quality control in silicon wafer manufacturing. The crystallographic characteristics of process-induced defects in silicon wafers are suitable for the application of PTH and PLH techniques, which are demonstrated on selected examples from different steps of silicon wafer production. Both PLH and PTH techniques meet the demand for nondestructive and on-line-suitable measurement in the semiconductor industry.

  19. P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

    Science.gov (United States)

    Adam, W.; Bergauer, T.; Brondolin, E.; Dragicevic, M.; Friedl, M.; Frühwirth, R.; Hoch, M.; Hrubec, J.; König, A.; Steininger, H.; Waltenberger, W.; Alderweireldt, S.; Beaumont, W.; Janssen, X.; Lauwers, J.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Beghin, D.; Brun, H.; Clerbaux, B.; Delannoy, H.; De Lentdecker, G.; Fasanella, G.; Favart, L.; Goldouzian, R.; Grebenyuk, A.; Karapostoli, G.; Lenzi, Th.; Léonard, A.; Luetic, J.; Postiau, N.; Seva, T.; Vanlaer, P.; Vannerom, D.; Wang, Q.; Zhang, F.; Abu Zeid, S.; Blekman, F.; De Bruyn, I.; De Clercq, J.; D'Hondt, J.; Deroover, K.; Lowette, S.; Moortgat, S.; Moreels, L.; Python, Q.; Skovpen, K.; Van Mulders, P.; Van Parijs, I.; Bakhshiansohi, H.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Delaere, C.; Delcourt, M.; De Visscher, S.; Francois, B.; Giammanco, A.; Jafari, A.; Komm, M.; Krintiras, G.; Lemaitre, V.; Magitteri, A.; Mertens, A.; Michotte, D.; Musich, M.; Piotrzkowski, K.; Quertenmont, L.; Szilasi, N.; Vidal Marono, M.; Wertz, S.; Beliy, N.; Caebergs, T.; Daubie, E.; Hammad, G. H.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Eerola, P.; Tuuva, T.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Vander Donckt, M.; Viret, S.; Agram, J.-L.; Andrea, J.; Bloch, D.; Bonnin, C.; Brom, J.-M.; Chabert, E.; Chanon, N.; Charles, L.; Conte, E.; Fontaine, J.-Ch.; Gross, L.; Hosselet, J.; Jansova, M.; Tromson, D.; Autermann, C.; Feld, L.; Karpinski, W.; Kiesel, K. M.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Pierschel, G.; Preuten, M.; Rauch, M.; Schael, S.; Schomakers, C.; Schulz, J.; Schwering, G.; Wlochal, M.; Zhukov, V.; Pistone, C.; Fluegge, G.; Kuensken, A.; Pooth, O.; Stahl, A.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garay Garcia, J.; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schuetze, P.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Lapsien, T.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; De Boer, W.; Butz, E.; Caselle, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmayer, A.; Kudella, S.; Muller, Th.; Simonis, H. J.; Steck, P.; Weber, M.; Weiler, Th.; Anagnostou, G.; Asenov, P.; Assiouras, P.; Daskalakis, G.; Kyriakis, A.; Loukas, D.; Paspalaki, L.; Siklér, F.; Veszprémi, V.; Bhardwaj, A.; Dalal, R.; Jain, G.; Ranjan, K.; Bakhshiansohl, H.; Behnamian, H.; Khakzad, M.; Naseri, M.; Cariola, P.; Creanza, D.; De Palma, M.; De Robertis, G.; Fiore, L.; Franco, M.; Loddo, F.; Silvestris, L.; Maggi, G.; Martiradonna, S.; My, S.; Selvaggi, G.; Albergo, S.; Cappello, G.; Chiorboli, M.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Saizu, M. A.; Tricomi, A.; Tuve, C.; Barbagli, G.; Brianzi, M.; Ciaranfi, R.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Latino, G.; Lenzi, P.; Meschini, M.; Paoletti, S.; Russo, L.; Scarlini, E.; Sguazzoni, G.; Strom, D.; Viliani, L.; Ferro, F.; Lo Vetere, M.; Robutti, E.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R. A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Nodari, B.; Riceputi, E.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Arezzini, S.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ciampa, A.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Magazzu, G.; Martini, L.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Raffaelli, F.; Rizzi, A.; Savoy-Navarro, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Bellan, R.; Costa, M.; Covarelli, R.; Da Rocha Rolo, M.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Mazza, G.; Migliore, E.; Monteil, E.; Pacher, L.; Ravera, F.; Solano, A.; Fernandez, M.; Gomez, G.; Jaramillo Echeverria, R.; Moya, D.; Gonzalez Sanchez, F. J.; Vila, I.; Virto, A. L.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bianchi, G.; Blanchot, G.; Bonnaud, J.; Caratelli, A.; Ceresa, D.; Christiansen, J.; Cichy, K.; Daguin, J.; D'Auria, A.; Detraz, S.; Deyrail, D.; Dondelewski, O.; Faccio, F.; Frank, N.; Gadek, T.; Gill, K.; Honma, A.; Hugo, G.; Jara Casas, L. M.; Kaplon, J.; Kornmayer, A.; Kottelat, L.; Kovacs, M.; Krammer, M.; Lenoir, P.; Mannelli, M.; Marchioro, A.; Marconi, S.; Mersi, S.; Martina, S.; Michelis, S.; Moll, M.; Onnela, A.; Orfanelli, S.; Pavis, S.; Peisert, A.; Pernot, J.-F.; Petagna, P.; Petrucciani, G.; Postema, H.; Rose, P.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Vichoudis, P.; Verlaat, B.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.-C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Jacob, J.; Seif El Nasr-Storey, S.; Cole, J.; Hoad, C.; Hobson, P.; Morton, A.; Reid, I. D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Hall, G.; James, T.; Magnan, A.-M.; Pesaresi, M.; Raymond, D. M.; Uchida, K.; Garabedian, A.; Heintz, U.; Narain, M.; Nelson, J.; Sagir, S.; Speer, T.; Swanson, J.; Tersegno, D.; Watson-Daniels, J.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B. R.; Gerosa, R.; Sharma, V.; Vartak, A.; Yagil, A.; Zevi Della Porta, G.; Dutta, V.; Gouskos, L.; Incandela, J.; Kyre, S.; Mullin, S.; Patterson, A.; Qu, H.; White, D.; Dominguez, A.; Bartek, R.; Cumalat, J. P.; Ford, W. T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S. R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J. N.; Canepa, A.; Cheung, H. W. K.; Chramowicz, J.; Christian, D.; Cooper, W. E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Lei, C. M.; Lipton, R.; Lopes De Sá, R.; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D. R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Evdokimov, O.; Gerber, C. E.; Hofman, D. J.; Makauda, S.; Mills, C.; Sandoval Gonzalez, I. D.; Alimena, J.; Antonelli, L. J.; Francis, B.; Hart, A.; Hill, C. S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D. H.; Shi, X.; Tan, P.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Bloom, K.; Claes, D. R.; Fangmeier, C.; Gonzalez Suarez, R.; Monroy, J.; Siado, J.; Hahn, K.; Sevova, S.; Sung, K.; Trovato, M.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Ramirez Vargas, J. E.; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K. M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; Betchart, B.; Covarelli, R.; Demina, R.; Hindrichs, O.; Petrillo, G.; Eusebi, R.; Osipenkov, I.; Perloff, A.; Ulmer, K. A.

    2017-06-01

    The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. This paper describes the main measurement results and conclusions that motivated this decision.

  20. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  1. Characteristics of Si+/B+ dual implanted silicon wafers

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Thin p+ layers with good electrical properties were fabricated by RTA (rapid thermal annealing) with post-FA (furance annealing) of Si+/B+ dual implanted silicon wafers. The electrical and structural characteristics of thin p+ layers have been measured by FPP (four-point probe), SRP (spreading resistance probe), RBS/channelling. Optimizing the implantation and annealing processes, especially using the thermal cycle of RTA followed by FA, shallow p+n junctions can be fabricated, which shows excellent I-V characteristics with revers-bias leakage current densities of 1.8?nA/cm2 at -1.4?V.

  2. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  3. Gated Silicon Drift Detector Fabricated from a Low-Cost Silicon Wafer

    Directory of Open Access Journals (Sweden)

    Hideharu Matsuura

    2015-05-01

    Full Text Available Inexpensive high-resolution silicon (Si X-ray detectors are required for on-site surveys of traces of hazardous elements in food and soil by measuring the energies and counts of X-ray fluorescence photons radially emitted from these elements. Gated silicon drift detectors (GSDDs are much cheaper to fabricate than commercial silicon drift detectors (SDDs. However, previous GSDDs were fabricated from \\(10\\-k\\(\\Omega \\cdot\\cm Si wafers, which are more expensive than \\(2\\-k\\(\\Omega \\cdot\\cm Si wafers used in commercial SDDs. To fabricate cheaper portable X-ray fluorescence instruments, we investigate GSDDs formed from \\(2\\-k\\(\\Omega \\cdot\\cm Si wafers. The thicknesses of commercial SDDs are up to \\(0.5\\ mm, which can detect photons with energies up to \\(27\\ keV, whereas we describe GSDDs that can detect photons with energies of up to \\(35\\ keV. We simulate the electric potential distributions in GSDDs with Si thicknesses of \\(0.5\\ and \\(1\\ mm at a single high reverse bias. GSDDs with one gate pattern using any resistivity Si wafer can work well for changing the reverse bias that is inversely proportional to the resistivity of the Si wafer.

  4. Dual ohmic contact to N- and P-type silicon carbide

    Science.gov (United States)

    Okojie, Robert S. (Inventor)

    2013-01-01

    Simultaneous formation of electrical ohmic contacts to silicon carbide (SiC) semiconductor having donor and acceptor impurities (n- and p-type doping, respectively) is disclosed. The innovation provides for ohmic contacts formed on SiC layers having n- and p-doping at one process step during the fabrication of the semiconductor device. Further, the innovation provides a non-discriminatory, universal ohmic contact to both n- and p-type SiC, enhancing reliability of the specific contact resistivity when operated at temperatures in excess of 600.degree. C.

  5. CCE measurements and annealing studies on proton-irradiated p-type MCz silicon diodes

    CERN Document Server

    Hoedlmoser, H; Köhler, M; Nordlund, H

    2007-01-01

    Magnetic Czochralski (MCz) silicon has recently been investigated for the development of radiation tolerant detectors for future high-luminosity HEP experiments. A study of p-type MCz Silicon diodes irradiated with protons up to a fluence of has been performed by means of Charge Collection Efficiency (CCE) measurements as well as standard CV/IV characterizations. The changes of CCE, full depletion voltage and leakage current as a function of fluence are reported. A subsequent annealing study of the irradiated detectors shows an increase in effective doping concentration and a decrease in the leakage current, whereas the CCE remains basically unchanged. Two different series of detectors have been compared differing in the implantation dose of p-spray isolation as well as effective doping concentration (Neff) of the p-type bulk presumably due to a difference in thermal donor (TD) activation during processing. The series with the higher concentration of TDs shows a delayed reverse annealing of Neff after irradia...

  6. Superparamagnetic iron oxide nanoparticle attachment on array of micro test tubes and microbeakers formed on p-type silicon substrate for biosensor applications

    Science.gov (United States)

    Ghoshal, Sarmishtha; Ansar, Abul Am; Raja, Sufi O.; Jana, Arpita; Bandyopadhyay, Nil R.; Dasgupta, Anjan K.; Ray, Mallar

    2011-10-01

    A uniformly distributed array of micro test tubes and microbeakers is formed on a p-type silicon substrate with tunable cross-section and distance of separation by anodic etching of the silicon wafer in N, N-dimethylformamide and hydrofluoric acid, which essentially leads to the formation of macroporous silicon templates. A reasonable control over the dimensions of the structures could be achieved by tailoring the formation parameters, primarily the wafer resistivity. For a micro test tube, the cross-section (i.e., the pore size) as well as the distance of separation between two adjacent test tubes (i.e., inter-pore distance) is typically approximately 1 μm, whereas, for a microbeaker the pore size exceeds 1.5 μm and the inter-pore distance could be less than 100 nm. We successfully synthesized superparamagnetic iron oxide nanoparticles (SPIONs), with average particle size approximately 20 nm and attached them on the porous silicon chip surface as well as on the pore walls. Such SPION-coated arrays of micro test tubes and microbeakers are potential candidates for biosensors because of the biocompatibility of both silicon and SPIONs. As acquisition of data via microarray is an essential attribute of high throughput bio-sensing, the proposed nanostructured array may be a promising step in this direction.

  7. Superparamagnetic iron oxide nanoparticle attachment on array of micro test tubes and microbeakers formed on p-type silicon substrate for biosensor applications

    Directory of Open Access Journals (Sweden)

    Raja Sufi

    2011-01-01

    Full Text Available Abstract A uniformly distributed array of micro test tubes and microbeakers is formed on a p-type silicon substrate with tunable cross-section and distance of separation by anodic etching of the silicon wafer in N, N-dimethylformamide and hydrofluoric acid, which essentially leads to the formation of macroporous silicon templates. A reasonable control over the dimensions of the structures could be achieved by tailoring the formation parameters, primarily the wafer resistivity. For a micro test tube, the cross-section (i.e., the pore size as well as the distance of separation between two adjacent test tubes (i.e., inter-pore distance is typically approximately 1 μm, whereas, for a microbeaker the pore size exceeds 1.5 μm and the inter-pore distance could be less than 100 nm. We successfully synthesized superparamagnetic iron oxide nanoparticles (SPIONs, with average particle size approximately 20 nm and attached them on the porous silicon chip surface as well as on the pore walls. Such SPION-coated arrays of micro test tubes and microbeakers are potential candidates for biosensors because of the biocompatibility of both silicon and SPIONs. As acquisition of data via microarray is an essential attribute of high throughput bio-sensing, the proposed nanostructured array may be a promising step in this direction.

  8. Empirical model predicting the layer thickness and porosity of p-type mesoporous silicon

    Science.gov (United States)

    Wolter, Sascha J.; Geisler, Dennis; Hensen, Jan; Köntges, Marc; Kajari-Schröder, Sarah; Bahnemann, Detlef W.; Brendel, Rolf

    2017-04-01

    Porous silicon is a promising material for a wide range of applications because of its versatile layer properties and the convenient preparation by electrochemical etching. Nevertheless, the quantitative dependency of the layer thickness and porosity on the etching process parameters is yet unknown. We have developed an empirical model to predict the porosity and layer thickness of p-type mesoporous silicon prepared by electrochemical etching. The impact of the process parameters such as current density, etching time and concentration of hydrogen fluoride is evaluated by ellipsometry. The main influences on the porosity of the porous silicon are the current density, the etching time and their product while the etch rate is dominated by the current density, the concentration of hydrogen fluoride and their product. The developed model predicts the resulting layer properties of a certain porosification process and can, for example be used to enhance the utilization of the employed chemicals.

  9. Delineation of Crystalline Extended Defects on Multicrystalline Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Mohamed Fathi

    2007-01-01

    Full Text Available We have selected Secco and Yang etch solutions for the crystalline defect delineation on multicrystalline silicon (mc-Si wafers. Following experimentations and optimization of Yang and Secco etching process parameters, we have successfully revealed crystalline extended defects on mc-Si surfaces. A specific delineation process with successive application of Yang and Secco agent on the same sample has proved the increased sensitivity of Secco etch to crystalline extended defects in mc-Si materials. The exploration of delineated mc-Si surfaces indicated that strong dislocation densities are localized mainly close to the grain boundaries and on the level of small grains in size (below 1 mm. Locally, we have observed the formation of several parallel dislocation lines, perpendicular to the grain boundaries. The overlapping of several dislocations lines has revealed particular forms for etched pits of dislocations.

  10. Fabrication of PIN diode detectors on thinned silicon wafers

    CERN Document Server

    Ronchin, Sabina; Dalla Betta, Gian Franco; Gregori, Paolo; Guarnieri, Vittorio; Piemonte, Claudio; Zorzi, Nicola

    2004-01-01

    Thin substrates are one of the possible choices to provide radiation hard detectors for future high-energy physics experiments. Among the advantages of thin detectors are the low full depletion voltage, even after high particle fluences, the improvement of the tracking precision and momentum resolution and the reduced material budget. In the framework of the CERN RD50 Collaboration, we have developed p-n diode detectors on membranes obtained by locally thinning the silicon substrate by means of tetra-methyl ammonium hydroxide etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 57 and 99mum thick membranes. They have been tested, showing a very low leakage current ( less than 0.4nA/cm**2) and, as expected, a very low depletion voltage ( less than 1V for the 57mum membrane). The paper describes the technological approach used for devices fabrication and reports selected results from the electrical characterization.

  11. Electrochemical behavior and polishing properties of silicon wafer in alkaline slurry with abrasive CeO2

    Institute of Scientific and Technical Information of China (English)

    SONG Xiao-lan; XU Da-yu; ZHANG Xiao-wei; SHI Xun-da; JIANG Nan; QIU Guan-zhou

    2008-01-01

    The electrochemical behavior of silicon wafer in alkaline slurry with nano-sized CeO2 abrasive was investigated. The variations of corrosion potential (φcorr) and corrosion current density (Jcorr) of the P-type (100) silicon wafer with the slurry pH value and the concentration of abrasive CeO2 were studied by polarization curve technologies. The dependence of the polishing rate on the pH and the concentration of CeO2 in slurries during chemical mechanical polishing(CMP) were also studied. It is discovered that there is a large change of φcorr and Jcorr when slurry pH is altered and the Jcorr reaches the maximum (1.306 μA/cm2) at pH 10.5 when the material removal rate(MRR) comes to the fastest value. The Jcorr increases gradually from 0.994 μA/cm2 with 1% CeO2 to 1.304 μA/cm2 with 3% CeO2 and reaches a plateau with the further increase of CeO2 concentration. There is a considerable MRR in the slurry with 3% CeO2 at pH 10.5. The coherence between Jcorr and MRR elucidates that the research on the electrochemical behavior of silicon wafers in the alkaline slurry could offer theoretic guidance on silicon polishing rate and ensure to adjust optimal components of slurry.

  12. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  13. Use of hexamethyldisiloxane for p-type microcrystalline silicon oxycarbide layers

    Directory of Open Access Journals (Sweden)

    Goyal Prabal

    2016-01-01

    Full Text Available The use of hexamethyldisiloxane (HMDSO as an oxygen source for the growth of p-type silicon-based layers deposited by Plasma Enhanced Chemical Vapor Deposition is evaluated. The use of this source led to the incorporation of almost equivalent amounts of oxygen and carbon, resulting in microcrystalline silicon oxycarbide thin films. The layers were examined with characterisation techniques including Spectroscopic Ellipsometry, Dark Conductivity, Fourier Transform Infrared Spectroscopy, Secondary Ion Mass Spectrometry and Transmission Electron Microscopy to check material composition and structure. Materials studies show that the refractive indices of the layers can be tuned over the range from 2.5 to 3.85 (measured at 600 nm and in-plane dark conductivities over the range from 10-8 S/cm to 1 S/cm, suggesting that these doped layers are suitable for solar cell applications. The p-type layers were tested in single junction amorphous silicon p-i-n type solar cells.

  14. Evolution of grain structures during directional solidification of silicon wafers

    Science.gov (United States)

    Lin, H. K.; Wu, M. C.; Chen, C. C.; Lan, C. W.

    2016-04-01

    The evolution of grain structures, especially the types of grain boundaries (GBs), during directional solidification is crucial to the electrical properties of multicrystalline silicon used for solar cells. To study this, the electric molten zone crystallization (EMZC) of silicon wafers at different drift speeds from 2 to 6 mm/min was considered. It was found that orientation was dominant at the lower drift velocity, while orientation at the higher drift velocity. Most of the non-∑GBs tended to align with the thermal gradient, but some tilted toward the unfavorable grains having higher interfacial energies. On the other hand, the tilted ∑3GBs tended to decrease during grain competition, except at the higher speed, where the twin nucleation became frequent. The competition of grains separated by ∑GBs could be viewed as the interactions of GBs that two coherent ∑3n GBs turned into one ∑3nGB following certain relations as reported before. On the other hand, when ∑ GBs met non-∑ GBs, the non-∑ GBs remained which explained the decrease of ∑ GBs at the lower speed.

  15. About the Nature of Electroluminescence Centers in Plastically Deformed Crystals of p-type Silicon

    Directory of Open Access Journals (Sweden)

    B.V. Pavlyk

    2015-10-01

    Full Text Available The paper describes research of dislocation electroluminescence of single crystal p-type silicon with a high concentration of dislocations on the surface (111. It is shown the reaction of the luminescence spectra and capacitive-modulation spectra of samples after high-temperature annealing in an atmosphere of flowing oxygen. The analysis of the results lets us to establish the nature of recombination centers and their reorganization under high-temperature annealing. It is shown that deposition of Al film on the substrate p-Si leads to the formation of strain capacity and the localization of defects in the surface layer that corresponds to luminescence centers.

  16. Nanopore formation on low-doped p-type silicon under illumination

    Energy Technology Data Exchange (ETDEWEB)

    Chiboub, N. [UDTS, 02 Bd. Frantz Fanon, B.P. 140, Alger-7 Merveilles, 16200 Algiers (Algeria); Gabouze, N., E-mail: ngabouze@yahoo.fr [UDTS, 02 Bd. Frantz Fanon, B.P. 140, Alger-7 Merveilles, 16200 Algiers (Algeria); Chazalviel, J.-N.; Ozanam, F. [Physique de la Matiere Condensee, Ecole Polytechnique, CNRS, 91128 Palaiseau (France); Moulay, S. [Universite Saad Dahleby, B.P. 270, Route de Soumaa, Blida (Algeria); Manseri, A. [UDTS, 02 Bd. Frantz Fanon, B.P. 140, Alger-7 Merveilles, 16200 Algiers (Algeria)

    2010-04-01

    Porous silicon layers were elaborated by anodization of highly resistive p-type silicon in HF/ethylene glycol solution under front side illumination, as a function of etching time, HF concentration and illumination intensity. The porous layer morphology was investigated by scanning electron microscopy (SEM). The illumination during anodization was provided by a tungsten lamp or lasers of different wavelengths. Under anodization, a microporous layer is formed up to a critical thickness above which macropores appear. Under illumination, the instability limiting the growth of the microporous layer occurs at a critical thickness much larger than in the dark. This critical thickness depends on HF concentration, illumination wavelength and intensity. These non-trivial dependencies are rationalized in a model in which photochemical etching in the electrochemically formed porous layer plays the central role.

  17. Improving the radiation hardness properties of silicon detectors using oxygenated n-type and p-type silicon

    CERN Document Server

    Casse, G L; Hanlon, M

    2000-01-01

    The degradation of the electrical properties of silicon detectors exposed to 24 GeV/c protons were studied using pad diodes made from different silicon materials. Standard high-grade p-type and n-type substrates and oxygenated n-type substrates have been used. The diodes were studied in terms of reverse current (I/sub r/) and full depletion voltage (V/sub fd/) as a function of fluence. The oxygenated devices from different suppliers with a variety of starting materials and techniques, all show a consistent improvement of the degradation rate of V/sub fd/ and CCE compared to un- oxygenated substrate devices. Radiation damage of n-type detectors introduces stable defects acting as effective p-type doping and leads to the change of the conductivity type of the silicon bulk (type inversion) at a neutron equivalent fluence of a few 10/sup 13/ cm/sup -2/. The diode junction after inversion migrates from the original side to the back plane of the detector. The migration of the junction is avoided using silicon detec...

  18. Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

    Science.gov (United States)

    Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

    2014-01-01

    Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

  19. Hadron-therapy beam monitoring: Towards a new generation of ultra-thin p-type silicon strip detectors

    Energy Technology Data Exchange (ETDEWEB)

    Bouterfa, M.; Aouadi, K. [Inst. of Information and Communication Technologies, Electronics and Applied Mathematics ICTEAM, Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium); Bertrand, D. [Particle Therapy Dept., Ion Beam Application IBA, 1348 Louvain-la-Neuve (Belgium); Olbrechts, B.; Delamare, R. [Inst. of Information and Communication Technologies, Electronics and Applied Mathematics ICTEAM, Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium); Raskin, J. P.; Gil, E. C. [Institut de Recherche en Mathematique et Physique IRMP, Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium); Flandre, D. [Inst. of Information and Communication Technologies, Electronics and Applied Mathematics ICTEAM, Universite Catholique de Louvain, 1348 Louvain-la-Neuve (Belgium)

    2011-07-01

    Hadron-therapy has gained increasing interest for cancer treatment especially within the last decade. System commissioning and quality assurance procedures impose to monitor the particle beam using 2D dose measurements. Nowadays, several monitoring systems exist for hadron-therapy but all show a relatively high influence on the beam properties: indeed, most devices consist of several layers of materials that degrade the beam through scattering and energy losses. For precise treatment purposes, ultra-thin silicon strip detectors are investigated in order to reduce this beam scattering. We assess the beam size increase provoked by the Multiple Coulomb Scattering when passing through Si, to derive a target thickness. Monte-Carlo based simulations show a characteristic scattering opening angle lower than 1 mrad for thicknesses below 20 {mu}m. We then evaluated the fabrication process feasibility. We successfully thinned down silicon wafers to thicknesses lower than 10 {mu}m over areas of several cm{sup 2}. Strip detectors are presently being processed and they will tentatively be thinned down to 20 {mu}m. Moreover, two-dimensional TCAD simulations were carried out to investigate the beam detector performances on p-type Si substrates. Additionally, thick and thin substrates have been compared thanks to electrical simulations. Reducing the pitch between the strips increases breakdown voltage, whereas leakage current is quite insensitive to strips geometrical configuration. The samples are to be characterized as soon as possible in one of the IBA hadron-therapy facilities. For hadron-therapy, this would represent a considerable step forward in terms of treatment precision. (authors)

  20. Laser-induced subsurface modification of silicon wafers

    NARCIS (Netherlands)

    Verburg, P.C.

    2015-01-01

    Wafer dicing is the technology to separate wafers into divided components known as dies. New developments in the semiconductor industry, such as die stacking and the development of microelectromechanical systems, present significant challenges to the dicing process. A promising wafer dicing method

  1. Lateral photovoltaic effect in p-type silicon induced by surface states

    Science.gov (United States)

    Huang, Xu; Mei, Chunlian; Gan, Zhikai; Zhou, Peiqi; Wang, Hui

    2017-03-01

    A colossal lateral photovoltaic effect (LPE) was observed at the surface of p-type silicon, which differs from the conventional thought that a large LPE is only observed in Schottky junctions and PN junctions consisting of several layers with different conductivities. It shows a high sensitivity of 499.24 mV/mm and an ultra-broadband spectral responsivity (from 405 nm to 980 nm) at room temperature, which makes it an attractive candidate for near-infrared detection. We propose that this phenomenon can be understood by considering the surface band bending near the surface of p-Si induced by charged surface states. The energy band diagrams of the samples are shown based on X-ray photoelectron spectroscopy suggesting the correlation between the LPE and surface band bending. The conjectures are validated by changing the surface states of p-type silicon using Ni nano-films. These findings reveal a generation mechanism of the LPE and may lead to p-Si based, broadband-responsivity, low-cost, and high-precision optical and optoelectronic applications.

  2. Improved quality control of silicon wafers using novel off-line air pocket image analysis

    Science.gov (United States)

    Valley, John F.; Sanna, M. Cristina

    2014-08-01

    Air pockets (APK) occur randomly in Czochralski (Cz) grown silicon (Si) crystals and may become included in wafers after slicing and polishing. Previously the only APK of interest were those that intersected the front surface of the wafer and therefore directly impacted device yield. However mobile and other electronics have placed new demands on wafers to be internally APK-free for reasons of thermal management and packaging yield. We present a novel, recently patented, APK image processing technique and demonstrate the use of that technique, off-line, to improve quality control during wafer manufacturing.

  3. Effect of internal stresses on the mechanical parameters of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Oksanich, A.P.; Cherner, V.M.; Tuzovskii, K.A.

    1988-12-01

    The authors examined how the mechanical parameters of silicon wafers vary with the stress area. The polished (100) wafers were cut from a billet grown by Czochralski's method. The internal stresses were produced by moving the wafers in and out of an oven having a working zone at 1420 K. Then the oxide film was removed. The area of the stressed parts was determined by photoelasticity. The mechanical parameters were measured with contactless pneumatic loading and continuous central deflection measurement. The internal stresses affect the properties; at a given load the central deflection in an unstressed wafer is larger than in a stressed one.

  4. a-Si:H/c-Si heterojunction front- and back contacts for silicon solar cells with p-type base

    Energy Technology Data Exchange (ETDEWEB)

    Rostan, Philipp Johannes

    2010-07-01

    This thesis reports on low temperature amorphous silicon back and front contacts for high-efficiency crystalline silicon solar cells with a p-type base. The back contact uses a sequence of intrinsic amorphous (i-a-Si:H) and boron doped microcrystalline (p-{mu}c-Si:H) silicon layers fabricated by Plasma Enhanced Chemical Vapor Deposition (PECVD) and a magnetron sputtered ZnO:Al layer. The back contact is finished by evaporating Al onto the ZnO:Al and altogether prepared at a maximum temperature of 220 C. Analysis of the electronic transport of mobile charge carriers at the back contact shows that the two high-efficiency requirements low back contact series resistance and high quality c-Si surface passivation are in strong contradiction to each other, thus difficult to achieve at the same time. The preparation of resistance- and effective lifetime samples allows one to investigate both requirements independently. Analysis of the majority charge carrier transport on complete Al/ZnO:Al/a-Si:H/c-Si back contact structures derives the resistive properties. Measurements of the effective minority carrier lifetime on a-Si:H coated wafers determines the back contact surface passivation quality. Both high-efficiency solar cell requirements together are analyzed in complete photovoltaic devices where the back contact series resistance mainly affects the fill factor and the back contact passivation quality mainly affects the open circuit voltage. The best cell equipped with a diffused emitter with random texture and a full-area a-Si:H/c-Si back contact has an independently confirmed efficiency {eta} = 21.0 % with an open circuit voltage V{sub oc} = 681 mV and a fill factor FF = 78.7 % on an area of 1 cm{sup 2}. An alternative concept that uses a simplified a-Si:H layer sequence combined with Al-point contacts yields a confirmed efficiency {eta} = 19.3 % with an open circuit voltage V{sub oc} = 655 mV and a fill factor FF = 79.5 % on an area of 2 cm{sup 2}. Analysis of the

  5. a-Si:H/c-Si heterojunction front- and back contacts for silicon solar cells with p-type base

    Energy Technology Data Exchange (ETDEWEB)

    Rostan, Philipp Johannes

    2010-07-01

    This thesis reports on low temperature amorphous silicon back and front contacts for high-efficiency crystalline silicon solar cells with a p-type base. The back contact uses a sequence of intrinsic amorphous (i-a-Si:H) and boron doped microcrystalline (p-{mu}c-Si:H) silicon layers fabricated by Plasma Enhanced Chemical Vapor Deposition (PECVD) and a magnetron sputtered ZnO:Al layer. The back contact is finished by evaporating Al onto the ZnO:Al and altogether prepared at a maximum temperature of 220 C. Analysis of the electronic transport of mobile charge carriers at the back contact shows that the two high-efficiency requirements low back contact series resistance and high quality c-Si surface passivation are in strong contradiction to each other, thus difficult to achieve at the same time. The preparation of resistance- and effective lifetime samples allows one to investigate both requirements independently. Analysis of the majority charge carrier transport on complete Al/ZnO:Al/a-Si:H/c-Si back contact structures derives the resistive properties. Measurements of the effective minority carrier lifetime on a-Si:H coated wafers determines the back contact surface passivation quality. Both high-efficiency solar cell requirements together are analyzed in complete photovoltaic devices where the back contact series resistance mainly affects the fill factor and the back contact passivation quality mainly affects the open circuit voltage. The best cell equipped with a diffused emitter with random texture and a full-area a-Si:H/c-Si back contact has an independently confirmed efficiency {eta} = 21.0 % with an open circuit voltage V{sub oc} = 681 mV and a fill factor FF = 78.7 % on an area of 1 cm{sup 2}. An alternative concept that uses a simplified a-Si:H layer sequence combined with Al-point contacts yields a confirmed efficiency {eta} = 19.3 % with an open circuit voltage V{sub oc} = 655 mV and a fill factor FF = 79.5 % on an area of 2 cm{sup 2}. Analysis of the

  6. Electrical band-gap narrowing in n- and p-type heavily doped silicon at 300 K

    Science.gov (United States)

    Van Cong, H.; Brunet, S.

    1986-09-01

    Based on previous results band-gap narrowing in heavily doped silicon at 300 K is investigated and expressed in terms of impurity size-and-doping effects. The results obtained for n- and p-type heavily doped silicon are compared with other theories and experiments.

  7. Characterization of perovskite layer on various nanostructured silicon wafer

    Science.gov (United States)

    Rostan, Nur Fairuz Mohd; Sepeai, Suhaila; Ramli, Noor Fadhilah; Azhari, Ayu Wazira; Ludin, Norasikin Ahmad; Teridi, Mohd Asri Mat; Ibrahim, Mohd Adib; Zaidi, Saleem H.

    2017-05-01

    Crystalline silicon (c-Si) solar cell dominates 90% of photovoltaic (PV) market. The c-Si is the most mature of all PV technologies and expected to remain leading the PV technology by 2050. The attractive characters of Si solar cell are stability, long lasting and higher lifetime. Presently, the efficiency of c-Si solar cell is still stuck at 25% for one and half decades. Tandem approach is one of the attempts to improve the Si solar cell efficiency with higher bandgap layer is stacked on top of Si bottom cell. Perovskite offers a big potential to be inserted into a tandem solar cell. Perovskite with bandgap of 1.6 to 1.9 eV will be able to absorb high energy photons, meanwhile c-Si with bandgap of 1.124 eV will absorb low energy photons. The high carrier mobility, high carrier lifetime, highly compatible with both solution and evaporation techniques makes perovskite an eligible candidate for perovskite-Si tandem configuration. The solution of methyl ammonium lead iodide (MAPbI3) was prepared by single step precursor process. The perovskite layer was deposited on different c-Si surface structure, namely planar, textured and Si nanowires (SiNWs) by using spin-coating technique at different rotation speeds. The nanostructure of Si surface was textured using alkaline based wet chemical etching process and SiNW was grown using metal assisted etching technique. The detailed surface morphology and absorbance of perovskite were studied in this paper. The results show that the thicknesses of MAPbI3 were reduced with the increasing of rotation speed. In addition, the perovskite layer deposited on the nanostructured Si wafer became rougher as the etching time and rotation speed increased. The average surface roughness increased from ˜24 nm to ˜38 nm for etching time range between 5-60 min at constant low rotation speed (2000 rpm) for SiNWs Si wafer.

  8. A re-examination of cobalt-related defects in n- and p-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Scheffler, Leopold; Kolkovsky, Vladimir; Weber, Joerg [Technische Universitaet Dresden, 01069 Dresden (Germany)

    2012-10-15

    In the present work cobalt-doped n- and p-type silicon samples were studied by means of deep level transient spectroscopy (DLTS) and Laplace-DLTS (LDLTS). We demonstrate that two dominant DLTS peaks previously assigned to a substitutional Co defect have different annealing behaviour and therefore belong to different defects. After wet chemical etching three other peaks (E90, E140 and H160) were observed in the samples. The intensity of the peaks becomes larger in the H-plasma treated samples. This together with depth profiling demonstrates that the peaks are hydrogen-related defects. The origin of the peaks will be discussed. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  9. Low-temperature TCT characterization of heavily proton irradiated p-type magnetic Czochralski silicon detectors

    CERN Document Server

    Härkönen, J; Luukka, P; Kassamakov, I; Autioniemi, M; Tuominen, E; Sane, P; Pusa, P; Räisänen, J; Eremin, V; Verbitskaya, E; Li, Z

    2007-01-01

    n+/p−/p+ pad detectors processed at the Microelectronics Center of Helsinki University of Technology on boron-doped p-type high-resistivity magnetic Czochralski (MCz-Si) silicon substrates have been investigated by the transient current technique (TCT) measurements between 100 and 240 K. The detectors were irradiated by 9 MeV protons at the Accelerator Laboratory of University of Helsinki up to 1 MeV neutron equivalent fluence of 2×1015 n/cm2. In some of the detectors the thermal donors (TD) were introduced by intentional heat treatment at 430 °C. Hole trapping time constants and full depletion voltage values were extracted from the TCT data. We observed that hole trapping times in the order of 10 ns were found in heavily (above 1×1015 neq/cm2) irradiated samples. These detectors could be fully depleted below 500 V in the temperature range of 140–180 K.

  10. Effect of PECVD SiNx/SiOyNx-Si interface property on surface passivation of silicon wafer

    Science.gov (United States)

    Jia, Xiao-Jie; Zhou, Chun-Lan; Zhu, Jun-Jie; Zhou, Su; Wang, Wen-Jing

    2016-12-01

    It is studied in this paper that the electrical characteristics of the interface between SiOyNx/SiNx stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiOyNx layer on interface parameters, such as interface state density Dit and fixed charge Qf, and the surface passivation quality of silicon are observed. Capacitance-voltage measurements reveal that inserting a thin SiOyNx layer between the SiNx and the silicon wafer can suppress Qf in the film and Dit at the interface. The positive Qf and Dit and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiOyNx film increasing. Prepared by deposition at a low temperature and a low ratio of N2O/SiH4 flow rate, the SiOyNx/SiNx stacks result in a low effective surface recombination velocity (Seff) of 6 cm/s on a p-type 1 Ω·cm-5 Ω·cm FZ silicon wafer. The positive relationship between Seff and Dit suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA050302) and the National Natural Science Foundation of China (Grant No. 61306076).

  11. Optical characterization of double-side-textured silicon wafer based on photonic nanostructures for thin-wafer crystalline silicon solar cells

    Science.gov (United States)

    Tayagaki, Takeshi; Furuta, Daichi; Aonuma, Osamu; Takahashi, Isao; Hoshi, Yusuke; Kurokawa, Yasuyoshi; Usami, Noritaka

    2017-04-01

    Crystalline silicon (c-Si) wafers have found extensive use in photovoltaic applications. In this regard, to enable advanced light manipulation in thin-wafer c-Si solar cells, we demonstrate the fabrication of double-side-textured Si wafers composed of a front-surface photonic nanotexture fabricated with quantum dot arrays and a rear-surface microtexture. The addition of the rear-surface microtexture to a Si wafer with the front-surface photonic nanotexture increases the wafer’s optical absorption in the near-infrared region, thus enabling enhanced light trapping. Excitation spectroscopy reveals that the photoluminescence intensity in the Si wafer with the double-sided texture is higher than that in the Si wafer without the rear-surface microtexture, thus indicating an increase in true optical absorption in the Si wafer with the double-sided texture. Our results indicate that the double-sided textures, i.e., the front-surface photonic nanotexture and rear-surface microtexture, can effectively reduce the surface reflection loss and provide enhanced light trapping, respectively.

  12. The development of p-type silicon detectors for the high radiation regions of the LHC

    CERN Document Server

    Hanlon, M D L

    1998-01-01

    This thesis describes the production and characterisation of silicon microstrip detectors and test structures on p-type substrates. An account is given of the production and full parameterisation of a p-type microstrip detector, incorporating the ATLAS-A geometry in a beam test. This detector is an AC coupled device incorporating a continuous p-stop isolation frame and polysilicon biasing and is typical of n-strip devices proposed for operation at the LHC. It was successfully read out using the FELix-128 analogue pipeline chip and a signal to noise (s/n) of 17+-1 is reported, along with a spatial resolution of 14.6+-0.2 mu m. Diode test structures were fabricated on both high resistivity float zone material and on epitaxial material and subsequently irradiated with 24 GeV protons at the CERN PS up to a dose of (8.22+-0.23) x 10 sup 1 sup 4 per cm sup 2. An account of the measurement program is presented along with results on the changes in the effective doping concentration (N sub e sub f sub f) with irradiat...

  13. Evidence for an iron-hydrogen complex in p-type silicon

    Science.gov (United States)

    Leonard, S.; Markevich, V. P.; Peaker, A. R.; Hamilton, B.; Murphy, J. D.

    2015-07-01

    Interactions of hydrogen with iron have been studied in Fe contaminated p-type Czochralski silicon using capacitance-voltage profiling and deep level transient spectroscopy (DLTS). Hydrogen has been introduced into the samples from a silicon nitride layer grown by plasma enhanced chemical vapor deposition. After annealing of the Schottky diodes on Si:Fe + H samples under reverse bias in the temperature range of 90-120 °C, a trap has been observed in the DLTS spectra which we have assigned to a Fe-H complex. The trap is only observed when a high concentration of hydrogen is present in the near surface region. The trap concentration is higher in samples with a higher concentration of single interstitial Fe atoms. The defect has a deep donor level at Ev + 0.31 eV. Direct measurements of capture cross section of holes have shown that the capture cross section is not temperature dependent and its value is 5.2 × 10-17 cm2. It is found from an isochronal annealing study that the Fe-H complex is not very stable and can be eliminated completely by annealing for 30 min at 125 °C.

  14. RF performances of inductors integrated on localized p+-type porous silicon regions

    National Research Council Canada - National Science Library

    Capelle, Marie; Billoué, Jérôme; Poveda, Patrick; Gautier, Gaël

    2012-01-01

    To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet...

  15. Artificial solid electrolyte interphase with in-situ formed porosity for enhancing lithiation of silicon wafer

    Science.gov (United States)

    Lin, Jie; Guo, Jianlai; Liu, Chang; Guo, Hang

    2016-12-01

    In order to utilize silicon wafer as electrode and substrate for integrated lithium-ion batteries, a composite film with in-situ formed porosity (lithium phosphorous oxynitride/tin oxide, LiPON/SnO2) is fabricated and directly exploited as the artificial solid electrolyte interphase film. Without the compromise of Coulombic efficiency, the capacity and cycle performance of silicon wafer are both developed, resulting from the reduced resistance and the dynamically stable coating. This work provides guidance to enhance the lithiation of bulk silicon, and the strategy of surface modification can be applied to other advanced materials or fields.

  16. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  17. Study the Characteristic of P-Type Junction-Less Side Gate Silicon Nanowire Transistor Fabricated by Atomic Force Microscopy Lithography

    Directory of Open Access Journals (Sweden)

    Arash Dehzangi

    2011-01-01

    Full Text Available Problem statement: Nanotransistor now is one of the most promising fields in nanoelectronics in order to decrease the energy consuming and application to create developed programmable information processors. Most of Computing and communications companies invest hundreds of millions of dollars in research funds every year to develop smaller transistors. Approach: The Junction-less side gate silicon Nano-wire transistor has been fabricated by Atomic Force Microscopy (AFM and wet etching on p-type Silicon On Insulator (SOI wafer. Then, we checked the characteristic and conductance trend in this device regarding to semi-classical approach by Semiconductor Probe Analyser (SPA. Results: We observed in characteristic of the device directly proportionality of the negative gate voltage and Source-Drain current. In semi classical approach, negative Gate voltage decreased the energy States of the Nano-wire between the source and the drain. The graph for positive gate voltage plotted as well to check. In other hand, the conductance will be following characteristic due to varying the gate voltage under the different drain-source voltage. Conclusion: The channel energy states are supposed to locate between two electrochemical potentials of the contacts in order to transform the charge. For the p-type channel the transform of the carriers is located in valence band and changing the positive or negative gate voltage, making the valence band energy states out of or in the area between the electrochemical potentials of the contacts causing the current reduced or increased.

  18. Development of Megasonic cleaning for silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  19. Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

    Science.gov (United States)

    Pa, Pai-Shan

    2010-01-01

    A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

  20. Investigation of Wafer Level Au-Si Eutectic Bonding of Shape Memory Alloy (SMA) with Silicon

    OpenAIRE

    Bushra, Sobia

    2011-01-01

    The objective of this research work was to investigate the low temperature gold silicon eutectic bonding of SMA with silicon wafers. The research work was carried out to optimize a bond process with better yield and higher bond strength. The gold layer thickness, processing temperature, diffusion barrier, adhesive layer, and the removal of silicon oxide are the important parameters in determining a reliable and uniform bond. Based on the previous work on Au-Si eutectic bonding, 7 different Si...

  1. Diffusion length and resistivity distribution characteristics of silicon wafer by photoluminescence

    Energy Technology Data Exchange (ETDEWEB)

    Baek, Dohyun; Lee, Jaehyeong; Choi, Byoungdeog, E-mail: bdchoi@skku.edu

    2014-10-15

    Highlights: • Analytical photoluminescence efficiency calculation and PL intensity ratio method are developed. • Wafer resistivity and diffusion length characteristics are investigated by PL intensity ratio. • PL intensity is well correlated with resistivity, diffusion length or defect density on wafer measurement. - Abstract: Photoluminescence is a convenient, contactless method to characterize semiconductors. Its use for room-temperature silicon characterization has only recently been implemented. We have developed the PL efficiency theory as a function of substrate doping densities, bulk trap density, photon flux density, and reflectance and compared it with experimental data initially for bulk Si wafers. New developed PL intensity ratio method is able to predict the silicon wafer properties, such as doping densities, minority carrier diffusion length and bulk trap density.

  2. First results on charge collection efficiency of heavily irradiated microstrip sensors fabricated on oxygenated p-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Casse, G. E-mail: gcasse@hep.ph.liv.ac.uk; Allport, P.P.; Marti i Garcia, S.; Lozano, M.; Turner, P.R

    2004-02-01

    Heavy hadron irradiation leads to type inversion of n-type silicon detectors. After type inversion, the charge collected at low bias voltages by silicon microstrip detectors is higher when read out from the n-side compared to p-side read out. The n-side read out has been successfully used in combination with oxygen-enriched n-type silicon substrate to maximise the radiation hardness of microstrip detectors. Alternatively, the n-side read out can be implemented on p-type substrates reducing the complexity of fabrication. Miniature silicon microstrip detectors made on standard and oxygen-enriched p-type substrate have been produced. The charge collection properties of such detectors with and without oxygenation are here compared for the first time after severe charged hadron irradiation.

  3. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  4. Radiation thermometry of silicon wafers based on emissivity-invariant condition.

    Science.gov (United States)

    Iuchi, Tohru; Seo, Tomohiro

    2011-01-20

    An emissivity-invariant condition for a silicon wafer was determined by simulation modeling and it was confirmed experimentally. The p-polarized spectral emissivity at a wavelength of 900 nm and at temperatures over 900 K was constant at 0.83 at an angle of about 55.4° irrespective of large variations in the oxide layer thickness and the resistivity due to the different impurity doping concentrations of the silicon wafer. The expanded uncertainty, U(c) = ku(c) (k = 2), of the temperature measurement is estimated to be 4.9 K. This result is expected to significantly enhance the accuracy of radiometric temperature measurements of silicon wafers in actual manufacturing processes.

  5. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    Directory of Open Access Journals (Sweden)

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  6. DRIE fabrication of notch-free silicon structures using a novel silicon-on-patterned metal and glass wafer

    Science.gov (United States)

    Kim, Ki Hoon; Kim, Sang Cheol; Park, Kyu Yeon; Yang, Sang Sik

    2011-04-01

    This paper presents a method of fabricating a silicon structure without notches using a new kind of substrate consisting of silicon-on-patterned metal and glass (SOMG). It has a metal interlayer with a thickness of 0.1 µm between a silicon wafer and glass wafer as an insulation layer to eliminate the micro-charging effect on the insulation surface for the silicon dry etching process. This substrate is fabricated by anodic bonding and polishing. To ascertain the effect of the SOMG substrate, 100 µm deep silicon structures with 5 and 20 µm wide trenches have been etched on SOG (silicon-on-glass) and SOMG substrates under similar conditions. In order to perform the deep silicon etching process, a thick photoresist of AZ9260 is used as a dry etch mask. In the results, no notches are on SOMG, while notches occur on SOG. Also, regardless of the over-etching time as the dimensions of the area to be etched, no notches are formed at the bottom of the silicon structure. This results in a notchless silicon structure. This research shows the feasibility of applying this technique to many applications using silicon devices.

  7. Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Johnston, S.; Yan, F.; Dorn, D.; Zaunbrecher, K.; Al-Jassim, M.; Sidelkheir, O.; Ounadjela, K.

    2012-06-01

    Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect band images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.

  8. The Process of Plasma Chemical Photoresist Film Ashing from the Surface of Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Siarhei Bordusau

    2013-01-01

    Full Text Available At present, the research for finding new technical methods of treating materials with plasma, including the development of energy and resource saving technologies for microelectronic manufacturing, is particularly actual.In order to improve the efficiency of microwave plasma chemical ashing of photoresist films from the surface of silicon wafers a two-stage process of treating was developed. The idea of the developed process is that wafers coated with photoresist are pre-heated by microwave energy. This occurs because the microwave energy initially is not spent on the excitation and maintenance of a microwave discharge but it is absorbed by silicon wafers which have a high tangent of dielectric losses. During the next step after the excitation of the microwave discharge the interaction of oxygen plasma with a pre-heated photoresist films proceeds more intensively. The delay of the start of plasma forming process in the vacuum chamber of a plasmatron with respect to the beginning of microwave energy generation by a magnetron leads to the increase of the total rate of photoresist ashing from the surface of silicon wafers approximately 1.7 times. The advantage of this method of microwave plasma chemical processing of semi-conductor wafers is the possibility of intensifying the process without changing the design of microwave discharge module and without increasing the input microwave power supplied into the discharge.

  9. Thin, High Lifetime Silicon Wafers with No Sawing; Re-crystallization in a Thin Film Capsule

    Energy Technology Data Exchange (ETDEWEB)

    Emanuel Sachs

    2013-01-16

    The project fits within the area of renewable energy called photovoltaics (PV), or the generation of electricity directly from sunlight using semiconductor devices. PV has the greatest potential of any renewable energy technology. The vast majority of photovoltaic modules are made on crystalline silicon wafers and these wafers accounts for the largest fraction of the cost of a photovoltaic module. Thus, a method of making high quality, low cost wafers would be extremely beneficial to the PV industry The industry standard technology creates wafers by casting an ingot and then sawing wafers from the ingot. Sawing rendered half of the highly refined silicon feedstock as un-reclaimable dust. Being a brittle material, the sawing is actually a type of grinding operation which is costly both in terms of capital equipment and in terms of consumables costs. The consumables costs associated with the wire sawing technology are particularly burdensome and include the cost of the wire itself (continuously fed, one time use), the abrasive particles, and, waste disposal. The goal of this project was to make wafers directly from molten silicon with no sawing required. The fundamental concept was to create a very low cost (but low quality) wafer of the desired shape and size and then to improve the quality of the wafer by a specialized thermal treatment (called re-crystallization). Others have attempted to create silicon sheet by recrystallization with varying degrees of success. Key among the difficulties encountered by others were: a) difficulty in maintaining the physical shape of the sheet during the recrystallization process and b) difficulty in maintaining the cleanliness of the sheet during recrystallization. Our method solved both of these challenges by encapsulating the preform wafer in a protective capsule prior to recrystallization (see below). The recrystallization method developed in this work was extremely effective at maintaining the shape and the cleanliness of the

  10. Detection of inter band gap photoluminescence in multicrystalline silicon wafer

    OpenAIRE

    Jerpetjøn, Lena-Marie

    2011-01-01

    Measurements executed at 300 K revealed photoluminescence solely from silicon. However, at 93 K the measurements revealed photoluminescence from both silicon and defects. The detected photoluminescence signal of silicon at 93 K was stronger though spectrally narrower than the signal detected at 300 K. Hence, the photoluminescence signal was affected by multi-phonon interactions. Two features, D1 and D2, were detected among other defects at 93 K. These two features have been put in relation t...

  11. Analysis of organic contaminants from silicon wafer and disk surfaces by thermal desorption-GC-MS

    Science.gov (United States)

    Camenzind, Mark J.; Ahmed, Latif; Kumar, Anurag

    1999-03-01

    Organic contaminants can affect semiconductor wafer processing including gate oxide integrity, polysilicon growth, deep ultraviolet photoresist line-width, and cleaning & etching steps. Organophosphates are known to counter dope silicon wafers. Organic contaminants in disk drives can cause failures due to stiction or buildup on the heads. Therefore, it is important to identify organic contaminants adsorbed on wafer or disk surfaces and find their sources so they can be either completely eliminated or at least controlled. Dynamic headspace TD-GC-MS (Thermal Desorption-Gas Chromatography-Mass Spectrometry) methods are very sensitive and can be used to identify organic contaminants on disks and wafers, in air, or outgassing from running drives or their individual components.

  12. Copper diffusivity in boron-doped silicon wafer measured by dynamic secondary ion mass spectrometry

    Energy Technology Data Exchange (ETDEWEB)

    Koh, Songfoo [S.E.H (M) Sdn. Bhd., Lot 2, Lorong Enggang 35, Ulu Klang FTZ, 54200 Selangor (Malaysia); You, Ahheng [Faculty of Engineering and Technology, Multimedia University, Jalan Ayer Keroh Lama, Bukit Beruang, 75450 Melaka (Malaysia); Tou, Teckyong, E-mail: tytou@mmu.edu.my [Faculty of Engineering, Multimedia Univesity, Jalan Multimedia, 63100 Cyberjaya (Malaysia)

    2013-03-20

    Highlights: ► Effective copper diffusivity in boron-doped silicon wafer was measured. ► Dynamic secondary ion mass spectrometry was used. ► Interstitial copper ions were first drifted to surface region and allowed to back-diffuse. ► Boron concentration largely influenced the effect copper diffusivity. -- Abstract: The effective copper diffusivity (D{sub eff}) in boron-doped silicon wafer was measured using a Dynamic Secondary Ion Mass Spectrometry (D-SIMS) that was incorporated with an out-drift technique. By this technique, positive interstitial copper ions (Cu{sub I}{sup +}) migrated to the surface region when a continuous charge of electrons showered on the oxidized silicon wafer, which was also bombarded by primary O{sub 2}{sup +} ions. The Cu{sub I}{sup +} ions at the surface region diffused back to the bulk when the electron showering stopped. The D-SIMS recorded the real-time distribution of Cu{sub I}{sup +} ions, generating depth profiles for in-diffusion of copper for silicon-wafer samples with different boron concentrations. These were curve-fitted using the standard diffusion expressions to obtain different D{sub eff} values, and compared with other measurement techniques.

  13. Wafer bonding solution to epitaxial graphene-silicon integration

    Science.gov (United States)

    Dong, Rui; Guo, Zelei; Palmer, James; Hu, Yike; Ruan, Ming; Hankinson, John; Kunc, Jan; Bhattacharya, Swapan K.; Berger, Claire; de Heer, Walt A.

    2014-03-01

    A new strategy for the integration of graphene electronics with silicon complementary metal-oxide-semiconductor (Si-CMOS) technology is demonstrated that requires neither graphene transfer nor patterning. Inspired by silicon-on-insulator and three-dimensional device hyper-integration techniques, a thin monocrystalline silicon layer ready for CMOS processing is bonded to epitaxial graphene (EG) on SiC. The parallel Si and graphene electronic platforms are interconnected by metal vias. In this method, EG is grown prior to bonding so that the process is compatible with EG high temperature growth and preserves graphene integrity and nano-structuring.

  14. Study of an Amorphous Silicon Oxide Buffer Layer for p-Type Microcrystalline Silicon Oxide/n-Type Crystalline Silicon Heterojunction Solar Cells and Their Temperature Dependence

    Directory of Open Access Journals (Sweden)

    Taweewat Krajangsang

    2014-01-01

    Full Text Available Intrinsic hydrogenated amorphous silicon oxide (i-a-SiO:H films were used as front and rear buffer layers in crystalline silicon heterojunction (c-Si-HJ solar cells. The surface passivity and effective lifetime of these i-a-SiO:H films on an n-type silicon wafer were improved by increasing the CO2/SiH4 ratios in the films. Using i-a-SiO:H as the front and rear buffer layers in c-Si-HJ solar cells was investigated. The front i-a-SiO:H buffer layer thickness and the CO2/SiH4 ratio influenced the open-circuit voltage (Voc, fill factor (FF, and temperature coefficient (TC of the c-Si-HJ solar cells. The highest total area efficiency obtained was 18.5% (Voc=700 mV, Jsc=33.5 mA/cm2, and FF=0.79. The TC normalized for this c-Si-HJ solar cell efficiency was −0.301%/°C.

  15. Silicon Wafer Fabrication and Microchannel for Cooling System in ALICE ITS

    CERN Document Server

    Pasuwan, Patrawan

    2013-01-01

    My summer student project covered details of the upgrade of Inner Tracking System (ITS) of the ALICE detector. The tasks are divided in two parts. First was on silicon wafer dicing technology and its resistivity under the supervision of Petra Riedler. Next was on silicon wafer microfabrication and cooling system in microchannel under the supervision of Andrea Francescon. ITS upgrade was proposed for better detection performance and reduction of budget. Detectors in the ITS are composed of monolithic silicon pixel chips. The thickness of the chips was proposed to be 50 μm so that particles that pass through them do not lose too much momentum. Working with very thin chips requires suitable dicing technology. Sum- mary of dicing technology is proposed for the most suitable dicing technique. Properties of the chip can be denoted by observing its resistivity. Literature reviews on surface resistivity profile measurement is represented for consideration. Cooling system is very important for the detector. Fluid t...

  16. Laser cutting silicon-glass double layer wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Yang, Lijun; Zhang, Hongzhi; Wang, Yang

    2016-07-01

    This study was aimed at introducing the laser induced thermal-crack propagation (LITP) technology to solve the silicon-glass double layer wafer dicing problems in the packaging procedure of silicon-glass device packaged by WLCSP technology, investigating the feasibility of this idea, and studying the crack propagation process of LITP cutting double layer wafer. In this paper, the physical process of the 1064 nm laser beam interact with the double layer wafer during the cutting process was studied theoretically. A mathematical model consists the volumetric heating source and the surface heating source has been established. The temperature and stress distribution was simulated by using finite element method (FEM) analysis software ABAQUS. The extended finite element method (XFEM) was added to the simulation as the supplementary features to simulate the crack propagation process and the crack propagation profile. The silicon-glass double layer wafer cutting verification experiment under typical parameters was conducted by using the 1064 nm semiconductor laser. The crack propagation profile on the fracture surface was examined by optical microscope and explained from the stress distribution and XFEM status. It was concluded that the quality of the finished fracture surface has been greatly improved, and the experiment results were well supported by the numerical simulation results.

  17. Doped and Undoped Zinc Oxide Nanostructures on Silicon Wafers

    Science.gov (United States)

    Chubenko, E.; Bondarenko, V.

    2013-05-01

    We present results of hydrothermal deposition of undoped and Al doped ZnO nanocrystals on nanocrystalline silicon. ZnO nanocrystals were deposited in an equimolar zinc nitride and hexamethylenetetramine solution. Aluminum nitride was used as Al precursor. The difference of the morphology of doped and undoped ZnO nanocrystals is discussed. Photoluminescence properties of the obtained nanocrystals are shown.

  18. Effects of Germanium on Movement of Dislocations in p-Type Czochralski Silicon

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    By indentation at room temperature followed by annealing at high temperatures, the pinning effect of germanium on dislocations in germanium-doped Czochralski silicon was investigated. Experimental results show that the dislocations in germanium-doped Czochralski silicon move shorter and slower than those in Czochralski silicon undoping with germanium when the concentration of germanium is over 1×1018 cm-3. The retarding velocity of dislocations is contributed to the dislocations pinning effect of the strain field introduced by the high concentration germanium, and the Ge4B cluster and the oxygen precipitation those are preferred to form at higher concentration germanium.

  19. Micro-spectroscopy on silicon wafers and solar cells

    Directory of Open Access Journals (Sweden)

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  20. Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

    Science.gov (United States)

    Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

    2015-01-01

    Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

  1. Electronic transport characterization of silicon wafers by spatially resolved steady-state photocarrier radiometric imaging

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Qian [Institute of Optics and Electronics, Chinese Academy of Sciences, P. O. Box 350, Shuangliu, Chengdu 610209 (China); University of the Chinese Academy of Sciences, Beijing 100039 (China); Li, Bincheng, E-mail: bcli@ioe.ac.cn [Institute of Optics and Electronics, Chinese Academy of Sciences, P. O. Box 350, Shuangliu, Chengdu 610209 (China); School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China)

    2015-09-28

    Spatially resolved steady-state photocarrier radiometric (PCR) imaging technique is developed to characterize the electronic transport properties of silicon wafers. Based on a nonlinear PCR theory, simulations are performed to investigate the effects of electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) on the steady-state PCR intensity profiles. The electronic transport parameters of an n-type silicon wafer are simultaneously determined by fitting the measured steady-state PCR intensity profiles to the three-dimensional nonlinear PCR model. The determined transport parameters are in good agreement with the results obtained by the conventional modulated PCR technique with multiple pump beam radii.

  2. Nano-scratch study of molecular deposition (MD) films on silicon wafer using nanoindentation~1

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Experiment of the molecular deposition (MD) films with and without alkyl terminal de-posited on the silicon wafer were conducted by using nanoindentation. It was found that MD filmsand alkyl terminated MD films exhibit higher critical load (scratch resistance or adhesive strength)and lower coefficient of friction compared with the silicon substrate. Critical load (scratch resis-tance) increases with the number of layers, and coefficients of friction of those MD film with alkylterminal are still best for the same layer of MD film.

  3. Effect of Rapid Thermal Process on Oxygen Precipitates in Heavily Sb-Doped Silicon Wafer

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Oxygen precipitates in heavily Sb-doped silicon after rapid thermal process (RTP) in Ar ambient were investigated by RTP at high temperature following annealing at 800 ℃ for 4 h and 1000 ℃ for 16 h. RTP temperature and cooling rates were changed from 1200 to 1260 ℃ and from 10 to 100 ℃·s-1, respectively. The experiment results show that high density of oxygen precipitates is observed in heavily Sb-doped wafer. It is found that the oxygen precipitates in heavily Sb-doped silicon are enhanced at high cooling rate.

  4. Three-dimensional (3D) monolithically integrated photodetector and WDM receiver based on bulk silicon wafer.

    Science.gov (United States)

    Song, Junfeng; Luo, Xianshu; Tu, Xiaoguang; Jia, Lianxi; Fang, Qing; Liow, Tsung-Yang; Yu, Mingbin; Lo, Guo-Qiang

    2014-08-11

    We propose a novel three-dimensional (3D) monolithic optoelectronic integration platform. Such platform integrates both electrical and photonic devices in a bulk silicon wafer, which eliminates the high-cost silicon-on-insulator (SOI) wafer and is more suitable for process requirements of electronic and photonic integrated circuits (ICs). For proof-of-concept, we demonstrate a three-dimensional photodetector and WDM receiver system. The Ge is grown on a 8-inch bulk silicon wafer while the optical waveguide is defined in a SiN layer which is deposited on top of it, with ~4 µm oxide sandwiched in between. The light is directed to the Ge photodetector from the SiN waveguide vertically by using grating coupler with a Aluminum mirror on top of it. The measured photodetector responsivity is ~0.2 A/W and the 3-dB bandwidth is ~2 GHz. Using such vertical-coupled photodetector, we demonstrated an 8-channel receiver by integrating a 1 × 8 arrayed waveguide grating (AWG). High-quality optical signal detection with up to 10 Gbit/s data rate is demonstrated, suggesting a 80 Gbit/s throughput. Such receiver can be applied to on-chip optical interconnect, DRAM interface, and telecommunication systems.

  5. Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

    Science.gov (United States)

    Choi, Youn Sung; Numata, Toshinori; Nishida, Toshikazu; Harris, Rusty; Thompson, Scott E.

    2008-03-01

    Uniaxial four-point wafer bending stress-altered gate tunneling currents are measured for germanium (Ge)/silicon (Si) channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with HfO2/SiO2 gate dielectrics and TiN/P+ poly Si electrodes. Carrier separation is used to measure electron and hole currents. The strain-altered hole tunneling current from the p-type inversion layer of Ge is measured to be ˜4 times larger than that for the Si channel MOSFET, since the larger strain-induced valence band-edge splitting in Ge results in more hole repopulation into a subband with a smaller out-of-plane effective mass and a lower tunneling barrier height. The strain-altered electron tunneling current from the metal gate is measured and shown to change due to strain altering the metal work function as quantified by flatband voltage shift measurements of Si MOS capacitors with TaN electrodes.

  6. Hot-wire chemical vapor deposition prepared aluminum doped p-type microcrystalline silicon carbide window layers for thin film silicon solar cells

    Science.gov (United States)

    Chen, Tao; Köhler, Florian; Heidt, Anna; Carius, Reinhard; Finger, Friedhelm

    2014-01-01

    Al-doped p-type microcrystalline silicon carbide (µc-SiC:H) thin films were deposited by hot-wire chemical vapor deposition at substrate temperatures below 400 °C. Monomethylsilane (MMS) highly diluted in hydrogen was used as the SiC source in favor of SiC deposition in a stoichiometric form. Aluminum (Al) introduced from trimethylaluminum (TMAl) was used as the p-type dopant. The material property of Al-doped p-type µc-SiC:H thin films deposited with different deposition pressure and filament temperature was investigated in this work. Such µc-SiC:H material is of mainly cubic (3C) SiC polytype. For certain conditions, like high deposition pressure and high filament temperature, additional hexagonal phase and/or stacking faults can be observed. P-type µc-SiC:H thin films with optical band gap E04 ranging from 2.0 to 2.8 eV and dark conductivity ranging from 10-5 to 0.1 S/cm can be prepared. Such transparent and conductive p-type µc-SiC:H thin films were applied in thin film silicon solar cells as the window layer, resulting in an improved quantum efficiency at wavelengths below 480 nm.

  7. Reducing thermal mismatch stress in anodically bonded silicon-glass wafers: theoretical estimation

    Science.gov (United States)

    Sinev, Leonid S.; Ryabov, Vladimir T.

    2017-01-01

    This paper reports the theoretical study and estimations of thermal mismatch stress reduction in anodically bonded silicon-glass stacks by justifiable selection of bonding temperature and glass thickness. This can be done only after prior thorough study of temperature dependence of the linear thermal expansion coefficient of the glass and silicon to be used. We show by analyzing such a dependence of several glass brands that the usual idea of decreasing the bonding process temperature as a solution to the thermal mismatch stress problem can be a failure. Interchanging glass brands during device design is shown to produce very contrasting changes in residual stresses. These results are in good agreement with finite-element modeling. This paper reports there is proportion between glass and silicon wafer thicknesses minimizing thermal mismatch stress at unbonded side of the silicon independently of the bonding or working temperatures chosen.

  8. Accurate determination of electronic transport properties of silicon wafers by nonlinear photocarrier radiometry with multiple pump beam sizes

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Qian [Institute of Optics and Electronics, Chinese Academy of Sciences, P. O. Box 350, Shuangliu, Chengdu 610209 (China); University of the Chinese Academy of Sciences, Beijing 100039 (China); Li, Bincheng, E-mail: bcli@uestc.ac.cn [Institute of Optics and Electronics, Chinese Academy of Sciences, P. O. Box 350, Shuangliu, Chengdu 610209 (China); School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China)

    2015-12-07

    In this paper, photocarrier radiometry (PCR) technique with multiple pump beam sizes is employed to determine simultaneously the electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) of silicon wafers. By employing the multiple pump beam sizes, the influence of instrumental frequency response on the multi-parameter estimation is totally eliminated. A nonlinear PCR model is developed to interpret the PCR signal. Theoretical simulations are performed to investigate the uncertainties of the estimated parameter values by investigating the dependence of a mean square variance on the corresponding transport parameters and compared to that obtained by the conventional frequency-scan method, in which only the frequency dependences of the PCR amplitude and phase are recorded at single pump beam size. Simulation results show that the proposed multiple-pump-beam-size method can improve significantly the accuracy of the determination of the electronic transport parameters. Comparative experiments with a p-type silicon wafer with resistivity 0.1–0.2 Ω·cm are performed, and the electronic transport properties are determined simultaneously. The estimated uncertainties of the carrier lifetime, diffusion coefficient, and front surface recombination velocity are approximately ±10.7%, ±8.6%, and ±35.4% by the proposed multiple-pump-beam-size method, which is much improved than ±15.9%, ±29.1%, and >±50% by the conventional frequency-scan method. The transport parameters determined by the proposed multiple-pump-beam-size PCR method are in good agreement with that obtained by a steady-state PCR imaging technique.

  9. Effects of Helium and Oxygen Common Implantation in Silicon Wafer

    Institute of Scientific and Technical Information of China (English)

    LI Bing-Sheng; ZHANG Chong-Hong; ZHOU Li-Hong; YANG Yi-Tao

    2008-01-01

    Defect engineering for SiO2 precipitation is investigated using He-ion implantation as the first stage of separation by implanted oxygen (SIMOX). Cavities are created in Si by implantation with helium ions. After thermal annealing at different temperatures, the sample is implanted with 120 keV 8.0 × 1016 cm-2 O ions. The O ion energy is chosen such that the peak of the concentration distribution is centred at the cavity band. For comparison,another sample is implanted with O ions alone. Cross-sectional transmission electron microscopy (XTEM), Fourier transform infrared absorbance spectrometry (FTIR) and atomic force microscopy (AFM) measurements are used to investigate the samples. The results show that a narrow nano-cavity layer is found to be excellent nucleation sites that effectively assisted SiO2 formation and released crystal lattice strain associated with silicon oxidation.

  10. Primary defect transformations in high-resistivity p-type silicon irradiated with electrons at cryogenic temperatures

    CERN Document Server

    Makarenko, L F; Korshunov, F P; Murin, L I; Moll, M

    2009-01-01

    It has been revealed that self-interstitials formed under low intensity electron irradiationin high resistivity p-type silicon can be retained frozen up to room temperature. Low thermal mobility of the self-interstitials suggests that Frenkelpair sinsilicon can be stable at temperatures of about or higher than 100K. A broad DLTS peak with activation energy of 0.14–0.17eV can be identified as related to Frenkel pairs. This peak anneals out at temperatures of 120 140K. Experimental evidences are presented that be coming more mobile under forwardcurrent injection the self-interstitials change their charge state to a less positive one.

  11. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  12. Primary defect transformations in high-resistivity p-type silicon irradiated with electrons at cryogenic temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Makarenko, L.F., E-mail: makarenko@bsu.b [Department of Applied Mathematics and Computer Science, Belarusian State University, Independence Ave. 4, 220030 Minsk (Belarus); Lastovski, S.B.; Korshunov, F.P.; Murin, L.I. [Scientific-Practical Materials Research Centre of NAS of Belarus, Minsk (Belarus); Moll, M. [CERN, Geneva (Switzerland)

    2009-12-15

    It has been revealed that self-interstitials formed under low intensity electron irradiation in high resistivity p-type silicon can be retained frozen up to room temperature. Low thermal mobility of the self-interstitials suggests that Frenkel pairs in silicon can be stable at temperatures of about or higher than 100 K. A broad DLTS peak with activation energy of 0.14-0.17 eV can be identified as related to Frenkel pairs. This peak anneals out at temperatures of 120-140 K. Experimental evidences are presented that becoming more mobile under forward current injection the self-interstitials change their charge state to a less positive one.

  13. Ultrasonic study of point defects in electron-irradiated p-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, W.L.

    1987-01-01

    The mechanisms of interaction of ultrasonic waves with point defects in crystals are reviewed, and a perturbation approach is introduced that leads to general expressions for the resonance and relaxation strengths in terms of matrix elements of the ultrasonic perturbation. These expressions provide the basis for a discussion of the polarization dependence of resonance and relaxation. Selection rules for cubic crystals are presented. An exploratory ultrasonic study is performed on electron-irradiated B-doped and Al-doped silicon. Neutral substitutional boron is detected before irradiation, as expected from previous ultrasonic studies on unirradiated silicon. This defect produces both resonance and relaxation. Similar effects are observed for substitutional aluminum. After irradiation, a relaxation is observed when the sample is exposed to 0.18-0.39 eV light. By comparison with previous EPR results, this relaxation is identified as the singly positively charged state of the vacancy, V/sup +/. Preliminary results on the relaxation time and strength of V/sup +/ suggest that it may have several populated vibronic levels. Another relaxation is observed in irradiated Al-doped silicon when the sample is exposed to white light. From its annealing behavior and dopant dependence, it is identified as a nonequilibrium charge state of interstitial aluminum.

  14. Shaped silicon wafers obtained by hot plastic deformation: performance evaluation for future astronomical x-ray telescopes.

    Science.gov (United States)

    Ezoe, Yuichiro; Shirata, Takayuki; Mitsuishi, Ikuyuki; Ishida, Manabu; Mitsuda, Kazuhisa; Morishita, Kohei; Nakajima, Kazuo

    2009-07-01

    In order to develop lightweight and high angular resolution x-ray mirrors, we have investigated hot plastic deformation of 4 in. silicon (111) wafers. A sample wafer was deformed using hemispherical dies with a curvature radius of 1000 mm. The measured radius of the deformed wafer was 1030 mm, suggesting that further conditioning is indispensable for better shaping. For the first time to our knowledge, x-ray reflection on a deformed wafer was detected at Al K(alpha) 1.49 keV. An estimated surface roughness of <1 nm from the x-ray reflection profile was comparable to that of a bare silicon wafer without deformation. Hence, no significant degradation of the microroughness was seen.

  15. Photon-Enhanced Thermionic Emission in Cesiated p-Type and n-Type Silicon

    DEFF Research Database (Denmark)

    Reck, Kasper; Dionigi, Fabio; Hansen, Ole

    2014-01-01

    electrons. Efficiencies above 60% have been predicted theoretically for high solar concentration systems. Silicon is an interesting absorber material for high efficiency PETE solar cells, partly due to its mechanical and thermal properties and partly due to its electrical properties, including a close......Photon-enhanced thermionic emission (PETE) is a relatively new concept for high efficiency solar cells that utilize not only the energy of electrons excited across the band gap by photons, as in conventional photovoltaic solar cells, but also the energy usual lost to thermalization of the excited...

  16. P-stop isolation study of irradiated n-in-p type silicon strip sensors for harsh radiation environment

    CERN Document Server

    AUTHOR|(CDS)2084505

    2015-01-01

    In order to determine the most radiation hard silicon sensors for the CMS Experiment after the Phase II Upgrade in 2023 a comprehensive study of silicon sensors after a fluence of up to $1.5\\times10^{15} n_{eq}/cm^{2}$ corresponding to $3000 fb^{-1}$ after the HL-LHC era has been carried out. The results led to the decision that the future Outer Tracker (20~cm${<}R{<}$110~cm) of CMS will consist of n-in-p type sensors. This technology is more radiation hard but also the manufacturing is more challenging compared to p-in-n type sensors due to additional process steps in order to suppress the accumulation of electrons between the readout strips. One possible isolation technique of adjacent strips is the p-stop structure which is a p-type material implantation with a certain pattern for each individual strip. However, electrical breakdown and charge collection studies indicate that the process parameters of the p-stop structure have to be carefully calibrated in order to achieve a sufficient strip isolatio...

  17. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  18. Short p-type silicon microstrip detectors in 3D-stc technology

    Energy Technology Data Exchange (ETDEWEB)

    Eckert, S. [Physikalisches Institut, Albert-Ludwigs-Universitaet Freiburg, Hermann-Herder Strasse 3b, D-79104 Freiburg i. Br. (Germany)], E-mail: simon.eckert@physik.uni-freiburg.de; Jakobs, K.; Kuehn, S.; Parzefall, U. [Physikalisches Institut, Albert-Ludwigs-Universitaet Freiburg, Hermann-Herder Strasse 3b, D-79104 Freiburg i. Br. (Germany); Dalla-Betta, G.-F.; Zoboli, A. [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita degli Studi di Trento, via Sommarive 14, I-38050 Povo di Trento (Italy); Pozza, A.; Zorzi, N. [FBK-irst Trento, Microsystems Division, via Sommarive 18, I-38050 Povo di Trento (Italy)

    2008-10-21

    The luminosity upgrade of the Large Hadron Collider (LHC), the sLHC, will constitute an extremely challenging radiation environment for tracking detectors. Significant improvements in radiation hardness are needed to cope with the increased radiation dose, requiring new tracking detectors. In the upgraded ATLAS detector the region from 20 to 50 cm distance to the beam will be covered by silicon strip detectors (SSD) with short strips. These will have to withstand a 1 MeV neutron equivalent fluence of about 1x10{sup 15}n{sub eq}/cm{sup 2}, hence extreme radiation resistance is necessary. For the short strips, we propose to use SSD realised in the radiation tolerant 3D technology, where rows of columns-etched into the silicon bulk-are joined together to form strips. To demonstrate the feasibility of 3D SSD for the sLHC, we have built prototype modules using 3D-single-type-column (stc) SSD with short strips and front-end electronics from the present ATLAS SCT. The modules were read out with the SCT Data Acquisition system and tested with an IR-laser. We report on the performance of these 3D modules, in particular the noise at 40 MHz which constitutes a measurement of the effective detector capacitance. Conclusions about options for using 3D SSD detectors for tracking at the sLHC are drawn.

  19. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  20. RF Magnetron Sputtering Aluminum Oxide Film for Surface Passivation on Crystalline Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Siming Chen

    2013-01-01

    Full Text Available Aluminum oxide films were deposited on crystalline silicon substrates by reactive RF magnetron sputtering. The influences of the deposition parameters on the surface passivation, surface damage, optical properties, and composition of the films have been investigated. It is found that proper sputtering power and uniform magnetic field reduced the surface damage from the high-energy ion bombardment to the silicon wafers during the process and consequently decreased the interface trap density, resulting in the good surface passivation; relatively high refractive index of aluminum oxide film is benefic to improve the surface passivation. The negative-charged aluminum oxide film was then successfully prepared. The surface passivation performance was further improved after postannealing by formation of an SiOx interfacial layer. It is demonstrated that the reactive sputtering is an effective technique of fabricating aluminum oxide surface passivation film for low-cost high-efficiency crystalline silicon solar cells.

  1. Geometrical Deviation and Residual Strain in Novel Silicon-on-Aluminium-Nitride Bonded Wafers

    Institute of Scientific and Technical Information of China (English)

    门传玲; 徐政; 吴雁军; 安正华; 谢欣云; 林成鲁

    2002-01-01

    Aluminium nitride (AlN), with much higher thermal conductivity, is considered to be an excellent alternative to the SiO2 layer in traditional silicon-on-insulator (SOI) materials. The silicon-on-aluminium-nitride (SOAN) structure was fabricated by the smart-cut process to alleviate the self-heating effects for traditional SOI. The convergent beam Kikuchi line diffraction pattern results show that some rotational misalignment exists when two wafers are bonded, which is about 3°. The high-resolution x-ray diffraction result indicates that, before annealing at high temperature, the residual lattice strain in the top silicon layer is tensile. After annealing at 1100° C for an hour, the strain in the top Si decreases greatly and reverses from tensile to slightly compressive as a result of viscous flow of AlN.

  2. Integration of self-assembled three-dimensional photonic crystals onto structured silicon wafers.

    Science.gov (United States)

    Ye, Jianhui; Zentel, Rudolf; Arpiainen, Sanna; Ahopelto, Jouni; Jonsson, Fredrik; Romanov, Sergei G; Sotomayor Torres, Clivia M

    2006-08-15

    We report on the fabrication of high-quality opaline photonic crystals from large silica spheres (diameter of 890 nm), self-assembled in hydrophilic trenches of silicon wafers by using a novel technique coined a combination of "lifting and stirring". The achievements reported here comprise a spatial selectivity of opal crystallization without special treatment of the wafer surface, a filling of the trenches up to the top, leading to a spatially uniform film thickness, particularly an absence of cracks within the size of the trenches, and finally a good 3D order of the opal lattice even in trenches with a complex confined geometry, verified using optical measurements. The opal lattice was found to match the pattern precisely in width as well as depth, providing an important step toward applications of opals in integrated optics.

  3. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  4. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Science.gov (United States)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  5. Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

    Science.gov (United States)

    Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

    2016-03-01

    Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low

  6. Eutectic and solid-state wafer bonding of silicon with gold

    Energy Technology Data Exchange (ETDEWEB)

    Abouie, Maryam; Liu, Qi [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 (Canada); Ivey, Douglas G., E-mail: doug.ivey@ualberta.ca [Department of Chemical and Materials Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4 (Canada)

    2012-12-01

    Highlights: Black-Right-Pointing-Pointer Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. Black-Right-Pointing-Pointer Exchange of a-Si and Au layer was observed in both types of bonded samples. Black-Right-Pointing-Pointer Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. Black-Right-Pointing-Pointer Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 Degree-Sign C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 Degree-Sign C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  7. Correlation Between the Raman Crystallinity of p-Type Micro-Crystalline Silicon Layer and Open Circuit Voltage of n-i-p Solar Cells.

    Science.gov (United States)

    Jung, Junhee; Kim, Sunbo; Park, Jinjoo; Shin, Chonghoon; Pham, Duy Phong; Kim, Jiwoong; Chung, Sungyoun; Lee, Youngseok; Yi, Junsin

    2015-10-01

    This article mainly discusses the difference between p-i-n and n-i-p type solar cells. Their structural difference has an effect on cell performance, such as open circuit voltage and fill factor. Although the deposition conditions are the same for both p-i-n and n-i-p cases, the substrate layers for depositing p-type microcrystalline silicon layers differ. In n-i-p cells, the substrate layer is p-type amorphous silicon oxide layer; whereas, in p-i-n cells, the substrate layer is ZnO:Al. The interfacial change leads to a 12% difference in the crystallinity of the p-type microcrystalline silicon layers. When the p-type microcrystalline silicon layer's crystallinity was not sufficient to activate an internal electric field, the open circuit voltage and fill factor decreased 0.075 V and 7.36%, respectively. We analyzed this problem by comparing the Raman spectra, electrical conductivity, activation energy and solar cell performance. By adjusting the thickness of the p-type microcrystalline silicon layer, we increased the open circuit voltage of the n-i-p cell from 0.835 to 0.91 V.

  8. Atomically flattening of Si surface of silicon on insulator and isolation-patterned wafers

    Science.gov (United States)

    Goto, Tetsuya; Kuroda, Rihito; Akagawa, Naoya; Suwa, Tomoyuki; Teramoto, Akinobu; Li, Xiang; Obara, Toshiki; Kimoto, Daiki; Sugawa, Shigetoshi; Ohmi, Tadahiro; Kamata, Yutaka; Kumagai, Yuki; Shibusawa, Katsuhiko

    2015-04-01

    By introducing high-purity and low-temperature Ar annealing at 850 °C, atomically flat Si surfaces of silicon-on-insulator (SOI) and shallow-trench-isolation (STI)-patterned wafers were obtained. In the case of the STI-patterned wafer, this low-temperature annealing and subsequent radical oxidation to form a gate oxide film were introduced into the complementary metal oxide semiconductor (CMOS) process with 0.22 µm technology. As a result, a test array circuit for evaluating the electrical characteristics of a very large number (>260,000) of metal oxide semiconductor field effect transistors (MOSFETs) having an atomically flat gate insulator/Si interface was successfully fabricated on a 200-mm-diameter wafer. By evaluating 262,144 nMOSFETs, it was found that not only the gate oxide reliability was improved, but also the noise amplitude of the gate-source voltage related to the random telegraph noise (RTN) was reduced owing to the introduction of the atomically flat gate insulator/Si interface.

  9. Silicon wafer microstructure imaging using InfraRed Transport of Intensity Equation

    Science.gov (United States)

    Li, Hongru; Feng, Guoying; Bourgade, Thomas; Zuo, Chao; Du, Yongzhao; Zhou, Shouhuan; Asundi, Anand

    2015-03-01

    A novel quantitative 3D imaging system of silicon microstructures using InfraRed Transport of Intensity Equation (IRTIE) is proposed in this paper. By recording the intensity at multiple planes and using FFT or DCT based TIE solver, fast and accurate phase retrieval for both uniform and non-uniform intensity distributions is proposed. Numerical simulation and experiments confirm the accuracy and reliability of the proposed method. The application of IR-TIE for inspection of micro-patterns in visibly opaque media using 1310 nm light source is demonstrated. For comparison, micro-patterns are also inspected by the contact scanning mode Taylor Hobson system. Quantitative agreement suggests the possibility of using IR-TIE for phase imaging of silicon wafers.

  10. Effects of indium tin oxide on the performance of heterojunction silicon wafer solar cells

    Science.gov (United States)

    Huang, Mei; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    The effects of indium tin oxide (ITO) films on the performance of heterojunction silicon wafer solar cells is investigated, using heterojunction (HET) solar cell precursors. Different ITO deposition conditions are used, which result in significant differences in the performance of HET solar cells. It is found that HET solar cells with ITO films deposited at room temperature exhibit severer sputter damage, while those with substrate heating show less damage. Besides the ITO deposition temperature, the sputtering gas ambient is also investigated. The hydrogen gas used in the ITO deposition can greatly affect the interface properties between the ITO film and the amorphous silicon layers. The champion solar cell fabricated under the optimum ITO deposition conditions (a deposition temperature of 150 °C with optimal gas concentration) shows a conversion efficiency of 19.7%.

  11. Chemical processing of materials on silicon: more functionality, smaller features, and larger wafers.

    Science.gov (United States)

    Marchack, Nathan; Chang, Jane P

    2012-01-01

    The invention of the transistor followed by more than 60 years of aggressive device scaling and process integration has enabled the global information web and subsequently transformed how people communicate and interact. The principles and practices built upon chemical processing of materials on silicon have been widely adapted and applied to other equally important areas, such as microfluidic systems for chemical and biological analysis and microscale energy storage solutions. The challenge of continuing these technological advances hinges on further improving the performance of individual devices and their interconnectivity while making the manufacturing processes economical, which is dictated by the materials' innate functionality and how they are chemically processed. In this review, we highlight challenges in scaling up the silicon wafers and scaling down the individual devices as well as focus on needs and challenges in the synthesis and integration of multifunctional materials.

  12. Length Scale Dependence of Periodic Textures for Photoabsorption Enhancement in Ultra-thin Silicon Foils and Thick Wafers

    CERN Document Server

    Kumar, K; Liu, G; Nogami, J; Kherani, N P

    2016-01-01

    In this paper, we simulate a front surface inverted pyramidal grating texture on 2 to 400 micron thick silicon and optimize it to derive maximum photocurrent density from the cell. We identify a one size fits all front grating period of 1000 nm that leads to maximum photo-absorption of normally incident AM1.5g solar spectrum in silicon (configured with a back surface reflector) irrespective of the thickness of the crystalline silicon absorbing layer. With the identification of such universally optimized periodicity for the case of an inverted pyramidal grating texture, a common fabrication process can be designed to manufacture high-efficiency devices on crystalline silicon regardless of wafer thickness. In order to validate the results of the simulation, we fabricated high resolution inverted pyramidal textures on a 400 micron thick silicon wafer with electron beam lithography to compare the reflectance from submicron and wavelength scale periodic textures. The experimental reflectance measurements on textur...

  13. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  14. A method of reducing background radiance for emissivity-compensated radiation thermometry of silicon wafers.

    Science.gov (United States)

    Iuchi, T; Toyoda, Y; Seo, T

    2013-02-01

    We studied the spectral and directional emissivities of silicon wafers using an optical polarization technique. Based on simulation and experimental results, we developed two radiation thermometry methods for silicon wafers: one is based on the polarized emissivity-invariant condition and the other is based on the relationship between the ratio of the p- and s-polarized radiance and the polarized emissivity. These methods can be performed at temperatures above 600 °C and over a wide wavelength range (0.9-4.8 μm), irrespective of the dielectric film thickness and the substrate resistivity, which depends on the dopant concentration. The temperature measurements were estimated to have expanded uncertainties (k = 2) of less than 5 °C. With a view to practically applying these methods, we investigated a method to reduce the intense background radiance produced by high-intensity heating lamps. We found that the background radiance can be greatly reduced by using a radiometer that is sensitive to wavelengths of 4.5 or 4.8 μm and suitable geometrical arrangements of a quartz plate. This opens up the possibility of using the two proposed radiation thermometry methods in practical applications.

  15. Development of a miniature silicon wafer fuel cell using L-ascorbic acid as fuel

    Institute of Scientific and Technical Information of China (English)

    Jian WO; Zhi-yong XIAO; Yi-bin YING; Philip C.H. CHAN

    2008-01-01

    In the current studies a miniature silicon wafer fuel cell (FC) using L-ascorbic acid as fuel was developed, The cell employs L-ascorbic acid and air as reactants and a thin polymer electrolyte as a separator. Inductively coupled plasma (ICP) silicon etching was employed to fabricate high aspect-ratio columns on the silicon substrate to increase the surface area. A thin platinum layer deposited directly on the silicon surface by the sputtering was used as the catalyst layer for L-ascorbic acid electro-oxidation.Cyclic voltammetry shows that the oxidation of L-ascorbic acid on the sputtered platinum layer is irreversible and that the onset potentials for the oxidation of L-ascorbic acid are from 0.27 V to 0.35 V versus an Ag/AgCI reference electrode. It is found that at the room temperature, with 1 mol/L L-ascorbic acid/PBS (phosphate buffered solution) solution pumped to the anode at 1 ml/min flow rate and air spontaneously diffusing to the cathode as the oxidant, the maximum output power density of the cell was 1.95m W/cm2 at a current density of 10 mA/cm2.

  16. A novel method to enhance the gettering efficiency in p-type Czochralski silicon by a sacrificial porous silicon layer

    Institute of Scientific and Technical Information of China (English)

    Zhang Caizhen; Wang Yongshun; Wang Zaixing

    2011-01-01

    A new two-step phosphorous diffusion gettering (TSPDG) process using a sacrificial porous silicon layer (PSL) is proposed.Due to a decrease in high temperature time,the TSPDG (PSL) process weakens the deterioration in performances of PSL,and increases the capability of impurity clusters to dissolve and diffuse to the gettering regions.By means of the TSPDG (PSL) process under conditions of 900 ℃/60 min + 700 ℃/30 min,the effective lifetime of minority carriers in solar-grade (SOG) Si is increased to 14.3 times its original value,and the short-circuit current density of solar cells is improved from 23.5 o 28.7 mA/cm2,and the open-circuit voltage from 0.534 to 0.596 V along with the transform efficiency from 8.1% to 11.8%,which are much superior to the results achieved by the PDG (PSL) process at 900 ℃ for 90 min.

  17. Elastic Softening of Surface Acoustic Wave Caused by Vacancy Orbital in Silicon Wafer

    Science.gov (United States)

    Mitsumoto, Keisuke; Akatsu, Mitsuhiro; Baba, Shotaro; Takasu, Rie; Nemoto, Yuichi; Goto, Terutaka; Yamada-Kaneta, Hiroshi; Furumura, Yuji; Saito, Hiroyuki; Kashima, Kazuhiko; Saito, Yoshihiko

    2014-03-01

    We have performed surface acoustic wave (SAW) measurements to examine vacancies in a surface layer of a boron-doped silicon wafer currently used in semiconductor industry. A SAW with a frequency of fs = 517 MHz was optimally generated by an interdigital transducer with a comb gap of w=2.5 µm on a piezoelectric ZnO film deposited on the (001) silicon surface. The SAW propagating along the [100] axis with a velocity of vs=4.967 km/s is in agreement with the Rayleigh wave, which shows an ellipsoidal trajectory motion in the displacement components ux and uz within a penetration depth of λp = 3.5 µm. The elastic constant Cs of the SAW revealed the softening of ΔCs/Cs = 1.9 × 10-4 below 2 K down to 23 mK. Applied magnetic fields of up to 2 T completely suppress the softening. The quadrupole susceptibilities based on the coupling between the electric quadrupoles Ou, Ov, and Ozx of the vacancy orbital consisting of Γ8-Γ7 states and the symmetry strains ɛu, ɛv, and ɛzx associated with the SAW account for the softening and its field dependence on Cs. We deduced a low vacancy concentration N = 3.1 × 1012/cm3 in the surface layer within λp = 3.5 µm of the silicon wafer. This result promises an innovative technology for vacancy evaluation in the fabrication of high-density semiconductor devices in industry.

  18. Study of nanoparticles TiO2 thin films on p-type silicon substrate using different alcoholic solvents

    Science.gov (United States)

    Muaz, A. K. M.; Hashim, U.; Arshad, M. K. Md.; Ruslinda, A. R.; Ayub, R. M.; Gopinath, Subash C. B.; Voon, C. H.; Liu, Wei-Wen; Foo, K. L.

    2016-07-01

    In this paper, sol-gel method spin coating technique is adopted to prepare nanoparticles titanium dioxide (TiO2) thin films. The prepared TiO2 sol was synthesized using titanium butoxide act as a precursor and subjected to deposited on the p-type silicon oxide (p-SiO2) and glass slide substrates under room temperature. The effect of different alcoholic solvents of methanol and ethanol on the structural, morphological, optical and electrical properties were systematically investigated. The coated TiO2 thin films were annealed in furnace at 773 K for 1 h. The structural properties of the TiO2 films were examined with X-ray Diffraction (XRD). From the XRD analysis, both solvents showing good crystallinity with anatase phase were the predominant structure. Atomic Force Microscopy (AFM) was employed to study the morphological of the thin films. The optical properties were investigated by Ultraviolet-visible (UV-Vis) spectroscopy were found that ethanol as a solvent give a higher optical transmittance if compare to the methanol solvent. The electrical properties of the nanoparticles TiO2 thin films were measured using two-point-probe technique.

  19. Oligo(ethylene glycol) monolayers by silanization of silicon wafers: Real nature and stability.

    Science.gov (United States)

    Dekeyser, C M; Buron, C C; Mc Evoy, K; Dupont-Gillain, C C; Marchand-Brynaert, J; Jonas, A M; Rouxhet, P G

    2008-08-01

    Grafting silicon wafers with CH(3)O(CH(2)CH(2)O)(n)C(3)H(6)-trimethoxysilane and -trichlorosilane (n=6 to 9) was performed in different conditions (solvent, reaction time, washing) in order to select procedures compatible with the design of nanostructured surfaces for biomaterial applications, using electron-beam lithography. After a first screening by principal component analysis (PCA), the X-ray photoelectron spectroscopy (XPS) data were analyzed by plotting the carbon to oxygen molar ratio vs the molar ratio of carbon singly bound to oxygen [CO] over carbon bound only to carbon and hydrogen [C(C,H)]. This was found to be a convenient method for discarding samples containing free polymerized silane. Such excess occurred as a result of insufficient washing or unsuitable solvent for the reaction (ether), as confirmed by AFM and thickness measured by X-ray reflectometry. Angle resolved XPS analysis indicated that the grafted silane layer had a 1-2 nm thickness and was covered by a thin layer of adventitious contaminant. As a result, the surface chemical composition obtained covered a broad range (O/C of 0.4 to 1.1; CO/C(C,H) of 2.5 to 6.5); variations could not be related to the nature of the silane reagent and no significant difference was found between hexane and toluene as solvent for the reaction. The grafted silane layer was not stable upon incubation during 24 h in phosphate buffered saline (PBS) at 37 degrees C, which mimics biological environments. As a consequence, the grafted wafers did not show protein repellent properties. This alteration was not observed at room temperature. XPS analysis demonstrated that silane layer detachment was due to a hydrolysis within the SiO(2) layer initially present at the wafer surface.

  20. RADICAL GRAFTING OF POLY(METHYL METHACRYLATE) ONTO SILICON-WAFERS, GLASS SLIDES AND GLASS-BEADS

    NARCIS (Netherlands)

    FOLKERSMA, R; CHALLA, G; SCHOUTEN, AJ

    1991-01-01

    Poly(methyl methacrylate) was grafted onto glass beads, glass slides and silicon wafers using an immobilized radical initiator. The polymeric monolayers had thicknesses varying from a few hundred to 4000 angstrom, being up to 10 times larger than the radii of gyration of comparable free polymers. Du

  1. Microscopic Distributions of Defect Luminescence From Subgrain Boundaries in Multicrystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Hieu T.; Jensen, Mallory A.; Li, Li; Samundsett, Christian; Sio, Hang C.; Lai, Barry; Buonassisi, Tonio; Macdonald, Daniel

    2017-05-01

    We investigate the microscopic distributions of sub-band-gap luminescence emission (the so-called D-lines D1/D2/D3/D4) and the band-to-band luminescence intensity, near recombination-active sub-grain boundaries in multicrystalline silicon wafers for solar cells. We find that the sub-band-gap luminescence from decorating defects/impurities (D1/D2) and from intrinsic dislocations (D3/D4) have distinctly different spatial distributions, and are asymmetric across the sub-grain boundaries. The presence of D1/D2 is correlated with a strong reduction in the band-to-band luminescence, indicating a higher recombination activity. In contrast, D3/D4 emissions are not strongly correlated with the band-to-band intensity. Based on spatially-resolved, synchrotron-based micro-X-ray fluorescence measurements of metal impurities, we confirm that high densities of metal impurities are present at locations with strong D1/D2 emission but low D3/D4 emission. Finally, we show that the observed asymmetry of the sub-band-gap luminescence across the sub-grain boundaries is due to their inclination below the wafer surface. Based on the luminescence asymmetries, the sub-grain boundaries are shown to share a common inclination locally, rather than be orientated randomly.

  2. Ultraclean wafer-level vacuum-encapsulated silicon ring resonators for timing and frequency references

    Science.gov (United States)

    Xereas, George; Chodavarapu, Vamsy P.

    2016-07-01

    We present the design and development of breath-mode silicon ring resonators fabricated using a commercial pure-play microfabrication process that provides ultraclean wafer-level vacuum-encapsulation. The micromechanical resonators are fabricated in MEMS integrated design for inertial sensors process that is developed by Teledyne DALSA Semiconductor Inc. The ring resonators are designed to operate with a relatively low DC polarization voltage, starting at 5 V, while providing a high frequency-quality factor product. We study the quality of the vacuum packaging using an automated testing setup over an extended time period. We study the effect of motional resistance on the performance of MEMS resonators. The fabricated devices had a resonant frequency of 10 MHz with the quality factor exceeding 8.4×104.

  3. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    CERN Document Server

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  4. Optical and Electrical Effects of p-type μc-SiOx:H in Thin-Film Silicon Solar Cells on Various Front Textures

    Directory of Open Access Journals (Sweden)

    Chao Zhang

    2014-01-01

    Full Text Available p-type hydrogenated microcrystalline silicon oxide (µc-SiOx:H was developed and implemented as a contact layer in hydrogenated amorphous silicon (a-Si:H single junction solar cells. Higher transparency, sufficient electrical conductivity, low ohmic contact to sputtered ZnO:Al, and tunable refractive index make p-type µc-SiOx:H a promising alternative to the commonly used p-type hydrogenated microcrystalline silicon (µc-Si:H contact layers. In this work, p-type µc-SiOx:H layers were fabricated with a conductivity of up to 10−2 S/cm and a Raman crystallinity of above 60%. Furthermore, we present p-type µc-SiOx:H films with a broad range of optical properties (2.1 eV < band gap E04<2.8 eV and 1.6 < refractive index n<2.6. These properties can be tuned by adapting deposition parameters, for example, the CO2/SiH4 deposition gas ratio. A conversion efficiency improvement of a-Si:H solar cells is achieved by applying p-type µc-SiOx:H contact layer compared to the standard p-type µc-Si:H contact layer. As another aspect, the influence of the front side texture on a-Si:H p-i-n solar cells with different p-type contact layers, µc-Si:H and µc-SiOx:H, is investigated. Furthermore, we discuss the correlation between the decrease of Voc and the cell surface area derived from AFM measurements.

  5. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  6. Simulations and Silicon Wafer Compatibility of a Voltage-Controlled Optical Switch Using ITO/NbOx

    Science.gov (United States)

    Burghardt, Kevin

    The story of optics and processing has always been on of silicon devices making strides faster and cheaper than optics. The idea of creating optical switches has been generally relegated to academic exercises or niche markets. This research takes a view of optical processing that is complimentary to silicon. Silicon wafers produce extremely dense, high quality devices but producing truly 3D integrated circuits has been a challenge. It would be advantageous to not need to bond wafers to create a 3D active structure. An argument for an optical switch that has a simple structure and uses industry established fabrication methods is given. The proposed switch uses the material indium tin oxide nanoparticles in niobum oxide glass (ITO/NbOx) as the active layer. The transmittance through this material is proportional to the electric field applied to it meaning the structure of a capacitor could be used to control it. It uses a metal for one plate of the capacitor and the ITO/NbOx as the other plate with the light running through ITO/NbO x plate. Each of the plates are separated from one another and surrounded by a dielectric material. Simulations show that silicon dioxide (SiO 2) can be used effectively to turn the ITO/NbOx into a light guide with a transmittance controllable using an applied voltage and that the proposed structure can be created using industry established wafer fabrication processes.

  7. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  8. Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

    Science.gov (United States)

    Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

    2013-05-06

    Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

  9. Achieving Uniform Monolayer Transition Metal Dichalcogenides Film on Silicon Wafer via Silanization Treatment: A Typical Study on WS2.

    Science.gov (United States)

    Chen, Ying; Gan, Lin; Li, Huiqiao; Ma, Ying; Zhai, Tianyou

    2017-02-01

    A silanization reaction is employed to improve the dispersion of precursors on a silicon wafer for a large-size uniform transition metal dichalcogenide (TMD) film synthesis and to achieve a highly crystalline monolayer WS2 film up to 1 cm(2) . The novel strategy is also verified for the synthesis of WSe2 and MoS2 uniform films, suggesting universality for TMD film fabrication.

  10. Defects, detection and measurement on polished silicon wafer surface by atomic force microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Lee, W.P.; Seow, W.S. [S.E.H. (M) Sdn. Kuala Lumpur (Malaysia); Yow, H.K.; Tou, T.Y. [Multimedia Univ., Faculty of Engineering, Cyberjaya (Malaysia)

    2000-01-01

    Crystal originated ''particles'' (COPs) have been recognized as surface defects or micro-pits which originate from grown-in defects. The basic microstructure of the COP is an octahedral void with faces along the {l_brace}111{r_brace} orientation. In this paper, COPs were detected using an optical scattering technique and the change of their widths in an etching solution of NH{sub 4}OH:H{sub 2}O{sub 2}:H{sub 2}O (SC-1) was measured using atomic force microscopy (AFM). The rate of change in the width, r, of these COPs in the SC-1 solution was determined. r can be used to determine if a COP emanated from either the upper or lower portion of the void. For a single type COP originating from the lower portion of the void, r was measured to be 0.94 nm/min along the left angle 011 right angle direction. However, a single type COP from the upper portion has an r value of 2.5 nm/min. For this case, two factors are responsible for the higher rate; the etching of silicon horizontally along the left angle 011 right angle direction and the sloping {l_brace}111{r_brace} surface of the octahedral void during the removal of the silicon (100) plane. Further, a single type COP might also develop into a twin type COP after repeated SC-1 dipping if there is a second void located close to the first COP but lying just below the wafer surface. (orig.)

  11. Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer

    Science.gov (United States)

    Zhenlong, Zhang; Xiangyang, Liu; Yanli, Mao

    2009-09-01

    The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator (SOI) wafer. The access resistance and capacitance of SOI-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.

  12. XANES and IR spectroscopy study of the electronic structure and chemical composition of porous silicon on n- and p-type substrates

    Energy Technology Data Exchange (ETDEWEB)

    Lenshin, A. S., E-mail: lenshinas@phys.vsu.ru; Kashkarov, V. M.; Seredin, P. V. [Voronezh State University (Russian Federation); Spivak, Yu. M.; Moshnikov, V. A. [LETI St. Petersburg State Electrotechnical University (Russian Federation)

    2011-09-15

    The differences in the electronic structure and composition of porous silicon samples obtained under identical conditions of electrochemical etching on the most commonly used n- and p-type substrates with different conductivities are demonstrated by X-ray absorption near-edge spectroscopy (XANES) and Fourier transform IR spectroscopy (FTIR) methods. It is shown that significantly higher oxidation and saturation with hydrogen is observed for the porous layer on n-type substrates.

  13. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  14. Second-harmonic generation in periodically-poled thin film lithium niobate wafer-bonded on silicon

    Science.gov (United States)

    Rao, Ashutosh; Malinowski, Marcin; Honardoost, Amirmahdi; Talukder, Javed Rouf; Rabiei, Payam; Delfyett, Peter; Fathpour, Sasan

    2016-12-01

    Second-order optical nonlinear effects (second-harmonic and sum-frequency generation) are demonstrated in the telecommunication band by periodic poling of thin films of lithium niobate wafer-bonded on silicon substrates and rib-loaded with silicon nitride channels to attain ridge waveguide with cross-sections of ~ 2 {\\mu}m2. The compactness of the waveguides results in efficient second-order nonlinear devices. A nonlinear conversion of 8% is obtained with a pulsed input in 4 mm long waveguides. The choice of silicon substrate makes the platform potentially compatible with silicon photonics, and therefore may pave the path towards on-chip nonlinear and quantum-optic applications.

  15. Second-harmonic generation in periodically-poled thin film lithium niobate wafer-bonded on silicon

    CERN Document Server

    Rao, Ashutosh; Honardoost, Amirmahdi; Talukder, Javed Rouf; Rabiei, Rayam; Delfyett, Peter; Fathpour, Sasan

    2016-01-01

    Second-order optical nonlinear effects (second-harmonic and sum-frequency generation) are demonstrated in the telecommunication band by periodic poling of thin films of lithium niobate wafer-bonded on silicon substrates and rib-loaded with silicon nitride channels to attain ridge waveguide with cross-sections of ~ 2 {\\mu}m2. The compactness of the waveguides results in efficient second-order nonlinear devices. A nonlinear conversion of 8% is obtained with a pulsed input in 4 mm long waveguides. The choice of silicon substrate makes the platform potentially compatible with silicon photonics, and therefore may pave the path towards on-chip nonlinear and quantum-optic applications.

  16. Impact of common metallurgical impurities on ms-Si solar cell efficiency. P-type versus n-type doped ingots

    Energy Technology Data Exchange (ETDEWEB)

    Geerligs, L.J.; Manshanden, P. [ECN Solar Energy, Petten (Netherlands); Solheim, I.; Ovrelid, E.J.; Waernes, A.N. [Sintef materials technology, Trondheim (Norway)

    2006-09-15

    Silicon solar cells based on n-type silicon wafers are less sensitive to carrier lifetime degradation due to several common metal impurities than p-base cells. The theoretical and experimental indications for this have recently received considerable attention. This paper compares p-type and n-type cells purposely contaminated with relatively high levels of impurities, processed by industrial techniques. The impurities considered are Al, Ti, and Fe, which are the dominant impurities in metallurgical silicon and natural quartz. The work also preliminary addresses the question whether the optimal wafer resistivity is the same for n-type as for p-type base mc-Si cells.

  17. Ultra-thin crystalline silicon films produced by plasma assisted epitaxial growth on silicon wafers and their transfer to foreign substrates*

    Directory of Open Access Journals (Sweden)

    Cabarrocas P. Roca i

    2010-10-01

    Full Text Available We have developed a new process to produce ultra-thin crystalline silicon films with thicknesses in the range of 0.1 − 1 μm on flexible substrates. A crystalline silicon wafer was cleaned by SiF4 plasma exposure and without breaking vacuum, an epitaxial film was grown from SiF4, H2 and Ar gas mixtures at low substrate temperature (Tsub ≈ 200 °C in a standard RF PECVD reactor. We found that H2 dilution is a key parameter for the growth of high quality epitaxial films and modification of the structural composition of the interface with the c-Si wafer, allowing one to switch from a smooth interface at low hydrogen flow rates to a fragile one, composed of hydrogen-rich micro-cavities, at high hydrogen flow rates. This feature can be advantageously used to separate the epitaxial film from the crystalline Si wafer. As a example demonstration, we show that by depositing a metal film followed by a spin-coated polyimide layer and applying a moderate thermal treatment to the stack, the fragile interface breaks down and allows one to obtain an ultrathin crystalline wafer on the flexible polyimide support.

  18. Iron-boron pairing kinetics in illuminated p-type and in boron/phosphorus co-doped n-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Möller, Christian, E-mail: cmoeller@cismst.de [CiS Forschungsinstitut für Mikrosensorik und Photovoltaik GmbH, Konrad-Zuse-Str. 14, 99099 Erfurt (Germany); TU Ilmenau, Institut für Physik, Weimarer Str. 32, 98693 Ilmenau (Germany); Bartel, Til; Gibaja, Fabien [Calisolar GmbH, Magnusstraße 11, 12489 Berlin (Germany); Lauer, Kevin [CiS Forschungsinstitut für Mikrosensorik und Photovoltaik GmbH, Konrad-Zuse-Str. 14, 99099 Erfurt (Germany)

    2014-07-14

    Iron-boron (FeB) pairing is observed in the n-type region of a boron and phosphorus co-doped silicon sample which is unexpected from the FeB pair model of Kimerling and Benton. To explain the experimental data, the existing FeB pair model is extended by taking into account the electronic capture and emission rates at the interstitial iron (Fe{sub i}) trap level as a function of the charge carrier densities. According to this model, the charge state of the Fe{sub i} may be charged in n-type making FeB association possible. Further, FeB pair formation during illumination in p-type silicon is investigated. This permits the determination of the charge carrier density dependent FeB dissociation rate and in consequence allows to determine the acceptor concentration in the co-doped n-type silicon by lifetime measurement.

  19. P-stop isolation study of irradiated n-in-p type silicon strip sensors for harsh radiation environments

    Science.gov (United States)

    Printz, Martin

    2016-09-01

    In order to determine the most radiation hard silicon sensors for the CMS Experiment after the Phase II Upgrade in 2023 a comprehensive study of silicon sensors after a fluence of up to 1.5 ×1015neq /cm2 corresponding to 3000fb-1 after the HL-LHC era has been carried out. The results led to the decision that the future Outer Tracker (20 cm MIPs penetrating the sensor between two strips.

  20. The life-cycle environmental impacts of etching silicon wafers and (PE)CVD chamber cleaning

    Energy Technology Data Exchange (ETDEWEB)

    Schottler, M. [M and W Zander FE, Stuttgart (Germany); De Wild-Scholten, M.J. [ECN Solar Energy, Petten (Netherlands)

    2008-09-15

    Fluorinated gases are used by the semiconductor and photovoltaic industry for etching silicon wafers and (PE)CVD chamber cleaning. The desired result is due to F atoms and other reactive species, but the emission of the undecomposed PFC (perfluorinated) gases is unwanted because they have a high global warming effect and high atmospheric life-time. In this study a full life-cycle assessment is used in order to (1) compare the environmental impacts of the different technologies and (2) to indicate improvement options. The steps in the life cycle are the following: synthesis of the compounds, transportation, distribution in the fab (connection of cylinders), use in the process, abatement to destroy the unreacted gases and take-back of cylinders. Emissions from each step can be direct (from emission of the fluorinated gases) or indirect (from energy use). Results, partly based on best guesses, indicate that fugitive emissions of the fluorinated gases during synthesis, downtime of abatement system and cleaning of the not completely empty cylinders dominate the life-cycle global warming effect. This means that the global warming effect of the gas itself determines the effect being the highest for SF6. F2 turns out to be clearly in advantage over the other fluorinated compounds because it has a global warming potential of zero with moderate efforts for synthesis. Possible improvement options to minimize the use and emission of fluorinated gas are (1) strict procedure for connection of cylinders, (2) complete usage or reliable abatement of the gas from the bottle, (3) the recovery or reliable abatement of unused gases from the process and (4) end-point detection of the process.

  1. Interface modification effect between p-type a-SiC:H and ZnO:Al in p-i-n amorphous silicon solar cells.

    Science.gov (United States)

    Baek, Seungsin; Lee, Jeong Chul; Lee, Youn-Jung; Iftiquar, Sk Md; Kim, Youngkuk; Park, Jinjoo; Yi, Junsin

    2012-01-18

    Aluminum-doped zinc oxide (ZnO:Al) [AZO] is a good candidate to be used as a transparent conducting oxide [TCO]. For solar cells having a hydrogenated amorphous silicon carbide [a-SiC:H] or hydrogenated amorphous silicon [a-Si:H] window layer, the use of the AZO as TCO results in a deterioration of fill factor [FF], so fluorine-doped tin oxide (Sn02:F) [FTO] is usually preferred as a TCO. In this study, interface engineering is carried out at the AZO and p-type a-SiC:H interface to obtain a better solar cell performance without loss in the FF. The abrupt potential barrier at the interface of AZO and p-type a-SiC:H is made gradual by inserting a buffer layer. A few-nanometer-thick nanocrystalline silicon buffer layer between the AZO and a-SiC:H enhances the FF from 67% to 73% and the efficiency from 7.30% to 8.18%. Further improvements in the solar cell performance are expected through optimization of cell structures and doping levels.

  2. Assessing the role of iron-acceptor pairs in solar grade multicrystalline silicon wafers from the metallurgical route

    Energy Technology Data Exchange (ETDEWEB)

    Hvidsten Dahl, Espen [Department of Physics and Astronomy/iNANO, Aarhus University, Aarhus (Denmark); Elkem AS Technology, Kristiansand (Norway); Osinniy, Viktor [Department of Physics and Astronomy/iNANO, Aarhus University, Aarhus (Denmark); RACell Solar AS, Fredriksberg (Denmark); Friestad, Kenneth; Soeiland, Anne-Karin [Elkem AS Solar, Kristiansand (Norway); Safir, Yakov [RACell Solar AS, Fredriksberg (Denmark); Skorupa, Wolgang [Institute of Ion Beam Physics and Materials Research, Forschungszentrum Dresden-Rossendorf e.V., Dresden (Germany); Tronstad, Ragnar [Elkem AS Technology, Kristiansand (Norway); Nylandsted Larsen, Arne [Department of Physics and Astronomy/iNANO, Aarhus University, Aarhus (Denmark)

    2012-10-15

    The recombination parameters of iron-boron (FeB), iron-aluminium (FeAl) and iron-gallium (FeGa) pairs in Fe implanted FZ monocrystalline silicon wafers and Fe contaminated multicrystalline silicon (mc-Si) wafers of solar grade feedstock from the metallurgical route have been studied by combining the Deep Level Transient Spectroscopy (DLTS) and Microwave Photoconductive Decay ({mu}-PCD) techniques. Energy levels associated with FeB, FeAl and FeGa pairs were detected in the monocrystalline samples. The activation energy and capture cross section of these levels were determined. FeGa gave the strongest recombination effect, reducing the minority carrier lifetime of the sample from about 39 {mu}s to 0.7 {mu}s at a concentration of 4x10{sup 13} cm{sup -3}. No electrically active iron-acceptor pairs could be detected in the mc-Si wafer. However, it was demonstrated that micrometer-sized clusters, most likely composed of metallic oxides, collect iron from the bulk. This iron collection may reduce the available amount of iron for creating electrically active iron-acceptor pairs below the detection limit of DLTS. The contamination did, however, degrade the lifetime from 40 {mu}s to less than 1 {mu}s in the wafer. This is likely a result of at least three overlapping energy levels believed to be related to iron (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  3. Gas doping ratio effects on p-type hydrogenated nanocrystalline silicon thin films grown by hot-wire chemical vapor deposition

    Energy Technology Data Exchange (ETDEWEB)

    Luo, P.Q. [Solar Energy Institute, Department of Physics, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai 200240 (China)], E-mail: robt@sjtu.edu.cn; Zhou, Z.B. [Solar Energy Institute, Department of Physics, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai 200240 (China)], E-mail: zbzhou@sjtu.edu.cn; Chan, K.Y. [Thin Film Laboratory, Faculty of Engineering, Multimedia University, Jalan Multimedia, Cyberjaya 63100, Selangor (Malaysia); Tang, D.Y.; Cui, R.Q.; Dou, X.M. [Solar Energy Institute, Department of Physics, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai 200240 (China)

    2008-12-30

    Hydrogenated nanocrystalline silicon (nc-Si:H) grown by hot-wire chemical vapor deposition (HWCVD) has recently drawn significant attention in the area of thin-film large area optoelectronics due to possibility of high deposition rate. We report on the effects of diborane (B{sub 2}H{sub 6}) doping ratio on the microstructural and optoelectrical properties of the p-type nc-Si:H thin films grown by HWCVD at low substrate temperature of 200 deg. C and with high hydrogen dilution ratio of 98.8%. An attempt has been made to elucidate the boron doping mechanism of the p-type nc-Si:H thin films deposited by HWCVD and the correlation between the B{sub 2}H{sub 6} doping ratio, crystalline volume fraction, optical band gap and dark conductivity.

  4. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  5. Wafer-level packaging and laser bonding as an approach for silicon-into-lab-on-chip integration

    Science.gov (United States)

    Brettschneider, T.; Dorrer, C.; Bründel, M.; Zengerle, R.; Daub, M.

    2013-05-01

    A novel approach for the integration of silicon biosensors into microfluidics is presented. Our approach is based on wafer-level packaging of the silicon die and a laser-bonding process of the resulting mold package into a polymer-multilayer stack. The introduction of a flexible and 40 μm thin hot melt foil as an intermediate layer enables laser bonding between materials with different melting temperatures, where standard laser welding processes cannot be employed. All process steps are suitable for mass production, e.g. the approach does not involve any dispensing steps for glue or underfiller. The integration approach was demonstrated and evaluated regarding process technology by wafer-level redistribution of daisy chain silicon dies representing a generic biosensor. Electrical connection was successfully established and laser-bonding tensile strength of 5.7 N mm-2 and burst pressure of 587 kPa at a temperature of 100 °C were achieved for the new material combination. The feasibility of the complete packaging approach was shown by the fabrication of a microfluidic flow cell with embedded mold package.

  6. Fabricating nanostructures through a combination of nano-oxidation and wet etching on silicon wafers with different surface conditions.

    Science.gov (United States)

    Huang, Jen-Ching

    2012-01-01

    This study investigates the surface conditions of silicon wafers with native oxide layers (NOL) or hydrogen passivated layers (HPL) and how they influence the processes of nano-oxidation and wet etching. We also explore the combination of nano-oxidation and wet etching processes to produce nanostructures. Experimental results reveal that the surface conditions of silicon wafers have a considerable impact on the results of nano-oxidation when combined with wet etching. The height and width of oxides on NOL samples exceeded the dimensions of oxides on HPL samples, and this difference became increasingly evident with an increase in applied bias voltage. The height of oxidized nanolines on the HPL sample increased after wet etching; however, the width of the lines increased only marginally. After wet etching, the height and width of oxides on the NOL were more than two times greater than those on the HPL. Increasing the applied bias voltage during nano-oxidation on NOL samples increased both the height and width of the oxides. After wet etching however, the increase in bias voltage appeared to have little effect on the height of oxidized nanolines, but the width of oxidized lines increased. This study also discovered that the use of higher applied bias voltages on NOL samples followed by wet etching results in nanostructures with a section profile closely resembling a curved surface. The use of this technique enabled researchers to create molds in the shape of a silicon nanolens array and an elegantly shaped nanoscale complex structures mold.

  7. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Beccherle, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Pisa (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste (Italy); INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2016-09-21

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  8. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Science.gov (United States)

    Calderini, G.; Bagolini, A.; Beccherle, R.; Bomben, M.; Boscardin, M.; Bosisio, L.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

    2016-09-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  9. Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    INSPIRE-00052711; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

    2016-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

  10. 硅片及其太阳电池的光衰规律研究%Study on light-induced degradation of silicon wafers and solar cells

    Institute of Scientific and Technical Information of China (English)

    曾湘安; 艾斌; 邓幼俊; 沈辉

    2014-01-01

    In this paper, the laws of light-induced degradation (LID) in silicon wafers and solar cells are investigated by using xenon lamp as light source. There are tested 15 types of the silicon wafers contain the including primary wafer, chemical thinned wafer, thermal oxidation passivation wafer, passivation SiNx : H wafer deposited by plasma enhanced chemical vapor deposition, iodine passivation wafers of three different types of silicons: B-doped CZ-Silicon, B-doped Multicrystalline (MC) silicon, and B-doped Upgraded-Metallurgical-grade (UMG) silicon. There are tested 3 types of silicon solar cells: CZ solar cell, MC solar cell, and UMG solar cell. The light intensity is 1000 W/m2 in test. By using WT-2000 tester and solar cells I-V tester, the variations of minority carrier lifetimes of silicon wafers and the I-V characteristic parameters of solar cells with time of light exposure are tested and recorded. Finally the law of LID is found. Under our light condition (light source is a xenon lamp with a light intensity of 1000 W/m2), all kinds of silicon wafers and solar cells are degraded rapidly within the first 60 min, then slowly until the 180 min, finally the rate tends to 0. The LID becomes very slight after 180 min lighting.%采用氙灯模拟太阳光源,将光强调至1000 W/m2,研究常规太阳能级单晶硅片、多晶硅片和物理提纯硅片的原片、去损减薄片、热氧化钝化片、双面镀氮化硅(SiNx : H)膜钝化片、碘酒钝化片以及太阳电池的光衰规律。利用WT-2000少子寿命测试仪以及太阳电池I-V 特性测试仪分别对硅片的少子寿命和太阳电池的I-V 特性参数随光照时间的变化进行了测试。结果表明:所有硅片以及太阳电池在光照的最初60 min内衰减很快随后衰减变慢,180 min之后光衰速率变得很小,几乎趋于零。

  11. Wafer-level integration of NiTi shape memory alloy on silicon using Au-Si eutectic bonding

    OpenAIRE

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; van der Wijngaart, Wouter

    2012-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au-Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more ...

  12. Investigation of stoichiometry of oxygen precipitates in Czochralski silicon wafers by means of EDX, EELS and FTIR spectroscopy

    Science.gov (United States)

    Kot, D.; Kissinger, G.; Schubert, M. A.; Klingsporn, M.; Huber, A.; Sattler, A.

    2016-11-01

    In this work, we used EDX, EELS and FTIR spectroscopy to investigate the stoichiometry of oxygen precipitates in Czochralski silicon wafers. The EDX analysis of a plate-like precipitate demonstrated that the composition of the precipitate is SiO1.93. This result was confirmed by EELS where the characteristic plasmon peak of SiO2 was observed. Additionally, the absorption band of plate-like precipitates at 1223 cm-1 was found in the FTIR spectrum measured at liquid helium temperature. It was demonstrated that this band can only be simulated by the dielectric constants of amorphous SiO2.

  13. Proximity gettering of C3H5 carbon cluster ion-implanted silicon wafers for CMOS image sensors: Gettering effects of transition metal, oxygen, and hydrogen impurities

    Science.gov (United States)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko

    2016-12-01

    A new technique is described for manufacturing silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication. It is demonstrated that this technique can implant wafers simultaneously with carbon and hydrogen elements that form the projection range by using hydrocarbon compounds. Furthermore, these wafers can getter oxygen impurities out-diffused from the silicon substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as dark current and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly reduce dark current in advanced CMOS image sensors.

  14. Photoelectron yield spectroscopy and inverse photoemission spectroscopy evaluations of p-type amorphous silicon carbide films prepared using liquid materials

    Energy Technology Data Exchange (ETDEWEB)

    Murakami, Tatsuya, E-mail: mtatsuya@jaist.ac.jp, E-mail: mtakashi@jaist.ac.jp [Center for Nano Materials and Technology, Japan Advanced Institute of Science and Technology (JAIST), 1-1 Asahidai, Nomi, Ishikawa 923-1292 (Japan); Masuda, Takashi, E-mail: mtatsuya@jaist.ac.jp, E-mail: mtakashi@jaist.ac.jp; Inoue, Satoshi; Shimoda, Tatsuya [Green Device Research Center, Japan Advanced Institute of Science and Technology, Nomi, Ishikawa 923-1211 (Japan); Yano, Hiroshi; Iwamuro, Noriyuki [Graduate School of Pure and Applied Sciences, University of Tsukuba, Tennoudai, Tsukuba, Ibaraki 305-8573 (Japan)

    2016-05-15

    Phosphorus-doped amorphous silicon carbide films were prepared using a polymeric precursor solution. Unlike conventional polymeric precursors, this polymer requires neither catalysts nor oxidation for its synthesis and cross-linkage, providing semiconducting properties in the films. The valence and conduction states of resultant films were determined directly through the combination of inverse photoemission spectroscopy and photoelectron yield spectroscopy. The incorporated carbon widened energy gap and optical gap comparably in the films with lower carbon concentrations. In contrast, a large deviation between the energy gap and the optical gap was observed at higher carbon contents because of exponential widening of the band tail.

  15. Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel

    Science.gov (United States)

    Yu, Eunseon; Cho, Seongjae

    2016-11-01

    In this work, a nanowire p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) coaxially having a Si core and a Ge peripheral channel is designed and characterized by device simulations. Owing to the high hole mobility of Ge, the device can be utilized for high-speed CMOS integrated circuits, with the effective confinement of mobile holes in Ge by the large valence band offset between Si and Ge. Source/drain doping concentrations and the ratio between the Si core and Ge channel thicknesses are determined. On the basis of the design results, the channel length is aggressively scaled down by evaluating the primary DC parameters in order to confirm device scalability and low-power applicability in sub-10-nm technology nodes.

  16. Electrical properties and surface morphology of electron beam evaporated p-type silicon thin films on polyethylene terephthalate for solar cells applications

    Energy Technology Data Exchange (ETDEWEB)

    Ang, P. C.; Ibrahim, K.; Pakhuruddin, M. Z. [Nano-Optoelectronics Research and Technology Laboratory, School of Physics, Universiti Sains Malaysia, Minden 11800 Penang (Malaysia)

    2015-04-24

    One way to realize low-cost thin film silicon (Si) solar cells fabrication is by depositing the films with high-deposition rate and manufacturing-compatible electron beam (e-beam) evaporation onto inexpensive foreign substrates such as glass or plastic. Most of the ongoing research is reported on e-beam evaporation of Si films on glass substrates to make polycrystalline solar cells but works combining both e-beam evaporation and plastic substrates are still scarce in the literature. This paper studies electrical properties and surface morphology of 1 µm electron beam evaporated Al-doped p-type silicon thin films on textured polyethylene terephthalate (PET) substrate for application as an absorber layer in solar cells. In this work, Si thin films with different doping concentrations (including an undoped reference) are prepared by e-beam evaporation. Energy dispersion X-ray (EDX) showed that the Si films are uniformly doped by Al dopant atoms. With increased Al/Si ratio, doping concentration increased while both resistivity and carrier mobility of the films showed opposite relationships. Root mean square (RMS) surface roughness increased. Overall, the Al-doped Si film with Al/Si ratio of 2% (doping concentration = 1.57×10{sup 16} atoms/cm{sup 3}) has been found to provide the optimum properties of a p-type absorber layer for fabrication of thin film Si solar cells on PET substrate.

  17. Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays

    Science.gov (United States)

    Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

    2014-10-01

    Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly

  18. Recombination activity of light-activated copper defects in p-type silicon studied by injection- and temperature-dependent lifetime spectroscopy

    Science.gov (United States)

    Inglese, Alessandro; Lindroos, Jeanette; Vahlman, Henri; Savin, Hele

    2016-09-01

    The presence of copper contamination is known to cause strong light-induced degradation (Cu-LID) in silicon. In this paper, we parametrize the recombination activity of light-activated copper defects in terms of Shockley—Read—Hall recombination statistics through injection- and temperature dependent lifetime spectroscopy (TDLS) performed on deliberately contaminated float zone silicon wafers. We obtain an accurate fit of the experimental data via two non-interacting energy levels, i.e., a deep recombination center featuring an energy level at Ec-Et=0.48 -0.62 eV with a moderate donor-like capture asymmetry ( k =1.7 -2.6 ) and an additional shallow energy state located at Ec-Et=0.1 -0.2 eV , which mostly affects the carrier lifetime only at high-injection conditions. Besides confirming these defect parameters, TDLS measurements also indicate a power-law temperature dependence of the capture cross sections associated with the deep energy state. Eventually, we compare these results with the available literature data, and we find that the formation of copper precipitates is the probable root cause behind Cu-LID.

  19. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    Calderini, G; Bomben, M; Boscardin, M; Bosisio, L; Chauveau, J; Giacomini, G; La Rosa, A; Marchiori, G; Zorzi, N

    2014-01-01

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R&D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  20. Characterization of stain etched p-type silicon in aqueous HF solutions containing HNO{sub 3} or KMnO{sub 4}

    Energy Technology Data Exchange (ETDEWEB)

    Mogoda, A.S., E-mail: awad_mogoda@hotmail.com [Department of Chemistry, Faculty of Science, Cairo University, Giza (Egypt); Ahmad, Y.H.; Badawy, W.A. [Department of Chemistry, Faculty of Science, Cairo University, Giza (Egypt)

    2011-04-15

    Research highlights: {yields} Stain etching of p-Si in aqueous HF solutions containing HNO{sub 3} or KMnO{sub 4} was investigated. {yields} The electrical conductivity of the etched Si surfaces was measured using impedance technique. {yields} Scanning electron microscope and energy disperse X-ray were used to analyze the etched surfaces. {yields} Etching in aqueous HF solution containing HNO{sub 3} led to formation of a porous silicon layer. {yields} The formation of the porous silicon layer in HF/KMnO{sub 4} was accompanied by deposition of K{sub 2}SiF{sub 6} on the pores surfaces. - Abstract: Stain etching of p-type silicon in hydrofluoric acid solutions containing nitric acid or potassium permanganate as an oxidizing agent has been examined. The effects of etching time, oxidizing agent and HF concentrations on the electrochemical behavior of etched silicon surfaces have been investigated by electrochemical impedance spectroscopy (EIS). An electrical equivalent circuit was used for fitting the impedance data. The morphology and the chemical composition of the etched Si surface were studied using scanning electron microscopy (SEM) and energy dispersive X-ray (EDX) techniques, respectively. A porous silicon layer was formed on Si etched in HF solutions containing HNO{sub 3}, while etching in HF solutions containing KMnO{sub 4} led to the formation of a porous layer and simultaneous deposition of K{sub 2}SiF{sub 6} inside the pores. The thickness of K{sub 2}SiF{sub 6} layer increases with increasing the KMnO{sub 4} concentration and decreases as the concentration of HF increases.

  1. Exploration of surface hydrophilic properties on AISI 304 stainless steel and silicon wafer against aging after atmospheric pressure plasma treatment

    Science.gov (United States)

    Chuang, Shang-I.; Duh, Jenq-Gong

    2014-11-01

    The aim of this work is to seek the enhanced surface hydrophilic properties on AISI 304 stainless steel and silicon wafer after atmospheric pressure plasma treatment using a specifically designed atmospheric pressure plasma jet. The aging tendency of surface hydrophilic property under air is highlighted. It is concluded that both of the silicon wafer and stainless steel treated with plasma generated from supply gas of argon 15 slm mixed with oxygen 40 sccm shows a better tendency on remaining high water contact angle as compared to that with pure argon and nitrogen addition. Additional peaks of O I (777, 844 nm), O II (408 nm) are detected by optical emission spectroscope indicating the presence of the oxygen radicals and ionic species, which interact with surfaces and thus contribute to low water contact angle (WCA) surfaces. Moreover, the result acquired from X-ray photoelectron spectroscopy (XPS) indicates that the increase in the oxygen-related bonding exhibits a better contribution on remaining high surface energy over a period of time.

  2. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    Energy Technology Data Exchange (ETDEWEB)

    Takahara, Hikari, E-mail: hikari@rigaku.co.jp [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Mori, Yoshihiro [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Shibata, Harumi [SUMCO Corporation, Seavance North, 1-2-1 Shibaura, Minato-ku, Tokyo 105-8634 (Japan); Shimazaki, Ayako [Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522 (Japan); Shabani, Mohammad B. [Mitsubishi Material Corporation, 1-297, Kitabukuro-cho, Omiya-ku, Saitama 330-8508 (Japan); Yamagami, Motoyuki [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Yabumoto, Norikuni [Analysis Atelier Co., 4-36-4, Yoyogi, Shibuya-ku, Tokyo 151-0053 (Japan); Nishihagi, Kazuo [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Gohshi, Yohichi [Tsukuba University, 1-1-1, Tennodai, Tsukuba, Ibaraki 305-8571 (Japan)

    2013-12-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10{sup 9} and 5 × 10{sup 10} atoms/cm{sup 2} Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO{sub 2}, silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10{sup 10} atoms/cm{sup 2}. • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies.

  3. The electrical properties of photodiodes based on nanostructure gallium doped cadmium oxide/p-type silicon junctions

    Science.gov (United States)

    Çavaş, M.; Yakuphanoğlu, F.; Karataş, Ş.

    2017-01-01

    Gallium doped cadmium-oxide (CdO: Ga) thin films were successfully deposited by sol-gel spin coating method on p-type Si substrate. The electrical properties of the photodiode based on nanostructure Ga doped n-CdO/p-Si junctions were investigated. The current-voltage (I-V) characteristics of the structure were investigated under various light intensity and dark. It was observed that generated photocurrent of the Au/n-CdO/p-Si junctions depended on light intensity. The capacitance-voltage and conductance-voltage measurements were carried out for this diode in the frequency range between 100 and 1000 kHz at room temperature by steps of 100 kHz. The capacitance decreased with increasing frequency due to a continuous distribution of the interface states. These results suggested that the Au/n-CdO/p-Si Schottky junctions could be utilized as a photosensor. Furthermore, the voltage and frequency dependence of series resistance were calculated from the C-V and G/ω-V measurements and plotted as functions of voltage and frequency. The distribution profile of R S -V gave a peak in the depletion region at low frequencies and disappeared with increasing frequencies.

  4. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    Science.gov (United States)

    Khan, M. F.; Ghavanini, F. A.; Haasl, S.; Löfgren, L.; Persson, K.; Rusu, C.; Schjølberg-Henriksen, K.; Enoksson, P.

    2010-06-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  5. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Energy Technology Data Exchange (ETDEWEB)

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  6. Chemiluminescence system for direct determination and mapping of ultra-trace metal impurities on a silicon wafer.

    Science.gov (United States)

    Kim, Romertta; Sung, Y I; Lee, J S; Lim, H B

    2010-11-01

    A highly sensitive chemiluminescence (CL) system which consumed low sample and reagent volumes in the microlitre range was developed for direct determination and mapping of ultra-trace metal contaminants on solid surfaces, such as silicon wafers or flat display panels. The analytical result of the system was confirmed with ICP-MS. The system was composed of a scanner, sensor and a wafer moving stage. The scanner, with a scanning tip made of 0.03'' i.d. PTFE tubing, was used to collect metal impurities on the wafer surface with 5 μL of scanning solution. A coaxial sensing head of about 13 mm o.d. and 110 mm height was designed both to inject a luminescent reagent of luminol-H(2)O(2) mixture and to collect the luminescence light resulting from the reaction with metal ions of Co(2+), Fe(2+), Cu(2+), and Ni(2+). Due to the almost zero background, an extremely low limit of detection of 20.8 pg/mL for Co(2+) in 1% hydrofluoric acid (HF) was obtained from the calibration curve. In order to map the spatial distribution of the impurities, 11 cross sections of a Co-contaminated wafer were selected and scanned individually with a diluted HF solution. A contaminant level of 1.45-7.11 × 10(11) atoms cm(-2) was obtained for each section with an average of 4.21 × 10(11) atoms cm(-2), which was similar to the analytical result of 5.48 × 10(11) atoms cm(-2) obtained from vapor phase deposition-inductively coupled plasma-mass spectrometry (VPD-ICP-MS). Although this CL system does not have selectivity for each specific metal ion, its high sensitivity facilitates the monitoring and mapping of metal impurities of Co, Fe, Cu, etc. on the wafer directly and it can be used as an on-line inspection sensor for the first time in the semiconductor industry.

  7. Sub-band transport mechanism and switching properties for resistive switching nonvolatile memories with structure of silver/aluminum oxide/p-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Yanhong; Li, La; Wang, Song; Gao, Ping; Pan, Lujun; Zhang, Jialiang [School of Physics and Optoelectronic Engineering, Dalian University of Technology, No. 2 Linggong Road, Ganjingzi District, Dalian 116024 (China); Zhou, Peng [Department of Microelectronics, State Key Laboratory of ASIC and System, Fudan University, Shanghai 200433 (China); Li, Jinhua; Weng, Zhankun [Center for Nano Metrology and Manufacturing Technologies and International Joint Research Center for Nanophotonics and Biophotonics, Changchun University of Science and Technology, Changchun 130022 (China)

    2015-02-09

    In this paper, we discuss a model of sub-band in resistive switching nonvolatile memories with a structure of silver/aluminum oxide/p-type silicon (Ag/Al{sub x}O{sub y}/p-Si), in which the sub-band is formed by overlapping of wave functions of electron-occupied oxygen vacancies in Al{sub x}O{sub y} layer deposited by atomic layer deposition technology. The switching processes exhibit the characteristics of the bipolarity, discreteness, and no need of forming process, all of which are discussed deeply based on the model of sub-band. The relationships between the SET voltages and distribution of trap levels are analyzed qualitatively. The semiconductor-like behaviors of ON-state resistance affirm the sub-band transport mechanism instead of the metal filament mechanism.

  8. A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

    Directory of Open Access Journals (Sweden)

    P. S. Pa

    2013-01-01

    Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

  9. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  10. Simulation of photoacoustic imaging of microcracks in silicon wafers using a structure-changeable multilayered thermal diffusion model.

    Science.gov (United States)

    Nakata, Toshihiko; Kitamori, Takehiko; Sawada, Tsuguo

    2007-03-01

    The detection characteristics for photoacoustic imaging of microcracks in silicon wafers were theoretically and quantitatively investigated using a numerical simulation. The simulation is based on a one-dimensional multilayered thermal diffusion model coupled with the thermal-wave impedance of each layer, the layer structures of which are constructed along the wafer surface and are variable according to the scanning position of the point heat source. As the modulation frequency was reduced, the spatial resolution of the temperature amplitude profile at the cracks decreased, showing good agreement with the experimentally obtained photoacoustic amplitude images. At a modulation frequency of 200 kHz, for cracks with narrow air gaps of up to 20 nm, which is much smaller than both the beam spot size of 1.5 microm and the thermal diffusion length of 12 microm, the temperature amplitude is twice that of regions without cracks, and the temperature contrast increased with an increase in the modulation frequency. These calculation results suggest the effectiveness of using a high modulation frequency, making it possible to detect microcracks of the order of 10 nm.

  11. Charging effects on the carrier mobility in silicon-on-insulator wafers covered with a high-k layer

    Science.gov (United States)

    Halley, D.; Norga, G.; Guiller, A.; Fompeyrine, J.; Locquet, J. P.; Drechsler, U.; Siegwart, H.; Rossel, C.

    2003-11-01

    The carrier mobility μ in low-doped silicon-on-insulator wafers is found to be strongly modified by the deposition of a thin ZrO2 or SrZrO3 top layer grown by molecular-beam epitaxy. Pseudo-metal-oxide-semiconductor field-effect-transistor measurements performed on several samples clearly show a correlation between μ and the density of interface traps (Dit) at the Si/buried-oxide interface. The reduction of Dit by a forming gas anneal leads to a corresponding increase in mobility. Moreover, the high-k/Si interface can contribute to the total drain current via the creation of an inversion channel induced by trapped charges in the high-k layer. Using Hall-effect measurements, we took advantage of this additional current to evaluate the carrier mobility at the high-k/Si interface, without the need of a top gate electrode.

  12. Anodic Bonding of Transparent Conductive Oxide Coated Silicon Wafer to Glass Substrate for Solar Cell Applications

    Science.gov (United States)

    Yuda, Yohei; Koida, Takashi; Kaneko, Tetsuya; Kondo, Michio

    2013-01-01

    We report on the anodic bonding of Si wafer coated by thin transparent conductive oxide (TCO) with a glass substrate, for the first time. We obtained sufficient bonding strength of as high as 9.5 MPa using a 30-nm-thick indium tin oxide (ITO) layer. We have also found that the ITO sample shows much stronger bonding strength does a sample that with a zinc oxide layer. The bonding mechanism is discussed in terms of the permeation of indium elements into the glass side driven by electric field. Finally we demonstrated a solar cell using this substrate.

  13. Design and fabrication of high performance wafer-level vacuum packaging based on glass-silicon-glass bonding techniques

    Science.gov (United States)

    Zhang, Jinwen; Jiang, Wei; Wang, Xin; Zhou, Jilong; Yang, Huabing

    2012-12-01

    In this paper, a high performance wafer-level vacuum packaging technology based on GSG triple-layer sealing structure for encapsulating large mass inertial MEMS devices fabricated by silicon-on-glass bulk micromachining technology is presented. Roughness controlling strategy of bonding surfaces was proposed and described in detail. Silicon substrate was thinned and polished by CMP after the first bonding with the glass substrate and was then bonded with the glass micro-cap. Zr thin film was embedded into the concave of the micro-cap by a shadow-mask technique. The glass substrate was thinned to about 100 µm, wet etched through and metalized for realizing vertical feedthrough. During the fabrication, all patterning processes were operated carefully so as to reduce extrusive fragments to as little as possible. In addition, a high-performance micro-Pirani vacuum gauge was integrated into the package for monitoring the pressure and the leak rate further. The result shows that the pressure in the package is about 120 Pa and has no obvious change for more than one year indicating 10-13 stdcc s-1 leak rate.

  14. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  15. High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Zihao; Preble, Stefan F. [Microsystems Engineering, Rochester Institute of Technology, Rochester, New York 14623 (United States); Yao, Ruizhe; Lee, Chi-Sen; Guo, Wei, E-mail: wei-guo@uml.edu [Physics and Applied Physics Department, University of Massachusetts Lowell, Lowell, Massachusetts 01854 (United States); Lester, Luke F. [Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Virginia 24061 (United States)

    2015-12-28

    InAs quantum dot (QD) laser heterostructures have been grown by molecular beam epitaxy system on GaAs substrates, and then transferred to silicon substrates by a low temperature (250 °C) Pd-mediated wafer bonding process. A low interfacial resistivity of only 0.2 Ω cm{sup 2} formed during the bonding process is characterized by the current-voltage measurements. The InAs QD lasers on Si exhibit comparable characteristics to state-of-the-art QD lasers on silicon substrates, where the threshold current density J{sub th} and differential quantum efficiency η{sub d} of 240 A/cm{sup 2} and 23.9%, respectively, at room temperature are obtained with laser bars of cavity length and waveguide ridge of 1.5 mm and 5 μm, respectively. The InAs QD lasers also show operation up to 100 °C with a threshold current density J{sub th} and differential quantum efficiency η{sub d} of 950 A/cm{sup 2} and 9.3%, respectively. The temperature coefficient T{sub 0} of 69 K from 60 to 100 °C is characterized from the temperature dependent J{sub th} measurements.

  16. The performance of Y2O3 as interface layer between La2O3 and p-type silicon substrate

    Directory of Open Access Journals (Sweden)

    Shulong Wang

    2016-11-01

    Full Text Available In this study, the performance of Y2O3 as interface layer between La2O3 and p-type silicon substrate is studied with the help of atomic layer deposition (ALD and magnetron sputtering technology. The surface morphology of the bilayer films with different structures are observed after rapid thermal annealing (RTA by atomic force microscopy (AFM. The results show that Y2O3/Al2O3/Si structure has a larger number of small spikes on the surface and its surface roughness is worse than Al2O3/Y2O3/Si structure. The reason is that the density of Si substrate surface is much higher than that of ALD growth Al2O3. With the help of high-frequency capacitance-voltage(C-V measurement and conductivity method, the density of interface traps can be calculated. After a high temperature annealing, the metal silicate will generate at the substrate interface and result in silicon dangling bond and interface trap charge, which has been improved by X-ray photoelectron spectroscopy (XPS and interface trap charge density calculation. The interface trapped charge density of La2O3/Al2O3/Si stacked gate structure is lower than that of La2O3/Y2O3/Si gate structure. If Y2O3 is used to replace Al2O3 as the interfacial layer, the accumulation capacitance will increase obviously, which means lower equivalent oxide thickness (EOT. Our results show that interface layer Y2O3 grown by magnetron sputtering can effectively ensure the interface traps near the substrate at relative small level while maintain a relative higher dielectric constant than Al2O3.

  17. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  18. TEM Observation of the Dislocations Nucleated from Cracks inside Lightly or Heavily Doped Czochralski Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Seiji Shiba

    2011-01-01

    Full Text Available The crack propagation from the indent introduced with a Vickers hardness tester at room temperature and the dislocation nucleation from the cracks at 900°C inside lightly boron (B, heavily B, or heavily arsenic (As doped Czochralski (CZ Si wafers were investigated with transmission electron microscopy (TEM observations. It was found that the dopant concentration and the dopant type did not significantly affect the crack propagation and the dislocation nucleation. The slip dislocations with a density of about (0.8∼2.8 × 1013/cm3 were nucleated from the cracks propagated about 10 μm in depth. Furthermore, small dislocations that nucleated with very high density and without cracks were found around the indent introduced at 1000°C.

  19. Three-dimensional numerical analysis of hybrid heterojunction silicon wafer solar cells with heterojunction rear point contacts

    Directory of Open Access Journals (Sweden)

    Zhi Peng Ling

    2015-07-01

    Full Text Available This paper presents a three-dimensional numerical analysis of homojunction/heterojunction hybrid silicon wafer solar cells, featuring front-side full-area diffused homojunction contacts and rear-side heterojunction point contacts. Their device performance is compared with conventional full-area heterojunction solar cells as well as conventional diffused solar cells featuring locally diffused rear point contacts, for both front-emitter and rear-emitter configurations. A consistent set of simulation input parameters is obtained by calibrating the simulation program with intensity dependent lifetime measurements of the passivated regions and the contact regions of the various types of solar cells. We show that the best efficiency is obtained when a-Si:H is used for rear-side heterojunction point-contact formation. An optimization of the rear contact area fraction is required to balance between the gains in current and voltage and the loss in fill factor with shrinking rear contact area fraction. However, the corresponding optimal range for the rear-contact area fraction is found to be quite large (e.g. 20-60 % for hybrid front-emitter cells. Hybrid rear-emitter cells show a faster drop in the fill factor with decreasing rear contact area fraction compared to front-emitter cells, stemming from a higher series resistance contribution of the rear-side a-Si:H(p+ emitter compared to the rear-side a-Si:H(n+ back surface field layer. Overall, we show that hybrid silicon solar cells in a front-emitter configuration can outperform conventional heterojunction silicon solar cells as well as diffused solar cells with rear-side locally diffused point contacts.

  20. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  1. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  2. Fabrication and characterization of silicon nanowire p-i-n MOS gated diode for use as p-type tunnel FET

    Science.gov (United States)

    Brouzet, V.; Salem, B.; Periwal, P.; Rosaz, G.; Baron, T.; Bassani, F.; Gentile, P.; Ghibaudo, G.

    2015-11-01

    In this paper, we present the fabrication and electrical characterization of a MOS gated diode based on axially doped silicon nanowire (NW) p-i-n junctions. These nanowires are grown by chemical vapour deposition (CVD) using the vapour-liquid-solid (VLS) mechanism. NWs have a length of about 7 \\upmu {m} with 3 \\upmu {m} of doped regions (p-type and n-type) and 1 \\upmu {m} of intrinsic region. The gate stack is composed of 15 nm of hafnium dioxide ({HfO}2), 80 nm of nickel and 120 nm of aluminium. At room temperature, I_{{on}} =-52 {nA}/\\upmu {m} (V_{{DS}}=-0.5 {V}, V_{{GS}}=-4 {V}), and an I_{{on}}/I_{{off}} ratio of about 104 with a very low I_{{off}} current has been obtained. Electrical measurements are carried out between 90 and 390 K, and we show that the I on current is less temperature dependent below 250 K. We also observe that the ON current is increasing between 250 and 390 K. These transfer characteristics at low and high temperature confirm the tunnelling transport mechanisms in our devices.

  3. Impact of strain on gate-induced floating body effect for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor-field-effect-transistors

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Wen-Hung [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Dai, Chih-Hao [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chung, Wan-Lin [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chen, Ching-En; Ho, Szu-Han [Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC (China); Tsai, Jyun-Yu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Chen, Hua-Mao [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan, ROC (China); Liu, Guan-Ru [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC (China); Cheng, Osbert; Huang, Cheng-Tung [Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan, ROC (China)

    2013-01-01

    This work investigates impact of mechanical strain on gate-induced-floating-body-effect (GIFBE) for partially depleted silicon-on-insulator p-type metal–oxide–semiconductor field effect transistors (PD SOI p-MOSFETs). First part, the original mechanism of GIFBE on PD SOI p-MOSFETs is studied. The experimental results indicate that GIFBE causes a reduction in oxide electric field (E{sub ox}), resulting in an underestimate of negative-bias temperature instability (NBTI) degradation. This can be attributed to the electrons tunneling from the process-induced partial n{sup +} poly gate and anode electron injection (AEI) model, rather than the electron valence band tunneling (EVB) widely accepted as the mechanism for n-MOSFETs. And then, the second part shows that the strained FB device has less NBTI degradation than the unstrained devices. This behavior can be attributed to the fact that more electron accumulation was induced by strain-induced band gap narrowing, reducing NBTI significantly. - Highlights: ► This work investigates the impact of mechanical strain on GIFBE for PD SOI p-MOSFETs. ► FB device shows an insignificant NBTI due to GIFBE. ► GIFBE results from the partial n{sup +} poly gate and anode electron injection model. ► The strained FB device has less NBTI degradation than unstrained devices. ► We verify the band gap narrowing causes less NBTI on strained FB device.

  4. A novel technique based on a plasma focus device for nano-porous gallium nitride formation on P-type silicon

    Science.gov (United States)

    Sharifi Malvajerdi, S.; Salar Elahi, A.; Habibi, M.

    2017-04-01

    A new deposition formation was observed with a Mather-type Plasma Focus Device (MPFD). MPFD was unitized to fabricate porous Gallium Nitride (GaN) on p-type Silicon (Si) substrate with a (100) crystal orientation for the first time in a deposition process. GaN was deposited on Si with 4 and 7 shots. The samples were subjected to a 3 phase annealing procedure. First, the semiconductors were annealed in the PFD with nitrogen plasma shots after their deposition. Second, a thermal chemical vapor deposition annealed the samples for 1 h at 1050 °C by nitrogen gas at a pressure of 1 Pa. Finally, an electric furnace annealed the samples for 1 h at 1150 °C with continuous flow of nitrogen. Porous GaN structures were observed by Field emission scanning electron microscopy and atomic force microscopy. Furthermore, X-Ray diffraction analysis was carried out to determine the crystallinity of GaN after the samples were annealed. Energy-Dispersive X-Ray Spectroscopy indicated the amount of gallium, nitrogen, and oxygen due to the self-oxidation of the samples. Photoluminescence spectroscopy revealed emissions at 2.94 eV and 3.39 eV, which shows that hexagonal wurtzite crystal structures were formed.

  5. Model of Grain Depth of Cut in Wafer Rotation Grinding Method for Silicon Wafers%工件旋转法磨削硅片的磨粒切削深度模型

    Institute of Scientific and Technical Information of China (English)

    高尚; 王紫光; 康仁科; 董志刚; 张璧

    2016-01-01

    During the integrated circuit manufacturing process, ultra-precision grinding based on the principle of wafer rotation grinding is currently utilized as a major method in flattening and back-thinning of large-size silicon wafers. Grain depth of cut is a function to characterize the overall grinding conditions and has direct effect on the surface/subsurface quality of ground workpieces. Modelling of grain depth of cut of workpiece rotation grinding has great significance in grinding of silicon wafers with high efficiency and high surface layer quality. Based on the analysis of relative motion between cup-type grinding wheel, abrasives and silicon water in wafer rotation grinding, the model of grain depth of cut is proposed and the mathematical relationship among grain depth of cut, dimensions of cup-type grinding wheel, grinding parameters and radical distance is presented. With the proposed model, the subsurface damage distributions along the radical direction of ground silicon wafers and the effects of machining conditions on subsurface damage in wafer rotation grinding are then analyzed, and the grinding experiments are conducted to verify the model. The experiment results show that the subsurface damage depth decreases gradually along radical direction from edge to centre of the ground wafer surface. The subsurface damage depth increases with the increase in wheel grain size, wafer rotation speed, wheel feedrate and the decrease in wheel rotation speed. The experiment results agree well with the model predictions.%半导体器件制造中,工件旋转法磨削是大尺寸硅片正面平坦化加工和背面薄化加工最广泛应用的加工方法。磨粒切削深度是反映磨削条件综合作用的磨削参量,其大小直接影响磨削工件的表面/亚表面质量,研究工件旋转法磨削的磨粒切削深度模型对于实现硅片高效率高质量磨削加工具有重要的指导意义。通过分析工件旋转法磨削过程中砂轮、

  6. Laser cleaning of the metallic thin films from silicon wafer surface with UV laser radiation

    Science.gov (United States)

    Apostol, Ileana; Apostol, Dan; Victor, Damian; Timcu, Adrian; Iordache, Iuliana; Castex, Marie-Claude C.; Galli, Roberta; Ulieru, Dumitru G.

    2004-10-01

    The interest to use laser surface processing in microtechnology as a friendly method from the technologic and environmental point of view lead our studies about laser radiation interaction with photo-resist and metallic thin films. In this view we have tried in our experiments to process metallic thin films deposited on silicon substrate by using laser radiation. To obtain a good quality of the metallic thin film removal from the silicon surface a careful selection of the incident laser intensity, number of pulses and irradiation geometry is needed. The threshold value for the laser cleaning intensity depends on the number of incident laser pulses. A careful experimental estimation of the cleaning conditions from the point of view of incident laser energy, fluence, intensity and irradiation geometry was realized for aluminum, copper, and chromium thin films.

  7. Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

    Directory of Open Access Journals (Sweden)

    Granata M.

    2015-04-01

    Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

  8. Neutron activation analysis of low-level element contents in silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Goerner, W. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D. [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  9. Multi scale modeling and simulation for oxygen precipitate behavior in silicon wafer.

    Science.gov (United States)

    Lee, Sang Hun; Kang, Jeong Won; Kim, Do Hyun

    2011-07-01

    Oxygen precipitates in semiconductor device are generally considered beneficial for its metallic contaminants gettering function, but the oxygen precipitates also affect to degrade the efficiency of solar cell. The formation of oxygen precipitates is closely related to the grown-in defects like oxygen in crystal growth process and heat treatment cycle in device process. Oxygen comes into the silicon melt by dissolving quartz (SiO2) crucible and incorporates into the silicon crystal in Czochralski process. The oxygen plays key role in the formation of oxygen precipitate nuclei in crystal growth process and then the nuclei grow up to be oxygen precipitates in device process. Therefore, the formation of oxygen precipitates is closely related to the crystal growing process and device manufacturing process. In this research, we interpreted the formation and behavior of oxygen precipitates depending on varying oxygen concentrations by using Multi_Scale method. The method is very useful to obtain more reliable interpretation result than other single methods. The validity of this research is verified by comparing with experimental data.

  10. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    Science.gov (United States)

    Yoon, Sang Won; Lee, Sangwoo; Perkins, Noel C.; Najafi, Khalil

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped-clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm2 footprint. The contact resistance ranges from 4-11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  11. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Directory of Open Access Journals (Sweden)

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  12. Processing silicon microparticles recycled from wafer waste via Rapid Thermal Process for lithium-ion battery anode materials

    Science.gov (United States)

    Tan, Hui-Gee; Duh, Jenq-Gong

    2016-12-01

    A vast quantity of waste sludge is generated during the silicon wafers slicing process in semiconductor and photovoltaic industries. Turning the waste powder into high-value products is of strategic importance for industrial processes. The purified Si microparticles (Si-MP) are recycled by a simple and fast procedure, Rapid Thermal Process (RTP). A prominent anodic material of Si-MP/Carbon composite with porous structure is obtained via in-spaced carbonization of water-soluble binder sodium carboxymethyl cellulose during RTP. This strategy provides buffer space, which is constructed by carbon porous continuous conductive framework throughout the entire electrode, to resist local stress and intense volume variation. In addition, a sufficiently electrochemically stable solid-electrolyte interphase layer is accomplished with the coating of SiOx film and amorphous carbon on the surface of Si-MP. Under these circumstances, the enhanced electrodes achieve a first cycle efficiency of approximately 80% and a reversible charge capacity of 800 mAhg-1 over 100 cycles at 0.5 Ag-1 with good retention. Through a green and simple procedure, a remarkable Si-MP embedded carbon-matrix with porous structure is established to achieve commercially high performance Si-MP/C composite anodes and also to resolve the issues of waste disposal.

  13. Resistless photochemical etching of a silicon wafer by UV laser with an H2O2 and HF aqueous solution

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    A new resistless etching method has been developed for Silicon wafers. This new method uses an aqueous solution consisting of hydrogen peroxide (H2O2) and hydrogen fluoride (HF) as the activating etchants. A 193 nm ArF excimer laser and a 266 nm fourth harmonic generation Nd:YAG laser were used as the photon sources. Results showed that pattern etching has been achieved without any photoresist film. In the case of the 193 nm laser, the optimal etching appeared at a 1.3 H2O2/HF ratio, where an etch depth of 210 nm was achieved with a fluence of 29 mJ/cm2 and shot number of 10000. At the same conditions, the etch depth with H2O2 and HF solution was three times of that by using H2O and HF mixture. In the case of the 266 nm Nd:YAG laser, the optimal etching appeared at twice ratio of H2O2/HF, where the etch depth of 420 nm was achieved with a fluence of 12 mJ/cm2 and shot number of 30000. Results showed that the etch effect of the 266 nm Nd: YAG laser was more desirable than that of the 193 nm ArF excimer laser.``Keyords: UV laser, resistless photochemical etching, hydrogen peroxide (H2O2).

  14. MICROBRIDGE TESTING OF YOUNG'S MODULUS AND RESIDUAL STRESS OF NICKEL FILM ELECTROPLATED ON SILICON WAFER

    Institute of Scientific and Technical Information of China (English)

    Y. Zhou; C.S Yang; J.A. Chen; G.F. Ding; L. Wang; M.J. Wang; Y.M. Zhang; T.H. Zhang

    2004-01-01

    Microbridge testing is used to measure the Young's modulus and residual stresses of metallic films. Nickel film microbridges with widths of several hundred microns are fabricated by Microelectromechanical Systems. In order to measure the mechanical properties of nickel film microbridges, special shaft structure is designed to solve the problem of getting the load-deflection curves of metal film microbridge by Nanoindenter XP system with normal Berkovich probe. Theoretical analysis of the microbridge load-deflection curve is proposed to evaluate the Young's modulus and residual stress of the films simultaneously. The calculated results based on the experimental measurements show that the average Young's modulus and residual stress are around 190GPa and 175MPa respectively, while the Young's modulus measured by Nanohardness method on nickel film with silicon substrate is 186.8±7.34GPa.

  15. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    KAUST Repository

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  16. Effect of Jig Shape on Surface Quality of Silicon Polished Wafers%夹具形状对硅抛光片表面质量的影响

    Institute of Scientific and Technical Information of China (English)

    杨洪星; 陈亚楠

    2013-01-01

      在硅抛光片的清洗技术中,湿法清洗技术仍然是主流清洗技术。随着抛光片尺寸增大,传统的手工清洗方式和半自动清洗方式已经不适于大尺寸硅抛光片的清洗,因此全自动湿法清洗设备逐步在大尺寸硅抛光片清洗设备中占据主导地位。在湿法清洗工艺中,夹具形状对清洗槽中液体的流动有着较大的影响,若夹具形状设计不合理,将影响抛光片表面沾污的去除,在抛光片表面形成“色斑”缺陷。%In the silicon wafer cleaning technology, wet cleaning technology is still the mainstream cleaning technology. With the polishing sheet size increases, the traditional manual cleaning methods and semi automatic cleaning method is not suitable for large size silicon wafer cleaning, thus automatic wet cleaning equipment occupies the main position gradually in large size silicon wafer cleaning. In the wet cleaning process, jig shape has a greater impact on the flow of the liquid in the cleaning tank, if the jig shape design is unreasonable, the stain defect would be observed on the polished wafers.

  17. On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

    Science.gov (United States)

    Samoska, Lorene; Man Fung, King; Gaier, Todd; Huang, Daquan; Larocca, Tim; Chang, M. F.; Campbell, Richard; Andrews, Michael

    2008-01-01

    The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

  18. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    Science.gov (United States)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  19. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  20. LiTaO3/Silicon Composite Wafers for the Fabrication of Low Loss Low TCF High Coupling Resonators for Filter Applications

    Science.gov (United States)

    Ballandras, S.; Courjon, E.; Baron, T.; Moulet, J.-B.; Signamarcheix, T.; Daniau, W.

    SAW devices are widely used for radio-frequency (RF) telecommunication filtering and the number of SAW filters, resonators or duplexers is still increasing in RF stage of cellular phones. Therefore, a strong effort is still dedicated to reduce as much as possible their sensitivity to environmental parameter and more specifically to temperature. Bounding processes have been developed at FEMTO-ST and CEA-LETI using either Au/Au or direct bonding techniques for the fabrication of composite wafers combining materials with very different thermoelastic properties, yielding innovative solutions for about-zero temperature coefficient of frequency (TCF) bulk acoustic wave devices. In the present work, this approach has been applied to (YXl)/42∘ lithium tantalate plates, bounded onto (100) silicon wafers and thinned down to 25 μm. The leading idea already explored by other groups as mentioned in introduction consists in impeding the thermal expansion of the piezoelectric material using silicon limited expansion. 2 GHz resonators have been built on such plates and tested electrically and thermally, first by tip probing. A dramatic reduction of the TCF is observed for all the tested devices, allowing to reduce the thermal drift of the resonators down to a few ppm.K-1 within the standard temperature range. We then propose an analysis of the frequency-temperature behavior of the device to improve the resonator design to use these wafers for industrial applications.

  1. Mechanism of β-FeSi{sub 2} precipitates growth-and-dissolution and pyramidal defects' formation during oxidation of Fe-contaminated silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    De Luca, Anthony; Texier, Michaël, E-mail: michael.texier@univ-amu.fr; Portavoce, Alain; Burle, Nelly [Aix Marseille Université, CNRS, IM2NP UMR 7334, bd Escadrille Normandie Niémen, F-13397 Marseille (France); Grosjean, Catherine [ST MicroElectronics, 190 av. Célestin Coq, Z.I. Peynier Rousset, F-13106 Rousset (France); Morata, Stéphane [Ion Beam Services, rue G. Imbert prolongée, Z.I. Peynier Rousset, F-13790 Rousset (France); Michel, Fabrice [Vegatec, 150 av. Célestin Coq, Z.I. Peynier Rousset, F-13106 Rousset (France)

    2015-03-21

    Fe-implanted Si-wafers have been oxidized at 900 °C and 1100 °C in order to investigate the behaviour of Fe atoms at the growing SiO{sub 2}/Si interface and the impact on the integrity of microelectronic devices of an involuntary Fe contamination before or during the oxidation process. As-implanted and oxidized wafers have been characterized using secondary ion mass spectroscopy, atom probe tomography, and high-resolution transmission electron microscopy. Experimental results were compared to calculated implantation profiles and simulated images. Successive steps of iron disilicide precipitation and oxidation were evidenced during the silicon oxidation process. The formation of characteristic pyramidal-shaped defects, at the SiO{sub 2}/Si interface, was notably found to correlate with the presence of β-FeSi{sub 2} precipitates. Taking into account the competitive oxidation of these precipitates and of the surrounding silicon matrix, dynamic mechanisms are proposed to model the observed microstructural evolution of the SiO{sub 2}/Si interface, during the growth of the silicon oxide layer.

  2. Recycling of p-type mc-si Top Cuts into p-type mono c-Si Solar Cells

    Energy Technology Data Exchange (ETDEWEB)

    Bronsveld, P.C.P.; Manshanden, P.; Lenzmann, F.O. [ECN Solar Energy, Westerduinweg 3, P.O. Box 1, NL-1755 ZG Petten (Netherlands); Gjerstad, O. [Si Pro Holding AS, Ornesveien 3, P.O. Box 37, 8161, Glomfjord (Norway); Oevrelid, E.J. [SINTEF, Alfred Getz Vei 2, 7465, Trondheim (Norway)

    2013-07-01

    Solar cell results and material analysis are presented of 2 p-type Czochralski (Cz) ingots pulled from a charge consisting of 100% and 50% recycled multicrystalline silicon top cuts. The top cuts were pre-cleaned with a dedicated low energy consuming technology. No structure loss was observed in the bodies of the ingots. The performance of solar cells made from the 100% recycled Si ingot decreases towards the seed end of the ingot, which could be related to a non-optimal pulling process. Solar cells from the tail end of this ingot and from the 50% recycled Si ingot demonstrated an average solar cell efficiency of 18.6%. This is only 0.1% absolute lower than the efficiency of higher resistivity reference solar cells from commercially available wafers that were co-processed.

  3. 一种太阳能硅片清洗剂的制备方法%A preparation method of the solar silicon wafer cleaning agent

    Institute of Scientific and Technical Information of China (English)

    王亚妮; 刘军; 李峰; 许军训

    2012-01-01

    A water-based cleaning agent is prepared for commercial production of solar silicon wafer, it is applied to clean the surface of a solar silicon wafer. The cleaning agent is made up of non-ionic surfactant and an-ionic surfactant. Its solution is alkaline, it doesn't contain organic solvents, no irritating odour, cheaper and good performance of cleaning. The cleaning method is easy and non-toxic on humanbeings and the environment.%研制一种用于工业生产中太阳能硅片的水基专用清洗剂,适用于硅片的表面清洗处理.该清洗剂以非离子表面活性剂和阴离子表面活性剂为主剂,溶液呈碱性,不含有机溶剂,无刺激性气味、成本低、具有良好的去污、清洗性能.清洗方法操作方便、无毒、对人体无危害、对环境无污染.

  4. Robust Technique for Measuring and Simulating Silicon Wafer Quality Characteristics that Enable the Prediction of Solar Cell Electrical Performance of MEMC Silicon Wafer. Cooperative Research and Development Final Report, CRADA Number CRD-11-438

    Energy Technology Data Exchange (ETDEWEB)

    Sopori, Bhushan [National Renewable Energy Lab. (NREL), Golden, CO (United States)

    2015-12-01

    NREL and MEMC Electronic Materials are interested in developing a robust technique for monitoring material quality of mc-Si and mono-Si wafers -- a technique that can provide relevant data to accurately predict the performance of solar cells fabricated on them. Previous work, performed under two TSAs between NREL and MEMC, has established that dislocation clusters are the dominant performance-limiting factor in MEMC mc-Si solar cells. The work under this CRADA will go further in verifying these results on a larger data set, evaluate possibilities of faster method(s) for mapping dislocations in wafers/ingots, understanding dislocation generation during ingot casting, and helping MEMC to have an internal capability for basic characterization that will provide feedback needed for more accurate crystallization simulations. NREL has already developed dislocation mapping technique and developed a basic electronic model (called Network Model) that uses spatial distribution of dislocations to predict the cell performance. In this CRADA work, we will use these techniques to: (i) establish dislocation, grain size, and grain orientation distributions of the entire ingots (through appropriate DOE) and compare these with theoretical models developed by MEMC, (ii) determine concentrations of some relevant impurities in selected wafers, (iii) evaluate potential of using photoluminescence for dislocation mapping and identification of recombination centers, (iv) evaluate use of diode array analysis as a detailed characterization tool, and (v) establish dislocation mapping as a wafer-quality monitoring tool for commercial mc-Si production.

  5. Thermal stress induced void formation during 450 mm defect free silicon crystal growth and implications for wafer inspection

    Science.gov (United States)

    Kamiyama, E.; Vanhellemont, J.; Sueoka, K.; Araki, K.; Izunome, K.

    2013-02-01

    When pulling large diameter Si crystals from a melt close to the Voronkov criterion, small changes in pulling speed and thermal gradient can lead to the formation of voids leading to detrimental pits on the polished wafer surface. The creation of voids is mainly due to the lowering of the vacancy formation energy due to increased thermal compressive stress. The small size and low density of the formed voids when pulling crystals close to the Voronkov criterion conditions are a challenge for wafer surface inspection tools and possible solutions are discussed.

  6. Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers.

    Science.gov (United States)

    Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

    2015-12-04

    Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

  7. 单晶硅片在脉冲激光作用下的断裂行为%Fracture behavior during pulsed laser irradiating silicon wafer

    Institute of Scientific and Technical Information of China (English)

    刘剑; 陆建; 倪晓武; 戴罡; 张梁

    2011-01-01

    Based on the fracture behavior during laser irradiating brittle materials, a controlling fracture technique was used for cutting brittle materials. In order to investigate the mechanism of fracture behavior during pulsed laser irradiating single silicon, a three-dimensional finite element thermoelastic calculational model which contains a pre-existing crack was established based on the heat transfer theory. The development of the temperature field and thermal stress field were investigated during the pulse duration and the changes of stress intensity factor around a crack tip were analyzed. The simulation results show that there are two tensile stress zones induced by the laser heating zone. When the laser spot is near the edge of the silicon wafer, the larger tensile stress is induced at the edge of the silicon wafer, and when the pulsed laser scans the silicon wafer, the pre-existing crack can induce the fracture to propagate along the moving direction of the laser beam. Obtained results are well coincident with the crack expanding process reported by the literature.%基于脆性材料在激光辐照下的断裂行为,将可控断裂激光切割技术应用于脆性材料的加工.为了分析脉冲激光辐照脆性材料过程及脉冲激光扫描过程中产生的断裂行为机理,采用数值计算方法建立了含有裂纹的三维有限元热弹计算模型.分析了脉冲激光辐照单晶硅片过程中温度场和热应力场的变化情况,并模拟计算了硅片边缘含有裂纹时裂纹尖端应力强度因子的变化.计算结果表明,在激光加热区域前后位置存在两个拉应力区,且激光加热区域靠近硅片边缘位置时,硅片边缘会产生较大拉应力;脉冲激光扫描硅片过程中,裂纹尖端的应力集中现象诱发材料持续开裂并引导裂纹沿激光扫描方向扩展.得到的结果与文献报道的裂纹扩展过程相符.

  8. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  9. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  10. Study of hybrid orientation structure wafer*

    Institute of Scientific and Technical Information of China (English)

    Tan Kaizhou; Zhang Jing; Xu Shiliu; Zhang Zhengfan; Yang Yonghui; Chen Jun; Liang Tao

    2011-01-01

    Two types of 5 μm thick hybrid orientation structure wafers, which were integrated by (110) or (100) orientation silicon wafers as the substrate, have been investigated for 15-40 V voltage ICs and MEMS sensor applications. They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique, and have been presented in China for the first time. The thickness of BOX SiO2 buried in wafer is 220 nm. It has been found that the quality of hybrid orientation structure with (100) wafer substrate is better than that with (110) wafer substrate by “Sirtl defect etching of HOSW”.

  11. Optical properties of nanowire structures produced by the metal-assisted chemical etching of lightly doped silicon crystal wafers

    Energy Technology Data Exchange (ETDEWEB)

    Gonchar, K. A., E-mail: k.a.gonchar@gmail.com; Osminkina, L. A. [Moscow State University, Faculty of Physics (Russian Federation); Sivakov, V. [Leibniz Institute of Photonic Technology (Germany); Lysenko, V. [Institut National des Sciences Appliquées (INSA) de Lyon, Nanotechnology Institute of Lyon (France); Timoshenko, V. Yu. [Moscow State University, Faculty of Physics (Russian Federation)

    2014-12-15

    Layers of Si nanowires produced by the metal-assisted chemical etching of (100)-oriented single-crystal p-Si wafers with a resistivity of 1–20 Ω · cm are studied by reflectance spectroscopy, Raman spectros-copy, and photoluminescence measurements. The nanowire diameters are 20–200 nm. The wafers are supplied by three manufacturing companies and distinguished by their different lifetimes of photoexcited charge carriers. It is established that the Raman intensity for nanowires longer than 1 μm is 3–5 times higher than that for the substrates. The interband photoluminescence intensity of nanowires at the wavelength 1.12 μm is substantially higher than that of the substrates and reaches a maximum for samples with the longest bulk lifetime, suggesting a low nonradiative recombination rate at the nanowire surfaces.

  12. Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

    Energy Technology Data Exchange (ETDEWEB)

    Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

    2015-03-14

    The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

  13. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    NARCIS (Netherlands)

    Legrain, A.; Berenschot, J.W.; Sanders, R.G.P.; Ma, K.; Tas, N.R.; Abelmann, L.

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  14. Wafer Replacement Cluster Tool (Presentation);

    Energy Technology Data Exchange (ETDEWEB)

    Branz, H. M.

    2008-04-01

    This presentation on wafer replacement cluster tool discusses: (1) Platform for advanced R and D toward SAI 2015 cost goal--crystal silicon PV at area costs closer to amorphous Si PV, it's 15% efficiency, inexpensive substrate, and moderate temperature processing (<800 C); (2) Why silicon?--industrial and knowledge base, abundant and environmentally benign, market acceptance, and good efficiency; and (3) Why replace wafers?--expensive, high embedded energy content, and uses 50-100 times more silicon than needed.

  15. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  16. Preparation of a catalytic reactor composed of a microchannel etched on a silicon wafer; Shirikon ueha jo ni sakuseishita mikuro channeru wo mochiiru shokubai hanno sochi no shisaku

    Energy Technology Data Exchange (ETDEWEB)

    Tsubota, T.; Miyagawa, D.; Kusakabe, K.; Morooka, S. [Kyushu Univ., Fukuoka (Japan). Dept. of Applied Chemistry

    2000-11-10

    A Microchannel (upper width = 280 {mu}m, lower width = 138 {mu}m, depth 100 {mu}m, length = 27 mm) was formed on a (100) silicon wafer by means of wet chemical etching, and a platinum layer was then coated on the microchannel walls by sputtering. The resulting channel was sealed with a glass cover by an anodic bonding technique. Cyclohexane vapor, carried by a stream of nitrogen, was then introduced into the microreactor at 400 degree C, and the concentrations of both the reactant, and the products of the ensuing dehydrogenation reaction over the platinum catalyst, were determined by means of a micro gas chromatograph. Thus, a series of procedures for manufacturing and testing a microreactor such as lithography of a microchannel, the formation of a catalytic Pt film, the introduction of a reactant into the covered microchannel, or an analysis of reactants and products was established and verified. (author)

  17. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    Science.gov (United States)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-10-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

  18. Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dierickx, B.; Wouters, D.; Willems, G.; Alaerts, A.; Debusschere, I.; Simoen, E.; Vlummens, J.; Akimoto, H.; Claeys, C.; Maes, H.; Hermans, L. (IMEC, Leuven (Belgium)); Heijne, E.H.M.; Jarron, P.; Anghinolfi, F.; Campbell, M.; Pengg, F.X.; Aspell, P. (CERM, Geneve (Switzerland)); Bosisio, L.; Focardi, E.; Forti, F.; Kashigin, S. (INFN sezione di Pisa, Pisa (Italy)); Mekkaoui, A.; Habrard, M.C.; Sauvage, D. (CPPM, Marseille (France)); Delpierre, P. (Coll. de France/IN2P3-CNRS, Paris (France)); Detector R and D Collaboration

    1993-08-01

    A new approach to monolithic pixel detectors, based on SOI wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. This paper reports on the used fabrication methods, and on the results of the electrical evaluation of the SOI - MOSFET devices and of the detector structures fabricated in the bulk. The leakage current of the high-resistivity PIN-diodes was kept in the order of 5 to 10 aA/cm[sup 2]. The SOI preparation processes considered (SIMOX and ZMR) produced working electronic circuits and appear to be compatible with the fabrication of detectors to suitable quality.

  19. Double-plasma enhanced carbon shield for spatial/interfacial controlled electrodes in lithium ion batteries via micro-sized silicon from wafer waste

    Science.gov (United States)

    Chen, Bing-Hong; Chuang, Shang-I.; Duh, Jenq-Gong

    2016-11-01

    Using spatial and interfacial control, the micro-sized silicon waste from wafer slurry could greatly increase its retention potential as a green resource for silicon-based anode in lithium ion batteries. Through step by step spatial and interfacial control for electrode, the cyclability of recycled waste gains potential performance from its original poor retention property. In the stages of spatial control, the electrode stabilizers of active, inactive and conductive additives were mixed into slurries for maintaining architecture and conductivity of electrode. In addition, a fusion electrode modification of interfacial control combines electrolyte additive, technique of double-plasma enhanced carbon shield (D-PECS) to convert the chemical bond states and to alter the formation of solid electrolyte interphases (SEIs) in the first cycle. The depth profiles of chemical composition from external into internal electrode illustrate that the fusion electrode modification not only forms a boundary to balance the interface between internal and external electrodes but also stabilizes the SEIs formation and soothe the expansion of micro-sized electrode. Through these effect approaches, the performance of micro-sized Si waste electrode can be boosted from its serious capacity degradation to potential retention (200 cycles, 1100 mAh/g) and better meet the requirements for facile and cost-effective in industrial production.

  20. Patterned growth of high aspect ratio silicon wire arrays at moderate temperature

    Science.gov (United States)

    Morin, Christine; Kohen, David; Tileli, Vasiliki; Faucherand, Pascal; Levis, Michel; Brioude, Arnaud; Salem, Bassem; Baron, Thierry; Perraud, Simon

    2011-04-01

    High aspect ratio silicon wire arrays with excellent pattern fidelity over wafer-scale area were grown by chemical vapor deposition at moderate temperature, using a gas mixture of silane and hydrogen chloride. An innovative two-step process was developed for in situ doping of silicon wires by diborane. This process led to high p-type doping levels, up to 10 18-10 19 cm -3, without degradation of the silicon wire array pattern fidelity.

  1. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  2. Effect of Nano-sized CeO2 Abrasives on Chemical Mechanical Polishing of Silicon Wafer

    Institute of Scientific and Technical Information of China (English)

    ZHANG Bao-sen; CHEN Yang

    2006-01-01

    The conception of the soft layer during chemical mechanical polishing(CMP) was proposed for the first time. The soft layer was a reaction layer formed on the silicon surface; it was softer than the silicon substrate and its thickness was about several nanometers. The existence of the soft layer could increase the material volume removed by one particle and increase the material removal rate during CMP. At the same time, the soft layer could decrease the cutting depth of the abrasive particle so as to realize ductile grinding, and it is useful to decrease the roughness of the polished surface and to improve the polishing quality.

  3. 用于先进CMOS电路的150mm硅外延片外延生长%Epitaxial Growth of 150mm Silicon Epi-Wafers for Advanced IC Applications

    Institute of Scientific and Technical Information of China (English)

    王启元; 蔡田海; 郁元桓; 林兰英

    2000-01-01

    With the device feature's size miniaturization in very large scale integrated circuit and ultralarge scale integrated circuit towards the sub-micron and beyond level, the next generation of IC device requires silicon wafers with more improved electrical characteristics and reliability as well as a high perfection of the wafer surface. Compared with the polished wafer with a relatively high density of crystal originated defects (e. g. COPs), silicon epi-wafers can meet such high requirements. The current development of researches on the 150mm-silicon epi-wafers for advanced IC applications is described. The P/P+ CMOS silicon epi-wafers were fabricated on a PE2061 Epitaxial Reactor (made by Italian LPE Company). The material parameters of epiwafers, such as epi-defects, uniformity of thickness and resistivity, transition width, and minority carrier generation lifetime for epi-layer were characterized in detail. It is demonstrated that the 150mm silicon epi-wafers on PE2061 can meet the stringent requirements for the advanced IC applications.%随着大规模和超大规模集成电路特征尺寸向亚微米、深亚微米发展,下一代集成电路对硅片的表面晶体完整性和电学性能提出了更高的要求.与含有高密度晶体原生缺陷的硅抛光片相比,硅外延片一般能满足这些要求.该文报道了应用于先进集成电路的150mm P/P+CMOS硅外延片研究进展.在PE2061硅外延炉上进行了P/P+硅外延生长.外延片特征参数,如外延层厚度、电阻率均匀性,过渡区宽度及少子产生寿命进行了详细表征.研究表明:150mm P/P+CMOS硅外延片能够满足先进集成电路对材料更高要求,

  4. Double-layer antireflection from silver nanoparticle integrated SiO2 layer on silicon wafer: effect of nanoparticle morphology and SiO2 film thickness

    Science.gov (United States)

    Parashar, Piyush K.; Sharma, R. P.; Komarala, Vamsi K.

    2017-01-01

    Optical properties of silver nanoparticles (Ag NPs) on SiO2 thin films of variable thickness, as a plasmonic double layer on a plain silicon wafer, are investigated for broadband antireflection. The light confinement into the silicon is found to be sensitive to the SiO2 film thickness of a few nanometers due to an evanescent character of the Ag NPs’ near-fields. The Ag NPs’ size anisotropy plays a pivotal role in incident light coupling due to the sub-wavelength spatial variation of near-fields at the interface, which leads to reflectance spectrum oscillation behavior in the nanoparticles’ surface plasmon resonance and off-resonance regions. With an optimized SiO2/Ag NP double layer, the average reflectance in the 300-1200 nm spectral range is reduced to 14% in comparison to 42% in bare silicon, with a flat minimum reflectance of 3.5% in the 725-1020 nm spectral region. Finite difference time domain calculations are performed for spatial variation of near-fields and their angular distribution of far-fields at different inhomogeneous interfaces (where near-fields exist). The total reflectance from various configurations is simulated theoretically by considering the experimentally optimized physical parameters of the plasmonic double layer to support the observations. To verify the role of SiO2 surface topology apart from the nanoparticle morphology in plasmon near-field coupling, thermally grown SiO2 films are investigated along with the sputtered SiO2 thin films.

  5. Biocompatible "click" wafer bonding for microfluidic devices.

    Science.gov (United States)

    Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

    2012-09-07

    We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via"click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density of surface bound thiol groups and the substrate is a silicon wafer that has been functionalized with common bio-linker molecules. We demonstrate here void free, and low temperature (silane functionalized silicon wafer.

  6. Dry etch method for texturing silicon and device

    Energy Technology Data Exchange (ETDEWEB)

    Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan; Lee, Yun Seog

    2017-07-25

    A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

  7. Performances of miniature microstrip detectors made on oxygen enriched p-type substrates after very high proton irradiation

    Energy Technology Data Exchange (ETDEWEB)

    Casse, G. [Oliver Lodge Laboratory, Department of Physics, University of Liverpool, P.O. Box 147, Liverpool L69 3BX (United Kingdom)]. E-mail: gcasse@hep.ph.liv.ac.uk; Allport, P.P. [Oliver Lodge Laboratory, Department of Physics, University of Liverpool, P.O. Box 147, Liverpool L69 3BX (United Kingdom); Marti i Garcia, S. [IFIC CSIC, Edificio Institutos de Investigacion Apartado de Correos 22085 E-46071, Valencia-Spain (Spain); Lozano, M. [IMB-CNM (CSIC), Campus Universidad Autonoma de Barcelona, 08193 Bellaterra, Barcelona (Spain); Turner, P.R. [Oliver Lodge Laboratory, Department of Physics, University of Liverpool, P.O. Box 147, Liverpool L69 3BX (United Kingdom)

    2004-12-11

    Silicon microstrip detectors with n-type implant read-out strips on FZ p-type bulk (n-in-p) show superior charge collection properties, after heavy irradiation, to the more standard p-strips in n-type silicon (p-in-n). It is also well established that oxygen-enriched n-type silicon substrates show better performance, in terms of degradation of the full depletion voltage after charged hadron irradiation, than the standard FZ silicon used for high energy physics detectors. Silicon microstrip detectors combining both the advantages of oxygenation and of n-strip read-out (n-in-n) have achieved high radiation tolerance to charged hadrons. The manufacturing of n-in-n detectors though requires double-sided processing, resulting in more complicated and expensive devices than standard p-in-n. A cheaper single-sided option, that still combines these advantages, is to use n-in-p devices. P-type FZ wafers have been oxygen-enriched by high temperature diffusion from an oxide layer and successfully used to process miniature (1x1 cm{sup 2}) microstrip detectors. These detectors have been irradiated with 24 GeV/c protons in the CERN/PS T7 irradiation area up to {approx}7.5x10{sup 15} cm{sup -2}. We report results with these irradiated detectors in terms of the charge collection efficiency as a function of the applied bias voltage.

  8. Performances of miniature microstrip detectors made on oxygen enriched p-type substrates after very high proton irradiation

    Science.gov (United States)

    Casse, G.; Allport, P. P.; Martí i Garcia, S.; Lozano, M.; Turner, P. R.

    2004-12-01

    Silicon microstrip detectors with n-type implant read-out strips on FZ p-type bulk (n-in-p) show superior charge collection properties, after heavy irradiation, to the more standard p-strips in n-type silicon (p-in-n). It is also well established that oxygen-enriched n-type silicon substrates show better performance, in terms of degradation of the full depletion voltage after charged hadron irradiation, than the standard FZ silicon used for high energy physics detectors. Silicon microstrip detectors combining both the advantages of oxygenation and of n-strip read-out (n-in-n) have achieved high radiation tolerance to charged hadrons. The manufacturing of n-in-n detectors though requires double-sided processing, resulting in more complicated and expensive devices than standard p-in-n. A cheaper single-sided option, that still combines these advantages, is to use n-in-p devices. P-type FZ wafers have been oxygen-enriched by high temperature diffusion from an oxide layer and succesfully used to process miniature (1×1 cm 2) microstrip detectors. These detectors have been irradiated with 24 GeV/c protons in the CERN/PS T7 irradiation area up to ˜7.5×10 15 cm -2. We report results with these irradiated detectors in terms of the charge collection efficiency as a function of the applied bias voltage.

  9. Cracks and blisters formed close to a silicon wafer surface by He-H co-implantation at low energy

    Energy Technology Data Exchange (ETDEWEB)

    Cherkashin, N., E-mail: nikolay.cherkashin@cemes.fr; Darras, F.-X.; Claverie, A. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse (France); Daghbouj, N. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse (France); Faculté des Sciences de Monastir, Université de Monastir, Monastir (Tunisia); Fnaiech, M. [Faculté des Sciences de Monastir, Université de Monastir, Monastir (Tunisia)

    2015-12-28

    We have studied the effect of reducing the implantation energy towards low keV values on the areal density of He and H atoms stored within populations of blister cavities formed by co-implantation of the same fluence of He then H ions into Si(001) wafers and annealing. Using a variety of experimental techniques, we have measured blister heights and depth from the surface, diameter, areal density of the cracks from which they originate as functions of implantation energy and fluence. We show that there is a direct correlation between the diameters of the cracks and the heights of the associated blisters. This correlation only depends on the implantation energy, i.e., only on the depth at which the cracks are located. Using finite element method modeling, we infer the pressure inside the blister cavities from the elastic deformations they generate, i.e., from the height of the blisters. From this, we demonstrate that the gas pressure within a blister only depends on the diameter of the associated crack and not on its depth position and derive an analytical expression relating these parameters. Relating the pressure inside a blister to the respective concentrations of gas molecules it contains, we deduce the areal densities of He and H atoms contained within the populations of blisters. After low-energy implantations (8 keV He{sup +}, 3 keV H{sup +}), all the implanted He and H atoms contribute to the formation of the blisters. There is no measurable exo-diffusion of any of the implanted gases, in contrast to what was assumed at the state of the art to explain the failure of the Smart-Cut technology when using very low energy ion implantation for the fabrication of ultra-thin layers. Alternative explanations must be investigated.

  10. Cracks and blisters formed close to a silicon wafer surface by He-H co-implantation at low energy

    Science.gov (United States)

    Cherkashin, N.; Daghbouj, N.; Darras, F.-X.; Fnaiech, M.; Claverie, A.

    2015-12-01

    We have studied the effect of reducing the implantation energy towards low keV values on the areal density of He and H atoms stored within populations of blister cavities formed by co-implantation of the same fluence of He then H ions into Si(001) wafers and annealing. Using a variety of experimental techniques, we have measured blister heights and depth from the surface, diameter, areal density of the cracks from which they originate as functions of implantation energy and fluence. We show that there is a direct correlation between the diameters of the cracks and the heights of the associated blisters. This correlation only depends on the implantation energy, i.e., only on the depth at which the cracks are located. Using finite element method modeling, we infer the pressure inside the blister cavities from the elastic deformations they generate, i.e., from the height of the blisters. From this, we demonstrate that the gas pressure within a blister only depends on the diameter of the associated crack and not on its depth position and derive an analytical expression relating these parameters. Relating the pressure inside a blister to the respective concentrations of gas molecules it contains, we deduce the areal densities of He and H atoms contained within the populations of blisters. After low-energy implantations (8 keV He+, 3 keV H+), all the implanted He and H atoms contribute to the formation of the blisters. There is no measurable exo-diffusion of any of the implanted gases, in contrast to what was assumed at the state of the art to explain the failure of the Smart-Cut technology when using very low energy ion implantation for the fabrication of ultra-thin layers. Alternative explanations must be investigated.

  11. Improvement of multicrystalline silicon wafer solar cells by post-fabrication wet-chemical etching in phosphoric acid

    Indian Academy of Sciences (India)

    A Mefoued; M Fathi; J Bhatt; A Messaoud; B Palahouane; N Benrekaa

    2011-12-01

    In this study, we have improved electrical characteristics such as the efficiency () and the fill factor (FF) of finished multicrystalline silicon (-Si) solar cells by using a new chemical treatment with a hot phosphoric (H3PO4) acidic solution. These -Si solar cells were made by a standard industrial process with screen-printed contacts and a silicon nitride (SiN) antireflection coating. We have deposited SiN thin layer (80 nm) on -type -Si substrate by the mean of plasma enhanced chemical vapour deposition (PECVD) technique. The reactive gases used as precursors inside PECVD chamber are a mixture of silane (SiH4) and ammonia (NH3) at a temperature of 380°C. The developed H3PO4 chemical surface treatment has improved from 5.4 to 7.7% and FF from 50.4 to 70.8%, this means a relative increase of up to 40% from the initial values of and FF. In order to explain these improvements, physical (AFM, EDX), chemical (FTIR) and optical (spectrophotometer) analyses were done.

  12. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  13. Effect of the charge on the morphology of sodium salt form of the randomly sulfonated polystyrene ionomer cast onto silicon wafers.

    Science.gov (United States)

    Yu, Jeong-A; Oh, Sung-Hwa; Kim, Joon-Seop

    2007-11-01

    The morphology of the sodium salt form of randomly copolymerized polystyrene sulfonate (Na-PSS) in water/THF(99/1 v/v) cast onto silicon wafers, was studied by using scanning electron microscope (SEM). The contents of the sulfonate repeat units in Na-PSS were 1.1, 2.4, 4.6, 10.8, and 15.6 mol%. Based on the observed SEM images, the morphology of the Na-PSS changed with increasing ionic group content. For 1.1 and 2.4 mol%, sphere-shaped aggregates were formed with average sizes of 90 nm and of 77 nm, respectively. For 4.6 mol% and 10.8 mol%, 20-30 nm-sized aggregates were close-packed and fused together, resulting a surface with large roughness and ca. 10 nm-sized pores were formed. As the mol% increased to 15.6, the surface became smoother and flat films were formed.

  14. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  15. 用稻壳硅源水热合成P型分子筛的研究%Study on the hydrothermal synthesis of P-type zeolite from rice husk silicon

    Institute of Scientific and Technical Information of China (English)

    杨君; 马红超; 付颖寰; 宋宇; 王永为; 于春玲; 董晓丽

    2011-01-01

    利用稻壳中丰富的氧化硅为硅源,以Al(OH)3为外加铝源,采用水热法合成P型分子筛.通过实验得到制备P型分子筛的最佳条件:硅铝摩尔比(SiO2/A12O3)为5.6,钠硅摩尔比(Na2O/SiO2)为1.43,水钠摩尔比(H2O/Na2O)为18.3,反应温度为85℃,反应时间为24 h.X射线衍射(XRD)与扫描电镜分析表明,该条件下合成的P型分子筛具有较高的结晶度,无杂相,其Ca2+(以CaCO3计)交换容量可达320 mg/g.该方法为农业副产物的再利用提供了一条有效途径.%P-type zeolite was hydrothermal synthesized with rice husk as silicon source and A1(OH)3 as Al source. Results showed that the optimum composition for synthesis of P-type zeolite was SiO2/AlzO3 molar ratio of 5. 6, Na2O/SiO2 molar ratio of 1. 43, and H2O/Na2O molar ratio of 18. 3, which could give maximum calcium ionic exchange capacity of P-type zeolite for 320 mg/g (equivalent to CaCO3) when the crystallization temperature was 85 ℃ and reacted for 24 h. Analysis of XRD and SEM indicated that the P zeolite synthesized under optimum condition had pure form, single phase and high crystalline, it could be used as wash auxiliary. The method provided an effective way for the reuse of agricultural by-products.

  16. Simulation of micro contact based on interacting force in self rotating grinding of silicon wafer%硅片自旋转磨削中基于作用力的微观接触仿真研究

    Institute of Scientific and Technical Information of China (English)

    任庆磊; 魏昕; 谢小柱; 胡伟

    2016-01-01

    Self rotating grinding with cup diamond wheel is a typical ultra precision grinding process for silicon wafer.The simulation model based on the force of micro contact between wheel micro unit and silicon wafer is established from the stable ductile grinding process.Micro contact process of self rotating grinding is simulated using the analysis software LS–DYNA.The stress-strain results between silicon wafer and wheel micro unit are analyzed using finite element method.The results show that there exist critical displacements and loads of elastic-plastic and plastic-brittle transitions when processing silicon wafer.During the tangential sliding in plastic zone,plastic grooves and uplifts appear on silicon surface.Wear of wheel micro unit can be judged based on the simulation data.The research provides support for wafer grinding and wheel wear mechanism.%采用杯型金刚石砂轮进行硅片自旋转磨削是典型的硅片超精密磨削加工形式。本试验从其磨削过程中抽象出砂轮微单元与硅片的微观接触作为研究对象,建立基于作用力的仿真模型,采用软件 LS–DYNA 对自旋转磨削微观作用过程进行了模拟,对作用过程中硅片与砂轮微单元的应力应变情况进行了有限元分析。结果表明:硅片材料存在相应弹性转塑性和塑性转脆性的临界位移与载荷;在硅片塑性区域切向滑动时可在硅片表面产生塑性沟槽与隆起;砂轮微单元上的磨损可依据其仿真数据作出判断。研究为硅片磨削及砂轮磨损机理研究提供支撑。

  17. Silver nanocrystals of various morphologies deposited on silicon wafer and their applications in ultrasensitive surface-enhanced Raman scattering

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Limiao, E-mail: chenlimiao@csu.edu.cn; Jing, Qifeng; Chen, Jun; Wang, Bodong; Huang, Jianhan; Liu, Younian

    2013-11-15

    Silver nanostructures with dendritic, flower-like and irregular morphologies were controllably deposited on a silicon substrate in an aqueous hydrogen fluoride solution at room temperature. The morphology of the Ag nanostructures changed from dendritic to urchin-like, flowerlike and pinecone-like with increasing the concentration of polyvinyl pyrrolidone (MW = 55,000) from 2 to 10 mM. The Ag nanostructures were characterized by transmission electron microscopy, high-resolution transmission electron microscopy, scanning electron microscopy, energy-dispersive X-ray, and X-ray diffraction. Through a series of time-dependent morphological evolution studies, the growth processes of Ag nanostructures have been systematically investigated and the corresponding growth mechanisms have been discussed. In addition, the morphology-dependent surface-enhanced Raman scattering of as-synthesized Ag nanostructures were investigated. The results indicated that flower-like Ag nanostructure had the highest activity than the other Ag nanostructures for Rhodamine 6G probe molecules. Highlights: • A simple method was developed to prepare dendritic and flower-like Ag nanostructures. • The flower-like Ag nanoparticles exhibit highest SERS activity. • The SERS substrate based on flower-like Ag particles can be used to detect melamine.

  18. Image Shutters: Gated Proximity-Focused Microchannel-Plate (MCP) Wafer Tubes Versus Gated Silicon Intensified Target (SIT) Vidicons

    Science.gov (United States)

    Yates, G. J.; King, N. S. P.; Jaramillo, S. A.; Ogle, J. W.; Noel, B. W.; Thayer, N. N.

    1983-03-01

    The imaging characteristics of two fast image shutters used for recording the spatial and temporal evolution of transient optical events in the nanosecond range have been studied. Emphasis is on the comparative performances of each shutter type under similar conditions. Response data, including gating speed, gain, dynamic range, shuttering efficiency, and resolution for 18 and 25-mm-diam proximity-focused microchannel-plate (MCP) intensifiers are com-pared with similar data for a prototype electrostatically-focused 25-mm-diam gated silicon-intensified-target (SIT) vidicon currently under development for Los Alamos National Laboratory. Several key parameters critical to optical gating speed have been varied in both tube types in order to determine the optimum performance attainable from each design. These include conductive substrate material and thickness used to reduce photocathode resistivity, spacing between gating electrodes to minimize interelectrode capacitance, the use of con-ductive grids on the photocathode substrate to permit rapid propagation of the electrical gate pulse to all areas of the photocathode, and different package geometries to provide a more effective interface with external biasing and gating circuitry. For comparable spatial resolution, most 18-mm-diam MCPs require gate times > 2.5 ns while the fastest SIT has demonstrated sub-nanosecond optical gates as short as r 400 ± 50 ps for full shuttering of the 25-mm-diam input window.

  19. Image shutters: Gated proximity-focused Microchannel Plate (MCP) wafer tubes versus gated Silicon Intensified Target (SIT) vidicons

    Science.gov (United States)

    Yates, G. J.; King, N. S. P.; Jaramillo, S. A.; Ogle, J. W.; Noel, B. W.; Thayer, N. N.

    Response data, including gating speed, gain, dynamic range, shuttering efficiency, and resolution for 18- and 25-mm-diam proximity-focused microchannel-plate (MCP) intensifiers are compared with similar data for a prototype electrostatically-focused 25-mm-diam gated silicon-intensified-target (SIT) vidicon. Conductive substrate material and thickness used to reduce photocathode resistivity, spacing between gating electrodes to minimize inter-electrode capacitance, the use of conductive grids on the photocathode substrate to permit rapid propagation of the electrical gate pulse to all areas of the photocathode, and different package geometries to provide a more effective interface with external biasing and gating circuitry were varied in both tube types to determine optimal performance from each design. For comparable spatial resolution, most 18-mm-diam MCPs require gate times 2.5 ns while the fastest SIT has demonstrated sub-nanosecond optical gates as short as approximately 400 + or - 50 ps for full shuttering of the 25-mm-diam input window.

  20. 单晶硅片质量对太阳能电池性能的影响研究%Study on the Influence of the Quality of Single Crystal Silicon Wafer on the Performance of Solar Cells

    Institute of Scientific and Technical Information of China (English)

    谢义

    2016-01-01

    The quality of solar cell silicon wafer is a key factor to affect the conversion efficiency of the battery and the power efficiency of the battery module.The existence of wafer defect can greatly reduce the power generation ef-ficiency, shorten the service life of the battery components, and even affect the stability of photovoltaic power gen-eration system.Based on the detection of single crystal silicon wafer, this paper also analyzed the effect of little sub life, early light induced attenuation and dislocation on solar cell and proposed solutions.%太阳能电池硅片的质量是影响电池片转换效率以及电池组件发电效率的一个关键因素。硅片缺陷的存在会极大地降低电池片的发电效率,减少电池组件的使用寿命,甚至影响光伏发电系统的稳定性。通过对单晶硅片质量进行检测,分析少子寿命、早期光致衰减以及位错对太阳能电池性能的影响及解决方案。

  1. 在单晶硅片上直接电化学沉积制备镍反opal光子晶体%Fabrication of Ni inverse opal photonic crystals on silicon wafer by electrodeposition

    Institute of Scientific and Technical Information of China (English)

    许静

    2012-01-01

    采用电化学沉积工艺直接向组装在单晶硅片上的聚苯乙烯胶体晶体中填充金属Ni,成功制备了Ni的反opal光子晶体.采用线性扫描伏安法研究了单晶硅表面的化学刻蚀对Ni的电化学沉积过程的影响,并采用扫描电子显微镜(SEM)、X射线衍射等对Ni反opal光子晶体的形貌和结构进行了观察分析,对其光学性能进行了初步研究.研究结果表明,对单晶硅片表面进行化学刻蚀有利于金属Ni的电化学沉积;在PS胶体晶体模板中电化学生长的金属Ni呈多晶状态,去除模板后形成了金属Ni的有序多孔结构.%Electrodeposition was used to fill the voids of PS colloidal crystals on silicon wafer with Ni and Ni inverse opal was obtained. The influence of chemical etching of silicon wafer on the electrodeposition of Ni was studied by using cyclic voltammetry scan. The resulted Ni inverse opal was characterized by scanning electron microscopy and X-ray diffraction. It showed that chemical etching of silicon surface is beneficial for the deposition of Ni on silicon wafer. Ni grown in the voids of PS colloidal crystals is the polycrystalline phase and the ordered porous structure of Ni is formed after the removing of the PS template.

  2. Fabricating Capacitive Micromachined Ultrasonic Transducers with Wafer Bonding Technique

    Directory of Open Access Journals (Sweden)

    Anil ARORA

    2008-06-01

    Full Text Available We report the fabrication of capacitive micromachined ultrasonic transducer by wafer bonding technique. Membrane is transferred from SOI wafer to the prime wafer having silicon dioxide cavity. The thickness of cavity height depends on silicon dioxide grown on prime wafer by dry/wet oxidation. Thinning of device wafer of SOI by oxidation, controls membrane thickness. Two wafers are bonded in vacuum under optimized controlled parameters. Using this method, we can get single crystal silicon as membrane, whose mechanical and electrical parameters are well known. Silicon membrane is free from stress and density variation. Focused Ion Beam etching and laser Doppler Vibrometer were used to do structural and electrical characterization respectively. The measured resonance frequency of fabricated device i.e. 2.24 MHz is much closer to the designed value i.e. 2.35 MHz.

  3. Low-loss and flatband silicon-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm SOI wafer

    Science.gov (United States)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Seki, Miyoshi; Yokoyama, Nobuyuki; Ohtsuka, Minoru; Koshino, Keiji; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-03-01

    We present flatband, low-loss and low-crosstalk characteristics of Si-nanowire-based 5th-order coupled resonator optical waveguides (CROW) fabricated by ArF-immersion lithography process on a 300-mm silicon-on-insulator (SOI) wafer. We theoretically specified why phase controllability over Si-nanowire waveguides is prerequisite to attain desired spectral response, discussing spectral degradation by random phase errors during fabrication process. It was experimentally demonstrated that advanced patterning technology based on ArF-immersion lithography process showed extremely low phase errors even for Si-nanowire channel waveguides. As a result, the device exhibited extremely low loss of CROW. We believe these high-precision fabrication technologies based on 300-mm SOI wafer scale ArF-immersion lithography would be promising for several kinds of WDM multiplexers/demultiplexers having much complicated configurations and requiring much finer phase controllability.

  4. Design and Development of Surface Modified p and n Type Silicon Sensor for Nitrogen Gas Flow Measurement

    CERN Document Server

    Satheesh, U; Devaprakasam, D

    2014-01-01

    We report a gas flow driven voltage generation of Octyltrichlorosilane (OTS) molecules self assembled on silicon wafers (Si wafers). OTS Self assembled Monolayer (SAM) has been coated on both p-type and n-type doped silicon wafers (p-Si and n-Si wafers) using dip coating method. We have measured the flow induced voltage generation on OTS SAM coated Si wafers/ Uncoated Si wafers at modest gas flow velocities of subsonic regime (Mach number < 0.2) using national instruments NI-PXI-1044 Workstation. The gas flow driven voltage generation is mainly due to the interplay mechanisms of Bernoulli principle and Seebeck effect. The surface morphology of OTS SAM coated p-Si and n-Si wafers were characterized by SEM analysis. In this study, our results shows that OTS SAM coated p-Si and n-Si wafers shows better sensitivity towards nitrogen gas flow when compared with the uncoated Si wafers. OTS SAM also exhibits high thermal stability and hydrophobicity.

  5. Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

    Energy Technology Data Exchange (ETDEWEB)

    Fong, Theodore E.

    2013-05-06

    The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technology further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.

  6. P型硅衬底异质结太阳电池的优化设计%Design Optimization of Heterojunction Solar Cells on p-type Silicon Substrates

    Institute of Scientific and Technical Information of China (English)

    汪骏康; 徐静平

    2012-01-01

    The performance of TCO/a-Si∶H(n)/a-Si∶H(i)/c-Si(p)/a-Si∶H(p+)/Ag heterojunction solar cells on p-type silicon substrates was simulated by Afors-het software.Optimal structural parameters of thickness,band gap,doping concentration and interface states density were obtained by the results of software optimization and theoretical analysis.The results indicate that well-performed heterojunction solar cells can be designed by using thin and high doping window layer,passivating the defect states of heterojunction interface with intrinsic layer,and making full use of the mirror effect of back surface field.The optimum performance parameters are Voc=678.9 mV,Jsc=38.33 mA/cm2,FF=84.05%,η=21.87%.%采用Afors-het软件模拟分析了结构为TCO/a-Si:H(n)/a-Si:H(i)/c-Si(p)/a-Si:H(p+)/Ag的p型硅衬底异质结太阳电池的性能,研究了各层厚度、带隙、掺杂浓度以及界面态密度等结构参数和物理参数对电池性能的影响。通过模拟优化,结合理论分析和实际工艺,得到合适的各结构参数取值。采用厚度薄且掺杂高的窗口层,嵌入本征层以钝化异质结界面缺陷,合理利用背场对于少子的背反作用,获得了较佳的太阳电池综合性能:开路电压Voc为678.9mV、短路电流密度Jsc为38.33mA/cm2、填充因子FF为84.05%、转换效率η为21.87%。

  7. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  8. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  9. Efficiency Enhancement of Nanoporous Silicon/Polycrystalline-Silicon Solar Cells by Application of Trenched Electrodes

    OpenAIRE

    Kuen-Hsien Wu; Chia-Chun Tang

    2014-01-01

    Trenched electrodes were proposed to enhance the short-circuit current and conversion efficiency of polycrystalline-silicon (poly-Si) solar cells with nanoporous silicon (NPS) surface layers. NPS films that served as textured surface layers were firstly prepared on heavily doped p+-type (100) poly-Si wafers by anodic etching process. Interdigitated trenches were formed in the NPS layers by a reactive-ion-etch (RIE) process and Cr/Al double-layered metal was then deposited to fill the trenches...

  10. Effect of temperature and silicon resistivity on the elaboration of silicon nanowires by electroless etching

    Energy Technology Data Exchange (ETDEWEB)

    Fellahi, Ouarda, E-mail: fellahi_warda@yahoo.fr [Silicon Technology Development Unit, 02 Bd Frantz Fanon, BP 140 Alger-7 Merveilles, Algiers (Algeria); Hadjersi, Toufik [Silicon Technology Development Unit, 02 Bd Frantz Fanon, BP 140 Alger-7 Merveilles, Algiers (Algeria); Maamache, Mustapha [Laboratoire de Physique Quantique et Systemes Dynamiques, Universite Ferhat Abbas de Setif (Algeria); Bouanik, Sihem; Manseri, Amar [Silicon Technology Development Unit, 02 Bd Frantz Fanon, BP 140 Alger-7 Merveilles, Algiers (Algeria)

    2010-11-01

    The morphology of silicon nanowire (SiNW) layers formed by Ag-assisted electroless etching in HF/H{sub 2}O{sub 2} solution was studied. Prior to the etching, the Ag nanoparticles were deposited on p-type Si(1 0 0) wafers by electroless metal deposition (EMD) in HF/AgNO{sub 3} solution at room temperature. The effect of etching temperature and silicon resistivity on the formation process of nanowires was studied. The secondary ion mass spectra (SIMS) technique is used to study the penetration of silver in the etched layers. The morphology of etched layers was investigated by scanning electron microscope (SEM).

  11. Superhydrophobic Porous Silicon Surfaces

    Directory of Open Access Journals (Sweden)

    Paolo NENZI

    2011-12-01

    Full Text Available In this paper, we present an inexpensive technique to produce superhydrophobic surfaces from porous silicon. Superhydrophobic surfaces are a key technology for their ability to reduce friction losses in microchannels and their self cleaning properties. The morphology of a p-type silicon wafer is modified by a electrochemical wet etch to produce pores with controlled size and distribution and coated with a silane hydrophobic layer. Surface morphology is characterized by means of scanning electron microscope images. Large contact angles are observed on such surfaces and the results are compared with classical wetting models (Cassie and Wenzel suggesting a mixed Wenzel-Cassie behavior. The presented technique represents a cost-effective means for friction reduction in microfluidic applications, such as lab-on-a-chip.

  12. Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

    Science.gov (United States)

    Nogay, Gizem; Stuckelberger, Josua; Wyss, Philippe; Jeangros, Quentin; Allebé, Christophe; Niquille, Xavier; Debrot, Fabien; Despeisse, Matthieu; Haug, Franz-Josef; Löper, Philipp; Ballif, Christophe

    2016-12-28

    The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiCx(p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiCx(p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiCx(p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm(-2) on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a Voc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p(+)/p-wafer full-side-passivated rear-side scheme shown here.

  13. Scanning transmission electron microscope analysis of amorphous-Si insertion layers prepared by catalytic chemical vapor deposition, causing low surface recombination velocities on crystalline silicon wafers

    OpenAIRE

    2012-01-01

    Microstructures of stacked silicon-nitride/amorphous-silicon/crystalline-silicon (SiN_x/a-Si/c-Si) layers prepared by catalytic chemical vapor deposition were investigated with scanning transmission electron microscopy to clarify the origin of the sensitive dependence of surface recombination velocities (SRVs) of the stacked structure on the thickness of the a-Si layer. Stacked structures with a-Si layers with thicknesses greater than 10 nm exhibit long effective carrier lifetimes, while thos...

  14. Characterization of thermal, optical and carrier transport properties of porous silicon using the photoacoustic technique

    Energy Technology Data Exchange (ETDEWEB)

    Sheng, Chan Kok [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 UPM Serdang, Selangor (Malaysia); Mahmood Mat Yunus, W. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 UPM Serdang, Selangor (Malaysia)], E-mail: mahmood@science.upm.edu.my; Yunus, Wan Md. Zin Wan [Department of Chemistry, Faculty of Science, Universiti Putra Malaysia, 43400 UPM Serdang (Malaysia); Abidin Talib, Zainal [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 UPM Serdang, Selangor (Malaysia); Kassim, Anuar [Department of Chemistry, Faculty of Science, Universiti Putra Malaysia, 43400 UPM Serdang (Malaysia)

    2008-08-01

    In this work, the porous silicon layer was prepared by the electrochemical anodization etching process on n-type and p-type silicon wafers. The formation of the porous layer has been identified by photoluminescence and SEM measurements. The optical absorption, energy gap, carrier transport and thermal properties of n-type and p-type porous silicon layers were investigated by analyzing the experimental data from photoacoustic measurements. The values of thermal diffusivity, energy gap and carrier transport properties have been found to be porosity-dependent. The energy band gap of n-type and p-type porous silicon layers was higher than the energy band gap obtained for silicon substrate (1.11 eV). In the range of porosity (50-76%) of the studies, our results found that the optical band-gap energy of p-type porous silicon (1.80-2.00 eV) was higher than that of the n-type porous silicon layer (1.70-1.86 eV). The thermal diffusivity value of the n-type porous layer was found to be higher than that of the p-type and both were observed to increase linearly with increasing layer porosity.

  15. Bubble evolution mechanism and stress-induced crystallization in low-temperature silicon wafer bonding based on a thin intermediate amorphous Ge layer

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2017-10-01

    The dependence of the morphology and crystallinity of an amorphous Ge (a-Ge) interlayer between two Si wafers on the annealing temperature is identified to understand the bubble evolution mechanism. The effect of a-Ge layer thickness on the bubble density and size at different annealing temperatures is also clearly clarified. It suggests that the bubble density is significantly affected by the crystallinity and thickness of the a-Ge layer. With the increase of the crystallinity and thickness of the a-Ge layer, the bubble density decreases. It is important that a near-bubble-free Ge interface, which is also an oxide-free interface, is achieved when the bonded Si wafers (a-Ge layer thickness  ⩾  20 nm) are annealed at 400 °C. Furthermore, the crystallization temperature of the a-Ge between the bonded Si wafers is lower than that on a Si substrate alone and the Ge grains firstly form at the Ge/Ge bonded interface, rather than the Ge/Si interface. We believe that the stress-induced crystallization of a-Ge film and the intermixing of Ge atoms at the Ge/Ge interface can be responsible for this feature.

  16. 雾化施液抛光硅片位错的化学腐蚀形貌分析%Chemical Corrosion Morphology Analysis of Dislocations of Silicon Wafer Polished by Ultrasonic Atomization CMP

    Institute of Scientific and Technical Information of China (English)

    壮筱凯; 李庆忠

    2015-01-01

    目的:研究硅片经雾化施液抛光技术加工后存在的位错缺陷。方法应用化学腐蚀法、光学方法分析硅片不同部位的位错腐蚀形貌、位错密度及其分布,通过单因素实验研究雾化参数对位错形貌和位错密度的影响规律。在相同的工艺参数下,和传统抛光进行对比实验。结果雾化抛光硅片的平均位错密度为1.2×104/cm2,边沿处的位错密度小于其他区域。在相同的工艺参数下,雾化施液CMP的抛光液消耗量约为传统CMP的1/10,但硅片的位错腐蚀形貌和位错密度明显好于传统抛光,且蚀坑分布均匀分散,没有出现位错排等严重缺陷。通过增大雾化器的出雾量能有效改善硅片表层的位错缺陷。结论相对于传统抛光,雾化施液抛光技术能更加高效地去除硅片的位错缺陷。%ABSTRACT:Objective To study the dislocation defect of silicon wafer which was polished by ultrasonic atomization chemical me-chanical polishing ( CMP) . Methods The chemical etching method and optics method were used to analyze the morphology, densi-ty, and distribution of the dislocation etch pits. Besides, the influence of atomization quantity on the morphology and density of dis-location was studied by single factor experiment. Then comparative experiments were conducted with traditional CMP under the same conditions. Results The average dislocation density of the polished silicon wafer was about 1. 2×104/cm2 and the dislocation density in edge area was lower than other areas. Besides, the dislocation morphology and dislocation density of silicon wafer pol-ished by ultrasonic atomization CMP were obviously better than those treated by traditional CMP under the same conditions while thepolishing liquid consumption was about one tenth of traditional CMP. The dislocation etch pits distributed evenly and there were no serious flaws such as dislocation piles and so on. In addition to that, the dislocation defect could be

  17. Solar wafer market in a crisis; Ausgeduennt

    Energy Technology Data Exchange (ETDEWEB)

    Heup, Juergen

    2010-07-15

    After a boom period in which producers of silicon wafers were hailed for reducing the cost of solar modules, the market is now undergoing a period of stress, and some producers were unable to continue. The contribution presents an example to show how the industry can be saved. (orig.)

  18. Characterizations of Tb:Zn2SiO4 films on silicon wafer prepared by sol-gel dip-coating and solid-phase reaction

    Institute of Scientific and Technical Information of China (English)

    Ji Zhen-Guo; Zhao Shi-Chao; Xiang Yin; Song Yong-Liang; Ye Zhi-Zhen

    2004-01-01

    Terbium-doped Zn2SiO4 films were successfully prepared on Si wafers by a simple sol-gel dip-coating and solidphase reaction method of ZnO and SiO2. X-ray diffraction (XRD) and UV-Vis absorption results revealed that films processed below 850℃ were ZnO in wurzite structure, and films processed above 850℃ were Zn2SiO4 in wellimite structure. Photoluminescence measurements of the Tb-doped Zn2SiO4 films showed two strong emission bands at 490and 545nm. The photoluminescence lifetime was 4.6ms.

  19. Investigation of the Relationship between Whole-Wafer Strength and Control of Its Edge Engineering

    Science.gov (United States)

    Chen, Po-Ying; Tsai, Ming-Hsing; Yeh, Wen-Kuan; Jing, Ming-Haw; Chang, Yukon

    2009-12-01

    Silicon wafer breakage has become a major concern for all semiconductor fabrication lines because it is brittle, and thus high stresses are easily induced in its manufacture. The production cost of devices significantly increases even for a breakage loss of a few percent if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant. In this investigation, we develop a brand new approach to reducing breakage by using a charge-coupled device (CCD) to capture the cross-section image of the wafer at its edge; the data measured at the edge can be used to determine overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength, and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in the wafer bulk before failure. We also describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unidentified causes. Our analysis gives the optimal front size (B1), edge widths (A1,A2), and bevel angle (θ) for the edge profiles of wafers to prevent wafer breakage. Briefly, when a suitable material and suitable process control approaches are utilized, silicon wafer breakage can be prevented. This is the first investigation providing evidence that whole-wafer strength is an important issue. We present a physical model to explain why wafer fracture has become an increasingly serious problem as the diameter of wafers has increased. The control of wafer edge geometry has been demonstrated to be an effective means of protecting wafers with large diameters against breakage. This model reveals that the breakage rate of wafers can be reduced by controlling the uniformity of the differences between the front size and the rear edge widths during the wafer manufacturing process.

  20. Interfacial Characterizations of a Nickel-Phosphorus Layer Electrolessly Deposited on a Silane Compound-Modified Silicon Wafer Under Thermal Annealing

    Science.gov (United States)

    Lai, Kuei-Chang; Wu, Pei-Yu; Chen, Chih-Ming; Wei, Tzu-Chien; Wu, Chung-Han; Feng, Shien-Ping

    2016-10-01

    Front-side metallization of a Si wafer was carried out using electroless deposition of nickel-phosphorus (Ni-P) catalyzed by polyvinylpyrrolidone-capped palladium nanoclusters (PVP-nPd). A 3-[2-(2-Aminoethylamino)ethylamino] propyl-trimethoxysilane (ETAS) layer was covalently bonded on the Si surface as bridge linker to the Pd cores of PVP-nPd clusters for improving adhesion between the Ni-P layer and the Si surface. To investigate the effects of an interfacial ETAS layer on the Ni silicide formation at the Ni-P/Si contact, the Ni-P-coated Si samples were thermally annealed via rapid thermal annealing (RTA) from 500°C to 900°C for 2 min. To compare with the ETAS sample, the sputtered Ni layer on Si and electroless Ni-P layer on ion-Pd-catalyzed Si (both are standard processes) were also investigated. The microstructural characterizations for the Ni-P or Ni layer deposited on the Si wafer were performed using x-ray diffractometer, scanning electron microscopy, and transmission electron microscopy. Our results showed that the ETAS layer acted as a barrier to slow the atomic diffusion of Ni toward the Si side. Although the formation of Ni silicides required a higher annealing temperature, the adhesion strength and contact resistivity measurements of annealed Ni-P/Si contacts showed satisfactory results, which were essential to the device performance and reliability during thermal annealing.

  1. Particle detectors made of high-resistivity Czochralski silicon

    CERN Document Server

    Härkönen, J; Ivanov, A; Li, Z; Luukka, Panja; Pirojenko, A; Riihimaki, I; Tuominen, E; Tuovinen, E; Verbitskaya, E; Virtanen, A

    2005-01-01

    We have processed pin-diodes and strip detectors on n- and p-type high-resistivity silicon wafers grown by magnetic Czochralski method. The Czochralski silicon (Cz-Si) wafers manufactured by Okmetic Oyj have nominal resistivity of 900 Omega cm and 1.9 kOmega cm for n- and p-type, respectively. The oxygen concentration in these substrates is slightly less than typically in wafers used for integrated circuit fabrication. This is optimal for semiconductor fabrication as well as for radiation hardness. The radiation hardness of devices has been investigated with several irradiation campaigns including low- and high-energy protons, neutrons, gamma-rays, lithium ions and electrons. Cz-Si was found to be more radiation hard than standard Float Zone silicon (Fz-Si) or oxygenated Fz-Si. When irradiated with protons, the full depletion voltage in Cz-Si has not exceeded its initial value of 300 V even after the fluence of 5 multiplied by 10**1**4 cm**-**2 1-MeV eq. n cm **-**2 that equals more than 30 years operation of...

  2. Realization of Ultraviolet Electroluminescence from ZnO Homo junction Fabricated on Silicon Substrate with p-Type ZnO:N Layer Formed by Radical N2O Doping

    Institute of Scientific and Technical Information of China (English)

    SUN Jing-Chang; LIANG Hong-Wei; ZHAO Jian-Ze; BIAN Ji-Ming; FENG Qiu-Ju; WANG Jing-Wei; ZHAO Zi-Wen; DU Guo-Tong

    2008-01-01

    @@ ZnO homojunction light-emitting diodes are fabricated on Si(100) substrates by plasma assisted metal organic chemical vapour deposition, A p-type layer of nitrogen-doped ZnO film is formed using radical N2O as the acceptor precursor.The n-type ZnO layer is composed of un-doped ZnO film.The device exhibits desirable rectifying behaviour with a turn-on voltage of 3.3 V and a reverse breakdown voltage higher than 6 V.Distinct electroluminescence emissions centred at 395nm and 49Ohm are detected from this device at forvcard current higher than 20mA at room temperature.

  3. Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

    Institute of Scientific and Technical Information of China (English)

    Ngoc Huynh Van; Jae-Hyun Lee; Dongmok Whang; Dae Joon Kang

    2015-01-01

    A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)). We overcame the interfacial layer problem by incorporating P(VDF-TrFE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFF ratio higher than 102.

  4. Technology Development for High-Efficiency Solar Cells and Modules Using Thin (<80 um) Single-Crystal Silicon Wafers Produced by Epitaxy: June 11, 2011 - April 30, 2013

    Energy Technology Data Exchange (ETDEWEB)

    Ravi, T. S.

    2013-05-01

    Final technical progress report of Crystal Solar subcontract NEU-31-40054-01. The objective of this 18-month program was to demonstrate the viability of high-efficiency thin (less than 80 um) monocrystalline silicon (Si) solar cells and modules with a low-cost epitaxial growth process.

  5. Technology Development for High-Efficiency Solar Cells and Modules Using Thin (<80 um) Single-Crystal Silicon Wafers Produced by Epitaxy: June 11, 2011 - April 30, 2013

    Energy Technology Data Exchange (ETDEWEB)

    Ravi, T. S.

    2013-05-01

    Final technical progress report of Crystal Solar subcontract NEU-31-40054-01. The objective of this 18-month program was to demonstrate the viability of high-efficiency thin (less than 80 um) monocrystalline silicon (Si) solar cells and modules with a low-cost epitaxial growth process.

  6. Optical and electrical characterization of crystalline silicon films formed by rapid thermal annealing of amorphous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Baldus-Jeursen, Christopher, E-mail: cjbaldus@uwaterloo.ca; Tarighat, Roohollah Samadzadeh, E-mail: rsamadza@uwaterloo.ca; Sivoththaman, Siva, E-mail: sivoththaman@uwaterloo.ca

    2016-03-31

    The effect of rapid thermal annealing (RTA) on n-type hydrogenated amorphous silicon (a-Si:H) films deposited on single-crystal silicon (c-Si) wafers was studied by electrical and optical methods. Deposition of a-Si:H films by plasma-enhanced chemical vapor deposition (PECVD) was optimized for high deposition rate and maximum film uniformity. RTA processed films were characterized by spreading resistance profiling (SRP), Hall effect, spectroscopic ellipsometry, defect etching, and transmission electron microscopy (TEM). It was found that the films processed between 600 °C and 1000 °C were highly crystalline and that the defect density in the films diminished with increasing thermal budget. Junctions formed by the RTA processed n-type a-Si:H films on p-type c-Si wafers were tested for device applicability. It was established that these films can be used as the emitter layer in n{sup +}p photovoltaic (PV) devices with over 14% conversion efficiency. - Highlights: • Rapid thermal annealing of doped amorphous silicon deposited on single-crystal silicon (c-Si) wafers resulted in highly crystalline films for photovoltaic devices. • As the annealing temperature increased, the electrical and optical properties of the films became increasingly similar to single-crystal silicon. • Annealing temperatures between 500-1000 oC were investigated. Solar cell devices fabricated after annealing at 750 oC were found to be the most suitable compromise between good quality crystalline films and minimal dopant diffusion into the c-Si wafer. • Annealed films were highly conductive without the need for a transparent conducting oxide.

  7. Wafer-scale graphene integrated circuit.

    Science.gov (United States)

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  8. Wafer-scale nanostructure formation inside vertical nano-pores

    NARCIS (Netherlands)

    Berenschot, Johan W.; Sun, Xingwu; Le The, Hai; Tiggelaar, Roald M.; de Boer, Meint J.; Eijkel, Jan C.T.; Gardeniers, Johannes G.E.; Tas, Niels Roelof; Sarajlic, Edin

    We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced

  9. Wafer-scale nanostructure formation inside vertical nano-pores

    NARCIS (Netherlands)

    Berenschot, Johan W.; Sun, Xingwu; Le The, Hai; Tiggelaar, Roald M.; de Boer, Meint J.; Eijkel, Jan C.T.; Gardeniers, Johannes G.E.; Tas, Niels Roelof; Sarajlic, Edin

    2017-01-01

    We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced

  10. Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

    Directory of Open Access Journals (Sweden)

    Atteq ur Rehman

    2013-01-01

    Full Text Available The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

  11. Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

    Science.gov (United States)

    ur Rehman, Atteq; Lee, Soo Hong

    2013-01-01

    The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

  12. Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

    Science.gov (United States)

    ur Rehman, Atteq; Lee, Soo Hong

    2013-01-01

    The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

  13. Some disconnected speculations on slicing silicon

    Science.gov (United States)

    Iles, P. A.

    1982-02-01

    The basic principles for qualifying silicon wafering methods are summarized, and unconventional methods of wafering was discussed. Methods of cleaving analogous to diamond cutting, geological processes employing the expansion of freezing water, and karate chops are touched upon.

  14. Biocompatible "click" wafer bonding for microfluidic devices

    OpenAIRE

    Saharil, Farizah; Carlborg, Carl Fredrik; Haraldsson, Tommy; van der Wijngaart, Wouter

    2012-01-01

    We introduce a novel dry wafer bonding concept designed for permanent attachment of micromolded polymer structures to surface functionalized silicon substrates. The method, designed for simultaneous fabrication of many lab-on-chip devices, utilizes a chemically reactive polymer microfluidic structure, which rapidly bonds to a functionalized substrate via "click" chemistry reactions. The microfluidic structure consists of an off-stoichiometry thiol-ene (OSTE) polymer with a very high density o...

  15. In-line high-rate evaporation of aluminum for the metallization of silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Mader, Christoph Paul

    2012-07-11

    This work focuses on the in-line high-rate evaporation of aluminum for contacting rear sides of silicon solar cells. The substrate temperature during the deposition process, the wafer bow after deposition, and the electrical properties of evaporated contacts are investigated. Furthermore, this work demonstrates for the first time the formation of aluminum-doped silicon regions by the in-line high-rate evaporation of aluminum without any further temperature treatment. The temperature of silicon wafers during in-line high-rate evaporation of aluminum is investigated in this work. The temperatures are found to depend on the wafer thickness W, the aluminum layer thickness d, and on the wafer emissivity {epsilon}. Two-dimensional finite-element simulations reproduce the measured peak temperatures with an accuracy of 97%. This work also investigates the wafer bow after in-line high-rate evaporation and shows that the elastic theory overestimates the wafer bow of planar Si wafers. The lower bow is explained with plastic deformation in the Al layer. Due to the plastic deformation only the first 79 K in temperature decrease result in a bow formation. Furthermore the electrical properties of evaporated point contacts are examined in this work. Parameterizations for the measured saturation currents of contacted p-type Si wafers and of contacted boron-diffused p{sup +}-type layers are presented. The contact resistivity of the deposited Al layers to silicon for various deposition processes and silicon surface concentrations are presented and the activation energy of the contact formation is determined. The measured saturation current densities and contact resistivities of the evaporated contacts are used in one-dimensional numerical Simulations and the impact on energy conversion efficiency of replacing a screen-printed rear side by an evaporated rear side is presented. For the first time the formation of aluminum-doped p{sup +}-type (Al-p{sup +}) silicon regions by the in

  16. Wafer characteristics via reflectometry

    Science.gov (United States)

    Sopori, Bhushan L.

    2010-10-19

    Various exemplary methods (800, 900, 1000, 1100) are directed to determining wafer thickness and/or wafer surface characteristics. An exemplary method (900) includes measuring reflectance of a wafer and comparing the measured reflectance to a calculated reflectance or a reflectance stored in a database. Another exemplary method (800) includes positioning a wafer on a reflecting support to extend a reflectance range. An exemplary device (200) has an input (210), analysis modules (222-228) and optionally a database (230). Various exemplary reflectometer chambers (1300, 1400) include radiation sources positioned at a first altitudinal angle (1308, 1408) and at a second altitudinal angle (1312, 1412). An exemplary method includes selecting radiation sources positioned at various altitudinal angles. An exemplary element (1650, 1850) includes a first aperture (1654, 1854) and a second aperture (1658, 1858) that can transmit reflected radiation to a fiber and an imager, respectfully.

  17. Electrical properties of deuteron irradiated high resistivity silicon

    Energy Technology Data Exchange (ETDEWEB)

    Krupka, Jerzy, E-mail: krupka@imio.pw.edu.pl [Insitute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Karcz, Waldemar [H. Niewodniczański Institute of Nuclear Physics Polish Academy of Science, Cracow (Poland); Joint Institute for Nuclear Research, Joliot-Curie 6, 141980 Dubna (Russian Federation); Avdeyev, Sergej P. [Joint Institute for Nuclear Research, Joliot-Curie 6, 141980 Dubna (Russian Federation); Kamiński, Paweł; Kozłowski, Roman [Institute of Electronic Materials Technology, Wólczyńska 133, 01-919 Warsaw (Poland)

    2014-04-01

    We have investigated resistivity changes introduced on the high-resistivity p-type silicon wafer by the irradiation with deuteron beam with an energy of 4.4 GeV performed in the NUCLOTRON superconducting accelerator. Two contactless techniques were used for the measurements of resistivity changes: namely the microwave split post dielectric resonator (SPDR) technique and capacitance measurements in the frequency domain. The first technique allows resistivity measurements in the plane of the wafer, while the second one in the direction perpendicular to the wafer. The resistivity map obtained with the SPDR technique enabled us to obtain a permanent fingerprint of the accelerator beam intensity profile. It has been shown that after the irradiation, the material resistivity increased to ∼3.9 × 10{sup 5} Ω cm in the wafer region exposed to the maximum beam intensity. Complementary studies of the properties and concentrations of radiation deep-level defects were performed by the high-resolution photo-induced current transient spectroscopy (HRPITS). These studies have shown that the irradiation of the high resistivity silicon with 4.4-GeV deuterons results in the formation of several types of deep-level defects responsible for the charge compensation.

  18. Liquid-phase-deposited siloxane-based capping layers for silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Veith-Wolf, Boris [Institute for Solar Energy Research Hamelin (ISFH), Am Ohrberg 1, 31860 Emmerthal (Germany); Wang, Jianhui; Hannu-Kuure, Milja; Chen, Ning; Hadzic, Admir; Williams, Paul; Leivo, Jarkko; Karkkainen, Ari [Optitune International Pte. Ltd., 20 Maxwell Road, #05-08 Maxwell House, Singapore 069113 (Singapore); Schmidt, Jan [Institute for Solar Energy Research Hamelin (ISFH), Am Ohrberg 1, 31860 Emmerthal (Germany); Department of Solar Energy, Institute of Solid-State Physics, Leibniz University Hanover, Appelstrasse 2, 30167 Hanover (Germany)

    2015-02-02

    We apply non-vacuum processing to deposit dielectric capping layers on top of ultrathin atomic-layer-deposited aluminum oxide (AlO{sub x}) films, used for the rear surface passivation of high-efficiency crystalline silicon solar cells. We examine various siloxane-based liquid-phase-deposited (LPD) materials. Our optimized AlO{sub x}/LPD stacks show an excellent thermal and chemical stability against aluminum metal paste, as demonstrated by measured surface recombination velocities below 10 cm/s on 1.3 Ωcm p-type silicon wafers after firing in a belt-line furnace with screen-printed aluminum paste on top. Implementation of the optimized LPD layers into an industrial-type screen-printing solar cell process results in energy conversion efficiencies of up to 19.8% on p-type Czochralski silicon.

  19. Fast Homo-epitaxy Growth of 4-inch Silicon Carbide Wafer%4英寸碳化硅快速同质外延生长研究

    Institute of Scientific and Technical Information of China (English)

    钮应喜; 杨霏; 温家良; 陈新

    2014-01-01

    Homo-epitaxial growth of 4H-SiC epi-layers are conducted on the 4-inch substrates by hot-wall chemical vapor deposition (CVD), the silicon precursor dependence of growth rate, the temperature dependences of surface morphology and surface defect are investigated. The high growth rate of 26.8 µm/h is achieved;the good layer with the mirror-like smooth surface is got on the growth rate of 22 µm/h after optimization. The layers are characterized by an atomic force microscope (AFM) and optical surface defect analyzer candela CS20, indicating an surface roughness of 0.12 nm and a total morphological defect density of 0.36 cm–2.It is found that the temperature could greatly influence the surface roughness and defects, while the good quality silicon carbide epitaxial materials without Si droplets and with low defect density could be obtained by increasing the temperature.%采用热壁化学气相沉积法在4英寸4H-SiC衬底上进行同质外延生长,研究硅烷流量、温度的变化对外延生长速率、表面形貌以及表面缺陷的影响。外延生长速率最高达到26.8µm/h,优化后在22µm/h的生长速率上获得表面光滑的外延层。通过原子力显微镜分析,优化后的外延层表面粗糙度达到0.12 nm;通过表面缺陷测试仪分析,优化后的外延层表面缺陷密度达到0.36 cm–2。研究发现,温度变化会对表面粗糙度以及表面缺陷有很大的影响,通过提高温度可获得无硅滴、低缺陷密度的高质量碳化硅外延材料。

  20. Microfabrication and Evaluation of a Silicon Microelectrode Based on SOI Wafer%基于SOI硅片的硅微电极制作与评估

    Institute of Scientific and Technical Information of China (English)

    隋晓红; 陈弘达

    2008-01-01

    采用微机电系统(MEMS)工艺方法制作了基于SOI衬底的七通道硅微电极,用于视神经视觉修复.通过噪声分析确定了硅微电极的金属暴露位点的几何尺寸.优化设计了硅微电极的几何结构,以便于减小植入损伤.阻抗测试结果表明,当测试电压为50mVpp时,1kHz频率下,微电极的单通道阻抗为2.3MQ,适用于神经电信号记录.在体实验结果表明,动物初级视皮层记录到的神经电信号幅度为8μV.%An implantable seven-channel silicon microelectrode was fabricated by MEMS (micro-electro-mechanical system) micromachining techniques for optic-nerve visual prosthesis applications. Theoretical analyses of noise contributed to determining the size of the exposed recording sites of the microprobe. The geometry configuration was optimized for the ilicon microprobe to have enough strength and flexibility and to reduce the insertion-induced tissue trauma. Impedance test results showed that the average value of the channels was 2.3MΩ at 1kHz when applied with a stimulating voltage with the amplitude of 50mVpp,which is suitable for neural signal recordings. In-vivo animal experiment showed that the recorded neural signal amplitude from the primary visual cortex was 8μV.

  1. The doping concentration and physical properties measurement of silicon water using tera hertz wave

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sung Hyeon; Oh, Gyung Hwan; Kim, Hak Sung [Dept. of Mechanical Convergence Engineering, Hanyang University, Seoul(Korea, Republic of)

    2017-02-15

    In this study, a tera hertz time domain spectroscopy (THz-TDS) imaging technique was used to measure doping concentration and physical properties (such as refractive index and permittivity) of the doped silicon (Si) wafers. The transmission and reflection modes with an incidence angle of 30° were employed to determine the physical properties of the doped Si wafers. The doping concentrations of the prepared Si wafers were varied from 10{sup 14} to 10{sup 18} in both N-type and P-type cases. Finally, the correlation between the doping concentration and the power of the THz wave was determined by measuring the powers of the transmitted and reflected THz waves of the doped Si wafers. Additionally, the doped thickness, the refractive index, and permittivity of each doped Si wafer were calculated using the THz time domain waveform. The results indicate that the THz-TDS imaging technique is potentially a promising technique to measure the doping concentration as well as other optical properties (such as the refractive index and permittivity) of the doped Si wafer.

  2. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Science.gov (United States)

    Heib, F.; Hempelmann, R.; Munief, W. M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-07-01

    Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θa and the receding θr contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis relative to the first boundary points XB,10. Therefore, sessile drops during the inclination of the sample surface are video recorded and different specific contact angle events in dependence on the acceleration/deceleration of the triple line motion are analyzed. This procedure results in characteristically density distributions in dependence on the surface properties. The used procedures lead to the possibility to investigate influences on contact

  3. Novel Scheme of Amorphous/Crystalline Silicon Heterojunction Solar Cell

    Energy Technology Data Exchange (ETDEWEB)

    De Iuliis, S.; Geerligs, L.J. [ECN Solar Energy, Petten (Netherlands); Tucci, M.; Serenelli, L.; Salza, E. [ENEA Research Center Casaccia, Roma (Italy); De Cesare, G.; Caputo, D.; Ceccarelli, M. [University ' Sapienza' , Department of Electronic Engineering, Roma (Italy)

    2007-01-15

    In this paper we investigate in detail how the heterostructure concept can be implemented in an interdigitated back contact solar cell, in which both the emitters are formed on the back side of the c-Si wafer by amorphous/crystalline silicon heterostructure, and at the same time the grid-less front surface is passivated by a double layer of amorphous silicon and silicon nitride, which also provides an anti-reflection coating. The entire process, held at temperature below 300C, is photolithography-free, using a metallic self-aligned mask to create the interdigitated pattern, and we show that the alignment is feasible. An open-circuit voltage of 687 mV has been measured on a p-type monocrystalline silicon wafer. The mask-assisted deposition process does not influence the uniformity of the deposited amorphous silicon layers. Photocurrent limits factor has been investigated with the aid of one-dimensional modeling and quantum efficiency measurements. On the other hand several technological aspects that limit the fill factor and the short circuit current density still need improvements.

  4. Silicon micro-mold

    Science.gov (United States)

    Morales, Alfredo M.

    2006-10-24

    The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

  5. Surface property modification of silicon

    Science.gov (United States)

    Danyluk, S.

    1984-01-01

    The main emphasis of this work has been to determine the wear rate of silicon in fluid environments and the parameters that influence wear. Three tests were carried out on single crystal Czochralski silicon wafers: circular and linear multiple-scratch tests in fluids by a pyramidal diamond simulated fixed-particle abrasion; microhardness and three-point bend tests were used to determine the hardness and fracture toughness of abraded silicon and the extent of damage induced by abrasion. The wear rate of (100) and (111) n and p-type single crystal Cz silicon abraded by a pyramidal diamond in ethanol, methanol, acetone and de-ionized water was determined by measuring the cross-sectional areas of grooves of the circular and linear multiple-scratch tests. The wear rate depends on the loads on the diamond and is highest for ethanol and lowest for de-ionized water. The surface morphology of the grooves showed lateral and median cracks as well as a plastically deformed region. The hardness and fracture toughness are critical parameters that influence the wear rate. Microhardness tests were conducted to determine the hardness as influenced by fluids. Median cracks and the damage zone surrounding the indentations were also related to the fluid properties.

  6. One step automated unpatterned wafer defect detection and classification

    Science.gov (United States)

    Dou, Lie; Kesler, Daniel; Bruno, William; Monjak, Charles; Hunt, Jim

    1998-11-01

    Automated detection and classification of crystalline defects on micro-grade silicon wafers is extremely important for integrated circuit (IC) device yield. High training cost, limited capability of classifying defects, increasing possibility of contamination, and unexpected human mistakes necessitate the need to replace the human visual inspection with automated defect inspection. The Laser Scanning Surface Inspection Systems (SSISs) equipped with the Reconvergent Specular Detection (RSD) apparatus are widely used for final wafer inspection. RSD, more commonly known as light channel detection (LC), is capable of detecting and classifying material defects by analyzing information from two independent phenomena, light scattering and reflecting. This paper presents a new technique including a new type of light channel detector to detect and classify wafer surface defects such as slipline dislocation, Epi spikes, Pits, and dimples. The optical system to study this technique consists of a particle scanner to detect and quantify light scattering events from contaminants on the wafer surface and a RSD apparatus (silicon photo detector). Compared with the light channel detector presently used in the wafer fabs, this new light channel technique provides higher sensitivity for small defect detection and more defect scattering signatures for defect classification. Epi protrusions (mounds and spikes), slip dislocations, voids, dimples, and some other common defect features and contamination on silicon wafers are studied using this equipment. The results are compared quantitatively with that of human visual inspection and confirmed by microscope or AFM. This new light channel technology could provide the real future solution to the wafer manufacturing industry for fully automated wafer inspection and defect characterization.

  7. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  8. Within-wafer CD variation induced by wafer shape

    Science.gov (United States)

    Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

    2016-03-01

    In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

  9. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  10. Porous silicon photonic devices using pulsed anodic etching of lightly doped silicon

    Energy Technology Data Exchange (ETDEWEB)

    Escorcia-Garcia, J; Sarracino MartInez, O; Agarwal, V [CIICAP-Universidad Autonoma del Estado de Morelos, Av. Universidad 1001, Col Chamilpa, CP 62210, Cuernavaca, Morelos (Mexico); Gracia-Jimenez, J M, E-mail: vagarwal@uaem.m [Instituto de Fisica, BUAP, Apdo. Postal J-48, San Manuel, 72570 Puebla, Puebla (Mexico)

    2009-07-21

    The fabrication of porous silicon photonic structures using lightly doped, p-type, silicon wafers (resistivity: 14-22 OMEGA cm) by pulsed anodic etching is reported. The optical properties have been found to be strongly dependent on the duty cycle and frequency of the applied current. All the interfaces of the single layered samples were digitally analysed by calculating the mean interface roughness (R{sub m}). The interface roughness was found to be maximum for the sample with direct current. The use of a duty cycle above 50%, in a certain range of frequencies, is found to reduce the interface roughness. The optical properties of some microcavities and rugate filters are investigated from the optimized parameters of the duty cycle and frequency, using the current densities of 10, 90 and 150 mA cm{sup -2}.

  11. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    Science.gov (United States)

    Xianglong, Zhu; Renke, Kang; Zhigang, Dong; Guang, Feng

    2011-10-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (>= 300 mm) silicon wafers for integrated circuits. It is important, but insufficiently studied, to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables. In this paper, the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed. A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed. Based on the proposed configuration, an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward. The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived. The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  12. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released

  13. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released t

  14. Lithographically patterned silicon nanostructures on silicon substrates

    Energy Technology Data Exchange (ETDEWEB)

    Megouda, Nacera [Institut de Recherche Interdisciplinaire (IRI, USR 3078), Universite Lille1, Parc de la Haute Borne, 50 Avenue de Halley-BP 70478, 59658 Villeneuve d' Ascq and Institut d' Electronique, de Microelectronique et de Nanotechnologie (IEMN, CNRS-8520), Cite Scientifique, Avenue Poincare-B.P. 60069, 59652 Villeneuve d' Ascq (France); Faculte des Sciences, Universite Mouloud Mammeri, Tizi-Ouzou (Algeria); Unite de Developpement de la Technologie du Silicium (UDTS), 2 Bd. Frantz Fanon, B.P. 140 Alger-7 merveilles, Alger (Algeria); Piret, Gaeelle; Galopin, Elisabeth; Coffinier, Yannick [Institut de Recherche Interdisciplinaire (IRI, USR 3078), Universite Lille1, Parc de la Haute Borne, 50 Avenue de Halley-BP 70478, 59658 Villeneuve d' Ascq and Institut d' Electronique, de Microelectronique et de Nanotechnologie (IEMN, CNRS-8520), Cite Scientifique, Avenue Poincare-B.P. 60069, 59652 Villeneuve d' Ascq (France); Hadjersi, Toufik, E-mail: hadjersi@yahoo.com [Unite de Developpement de la Technologie du Silicium (UDTS), 2 Bd. Frantz Fanon, B.P. 140 Alger-7 merveilles, Alger (Algeria); Elkechai, Omar [Faculte des Sciences, Universite Mouloud Mammeri, Tizi-Ouzou (Algeria); and others

    2012-06-01

    The paper reports on controlled formation of silicon nanostructures patterns by the combination of optical lithography and metal-assisted chemical dissolution of crystalline silicon. First, a 20 nm-thick gold film was deposited onto hydrogen-terminated silicon substrate by thermal evaporation. Gold patterns (50 {mu}m Multiplication-Sign 50 {mu}m spaced by 20 {mu}m) were transferred onto the silicon wafer by means of photolithography. The etching process of crystalline silicon in HF/AgNO{sub 3} aqueous solution was studied as a function of the silicon resistivity, etching time and temperature. Controlled formation of silicon nanowire arrays in the unprotected areas was demonstrated for highly resistive silicon substrate, while silicon etching was observed on both gold protected and unprotected areas for moderately doped silicon. The resulting layers were characterized using scanning electron microscopy (SEM).

  15. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Energy Technology Data Exchange (ETDEWEB)

    Heib, F., E-mail: f.heib@mx.uni-saarland.de [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Hempelmann, R. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Munief, W.M.; Ingebrandt, S. [Department of Informatics and Microsystem Technology, University of Applied Sciences, Kaiserslautern, 66482 Zweibrücken (Germany); Fug, F.; Possart, W. [Department of Adhesion and Interphases in Polymers, Saarland University, 66123 Saarbrücken (Germany); Groß, K.; Schmitt, M. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany)

    2015-07-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ{sub a} and the receding θ{sub r} contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple

  16. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    Science.gov (United States)

    1989-12-01

    M1 F. 1 . Schematic of thle ge oral I wo-concltict or con figutrat ion .. .. .. .... F- 7 1 .2. S( hevin a t I c of thle general t.wo-condltct or con...G.5. Measured chtaracter’ist ic ImpJedlance of St ructutre (G5 fromi Ill’ [)IQ\\ VIh (ceniter conduictor). (a) Niagnit tide. (1)) Ph1ase

  17. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, Vincent L.; Berenschot, J.W.; Elwenspoek, Miko; Fluitman, Jan H.J

    1995-01-01

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a w

  18. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  19. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  20. Porous silicon gettering

    Energy Technology Data Exchange (ETDEWEB)

    Tsuo, Y.S.; Menna, P.; Al-Jassim, M. [National Renewable Energy Lab., Golden, CO (United States)] [and others

    1995-08-01

    We have studied a novel extrinsic gettering method that utilizes the very large surface areas, produced by porous silicon etch on both front and back surfaces of the silicon wafer, as gettering sites. In this method, a simple and low-cost chemical etching is used to generate the porous silicon layers. Then, a high-flux solar furnace (HFSF) is used to provide high-temperature annealing and the required injection of silicon interstitials. The gettering sites, along with the gettered impurities, can be easily removed at the end the process. The porous silicon removal process consists of oxidizing the porous silicon near the end the gettering process followed by sample immersion in HF acid. Each porous silicon gettering process removes up to about 10 {mu}m of wafer thickness. This gettering process can be repeated so that the desired purity level is obtained.

  1. Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

    NARCIS (Netherlands)

    Vermeer, Rolf; Berenschot, Erwin; Sarajlic, Edin; Tas, Niels; Jansen, Henri

    2014-01-01

    In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using (111) silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom surface enclosed by th

  2. Evolution of plant P-type ATPases

    Directory of Open Access Journals (Sweden)

    Christian N.S. Pedersen

    2012-02-01

    Full Text Available Five organisms having completely sequenced genomes and belonging to all major branches of green plants (Viridiplantae were analyzed with respect to their content of P-type ATPases encoding genes. These were the chlorophytes Ostreococcus tauria and Chlamydomonas reinhardtii, and the streptophytes Physcomitrella patens (a moss, Selaginella moellendorffii (a primitive vascular plant, and Arabidopsis thaliana (a model flowering plant. Each organism contained sequences for all five subfamilies of P-type ATPases. Our analysis demonstrates when specific subgroups of P-type ATPases disappeared in the evolution of Angiosperms. Na/K-pump related P2C ATPases were lost with the evolution of streptophytes whereas Na+ or K+ pumping P2D ATPases and secretory pathway Ca2+-ATPases remained until mosses. An N-terminally located calmodulin binding domain in P2B ATPases can only be detected in pumps from Streptophytae, whereas, like in animals, a C-terminally localized calmodulin binding domain might be present in chlorophyte P2B Ca2+-ATPases. Chlorophyte genomes encode P3A ATPases resembling protist plasma membrane H+-ATPases and a C-terminal regulatory domain is missing. The complete inventory of P-type ATPases in the major branches of Viridiplantae is an important starting point for elucidating the evolution in plants of these important pumps.

  3. Strategy optimization for mask rule check in wafer fab

    Science.gov (United States)

    Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

    2015-07-01

    Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

  4. Effect of surfactant on removal of particle contamination on Si wafers in ULSI

    Institute of Scientific and Technical Information of China (English)

    TAN Bai-mei; LI Wei-wei; NIU Xin-huan; WANG Sheng-li; LIU Yu-ling

    2006-01-01

    The adsorption mechanism of particle on the surface of silicon wafer after polishing or grinding whose surface force field is very strong was discussed,and the removal method of particle was studied. Particle is deposited on the wafer surface by interactions,mainly including the Van der Waals forces and static forces. In order to suppress particles depositing on the wafer surface,it is essential that the wafer surface and the particles should have the same polarity of the zeta potential. According to colloid chemistry and lots of experiments,this can be achieved by adding surfactants. Nonionic complex surfactant was used as megasonic cleaning solution,and the adsorptive state of particle on Si wafers was effectively controlled. The efficiency and effect of megasonic particle removal is greatly improved. A perfect result is also obtained in wafer cleaning.

  5. Wafer-shape based in-plane distortion predictions using superfast 4G metrology

    Science.gov (United States)

    van Dijk, Leon; Mileham, Jeffrey; Malakhovsky, Ilja; Laidler, David; Dekkers, Harold; Van Elshocht, Sven; Anberg, Doug; Owen, David M.; van Haren, Richard

    2017-03-01

    With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent ( 1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

  6. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge;

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  7. Deposited low temperature silicon GHz modulator

    CERN Document Server

    Lee, Yoon Ho Daniel; Lipson, Michal

    2013-01-01

    The majority of silicon photonics is built on silicon-on-insulator (SOI) wafers while the majority of electronics, including CPUs and memory, are built on bulk silicon wafers, limiting broader acceptance of silicon photonics. This discrepancy is a result of silicon photonics's requirement for a single-crystalline silicon (c-Si) layer and a thick undercladding for optical guiding that bulk silicon wafers to not provide. While the undercladding problem can be partially addressed by substrate removal techniques, the complexity of co-integrating photonics with state-of-the-art transistors and real estate competition between electronics and photonics remain problematic. We show here a platform for deposited GHz silicon photonics based on polycrystalline silicon with high optical quality suitable for high performance electro-optic devices. We demonstrate 3 Gbps polysilicon electro-optic modulator fabricated on a deposited polysilicon layer fully compatible with CMOS backend integration. These results open up an arr...

  8. Silicon Heterojunction Solar Cell Characterization and Optimization Using In Situ and Ex Situ Spectroscopic Ellipsometry: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Levi, D.; Iwaniczko, E.; Page, M.; Branz, H.; Wang, T.

    2006-05-01

    We use in-situ and ex-situ spectroscopic ellipsometry to characterize the optical, electronic, and structural properties of individual layers and completed silicon heterojunction devices. The combination of in-situ measurements during thin film deposition with ex-situ measurements of completed devices allows us to understand both the growth dynamics of the materials and the effects of each processing step on material properties. In-situ ellipsometry measurements enable us to map out how the optical properties change with deposition conditions, pointing the way towards reducing the absorption loss and increasing device efficiency. We use the measured optical properties and thickness of the i-, n-, and p-layers in optical device modeling to determine how the material properties affect device performance. Our best solar energy conversion efficiencies are 16.9% for a non-textured, single-sided device with an aluminum back surface field contact on a p-type float zone silicon wafer, and 17.8% for a textured double-sided device on a p-type float zone silicon wafer.

  9. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  10. Hybrid solar cells with conducting polymers and vertically aligned silicon nanowire arrays: The effect of silicon conductivity

    Energy Technology Data Exchange (ETDEWEB)

    Woo, Sungho, E-mail: shwoo@dgist.ac.kr [Green Energy Research Division, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 711-873 (Korea, Republic of); Hoon Jeong, Jae [Green Energy Research Division, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 711-873 (Korea, Republic of); Organic Nanoelectronics Laboratory, Department of Chemical Engineering, Kyungpook National University, Daegu 702-701 (Korea, Republic of); Kun Lyu, Hong; Jeong, Seonju; Hyoung Sim, Jun; Hyun Kim, Wook [Green Energy Research Division, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu 711-873 (Korea, Republic of); Soo Han, Yoon [Department of Advanced Energy Material Science and Engineering, Catholic University of Daegu, Gyeongbuk 712-702 (Korea, Republic of); Kim, Youngkyoo, E-mail: ykimm@knu.ac.kr [Organic Nanoelectronics Laboratory, Department of Chemical Engineering, Kyungpook National University, Daegu 702-701 (Korea, Republic of)

    2012-08-01

    Organic/inorganic hybrid solar cells, based on vertically aligned n-type silicon nanowires (n-Si NWs) and p-type conducting polymers (PEDOT:PSS), were investigated as a function of Si conductivity. The n-Si NWs were easily prepared from the n-Si wafer by employing a silver nanodot-mediated micro-electrochemical redox reaction. This investigation shows that the photocurrent-to-voltage characteristics of the n-Si NW/PEDOT:PSS cells clearly exhibit a stable rectifying diode behavior. The increase in current density and fill factor using high conductive silicon is attributed to an improved charge transport towards the electrodes achieved by lowering the device's series resistance. Our results also show that the surface area of the nanowire that can form heterojunction domains significantly influences the device performance.

  11. Magnetic Czochralski silicon as detector material

    CERN Document Server

    Härkönen, J; Luukka, P; Nordlund, H K; Tuominen, E

    2007-01-01

    The Czochralski silicon (Cz-Si) has intrinsically high oxygen concentration. Therefore Cz-Si is considered as a promising material for the tracking systems in future very high luminosity colliders. In this contribution a brief overview of the Czochralski crystal growth is given. The fabrication process issues of Cz-Si are discussed and the formation of thermal donors is especially emphasized. N+/p−/p+ and p+/n−/n+ detectors have been processed on magnetic Czochralski (MCz-Si) wafers. We show measurement data of AC-coupled strip detectors and single pad detectors as well as experimental results of intentional TD doping. Data of spatial homogeneity of electrical properties, full depletion voltage and leakage current, is shown and n and p-type devices are compared. Our results show that it is possible to manufacture high quality n+/p−/p+ and p+/n−/n+ particle detectors from high-resistivity Cz-Si.

  12. Raw data for 'Spin-on doping of germanium-on-insulator wafers for monolithic light sources on silicon'. Published by Japanese Journal of Applied Physics (JJAP). Copyright 2015 The Japan Society of Applied Physics.

    OpenAIRE

    Al-Attili, Abdelrahman; Kako, Satoshi; Husain, Muhammad; Gardes, Frederic; Arimoto, Hideo; Higashitarumizu, Naoki; Iwamoto, Satoshi; Arakawa, Yasuhiko; Ishikawa, Yasuhiko; Saito, Shinichi

    2015-01-01

    This dataset contains the raw data for spin-on doping experiments of Ge-on-insulator wafers for light emission purposes. Summary of this dataset in the form of figures were published Japanese Journal of Applied Physics (JJAP). Copyright 2015 The Japan Society of Applied Physics.\\ud Citation:\\ud Abdelrahman Zaher Al-Attili, Satoshi Kako, Muhammad K. Husain, Frederic Y. Gardes, Hideo Arimoto, Naoki Higashitarumizu, Satoshi Iwamoto, Yasuhiko Arakawa, Yasuhiko Ishikawa, and Shinichi Saito. "Spin-...

  13. Raw data for 'Spin-on doping of germanium-on-insulator wafers for monolithic light sources on silicon'. Published by Japanese Journal of Applied Physics (JJAP). Copyright 2015 The Japan Society of Applied Physics.

    OpenAIRE

    Al-Attili, Abdelrahman; Kako, Satoshi; Husain, Muhammad; Gardes, Frederic; Arimoto, Hideo; Higashitarumizu, Naoki; Iwamoto, Satoshi; Arakawa, Yasuhiko; Ishikawa, Yasuhiko; Saito, Shinichi

    2015-01-01

    This dataset contains the raw data for spin-on doping experiments of Ge-on-insulator wafers for light emission purposes. Summary of this dataset in the form of figures were published Japanese Journal of Applied Physics (JJAP). Copyright 2015 The Japan Society of Applied Physics. Citation: Abdelrahman Zaher Al-Attili, Satoshi Kako, Muhammad K. Husain, Frederic Y. Gardes, Hideo Arimoto, Naoki Higashitarumizu, Satoshi Iwamoto, Yasuhiko Arakawa, Yasuhiko Ishikawa, and Shinichi Saito. "Spin-...

  14. Influence of experimental parameters on physical properties of porous silicon and oxidized porous silicon layers

    Science.gov (United States)

    Charrier, J.; Alaiwan, V.; Pirasteh, P.; Najar, A.; Gadonna, M.

    2007-08-01

    This paper reports physical properties of porous silicon and oxidized porous silicon, manufactured by anodisation from heavily p-type doped silicon wafers as a function of experimental parameters. The growth rate and refractive index of the layers were studied at different applied current densities and glycerol concentrations in electrolyte. When the current density varied from 5 to 100 mA/cm 2, the refractive index was between 1.2 and 2.4 which corresponded to a porosity range from 42 to 85%. After oxidation, the porosity decreased and was between 2 and 45% for a refractive index range from 1.22 to 1.46. The thermal processing also induced an increase in thickness which was dependent on the initial porosity. This increase in thickness was more important for the lowest porosities. Lastly, the roughness of the porous layer/silicon substrate interface was studied at different applied current densities and glycerol concentrations in solution. Roughness decreased when the current density or glycerol concentration increased. Moreover, roughness was also reduced by thermal oxidation.

  15. P-type transparent conducting oxides

    Science.gov (United States)

    Zhang, Kelvin H. L.; Xi, Kai; Blamire, Mark G.; Egdell, Russell G.

    2016-09-01

    Transparent conducting oxides constitute a unique class of materials combining properties of electrical conductivity and optical transparency in a single material. They are needed for a wide range of applications including solar cells, flat panel displays, touch screens, light emitting diodes and transparent electronics. Most of the commercially available TCOs are n-type, such as Sn doped In2O3, Al doped ZnO, and F doped SnO2. However, the development of efficient p-type TCOs remains an outstanding challenge. This challenge is thought to be due to the localized nature of the O 2p derived valence band which leads to difficulty in introducing shallow acceptors and large hole effective masses. In 1997 Hosono and co-workers (1997 Nature 389 939) proposed the concept of ‘chemical modulation of the valence band’ to mitigate this problem using hybridization of O 2p orbitals with close-shell Cu 3d 10 orbitals. This work has sparked tremendous interest in designing p-TCO materials together with deep understanding the underlying materials physics. In this article, we will provide a comprehensive review on traditional and recently emergent p-TCOs, including Cu+-based delafossites, layered oxychalcogenides, nd 6 spinel oxides, Cr3+-based oxides (3d 3) and post-transition metal oxides with lone pair state (ns 2). We will focus our discussions on the basic materials physics of these materials in terms of electronic structures, doping and defect properties for p-type conductivity and optical properties. Device applications based on p-TCOs for transparent p-n junctions will also be briefly discussed.

  16. MEMS Wafer-level Packaging Technology Using LTCC Wafer

    Science.gov (United States)

    Mohri, Mamoru; Esashi, Masayoshi; Tanaka, Shuji

    This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature co-fired ceramic (LTCC) wafer, in which multi-layer electrical feedthroughs can be embedded. The LTCC wafer allows many kinds of micro electro mechanical systems (MEMS) to be more flexibly designed and more easily packaged. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of thermal shock (-40°C×30min/+125°C×30min) by diaphragm method. To practically apply the LTCC wafer to a variety of MEMS, the electrical connection between MEMS on a Si wafer and feedthroughs in the LTCC should be established by a simple and reliable method. We have developed a new electrical connection methods; The electrical connection is established by porous Au bumps, which are a part of Au vias exposed in wet-etched cavities on the LTCC wafer. 100% yield of both electrical connection and hermetic sealing was demonstrated. A thermal shock test up to 3000 cycles confirmed the reliability of this packaging technology.

  17. Graphene-Al2O3-silicon heterojunction solar cells on flexible silicon substrates

    Science.gov (United States)

    Ahn, Jaehyun; Chou, Harry; Banerjee, Sanjay K.

    2017-04-01

    The quest of obtaining sustainable, clean energy is an ongoing challenge. While silicon-based solar cells have widespread acceptance in practical commercialization, continuous research is important to expand applicability beyond fixed-point generation to other environments while also improving power conversion efficiency (PCE), stability, and cost. In this work, graphene-on-silicon Schottky junction and graphene-insulator-silicon (GIS) solar cells are demonstrated on flexible, thin foils, which utilize the electrical conductivity and optical transparency of graphene as the top transparent contact. Multi-layer graphene was grown by chemical vapor deposition on Cu-Ni foils, followed by p-type doping with Au nanoparticles and encapsulated in poly(methyl methacrylate), which showed high stability with minimal performance degradation over more than one month under ambient conditions. Bendable silicon film substrates were fabricated by a kerf-less exfoliation process based on spalling, where the silicon film thickness could be controlled from 8 to 35 μm based on the process recipe. This method allows for re-exfoliation from the parent Si wafer and incorporates the process for forming the backside metal contact of the solar cell. GIS cells were made with a thin insulating Al2O3 atomic layer deposited film, where the thin Al2O3 film acts as a tunneling barrier for holes, while simultaneously passivating the silicon surface, increasing the minority carrier lifetime from 2 to 27 μs. By controlling the Al2O3 thickness, an optimized cell with 7.4% power conversion efficiency (PCE) on a 35 μm thick silicon absorber was fabricated.

  18. Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

    Science.gov (United States)

    Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

    2011-04-21

    A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

  19. Silicon Field Emission Arrays Coated with CNx Thin Films

    Institute of Scientific and Technical Information of China (English)

    Chen Min-gan; Chen Ming-an; Li Jin-chai; Li Jin-chai; Liu Chuan-sheng; Liu Chuan-sheng; Ma You-peng; Ma You-peng; Lu Xian-feng; Lu Xian-feng; Ye Ming-sheng; Ye Ming-sheng

    2003-01-01

    Arrays of silicon micro-tips were made by etching the p-type (1 0 0) silicon wafers which had SiO2 masks with alkaline solution. The density of the micro-tips is 2 ×104 cm-2. The Scanning Electron Microscope (SEM) photos showed that the tips in these arrays are uniform and orderly.The CNx thin film, with the thickness of 1.27μm was deposited on the silicon micro-tip arrays by using the middle frequency magnetron sputtering technology. The SEM photos showed that the films on the tips are smoothly without particles. Keeping the sharpness of the tips will benefit the properties of field emission. The X-ray photoelectron spectrum (XPS) showed that carbon, nitrogen and oxygen are the three major elements in the surfaces of the films. The percents of them are C: 69.5 %, N: 12.6 % and O: 17.9 %. The silicon arrays coated with CNx thin films had shown a good field emission characterization. The emission current intensity reached 3.2 mA/cm2 at 32.8 V/μm, so it can be put into use. The result showed that the silicon arrays coated with CNx thin films are likely to be good field emission cathode.The preparation and the characterization of the samples were discussed in detail.

  20. Silicon Field Emission Arrays Coated with CNx Thin Films

    Institute of Scientific and Technical Information of China (English)

    ChertMing-an; LiJin-chai; LiuChuan-sheng; MaYou-peng; LuXlan-feng; YeMing-sheng

    2003-01-01

    Arrays of silicon micro-tips were made by etching the p-type (1 0 0) silicon wafers which had SiO2 masks with alkaline solution. The density of the micro-tips is 2 ×104 cm-2. The Scanning Electron Microscope (SEM) photos showed that the tips in these arrays are uniform and orderly.The CNx thin film, with the thickness of 1.27μm was deposited on the silicon micro-tip arrays by using the middle frequency magnetron sputtering technology. The SEM photos showed that the films on the tips are smoothly without particles. Keeping the sharpness of the tips will benefit the properties of field emission. The X-ray photoelectron spectrum (XPS) showed that carbon, nitrogen and oxygen are the three major elements in the surfaces of the films. The percents of them are C: 69.5 %, N: 12. 6 % and O: 17.9 %. The silicon arrays coated with CNx thin films had shown a good field emission characterization. The emission current intensity reached 3. 2 mA/cm2 at 32.8 V/μm, so it can be put into use. The result showed that the silicon arrays coated with CNx thin films are likely to be good field emission cathode.The preparation and the characterization of the samples were discussed in detail.

  1. A Box-through Diffusion Pattern to Reduce the Resistance of the Square Silicon Wafer%一种降低硅片方块电阻方差的通过式扩散方法

    Institute of Scientific and Technical Information of China (English)

    郑荣豪; 陆利新; 肖乐

    2013-01-01

    In order to eliminate the impact of the non-uniformity the square wafer resistance to the performance of the solar cell panel, a box-through diffusion pattern is proposed. First, the structure of a diffusion furnace is designed, the diffusion steps of box-through diffusion pattern are defined while the mathematical model of the relationship between the diffusion time, diffusion temperature , gas flow and the square wafer resistance is established. Secondly, by introduction of statistical sampling method and the establishment of the mathematical model, the square wafer resistance and its variance for each test point are calculated to demonstrate the effectiveness of the method and provide the reference for the improvement of the diffusion process.%为消除方块电阻不均匀性对太阳能电池板性能的影响,提出了一种通过式扩散方法.首先,设计了扩散炉结构,定义了通过式扩散方法的扩散步骤,并建立了方块电阻和扩散时间、扩散温度以及气体流量的关系的数学模型.其次,采用抽样统计方法,通过建立数学模型,计算各测试点的方块电阻及其方差,验证了该方法的有效性,为扩散工艺的改善提供借鉴.

  2. Selective low temperature microcap packaging technique through flip chip and wafer level alignment

    Science.gov (United States)

    Pan, C. T.

    2004-04-01

    In this study, a new technique of selective microcap bonding for packaging 3-D MEMS (Micro Electro Mechanical Systems) devices is presented. Microcap bonding on a selected area of the host wafer was successfully demonstrated through flip chip and wafer level alignment. A passivation treatment was developed to separate the microcap from the carrier wafer. A thick metal nickel (Ni) microcap was fabricated by an electroplating process. Its stiffness is superior to that of thin film poly-silicon made by the surface micromachining technique. For the selective microcap packaging process, photo definable materials served as the intermediate adhesive layer between the host wafer and the metal microcap on the carrier wafer. Several types of photo definable material used as the adhesive layer were tested and characterized for bonding strength. The experimental result shows that excellent bonding strength at low bonding temperature can be achieved.

  3. Infrared spectroscopy of wafer-scale graphene.

    Science.gov (United States)

    Yan, Hugen; Xia, Fengnian; Zhu, Wenjuan; Freitag, Marcus; Dimitrakopoulos, Christos; Bol, Ageeth A; Tulevski, George; Avouris, Phaedon

    2011-12-27

    We report spectroscopy results from the mid- to far-infrared on wafer-scale graphene, grown either epitaxially on silicon carbide or by chemical vapor deposition. The free carrier absorption (Drude peak) is simultaneously obtained with the universal optical conductivity (due to interband transitions) and the wavelength at which Pauli blocking occurs due to band filling. From these, the graphene layer number, doping level, sheet resistivity, carrier mobility, and scattering rate can be inferred. The mid-IR absorption of epitaxial two-layer graphene shows a less pronounced peak at 0.37 ± 0.02 eV compared to that in exfoliated bilayer graphene. In heavily chemically doped single-layer graphene, a record high transmission reduction due to free carriers approaching 40% at 250 μm (40 cm(-1)) is measured in this atomically thin material, supporting the great potential of graphene in far-infrared and terahertz optoelectronics.

  4. Impact of interstitial oxygen trapped in silicon during plasma growth of silicon oxy-nitride films for silicon solar cell passivation

    Science.gov (United States)

    Saseendran, Sandeep S.; Saravanan, S.; Raval, Mehul C.; Kottantharayil, Anil

    2016-03-01

    Low temperature oxidation of silicon in plasma ambient is a potential candidate for replacing thermally grown SiO2 films for surface passivation of crystalline silicon solar cells. In this work, we report the growth of silicon oxy-nitride (SiOxNy) film in N2O plasma ambient at 380 °C. However, this process results in trapping of interstitial oxygen within silicon. The impact of this trapped interstitial oxygen on the surface passivation quality is investigated. The interstitial oxygen trapped in silicon was seen to decrease for larger SiOxNy film thickness. Effective minority carrier lifetime (τeff) measurements on n-type float zone silicon wafers passivated by SiOxNy/silicon nitride (SiNv:H) stack showed a decrease in τeff from 347 μs to 68 μs, for larger SiOxNy film thickness due to degradation in interface properties. From high frequency capacitance-voltage measurements, it was concluded that the surface passivation quality was governed by the interface parameters (fixed charge density and interface state density). High temperature firing of the SiOxNy/SiNv:H stack resulted in a severe degradation in τeff due to migration of oxygen across the interface into silicon. However, on using the SiOxNy/SiNv:H stack for emitter surface passivation in screen printed p-type Si solar cells, an improvement in short wavelength response was observed in comparison to the passivation by SiNv:H alone, indicating an improvement in emitter surface passivation quality.

  5. Silicon Sensor and Detector Developments for the CMS Tracker Upgrade

    CERN Document Server

    D'Alessandro, Raffaello

    2011-01-01

    CMS started a campaign to identify the future silicon sensor technology baseline for a new Tracker for the high-luminosity phase of LHC, coupled to a new effective way of providing tracking information to the experiment trigger. To this end a large variety of 6'' wafers was acquired in different thicknesses and technologies at HPK and new detector module designs were investigated. Detector thicknesses ranging from 50$\\mu$m to 300$\\mu$m are under investigation on float zone, magnetic Czochralski and epitaxial material both in n-in-p and p-in-n versions. P-stop and p-spray are explored as isolation technology for the n-in-p type sensors as well as the feasibility of double metal routing on 6'' wafers. Each wafer contains different structures to answer different questions, e.g. influence of geometry, Lorentz angle, radiation tolerance, annealing behaviour, validation of read-out schemes. Dedicated process test-structures, as well as diodes, mini-sensors, long and very short strip sensors and real pixel sensors ...

  6. Effect of low segregation coefficient on Ga-doped multicrystalline silicon solar cell performance

    Energy Technology Data Exchange (ETDEWEB)

    Dhamrin, Marwan; Kamisako, Koichi; Saitoh, Tadashi [Tokyo University of Agriculture and Technology, Tokyo (Japan); Eguchi, Takeshi; Hirasawa, Teruhiko; Yamaga, Isao [Dai-ichi Kiden Co., Tokyo (Japan)

    2005-11-15

    High-quality Ga-doped ingots are grown in different casting furnaces at optimized growth parameters; 3.5 kg ingots exhibit normal distribution of diffusion lengths along their height with very high diffusion lengths at the center of the ingot. Effective lifetimes as high as 1.1 ms are realized in 10 {omega} cm Ga-doped wafers after proper P-diffusion and hydrogen passivation. Average effective lifetimes above 400 {mu}s are also realized after P-diffusion and hydrogen passivation for Ga-doped wafers cut from 75 kg ingot where the response to P-diffusion and hydrogen passivation is pronounced. High effective lifetimes are realized over the whole ingot with minimum values of 20 {mu}s at the top of the ingot, indicating the possible use of about 85% of the ingot for solar cell production. Conversion efficiencies above 15.5% were realized in utilizing more than 80% of the ingot. High efficiencies of about 16% were realized in wafers with resistivities higher than 5 {omega} cm p-type multicrystalline silicon wafers. (Author)

  7. Hybrid Integrated Platforms for Silicon Photonics

    Directory of Open Access Journals (Sweden)

    John E. Bowers

    2010-03-01

    Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  8. Silicon Holder For Molecular-Beam Epitaxy

    Science.gov (United States)

    Hoenk, Michael E.; Grunthaner, Paula J.; Grunthaner, Frank J.

    1993-01-01

    Simple assembly of silicon wafers holds silicon-based charge-coupled device (CCD) during postprocessing in which silicon deposited by molecular-beam epitaxy. Attains temperatures similar to CCD, so hotspots suppressed. Coefficients of thermal expansion of holder and CCD equal, so thermal stresses caused by differential thermal expansion and contraction do not develop. Holder readily fabricated, by standard silicon processing techniques, to accommodate various CCD geometries. Silicon does not contaminate CCD or molecular-beam-epitaxy vacuum chamber.

  9. Characterization of electrical and optical properties of silicon based materials

    Energy Technology Data Exchange (ETDEWEB)

    Jia, Guobin

    2009-12-04

    characteristic DRL lines D1 to D4 has been detected, indicating the dislocations in the Alile sample are relatively clean. Test p-n junction diodes with dislocation networks (DNs) produced by silicon wafer direct bonding have been investigated by EBIC technique. Charge carriers collection and electrical conduction phenomena by the DNs were observed. Inhomogeneities in the charge collection were detected in n- and p-type samples under appropriate beam energy. The diffusion lengths in the thin top layer of silicon-on-insulator (SOI) have been measured by EBIC with full suppression of the surface recombination at the buried oxide (BOX) layer and at surface of the top layer by biasing method. The measured diffusion length is several times larger than the layer thickness. Silicon nanostructures are another important subject of this work. Electrical and optical properties of various silicon based materials like silicon nanowires, silicon nano rods, porous silicon, and Si/SiO{sub 2} multi quantum wells (MQWs) samples were investigated in this work. Silicon sub-bandgap infrared (IR) luminescence around 1570 nm was found in silicon nanowires, nano rods and porous silicon. PL measurements with samples immersed in different liquid media, for example, in aqueous HF (50%), concentrated H{sub 2}SO{sub 4} (98%) and H{sub 2}O{sub 2} established that the subbandgap IR luminescence originated from the Si/SiO{sub x} interface. EL in the sub-bandgap IR range has been observed in simple devices prepared on porous silicon and MQWs at room temperature. (orig.)

  10. Synthesis of buried silicon oxynitride layers by ion implantation for silicon-on-insulator (SOI) structures

    Energy Technology Data Exchange (ETDEWEB)

    Yadav, A.D. [Department of Physics, University of Mumbai, Vidyanagari Campus, Santacruz (E), Mumbai 400 098 (India)]. E-mail: adyadav@physics.mu.ac.in; Polji, Rucha H. [Department of Physics, University of Mumbai, Vidyanagari Campus, Santacruz (E), Mumbai 400 098 (India); Singh, Vibha [Department of Physics, University of Mumbai, Vidyanagari Campus, Santacruz (E), Mumbai 400 098 (India); Dubey, S.K. [Department of Physics, University of Mumbai, Vidyanagari Campus, Santacruz (E), Mumbai 400 098 (India); Gundu Rao, T.K. [Regional Sophisticated Instrumentation Center, IIT Bombay, Powai, Mumbai 400 076 (India)

    2006-04-15

    Silicon oxynitride (Si {sub x}O {sub y}N {sub z}) buried insulating layers were synthesized by SIMNOX (separation by implanted nitrogen-oxygen) process by {sup 14}N{sup +} and {sup 16}O{sup +} ion implantation to high fluence levels 1 x 10{sup 17}, 2.5 x 10{sup 17} and 5 x 10{sup 17} ions cm{sup -2} sequentially in the ratio 1:1 at 150 keV into p-type (1 0 0) silicon wafers. The identification of structures and defects in the ion beam synthesized buried layers were carried out by FTIR, XRD and ESR measurements before and after RTA treatments at different temperatures in nitrogen ambient. The FTIR spectra show single broad absorption band in the wavenumber range 1250-600 cm{sup -1} confirming the formation of silicon oxynitride. The integrated absorption band intensity is found to increase with increasing ion fluence and on annealing indicating gradual chemical transformation of the ion implanted layer into silicon oxynitride. The XRD data of the implanted samples show the formation of Si{sub 2}N{sub 2}O (O) phase of silicon oxynitride. On annealing the samples, SiO{sub 2} (H)/Si{sub 3}N{sub 4} (H) phases are also formed in addition to Si{sub 2}N{sub 2}O (O) phase. The concentration of the formed phases is found to increase with increase in the ion fluence as well as the annealing temperature. The ESR studies both at room temperature and at low temperatures reveal the presence of a defect center associated with silicon dangling bonds. The increase in ion fluence gives rise to small variations in g-values and increase in the spin density. The spin density decreases in general with increasing the annealing temperature.

  11. Characterization of wafer-level bonded hermetic packages using optical leak detection

    Science.gov (United States)

    Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

    2009-07-01

    For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

  12. Glass-silicon column

    Energy Technology Data Exchange (ETDEWEB)

    Yu, Conrad M.

    2003-12-30

    A glass-silicon column that can operate in temperature variations between room temperature and about 450.degree. C. The glass-silicon column includes large area glass, such as a thin Corning 7740 boron-silicate glass bonded to a silicon wafer, with an electrode embedded in or mounted on glass of the column, and with a self alignment silicon post/glass hole structure. The glass/silicon components are bonded, for example be anodic bonding. In one embodiment, the column includes two outer layers of silicon each bonded to an inner layer of glass, with an electrode imbedded between the layers of glass, and with at least one self alignment hole and post arrangement. The electrode functions as a column heater, and one glass/silicon component is provided with a number of flow channels adjacent the bonded surfaces.

  13. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  14. Development of laser-fired contacts for amorphous silicon layers obtained by Hot-Wire CVD

    Energy Technology Data Exchange (ETDEWEB)

    Munoz, D. [XaRMAE-Universitat de Barcelona, Departament de Fisica Aplicada i Optica, Diagonal 647, Barcelona 08028 (Spain)], E-mail: delfina@eel.upc.edu; Voz, C.; Blanque, S. [Universitat Politecnica de Catalunya, Grup de Recerca en Micro i Nanotecnologies, Jordi Girona 1-3, Barcelona 08034 (Spain); Ibarz, D.; Bertomeu, J. [XaRMAE-Universitat de Barcelona, Departament de Fisica Aplicada i Optica, Diagonal 647, Barcelona 08028 (Spain); Alcubilla, R. [Universitat Politecnica de Catalunya, Grup de Recerca en Micro i Nanotecnologies, Jordi Girona 1-3, Barcelona 08034 (Spain)

    2009-03-15

    In this work we study aluminium laser-fired contacts for intrinsic amorphous silicon layers deposited by Hot-Wire CVD. This structure could be used as an alternative low temperature back contact for rear passivated heterojunction solar cells. An infrared Nd:YAG laser (1064 nm) has been used to locally fire the aluminium through the thin amorphous silicon layers. Under optimized laser firing parameters, very low specific contact resistances ({rho}{sub c} {approx} 10 m{omega} cm{sup 2}) have been obtained on 2.8 {omega} cm p-type c-Si wafers. This investigation focuses on maintaining the passivation quality of the interface without an excessive increase in the series resistance of the device.

  15. The Development of High-Density Vertical Silicon Nanowires and Their Application in a Heterojunction Diode

    Directory of Open Access Journals (Sweden)

    Wen-Chung Chang

    2016-06-01

    Full Text Available Vertically aligned p-type silicon nanowire (SiNW arrays were fabricated through metal-assisted chemical etching (MACE of Si wafers. An indium tin oxide/indium zinc oxide/silicon nanowire (ITO/IZO/SiNW heterojunction diode was formed by depositing ITO and IZO thin films on the vertically aligned SiNW arrays. The structural and electrical properties of the resulting ITO/IZO/SiNW heterojunction diode were characterized by field emission scanning electron microscopy (FE-SEM, X-ray diffraction (XRD, and current−voltage (I−V measurements. Nonlinear and rectifying I−V properties confirmed that a heterojunction diode was successfully formed in the ITO/IZO/SiNW structure. The diode had a well-defined rectifying behavior, with a rectification ratio of 550.7 at 3 V and a turn-on voltage of 2.53 V under dark conditions.

  16. High-efficiency silicon heterojunction solar cells: Status and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    De Wolf, S.

    2015-04-27

    Silicon heterojunction technology (HJT) uses silicon thin-film deposition techniques to fabricate photovoltaic devices from mono-crystalline silicon wafers (c-Si). This enables energy-conversion efficiencies above 21 %, also at industrial-production level. In this presentation we review the present status of this technology and point out recent trends. We first discuss how the properties of thin hydrogenated amorphous silicon (a-Si:H) films can be exploited to fabricate passivating contacts, which is the key to high- efficiency HJT solar cells. Such contacts enable very high operating voltages, approaching the theoretical limits, and yield small temperature coefficients. With this approach, an increasing number of groups are reporting devices with conversion efficiencies well over 20 % on n-type wafers, Panasonic leading the field with 24.7 %. Exciting results have also been obtained on p-type wafers. Despite these high voltages, important efficiency gains can still be made in fill factor and optical design. This requires improved understanding of carrier transport across device interfaces and reduced parasitic absorption in HJT solar cells. For the latter, several strategies can be followed: Short- wavelength losses can be reduced by replacing the front a-Si:H films with wider-bandgap window layers, such as silicon alloys or even metal oxides. Long-wavelength losses are mitigated by introducing new high-mobility TCO’s such as hydrogenated indium oxide, and also by designing new rear reflectors. Optical shadow losses caused by the front metalisation grid are significantly reduced by replacing printed silver electrodes with fine-line plated copper contacts, leading also to possible cost advantages. The ultimate approach to minimize optical losses is the implementation of back-contacted architectures, which are completely devoid of grid shadow losses and parasitic absorption in the front layers can be minimized irrespective of electrical transport requirements. The

  17. TiO₂-coated carbon nanotube-silicon solar cells with efficiency of 15

    National Research Council Canada - National Science Library

    Shi, Enzheng; Zhang, Luhui; Li, Zhen; Li, Peixu; Shang, Yuanyuan; Jia, Yi; Wei, Jinquan; Wang, Kunlin; Zhu, Hongwei; Wu, Dehai; Zhang, Sen; Cao, Anyuan

    2012-01-01

    Combining carbon nanotubes (CNTs), graphene or conducting polymers with conventional silicon wafers leads to promising solar cell architectures with rapidly improved power conversion efficiency until recently...

  18. 银纳米颗粒/多孔硅复合材料的制备与气敏性能研究∗%Preparation and gas-sensing prop erties of the silver nanoparticles/p orous silicon comp osite

    Institute of Scientific and Technical Information of China (English)

    严达利; 李申予; 刘士余; 竺云

    2015-01-01

    The p-type porous silicon layer with the aperture about 1.5 microns and hole depth about 15–20 microns is prepared by electrochemical etching of a p-type monocrystalline silicon wafer with a resistivity 10–15 Ω·cm and along [100] orientation in a double-tank cell which consists of the electrolyte (volume ratio HF: DMF=1 : 2). Silver nanoparticles film with different thickness has been deposited on porous silicon by the electroless deposition for different deposition times. Morphology and microstructure of the silver nanoparticles/porous silicon composite are studied by scanning electron microscope and X ray diffracmeter. Result indicates that the silver nanoparticles are uniformly distributed on the surface of porous silicon and the deposition time has an important influence on the morphology of the composite. The gas-sensing properties of the silver nanoparticles/porous silicon composite to NH3 are tested at room temperature by the static volumetric method. Results show that the deposition time has a significant impact on the gas-sensing properties of the silver nanoparticles/porous silicon. In a short deposition time, the composite with an appropriate amount of silver nanoparticles doped on the porous silicon shows good gas-sensing properties to NH3 with high sensitivity, fast response-recovery characteristic due to the high specific surface area and special microstructure. At room temperature, the gas sensor has a sensitivity of about 5.8 to 50 ppm NH3.

  19. Reaction of porous silicon with both end-functionalized organic compounds bearing alpha-bromo and omega-carboxy groups for immobilization of biomolecules.

    Science.gov (United States)

    Guo, Dong-Jie; Xiao, Shou-Jun; Xia, Bing; Wei, Shuai; Pei, Jia; Pan, Yi; You, Xiao-Zeng; Gu, Zhong-Ze; Lu, Zuhong

    2005-11-03

    Both end-functionalized (alpha-bromo and omega-carboxy) compounds were first tested for the radical reaction on the silicon-hydride (Si-H) terminated porous silicon (PSi) with/without the presence of diacyl peroxide initiator under microwave irradiation. Then the carboxylic acid monolayers (CAMs) assembled on PSi through the robust Si-C bonds were converted to amino-reactive linker, N-hydroxysuccinimide (NHS)-ester, terminated monolayers. And finally two proteins of bovine serum albumin (BSA) and lysozyme (Lys) were immobilized through amide bonds. The optimum PSi membrane for protein immobilization without collapse, with parameters of porous radii 4-10 nm and depth 0.2-4.6 mum, was prepared from the (100)-oriented p-type silicon wafer. The chemically converted surface products were monitored with Fourier transform infrared spectroscopy (FTIR), X-ray photoelectron spectroscopy (XPS), and field emission scanning electron microscopy (FESEM).

  20. Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

    Science.gov (United States)

    Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

    2015-11-01

    Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group.

  1. Preparation and Thermal Characterization of Annealed Gold Coated Porous Silicon

    Directory of Open Access Journals (Sweden)

    Afarin Bahrami

    2012-01-01

    Full Text Available Porous silicon (PSi layers were formed on a p-type Si wafer. Six samples were anodised electrically with a 30 mA/cm2 fixed current density for different etching times. The samples were coated with a 50–60 nm gold layer and annealed at different temperatures under Ar flow. The morphology of the layers, before and after annealing, formed by this method was investigated by scanning electron microscopy (SEM. Photoacoustic spectroscopy (PAS measurements were carried out to measure the thermal diffusivity (TD of the PSi and Au/PSi samples. For the Au/PSi samples, the thermal diffusivity was measured before and after annealing to study the effect of annealing. Also to study the aging effect, a comparison was made between freshly annealed samples and samples 30 days after annealing.

  2. Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

    NARCIS (Netherlands)

    Haneveld, Jeroen; Berenschot, Erwin; Maury, Pascale; Jansen, Henri

    2006-01-01

    A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7–20 nm wide, 40–100 nm high and centimeters long. All dimensions are easily a

  3. Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

    NARCIS (Netherlands)

    Haneveld, Jeroen; Berenschot, Erwin; Maury, Pascale; Jansen, Henri

    2005-01-01

    A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily a

  4. Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

    Science.gov (United States)

    Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

    1979-01-01

    The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

  5. Time-varying wetting behavior on copper wafer treated by wet-etching

    Energy Technology Data Exchange (ETDEWEB)

    Tu, Sheng-Hung; Wu, Chuan-Chang [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China); Wu, Hsing-Chen [Advanced Technology Materials Inc, Hsinchu 310, Taiwan, ROC (China); Cheng, Shao-Liang [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China); Sheng, Yu-Jane, E-mail: yjsheng@ntu.edu.tw [Department of Chemical Engineering, National Taiwan University, Taipei 106, Taiwan, ROC (China); Tsao, Heng-Kwong, E-mail: hktsao@cc.ncu.edu.tw [Department of Chemical and Materials Engineering, National Central University, Jhongli 320, Taiwan, ROC (China)

    2015-06-30

    Graphical abstract: - Highlights: • A thin oxide layer always remains on surfaces of Cu wafers after aqueous etching. • A pure Cu wafer is obtained by the HAc treatment and the water CA is about 45°. • The oxide layer and CA grow with time after the Cu wafer is exposed to air. • Surface roughness and hydrophobicity of pure Cu wafers grow rapidly in vacuum. - Abstract: The wet cleaning process in semiconductor fabrication often involves the immersion of the copper wafer into etching solutions and thereby its surface properties are significantly altered. The wetting behavior of a copper film deposited on silicon wafer is investigated after a short dip in various etching solutions. The etchants include glacial acetic acid and dilute solutions of nitric acid, hydrofluoric acid, and tetramethylammonium hydroxide. It was found that in most cases a thin oxide layer still remains on the surface of as-received Cu wafers when they are subject to etching treatments. However, a pure Cu wafer can be obtained by the glacial acetic acid treatment and its water contact angle (CA) is about 45°. As the pure Cu wafer is placed in the ambient condition, the oxide thickness grows rapidly to the range of 10–20 Å within 3 h and the CA on the hydrophilic surface also rises. In the vacuum, it is surprising to find that the CA and surface roughness of the pure Cu wafer can grow significantly. These interesting results may be attributed to the rearrangement of surface Cu atoms to reduce the surface free energy.

  6. High-performance flexible thin-film transistors exfoliated from bulk wafer.

    Science.gov (United States)

    Zhai, Yujia; Mathew, Leo; Rao, Rajesh; Xu, Dewei; Banerjee, Sanjay K

    2012-11-14

    Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal-oxide-semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).

  7. Monocrystalline silicon used for integrated circuits: still on the way

    Institute of Scientific and Technical Information of China (English)

    Jia-he CHEN; De-ren YANG; Duan-lin QUE

    2008-01-01

    With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impur-ities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insu-lator) are reviewed. It is proposed that the silicon man-ufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore's law into a couple of decades.

  8. Surface shape control of the workpiece in a double-spindle triple-workstation wafer grinder

    Institute of Scientific and Technical Information of China (English)

    Zhu Xianglong; Kang Renke; Dong Zhigang; Feng Guang

    2011-01-01

    Double-spindle triple-workstation (DSTW) ultra precision grinders are mainly used in production lines for manufacturing and back thinning large diameter (≥ 300 mm) silicon wafers for integrated circuits.It is important,but insufficiently studied,to control the wafer shape ground on a DSTW grinder by adjusting the inclination angles of the spindles and work tables.In this paper,the requirements of the inclination angle adjustment of the grinding spindles and work tables in DSTW wafer grinders are analyzed.A reasonable configuration of the grinding spindles and work tables in DSTW wafer grinders are proposed.Based on the proposed configuration,an adjustment method of the inclination angle of grinding spindles and work tables for DSTW wafer grinders is put forward.The mathematical models of wafer shape with the adjustment amount of inclination angles for both fine and rough grinding spindles are derived.The proposed grinder configuration and adjustment method will provide helpful instruction for DSTW wafer grinder design.

  9. Design of Remote Monitoring System for Abrasive Electrochemical Multi-wire Sawing Silicon Ingot into Solar Wafers%太阳能硅片电解磨削多线切割远程监控系统的设计

    Institute of Scientific and Technical Information of China (English)

    张霞; 汪炜; 鲍官培; 章恺

    2015-01-01

    为满足太阳能硅片大规模生产的精益化管理需求,针对太阳能硅片电解磨削多线切割工艺特点,设计了一种以C/S为主、B/S为辅的混合式软件架构远程监控系统。采用Visual C#编程实现上、下位机的数据通讯,开发基于工业以太网的车间现场监控模块,通过PHP和MySQL开发基于web的数据查询模块。经长时间试验运行,该系统能实现电解磨削多线切割设备工作状态及加工参数的远程实时监控,稳定可靠,具有重要的工程应用价值。%To meet the demands of lean management for mass production of solar wafers ,a remote monitoring system based on B/S and C/S architectures is designed according to the process characteristics of abrasive electrochemical multi-wire sawing. On the basis of the communication protocols,the monitoring module between master and slave computer is realized by using Visual C#, and the web-based information inquiry module is developed by using PHP and MySQL. It is demonstrated that the working status and machining parameters can be stably and reliably remote monitored with it in long run test,which has significant engineering application prospects.

  10. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    Science.gov (United States)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  11. Effects of cleaning procedures of silica wafers on their friction characteristics.

    Science.gov (United States)

    Donose, Bogdan C; Taran, Elena; Vakarelski, Ivan U; Shinto, Hiroyuki; Higashitani, Ko

    2006-07-01

    Silicon wafers with thermal silicon oxide layers were cleaned and hydrophilized by three different methods: (1) the remote chemical analysis (RCA) wet cleaning by use of ammonia and hydrogen peroxide mixture solutions, (2) water-vapor plasma cleaning, and (3) UV/ozone combined cleaning. All procedures were found to remove effectively organic contaminations on wafers and gave identical characteristics of the contact angle, the surface roughness and the normal force interactions, measured by atomic force microscopy (AFM). However, it is found that wafers cleaned by the RCA method have several times larger friction coefficients than those cleaned by the plasma and UV/ozone methods. The difference was explained by the atomic-scale topological difference induced during the RCA cleaning. This study reveals the lateral force microscopy as a very sensitive method to detect the microstructure of surfaces.

  12. 3D micro-optical lens scanner made by multi-wafer bonding technology

    Science.gov (United States)

    Bargiel, S.; Gorecki, C.; Barański, M.; Passilly, N.; Wiemer, M.; Jia, C.; Frömel, J.

    2013-03-01

    We present the preliminary design, construction and technology of a microoptical, millimeter-size 3-D microlens scanner, which is a key-component for a number of optical on-chip microscopes with emphasis on the architecture of confocal microscope. The construction of the device relies on the vertical integration of micromachined building blocks: top glass lid, silicon electrostatic comb-drive X-Y and Z microactuators with integrated scanning microlenses, ceramic LTCC spacer, and bottom lid with focusing microlens. All components are connected on the wafer level only by sequential anodic bonding. The technology of through wafer vias is applied to create electrical connections through a stack of wafers. More generally, the presented bonding/connection technologies are also of a great importance for the development of various silicon-based devices based on vertical integration scheme. This approach offers a space-effective integration of complex MOEMS devices and an effective integration of various heterogeneous technologies.

  13. A porous silicon thermally tunable optical filter

    Science.gov (United States)

    Song, Da; Tokranova, Natalya; Gracias, Alison; Castracane, James

    2008-02-01

    Porous silicon (PSi) is a promising material for the creation of optical components for chip-to-chip interconnects because of its unique optical properties, flexible fabrication methods and integration with conventional CMOS material sets. In this paper, we present a novel active optical filter made of PSi to select desired optical wavelengths. The tunable membrane type optical filter is based on a Fabry-Perot interferometer employing two Bragg reflectors separated by an adjustable air gap, which can be thermally controlled. The Bragg reflectors contain alternating layers of high and low porosities. These layers were created by electrochemical etching of p+ type silicon wafers by varying the applied current during etching process. Micro bimorph actuators are designed to control the movement of the top DBR mirror, which changes the cavity thickness. By varying the applied current, the proposed filter can tune the transmitted wavelength of the optical signal. Various geometrical shapes and sizes ranging from 100μm to 1mm of the active filtering region have been realized for specific applications. The MOEMS technology-based device fabrication is fully compatible with the existing IC mass fabrication processes, and can be integrated with a variety of active and passive optical components to realize inter-chip or intra-chip communication at the system level at a relatively low cost.

  14. Hybrid silicon evanescent approach to optical interconnects

    OpenAIRE

    Liang, Di; Fang, Alexander W.; Chen, Hui-Wen; Sysak, Matthew N; Koch, Brian R.; Lively, Erica; Raday, Omri; Kuo, Ying-hao; Jones, Richard; Bowers, John E

    2009-01-01

    We discuss the recently developed hybrid silicon evanescent platform (HSEP), and its application as a promising candidate for optical interconnects in silicon. A number of key discrete components and a wafer-scale integration process are reviewed. The motivation behind this work is to realize silicon-based photonic integrated circuits possessing unique advantages of III–V materials and silicon-on-insulator waveguides simultaneously through a complementary metal-oxide semiconductor fabrication...

  15. Silicon photonics manufacturing.

    Science.gov (United States)

    Zortman, William A; Trotter, Douglas C; Watts, Michael R

    2010-11-08

    Most demonstrations in silicon photonics are done with single devices that are targeted for use in future systems. One of the costs of operating multiple devices concurrently on a chip in a system application is the power needed to properly space resonant device frequencies on a system's frequency grid. We asses this power requirement by quantifying the source and impact of process induced resonant frequency variation for microdisk resonators across individual die, entire wafers and wafer lots for separate process runs. Additionally we introduce a new technique, utilizing the Transverse Electric (TE) and Transverse Magnetic (TM) modes in microdisks, to extract thickness and width variations across wafers and dice. Through our analysis we find that a standard six inch Silicon on Insulator (SOI) 0.35 μm process controls microdisk resonant frequencies for the TE fundamental resonances to within 1 THz across a wafer and 105 GHz within a single die. Based on demonstrated thermal tuner technology, a stable manufacturing process exhibiting this level of variation can limit the resonance trimming power per resonant device to 231 μW. Taken in conjunction with the power to compensate for thermal environmental variations, the expected power requirement to compensate for fabrication-induced non-uniformities is 17% of that total. This leads to the prediction that thermal tuning efficiency is likely to have the most dominant impact on the overall power budget of silicon photonics resonator technology.

  16. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  17. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Berenschot, J.W.; Elwenspoek, M.; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique co

  18. Wafer-Scale Leaning Silver Nanopillars for Molecular Detection at Ultra-Low Concentrations

    DEFF Research Database (Denmark)

    Wu, Kaiyu; Rindzevicius, Tomas; Schmidt, Michael Stenbæk;

    2015-01-01

    Wafer-scale surface-enhanced Raman scattering (SERS) substrates fabricated using maskless lithography are important for scalable production targets. Large-area, leaning silver-capped silicon nanopillar (Ag NP) structures suitable for SERS molecular detection at extremely low analyte concentration...

  19. Wafer-level assembly and sealing of a MEMS nanoreactor for in situ microscopy

    NARCIS (Netherlands)

    Mele, L.; Santagata, F.; Panraud, G.; Morana, B.; Tichelaar, F.D.; Creemer, J.F.; Sarro, P.M.

    2010-01-01

    This paper presents a new process for the fabrication of MEMS-based nanoreactors for in situ atomic-scale imaging of nanoparticles under relevant industrial conditions. The fabrication of the device is completed fully at wafer level in an ISO 5 clean room and it is based on silicon fusion bonding

  20. Controllable elastocapillary folding of three-dimensional micro-objects by through-wafer filling

    NARCIS (Netherlands)

    Legrain, A.B.H.; Janson, T.G.; Berenschot, Johan W.; Abelmann, Leon; Tas, Niels Roelof

    2014-01-01

    We present a technique for the controllable capillary folding of planar silicon nitride templates into 3D micro-structures by means of through-wafer liquid application. We demonstrate for the first time hydro-mechanical, repeatable, actuation of capillary folded structures via the addition or

  1. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  2. Deposition uniformity inspection in IC wafer surface

    Science.gov (United States)

    Li, W. C.; Lin, Y. T.; Jeng, J. J.; Chang, C. L.

    2014-03-01

    This paper focuses on the task of automatic visual inspection of color uniformity on the surface of integrated circuits (IC) wafers arising from the layering process. The oxide thickness uniformity within a given wafer with a desired target thickness is of great importance for modern semiconductor circuits with small oxide thickness. The non-uniform chemical vapor deposition (CVD) on a wafer surface will proceed to fail testing in Wafer Acceptance Test (WAT). Early detection of non-uniform deposition in a wafer surface can reduce material waste and improve production yields. The fastest and most low-priced inspection method is a machine vision-based inspection system. In this paper, the proposed visual inspection system is based on the color representations which were reflected from wafer surface. The regions of non-uniform deposition present different colors from the uniform background in a wafer surface. The proposed inspection technique first learns the color data via color space transformation from uniform deposition of normal wafer surfaces. The individual small region statistical comparison scheme then proceeds to the testing wafers. Experimental results show that the proposed method can effectively detect the non-uniform deposition regions on the wafer surface. The inspection time of the deposited wafers is quite compatible with the atmospheric pressure CVD time.

  3. Dry texturing of mc-Si wafers

    Energy Technology Data Exchange (ETDEWEB)

    Agarwal, Garima [ENEA-Casaccia, Rome (Italy); CNER, 14-Vigyan Bhawan, University of Rajasthan, Jaipur (India); De Iuliis, Simona; Serenelli, Luca; Salza, Enrico; Tucci, Mario [ENEA-Casaccia, Rome (Italy)

    2011-03-15

    Texturing of mc-Si is a prevailing research topic to improve solar cell efficiency in production. Surface texturing for enhanced absorption in Si has been historically obtained by creating randomly distributed pyramids using anisotropic etchants; but this preferential etching works only on single crystalline silicon because of its crystallographic orientations. A low-cost, large area, random, mask-less texturing scheme is expected to significantly impact terrestrial PV technology and reduce the amount of wet-chemical waste. We propose an approach based on randomly etched mc-Si by RIE system using NF{sub 3} instead of SF{sub 6} or CF{sub 4} to reduce the detrimental formation of carbonaceous or sulfurous contamination at the silicon surface, which results in a surface recombination. To obtain a fast process we have investigated the effect of the chemical etching due to the NF{sub 3} radicals and the ion bombardment induced by Ar. We have found that Arions promote a helpful surface pre-conditioning, while fluorine radicals, produced by NF{sub 3} dissociation, are needed to increase the Si etching rate. Different combinations of flux ratios, gas pressures and RF power have been explored. Efforts have been devoted in obtaining a homogeneous texture on large area wafers, which is inescapable for industrialization. After 10 minutes process effective reflectance values have been measured within the range of 12-14%, and with a-Si/SiN{sub x} the value reduced to 7%. Post-processing minority carrier lifetime values in the range of 10 microseconds have been measured without applying any further chemical cleaning. Additionally, microscopic analysis has been performed to evaluate the surface microstructure morphology (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  4. Silicon materials task of the Low-Cost Solar Array Project (Phase IV). Effects of impurities and processing on silicon solar cells. Nineteenth quarterly report, April 1980-June 1980

    Energy Technology Data Exchange (ETDEWEB)

    Hopkins, R.H.; Davis, J.R.; Rohatgi, A.; Campbell, R.B.; Rai-Choudhury, P.; Hanes, M.H.; Mollenkopf, H.C.; McCormick, J.R.

    1980-07-01

    The overall objective of this program is to define the effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells. The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Nine 4 ohm-cm p type silicon ingots were grown and evaluated in support of the experimental program this quarter. Of these, three were polycrystalline ingots doped with Cr, Mo, and V, respectively, produced under conditions which successfully eliminated the metal-rich inclusions formed when growth of these heavily-doped specimens was attempted during the last quarter. Evaluation of polycrystalline ingots doped to the mid 10/sup 13/ cm/sup -3/ range with Ti or V showed little evidence for grain boundary segregation. Deep level spectroscopy on both as-grown wafers and solar cells showed little variation in impurity concentration from place to place across the ingot regardless of the presence of grain boundaries or other structural features. Deep level spectroscopy was also used to monitor the electrically active impurity concentrations in ingots to be used for process studies, aging experiments, and high efficiency cells. The basic aspects of a model to describe efficiency behavior in high efficiency cells have been formulated and a computer routine is being implemented for back field type devices to analyze the functional relationships between impurity concentrations and cell performance.

  5. An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED

    Institute of Scientific and Technical Information of China (English)

    ZHAO Li-qing; WU Chun-ya; HAO Da-shou; YAO Ying; MENG Zhi-guo; XIONG Shao-zhen

    2009-01-01

    Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is pro-posed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the parameters of LTPS TFTs were extracted from the LTPS TFTs made in our lab. The simulation results indicate that the circuit can fulfill the driving function.

  6. Piezoelectric Nanogenerator Using p-Type ZnO Nanowire Arrays

    KAUST Repository

    Lu, Ming-Pei

    2009-03-11

    Using phosphorus-doped ZnO nanowire (NW) arrays grown on silicon substrate, energy conversion using the p-type ZnO NWs has been demonstrated for the first time. The p-type ZnO NWs produce positive output voltage pulses when scanned by a conductive atomic force microscope (AFM) in contact mode. The output voltage pulse is generated when the tip contacts the stretched side (positive piezoelectric potential side) of the NW. In contrast, the n-type ZnO NW produces negative output voltage when scanned by the AFM tip, and the output voltage pulse is generated when the tip contacts the compressed side (negative potential side) of the NW. In reference to theoretical simulation, these experimentally observed phenomena have been systematically explained based on the mechanism proposed for a nanogenerator. © 2009 American Chemical Society.

  7. Increasing The Efficiency of Silicon Solar Cells via an Anti-reflecting Nano-porous Surface Layer

    Science.gov (United States)

    Coskuner, Ahmet; Gokce, Aisha; Altunay, Omer; Skarlatos, Yani; Ozatay, Ozhan

    2015-03-01

    Electrochemical etching of silicon in a controlled environment results in a porous surface that has many application areas from drug delivery to optoluminescent devices. There is vast interest in implementing porous silicon in silicon solar cells to increase light absorption and therefore the efficiency. Here we demonstrate successful formation of a nano-porous surface on mono-crystalline Si wafers as well as doped Si solar cells. Our results show that pre-cleaning and post-drying is crucial to acquire a smooth, non-cracked topography. We also find that under similar conditions, smaller pores in a denser arrangement and with shorter depths form in p-n junction type Si wafers compared to n-type or p-type Si. In ITO coated porous Si solar cells with Al back contacts, the measured efficiency increase is almost 50% of those without a porous surface. This is a promising result to further enhance the performance of Si solar cell devices.

  8. Surface recombination analysis in silicon-heterojunction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Barrio, R.; Gandia, J.J.; Carabe, J.; Gonzalez, N.; Torres, I. [CIEMAT, Madrid (Spain); Munoz, D.; Voz, C. [Universitat Politecnica de Catalunya, Barcelona (Spain)

    2010-02-15

    The origin of this work is the understanding of the correlation observed between efficiency and emitter-deposition temperature in single silicon-heterojunction solar cells prepared by depositing an n-doped hydrogenated-amorphous-silicon thin film onto a p-type crystalline-silicon wafer. In order to interpret these results, surface-recombination velocities have been determined by two methods, i.e. by fitting the current-voltage characteristics to a theoretical model and by means of the Quasi-Steady-State Photoconductance Technique (QSSPC). In addition, effective diffusion lengths have been estimated from internal quantum efficiencies. The analysis of these data has led to conclude that the performance of the cells studied is limited by back-surface recombination rather than by front-heterojunction quality. A 12%-efficient cell has been prepared by combining optimum emitter-deposition conditions with back-surface-field (BSF) formation by vacuum annealing of the back aluminium contact. This result has been achieved without using any transparent conductive oxide. (author)

  9. Silicon Strip Detectors for the ATLAS sLHC Upgrade

    CERN Document Server

    Soldevila, U; The ATLAS collaboration

    2011-01-01

    While the Large Hadron Collider (LHC) at CERN is continuing to deliver an ever-increasing luminosity to the experiments, plans for an upgraded machine called Super-LHC (sLHC) are progressing. The upgrade is foreseen to increase the LHC design luminosity by a factor ten. The ATLAS experiment will need to build a new tracker for sLHC operation, which needs to be suited to the harsh sLHC conditions in terms of particle rates and radiation doses. In order to cope with the increase in pile-up backgrounds at the higher luminosity, an all silicon detector is being designed. To successfully face the increased radiation dose, a new generation of extremely radiation hard silicon detectors is being designed. Silicon sensors with sufficient radiation hardness are the subject of an international R&amp;D programme, working on pixel and strip sensors. The efforts presented here concentrate on the innermost strip layers. We have developed a large number of prototype planar detectors produced on p-type wafers in a...

  10. Silicon strip detectors for the ATLAS HL-LHC upgrade

    CERN Document Server

    Bernabeu, J; The ATLAS collaboration

    2011-01-01

    While the Large Hadron Collider (LHC) at CERN is continuing to deliver an ever-increasing luminosity to the experiments, plans for an upgraded machine called Super-LHC (sLHC) are progressing. The upgrade is foreseen to increase the LHC design luminosity by a factor ten. The ATLAS experiment will need to build a new tracker for sLHC operation, which needs to be suited to the harsh sLHC conditions in terms of particle rates and radiation doses. In order to cope with the increase in pile-up backgrounds at the higher luminosity, an all silicon detector is being designed. To successfully face the increased radiation dose, a new generation of extremely radiation hard silicon detectors is being designed. Silicon sensors with sufficient radiation hardness are the subject of an international R&D programme, working on pixel and strip sensors. The efforts presented here concentrate on the innermost strip layers. We have developed a large number of prototype planar detectors produced on p-type wafers in a number of d...

  11. Scale-dependent diffusion anisotropy in nanoporous silicon

    Science.gov (United States)

    Kondrashova, Daria; Lauerer, Alexander; Mehlhorn, Dirk; Jobic, Hervé; Feldhoff, Armin; Thommes, Matthias; Chakraborty, Dipanjan; Gommes, Cedric; Zecevic, Jovana; de Jongh, Petra; Bunde, Armin; Kärger, Jörg; Valiullin, Rustem

    2017-01-01

    Nanoporous silicon produced by electrochemical etching of highly B-doped p-type silicon wafers can be prepared with tubular pores imbedded in a silicon matrix. Such materials have found many technological applications and provide a useful model system for studying phase transitions under confinement. This paper reports a joint experimental and simulation study of diffusion in such materials, covering displacements from molecular dimensions up to tens of micrometers with carefully selected probe molecules. In addition to mass transfer through the channels, diffusion (at much smaller rates) is also found to occur in directions perpendicular to the channels, thus providing clear evidence of connectivity. With increasing displacements, propagation in both axial and transversal directions is progressively retarded, suggesting a scale-dependent, hierarchical distribution of transport resistances (“constrictions” in the channels) and of shortcuts (connecting “bridges”) between adjacent channels. The experimental evidence from these studies is confirmed by molecular dynamics (MD) simulation in the range of atomistic displacements and rationalized with a simple model of statistically distributed “constrictions” and “bridges” for displacements in the micrometer range via dynamic Monte Carlo (DMC) simulation. Both ranges are demonstrated to be mutually transferrable by DMC simulations based on the pore space topology determined by electron tomography.

  12. Efficiency Enhancement of Nanoporous Silicon/Polycrystalline-Silicon Solar Cells by Application of Trenched Electrodes

    Directory of Open Access Journals (Sweden)

    Kuen-Hsien Wu

    2014-01-01

    Full Text Available Trenched electrodes were proposed to enhance the short-circuit current and conversion efficiency of polycrystalline-silicon (poly-Si solar cells with nanoporous silicon (NPS surface layers. NPS films that served as textured surface layers were firstly prepared on heavily doped p+-type (100 poly-Si wafers by anodic etching process. Interdigitated trenches were formed in the NPS layers by a reactive-ion-etch (RIE process and Cr/Al double-layered metal was then deposited to fill the trenches and construct trenched-electrode-contacts (TEC’s. Cells with TEC structures (called “TEC cells” obtained 5.5 times higher short-circuit current than that of cells with planar electrode contacts (called “non-TEC cells”. Most significantly, a TEC cell achieved 8 times higher conversion efficiency than that of a non-TEC cell. The enhanced short-circuit current and conversion efficiency in TEC cells were ascribed to the reduced overall series resistance of devices. In a TEC cell, trenched electrodes provided photocurrent flowing routes that directly access the poly-Si substrates without passing through the high resistive NPS layers. Therefore, the application of NPS surface layers with trenched electrodes is a novel approach to development of highly efficient poly-Si solar cells.

  13. Photovoltaic properties of ZnO nanorods/p-type Si heterojunction structures

    Directory of Open Access Journals (Sweden)

    Rafal Pietruszka

    2014-02-01

    Full Text Available Selected properties of photovoltaic (PV structures based on n-type zinc oxide nanorods grown by a low temperature hydrothermal method on p-type silicon substrates (100 are investigated. PV structures were covered with thin films of Al doped ZnO grown by atomic layer deposition acting as transparent electrodes. The investigated PV structures differ in terms of the shapes and densities of their nanorods. The best response is observed for the structure containing closely-spaced nanorods, which show light conversion efficiency of 3.6%.

  14. Passivation of c-Si surfaces by sub-nm amorphous silicon capped with silicon nitride

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Yimao, E-mail: yimao.wan@anu.edu.au; Yan, Di; Bullock, James; Zhang, Xinyu; Cuevas, Andres [Research School of Engineering, The Australian National University, Canberra, Australian Capital Territory 0200 (Australia)

    2015-12-07

    A sub-nm hydrogenated amorphous silicon (a-Si:H) film capped with silicon nitride (SiN{sub x}) is shown to provide a high level passivation to crystalline silicon (c-Si) surfaces. When passivated by a 0.8 nm a-Si:H/75 nm SiN{sub x} stack, recombination current density J{sub 0} values of 9, 11, 47, and 87 fA/cm{sup 2} are obtained on 10 Ω·cm n-type, 0.8 Ω·cm p-type, 160 Ω/sq phosphorus-diffused, and 120 Ω/sq boron-diffused silicon surfaces, respectively. The J{sub 0} on n-type 10 Ω·cm wafers is further reduced to 2.5 ± 0.5 fA/cm{sup 2} when the a-Si:H film thickness exceeds 2.5 nm. The passivation by the sub-nm a-Si:H/SiN{sub x} stack is thermally stable at 400 °C in N{sub 2} for 60 min on all four c-Si surfaces. Capacitance–voltage measurements reveal a reduction in interface defect density and film charge density with an increase in a-Si:H thickness. The nearly transparent sub-nm a-Si:H/SiN{sub x} stack is thus demonstrated to be a promising surface passivation and antireflection coating suitable for all types of surfaces encountered in high efficiency c-Si solar cells.

  15. Wafer scale oblique angle plasma etching

    Energy Technology Data Exchange (ETDEWEB)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  16. Phase shift reflectometry for wafer inspection

    Science.gov (United States)

    Peng, Kuang; Cao, Yiping; Li, Hongru; Sun, Jianfei; Bourgade, Thomas; Asundi, Anand Krishna

    2015-07-01

    In 3D measurement, specular surfaces can be reconstructed by phase shift reflectometry and the system configuration is simple. In this paper, a wafer is measured for industrial inspection to make sure the quality of the wafer by calibrating, phase unwrapping, slope calculation and integration. The profile result of the whole wafer can be reconstructed and it is a curve. As the height of the structures on the wafer is the target we are interested in, by fitting and subtracting the curve surface, the structures on the wafer can be observed on the flat surface. To confirm the quality farther, a part of the wafer is captured and zoomed in to be detected so that the difference between two structures can be observed better.

  17. Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

    2011-03-15

    Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  18. Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

    Science.gov (United States)

    Zhu, Chunsheng; Ning, Wenguo; Xu, Gaowei; Luo, Le

    2014-09-01

    Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature ( T g) of polyimide will help to reduce the final wafer warpage.

  19. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  20. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Energy Technology Data Exchange (ETDEWEB)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  1. Study of wafer pre-aligning approaches

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    Wafer pre-aligning system is an important component in IC manufacturing industry. A wafer prealigning platform with a CCD sensor is presented in this paper. The centering and notch detecting approaches are extended based on this platform. Least square circle fitting approach is adopted to calculate the center and radius of the wafer, and a formula for calculating the fitting error is derived. An approach called edge variation rate is also proposed to detect the range of wafer notch, and the fiducial is calculated by curve fitting approach. These approaches can improve the accuracy effectively as indicated by experiments.

  2. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  3. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  4. Sprayed and Spin-Coated Multilayer Antireflection Coating Films for Nonvacuum Processed Crystalline Silicon Solar Cells

    Directory of Open Access Journals (Sweden)

    Abdullah Uzum

    2017-01-01

    Full Text Available Using the simple and cost-effective methods, spin-coated ZrO2-polymer composite/spray-deposited TiO2-compact multilayer antireflection coating film was introduced. With a single TiO2-compact film on the surface of a crystalline silicon wafer, 5.3% average reflectance (the reflectance average between the wavelengths of 300 nm and 1100 nm was observed. Reflectance decreased further down to 3.3% after forming spin-coated ZrO2 on the spray-deposited TiO2-compact film. Silicon solar cells were fabricated using CZ-Si p-type wafers in three sets: (1 without antireflection coating (ARC layer, (2 with TiO2-compact ARC film, and (3 with ZrO2-polymer composite/TiO2-compact multilayer ARC film. Conversion efficiency of the cells improved by a factor of 0.8% (from 15.19% to 15.88% owing to the multilayer ARC. Jsc was improved further by 2 mA cm−2 (from 35.3 mA cm−2 to 37.2 mA cm−2 when compared with a single TiO2-compact ARC.

  5. High-efficiency silicon heterojunction solar cells: Status and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    De Wolf, S.; Geissbuehler, J.; Loper, P.; Martin de Nicholas, S.; Seif, J.; Tomasi, A.; Ballif, C.

    2015-05-11

    Silicon heterojunction technology (HJT) uses silicon thin-film deposition techniques to fabricate photovoltaic devices from mono-crystalline silicon wafers (c-Si). This enables energy-conversion efficiencies above 21 %, also at industrial-production level. In this presentation we review the present status of this technology and point out recent trends. We first discuss how the properties of thin hydrogenated amorphous silicon (a-Si:H) films can be exploited to fabricate passivating contacts, which is the key to high- efficiency HJT solar cells. Such contacts enable very high operating voltages, approaching the theoretical limits, and yield small temperature coefficients. With this approach, an increasing number of groups are reporting devices with conversion efficiencies well over 20 % on both-sides contacted n-type cells, Panasonic leading the field with 24.7 %. Exciting results have also been obtained on p-type wafers. Despite these high voltages, important efficiency gains can still be made in fill factor and optical design. This requires improved understanding of carrier transport across device interfaces and reduced parasitic absorption in HJT solar cells. For the latter, several strategies can be followed: Short-wavelength losses can be reduced by replacing the front a-Si:H films with wider-bandgap window layers, such as silicon alloys or even metal oxides. Long- wavelength losses are mitigated by introducing new high-mobility TCO’s such as hydrogenated indium oxide, and also by designing new rear reflectors. Optical shadow losses caused by the front metallization grid are significantly reduced by replacing printed silver electrodes with fine-line plated copper contacts, leading also to possible cost advantages. The ultimate approach to minimize optical losses is the implementation of back-contacted architectures, which are completely devoid of grid shadow losses and parasitic absorption in the front layers can be minimized irrespective of electrical

  6. Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

    Science.gov (United States)

    Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

    2009-01-01

    The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

  7. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  8. A comparison of batch and single wafer high dose arsenic ion implantation techniques

    Energy Technology Data Exchange (ETDEWEB)

    Irwin, R.B.; Filo, A.J.; Kannan, V.C.; Feygenson, A.; Prematta, R.J.

    1989-04-01

    High dose, low energy (4x10/sup 15/ cm/sup -2/ at 15 keV) arsenic ion implantation into silicon was performed in batch and single wafer mode using medium and high current ion implanters. An investigation of implanted and annealed samples by Rutherford backscattering (RBS), transmission electron microscopy (TEM), thermal wave technique, and sheet resistance mapping showed little to no difference of arsenic profiles and residual damage between batch and single wafer implantation conditions when the sample temperature during implantation was kept below 120/sup 0/C. (orig.).

  9. A comparison of batch and single wafer high dose arsenic ion implantation techniques

    Science.gov (United States)

    Irwin, R. B.; Filo, A. J.; Kannan, V. C.; Feygenson, A.; Prematta, R. J.

    1989-04-01

    High dose, low energy (4×10 15 cm -2 at 15 keV) arsenic ion implantation into silicon was performed in batch and single wafer mode using medium and high current ion implanters. An investigation of implanted and annealed samples by Rutherford backscattering (RBS), transmission electron microscopy (TEM), thermal wave technique, and sheet resistance mapping showed little to no difference of arsenic profiles and residual damage between batch and single wafer implantation conditions when the sample temperature during implantation was kept below 120° C.

  10. Single crystalline silicon solar cells with rib structure

    Science.gov (United States)

    Yoshiba, Shuhei; Hirai, Masakazu; Abe, Yusuke; Konagai, Makoto; Ichikawa, Yukimi

    2017-02-01

    To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer's strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC) could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  11. Silicon superconducting quantum interference device

    Energy Technology Data Exchange (ETDEWEB)

    Duvauchelle, J. E.; Francheteau, A.; Marcenat, C.; Lefloch, F., E-mail: francois.lefloch@cea.fr [Université Grenoble Alpes, CEA - INAC - SPSMS, F-38000 Grenoble (France); Chiodi, F.; Débarre, D. [Université Paris-sud, CNRS - IEF, F-91405 Orsay - France (France); Hasselbach, K. [Université Grenoble Alpes, CNRS - Inst. Néel, F-38000 Grenoble (France); Kirtley, J. R. [Center for probing at nanoscale, Stanford University, Palo Alto, California 94305-4045 (United States)

    2015-08-17

    We have studied a Superconducting Quantum Interference Device (SQUID) made from a single layer thin film of superconducting silicon. The superconducting layer is obtained by heavily doping a silicon wafer with boron atoms using the gas immersion laser doping technique. The SQUID is composed of two nano-bridges (Dayem bridges) in a loop and shows magnetic flux modulation at low temperature and low magnetic field. The overall behavior shows very good agreement with numerical simulations based on the Ginzburg-Landau equations.

  12. Electrical and optical properties of sub-10 nm nickel silicide films for silicon solar cells

    Science.gov (United States)

    Brahmi, Hatem; Ravipati, Srikanth; Yarali, Milad; Shervin, Shahab; Wang, Weijie; Ryou, Jae-Hyun; Mavrokefalos, Anastassios

    2017-01-01

    Highly conductive and transparent films of ultra-thin p-type nickel silicide films have been prepared by RF magnetron sputtering of nickel on silicon substrates followed by rapid thermal annealing in an inert environment in the temperature range 400-600 °C. The films are uniform throughout the wafer with thicknesses in the range of 3-6 nm. The electrical and optical properties are presented for nickel silicide films with varying thickness. The Drude-Lorentz model and Fresnel equations were used to calculate the dielectric properties, sheet resistance, absorption and transmission of the films. These ultrathin nickel silicide films have excellent optoelectronic properties for p-type contacts with optical transparencies up to 80% and sheet resistance as low as ~0.15 µΩ cm. Furthermore, it was shown that the use of a simple anti-reflection (AR) coating can recover most of the reflected light approaching the values of a standard Si solar cell with the same AR coating. Overall, the combination of ultra-low thickness, high transmittance, low sheet resistance and ability to recover the reflected light by utilizing standard AR coating makes them ideal for utilization in silicon based photovoltaic technologies as a p-type transparent conductor.

  13. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  14. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  15. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  16. Photonic Integration on the Hybrid Silicon Evanescent Device Platform

    Directory of Open Access Journals (Sweden)

    Hyundai Park

    2008-01-01

    Full Text Available This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

  17. Internal alignement of the BABAR silicon vertex tracking detector

    CERN Document Server

    Brown, D; Roberts, D

    2007-01-01

    The BABAR Silicon Vertex Tracker (SVT ) is a five-layer double-sided silicon detector designed to provide precise measurements of the position and direction of primary tracks, and to fully reconstruct low-momentum tracks produced in e+e¡ collisions at the PEP-II asymmetric collider at Stanford Linear Accelerator Center. This paper describes the design, implementation, performance and validation of the local alignment procedure used to determine the relative positions and orientations of the 340 Silicon Vertex Trackerwafers. This procedure uses a tuned mix of lab-bench measurements and complementary in-situ experimental data to control systematic distortions. Wafer positions and orientations are determined by minimizing a Â2 computed using these data for each wafer individually, iterating to account for between-wafer correlations. A correction for aplanar distortions of the silicon wafers is measured and applied. The net effect of residual mis-alignments on relevant physical variables evaluated in special co...

  18. Porous Silicon Covered with Silver Nanoparticles as Surface-Enhanced Raman Scattering (SERS) Substrate for Ultra-Low Concentration Detection.

    Science.gov (United States)

    Kosović, Marin; Balarin, Maja; Ivanda, Mile; Đerek, Vedran; Marciuš, Marijan; Ristić, Mira; Gamulin, Ozren

    2015-12-01

    Microporous and macro-mesoporous silicon templates for surface-enhanced Raman scattering (SERS) substrates were produced by anodization of low doped p-type silicon wafers. By immersion plating in AgNO3, the templates were covered with silver metallic film consisting of different silver nanostructures. Scanning electron microscopy (SEM) micrographs of these SERS substrates showed diverse morphology with significant difference in an average size and size distribution of silver nanoparticles. Ultraviolet-visible-near-infrared (UV-Vis-NIR) reflection spectroscopy showed plasmonic absorption at 398 and 469 nm, which is in accordance with the SEM findings. The activity of the SERS substrates was tested using rhodamine 6G (R6G) dye molecules and 514.5 nm laser excitation. Contrary to the microporous silicon template, the SERS substrate prepared from macro-mesoporous silicon template showed significantly broader size distribution of irregular silver nanoparticles as well as localized surface plasmon resonance closer to excitation laser wavelength. Such silver morphology has high SERS sensitivity that enables ultralow concentration detection of R6G dye molecules up to 10(-15) M. To our knowledge, this is the lowest concentration detected of R6G dye molecules on porous silicon-based SERS substrates, which might even indicate possible single molecule detection.

  19. Preparation and Characterization of PZT Wafers

    Science.gov (United States)

    Seal, A.; Rao, B. S. S. Chandra; Kamath, S. V.; Sen, A.; Maiti, H. S.

    2008-07-01

    Piezoelectric materials have recently attracted a lot of attention for ultrasonic structural health monitoring (shm) in aerospace, defence and civilian sectors, where they can act as both actuators and sensors. Incidentally, piezoelectric materials in the form of wafers (pwas-piezoelectric wafer active sensor, approx. 5-10 mm square and 0.2-0.3 mm thickness) are inexpensive, non intrusive and non-resonant wide band devices that can be surface-mounted on existing structures, inserted between the layers of lap joints or embedded inside composite materials. The material of choice for piezoelectric wafers is lead zirconate titanate (PZT) of composition close to morphotropic phase boundary [pb(zr0.52 ti0.48)o3]. However, an excess pbo is normally added to pzt as a densification aid and also to make up for the lead loss during high temperature sintering. Hence, it is of paramount importance to know how the shift of the lead content from the morphotropic composition affects the piezoelectric and mechanical properties of the sintered wafers, keeping in view the importance of mechanical properties of wafers in shm. In the present study, we observed that with the increase in the lead content of the sintered wafers, the dielectric and piezoelectric constants decreased. However, the elastic modulus, hardness and fracture toughness of the wafers increased with increasing lead content in the composition. Hence, the lead content in the sintered wafers should be optimized to get acceptable piezoelectric and mechanical

  20. Research and development of photovoltaic power system. Research on surface passivation for high-efficiency silicon solar cells; Taiyoko hatsuden system no kenkyu kaihatsu. Hyomen passivation no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    Saito, T. [Tokyo Univ. of Agriculture and Technology, Tokyo (Japan). Faculty of Technology

    1994-12-01

    This paper reports the result obtained during fiscal 1994 on research on surface passivation of high-efficiency silicon solar cells. In research on carrier recombination on SiO2/doped silicon interface, measurements were carried out on minority carrier life with respect to p-type silicon substrates with which phosphorus with high and low concentrations are diffused uniformly on the surface and non-uniformly on the back and then oxidized. The measurements were performed for the purpose of evaluating the carrier recombination at p-n junctions. Effective life time of oxidized test samples increased longer than that of prior to the oxidization as a result of effect of surface passivation contributing remarkably. In research on reduction in carrier recombination on SiO2/Si interface by using H radical annealing, experiments were conducted by using a method that uses more active H-atoms. As a result, it was revealed that the reduction effect is recognized at as low temperature as 200{degree}C, and photo-bias effect is also noticeable. Other research activities included analytic research on minority carrier recombination on micro crystalline silicon/crystalline silicon interface, and experimental research on evaluation of minority carrier life of poly-crystalline silicon wafers. 6 figs.

  1. 19.4%-efficient large-area fully screen-printed silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Gatz, Sebastian; Hannebauer, Helge; Hesse, Rene; Werner, Florian; Schmidt, Arne; Dullweber, Thorsten; Bothe, Karsten [Institute for Solar Energy Hamelin (ISFH), Am Ohrberg 1, 31860 Emmerthal (Germany); Schmidt, Jan; Brendel, Rolf [Institute for Solar Energy Hamelin (ISFH), Am Ohrberg 1, 31860 Emmerthal (Germany); Institute of Solid-State Physics, University of Hannover, Appelstrasse 2, 30167 Hannover (Germany)

    2011-04-15

    We demonstrate industrially feasible large-area solar cells with passivated homogeneous emitter and rear achieving energy conversion efficiencies of up to 19.4% on 125 x 125 mm{sup 2} p-type 2-3 {omega} cm boron-doped Czochralski silicon wafers. Front and rear metal contacts are fabricated by screen-printing of silver and aluminum paste and firing in a conventional belt furnace. We implement two different dielectric rear surface passivation stacks: (i) a thermally grown silicon dioxide/silicon nitride stack and (ii) an atomic-layer-deposited aluminum oxide/silicon nitride stack. The dielectrics at the rear result in a decreased surface recombination velocity of S{sub rear} = 70 cm/s and 80 cm/s, and an increased internal IR reflectance of up to 91% corresponding to an improved J{sub sc} of up to 38.9 mA/cm{sup 2} and V{sub oc} of up to 664 mV. We observe an increase in cell efficiency of 0.8% absolute for the cells compared to 18.6% efficient reference solar cells featuring a full-area aluminum back surface field. To our knowledge, the energy conversion efficiency of 19.4% is the best value reported so far for large area screen-printed solar cells. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  2. P-type electronic and thermal transport properties of Mg2Sn1-xSix

    Science.gov (United States)

    Kim, Sunphil; Wiendlocha, Bartlomiej; Heremans, Joseph P.

    2013-03-01

    P-type Mg2Sn doped with various acceptors(1)(2) has been studied as a potential thermoelectric material. Because of its narrow band gap and high lattice thermal conductivity, the zT values of the binary compound are limited: zTmax reported is 0.3(3). In this work, we synthesize and characterize p-type-doped Mg2Sn1-xSix with various acceptors. Silicon is added in order to widen the band gap and scatter the phonons. The conduction band degeneracy that yields excellent zT in n-type material in the Mg2Sn1-xSix alloy system unfortunately does not apply to p-type material. Thermomagnetic and galvanomagnetic properties (electrical resistivity, Seebeck, Hall, and Nernst coefficients) are measured, along with thermal conductivity and band gap measurements. Finally, zT values are reported. (1) H. Y. Chen et al. Journal of Electronic Materials, Vol. 38, No. 7, 2009 (2) S. Choi et al. Journal of Electronic Materials, Vol. 41, No. 6, 2012 (3) H. Y. Chen et al. Phys. Status Solidi A 207, No. 11, 2523-2531 (2010) The work is supported by the joint NSF/DOE program on thermoelectrics, NSF-CBET-1048622

  3. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  4. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  5. Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

    NARCIS (Netherlands)

    Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

    2008-01-01

    The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

  6. Integratible Process for Fabrication of Fluidic Microduct Networks on a Single Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Matzke, C.M.; Ashby, C.I.; Bridges, M.M.; Griego, L.; Wong, C.C.

    1999-09-07

    We present a microelectronics fabrication compatible process that comprises photolithography and a key room temperature SiON thin film plasma deposition to define and seal a fluidic microduct network. Our single wafer process is independent of thermo-mechanical material properties, particulate cleaning, global flatness, assembly alignment, and glue medium application, which are crucial for wafer fusion bonding or sealing techniques using a glue medium. From our preliminary experiments, we have identified a processing window to fabricate channels on silicon, glass and quartz substrates. Channels with a radius of curvature between 8 and 50 {micro}m, are uniform along channel lengths of several inches and repeatable across the wafer surfaces. To further develop this technology, we have begun characterizing the SiON film properties such as elastic modulus using nanoindentation, and chemical bonding compatibility with other microelectronic materials.

  7. Development of ultra-low impedance Through-wafer Micro-vias

    Energy Technology Data Exchange (ETDEWEB)

    Finkbeiner, F.M. E-mail: fmf@lheapop.gsfc.nasa.gov; Adams, C.; Apodaca, E.; Chervenak, J.A.; Fischer, J.; Doan, N.; Li, M.J.; Stahle, C.K.; Brekosky, R.P.; Bandler, S.R.; Figueroa-Feliciano, E.; Lindeman, M.A.; Kelley, R.L.; Saab, T.; Talley, D.J

    2004-03-11

    Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

  8. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  9. Capacitance-voltage analysis of a high-k dielectric on silicon

    Institute of Scientific and Technical Information of China (English)

    Davinder Rathee; Sandeep K. Arya; Mukesh Kumar

    2012-01-01

    Device characteristics of TiO2 gate dielectrics deposited by a sol-gel method and DC sputtering method on a P-type silicon wafer are reported.Metal-oxide-semiconductor capacitors with Al as the top electrode were fabricated to study the electrical properties of TiO2 films.The films were physically characterized by using X-ray diffraction,a capacitor voltage measurement,scanning electron microscopy,and by spectroscopy ellipsometry.The XRD and DST-TG indicate the presence of an anatase TiO2 phase in the film.Films deposited at higher temperatures showed better crystallinity.The dielectric constant calculated using the capacitance voltage measurement was found to be 18 and 73 for sputtering and sol-gel samples respectively.The refractive indices of the films were found to be 2.16 for sputtering and 2.42 for sol-gel samples.

  10. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  11. p-Type MWT. Integrated cell and module technology

    Energy Technology Data Exchange (ETDEWEB)

    Tool, C.J.J.; Kossen, E.J.; Bennett, I.J.

    2013-10-15

    A major issue of concern in MWT solar cells is the increased leakage current at reversed bias voltage through the vias compared. At ECN we have been working on reducing this leakage current to levels comparable to H-pattern cells. In this study we present the results of this work. We further show the benefit of a combined cell and module design for MWT solar cells. At the cell level, MWT production costs per wafer are comparable with H-pattern while the cell output increases. At the module level this design results in a further increase of the power output.

  12. p-type MWT. Integrated Cell and Module Technology

    Energy Technology Data Exchange (ETDEWEB)

    Tool, C.J.J.; Kossen, E.J.; Bennett, I.J. [ECN Solar Energy, Petten (Netherlands)

    2013-03-15

    A major issue of concern in MWT (metal wrap-through) solar cells is the increased leakage current at reversed bias voltage through the vias compared. At ECN we have been working on reducing this leakage current to levels comparable to H-pattern cells. In this study we present the results of this work. We further show the benefit of a combined cell and module design for MWT solar cells. At the cell level, MWT production costs per wafer are comparable with H-pattern while the cell output increases. At the module level this design results in a further increase of the power output.

  13. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  14. Wet-chemical systems and methods for producing black silicon substrates

    Energy Technology Data Exchange (ETDEWEB)

    Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

    2015-05-19

    A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

  15. Low cost sol–gel derived SiC–SiO{sub 2} nanocomposite as anti reflection layer for enhanced performance of crystalline silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Jannat, Azmira [School of Semiconductor and Chemical Engineering, Solar Energy Research Center, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); Solar Energy Engineering, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); Lee, Woojin [School of Semiconductor and Chemical Engineering, Solar Energy Research Center, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); Akhtar, M. Shaheer, E-mail: shaheerakhtar@jbnu.ac.kr [School of Semiconductor and Chemical Engineering, Solar Energy Research Center, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); New & Renewable Energy Materials Development Center (NewREC), Chonbuk National University, Jeonbuk (Korea, Republic of); Li, Zhen Yu [School of Semiconductor and Chemical Engineering, Solar Energy Research Center, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); Yang, O.-Bong, E-mail: obyang@jbnu.ac.kr [School of Semiconductor and Chemical Engineering, Solar Energy Research Center, Chonbuk National University, Jeonju, Jeonbuk 54896 (Korea, Republic of); New & Renewable Energy Materials Development Center (NewREC), Chonbuk National University, Jeonbuk (Korea, Republic of)

    2016-04-30

    Graphical abstract: - Highlights: • Sol–gel derived SiC–SiO{sub 2} nanocomposite was prepared. • It effectively coated as AR layer on p-type Si-wafer. • SiC–SiO{sub 2} layer on Si solar cells exhibited relatively low reflectance of 7.08%. • Fabricated Si solar cell attained highly comparable performance of 16.99% to commercial device. - Abstract: This paper describes the preparation, characterizations and the antireflection (AR) coating application in crystalline silicon solar cells of sol–gel derived SiC–SiO{sub 2} nanocomposite. The prepared SiC–SiO{sub 2} nanocomposite was effectively applied as AR layer on p-type Si-wafer via two step processes, where the sol–gel of precursor solution was first coated on p-type Si-wafer using spin coating at 2000 rpm and then subjected to annealing at 450 °C for 1 h. The crystalline, and structural observations revealed the existence of SiC and SiO{sub 2} phases, which noticeably confirmed the formation of SiC–SiO{sub 2} nanocomposite. The SiC–SiO{sub 2} layer on Si solar cells was found to be an excellent AR coating, exhibiting the low reflectance of 7.08% at wavelengths ranging from 400 to 1000 nm. The fabricated crystalline Si solar cell with SiC–SiO{sub 2} nanocomposite AR coating showed comparable power conversion efficiency of 16.99% to the conventional Si{sub x}N{sub x} AR coated Si solar cell. New and effective sol–gel derived SiC–SiO{sub 2} AR layer would offer a promising technique to produce high performance Si solar cells with low-cost.

  16. Single crystalline mesoporous silicon nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Hochbaum, A.I.; Gargas, Daniel; Jeong Hwang, Yun; Yang, Peidong

    2009-08-04

    Herein we demonstrate a novel electroless etching synthesis of monolithic, single-crystalline, mesoporous silicon nanowire arrays with a high surface area and luminescent properties consistent with conventional porous silicon materials. These porous nanowires also retain the crystallographic orientation of the wafer from which they are etched. Electron microscopy and diffraction confirm their single-crystallinity and reveal the silicon surrounding the pores is as thin as several nanometers. Confocal fluorescence microscopy showed that the photoluminescence (PL) of these arrays emanate from the nanowires themselves, and their PL spectrum suggests that these arrays may be useful as photocatalytic substrates or active components of nanoscale optoelectronic devices.

  17. Force Modeling for Ultrasonic-assisted Wire Saw Cutting SiC Monocryatal Wafers

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jie; LI Shujuan; Liu Yong

    2011-01-01

    The advantages, such as a small cutting force, narrow kerf and little material waste make wire saw cut- ting suitable for machining precious materials like SiC, Si monocrystal and a variety of gem. As regards wire saw cutting fo wafer, however, in traditional wire saw cutting process, the cutting efficiency is low, the wear of wire saw is badly, the surface roughness of wafer is poor etc, which have a seriously impact on the cutting process stability and the use of wafers. Ultrasonic-assisted machining method is very suitable for processing a variety of non-conduc- tive hard and brittle materials, glass, ceramics, quartz, silicon, precious stones and diamonds, etc. In this paper, the force model of ultrusonic-assisted wire saw cutting of SiC monocrystal wafer, based on the kinematic and experi- mental analysis were established. The single factor and orthogonal experimental scheme for different processing pa- rameters such as wire saw speed, part rotation speed of and part feed rate, were carried out in traditional wire saw and ultrasonic-assisted wire saw cutting process. The multiple linear regression method is used to establish the static model among the cutting force, processing parameters and ultrasonic vibration parameters, and the model signifi- cance is verified. The results show, as regards ultrasonic-assisted wire saw cutting of SiC monicrystal wafer, both the tangential and normal cutting forces can reduce about 24. 5%-36% and 36. 6%-40%.

  18. GeSn-on-insulator substrate formed by direct wafer bonding

    Science.gov (United States)

    Lei, Dian; Lee, Kwang Hong; Bao, Shuyu; Wang, Wei; Wang, Bing; Gong, Xiao; Tan, Chuan Seng; Yeo, Yee-Chia

    2016-07-01

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge1-xSnx layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO2 on Ge1-xSnx, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge1-xSnx layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge1-xSnx epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge1-xSnx film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  19. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  20. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates.

    Science.gov (United States)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-19

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  1. Tension assisted metal transfer of graphene for Schottky diodes onto wafer scale substrates

    Science.gov (United States)

    Lee, Jooho; Lee, Su Chan; Kim, Yongsung; Heo, Jinseong; Lee, Kiyoung; Lee, Dongwook; Kim, Jaekwan; Lee, Sunghee; Lee, Chang Seung; Nam, Min Sik; Jun, Seong Chan

    2016-02-01

    We developed an effective graphene transfer method for graphene/silicon Schottky diodes on a wafer as large as 6 inches. Graphene grown on a large scale substrate was passivated and sealed with a gold layer, protecting graphene from any possible contaminant and keeping good electrical contact. The Au/graphene was transferred by the tension-assisted transfer process without polymer residues. The gold film itself was used directly as the electrodes of a Schottky diode. We demonstrated wafer-scale integration of graphene/silicon Schottky diode using the proposed transfer process. The transmission electron microscopy analysis and relatively low ideality factor of the diodes indicated fewer defects on the interface than those obtained using the conventional poly(methyl methacrylate)-assisted transfer method. We further demonstrated gas sensors as an application of graphene Schottky diodes.

  2. Silica-sol-based spin-coating barrier layer against phosphorous diffusion for crystalline silicon solar cells.

    Science.gov (United States)

    Uzum, Abdullah; Fukatsu, Ken; Kanda, Hiroyuki; Kimura, Yutaka; Tanimoto, Kenji; Yoshinaga, Seiya; Jiang, Yunjian; Ishikawa, Yasuaki; Uraoka, Yukiharu; Ito, Seigo

    2014-01-01

    The phosphorus barrier layers at the doping procedure of silicon wafers were fabricated using a spin-coating method with a mixture of silica-sol and tetramethylammonium hydroxide, which can be formed at the rear surface prior to the front phosphorus spin-on-demand (SOD) diffusion and directly annealed simultaneously with the front phosphorus layer. The optimization of coating thickness was obtained by changing the applied spin-coating speed; from 2,000 to 8,000 rpm. The CZ-Si p-type silicon solar cells were fabricated with/without using the rear silica-sol layer after taking the sheet resistance measurements, SIMS analysis, and SEM measurements of the silica-sol material evaluations into consideration. For the fabrication of solar cells, a spin-coating phosphorus source was used to form the n(+) emitter and was then diffused at 930°C for 35 min. The out-gas diffusion of phosphorus could be completely prevented by spin-coated silica-sol film placed on the rear side of the wafers coated prior to the diffusion process. A roughly 2% improvement in the conversion efficiency was observed when silica-sol was utilized during the phosphorus diffusion step. These results can suggest that the silica-sol material can be an attractive candidate for low-cost and easily applicable spin-coating barrier for any masking purpose involving phosphorus diffusion.

  3. Carbon mediated reduction of silicon dioxide and growth of copper silicide particles in uniform width channels

    DEFF Research Database (Denmark)

    Pizzocchero, Filippo; Bøggild, Peter; Booth, Tim

    2013-01-01

    channels, which are aligned with the intersections of the (100) surface of the wafer and the {110} planes on an oxidized silicon wafer, as well as endotaxial copper silicide nanoparticles within the wafer bulk. We apply energy dispersive x-ray spectroscopy, in combination with scanning and transmission......We show that surface arc-discharge deposited carbon plays a critical intermediary role in the breakdown of thermally grown oxide diffusion barriers of 90 nm on a silicon wafer at 1035°C in an Ar/H2 atmosphere, resulting in the formation of epitaxial copper silicide particles in ≈ 10 μm wide...

  4. Silicon Strip Detectors for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Miñano, M; The ATLAS collaboration

    2011-01-01

    While the Large Hadron Collider (LHC) at CERN is continuing to deliver an ever-increasing luminosity to the experiments, plans for an upgraded machine called High Luminosity LHC (HL-LHC) are progressing. The upgrade is foreseen to increase the LHC design luminosity up to 5 x 1034 cm-2 s-1. The ATLAS experiment will need to build a new tracker for HL operation, which would cope with the increase in pile-up backgrounds at the higher luminosity. A new generation of extremely radiation hard silicon detectors is being designed. Silicon sensors with sufficient radiation hardness are the subject of an international R&D programme, working on pixel and strip sensors. The efforts presented here concentrate on the innermost strip layers. We have developed a large number of prototype planar detectors produced on p-type wafers in a number of different designs. The irradiated sensors were subsequently tested in order to study the radiation-induced degradation, and determine their performance after irradiation of up to ...

  5. New methodology for through silicon via array macroinspection

    Science.gov (United States)

    Fujimori, Yoshihiko; Tsuto, Takashi; Kudo, Yuji; Inoue, Takeshi; Suwa, Kyoichi; Okamoto, Kazuya

    2013-01-01

    A new methodology for inspection of through silicon via (TSV) process wafers is developed by utilizing an optical diffraction signal from the wafers. The optical system uses telecentric illumination and has a two-dimensional sensor for capturing the diffracted light from TSV arrays. The diffraction signal modulates the intensity of the wafer image. The optical configuration is optimized for TSV array inspection. The diffraction signal is sensitive to via-shape variations, and an area of deviation from a nominal via is analyzed using the signal. Using test wafers with deep via patterns on silicon wafers, the performance is evaluated and the sensitivities for various pattern profile changes are confirmed. This new methodology is available for high-volume manufacturing of future TSV three-dimensional complementary metal oxide semiconductor devices.

  6. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  7. Design of P-Type Cladding Layers for Tunnel-Injected UVA Light Emitting Diodes

    CERN Document Server

    Zhang, Yuewei; Akyol, Fatih; Allerman, Andrew A; Moseley, Michael W; Armstrong, Andrew M; Rajan, Siddharth

    2016-01-01

    We discuss the engineering of p-AlGaN cladding layers for achieving efficient tunnel-injected III-Nitride ultraviolet light emitting diodes (UV LEDs) in the UV-A spectral range. We show that capacitance-voltage measurements can be used to estimate the compensation and doping in p-AlGaN layers located between the multi-quantum well region and the tunnel junction layer. By increasing the p-type doping concentration to overcome the background compensation, on-wafer external quantum efficiency and wall-plug efficiency of 3.37% and 1.62% were achieved for tunnel-injected UV LEDs emitting at 325 nm. We also show that interband tunneling hole injection can be used to realize UV LEDs without any acceptor doping. The work discussed here provides new understanding of hole doping and transport in AlGaN-based UV LEDs, and demonstrates the excellent performance of tunnel-injected LEDs for the UV-A wavelength range.

  8. Phosphorus out-diffusion in laser molten silicon

    Energy Technology Data Exchange (ETDEWEB)

    Köhler, J. R.; Eisele, S. J. [Institut für Photovoltaik (ipv), Universität Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart (Germany)

    2015-04-14

    Laser doping via liquid phase diffusion enables the formation of defect free pn junctions and a tailoring of diffusion profiles by varying the laser pulse energy density and the overlap of laser pulses. We irradiate phosphorus diffused 100 oriented p-type float zone silicon wafers with a 5 μm wide line focused 6.5 ns pulsed frequency doubled Nd:YVO{sub 4} laser beam, using a pulse to pulse overlap of 40%. By varying the number of laser scans N{sub s} = 1, 2, 5, 10, 20, 40 at constant pulse energy density H = 1.3 J/cm{sup 2} and H = 0.79 J/cm{sup 2} we examine the out-diffusion of phosphorus atoms performing secondary ion mass spectroscopy concentration measurements. Phosphorus doping profiles are calculated by using a numerical simulation tool. The tool models laser induced melting and re-solidification of silicon as well as the out-diffusion of phosphorus atoms in liquid silicon during laser irradiation. We investigate the observed out-diffusion process by comparing simulations with experimental concentration measurements. The result is a pulse energy density independent phosphorus out-diffusion velocity v{sub out} = 9 ± 1 cm/s in liquid silicon, a partition coefficient of phosphorus 1 < k{sub p} < 1.1 and a diffusion coefficient D = 1.4(±0.2)cm{sup 2}/s × 10{sup −3 }× exp[−183 meV/(k{sub B}T)].

  9. TEM investigation of silicon carbide wafers with reduced micropipe density

    Science.gov (United States)

    Saddow, S. E.; Schattner, T. E.; Shamsuzzoha, M.; Rendakova, S. V.; Dmitriev, V. A.

    2000-03-01

    A technique to reduce the micropipe density in SiC substrates by first filling in the defects and then growing an LPE layer on the filled material has been developed by TDI. LPE growth in SiC is known to result in poor surface morphology, namely step-bunching due to the off-axis substrate orientation. Chemical vapor deposition (CVD) growth experiments on SiC substrates with reduced micropipe density using a cold-wall CVD reactor resulted in a significant improvement in the surface morphology. Although preliminary device results are encouraging, the exact nature of the filled micropipes nor the impact of growing CVD epitaxial layers on LPE SiC had not been fully characterized. We have preformed transmission electron microscopy (TEM) measurements to evaluate the crystallographic properties of the CVD/LPE and LPE/substrate interface. It was observed that no new dislocations were nucleated at the LPE/CVD interface. Although a micropipe was not located in the samples characterized, a tilt of 1.5° was observed between the LPE layer and the substrate. In addition, dislocations were observed to propagate through the LPE layer from the substrate which are most likely the 1C close-core screw dislocations common to SiC hexagonal substrates.

  10. Switchable static friction of piezoelectric composite-silicon wafer contacts

    NARCIS (Netherlands)

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  11. Switchable static friction of piezoelectric composite—silicon wafer contacts

    NARCIS (Netherlands)

    Van den Ende, D.A.; Fischer, H.R.; Groen, W.A.; Van der Zwaag, S.

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  12. Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

    Science.gov (United States)

    2014-08-01

    used adhesion promoter, Silane A-174, was applied to the surface of the sample just prior to placing it in a parylene coater. From the equipment point...pores, allowed to dry, and followed by a coating of parylene film. The NaClO4 solution is hygroscopic in nature and tends to absorb moisture from the

  13. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  14. Modelling deformation and fracture in confectionery wafers

    Science.gov (United States)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  15. Lipid membranes on nanostructured silicon.

    Energy Technology Data Exchange (ETDEWEB)

    Slade, Andrea Lynn; Lopez, Gabriel P. (University of New Mexico, Albuquerque, NM); Ista, Linnea K. (University of New Mexico, Albuquerque, NM); O' Brien, Michael J. (University of New Mexico, Albuquerque, NM); Sasaki, Darryl Yoshio; Bisong, Paul (University of New Mexico, Albuquerque, NM); Zeineldin, Reema R. (University of New Mexico, Albuquerque, NM); Last, Julie A.; Brueck, Stephen R. J. (University of New Mexico, Albuquerque, NM)

    2004-12-01

    A unique composite nanoscale architecture that combines the self-organization and molecular dynamics of lipid membranes with a corrugated nanotextured silicon wafer was prepared and characterized with fluorescence microscopy and scanning probe microscopy. The goal of this project was to understand how such structures can be assembled for supported membrane research and how the interfacial interactions between the solid substrate and the soft, self-assembled material create unique physical and mechanical behavior through the confinement of phases in the membrane. The nanometer scale structure of the silicon wafer was produced through interference lithography followed by anisotropic wet etching. For the present study, a line pattern with 100 nm line widths, 200 nm depth and a pitch of 360 nm pitch was fabricated. Lipid membranes were successfully adsorbed on the structured silicon surface via membrane fusion techniques. The surface topology of the bilayer-Si structure was imaged using in situ tapping mode atomic force microscopy (AFM). The membrane was observed to drape over the silicon structure producing an undulated topology with amplitude of 40 nm that matched the 360 nm pitch of the silicon structure. Fluorescence recovery after photobleaching (FRAP) experiments found that on the microscale those same structures exhibit anisotropic lipid mobility that was coincident with the silicon substructure. The results showed that while the lipid membrane maintains much of its self-assembled structure in the composite architecture, the silicon substructure indeed influences the dynamics of the molecular motion within the membrane.

  16. Flexible Thermoelectric Generators on Silicon Fabric

    KAUST Repository

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  17. Genesis Ultrapure Water Megasonic Wafer Spin Cleaner

    Science.gov (United States)

    Allton, Judith H.; Stansbery, Eileen K.; Calaway, Michael J.; Rodriquez, Melissa C.

    2013-01-01

    A device removes, with high precision, the majority of surface particle contamination greater than 1-micron-diameter in size from ultrapure semiconductor wafer materials containing implanted solar wind samples returned by NASA's Genesis mission. This cleaning device uses a 1.5-liter/minute flowing stream of heated ultrapure water (UPW) with 1- MHz oscillating megasonic pulse energy focused at 3 to 5 mm away from the wafer surface spinning at 1,000 to 10,000 RPM, depending on sample size. The surface particle contamination is removed by three processes: flowing UPW, megasonic cavitations, and centripetal force from the spinning wafer. The device can also dry the wafer fragment after UPW/megasonic cleaning by continuing to spin the wafer in the cleaning chamber, which is purged with flowing ultrapure nitrogen gas at 65 psi (.448 kPa). The cleaner also uses three types of vacuum chucks that can accommodate all Genesis-flown array fragments in any dimensional shape between 3 and 100 mm in diameter. A sample vacuum chuck, and the manufactured UPW/megasonic nozzle holder, replace the human deficiencies by maintaining a consistent distance between the nozzle and wafer surface as well as allowing for longer cleaning time. The 3- to 5-mm critical distance is important for the ability to remove particles by megasonic cavitations. The increased UPW sonication time and exposure to heated UPW improve the removal of 1- to 5-micron-sized particles.

  18. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination...

  19. LASER ABLATION OF MONOCRYSTALLINE SILICON UNDER PULSED-FREQUENCY FIBER LASER

    Directory of Open Access Journals (Sweden)

    V. P. Veiko

    2015-05-01

    Full Text Available Subject of research. The paper deals with research of the surface ablation for single-crystal silicon wafers and properties of materials obtained in response to silicon ablation while scanning beam radiation of pulse fiber ytterbium laser with a wavelenght λ = 1062 nm in view of variation of radiation power and scanning modes. Method. Wafers of commercial p-type conductivity silicon doped with boron (111, n-type conductivity silicon doped with phosphorus (100 have been under research with a layer of intrinsical silicon oxide having the thickness equal to several 10 s of nanometers and SiO2 layer thickness from 120 to 300 nm grown by thermal oxidation method. The learning system comprises pulse fiber ytterbium laser with a wavelenght λ = 1062 nm. The laser rated-power output is equal to 20 W, pulse length is 100 ns. Pulses frequency is in the range from 20 kHz to 100 kHz. Rated energy in the pulse is equal to 1.0 mJ. Scanning has been carried out by means of two axial scanning device driven by VM2500+ and controlled by personal computer with «SinMarkТМ» software package. Scanning velocity is in the range from 10 mm/s to 4000 mm/s, the covering varies from 100 lines per mm to 3000 lines per mm. Control of samples has been carried out by means of Axio Imager A1m optical microscope Carl Zeiss production with a high definition digital video camera. All experiments have been carried out in the mode of focused laser beam with a radiation spot diameter at the substrate equal to 50 μm. The change of temperature and its distribution along the surface have been evaluated by FLIR IR imager of SC7000 series. Main results. It is shown that ablation occurs without silicon melting and with plasma torch origination. The particles of ejected silicon take part in formation of silicon ions plasma and atmosphere gases supporting the plasmo-chemical growth of SiO2. The range of beam scanning modes is determined where the growth of SiO2 layer is observed

  20. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    Energy Technology Data Exchange (ETDEWEB)

    Bai, Fan; Li, Meicheng, E-mail: mcli@ncepu.edu.cn [Harbin Institute of Technology, School of Materials Science and Engineering (China); Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing [North China Electric Power University, State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, School of Renewable Energy (China)

    2013-09-15

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO{sub 2} produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO{sub 2} located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications.

  1. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    Science.gov (United States)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  2. The development of an inspection system for defects in silicon crystal growth

    Science.gov (United States)

    Liu, Ya-Cheng; Tsai, Hsin-Yi; Hung, Min-Wei; Huang, Kuo-Cheng

    2013-03-01

    This study presents an inspection system to detect the growth defects of silicon crystals that comprise a CCD camera, an LED light source, and power modulation. The defects on multicrystalline silicon can be observed clearly while the silicon wafer were irradiated by the red LED light at a small lighting angle (i.e., 20-30°). However, the growth defects on monocrystalline silicon wafer were difficult to observe because of it low image intensity. And then, the growth defects image was significantly enhanced when the wafer was illuminated by a white LED (WLED) and rotated at a specific angle (i.e., 23°). The experimental results showed that the WLED illumination system made the growth defects more easily observable than did other LED sources (i.e., red, blue, and green LEDs). In addition, the proposed inspection system can be used for on-line fast detection for quality control of monocrystalline silicon wafer.

  3. Floating Silicon Method

    Energy Technology Data Exchange (ETDEWEB)

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  4. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  5. Influence of Immersion Lithography on Wafer Edge Defectivity

    OpenAIRE

    Jami, K.; Pollentier, I.; Vedula, S; Blumenstock, G

    2010-01-01

    In this paper, we investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to inspection of the flat top part of the wafer edge due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. Our study used a new automated edge inspection system that provides full wafer edge imaging and automatic defect classification. The work revealed several key challenges to controlling wafer edge-...

  6. Quasi-perpetual discharge behaviour in p-type Ge-air batteries.

    Science.gov (United States)

    Ocon, Joey D; Kim, Jin Won; Abrenica, Graniel Harne A; Lee, Jae Kwang; Lee, Jaeyoung

    2014-11-07

    Metal-air batteries continue to become attractive energy storage and conversion systems due to their high energy and power densities, safer chemistries, and economic viability. Semiconductor-air batteries - a term we first define here as metal-air batteries that use semiconductor anodes such as silicon (Si) and germanium (Ge) - have been introduced in recent years as new high-energy battery chemistries. In this paper, we describe the excellent doping-dependent discharge kinetics of p-type Ge anodes in a semiconductor-air cell employing a gelled KOH electrolyte. Owing to its Fermi level, n-type Ge is expected to have lower redox potential and better electronic conductivity, which could potentially lead to a higher operating voltage and better discharge kinetics. Nonetheless, discharge measurements demonstrated that this prediction is only valid at the low current regime and breaks down at the high current density region. The p-type Ge behaves extremely better at elevated currents, evident from the higher voltage, more power available, and larger practical energy density from a very long discharge time, possibly arising from the high overpotential for surface passivation. A primary semiconductor-air battery, powered by a flat p-type Ge as a multi-electron anode, exhibited an unprecedented full discharge capacity of 1302.5 mA h gGe(-1) (88% anode utilization efficiency), the highest among semiconductor-air cells, notably better than new metal-air cells with three-dimensional and nanostructured anodes, and at least two folds higher than commercial Zn-air and Al-air cells. We therefore suggest that this study be extended to doped-Si anodes, in order to pave the way for a deeper understanding on the discharge phenomena in alkaline metal-air conversion cells with semiconductor anodes for specific niche applications in the future.

  7. Silicon-micromachined microchannel plates

    CERN Document Server

    Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

  8. Nickel Electroless Plating: Adhesion Analysis for Mono-Type Crystalline Silicon Solar Cells.

    Science.gov (United States)

    Shin, Eun Gu; Rehman, Atteq ur; Lee, Sang Hee; Lee, Soo Hong

    2015-10-01

    The adhesion of the front electrodes to silicon substrate is the most important parameters to be optimized. Nickel silicide which is formed by sintering process using a silicon substrate improves the mechanical and electrical properties as well as act as diffusion barrier for copper. In this experiment p-type mono-crystalline czochralski (CZ) silicon wafers having resistivity of 1.5 Ω·cm were used to study one step and two step nickel electroless plating process. POCl3 diffusion process was performed to form the emitter with the sheet resistance of 70 ohm/sq. The Six, layer was set down as an antireflection coating (ARC) layer at emitter surface by plasma enhanced chemical vapor deposition (PECVD) process. Laser ablation process was used to open SiNx passivation layer locally for the formation of the front electrodes. Nickel was deposited by electroless plating process by one step and two step nickel electroless deposition process. The two step nickel plating was performed by applying a second nickel deposition step subsequent to the first sintering process. Furthermore, the adhesion analysis for both one step and two steps process was conducted using peel force tester (universal testing machine, H5KT) after depositing Cu contact by light induced plating (LIP).

  9. Development of wafers with lowered glycemic index

    Directory of Open Access Journals (Sweden)

    N. N. Popova

    2016-01-01

    Full Text Available The negative impact on an organism is made by lack of culture of food of the population and low physical activity. It leads to violations of carbohydrate and lipidic exchange, development of obesity, diabetes, cardiovascular and other diseases. Relevance of development of foodstuff, in particular – the confectionery promoting decrease in risk of developing of such pathologies is proved. A research objective – development of a compounding of wafers with the lowered glycemic index. As an object of a research the wafers baked in house conditions are chosen. In work various characteristics are analysed (hygroscopicity, a cariogenicity sweet degree, power value, a glicemic index and a glycemic response the sweetening substances, the choice of fructose as sugar substitute for production of wafers with the lowered glycemic index is reasonable. By optimization of a compounding of wafers the amount of sugar was replaced with amount of sweetener, equivalent on sweet. As a result of predesigns the interval of a variation of amount of the fructose entered into a compounding of wafers is established. Further assessment of the indicators of quality forming consumer demand of products – appearance, taste, a smell, existence of a crunch is carried out. Humidity of the received wafers after their production and in the course of storage is also investigated. Decrease in a glycemic index was fixed by amount of glucose in blood. Its measurements saw by means of the glucose meter "on an empty stomach" and after the use of wafers to a complete recovery of level of sugar in blood. The confectionery made on the optimized compounding practically doesn't differ on caloric content from a control sample, and glucose level in blood after their use on about 20% below.

  10. One-step synthesis of lightly doped porous silicon nanowires in HF/AgNO{sub 3}/H{sub 2}O{sub 2} solution at room temperature

    Energy Technology Data Exchange (ETDEWEB)

    Bai, Fan [School of Materials Science and Engineering, Harbin Institute of Technology, Harbin 165001 (China); State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power University, Beijing 102206 (China); Li, Meicheng, E-mail: mcli@ncepu.edu.cn [State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power University, Beijing 102206 (China); Su Zhou Institute, North China Electric Power University, Suzhou 215123 (China); Song, Dandan; Yu, Hang; Jiang, Bing; Li, Yingfeng [State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources, North China Electric Power University, Beijing 102206 (China)

    2012-12-15

    One-step synthesis of lightly doped porous silicon nanowire arrays was achieved by etching the silicon wafer in HF/AgNO{sub 3}/H{sub 2}O{sub 2} solution at room temperature. The lightly doped porous silicon nanowires (pNWs) have circular nanopores on the sidewall, which can emit strong green fluorescence. The surface morphologies of these nanowires could be controlled by simply adjusting the concentration of H{sub 2}O{sub 2}, which influences the distribution of silver nanoparticles (Ag NPs) along the nanowire axis. A mechanism based on Ag NPs-induced lateral etching of nanowires was proposed to explain the formation of pNWs. The controllable and widely applicable synthesis of pNWs will open their potential application to nanoscale photoluminescence devices. - Graphical abstract: The one-step synthesis of porous silicon nanowire arrays is achieved by chemical etching of the lightly doped p-type Si (100) wafer at room temperature. These nanowires exhibit strong green photoluminescence. SEM, TEM, HRTEM and photoluminescence images of pNWs. The scale bars of SEM, TEM HRTEM and photoluminescence are 10 {mu}m, 20 nm, 10 nm, and 1 {mu}m, respectively. Highlights: Black-Right-Pointing-Pointer Simple one-step synthesis of lightly doped porous silicon nanowire arrays is achieved at RT. Black-Right-Pointing-Pointer Etching process and mechanism are illustrated with etching model from a novel standpoint. Black-Right-Pointing-Pointer As-prepared porous silicon nanowire emits strong green fluorescence, proving unique property.

  11. Very low surface recombination velocity on p-type c-Si by high-rate plasma-deposited aluminum oxide

    Science.gov (United States)

    Saint-Cast, Pierre; Kania, Daniel; Hofmann, Marc; Benick, Jan; Rentsch, Jochen; Preu, Ralf

    2009-10-01

    Aluminum oxide layers can provide excellent passivation for lowly and highly doped p-type silicon surfaces. Fixed negative charges induce an accumulation layer at the p-type silicon interface, resulting in very effective field-effect passivation. This paper presents highly negatively charged (Qox=-2.1×1012 cm-2) aluminum oxide layers produced using an inline plasma-enhanced chemical vapor deposition system, leading to very low effective recombination velocities (˜10 cm s-1) on low-resistivity p-type substrates. A minimum static deposition rate (100 nm min-1) at least one order of magnitude higher than atomic layer deposition was achieved on a large carrier surfaces (˜1 m2) without significantly reducing the resultant passivation quality.

  12. Silicon infrared diffuser for wireless communication

    Science.gov (United States)

    Massera, Ettore; Rea, Ilaria; Nasti, Ivana; Maddalena, Pasqualino; di Francia, Girolamo

    2006-09-01

    We show what we believe to be a novel way to use silicon in infrared radio communication as a suitable material for the realization of optical diffusers in the range of 850-1600 nm. A crystalline silicon wafer is made porous by means of electrochemical etching. The porous silicon produced is optically characterized, and measurements report a high reflectance in the band of interest. We also study the angular distribution of diffused radiation by the porous silicon surface at different angles of incident radiation. Measurements show that radiation diffuses in a quasi-Lambertian manner, confirming the good performance of this material as an incident radiation diffuser.

  13. Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling

    Science.gov (United States)

    Choi, Young Sin; Nam, Young Sun; Lee, Dong Han; Lee, Jae Il; Kang, Young Seog; Jang, Se Yeon; Kong, Jeong Heung

    2016-03-01

    As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry's preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement. In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer's behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

  14. Development in p-type Doping of ZnO

    Institute of Scientific and Technical Information of China (English)

    YU Liping; ZHU Qiqiang; FAN Dayong; LAN Zili

    2012-01-01

    Zinc oxide (ZnO) is a wide band-gap material of the Ⅱ-Ⅵ group with excellent optical properties for optoelectronics applications,such as the flat panel displays and solar cells used in sports tournament.Despite its advantages,the application of ZnO is hampered by the lack of stable p-type doping.In this paper,the recent progress in this field was briefly reviewed,and a comprehensive summary of the research was carried out on ZnO fabrication methods and its electrical,optical,and magnetic properties were presented.

  15. P-type conductivity in annealed strontium titanate

    Energy Technology Data Exchange (ETDEWEB)

    Poole, Violet M.; Corolewski, Caleb D.; McCluskey, Matthew D., E-mail: mattmcc@wsu.edu [Department of Physics and Astronomy, Washington State University, Pullman, WA 99164-2814 (United States)

    2015-12-15

    Hall-effect measurements indicate p-type conductivity in bulk, single-crystal strontium titanate (SrTiO{sub 3}, or STO) samples that were annealed at 1200°C. Room-temperature mobilities above 100 cm{sup 2}/V s were measured, an order of magnitude higher than those for electrons (5-10 cm{sup 2}/V s). Average hole densities were in the 10{sup 9}-10{sup 10} cm{sup −3} range, consistent with a deep acceptor.

  16. Bi-Se doped with Cu, p-type semiconductor

    Science.gov (United States)

    Bhattacharya, Raghu Nath; Phok, Sovannary; Parilla, Philip Anthony

    2013-08-20

    A Bi--Se doped with Cu, p-type semiconductor, preferably used as an absorber material in a photovoltaic device. Preferably the semiconductor has at least 20 molar percent Cu. In a preferred embodiment, the semiconductor comprises at least 28 molar percent of Cu. In one embodiment, the semiconductor comprises a molar percentage of Cu and Bi whereby the molar percentage of Cu divided by the molar percentage of Bi is greater than 1.2. In a preferred embodiment, the semiconductor is manufactured as a thin film having a thickness less than 600 nm.

  17. Fracture mechanics analysis on Smart-Cut(R) technology. Part 1: Effects of stiffening wafer and defect interaction

    Institute of Scientific and Technical Information of China (English)

    Bin Gu; Hongyuan Liu; YiuWing Mai; Xi Qiao Feng; Shou Wen Yu

    2009-01-01

    In the present paper, continuum fracture mecha-nics is used to analyze the Smart-Cut process, a recently established ion cut technology which enables highly efficient fabrication of various silicon-on-insulator (SO1) wafers of high uniformity in thickness. Using integral transform and Cauchy singular integral equation methods, the mode-Ⅰ and mode-II stress intensity factors, energy release rate, and crack opening displacements are derived in order to examine seve-ral important fracture mechanisms involved in the Smart-Cut process. The effects of defect interaction and stiffening wafer on defect growth are investigated. The numerical results indi-cate that a stiffener/handle wafer can effectively prevent the donor wafer from blistering and exfoliation, but it slows down the defect growth by decreasing the magnitudes of SIF's. Defect interaction also plays an important role in the splitting process of SOI wafers, but its contribution depends strongly on the size, interval and internal pressure of defects. Finally, an analytical formula is derived to estimate the implantation dose required for splitting a SOI wafer.

  18. Analysis of the interdigitated back contact solar cells:The n-type substrate lifetime and wafer thickness

    Institute of Scientific and Technical Information of China (English)

    张巍; 陈晨; 贾锐; 孙昀; 邢钊; 金智; 刘新宇; 刘晓文

    2015-01-01

    The n-type silicon integrated-back contact (IBC) solar cell has attracted much attention due to its high efficiency, whereas its performance is very sensitive to the wafer of low quality or the contamination during high temperature fab-rication processing, which leads to low bulk lifetimeτbulk. In order to clarify the influence of bulk lifetime on cell char-acteristics, two-dimensional (2D) TCAD simulation, combined with our experimental data, is used to simulate the cell performances, with the wafer thickness scaled down under variousτbulk conditions. The modeling results show that for the IBC solar cell with highτbulk, (such as 1 ms–2 ms), its open-circuit voltage Voc almost remains unchanged, and the short-circuit current density Jsc monotonically decreases as the wafer thickness scales down. In comparison, for the solar cell with lowτbulk (for instance,<500 µs) wafer or the wafer contaminated during device processing, the Voc increases monotonically but the Jsc first increases to a maximum value and then drops off as the wafer’s thickness decreases. A model combing the light absorption and the minority carrier diffusion is used to explain this phenomenon. The research results show that for the wafer with thinner thickness and high bulk lifetime, the good light trapping technology must be developed to offset the decrease in Jsc.

  19. Characterization of solar-grade silicon produced by the SiF4-Na process

    Science.gov (United States)

    Sanjurjo, A.; Sancier, K. M.; Emerson, R. M.; Leach, S. C.; Minahan, J.

    1986-01-01

    A process was developed for producing low cost solar grade silicon by the reaction between SiF4 gas and sodium metal. The results of the characterization of the silicon are presented. These results include impurity levels, electronic properties of the silicon after crystal growth, and the performance of solar photovoltaic cells fabricated from wafers of the single crystals. The efficiency of the solar cells fabricated from semiconductor silicon and SiF4-Na silicon was the same.

  20. Full-field wafer warpage measurement technique

    Science.gov (United States)

    Hsieh, H. L.; Lee, J. Y.; Huang, Y. G.; Liang, A. J.; Sun, B. Y.

    2017-06-01

    An innovative moiré technique for full-field wafer warpage measurement is proposed in this study. The wafer warpage measurement technique is developed based on moiré method, Talbot effect, scanning profiling method, stroboscopic, instantaneous phase-shift method, as well as four-step phase shift method, high resolution, high stability and full-field measurement capabilities can be easily achieved. According to the proposed full-field optical configuration, a laser beam is expanded into a collimated beam with a 2-inch diameter and projected onto the wafer surface. The beam is reflected by the wafer surface and forms a moiré fringe image after passing two circular gratings, which is then focused and captured on a CCD camera for computation. The corresponding moiré fringes reflected from the wafer surface are obtained by overlapping the images of the measuring grating and the reference grating. The moiré fringes will shift when wafer warpage occurs. The phase of the moiré fringes will change proportionally to the degree of warpage in the wafer, which can be measured by detecting variations in the phase shift of the moiré fringes in each detection points on the surface of the entire wafer. The phase shift variations of each detection points can be calculated via the instantaneous phase-shift method and the four-step phase-shift method. By adding up the phase shift variations of each detection points along the radii of the circular gratings, the warpage value and surface topography of the wafer can be obtained. Experiments show that the proposed method is capable of obtaining test results similar to that of a commercial sensor, as well as performing accurate measurements under high speed rotation of 1500rpm. As compared to current warpage measurement methods such as the beam optical method, confocal microscopy, laser interferometry, shadow moiré method, and structured light method, this proposed technique has the advantage of full-field measurement, high