WorldWideScience

Sample records for oxide semiconductor cmos

  1. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    Wang, Zhenwei

    2015-04-20

    In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

  2. High-temperature complementary metal oxide semiconductors (CMOS)

    McBrayer, J.D.

    1979-10-01

    Silicon CMOS devices were studied, tested, and evaluated at high temperatures to determine processing, geometric, operating characteristics, and stability parameters. After more than 1000 hours at 300 0 C, most devices showed good stability, reliability, and operating characteristics. Processing and geometric parameters were evaluated and optimization steps discussed

  3. Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

    Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, Mohamed N.; Alshareef, Husam N.

    2015-01-01

    , which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin

  4. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    Nayak, Pradipta K.

    2014-04-14

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

  5. A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

    2014-01-01

    ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

  6. Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

    Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, Mohamed N.; Wang, Q. X.; Alshareef, Husam N.

    2014-01-01

    We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling

  7. Oxide semiconductors

    Svensson, Bengt G; Jagadish, Chennupati

    2013-01-01

    Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scient

  8. Design of 5.8 GHz Integrated Antenna on 180nm Complementary Metal Oxide Semiconductor (CMOS) Technology

    Razak, A. H. A.; Shamsuddin, M. I. A.; Idros, M. F. M.; Halim, A. K.; Ahmad, A.; Junid, S. A. M. Al

    2018-03-01

    This project discusses the design and simulation performances of integrated loop antenna. Antenna is one of the main parts in any wireless radio frequency integrated circuit (RFIC). Naturally, antenna is the bulk in any RFIC design. Thus, this project aims to implement an integrated antenna on a single chip making the end product more compact. This project targets 5.8 GHz as the operating frequency of the integrated antenna for a transceiver module based on Silterra CMOS 180nm technology. The simulation of the antenna was done by using High Frequency Structure Simulator (HFSS). This software is industrial standard software that been used to simulate all electromagnetic effect including antenna simulation. This software has ability to simulate frequency at range of 100 MHz to 4 THz. The simulation set up in 3 dimension structure with driven terminal. The designed antenna has 1400um of diameter and placed on top metal layer. Loop configuration of the antenna has been chosen as the antenna design. From the configuration, it is able to make the chip more compact. The simulation shows that the antenna has single frequency band at center frequency 5.8 GHz with -48.93dB. The antenna radiation patterns shows, the antenna radiate at omnidirectional. From the simulation result, it could be concluded that the antenna have a good radiation pattern and propagation for wireless communication.

  9. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  10. Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

    Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

    2012-07-01

    In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

  11. Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

    Shojan P. Pavunny

    2014-03-01

    Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

  12. Decal electronics for printed high performance cmos electronic systems

    Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

    2017-01-01

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

  13. Absorbed dose by a CMOS in radiotherapy

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  14. Conductivity in transparent oxide semiconductors.

    King, P D C; Veal, T D

    2011-08-24

    Despite an extensive research effort for over 60 years, an understanding of the origins of conductivity in wide band gap transparent conducting oxide (TCO) semiconductors remains elusive. While TCOs have already found widespread use in device applications requiring a transparent contact, there are currently enormous efforts to (i) increase the conductivity of existing materials, (ii) identify suitable alternatives, and (iii) attempt to gain semiconductor-engineering levels of control over their carrier density, essential for the incorporation of TCOs into a new generation of multifunctional transparent electronic devices. These efforts, however, are dependent on a microscopic identification of the defects and impurities leading to the high unintentional carrier densities present in these materials. Here, we review recent developments towards such an understanding. While oxygen vacancies are commonly assumed to be the source of the conductivity, there is increasing evidence that this is not a sufficient mechanism to explain the total measured carrier concentrations. In fact, many studies suggest that oxygen vacancies are deep, rather than shallow, donors, and their abundance in as-grown material is also debated. We discuss other potential contributions to the conductivity in TCOs, including other native defects, their complexes, and in particular hydrogen impurities. Convincing theoretical and experimental evidence is presented for the donor nature of hydrogen across a range of TCO materials, and while its stability and the role of interstitial versus substitutional species are still somewhat open questions, it is one of the leading contenders for yielding unintentional conductivity in TCOs. We also review recent work indicating that the surfaces of TCOs can support very high carrier densities, opposite to the case for conventional semiconductors. In thin-film materials/devices and, in particular, nanostructures, the surface can have a large impact on the total

  15. Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

    Almuslem, A. S.; Hanna, Amir; Yapici, Tahir; Wehbe, N.; Diallo, Elhadj; Kutbee, Arwa T.; Bahabry, Rabab R.; Hussain, Muhammad Mustafa

    2017-01-01

    , in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured

  16. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  17. Ultralow-loss CMOS copper plasmonic waveguides

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  18. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... and display ultrasensitive mass detection in air. A mass sensitivity of 4 ag/Hz has been determined in air by placing a single glycerine drop, having a measured weight of 57 fg, at the apex of a cantilever and subsequently measuring a frequency shift of 14.8 kHz. CMOS integration enables electrostatic...

  19. P-type Oxide Semiconductors for Transparent & Energy Efficient Electronics

    Wang, Zhenwei

    2018-03-11

    Emerging transparent semiconducting oxide (TSO) materials have achieved their initial commercial success in the display industry. Due to the advanced electrical performance, TSOs have been adopted either to improve the performance of traditional displays or to demonstrate the novel transparent and flexible displays. However, due to the lack of feasible p-type TSOs, the applications of TSOs is limited to unipolar (n-type TSOs) based devices. Compared with the prosperous n-type TSOs, the performance of p-type counterparts is lag behind. However, after years of discovery, several p-type TSOs are confirmed with promising performance, for example, tin monoxide (SnO). By using p-type SnO, excellent transistor field-effect mobility of 6.7 cm2 V-1 s-1 has been achieved. Motivated by this encouraging performance, this dissertation is devoted to further evaluate the feasibility of integrating p-type SnO in p-n junctions and complementary metal oxide semiconductor (CMOS) devices. CMOS inverters are fabricated using p-type SnO and in-situ formed n-type tin dioxide (SnO2). The semiconductors are simultaneously sputtered, which simplifies the process of CMOS inverters. The in-situ formation of SnO2 phase is achieved by selectively sputtering additional capping layer, which serves as oxygen source and helps to balance the process temperature for both types of semiconductors. Oxides based p-n junctions are demonstrated between p-type SnO and n-type SnO2 by magnetron sputtering method. Diode operating ideality factor of 3.4 and rectification ratio of 103 are achieved. A large temperature induced knee voltage shift of 20 mV oC-1 is observed, and explained by the large band gap and shallow states in SnO, which allows minor adjustment of band structure in response to the temperature change. Finally, p-type SnO is used to demonstrating the hybrid van der Waals heterojunctions (vdWHs) with two-dimensional molybdenum disulfide (2D MoS2) by mechanical exfoliation. The hybrid vdWHs show

  20. CMOS/SOS processing

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  1. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    Paul C. McIntyre

    2012-07-01

    Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  2. JPL CMOS Active Pixel Sensor Technology

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  3. The effect of body bias of the metal-oxide-semiconductor field-effect transistor in the resistive network on spatial current distribution in a bio-inspired complementary metal-oxide-semiconductor vision chip

    Kong, Jae-Sung; Hyun, Hyo-Young; Seo, Sang-Ho; Shin, Jang-Kyoo

    2008-11-01

    Complementary metal-oxide-semiconductor (CMOS) vision chips for edge detection based on a resistive circuit have recently been developed. These chips help in the creation of neuromorphic systems of a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends predominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the metal-oxide-semiconductor field-effect transistor for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160 × 120 CMOS vision chips have been fabricated using a standard CMOS technology. The experimental results nicely match our prediction.

  4. DNA-decorated carbon-nanotube-based chemical sensors on complementary metal oxide semiconductor circuitry

    Chen, Chia-Ling; Yang, Chih-Feng; Dokmeci, Mehmet R; Agarwal, Vinay; Sonkusale, Sameer; Kim, Taehoon; Busnaina, Ahmed; Chen, Michelle

    2010-01-01

    We present integration of single-stranded DNA (ss-DNA)-decorated single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry as nanoscale chemical sensors. SWNTs were assembled onto CMOS circuitry via a low voltage dielectrophoretic (DEP) process. Besides, bare SWNTs are reported to be sensitive to various chemicals, and functionalization of SWNTs with biomolecular complexes further enhances the sensing specificity and sensitivity. After decorating ss-DNA on SWNTs, we have found that the sensing response of the gas sensor was enhanced (up to ∼ 300% and ∼ 250% for methanol vapor and isopropanol alcohol vapor, respectively) compared with bare SWNTs. The SWNTs coupled with ss-DNA and their integration on CMOS circuitry demonstrates a step towards realizing ultra-sensitive electronic nose applications.

  5. Semiconductor

    2000-01-01

    This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

  6. Recent Developments in p-Type Oxide Semiconductor Materials and Devices

    Wang, Zhenwei

    2016-02-16

    The development of transparent p-type oxide semiconductors with good performance may be a true enabler for a variety of applications where transparency, power efficiency, and greater circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, here, recent developments in materials and devices based on p-type oxide semiconductors are reviewed, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides, and nickel oxides. The crystal and electronic structures of these materials are discussed, along with approaches to enhance valence-band dispersion to reduce effective mass and increase mobility. Strategies to reduce interfacial defects, off-state current, and material instability are suggested. Furthermore, it is shown that promising progress has been made in the performance of various types of devices based on p-type oxides. Several innovative approaches exist to fabricate transparent complementary metal oxide semiconductor (CMOS) devices, including novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains. However, despite recent developments, p-type oxides still lag in performance behind their n-type counterparts, which have entered volume production in the display market. Recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented.

  7. Recent Developments in p-Type Oxide Semiconductor Materials and Devices

    Wang, Zhenwei; Nayak, Pradipta K.; Caraveo-Frescas, Jesus Alfonso; Alshareef, Husam N.

    2016-01-01

    The development of transparent p-type oxide semiconductors with good performance may be a true enabler for a variety of applications where transparency, power efficiency, and greater circuit complexity are needed. Such applications include transparent electronics, displays, sensors, photovoltaics, memristors, and electrochromics. Hence, here, recent developments in materials and devices based on p-type oxide semiconductors are reviewed, including ternary Cu-bearing oxides, binary copper oxides, tin monoxide, spinel oxides, and nickel oxides. The crystal and electronic structures of these materials are discussed, along with approaches to enhance valence-band dispersion to reduce effective mass and increase mobility. Strategies to reduce interfacial defects, off-state current, and material instability are suggested. Furthermore, it is shown that promising progress has been made in the performance of various types of devices based on p-type oxides. Several innovative approaches exist to fabricate transparent complementary metal oxide semiconductor (CMOS) devices, including novel device fabrication schemes and utilization of surface chemistry effects, resulting in good inverter gains. However, despite recent developments, p-type oxides still lag in performance behind their n-type counterparts, which have entered volume production in the display market. Recent successes along with the hurdles that stand in the way of commercial success of p-type oxide semiconductors are presented.

  8. Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

    Kim, Y; Pham, C; Chang, J P

    2015-01-01

    This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal–oxide–semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the

  9. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  10. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  11. CMOS MEMS Fabrication Technologies and Devices

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  12. Absorbed dose by a CMOS in radiotherapy

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  13. Transparent Oxide Semiconductors for Emerging Electronics

    Caraveo-Frescas, Jesus Alfonso

    2013-11-01

    Transparent oxide electronics have emerged as promising materials to shape the future of electronics. While several n-type oxides have been already studied and demonstrated feasibility to be used as active materials in thin film transistors, high performance p-type oxides have remained elusive. This dissertation is devoted to the study of transparent p-type oxide semiconductor tin monoxide and its use in the fabrication of field effect devices. A complete study on the deposition of tin monoxide thin films by direct current reactive magnetron sputtering is performed. Carrier density, carrier mobility and conductivity are studied over a set of deposition conditions where p-type conduction is observed. Density functional theory simulations are performed in order to elucidate the effect of native defects on carrier mobility. The findings on the electrical properties of SnO thin films are then translated to the fabrication of thin films transistors. The low processing temperature of tin monoxide thin films below 200 oC is shown advantageous for the fabrication of fully transparent and flexible thin film transistors. After careful device engineering, including post deposition annealing temperature, gate dielectric material, semiconductor thickness and source and drain electrodes material, thin film transistors with record device performance are demonstrated, achieving a field effect mobility >6.7 cm2V-1s-1. Device performance is further improved to reach a field effect mobility of 10.8 cm2V-1s-1 in SnO nanowire field effect transistors fabricated from the sputtered SnO thin films and patterned by electron beam lithography. Downscaling device dimension to nano scale is shown beneficial for SnO field effect devices not only by achieving a higher hole mobility but enhancing the overall device performance including better threshold voltage, subthreshold swing and lower number of interfacial defects. Use of p-type semiconductors in nonvolatile memory applications is then

  14. CMOS Active-Pixel Image Sensor With Simple Floating Gates

    Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

    1996-01-01

    Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

  15. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

  16. Laser line scan underwater imaging by complementary metal-oxide-semiconductor camera

    He, Zhiyi; Luo, Meixing; Song, Xiyu; Wang, Dundong; He, Ning

    2017-12-01

    This work employs the complementary metal-oxide-semiconductor (CMOS) camera to acquire images in a scanning manner for laser line scan (LLS) underwater imaging to alleviate backscatter impact of seawater. Two operating features of the CMOS camera, namely the region of interest (ROI) and rolling shutter, can be utilized to perform image scan without the difficulty of translating the receiver above the target as the traditional LLS imaging systems have. By the dynamically reconfigurable ROI of an industrial CMOS camera, we evenly divided the image into five subareas along the pixel rows and then scanned them by changing the ROI region automatically under the synchronous illumination by the fun beams of the lasers. Another scanning method was explored by the rolling shutter operation of the CMOS camera. The fun beam lasers were turned on/off to illuminate the narrow zones on the target in a good correspondence to the exposure lines during the rolling procedure of the camera's electronic shutter. The frame synchronization between the image scan and the laser beam sweep may be achieved by either the strobe lighting output pulse or the external triggering pulse of the industrial camera. Comparison between the scanning and nonscanning images shows that contrast of the underwater image can be improved by our LLS imaging techniques, with higher stability and feasibility than the mechanically controlled scanning method.

  17. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  18. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

    2015-01-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

  19. Neutron absorbed dose in a pacemaker CMOS

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  20. Neutron absorbed dose in a pacemaker CMOS

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  1. Resolution limits achievable with CMOS front-end in X- and γ-ray analysis with semiconductor detectors

    Manfredi, P.F.; Manghisoni, M.; Ratti, L.; Re, V.; Speziali, V.

    2003-01-01

    During the past 15 years, the CMOS technologies have provided the most widely followed approach to signal processing with microstrip detectors. In more recent times, CMOS front-end systems have been developed to acquire and process signals from pixel detectors. During the past few years, the favor toward CMOS processes in their applications in the broad area of detector signal processing has been enhanced by the technological advancement known as device scaling and by two aspects connected to it. One is the shrinking in channel length L into the deep submicron region. The second one is the related reduction in the gate-oxide thickness t ox to a few nm. The reduction in t ox has, as a consequence of primary importance, a decreased 1/f-noise contribution to the equivalent noise charge (ENC). The thinner gate-oxide and the shrinking in gate length, in some regions of operations, concur to increase the transconductance of the device, which results in a smaller ENC contribution from channel thermal noise. The goal of the present paper is to address the question of whether or not the most advanced CMOS processes may meet the requirements set by high resolution, high dynamic range applications like the energy-dispersive photon analysis with solid-state detectors of comparatively large capacitance

  2. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  3. Electrical Interconnections Through CMOS Wafers

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  4. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Hussain, Muhammad Mustafa; Hussain, Aftab M.; Hanna, Amir

    2016-01-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today

  5. Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

    Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

    2011-02-22

    Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

  6. Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process.

    Mehta, Karan K; Orcutt, Jason S; Shainline, Jeffrey M; Tehar-Zahav, Ofer; Sternberg, Zvi; Meade, Roy; Popović, Miloš A; Ram, Rajeev J

    2014-02-15

    We present measurements on resonant photodetectors utilizing sub-bandgap absorption in polycrystalline silicon ring resonators, in which light is localized in the intrinsic region of a p+/p/i/n/n+ diode. The devices, operating both at λ=1280 and λ=1550  nm and fabricated in a complementary metal-oxide-semiconductor (CMOS) dynamic random-access memory emulation process, exhibit detection quantum efficiencies around 20% and few-gigahertz response bandwidths. We observe this performance at low reverse biases in the range of a few volts and in devices with dark currents below 50 pA at 10 V. These results demonstrate that such photodetector behavior, previously reported by Preston et al. [Opt. Lett. 36, 52 (2011)], is achievable in bulk CMOS processes, with significant improvements with respect to the previous work in quantum efficiency, dark current, linearity, bandwidth, and operating bias due to additional midlevel doping implants and different material deposition. The present work thus offers a robust realization of a fully CMOS-fabricated all-silicon photodetector functional across a wide wavelength range.

  7. Radiation response of two Harris semiconductor radiation hardened 1k CMOS RAMs

    Abare, W.E.; Huffman, D.D.; Moffett, G.E.

    1982-01-01

    This paper describes the testing of two types 1K CMOS static RAMs in various transient and steady state ionizing radiation environments. Type HM 6551R (256x4 bits) and type HM 6508R (1024x1 bit) RAMs were evaluated. The RAMs are radiation hardened versions of Harris' commercial RAMs. A brief description of the radiation hardened process is presented

  8. CMOS Integrated Carbon Nanotube Sensor

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  9. Epitaxy of Polar Oxides and Semiconductors

    Shelton, Christopher Tyrel

    Integrating polar oxide materials with wide-bandgap nitride semiconductors offers the possibility of a tunable 2D carrier gas (2DCG) - provided defect densities are low and interfaces are abrupt. This dissertation investigates a portion of the synthesis science necessary to produce a "semiconductor-grade" interface between these highly dissimilar materials. A significant portion of this work is aligned with efforts to engineer a step-free GaN substrate to produce single in-plane oriented rocksalt oxide films. Initially, we explore the homoepitaxial MOCVD growth conditions necessary to produce highquality GaN films on ammonothermally grown substrates. Ammono substrates are only recently available for purchase and are the market leader in low-dislocation density material. Their novelty requires development of an understanding of morphology trade-offs in processing space. This includes preservation of the epi-polished surface in aggressive MOCVD environments and an understanding of the kinetic barriers affecting growth morphologies. Based on several factors, it was determined that GaN exhibits an 'uphill' diffusion bias that may likely be ascribed to a positive Ehrlich-Schwoebel (ES) barrier. This barrier should have a stabilizing effect against step-bunching but, for many growth conditions, regular step bunching was observed. One possible explanation for the step-bunching instability is the presence of impurities. Experimentally, conditions which incorporate more carbon into GaN homoepitaxial layers are correlated with step-bunching while conditions that suppress carbon produce bilayer stepped morphologies. These observations lead us to the conclusion that GaN homoepitaxial morphology is a competition between impurity induced step-bunching and a stabilizing diffusion bias due to a positive ES barrier. Application of the aforementioned homoepitaxial growth techniques to discrete substrate regions using selected- and confined area epitaxy (SAE,CAE) produces some

  10. Nanoscale Metal Oxide Semiconductors for Gas Sensing

    Hunter, Gary W.; Evans, Laura; Xu, Jennifer C.; VanderWal, Randy L.; Berger, Gordon M.; Kulis, Michael J.

    2011-01-01

    A report describes the fabrication and testing of nanoscale metal oxide semiconductors (MOSs) for gas and chemical sensing. This document examines the relationship between processing approaches and resulting sensor behavior. This is a core question related to a range of applications of nanotechnology and a number of different synthesis methods are discussed: thermal evaporation- condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed, providing a processing overview to developers of nanotechnology- based systems. The results of a significant amount of testing and comparison are also described. A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. The TECsynthesized single-crystal nanowires offer uniform crystal surfaces, resistance to sintering, and their synthesis may be done apart from the substrate. The TECproduced nanowire response is very low, even at the operating temperature of 200 C. In contrast, the electrospun polycrystalline nanofiber response is high, suggesting that junction potentials are superior to a continuous surface depletion layer as a transduction mechanism for chemisorption. Using a catalyst deposited upon the surface in the form of nanoparticles yields dramatic gains in sensitivity for both nanostructured, one-dimensional forms. For the nanowire materials, the response magnitude and response rate uniformly increase with increasing operating temperature. Such changes are interpreted in terms of accelerated surface diffusional processes, yielding greater access to chemisorbed oxygen species and faster dissociative chemisorption, respectively. Regardless of operating temperature, sensitivity of the nanofibers is a factor of 10 to 100 greater than that of nanowires with the same catalyst for the same test condition. In summary, nanostructure appears critical to governing the reactivity, as measured by electrical

  11. Broadband image sensor array based on graphene-CMOS integration

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  12. Total-ionizing-dose effects on isolation oxides in modern CMOS technologies

    Barnaby, Hugh J.; Mclain, Michael; Esqueda, Ivan Sanchez

    2007-01-01

    This paper presents experimental data on the total dose response of deep sub-micron bulk CMOS devices and integrated circuits. Ionizing radiation experiments on shallow trench isolation (STI) field oxide MOS capacitors (FOXCAP) indicate a characteristic build-up of radiation-induced defects in the dielectric. In this paper, capacitors fabricated with STI, thermal, SIMOX and bipolar base oxides of similar thickness are compared and show the STI oxide to be most susceptible to radiation effects. Experimental data on irradiated shift registers and n-channel MOSFETs are also presented. These data indicate that radiation damage to the STI can increase the off-state current of n-channel devices and the standby current of CMOS integrated circuits

  13. Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

    Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

    2009-01-01

    This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

  14. Determination of Insulator-to-Semiconductor Transition in Sol-Gel Oxide Semiconductors Using Derivative Spectroscopy.

    Lee, Woobin; Choi, Seungbeom; Kim, Kyung Tae; Kang, Jingu; Park, Sung Kyu; Kim, Yong-Hoon

    2015-12-23

    We report a derivative spectroscopic method for determining insulator-to-semiconductor transition during sol-gel metal-oxide semiconductor formation. When an as-spun sol-gel precursor film is photochemically activated and changes to semiconducting state, the light absorption characteristics of the metal-oxide film is considerable changed particularly in the ultraviolet region. As a result, a peak is generated in the first-order derivatives of light absorption ( A' ) vs. wavelength (λ) plots, and by tracing the peak center shift and peak intensity, transition from insulating-to-semiconducting state of the film can be monitored. The peak generation and peak center shift are described based on photon-energy-dependent absorption coefficient of metal-oxide films. We discuss detailed analysis method for metal-oxide semiconductor films and its application in thin-film transistor fabrication. We believe this derivative spectroscopy based determination can be beneficial for a non-destructive and a rapid monitoring of the insulator-to-semiconductor transition in sol-gel oxide semiconductor formation.

  15. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

  16. Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

    León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

    2018-05-01

    We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

  17. High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

    Sevilla, Galo T.

    2016-02-29

    Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

  18. Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

    Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

    2017-05-02

    Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

  19. Anisotropy-based crystalline oxide-on-semiconductor material

    McKee, Rodney Allen; Walker, Frederick Joseph

    2000-01-01

    A semiconductor structure and device for use in a semiconductor application utilizes a substrate of semiconductor-based material, such as silicon, and a thin film of a crystalline oxide whose unit cells are capable of exhibiting anisotropic behavior overlying the substrate surface. Within the structure, the unit cells of the crystalline oxide are exposed to an in-plane stain which influences the geometric shape of the unit cells and thereby arranges a directional-dependent quality of the unit cells in a predisposed orientation relative to the substrate. This predisposition of the directional-dependent quality of the unit cells enables the device to take beneficial advantage of characteristics of the structure during operation. For example, in the instance in which the crystalline oxide of the structure is a perovskite, a spinel or an oxide of similarly-related cubic structure, the structure can, within an appropriate semiconductor device, exhibit ferroelectric, piezoelectric, pyroelectric, electro-optic, ferromagnetic, antiferromagnetic, magneto-optic or large dielectric properties that synergistically couple to the underlying semiconductor substrate.

  20. Amphoteric oxide semiconductors for energy conversion devices: a tutorial review.

    Singh, Kalpana; Nowotny, Janusz; Thangadurai, Venkataraman

    2013-03-07

    In this tutorial review, we discuss the defect chemistry of selected amphoteric oxide semiconductors in conjunction with their significant impact on the development of renewable and sustainable solid state energy conversion devices. The effect of electronic defect disorders in semiconductors appears to control the overall performance of several solid-state ionic devices that include oxide ion conducting solid oxide fuel cells (O-SOFCs), proton conducting solid oxide fuel cells (H-SOFCs), batteries, solar cells, and chemical (gas) sensors. Thus, the present study aims to assess the advances made in typical n- and p-type metal oxide semiconductors with respect to their use in ionic devices. The present paper briefly outlines the key challenges in the development of n- and p-type materials for various applications and also tries to present the state-of-the-art of defect disorders in technologically related semiconductors such as TiO(2), and perovskite-like and fluorite-type structure metal oxides.

  1. SEMICONDUCTOR INTEGRATED CIRCUITS: A high performance 90 nm CMOS SAR ADC with hybrid architecture

    Xingyuan, Tong; Jianming, Chen; Zhangming, Zhu; Yintang, Yang

    2010-01-01

    A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 × 214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

  2. Semiconductor photocatalysts for water oxidation: current status and challenges.

    Yang, Lingling; Zhou, Han; Fan, Tongxiang; Zhang, Di

    2014-04-21

    Artificial photosynthesis is a highly-promising strategy to convert solar energy into hydrogen energy for the relief of the global energy crisis. Water oxidation is the bottleneck for its kinetic and energetic complexity in the further enhancement of the overall efficiency of the artificial photosystem. Developing efficient and cost-effective photocatalysts for water oxidation is a growing desire, and semiconductor photocatalysts have recently attracted more attention due to their stability and simplicity. This article reviews the recent advancement of semiconductor photocatalysts with a focus on the relationship between material optimization and water oxidation efficiency. A brief introduction to artificial photosynthesis and water oxidation is given first, followed by an explanation of the basic rules and mechanisms of semiconductor particulate photocatalysts for water oxidation as theoretical references for discussions of componential, surface structure, and crystal structure modification. O2-evolving photocatalysts in Z-scheme systems are also introduced to demonstrate practical applications of water oxidation photocatalysts in artificial photosystems. The final part proposes some challenges based on the dynamics and energetics of photoholes which are fundamental to the enhancement of water oxidation efficiency, as well as on the simulation of natural water oxidation that will be a trend in future research.

  3. Transparent Oxide Semiconductors for Emerging Electronics

    Caraveo-Frescas, Jesus Alfonso

    2013-01-01

    Transparent oxide electronics have emerged as promising materials to shape the future of electronics. While several n-type oxides have been already studied and demonstrated feasibility to be used as active materials in thin film transistors, high

  4. Development of a CMOS process using high energy ion implantation

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  5. Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

    Hussain, Aftab M.; Singh, Nirpendra; Fahad, Hossain M.; Rader, Kelly; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2014-01-01

    We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well

  6. Metal/oxide/semiconductor interface investigated by monoenergetic positrons

    Uedono, A.; Tanigawa, S.; Ohji, Y.

    1988-10-01

    Variable-energy positron-beam studies have been carried out for the first time on a metal/oxide/semiconductor (MOS) structure of polycrystalline Si/SiO 2/Si-substrate. We were successful in collecting injected positrons at the SiO 2/Si interface by the application of an electric field between the MOS electrodes.

  7. Positron studies of metal-oxide-semiconductor structures

    Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

    1993-03-01

    Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

  8. Variation-aware advanced CMOS devices and SRAM

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  9. Decal electronics for printed high performance cmos electronic systems

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  10. CMOS circuit design, layout and simulation

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  11. Metal oxide semiconductor thin-film transistors for flexible electronics

    Petti, Luisa; Vogt, Christian; Büthe, Lars; Cantarella, Giuseppe; Tröster, Gerhard [Electronics Laboratory, Swiss Federal Institute of Technology, Zürich (Switzerland); Münzenrieder, Niko [Electronics Laboratory, Swiss Federal Institute of Technology, Zürich (Switzerland); Sensor Technology Research Centre, University of Sussex, Falmer (United Kingdom); Faber, Hendrik; Bottacchi, Francesca; Anthopoulos, Thomas D. [Department of Physics and Centre for Plastic Electronics, Imperial College London, London (United Kingdom)

    2016-06-15

    The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In

  12. Where science fiction meets reality? With oxide semiconductors.

    Fortunato, E.; Martins, R. [CENIMAT/I3N, Departamento de Ciencia dos Materiais, Faculdade de Ciencias e Tecnologia, FCT, Universidade Nova de Lisboa, CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2011-09-15

    Transparent electronics is today one of the most advanced topics for a wide range of device applications, where the key components are wide band gap semiconductors, where oxides of different origin play an important role, not only as passive components but also as active components similar to what we observe in conventional semiconductors. As passive components they include the use of these materials as dielectrics for a wide range of electronic devices and also as transparent electrical conductors for use in several optoelectronic applications, such as liquid crystal displays, organic light emitting diodes, solar cells, optical sensors etc. As active materials, they exploit the use of truly electronic semiconductors where the main emphasis is being put on transparent thin film transistors, light emitting diodes, lasers, ultraviolet sensors and integrated circuits among others. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  13. Simulation of the selective oxidation process of semiconductors

    Chahoud, M.

    2012-01-01

    A new approach to simulate the selective oxidation of semiconductors is presented. This approach is based on the so-called b lack box simulation method . This method is usually used to simulate complex processes. The chemical and physical details within the process are not considered. Only the input and output data of the process are relevant for the simulation. A virtual function linking the input and output data has to be found. In the case of selective oxidation the input data are the mask geometry and the oxidation duration whereas the output data are the oxidation thickness distribution. The virtual function is determined as four virtual diffusion processes between the masked und non-masked areas. Each process delivers one part of the oxidation profile. The method is applied successfully on the oxidation system silicon-silicon nitride (Si-Si 3 N 4 ). The fitting parameters are determined through comparison of experimental and simulation results two-dimensionally.(author)

  14. First experimental results on CMOS Integrated Nickel Electroplated Resonators

    Yalcinkaya, Arda Deniz; Hansen, Ole

    2004-01-01

    This paper presents experimental results on MEMS metallic add-on post-fabrication effects on complementary metal oxide semiconductor (CMOS) transistors. Two versions of add-on processing, that use either e-beam evaporation or magnetron sputtering, are compared through investigation of the electri...

  15. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche

  16. Positron Studies of Oxide-Semiconductor Structures

    Uedono , A.; Wei , L.; Kawano , T.; Tanigawa , S.; Suzuki , R.; Ohgaki , H.; Mikado , T.

    1995-01-01

    The annihilation characteristics of positrons in SiO2 films grown on Si substrates were studied by using monoenergetic positron beams. Doppler broadening profiles of the annihilation radiation and lifetime spectra of positrons were measured as a function of incident positron energy for SiO2/Si structures fabricated by various oxidation techniques. From the measurements, it was found that the formation probability of positronium (Ps) atoms in SiO2 films strongly depends on the growth condition...

  17. Integrating Metal-Oxide-Decorated CNT Networks with a CMOS Readout in a Gas Sensor

    Suhwan Kim

    2012-02-01

    Full Text Available We have implemented a tin-oxide-decorated carbon nanotube (CNT network gas sensor system on a single die. We have also demonstrated the deposition of metallic tin on the CNT network, its subsequent oxidation in air, and the improvement of the lifetime of the sensors. The fabricated array of CNT sensors contains 128 sensor cells for added redundancy and increased accuracy. The read-out integrated circuit (ROIC was combined with coarse and fine time-to-digital converters to extend its resolution in a power-efficient way. The ROIC is fabricated using a 0.35 µm CMOS process, and the whole sensor system consumes 30 mA at 5 V. The sensor system was successfully tested in the detection of ammonia gas at elevated temperatures.

  18. Advanced CMOS Radiation Effects Testing and Analysis

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; hide

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  19. Aging sensor for CMOS memory cells

    Santos, Hugo Fernandes da Silva

    2016-01-01

    Dissertação de Mestrado, Engenharia e Tecnologia, Instituto Superior de Engenharia, Universidade do Algarve, 2016 As memórias Complementary Metal Oxide Semiconductor (CMOS) ocupam uma percentagem de área significativa nos circuitos integrados e, com o desenvolvimento de tecnologias de fabrico a uma escala cada vez mais reduzida, surgem problemas de performance e de fiabilidade. Efeitos como o BTI (Bias Thermal Instability), TDDB (Time Dependent Dielectric Breakdown), HCI (Hot Carrier Injec...

  20. Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

    McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

    2000-01-01

    A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

  1. Ion traps fabricated in a CMOS foundry

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  2. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    Ghoneim, Mohamed T.

    2015-06-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

  3. Efficient demodulation scheme for rolling-shutter-patterning of CMOS image sensor based visible light communications.

    Chen, Chia-Wei; Chow, Chi-Wai; Liu, Yang; Yeh, Chien-Hung

    2017-10-02

    Recently even the low-end mobile-phones are equipped with a high-resolution complementary-metal-oxide-semiconductor (CMOS) image sensor. This motivates using a CMOS image sensor for visible light communication (VLC). Here we propose and demonstrate an efficient demodulation scheme to synchronize and demodulate the rolling shutter pattern in image sensor based VLC. The implementation algorithm is discussed. The bit-error-rate (BER) performance and processing latency are evaluated and compared with other thresholding schemes.

  4. Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

    Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

    2015-07-16

    We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.

  5. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  6. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  8. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  9. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  10. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  11. Ultrasonic fingerprint sensor using a piezoelectric micromachined ultrasonic transducer array integrated with complementary metal oxide semiconductor electronics

    Lu, Y.; Fung, S.; Wang, Q.; Horsley, D. A. [Berkeley Sensor and Actuator Center, University of California, Davis, 1 Shields Avenue, Davis, California 95616 (United States); Tang, H.; Boser, B. E. [Berkeley Sensor and Actuator Center, University of California, Berkeley, California 94720 (United States); Tsai, J. M.; Daneman, M. [InvenSense, Inc., 1745 Technology Drive, San Jose, California 95110 (United States)

    2015-06-29

    This paper presents an ultrasonic fingerprint sensor based on a 24 × 8 array of 22 MHz piezoelectric micromachined ultrasonic transducers (PMUTs) with 100 μm pitch, fully integrated with 180 nm complementary metal oxide semiconductor (CMOS) circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. The array frequency response and vibration mode-shape were characterized using laser Doppler vibrometry and verified via finite element method simulation. The array's acoustic output was measured using a hydrophone to be ∼14 kPa with a 28 V input, in reasonable agreement with predication from analytical calculation. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20 × 8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D polydimethylsiloxane fingerprint phantom (10 mm × 8 mm) at a 1.2 mm distance from the array.

  12. Ultrawide band gap amorphous oxide semiconductor, Ga–Zn–O

    Kim, Junghwan, E-mail: JH.KIM@lucid.msl.titech.ac.jp [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Miyokawa, Norihiko; Sekiya, Takumi; Ide, Keisuke [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Toda, Yoshitake [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Hiramatsu, Hidenori; Hosono, Hideo; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan)

    2016-09-01

    We fabricated amorphous oxide semiconductor films, a-(Ga{sub 1–x}Zn{sub x})O{sub y}, at room temperature on glass, which have widely tunable band gaps (E{sub g}) ranging from 3.47–4.12 eV. The highest electron Hall mobility ~ 7 cm{sup 2} V{sup −1} s{sup −1} was obtained for E{sub g} = ~ 3.8 eV. Ultraviolet photoemission spectroscopy revealed that the increase in E{sub g} with increasing the Ga content comes mostly from the deepening of the valence band maximum level while the conduction band minimum level remains almost unchanged. These characteristics are explained by their electronic structures. As these films can be fabricated at room temperature on plastic, this achievement extends the applications of flexible electronics to opto-electronic integrated circuits associated with deep ultraviolet region. - Highlights: • Incorporation of H/H{sub 2}O stabilizes the amorphous phase. • Ultrawide band gap (~ 3.8 eV) amorphous oxide semiconductor was fabricated. • The increase in band gap comes mostly from the deepening of the valence band maximum level. • Donor level is more likely aligned to the valence band maximum level.

  13. Binary copper oxide semiconductors: From materials towards devices

    Meyer, B.K.; Polity, A.; Reppin, D.; Becker, M.; Hering, P.; Klar, P.J.; Sander, T.; Reindl, C.; Benz, J.; Eickhoff, M.; Heiliger, C.; Heinemann, M. [1. Physics Institute, Justus-Liebig University of Giessen (Germany); Blaesing, J.; Krost, A. [Institute of Experimental Physics (IEP), Otto-von-Guericke University Magdeburg (Germany); Shokovets, S. [Institute of Physics, Ilmenau University of Technology (Germany); Mueller, C.; Ronning, C. [Institute of Solid State Physics, Friedrich Schiller University Jena (Germany)

    2012-08-15

    Copper-oxide compound semiconductors provide a unique possibility to tune the optical and electronic properties from insulating to metallic conduction, from bandgap energies of 2.1 eV to the infrared at 1.40 eV, i.e., right into the middle of the efficiency maximum for solar-cell applications. Three distinctly different phases, Cu{sub 2}O, Cu{sub 4}O{sub 3}, and CuO, of this binary semiconductor can be prepared by thin-film deposition techniques, which differ in the oxidation state of copper. Their material properties as far as they are known by experiment or predicted by theory are reviewed. They are supplemented by new experimental results from thin-film growth and characterization, both will be critically discussed and summarized. With respect to devices the focus is on solar-cell performances based on Cu{sub 2}O. It is demonstrated by photoelectron spectroscopy (XPS) that the heterojunction system p-Cu{sub 2}O/n-AlGaN is much more promising for the application as efficient solar cells than that of p-Cu{sub 2}O/n-ZnO heterojunction devices that have been favored up to now. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  14. Toward CMOS image sensor based glucose monitoring.

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2012-09-07

    Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

  15. CMOS Time-Resolved, Contact, and Multispectral Fluorescence Imaging for DNA Molecular Diagnostics

    Nan Guo

    2014-10-01

    Full Text Available Instrumental limitations such as bulkiness and high cost prevent the fluorescence technique from becoming ubiquitous for point-of-care deoxyribonucleic acid (DNA detection and other in-field molecular diagnostics applications. The complimentary metal-oxide-semiconductor (CMOS technology, as benefited from process scaling, provides several advanced capabilities such as high integration density, high-resolution signal processing, and low power consumption, enabling sensitive, integrated, and low-cost fluorescence analytical platforms. In this paper, CMOS time-resolved, contact, and multispectral imaging are reviewed. Recently reported CMOS fluorescence analysis microsystem prototypes are surveyed to highlight the present state of the art.

  16. Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition

    Kelly, David Quest

    After the integrated circuit was invented in 1959, complementary metal-oxide-semiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. Although not yet in production, high-kappa dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicon-germanium (Si1-xGe x), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-kappa dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strain-relaxed Si1- xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge 1-yCy layers on Si for the fabrication

  17. Electro-mechanical coupling of semiconductor film grown on stainless steel by oxidation

    Lin, M. C.; Wang, G.; Guo, L. Q.; Qiao, L. J.; Volinsky, Alex A.

    2013-09-01

    Electro-mechanical coupling phenomenon in oxidation film on stainless steel has been discovered by using current-sensing atomic force microscopy, along with the I-V curves measurements. The oxidation films exhibit either ohmic, n-type, or p-type semiconductor properties, according to the obtained I-V curves. This technique allows characterizing oxidation films with high spatial resolution. Semiconductor properties of oxidation films must be considered as additional stress corrosion cracking mechanisms.

  18. Neutron absorbed dose in a pacemaker CMOS

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  19. A divalent rare earth oxide semiconductor: Yttrium monoxide

    Kaminaga, Kenichi; Sei, Ryosuke [Department of Chemistry, The University of Tokyo, Tokyo 113-0033 (Japan); Department of Chemistry, Tohoku University, Sendai 980-8578 (Japan); Hayashi, Kouichi [Department of Environmental and Materials Engineering, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Happo, Naohisa [School of Information Sciences, Hiroshima City University, Hiroshima 731-3194 (Japan); Tajiri, Hiroo [Japan Synchrotron Radiation Research Institute (JASRI)/SPring-8, Sayo 679-5198 (Japan); Oka, Daichi; Fukumura, Tomoteru, E-mail: tomoteru.fukumura.e4@tohoku.ac.jp [Department of Chemistry, Tohoku University, Sendai 980-8578 (Japan); Hasegawa, Tetsuya [Department of Chemistry, The University of Tokyo, Tokyo 113-0033 (Japan)

    2016-03-21

    Rare earth oxides are usually widegap insulators like Y{sub 2}O{sub 3} with closed shell trivalent rare earth ions. In this study, solid phase rock salt structure yttrium monoxide, YO, with unusual valence of Y{sup 2+} (4d{sup 1}) was synthesized in a form of epitaxial thin film by pulsed laser deposition method. YO has been recognized as gaseous phase in previous studies. In contrast with Y{sub 2}O{sub 3}, YO was dark-brown colored and narrow gap semiconductor. The tunable electrical conductivity ranging from 10{sup −1} to 10{sup 3} Ω{sup −1 }cm{sup −1} was attributed to the presence of oxygen vacancies serving as electron donor. Weak antilocalization behavior observed in magnetoresistance indicated significant role of spin-orbit coupling as a manifestation of 4d electron carrier.

  20. Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

    Bratkovsky, A M [Hewlett-Packard Laboratories, 1501 Page Mill Road, MS 1123, Palo Alto, CA 94304 (United States)

    2008-02-15

    Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

  1. Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

    Bratkovsky, A M

    2008-01-01

    Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field

  2. Spintronic effects in metallic, semiconductor, metal oxide and metal semiconductor heterostructures

    Bratkovsky, A. M.

    2008-02-01

    Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

  3. CMOS/SOS RAM transient radiation upset and ''inversion'' effect investigation

    Nikiforov, A.Y.; Poljakov, I.V.

    1996-01-01

    The Complementary Metal-Oxide-Semiconductor/Silicon-on-Sapphire Random Access Memory (CMOS/SOS RAM) transient upset and inversion effect were investigated with pulsed laser, pulsed voltage generator and low-intensity light simulators. It was found that the inversion of information occurs due to memory cell photocurrents simultaneously with the power supply voltage drop transfer to memory cells outputs

  4. CMOS Active-Pixel Image Sensor With Intensity-Driven Readout

    Langenbacher, Harry T.; Fossum, Eric R.; Kemeny, Sabrina

    1996-01-01

    Proposed complementary metal oxide/semiconductor (CMOS) integrated-circuit image sensor automatically provides readouts from pixels in order of decreasing illumination intensity. Sensor operated in integration mode. Particularly useful in number of image-sensing tasks, including diffractive laser range-finding, three-dimensional imaging, event-driven readout of sparse sensor arrays, and star tracking.

  5. CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

    Fossum, Eric R.

    1996-01-01

    The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

  6. Cu2O-based solar cells using oxide semiconductors

    Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

    2016-01-01

    We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu 2 O heterojunction solar cells fabricated using p-type Cu 2 O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu 2 O sheets under various deposition conditions using a pulsed laser deposition method. In Cu 2 O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa 2 O 4 thin-film layer. In most of the Cu 2 O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga 2 O 3 -Al 2 O 3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (V oc ) were obtained by using a relatively small amount of MgO or Al 2 O 3 , e.g., (ZnO) 0.91 –(MgO) 0.09 and (Ga 2 O 3 ) 0.975 –(Al 2 O 3 ) 0.025 , respectively. When Cu 2 O-based heterojunction solar cells were fabricated using Al 2 O 3 –Ga 2 O 3 –MgO–ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high V oc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu 2 O heterojunction solar cells fabricated using Na-doped Cu 2 O (Cu 2 O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a V oc of 0.84 V were obtained in a MgF 2 /AZO/n-(Ga 2 O 3 –Al 2 O 3 )/p-Cu 2 O:Na heterojunction solar cell fabricated using

  7. Cu2O-based solar cells using oxide semiconductors

    Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

    2016-01-01

    We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu2O heterojunction solar cells fabricated using p-type Cu2O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu2O sheets under various deposition conditions using a pulsed laser deposition method. In Cu2O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa2O4 thin-film layer. In most of the Cu2O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga2O3-Al2O3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (Voc) were obtained by using a relatively small amount of MgO or Al2O3, e.g., (ZnO)0.91-(MgO)0.09 and (Ga2O3)0.975-(Al2O3)0.025, respectively. When Cu2O-based heterojunction solar cells were fabricated using Al2O3-Ga2O3-MgO-ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high Voc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu2O heterojunction solar cells fabricated using Na-doped Cu2O (Cu2O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a Voc of 0.84 V were obtained in a MgF2/AZO/n-(Ga2O3-Al2O3)/p-Cu2O:Na heterojunction solar cell fabricated using a Cu2O:Na sheet with a resistivity of approximately 10 Ω·cm and a (Ga0.975Al0

  8. Group IIB-VIA semiconductor oxide cluster ions

    Jayasekharan, Thankan

    2018-05-01

    Metal oxide cluster ions, MnOm± (M = Zn, Cd) and HgnOm- of various stoichiometry have been generated from solid IIB-VIA semiconductor oxides targets, (ZnO(s), CdO(s), and HgO(s)) by using pulse laser desorption ionization time of flight mass spectrometry with a laser of λ = 355 nm. Analysis of mass spectral data indicates the formation of stoichiometric cluster ions viz., (ZnO)n=1-30+ and (CdO)n=1-40+ along with -O bound anions, (ZnO)n=1-30O-, (CdO)n=1-40O- and (HgO)n=1-36O- from their respective solids. Further, metal oxoanions such as ZnOn=2,3-, CdOn=2,3,6-, and HgOn=2,3,6,7- have also been noted signifying the higher coordination ability of both Cd and Hg with O/O2/O3 species.

  9. VLSI scaling methods and low power CMOS buffer circuit

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  10. Oxide Ferromagnetic Semiconductors for Spin-Electronic Transprt

    Pandey, R.K.

    2008-01-01

    The objective of this research was to investigate the viability of oxide magnetic semiconductors as potential materials for spintronics. We identified some members of the solid solution series of ilmenite (FeTiO3) and hematite (Fe2O3), abbreviated as (IH) for simplicity, for our investigations based on their ferromagnetic and semiconducting properties. With this objective in focus we limited our investigations to the following members of the modified Fe-titanates: IH33 (ilmenitehematite with 33 atomic percent hematite), IH45 (ilmenite-hematite with 45 atomic percent hematite), Mn-substituted ilmenite (Mn-FeTiO3), and Mn-substituted pseudobrookite (Mn- Fe2TiO5). All of them are: (1) wide bandgap semiconductors with band gaps ranging in values between 2.5 to 3.5 eV; (2) n-type semiconductors; (3) they exhibit well defined magnetic hysteresis loops and (4) their magnetic Curie points are greater than 400K. Ceramic, film and single crystal samples were studied and based on their properties we produced varistors (also known as voltage dependent resistors) for microelectronic circuit protection from power surges, three-terminal microelectronic devices capable of generating bipolar currents, and an integrated structured device with controlled magnetic switching of spins. Eleven refereed journal papers, three refereed conference papers and three invention disclosures resulted from our investigations. We also presented invited papers in three international conferences and one national conference. Furthermore two students graduated with Ph.D. degrees, three with M.S. degrees and one with B.S. degree. Also two post-doctoral fellows were actively involved in this research. We established the radiation hardness of our devices in collaboration with a colleague in an HBCU institution, at the Cyclotron Center at Texas A and M University, and at DOE National Labs (Los Alamos and Brookhaven). It is to be appreciated that we met most of our goals and expanded vastly the scope of

  11. Tin (Sn) for enhancing performance in silicon CMOS

    Hussain, Aftab M.; Fahad, Hossain M.; Singh, Nirpendra; Sevilla, Galo T.; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

    2013-01-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  12. Tin (Sn) for enhancing performance in silicon CMOS

    Hussain, Aftab M.

    2013-10-01

    We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.

  13. New approach to local anodic oxidation of semiconductor heterostructures

    Martaus, Jozef; Gregusova, Dagmar; Cambel, Vladimir; Kudela, Robert; Soltys, Jan

    2008-01-01

    We have experimentally explored a new approach to local anodic oxidation (LAO) of a semiconductor heterostructures by means of atomic force microscopy (AFM). We have applied LAO to an InGaP/AlGaAs/GaAs heterostructure. Although LAO is usually applied to oxidize GaAs/AlGaAs/GaAs-based heterostructures, the use of the InGaP/AlGaAs/GaAs system is more advantageous. The difference lies in the use of different cap layer materials: Unlike GaAs, InGaP acts like a barrier material with respect to the underlying AlGaAs layer and has almost one order of magnitude lower density of surface states than GaAs. Consequently, the InGaP/AlGaAs/GaAs heterostructure had the remote Si-δ doping layer only 6.5 nm beneath the surface and the two-dimensional electron gas (2DEG) was confined only 23.5 nm beneath the surface. Moreover, InGaP unaffected by LAO is a very durable material in various etchants and allows us to repeatedly remove thin portions of the underlying AlGaAs layer via wet etching. This approach influences LAO technology fundamentally: LAO was used only to oxidize InGaP cap layer to define very narrow (∼50 nm) patterns. Subsequent wet etching was used to form very narrow and high-energy barriers in the 2DEG patterns. This new approach is promising for the development of future nano-devices operated both at low and high temperatures

  14. Radiation effects in metal-oxide-semiconductor capacitors

    Collins, J.L.

    1987-01-01

    The effects of various radiations on commercially made Al-SiO 2 -Si Capacitors (MOSCs) have been investigated. Intrinsic dielectric breakdown in MOSCs has been shown to be a two-stage process dominated by charge injection in a pre-breakdown stage; this is associated with localised high-field injection of carriers from the semiconductor substrate to interfacial and bulk charge traps which, it is proposed, leads to the formation of conducting channels through the dielectric with breakdown occurring as a result of the dissipation of the conduction band energy. A study of radiation-induced dielectric breakdown has revealed the possibility of anomalous hot-electron injection to an excess of bulk oxide traps in the ionization channel produced by very heavily ionizing radiation, which leads to intrinsic breakdown in high-field stressed devices. This is interpreted in terms of a modified model for radiation-induced dielectric breakdown based upon the primary dependence of breakdown on charge injection rather than high-field mechanisms. A detailed investigation of charge trapping and interface state generation due to various radiations has revealed evidence of neutron induced interface states, and the generation of positive oxide charge in devices due to all the radiations tested. The greater the linear energy transfer of the radiation, the greater the magnitude of charge trapped in the oxide and the number of interface states generated. This is interpreted in terms of Si-H and Si-OH bond-breaking at the Si-SiO 2 interface which is enhanced by charge carrier transfer to the interface and by anomalous charge injection to compensate for the excess of charge carriers created by the radiation. (author)

  15. A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

    Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

    2011-03-01

    Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

  16. CMOS MEMS capacitive absolute pressure sensor

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  17. Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

    Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

    2013-05-06

    In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

  18. A divalent rare earth oxide semiconductor: Yttrium monoxide

    Kaminaga, Kenichi; Sei, Ryosuke; Hayashi, Kouichi; Happo, Naohisa; Tajiri, Hiroo; Oka, Daichi; Fukumura, Tomoteru; Hasegawa, Tetsuya

    Rare earth sesquioxides like Y2O3 are known as widegap insulators with the highly stable closed shell trivalent rare earth ions. On the other hand, rare earth monoxides such as YO have been recognized as gaseous phase, and only EuO and YbO were thermodynamically stable solid-phase rock salt monoxides. In this study, solid-phase rock salt yttrium monoxide, YO, was synthesized in a form of epitaxial thin film by pulsed laser deposition method. YO possesses unusual valence of Y2+ ([Kr] 4d1) . In contrast with Y2O3, YO was narrow gap semiconductor with dark-brown color. The electrical conductivity was tunable from 10-1 to 103 Ω-1 cm-1 by introducing oxygen vacancies as electron donor. Weak antilocalization behavior was observed indicating significant spin-orbit coupling owing to 4 d electron carrier. The absorption spectral shape implies the Mott-Hubbard insulator character of YO. Rare earth monoixdes will be new platform of functional oxides. This work was supported by JST-CREST, the Japan Society for the Promotion of Science (JSPS) with Grant-in-Aid for Scientific Research on Innovative Areas (Nos. 26105002 and 26105006), and Nanotechnology Platform (Project No.12024046) of MEXT, Japan.

  19. Synthesis, Characterization, and Ultrafast Dynamics of Metal, Metal Oxide, and Semiconductor Nanomaterials

    Wheeler, Damon Andreas

    2013-01-01

    SYNTHESIS, CHARACTERIZATION, AND ULTRAFAST DYNAMICS OF METAL, METAL OXIDE, AND SEMICONDUCTOR NANOMATERIALSABSTRACTThe optical properties of each of the three main classes of inorganic nanomaterials, metals, metal oxides, and semiconductors differ greatly due to the intrinsically different nature of the materials. These optical properties are among the most fascinating and useful aspects of nanomaterials with applications spanning cancer treatment, sensors, lasers, and solar cells. One techn...

  20. Dual passivation of intrinsic defects at the compound semiconductor/oxide interface using an oxidant and a reductant.

    Kent, Tyler; Chagarov, Evgeniy; Edmonds, Mary; Droopad, Ravi; Kummel, Andrew C

    2015-05-26

    Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

  1. Oxide Thin-Film Electronics using All-MXene Electrical Contacts

    Wang, Zhenwei; Kim, Hyunho; Alshareef, Husam N.

    2018-01-01

    show balanced performance, including field-effect mobilities of 2.61 and 2.01 cm2 V−1 s−1 and switching ratios of 3.6 × 106 and 1.1 × 103, respectively. Further, complementary metal oxide semiconductor (CMOS) inverters are demonstrated. The CMOS

  2. Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

    Valeri V. Afanas'ev

    2014-01-01

    Full Text Available Evolution of the electron energy band alignment at interfaces between different semiconductors and wide-gap oxide insulators is examined using the internal photoemission spectroscopy, which is based on observations of optically-induced electron (or hole transitions across the semiconductor/insulator barrier. Interfaces of various semiconductors ranging from the conventional silicon to the high-mobility Ge-based (Ge, Si1-xGex, Ge1-xSnx and AIIIBV group (GaAs, InxGa1-xAs, InAs, GaP, InP, GaSb, InSb materials were studied revealing several general trends in the evolution of band offsets. It is found that in the oxides of metals with cation radii larger than ≈0.7 Å, the oxide valence band top remains nearly at the same energy (±0.2 eV irrespective of the cation sort. Using this result, it becomes possible to predict the interface band alignment between oxides and semiconductors as well as between dissimilar insulating oxides on the basis of the oxide bandgap width which are also affected by crystallization. By contrast, oxides of light elements, for example, Be, Mg, Al, Si, and Sc exhibit significant shifts of the valence band top. General trends in band lineup variations caused by a change in the composition of semiconductor photoemission material are also revealed.

  3. Experimental demonstration of CMOS-compatible long-range dielectric-loaded surface plasmon-polariton waveguides (LR-DLSPPWs)

    Zektzer, Roy; Desiatov, Boris; Mazurski, Noa

    2015-01-01

    We demonstrate the design, fabrication and experimental characterization of long-range dielectric-loaded surface plasmon-polariton waveguides (LR-DLSPPWs) that are compatible with complementary metal-oxide semiconductor (CMOS) technology. The demonstrated waveguides feature good mode confinement...

  4. Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process

    Song, Ki-Whan; Lee, Yong Kyu; Sim, Jae Sung; Kim, Kyung Rok; Lee, Jong Duk; Park, Byung-Gook; You, Young Sub; Park, Joo-On; Jin, You Seung; Kim, Young-Wug

    2005-04-01

    We propose a complementary self-biasing method which enables the single-electron transistor (SET)/complementary metal-oxide semiconductor (CMOS) hybrid multi-valued logics (MVLs) to operate well at high temperatures, where the peak-to-valley current ratio (PVCR) of the Coulomb oscillation markedly decreases. The new architecture is implemented with a few transistors by utilizing the phase control capability of the sidewall depletion gates in dual-gate single-electron transistors (DGSETs). The suggested scheme is evaluated by a SPICE simulation with an analytical DGSET model. Furthermore, we have developed a new process technology for the SET/CMOS hybrid systems. We have confirmed that both of the fabricated devices, namely, SET and CMOS transistors, exhibit the ideal characteristics for the complementary self-biasing scheme: the SET shows clear Coulomb oscillations with a 100 mV period and the CMOS transistors show a high voltage gain.

  5. A CMOS-compatible silicon substrate optimization technique and its application in radio frequency crosstalk isolation

    Li Chen; Liao Huailin; Huang Ru; Wang Yangyuan

    2008-01-01

    In this paper, a complementary metal-oxide semiconductor (CMOS)-compatible silicon substrate optimization technique is proposed to achieve effective isolation. The selective growth of porous silicon is used to effectively suppress the substrate crosstalk. The isolation structures are fabricated in standard CMOS process and then this post-CMOS substrate optimization technique is carried out to greatly improve the performances of crosstalk isolation. Three-dimensional electro-magnetic simulation is implemented to verify the obvious effect of our substrate optimization technique. The morphologies and growth condition of porous silicon fabricated have been investigated in detail. Furthermore, a thick selectively grown porous silicon (SGPS) trench for crosstalk isolation has been formed and about 20dB improvement in substrate isolation is achieved. These results demonstrate that our post-CMOS SGPS technique is very promising for RF IC applications. (cross-disciplinary physics and related areas of science and technology)

  6. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  7. Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

    Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

    2008-11-01

    In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

  8. CMOS dot matrix microdisplay

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  9. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  10. Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

    Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

    2017-06-01

    The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. A CMOS silicon spin qubit

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  12. Review of recent developments in amorphous oxide semiconductor thin-film transistor devices

    Park, Joon Seok; Maeng, Wan-Joo; Kim, Hyun-Suk; Park, Jin-Seong

    2012-01-01

    The present article is a review of the recent progress and major trends in the field of thin-film transistor (TFT) research involving the use of amorphous oxide semiconductors (AOS). First, an overview is provided on how electrical performance may be enhanced by the adoption of specific device structures and process schemes, the combination of various oxide semiconductor materials, and the appropriate selection of gate dielectrics and electrode metals in contact with the semiconductor. As metal oxide TFT devices are excellent candidates for switching or driving transistors in next generation active matrix liquid crystal displays (AMLCD) or active matrix organic light emitting diode (AMOLED) displays, the major parameters of interest in the electrical characteristics involve the field effect mobility (μ FE ), threshold voltage (V th ), and subthreshold swing (SS). A study of the stability of amorphous oxide TFT devices is presented next. Switching or driving transistors in AMLCD or AMOLED displays inevitably involves voltage bias or constant current stress upon prolonged operation, and in this regard many research groups have examined and proposed device degradation mechanisms under various stress conditions. The most recent studies involve stress experiments in the presence of visible light irradiating the semiconductor, and different degradation mechanisms have been proposed with respect to photon radiation. The last part of this review consists of a description of methods other than conventional vacuum deposition techniques regarding the formation of oxide semiconductor films, along with some potential application fields including flexible displays and information storage.

  13. CMOS Cell Sensors for Point-of-Care Diagnostics

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  14. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

  15. Monolithic integration of a silicon nanowire field-effect transistors array on a complementary metal-oxide semiconductor chip for biochemical sensor applications.

    Livi, Paolo; Kwiat, Moria; Shadmani, Amir; Pevzner, Alexander; Navarra, Giulio; Rothe, Jörg; Stettler, Alexander; Chen, Yihui; Patolsky, Fernando; Hierlemann, Andreas

    2015-10-06

    We present a monolithic complementary metal-oxide semiconductor (CMOS)-based sensor system comprising an array of silicon nanowire field-effect transistors (FETs) and the signal-conditioning circuitry on the same chip. The silicon nanowires were fabricated by chemical vapor deposition methods and then transferred to the CMOS chip, where Ti/Pd/Ti contacts had been patterned via e-beam lithography. The on-chip circuitry measures the current flowing through each nanowire FET upon applying a constant source-drain voltage. The analog signal is digitized on chip and then transmitted to a receiving unit. The system has been successfully fabricated and tested by acquiring I-V curves of the bare nanowire-based FETs. Furthermore, the sensing capabilities of the complete system have been demonstrated by recording current changes upon nanowire exposure to solutions of different pHs, as well as by detecting different concentrations of Troponin T biomarkers (cTnT) through antibody-functionalized nanowire FETs.

  16. Note: A disposable x-ray camera based on mass produced complementary metal-oxide-semiconductor sensors and single-board computers

    Hoidn, Oliver R.; Seidler, Gerald T., E-mail: seidler@uw.edu [Physics Department, University of Washington, Seattle, Washington 98195 (United States)

    2015-08-15

    We have integrated mass-produced commercial complementary metal-oxide-semiconductor (CMOS) image sensors and off-the-shelf single-board computers into an x-ray camera platform optimized for acquisition of x-ray spectra and radiographs at energies of 2–6 keV. The CMOS sensor and single-board computer are complemented by custom mounting and interface hardware that can be easily acquired from rapid prototyping services. For single-pixel detection events, i.e., events where the deposited energy from one photon is substantially localized in a single pixel, we establish ∼20% quantum efficiency at 2.6 keV with ∼190 eV resolution and a 100 kHz maximum detection rate. The detector platform’s useful intrinsic energy resolution, 5-μm pixel size, ease of use, and obvious potential for parallelization make it a promising candidate for many applications at synchrotron facilities, in laser-heating plasma physics studies, and in laboratory-based x-ray spectrometry.

  17. Atomic layer deposition of perovskite oxides and their epitaxial integration with Si, Ge, and other semiconductors

    McDaniel, Martin D.; Ngo, Thong Q.; Hu, Shen; Ekerdt, John G., E-mail: ekerdt@utexas.edu [Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Posadas, Agham; Demkov, Alexander A. [Department of Physics, The University of Texas at Austin, Austin, Texas 78712 (United States)

    2015-12-15

    Atomic layer deposition (ALD) is a proven technique for the conformal deposition of oxide thin films with nanoscale thickness control. Most successful industrial applications have been with binary oxides, such as Al{sub 2}O{sub 3} and HfO{sub 2}. However, there has been much effort to deposit ternary oxides, such as perovskites (ABO{sub 3}), with desirable properties for advanced thin film applications. Distinct challenges are presented by the deposition of multi-component oxides using ALD. This review is intended to highlight the research of the many groups that have deposited perovskite oxides by ALD methods. Several commonalities between the studies are discussed. Special emphasis is put on precursor selection, deposition temperatures, and specific property performance (high-k, ferroelectric, ferromagnetic, etc.). Finally, the monolithic integration of perovskite oxides with semiconductors by ALD is reviewed. High-quality epitaxial growth of oxide thin films has traditionally been limited to physical vapor deposition techniques (e.g., molecular beam epitaxy). However, recent studies have demonstrated that epitaxial oxide thin films may be deposited on semiconductor substrates using ALD. This presents an exciting opportunity to integrate functional perovskite oxides for advanced semiconductor applications in a process that is economical and scalable.

  18. Atomic layer deposition of perovskite oxides and their epitaxial integration with Si, Ge, and other semiconductors

    McDaniel, Martin D.; Ngo, Thong Q.; Hu, Shen; Ekerdt, John G.; Posadas, Agham; Demkov, Alexander A.

    2015-01-01

    Atomic layer deposition (ALD) is a proven technique for the conformal deposition of oxide thin films with nanoscale thickness control. Most successful industrial applications have been with binary oxides, such as Al 2 O 3 and HfO 2 . However, there has been much effort to deposit ternary oxides, such as perovskites (ABO 3 ), with desirable properties for advanced thin film applications. Distinct challenges are presented by the deposition of multi-component oxides using ALD. This review is intended to highlight the research of the many groups that have deposited perovskite oxides by ALD methods. Several commonalities between the studies are discussed. Special emphasis is put on precursor selection, deposition temperatures, and specific property performance (high-k, ferroelectric, ferromagnetic, etc.). Finally, the monolithic integration of perovskite oxides with semiconductors by ALD is reviewed. High-quality epitaxial growth of oxide thin films has traditionally been limited to physical vapor deposition techniques (e.g., molecular beam epitaxy). However, recent studies have demonstrated that epitaxial oxide thin films may be deposited on semiconductor substrates using ALD. This presents an exciting opportunity to integrate functional perovskite oxides for advanced semiconductor applications in a process that is economical and scalable

  19. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  20. Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

    Kiyotaka Sasagawa

    2010-12-01

    Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

  1. Influence of semiconductor barrier tunneling on the current-voltage characteristics of tunnel metal-oxide-semiconductor diodes

    Nielsen, Otto M.

    1983-01-01

    of multistep tunneling recombination current and injected minority carrier diffusion current. This can explain the observed values of the diode quality factor n. The results also show that the voltage drop across the oxide Vox is increased with increased NA, with the result that the lowering of the minority...... carrier diode current Jmin is greater than in the usual theory. The conclusion drawn is that the increase in Vox and lowering of Jmin is due to multistep tunneling of majority carriers through the semiconductor barrier. Journal of Applied Physics is copyrighted by The American Institute of Physics.......Current–voltage characteristics have been examined for Al–SiO2–pSi diodes with an interfacial oxide thickness of delta[approximately-equal-to]20 Å. The diodes were fabricated on and oriented substrates with an impurity concentration in the range of NA=1014–1016 cm−3. The results show that for low...

  2. Radiation effects in semiconductors

    2011-01-01

    There is a need to understand and combat potential radiation damage problems in semiconductor devices and circuits. Written by international experts, this book explains the effects of radiation on semiconductor devices, radiation detectors, and electronic devices and components. These contributors explore emerging applications, detector technologies, circuit design techniques, new materials, and innovative system approaches. The text focuses on how the technology is being used rather than the mathematical foundations behind it. It covers CMOS radiation-tolerant circuit implementations, CMOS pr

  3. Effects of oxide traps, interface traps, and ''border traps'' on metal-oxide-semiconductor devices

    Fleetwood, D.M.; Winokur, P.S.; Reber, R.A. Jr.; Meisenheimer, T.L.; Schwank, J.R.; Shaneyfelt, M.R.; Riewe, L.C.

    1993-01-01

    We have identified several features of the 1/f noise and radiation response of metal-oxide-semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ''oxide traps'' are simply defects in the SiO 2 layer of the MOS structure, and ''interface traps'' are defects at the Si/SiO 2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ''fixed states'' are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ''switching states'' can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e., ''border traps'' [D. M. Fleetwood, IEEE Trans. Nucl. Sci. NS-39, 269 (1992)]. The effective density of border traps depends on the time scale and bias conditions of the measurements. We show the revised nomenclature can provide focus to discussions of the buildup and annealing of radiation-induced charge in non-radiation-hardened MOS transistors, and to changes in the 1/f noise of MOS devices through irradiation and elevated-temperature annealing

  4. Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

    Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji-Won; Rondinone, Adam Justin; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

    2017-09-19

    The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component comprising at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

  5. Laser Doppler perfusion imaging with a complimentary metal oxide semiconductor image sensor

    Serov, Alexander; Steenbergen, Wiendelt; de Mul, F.F.M.

    2002-01-01

    We utilized a complimentary metal oxide semiconductor video camera for fast f low imaging with the laser Doppler technique. A single sensor is used for both observation of the area of interest and measurements of the interference signal caused by dynamic light scattering from moving particles inside

  6. Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

    Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji Won; Rondinone, Adam J.; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

    2014-06-24

    The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component containing at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

  7. Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

    Jin, J.W.; Nathan, A.; Barquinha, P.; Pereira, L.; Fortunato, E.; Martins, R.; Cobb, B.

    2016-01-01

    Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We

  8. Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

    Ghoneim, Mohamed T.; Kutbee, Arwa T.; Ghodsi Nasseri, Seyed Faizelldin; Bersuker, G.; Hussain, Muhammad Mustafa

    2014-01-01

    We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect

  9. Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

    2016-04-01

    were built in-house at the SUNY Poly-technic Institute’s Center for Semiconductor Research ( CSR ); however, the initial devices for materials screening...A code that models the sweep-mode behavior of the bipolar ReRAM device that is initially in HRS. ............................................ 15...Standard (AES). AES is one of the most important encryption systems and is widely used in military and commercial systems. Based on an iterative

  10. Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

    Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

    2016-11-01

    2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. CMOS SPAD-based image sensor for single photon counting and time of flight imaging

    Dutton, Neale Arthur William

    2016-01-01

    The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications....

  12. High-pressure Raman investigation of the semiconductor antimony oxide

    Geng, Aihui; Cao, Lihua [State Key Lab on High Power Semiconductor Laser, Changchun University of Science and Technology, 130022 Changchun (China); Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, 130012 Changchun (China); Wan, Chunming [State Key Lab on High Power Semiconductor Laser, Changchun University of Science and Technology, 130022 Changchun (China); Ma, Yanmei [Department of Agronomy, Jilin University, 130062 Changchun (China)

    2011-05-15

    The in situ high-pressure behavior of the semiconductor antimony trioxide (Sb{sub 2}O{sub 3}) has been investigated by Raman spectroscopy techniques in a diamond anvil cell up to 20 GPa at room temperature. New peaks in the external lattice mode range emerged at a pressure above 8.6-15 GPa, suggesting that the structural phase transition occurred. The pressure dependence of Raman frequencies was obtained. The band at 139 cm{sup -1} (assigned to group mode) has a pressure dependence of -0.475 cm{sup -1}/GPa and reveals significant softening at high pressure. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  13. Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

    Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

  14. Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

    Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

    2017-10-10

    We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

  15. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  16. Micromachined high-performance RF passives in CMOS substrate

    Li, Xinxin; Ni, Zao; Gu, Lei; Wu, Zhengzheng; Yang, Chen

    2016-01-01

    This review systematically addresses the micromachining technologies used for the fabrication of high-performance radio-frequency (RF) passives that can be integrated into low-cost complementary metal-oxide semiconductor (CMOS)-grade (i.e. low-resistivity) silicon wafers. With the development of various kinds of post-CMOS-compatible microelectromechanical systems (MEMS) processes, 3D structural inductors/transformers, variable capacitors, tunable resonators and band-pass/low-pass filters can be compatibly integrated into active integrated circuits to form monolithic RF system-on-chips. By using MEMS processes, including substrate modifying/suspending and LIGA-like metal electroplating, both the highly lossy substrate effect and the resistive loss can be largely eliminated and depressed, thereby meeting the high-performance requirements of telecommunication applications. (topical review)

  17. High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

    Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

    2010-01-01

    In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

  18. CMOS-based avalanche photodiodes for direct particle detection

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  19. Free form CMOS electronics: Physically flexible and stretchable

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  20. Optimization Design Method for the CMOS-type Capacitive Micro-Machined Ultrasonic Transducer

    D. Y. Chiou

    2011-12-01

    Full Text Available In this study, an integrated modeling technique for characterization and optimization design of the complementary metal-oxide-semiconductor (CMOS capacitive micro-arrayed ultrasonic transducer (pCMOS-CMUT is presented. Electromechanical finite element simulations are performed to investigate its operational characteristics, such as the collapse voltage and the resonant frequency. Both the numerical and experimental results are in good agreement. In order to simultaneously customize the resonant frequency and minimize the collapse voltage, the genetic algorithm (GA is applied to optimize dimensional parameters of the transducer. From the present results, it is concluded that the FE/GA coupling approach provides another efficient numerical tool for multi-objective design of the pCMOS-CMUT.

  1. Interactions between graphene oxide and wide band gap semiconductors

    Kawa, M; Podborska, A; Szaciłowski, K

    2016-01-01

    The graphene oxide (GO) and GO@TiO 2 nanocomposite have been synthesised by using modified Hummers method and ultrasonics respectively. The materials were characterized by using X-ray diffraction, Fourier transform infrared spectroscopy and UV-Vis absorption spectroscopy. It was found that the interaction between GO and TiO 2 affects the average interlayer spacing in carbonaceous material. The formation of bonds between various oxygen-containing functional groups and surface of titanium dioxide was investigated. One of them formed between the quinone structures (occur in graphene oxide) and titanium atoms exhibited 1.5 bond order. Furthermore the charge-transfer processes in GO@TiO 2 composite were observed. (paper)

  2. Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

    Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

    2006-01-01

    We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

  3. Solar hydrogen production with semiconductor metal oxides: new directions in experiment and theory

    Valdes, Alvaro; Brillet, Jeremie; Graetzel, Michael

    2012-01-01

    An overview of a collaborative experimental and theoretical effort toward efficient hydrogen production via photoelectrochemical splitting of water into di-hydrogen and di-oxygen is presented here. We present state-of-the-art experimental studies using hematite and TiO2 functionalized with gold n...... nanoparticles as photoanode materials, and theoretical studies on electro and photo-catalysis of water on a range of metal oxide semiconductor materials, including recently developed implementation of self-interaction corrected energy functionals....

  4. Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

    Ghoneim, Mohamed T.

    2014-06-09

    We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect to breakdown voltage and leakage current of the devices. We also report the effect of continuous mechanical stress on the breakdown voltage over extended periods of times.

  5. Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

    Labram, John G.; Lin, Yenhung; Zhao, Kui; Li, Ruipeng; Thomas, Stuart R.; Semple, James; Androulidaki, Maria; Sygellou, Lamprini; McLachlan, Martyn A.; Stratakis, Emmanuel; Amassian, Aram; Anthopoulos, Thomas D.

    2015-01-01

    reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization

  6. Photodegradation of neonicotinoid insecticides in water by semiconductor oxides.

    Fenoll, José; Garrido, Isabel; Hellín, Pilar; Flores, Pilar; Navarro, Simón

    2015-10-01

    The photocatalytic degradation of three neonicotinoid insecticides (NIs), thiamethoxam (TH), imidacloprid (IM) and acetamiprid (AC), in pure water has been studied using zinc oxide (ZnO) and titanium dioxide (TiO2) as photocatalysts under natural sunlight and artificial light irradiation. Photocatalytic experiments showed that the addition of these chalcogenide oxides in tandem with the electron acceptor (Na2S2O8) strongly enhances the degradation rate of these compounds in comparison with those carried out with ZnO and TiO2 alone and photolytic tests. Comparison of catalysts showed that ZnO is the most efficient for the removal of such insecticides in optimal conditions and at constant volumetric rate of photon absorption. Thus, the complete disappearance of all the studied compounds was achieved after 10 and 30 min of artificial light irradiation, in the ZnO/Na2S2O8 and TiO2/Na2S2O8 systems, respectively. The highest degradation rate was noticed for IM, while the lowest rate constant was obtained for AC under artificial light irradiation. In addition, solar irradiation was more efficient compared to artificial light for the removal of these insecticides from water. The main photocatalytic intermediates detected during the degradation of NIs were identified.

  7. Development of a CMOS Route for Electron Pumps to Be Used in Quantum Metrology

    Sylvain Barraud

    2016-03-01

    Full Text Available The definition of the ampere will change in the next few years. This electrical base unit of the S.I. will be redefined by fixing the value of the charge quantum, i.e., the electron charge e. As a result electron pumps will become the natural device for the mise en pratique of this new ampere. In the last years semiconductor electron pumps have emerged as the most advanced systems, both in terms of speed and precision. Another figure of merit for a metrological device would be its ability to be predictible and shared. For that reason a mature fabrication process would certainly be an advantage. In this article we present electron pumps made within a CMOS (Complementary Metal Oxide Semiconductor research facility on 300 mm silicon-on-insulator wafers, using advanced microelectronics tools and processes. We give an overview of the whole integration scheme and emphasize the fabrication steps which differ from the normal CMOS route.

  8. Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

    An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

    2016-11-01

    Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

  9. Amorphous Hafnium-Indium-Zinc Oxide Semiconductor Thin Film Transistors

    Sheng-Po Chang

    2012-01-01

    Full Text Available We reported on the performance and electrical properties of co-sputtering-processed amorphous hafnium-indium-zinc oxide (α-HfIZO thin film transistors (TFTs. Co-sputtering-processed α-HfIZO thin films have shown an amorphous phase in nature. We could modulate the In, Hf, and Zn components by changing the co-sputtering power. Additionally, the chemical composition of α-HfIZO had a significant effect on reliability, hysteresis, field-effect mobility (μFE, carrier concentration, and subthreshold swing (S of the device. Our results indicated that we could successfully and easily fabricate α-HfIZO TFTs with excellent performance by the co-sputtering process. Co-sputtering-processed α-HfIZO TFTs were fabricated with an on/off current ratio of ~106, higher mobility, and a subthreshold slope as steep as 0.55 V/dec.

  10. Modelling of Leakage Current Through Double Dielectric Gate Stack in Metal Oxide Semiconductor Capacitor

    Fatimah A Noor; Mikrajuddin Abdullah; Sukirno; Khairurrijal

    2008-01-01

    In this paper, we have derived analytical expression of leakage current through double barriers in Metal Oxide Semiconductor (MOS) capacitor. Initially, electron transmittance through the MOS capacitor was derived by including the coupling between the transverse and longitudinal energies. The transmittance was then employed to obtain leakage current through the double barrier. In this model, we observed the effect of electron velocity due to the coupling effect and the oxide thickness to the leakage current. The calculated results showed that the leakage current decreases as the electron velocity increases. (author)

  11. Large Format CMOS-based Detectors for Diffraction Studies

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  12. Large Format CMOS-based Detectors for Diffraction Studies

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  13. 32 x 16 CMOS smart pixel array for optical interconnects

    Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

    2000-05-01

    Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

  14. Hybrid CMOS/Molecular Integrated Circuits

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  15. Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

    Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

    2008-01-01

    The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

  16. Emission channeling with short-lived isotopes lattice location of impurities in semiconductors and oxides

    We propose to perform emission channeling lattice location experiments in a number of semiconductor and oxide systems of technological relevance: \\\\- The lattice location of the transition metal probes $^{56}$Mn ($\\textit{t}_{1/2}$=2.6 h), $^{59}$Fe (45 d), $^{61}$Co (1.6 h) and $^{65}$Ni (2.5 h) is to be investigated in materials of interest as dilute magnetic semiconductors, such as GaMnAs, GaMnN, GaFeN, AlGaN, SiC, and in a number of oxides that are candidates for “single ion ferromagnetism”, in particular SrTiO$_3$ and LiNbO$_3$.\\\\- The topic of $\\textit{p}$-type doping of nitride semiconductors shall be addressed by studying the lattice sites of the acceptor dopants Mg and Be in GaN and AlN using the short-lived probes $^{27}$Mg (9.5 min) and $^{11}$Be (13.8 s). The aim is to reach a lattice location precision around 0.05 Å in order to provide critical tests for recent theoretical models which e.g. have predicted displacements of the Mg atom from the ideal substitutional Ga and Al sites of the order...

  17. Contact CMOS imaging of gaseous oxygen sensor array.

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  18. Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

    Kao, Wei-Chieh

    Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

  19. Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

    Hong, Augustin Jinwoo

    Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

  20. Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

    Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

    1992-06-01

    The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

  1. Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

    Asoka-Kumar, P.; Leung, T.C.; Lynn, K.G.; Nielsen, B.; Forcier, M.P.; Weinberg, Z.A.; Rubloff, G.W.

    1992-01-01

    The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions

  2. Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors

    Appenzeller, J.; Martel, R.; Solomon, P.; Chan, K.; Avouris, Ph.; Knoch, J.; Benedict, J.; Tanner, M.; Thomas, S.; Wang, K. L.

    2000-01-01

    We present a scheme for the fabrication of ultrashort channel length metal-oxide-semiconductor field-effect transistors (MOSFETs) involving nanolithography and molecular-beam epitaxy. The active channel is undoped and is defined by a combination of nanometer-scale patterning and anisotropic etching of an n ++ layer grown on a silicon on insulator wafer. The method is self-limiting and can produce MOSFET devices with channel lengths of less than 10 nm. Measurements on the first batch of n-MOSFET devices fabricated with this approach show very good output characteristics and good control of short-channel effects. (c) 2000 American Institute of Physics

  3. CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

    Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

    2011-09-01

    Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

  4. Chemically-modified electrodes in photoelectrochemical cells. [Tin oxide and TiO/sub 2/ semiconductor electrodes

    Fox, M A; Hohman, J R; Kamat, P V

    1893-01-01

    Tin oxide and titanium dioxide semiconductor electrodes hae been covalently modified by the attachment of functionalized olefins and arenes through surface silanation or via a cyanuric chloride linkage. The excited state and electrochemical properties of the molecules so attached are significantly affected by the semiconductor. Photocurrent measurements and time-resolved laser coulostatic monitoring have been employed to elucidate the mechanism of charge injection on these modified surfaces. 17 references, 7 figures.

  5. Atomic Layer Deposited Thin Films for Dielectrics, Semiconductor Passivation, and Solid Oxide Fuel Cells

    Xu, Runshen

    Atomic layer deposition (ALD) utilizes sequential precursor gas pulses to deposit one monolayer or sub-monolayer of material per cycle based on its self-limiting surface reaction, which offers advantages, such as precise thickness control, thickness uniformity, and conformality. ALD is a powerful means of fabricating nanoscale features in future nanoelectronics, such as contemporary sub-45 nm metal-oxide-semiconductor field effect transistors, photovoltaic cells, near- and far-infrared detectors, and intermediate temperature solid oxide fuel cells. High dielectric constant, kappa, materials have been recognized to be promising candidates to replace traditional SiO2 and SiON, because they enable good scalability of sub-45 nm MOSFET (metal-oxide-semiconductor field-effect transistor) without inducing additional power consumption and heat dissipation. In addition to high dielectric constant, high-kappa materials must meet a number of other requirements, such as low leakage current, high mobility, good thermal and structure stability with Si to withstand high-temperature source-drain activation annealing. In this thesis, atomic layer deposited Er2O3 doped TiO2 is studied and proposed as a thermally stable amorphous high-kappa dielectric on Si substrate. The stabilization of TiO2 in its amorphous state is found to achieve a high permittivity of 36, a hysteresis voltage of less than 10 mV, and a low leakage current density of 10-8 A/cm-2 at -1 MV/cm. In III-V semiconductors, issues including unsatisfied dangling bonds and native oxides often result in inferior surface quality that yields non-negligible leakage currents and degrades the long-term performance of devices. The traditional means for passivating the surface of III-V semiconductors are based on the use of sulfide solutions; however, that only offers good protection against oxidation for a short-term (i.e., one day). In this work, in order to improve the chemical passivation efficacy of III-V semiconductors

  6. A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

    Wallace, Robert M.

    2001-03-01

    Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

  7. Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors

    Chen Qu

    2017-09-01

    Full Text Available The CMOS (Complementary Metal-Oxide-Semiconductor is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze, causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

  8. Photocatalytic oxidation of organic compounds in a hybrid system composed of a molecular catalyst and visible light-absorbing semiconductor.

    Zhou, Xu; Li, Fei; Li, Xiaona; Li, Hua; Wang, Yong; Sun, Licheng

    2015-01-14

    Photocatalytic oxidation of organic compounds proceeded efficiently in a hybrid system with ruthenium aqua complexes as catalysts, BiVO4 as a light absorber, [Co(NH3)5Cl](2+) as a sacrificial electron acceptor and water as an oxygen source. The photogenerated holes in the semiconductor are used to oxidize molecular catalysts into the high-valent Ru(IV)=O intermediates for 2e(-) oxidation.

  9. Hysteresis phenomena at metal-semiconductor phase transformation in vanadium oxides

    Lanskaya, T.G.; Merkulov, I.A.; Chudnovski , F.A.

    1978-01-01

    The hysteresis phenomena during the metal-semiconductor phase transformation (MSPT) in vanadium oxides are investigated. It is shown experimentally that the hysteresis effects during MSPT in vanadium oxides are associated not only with the martensite nature of the transformation, but also with activation processes. It is shown that the hysteresis phenomena during MSPT may be described by the distribution function of microregions of the crystal in the phase transformation temperature T 0 and the coercive temperature Tsub(c). An experimental method for constructing this distribution function was worked out. An analysis of the experimental data shows that finely dispersed films are characterized by a wide range of values of T 0 and Tsub(c) (55 deg C 0 <65 deg C, 6 deg C< Tsub(c)<12 deg C). The peculiarities of the optical recording of information on monocrystal and finely dispersed films are considered

  10. Oxidized Mn:Ge magnetic semiconductor: Observation of anomalous Hall effect and large magnetoresistance

    Duc Dung, Dang; Choi, Jiyoun; Feng, Wuwei; Cao Khang, Nguyen; Cho, Sunglae

    2018-03-01

    We report on the structural and magneto-transport properties of the as-grown and oxidized Mn:Ge magnetic semiconductors. Based on X-ray diffraction and X-ray photoelectron spectroscopy results, the samples annealed at 650 and 700 °C became fully oxidized and the chemical binding energies of Mn was found to be Mn3O4. Thus, the system became Mn3O4 clusters embedded in Ge1-yOy. The as-grown sample showed positive linear Hall effect and negligible negative magnetoresistance (MR), which trend remained for the sample annealed up to 550 °C. Interestingly, for the samples annealed at above 650 °C, we observed the anomalous Hall effect around 45 K and the giant positive MR, which are respectively 59.2% and 78.5% at 7 kOe annealed at 650 °C and 700 °C.

  11. Silicon carbide: A unique platform for metal-oxide-semiconductor physics

    Liu, Gang [Institute for Advanced Materials, Devices and Nanotechnology, Rutgers University, Piscataway, New Jersey 08854 (United States); Tuttle, Blair R. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States)

    2015-06-15

    A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO{sub 2}/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.

  12. Electrosprayed Metal Oxide Semiconductor Films for Sensitive and Selective Detection of Hydrogen Sulfide

    Maryam Siadat

    2009-11-01

    Full Text Available Semiconductor metal oxide films of copper-doped tin oxide (Cu-SnO2, tungsten oxide (WO3 and indium oxide (In2O3 were deposited on a platinum coated alumina substrate employing the electrostatic spray deposition technique (ESD. The morphology studied with scanning electron microscopy (SEM and atomic force microscopy (AFM shows porous homogeneous films comprising uniformly distributed aggregates of nano particles. The X-ray diffraction technique (XRD proves the formation of crystalline phases with no impurities. Besides, the Raman cartographies provided information about the structural homogeneity. Some of the films are highly sensitive to low concentrations of H2S (10 ppm at low operating temperatures (100 and 200 °C and the best response in terms of Rair/Rgas is given by Cu-SnO2 films (2500 followed by WO3 (1200 and In2O3 (75. Moreover, all the films exhibit no cross-sensitivity to other reducing (SO2 or oxidizing (NO2 gases.

  13. Single Event Upset Rate Estimates for a 16-K CMOS (Complementary Metal Oxide Semiconductor) SRAM (Static Random Access Memory).

    1986-09-30

    4 . ~**..ft.. ft . - - - ft SI TABLES 9 I. SA32~40 Single Event Upset Test, 1140-MeV Krypton, 9/l8/8~4. . .. .. .. .. .. .16 II. CRUP Simulation...cosmic ray interaction analysis described in the remainder of this report were calculated using the CRUP computer code 3 modified for funneling. The... CRUP code requires, as inputs, the size of a depletion region specified as a retangular parallel piped with dimensions a 9 b S c, the effective funnel

  14. Photochemistry Aspects of the Laser Pyrolysis Addressing the Preparation of Oxide Semiconductor Photocatalysts

    R. Alexandrescu

    2008-01-01

    Full Text Available The laser pyrolysis is a powerful and a versatile tool for the gas-phase synthesis of nanoparticles. In this paper, some fundamental and applicative characteristics of this technique are outlined and recent results obtained in the preparation of gamma iron oxide (γ-Fe2O3 and titania (TiO2 semiconductor nanostructures are illustrated. Nanosized iron oxide particles (4 to 9 nm diameter values have been directly synthesized by the laser-induced pyrolysis of a mixture containing iron pentacarbonyl/air (as oxidizer/ethylene (as sensitizer. Temperature-dependent Mossbauer spectroscopy shows that mainly maghemite is present in the sample obtained at higher laser power. The use of selected Fe2O3 samples for the preparation of water-dispersed magnetic nanofluids is also discussed. TiO2 nanoparticles comprising a mixture of anatase and rutile phases were synthesized via the laser pyrolysis of TiCl4- (vapors based gas-phase mixtures. High precursor concentration of the oxidizer was found to favor the prevalent anatase phase (about 90% in the titania nanopowders.

  15. Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation

    Chou, Wei-Lung, E-mail: wlchou@sunrise.hk.edu.tw [Department of Safety, Health and Environmental Engineering, Hungkuang University, No. 34, Chung-Chie Road, Sha-Lu, Taichung 433, Taiwan (China); Wang, Chih-Ta [Department of Safety Health and Environmental Engineering, Chung Hwa University of Medical Technology, Tainan Hsien 717, Taiwan (China); Chang, Wen-Chun; Chang, Shih-Yu [Department of Safety, Health and Environmental Engineering, Hungkuang University, No. 34, Chung-Chie Road, Sha-Lu, Taichung 433, Taiwan (China)

    2010-08-15

    In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L{sup -1}). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K.

  16. Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation

    Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

    2010-01-01

    In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L -1 ). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K.

  17. Local anodic oxidation by AFM tip developed for novel semiconductor nanodevices

    Cambel, Vladimir; Martaus, Jozef; Soltys, Jan; Kudela, Robert; Gregusova, Dagmar

    2008-01-01

    The local anodic oxidation (LAO) by the tip of atomic force microscope (AFM) is used for fabrication of nanometer-scaled structures and devices. We study the technology of LAO applied to semiconductor heterostructures, theoretically and experimentally as well. The goal is to improve the LAO process itself, i.e., to create narrow LAO lines that form high-energy barriers in the plane with the 2D electron gas. In the first part we show the electric field distribution in the system tip-sample during LAO. For samples with low-conductive cap layer the maximum electric field is shifted apart the tip apex, which leads to wide oxide lines. Our Monte Carlo (MC) calculations show how the height of the energy barrier in the system depends on the geometry of the created lines (trenches), and on voltage applied to the structure. Based on the calculations, we have proposed a novel LAO technology and applied it to InGaP/AlGaAs/GaAs heterostructure with doping layer only 6 nm beneath the surface. The doping layer can be oxidized easily by the AFM tip in this case, and the oxide objects can be removed by several etchants. This approach to the LAO technology leads to narrow LAO trenches (∼60 nm) and to energy barriers high enough for room- and low-temperature applications

  18. Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation.

    Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

    2010-08-15

    In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L(-1)). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K. Copyright 2010 Elsevier B.V. All rights reserved.

  19. Nanometer CMOS ICs from basics to ASICs

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  20. Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

    Gagnard, Xavier; Bonnaud, Olivier

    2000-08-01

    We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

  1. CMOS circuits manual

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  2. Carrier transport and electronic structure in amorphous oxide semiconductor, a-InGaZnO4

    Takagi, Akihiro; Nomura, Kenji; Ohta, Hiromichi; Yanagi, Hiroshi; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

    2005-01-01

    Carrier transport properties in amorphous oxide semiconductor InGaZnO 4 (a-IGZO) thin films were investigated in detail using temperature dependence of Hall measurements. It was found that Hall mobility increased distinctly as carrier concentration increased. Unlikely conventional amorphous semiconductors such as a-Si/H, definite normal Hall voltage signals were observed on the films with carrier concentrations (N e )>10 16 cm -3 , and Hall mobilities as large as 15 cm 2 (Vs) -1 were attained in the films with N e >10 20 cm -3 . When N e was less than 10 19 cm -3 , the temperature dependence of Hall mobility showed thermally-activated behavior in spite that carrier concentration was independent of temperature. While, it changed to almost degenerate conduction at N e >10 18 cm -3 . These behaviors are similar to those observed in single-crystalline IGZO, and are explained by percolation conduction through distributed potential barriers which are formed in the vicinity of the conduction band bottom due to the randomness of the amorphous structure. The effective mass of a-IGZO was estimated to be ∼0.34 m e (m e is the mass of free electron) from optical data, which is almost the same as that of crystalline IGZO (∼0.32 m e )

  3. Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

    Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

    2017-05-24

    Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

  4. Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

    Jong Woo Jin

    2016-08-01

    Full Text Available Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

  5. Fabrication of smooth patterned structures of refractory metals, semiconductors, and oxides via template stripping.

    Park, Jong Hyuk; Nagpal, Prashant; McPeak, Kevin M; Lindquist, Nathan C; Oh, Sang-Hyun; Norris, David J

    2013-10-09

    The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics.

  6. Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

    Jin, Jong Woo [LPICM, CNRS, Ecole Polytechnique, Université Paris Saclay, 91128, Palaiseau (France); Nathan, Arokia, E-mail: an299@cam.ac.uk [Engineering Department, University of Cambridge, Cambridge, CB3 0FA (United Kingdom); Barquinha, Pedro; Pereira, Luís; Fortunato, Elvira; Martins, Rodrigo [i3N/CENIMAT, Department of Materials Science, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica (Portugal); Cobb, Brian [Holst Centre/TNO, Eindhoven, 5656 AE (Netherlands)

    2016-08-15

    Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

  7. Stannic Oxide-Titanium Dioxide Coupled Semiconductor Photocatalyst Loaded with Polyaniline for Enhanced Photocatalytic Oxidation of 1-Octene

    Hadi Nur

    2007-01-01

    Full Text Available Stannic oxide-titanium dioxide (SnO2–TiO2 coupled semiconductor photocatalyst loaded with polyaniline (PANI, a conducting polymer, possesses a high photocatalytic activity in oxidation of 1-octene to 1,2-epoxyoctane with aqueous hydrogen peroxide. The photocatalyst was prepared by impregnation of SnO2 and followed by attachment of PANI onto a TiO2 powder to give sample PANI-SnO2–TiO2. The electrical conductivity of the system becomes high in the presence of PANI. Enhanced photocatalytic activity was observed in the case of PANI-SnO2–TiO2 compared to PANI-TiO2, SnO2–TiO2, and TiO2. A higher photocatalytic activity in the oxidation of 1-octene on PANI-SnO2–TiO2 than SnO2–TiO2, PANI-TiO2, and TiO2 can be considered as an evidence of enhanced charge separation of PANI-SnO2–TiO2 photocatalyst as confirmed by photoluminescence spectroscopy. It suggests that photoinjected electrons are tunneled from TiO2 to SnO2 and then to PANI in order to allow wider separation of excited carriers.

  8. Positron annihilation in a metal-oxide semiconductor studied by using a pulsed monoenergetic positron beam

    Uedono, A.; Wei, L.; Tanigawa, S.; Suzuki, R.; Ohgaki, H.; Mikado, T.; Ohji, Y.

    1993-12-01

    The positron annihilation in a metal-oxide semiconductor was studied by using a pulsed monoenergetic positron beam. Lifetime spectra of positrons were measured as a function of incident positron energy for a polycrystalline Si(100 nm)/SiO2(400 nm)/Si specimen. Applying a gate voltage between the polycrystalline Si film and the Si substrate, positrons implanted into the specimen were accumulated at the SiO2/Si interface. From the measurements, it was found that the annihilation probability of ortho-positronium (ortho-Ps) drastically decreased at the SiO2/Si interface. The observed inhibition of the Ps formation was attributed to an interaction between positrons and defects at the SiO2/Si interface.

  9. Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

    Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

    2017-10-01

    Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

  10. Transparent p-type SnO nanowires with unprecedented hole mobility among oxide semiconductors

    Caraveo-Frescas, J. A.

    2013-11-25

    p-type tin monoxide (SnO) nanowire field-effect transistors with stable enhancement mode behavior and record performance are demonstrated at 160 °C. The nanowire transistors exhibit the highest field-effect hole mobility (10.83 cm2 V−1 s−1) of any p-type oxide semiconductor processed at similar temperature. Compared to thin film transistors, the SnO nanowire transistors exhibit five times higher mobility and one order of magnitude lower subthreshold swing. The SnO nanowire transistors show three times lower threshold voltages (−1 V) than the best reported SnO thin film transistors and fifteen times smaller than p-type Cu 2O nanowire transistors. Gate dielectric and process temperature are critical to achieving such performance.

  11. Dimensional optimization of nanowire--complementary metal oxide--semiconductor inverter.

    Hashim, Yasir; Sidek, Othman

    2013-01-01

    This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.

  12. Optically induced bistable states in metal/tunnel-oxide/semiconductor /MTOS/ junctions

    Lai, S. K.; Dressendorfer, P. V.; Ma, T. P.; Barker, R. C.

    1981-01-01

    A new switching phenomenon in metal-oxide semiconductor tunnel junction has been discovered. With a sufficiently large negative bias applied to the electrode, incident visible light of intensity greater than about 1 microW/sq cm causes the reverse-biased junction to switch from a low-current to a high-current state. It is believed that hot-electron-induced impact ionization provides the positive feedback necessary for switching, and causes the junction to remain in its high-current state after the optical excitation is removed. The junction may be switched back to the low-current state electrically. The basic junction characteristics have been measured, and a simple model for the switching phenomenon has been developed.

  13. Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

    Ngai, K.L.; Hsia, Y.

    1982-01-01

    A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features

  14. The role of metallic impurities in oxide semiconductors: first-principles calculations and PAC experiments

    Errico, L.A.; Fabricius, G.; Renteria, M. [Departamento de Fisica, Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC 67, 1900 La Plata (Argentina)

    2004-08-01

    We report an ab-initio comparative study of the electric-field-gradient tensor (EFG) and structural relaxations introduced by acceptor (Cd) and donor (Ta) impurities when they replace cations in a series of binary oxides: TiO{sub 2}, SnO{sub 2}, and In{sub 2}O{sub 3}. Calculations were performed with the Full-Potential Linearized-Augmented Plane Waves method that allows us to treat the electronic structure and the atomic relaxations in a fully self-consistent way. We considered different charge states for each impurity and studied the dependence on these charge states of the electronic properties and the structural relaxations. Our results are compared with available data coming from PAC experiments and previous calculations, allowing us to obtain a new insight on the role that metal impurities play in oxide semiconductors. It is clear from our results that simple models can not describe the measured EFGs at impurities in oxides even approximately. (copyright 2004 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  15. Electron transport properties of indium oxide - indium nitride metal-oxide-semiconductor heterostructures

    Wang, C.Y.; Hauguth, S.; Polyakov, V.; Schwierz, F.; Cimalla, V.; Kups, T.; Himmerlich, M.; Schaefer, J.A.; Krischok, S.; Ambacher, O.; Morales, F.M.; Lozano, J.G.; Gonzalez, D.; Lebedev, V.

    2008-01-01

    The structural, chemical and electron transport properties of In 2 O 3 /InN heterostructures and oxidized InN epilayers are reported. It is shown that the accumulation of electrons at the InN surface can be manipulated by the formation of a thin surface oxide layer. The epitaxial In 2 O 3 /InN heterojunctions show an increase in the electron concentration due to the increasing band banding at the heterointerface. The oxidation of InN results in improved transport properties and in a reduction of the sheet carrier concentration of the InN epilayer very likely caused by a passivation of surface donors. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  16. Pulsed laser deposition of piezoelectric lead zirconate titanate thin films maintaining a post-CMOS compatible thermal budget

    Schatz, A.; Pantel, D.; Hanemann, T.

    2017-09-01

    Integration of lead zirconate titanate (Pb[Zrx,Ti1-x]O3 - PZT) thin films on complementary metal-oxide semiconductor substrates (CMOS) is difficult due to the usually high crystallization temperature of the piezoelectric perovskite PZT phase, which harms the CMOS circuits. In this work, a wafer-scale pulsed laser deposition tool was used to grow 1 μm thick PZT thin films on 150 mm diameter silicon wafers. Three different routes towards a post-CMOS compatible deposition process were investigated, maintaining a post-CMOS compatible thermal budget limit of 445 °C for 1 h (or 420 °C for 6 h). By crystallizing the perovskite LaNiO3 seed layer at 445 °C, the PZT deposition temperature can be lowered to below 400 °C, yielding a transverse piezoelectric coefficient e31,f of -9.3 C/m2. With the same procedure, applying a slightly higher PZT deposition temperature of 420 °C, an e31,f of -10.3 C/m2 can be reached. The low leakage current density of below 3 × 10-6 A/cm2 at 200 kV/cm allows for application of the post-CMOS compatible PZT thin films in low power micro-electro-mechanical-systems actuators.

  17. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  18. CMOS VLSI Active-Pixel Sensor for Tracking

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  19. High-Voltage-Input Level Translator Using Standard CMOS

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  20. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  1. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  2. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique

    Chien-Fu Fong

    2015-10-01

    Full Text Available A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS-microelectromechanical system (MEMS technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

  3. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  4. Fabrication and Characterization of a Micro Methanol Sensor Using the CMOS-MEMS Technique.

    Fong, Chien-Fu; Dai, Ching-Liang; Wu, Chyan-Chyi

    2015-10-23

    A methanol microsensor integrated with a micro heater manufactured using the complementary metal oxide semiconductor (CMOS)-microelectromechanical system (MEMS) technique was presented. The sensor has a capability of detecting low concentration methanol gas. Structure of the sensor is composed of interdigitated electrodes, a sensitive film and a heater. The heater located under the interdigitated electrodes is utilized to provide a working temperature to the sensitive film. The sensitive film prepared by the sol-gel method is tin dioxide doped cadmium sulfide, which is deposited on the interdigitated electrodes. To obtain the suspended structure and deposit the sensitive film, the sensor needs a post-CMOS process to etch the sacrificial silicon dioxide layer and silicon substrate. The methanol senor is a resistive type. A readout circuit converts the resistance variation of the sensor into the output voltage. The experimental results show that the methanol sensor has a sensitivity of 0.18 V/ppm.

  5. Real-time biochemical sensor based on Raman scattering with CMOS contact imaging.

    Muyun Cao; Yuhua Li; Yadid-Pecht, Orly

    2015-08-01

    This work presents a biochemical sensor based on Raman scattering with Complementary metal-oxide-semiconductor (CMOS) contact imaging. This biochemical optical sensor is designed for detecting the concentration of solutions. The system is built with a laser diode, an optical filter, a sample holder and a commercial CMOS sensor. The output of the system is analyzed by an image processing program. The system provides instant measurements with a resolution of 0.2 to 0.4 Mol. This low cost and easy-operated small scale system is useful in chemical, biomedical and environmental labs for quantitative bio-chemical concentration detection with results reported comparable to a highly cost commercial spectrometer.

  6. High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

    Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

    2017-02-01

    Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

  7. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

    Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

    2018-04-05

    Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  8. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

    Kuei-Chi Tsao

    2018-04-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA. The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  9. CMOS image sensor-based immunodetection by refractive-index change.

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

  10. Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

    Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

    2016-01-01

    In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

  11. CMOS Imaging of Temperature Effects on Pin-Printed Xerogel Sensor Microarrays.

    Lei Yao; Ka Yi Yung; Chodavarapu, Vamsy P; Bright, Frank V

    2011-04-01

    In this paper, we study the effect of temperature on the operation and performance of a xerogel-based sensor microarrays coupled to a complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC) that images the photoluminescence response from the sensor microarray. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. A correlated double sampling circuit and pixel address/digital control/signal integration circuit are also implemented on-chip. The CMOS imager data are read out as a serial coded signal. The sensor system uses a light-emitting diode to excite target analyte responsive organometallic luminophores doped within discrete xerogel-based sensor elements. As a proto type, we developed a 3 × 3 (9 elements) array of oxygen (O2) sensors. Each group of three sensor elements in the array (arranged in a column) is designed to provide a different and specific sensitivity to the target gaseous O2 concentration. This property of multiple sensitivities is achieved by using a mix of two O2 sensitive luminophores in each pin-printed xerogel sensor element. The CMOS imager is designed to be low noise and consumes a static power of 320.4 μW and an average dynamic power of 624.6 μW when operating at 100-Hz sampling frequency and 1.8-V dc power supply.

  12. Development of a lens-coupled CMOS detector for an X-ray inspection system

    Kim, Ho Kyung; Ahn, Jung Keun; Cho, Gyuseong

    2005-01-01

    A digital X-ray imaging detector based on a complementary metal-oxide-semiconductor (CMOS) image sensor has been developed for X-ray non-destructive inspection applications. This is a cost-effective solution because of the availability of cheap commercial standard CMOS image sensors. The detector configuration adopts an indirect X-ray detection method by using scintillation material and lens assembly. As a feasibility test of the developed lens-coupled CMOS detector as an X-ray inspection system, we have acquired X-ray projection images under a variety of imaging conditions. The results show that the projected image is reasonably acceptable in typical non-destructive testing (NDT). However, the developed detector may not be appropriate for laminography due to a low light-collection efficiency of lens assembly. In this paper, construction of the lens-coupled CMOS detector and its specifications are described, and the experimental results are presented. Using the analysis of quantum accounting diagram, inefficiency of the lens-coupling method is discussed

  13. Test CMOS/SOS RAM for transient radiation upset comparative research and failure analysis

    Nikiforov, A.Y.; Poljakov, I.V.

    1995-01-01

    The test Complementary Metal-Oxide-Semiconductor/Silicon-on-Sapphire Random Access Memory (CMOS/SOS RAM) with eight types of memory cells was designed and tested at high dose rates with a flash X-ray machine and laser simulator. The memory cell (MC) design with additional transistors and RC-chain was found to be upset free up to 2 x 10 12 rad(Si)/s. An inversion effect was discovered in which almost 100% logic upset was observed in poorly protected memory cell arrays at very high dose rates

  14. Bi-component semiconductor oxide photoanodes for the photoelectrocatalytic oxidation of organic solutes and vapours: a short review with emphasis to TiO2-WO3 photoanodes.

    Georgieva, J; Valova, E; Armyanov, S; Philippidis, N; Poulios, I; Sotiropoulos, S

    2012-04-15

    The use of binary semiconductor oxide anodes for the photoelectrocatalytic oxidation of organic species (both in solution and gas phase) is reviewed. In the first part of the review, the principle of electrically assisted photocatalysis is presented, the preparation methods for the most common semiconductor oxide catalysts are briefly mentioned, while the advantages of appropriately chosen semiconductor combinations for efficient UV and visible (vis) light utilization are highlighted. The second part of the review focuses on the discussion of TiO(2)-WO(3) photoanodes (among the most studied bi-component semiconductor oxide systems) and in particular on coatings prepared by electrodeposition/electrosynthesis or powder mixtures (the focus of the authors' research during recent years). Studies concerning the microscopic, spectroscopic and photoelectrochemical characterization of the catalysts are presented and examples of photoanode activity towards typical dissolved organic contaminants as well as organic vapours are given. Particular emphasis is paid to: (a) The dependence of photoactivity on catalyst morphology and composition and (b) the possibility of carrying out photoelectrochemistry in all-solid cells, thus opening up the opportunity for photoelectrocatalytic air treatment. Copyright © 2011 Elsevier B.V. All rights reserved.

  15. A Multipurpose CMOS Platform for Nanosensing

    Alberto Bonanno

    2016-11-01

    Full Text Available This paper presents a customizable sensing system based on functionalized nanowires (NWs assembled onto complementary metal oxide semiconductor (CMOS technology. The Micro-for-Nano (M4N chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  16. A Multipurpose CMOS Platform for Nanosensing.

    Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

    2016-11-30

    This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

  17. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

    2015-01-01

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10 17  m −2 . We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching

  18. Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

    McConkey, M. L.

    1984-12-01

    A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

  19. Deep electron traps in HfO_2-based metal-oxide-semiconductor capacitors

    Salomone, L. Sambuco; Lipovetzky, J.; Carbonetto, S.H.; García Inza, M.A.; Redin, E.G.; Campabadal, F.

    2016-01-01

    Hafnium oxide (HfO_2) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO_2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO_2 interface at an energy level E_t = 1.59 eV below the HfO_2 conduction band edge with density N_t = 1.36 × 10"1"9 cm"−"3. A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. - Highlights: • We characterized deep electron trapping/detrapping in HfO_2 structures. • We modeled the experimental results through a tunneling-based model. • We obtained an electron trap energy level of 1.59 eV below conduction band edge. • We obtained a spatial trap distribution extending 1.7 nm within the insulator. • A simplified tunneling front model is able to reproduce the experimental results.

  20. CMOS capacitive biosensors for highly sensitive biosensing applications.

    Chang, An-Yu; Lu, Michael S-C

    2013-01-01

    Magnetic microbeads are widely used in biotechnology and biomedical research for manipulation and detection of cells and biomolecules. Most lab-on-chip systems capable of performing manipulation and detection require external instruments to perform one of the functions, leading to increased size and cost. This work aims at developing an integrated platform to perform these two functions by implementing electromagnetic microcoils and capacitive biosensors on a CMOS (complementary metal oxide semiconductor) chip. Compared to most magnetic-type sensors, our detection method requires no externally applied magnetic fields and the associated fabrication is less complicated. In our experiment, microbeads coated with streptavidin were driven to the sensors located in the center of microcoils with functionalized anti-streptavidin antibody. Detection of a single microbead was successfully demonstrated using a capacitance-to-frequency readout. The average capacitance changes for the experimental and control groups were -5.3 fF and -0.2 fF, respectively.

  1. Triple inverter pierce oscillator circuit suitable for CMOS

    Wessendorf,; Kurt, O [Albuquerque, NM

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  2. Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

    Labram, John G.

    2015-02-13

    Physical phenomena such as energy quantization have to-date been overlooked in solution-processed inorganic semiconducting layers, owing to heterogeneity in layer thickness uniformity unlike some of their vacuum-deposited counterparts. Recent reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization in inorganic semiconductor layers with appreciable surface roughness, as compared to the mean layer thickness, and present experimental evidence of the existence of quantized energy states in spin-cast layers of zinc oxide (ZnO). As-grown ZnO layers are found to be remarkably continuous and uniform with controllable thicknesses in the range 2-24 nm and exhibit a characteristic widening of the energy bandgap with reducing thickness in agreement with theoretical predictions. Using sequentially spin-cast layers of ZnO as the bulk semiconductor and quantum well materials, and gallium oxide or organic self-assembled monolayers as the barrier materials, two terminal electronic devices are demonstrated, the current-voltage characteristics of which resemble closely those of double-barrier resonant-tunneling diodes. As-fabricated all-oxide/hybrid devices exhibit a characteristic negative-differential conductance region with peak-to-valley ratios in the range 2-7.

  3. Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

    Almuslem, A. S.

    2017-02-14

    In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

  4. Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

    Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

    2006-04-01

    The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

  5. Magnetotransport investigations of the two-dimensional metallic state in silicon metal-oxid-semiconductor structures

    Prinz, A.

    2002-03-01

    For more than two decades it was the predominant view among the physical community that the every two-dimensional (2D) disordered electron system becomes insulating as the temperature approaches the absolute zero temperature (0 Kelvin or -273.15 o C). Two-dimensional means that the movement of the charge carriers is confined in one direction by a potential so that the carriers can move freely only perpendicular to the confinement. The most famous physical realization of a 2D system is the silicon metal-oxide-semiconductor field effect transistor (Si-MOSFET). It is one of the basic elements of most electronic devices in our daily life. The working principle is very simple. Charges are attracted to the semiconductor-oxide interface by an electric field applied between the metallic gate and the semiconductor, so that a 2D conductive channel is formed. The charge density can be adjusted by the voltage from zero up to 10 13 cm -2 . In 1994 Kravchenko and coworkers made a very important discovery. They studied high mobility Si-MOSFETs and found that for densities below a certain critical value, nc, the resistivity increases as the temperature is decreased below 2 K, whereas for densities above $n c $ the resistivity decreases unexpectedly. The transition from insulating to metallic behavior, known as metal-insulator transition (MIT), was obviously a contradiction to the commonly accepted theories which predict insulating behavior for any density. The insulating behavior is a consequence of the wave properties of electrons which leads to interference in disordered media and thus to enhanced backscattering. In the subsequent years, experimental studies were performed on a variety of 2D systems, which qualitatively showed a similar behavior. All the investigated samples had one thing in common. The interaction energy between the carriers was considerable higher than their mean kinetic energy due to their movement in the 2D plane. Since the electron-electron interaction was

  6. Probing the Unique Role of Gallium in Amorphous Oxide Semiconductors through Structure-Property Relationships

    Moffitt, Stephanie L.; Zhu, Qimin; Ma, Qing; Falduto, Allison F.; Buchholz, D. Bruce; Chang, Robert P.H.; Mason, Thomas O.; Medvedeva, Julia E.; Marks, Tobin J.; Bedzyk, Michael J. (NWU); (MUST)

    2017-09-01

    This study explores the unique role of Ga in amorphous (a-) In[BOND]Ga[BOND]O oxide semiconductors through combined theory and experiment. It reveals substitutional effects that have not previously been attributed to Ga, and that are investigated by examining how Ga influences structure–property relationships in a series of pulsed laser deposited a-In[BOND]Ga[BOND]O thin films. Element-specific structural studies (X-ray absorption and anomalous scattering) show good agreement with the results of ab initio molecular dynamics simulations. This structural knowledge is used to understand the results of air-annealing and Hall effect electrical measurements. The crystallization temperature of a-IO is shown to increase by as much as 325 °C on substituting Ga for In. This increased thermal stability is understood on the basis of the large changes in local structure that Ga undergoes, as compared to In, during crystallization. Hall measurements reveal an initial sharp drop in both carrier concentration and mobility with increasing Ga incorporation, which moderates at >20 at% Ga content. This decline in both the carrier concentration and mobility with increasing Ga is attributed to dilution of the charge-carrying In[BOND]O matrix and to increased structural disorder. The latter effect saturates at high at% Ga.

  7. Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

    Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

    2015-10-01

    We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

  8. Nano sulfide and oxide semiconductors as promising materials for studies by positron annihilation

    Nambissan, P M G

    2013-01-01

    A number of wide band gap sulfide and oxide semiconducting nanomaterial systems were investigated using the experimental techniques of positron lifetime and coincidence Doppler broadening measurements. The results indicated several features of the nanomaterial systems, which were found strongly related to the presence of vacancy-type defects and their clusters. Quantum confinement effects were displayed in these studies as remarkable changes in the positron lifetimes and the lineshape parameters around the same grain sizes below which characteristic blue shifts were observed in the optical absorption spectra. Considerable enhancement in the band gap and significant rise of the positron lifetimes were found occurring when the particle sizes were reduced to very low sizes. The results of doping or substitutions by other cations in semiconductor nanosystems were also interesting. Variously heat-treated TiO 2 nanoparticles were studied recently and change of positron annihilation parameters across the anatase to rutile structural transition are carefully analyzed. Preliminary results of positron annihilation studies on Eu-doped CeO nanoparticles are also presented.

  9. Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

    Leung, T. C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

    1993-01-01

    Studies of SiO2-Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO2-Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown.

  10. Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

    Leung, T.C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K.G.

    1993-01-01

    Studies of SiO 2 -Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO 2 -Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown

  11. Nano sulfide and oxide semiconductors as promising materials for studies by positron annihilation

    Nambissan, P. M. G.

    2013-06-01

    A number of wide band gap sulfide and oxide semiconducting nanomaterial systems were investigated using the experimental techniques of positron lifetime and coincidence Doppler broadening measurements. The results indicated several features of the nanomaterial systems, which were found strongly related to the presence of vacancy-type defects and their clusters. Quantum confinement effects were displayed in these studies as remarkable changes in the positron lifetimes and the lineshape parameters around the same grain sizes below which characteristic blue shifts were observed in the optical absorption spectra. Considerable enhancement in the band gap and significant rise of the positron lifetimes were found occurring when the particle sizes were reduced to very low sizes. The results of doping or substitutions by other cations in semiconductor nanosystems were also interesting. Variously heat-treated TiO2 nanoparticles were studied recently and change of positron annihilation parameters across the anatase to rutile structural transition are carefully analyzed. Preliminary results of positron annihilation studies on Eu-doped CeO nanoparticles are also presented.

  12. On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review

    Chu Manh Hung

    2017-09-01

    Full Text Available Semiconductor metal oxide nanowires (SMO-NWs show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW. SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO2, ZnO, WO3, CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.

  13. Thermal stability of atomic layer deposited WCxNy electrodes for metal oxide semiconductor devices

    Zonensain, Oren; Fadida, Sivan; Fisher, Ilanit; Gao, Juwen; Danek, Michal; Eizenberg, Moshe

    2018-01-01

    This study is a thorough investigation of the chemical, structural, and electrical stability of W based organo-metallic films, grown by atomic layer deposition, for future use as gate electrodes in advanced metal oxide semiconductor structures. In an earlier work, we have shown that high effective work-function (4.7 eV) was produced by nitrogen enriched films (WCxNy) dominated by W-N chemical bonding, and low effective work-function (4.2 eV) was produced by hydrogen plasma resulting in WCx films dominated by W-C chemical bonding. In the current work, we observe, using x-ray diffraction analysis, phase transformation of the tungsten carbide and tungsten nitride phases after 900 °C annealing to the cubic tungsten phase. Nitrogen diffusion is also observed and is analyzed with time-of-flight secondary ion mass spectroscopy. After this 900 °C anneal, WCxNy effective work function tunability is lost and effective work-function values of 4.7-4.8 eV are measured, similar to stable effective work function values measured for PVD TiN up to 900 °C anneal. All the observed changes after annealing are discussed and correlated to the observed change in the effective work function.

  14. Long-term research in Japan: amorphous metals, metal oxide varistors, high-power semiconductors and superconducting generators

    Hane, G.J.; Yorozu, M.; Sogabe, T.; Suzuki, S.

    1985-04-01

    The review revealed that significant activity is under way in the research of amorphous metals, but that little fundamental work is being pursued on metal oxide varistors and high-power semiconductors. Also, the investigation of long-term research program plans for superconducting generators reveals that activity is at a low level, pending the recommendations of a study currently being conducted through Japan's Central Electric Power Council.

  15. Highly stable and imperceptible electronics utilizing photoactivated heterogeneous sol-gel metal-oxide dielectrics and semiconductors.

    Jo, Jeong-Wan; Kim, Jaekyun; Kim, Kyung-Tae; Kang, Jin-Gu; Kim, Myung-Gil; Kim, Kwang-Ho; Ko, Hyungduk; Kim, Jiwan; Kim, Yong-Hoon; Park, Sung Kyu

    2015-02-18

    Incorporation of Zr into an AlOx matrix generates an intrinsically activated ZAO surface enabling the formation of a stable semiconducting IGZO film and good interfacial properties. Photochemically annealed metal-oxide devices and circuits with the optimized sol-gel ZAO dielectric and IGZO semiconductor layers demonstrate the high performance and electrically/mechanically stable operation of flexible electronics fabricated via a low-temperature solution process. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. Infrared rectification in a nanoantenna-coupled metal-oxide-semiconductor tunnel diode.

    Davids, Paul S; Jarecki, Robert L; Starbuck, Andrew; Burckel, D Bruce; Kadlec, Emil A; Ribaudo, Troy; Shaner, Eric A; Peters, David W

    2015-12-01

    Direct rectification of electromagnetic radiation is a well-established method for wireless power conversion in the microwave region of the spectrum, for which conversion efficiencies in excess of 84% have been demonstrated. Scaling to the infrared or optical part of the spectrum requires ultrafast rectification that can only be obtained by direct tunnelling. Many research groups have looked to plasmonics to overcome antenna-scaling limits and to increase the confinement. Recently, surface plasmons on heavily doped Si surfaces were investigated as a way of extending surface-mode confinement to the thermal infrared region. Here we combine a nanostructured metallic surface with a heavily doped Si infrared-reflective ground plane designed to confine infrared radiation in an active electronic direct-conversion device. The interplay of strong infrared photon-phonon coupling and electromagnetic confinement in nanoscale devices is demonstrated to have a large impact on ultrafast electronic tunnelling in metal-oxide-semiconductor (MOS) structures. Infrared dispersion of SiO2 near a longitudinal optical (LO) phonon mode gives large transverse-field confinement in a nanometre-scale oxide-tunnel gap as the wavelength-dependent permittivity changes from 1 to 0, which leads to enhanced electromagnetic fields at material interfaces and a rectified displacement current that provides a direct conversion of infrared radiation into electric current. The spectral and electrical signatures of the nanoantenna-coupled tunnel diodes are examined under broadband blackbody and quantum-cascade laser (QCL) illumination. In the region near the LO phonon resonance, we obtained a measured photoresponsivity of 2.7 mA W(-1) cm(-2) at -0.1 V.

  17. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  18. A CMOS smart temperature and humidity sensor with combined readout.

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  19. Radiation hardening of CMOS-based circuitry in SMART transmitters

    Loescher, D.H.

    1993-02-01

    Process control transmitters that incorporate digital signal processing could be used advantageously in nuclear power plants; however, because such transmitters are too sensitive to radiation, they are not used. The Electric Power Research Institute sponsored work at Sandia National Laboratories under EPRI contract RP2614-58 to determine why SMART transmitters fail when exposed to radiation and to design and demonstrate SMART transmitter circuits that could tolerate radiation. The term ''SMART'' denotes transmitters that contain digital logic. Tests showed that transmitter failure was caused by failure of the complementary metal oxide semiconductors (CMOS)-integrated circuits which are used extensively in commercial transmitters. Radiation-hardened replacements were not available for the radiation-sensitive CMOS circuits. A conceptual design showed that a radiation-tolerant transmitter could be constructed. A prototype for an analog-to-digital converter subsection worked satisfactorily after a total dose of 30 megarads(Si). Encouraging results were obtained from preliminary bench-top tests on a dc-to-dc converter for the power supply subsection

  20. Properties and growth peculiarities of Si{sub 0.30}Ge{sub 0.70} stressor integrated in 14 nm fin-based p-type metal-oxide-semiconductor field-effect transistors

    Hikavyy, A., E-mail: Andriy.Hikavyy@imec.be; Rosseel, E.; Kubicek, S.; Mannaert, G.; Favia, P.; Bender, H.; Loo, R.; Horiguchi, N.

    2016-03-01

    Integration of Si{sub 0.30}Ge{sub 0.70} in the Source/Drain (S/D) areas of metal oxide semiconductor transistors built according to 14 nm technological node rules has been shown. SiGe properties and growth peculiarities are presented and elaborated. In order to preserve the fin structures during a pre-epitaxy surface preparation, the H{sub 2} bake pressure had to be increased to 19,998 Pa at 800 °C. Influence of this bake on the Si recess in the S/D areas is presented. Excellent quality of both the raised and the embedded Si{sub 0.30}Ge{sub 0.70} was demonstrated by transmission electron microscopy inspections. Energy-dispersive X-ray spectroscopy measurement showed two stages of SiGe growth for the embedded case: first with a lower Ge content at the beginning of the deposition until the (111) facets are formed, and second with a higher Ge content which is governed by the growth on (111) planes. Nano-beam diffraction analysis showed that SiGe grown in the S/D areas of p-type metal-oxide-semiconductor field-effect transistor is fully elastically relaxed in the direction across the fin and partially strained along the fin. Finally, a strain accumulation effect in the chain of transistors has been observed. - Highlights: • Si{sub 0.30}Ge{sub 0.70} stressor has been implemented in the 14 nm technology node CMOS flow. • Embedded and raised variants have been investigated. • High Si{sub 0.30}Ge{sub 0.70} quality was confirmed. • Si{sub 0.30}Ge{sub 0.70} layer is elastically relaxed across the fin direction. • Partial stress presence and stress accumulation effect were observed.

  1. Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

    Yi Zhao

    2012-08-01

    Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO2 and La2O3. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La2O3, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

  2. Characterisation of diode-connected SiGe BiCMOS HBTs for space applications

    Venter, Johan; Sinha, Saurabh; Lambrechts, Wynand

    2016-02-01

    Silicon-germanium (SiGe) bipolar complementary metal-oxide semiconductor (BiCMOS) transistors have vertical doping profiles reaching deeper into the substrate when compared to lateral CMOS transistors. Apart from benefiting from high-speed, high current gain and low-output resistance due to its vertical profile, BiCMOS technology is increasingly becoming a preferred technology for researchers to realise next-generation space-based optoelectronic applications. BiCMOS transistors have inherent radiation hardening, to an extent predictable cryogenic performance and monolithic integration potential. SiGe BiCMOS transistors and p-n junction diodes have been researched and used as a primary active component for over the last two decades. However, further research can be conducted with diode-connected heterojunction bipolar transistors (HBTs) operating at cryogenic temperatures. This work investigates these characteristics and models devices by adapting standard fabrication technology components. This work focuses on measurements of the current-voltage relationship (I-V curves) and capacitance-voltage relationships (C-V curves) of diode-connected HBTs. One configuration is proposed and measured, which is emitterbase shorted. The I-V curves are measured for various temperature points ranging from room temperature (300 K) to the temperature of liquid nitrogen (77 K). The measured datasets are used to extract a model of the formed diode operating at cryogenic temperatures and used as a standard library component in computer aided software designs. The advantage of having broad-range temperature models of SiGe transistors becomes apparent when considering implementation of application-specific integrated circuits and silicon-based infrared radiation photodetectors on a single wafer, thus shortening interconnects and lowering parasitic interference, decreasing the overall die size and improving on overall cost-effectiveness. Primary applications include space-based geothermal

  3. Device Innovation and Material Challenges at the Limits of CMOS Technology

    Solomon, P. M.

    2000-08-01

    Scaling of the predominant silicon complementary metal-oxide semiconductor (CMOS) technology is finally approaching an end after decades of exponential growth. This review explores the reasons for this limit and some of the strategies available to the semiconductor industry to continue the technology extension. Evolutionary change to the silicon transistor will be pursued as long as possible, with increasing demands being placed on materials. Eventually new materials such a silicon-germanium may be used, and new device topologies such as the double-gated transistor may be employed. These strategies are being pursued in research organizations today. It is likely that planar technology will reach its limit with devices on the 10-nm scale, and then the third dimension will have to be exploited more efficiently to achieve further performance and density improvements.

  4. Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

    Olsen, Sarah H.

    2002-01-01

    Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

  5. Physics and Chemistry on Well-Defined Semiconductor and Oxide Surfaces

    Chen, Peijun

    High resolution electron energy loss spectroscopy (HREELS) and other surface spectroscopic techniques have been employed to investigate the following two classes of surface/interface phenomena on well-defined semiconductor and oxide surfaces: (i) the fundamental physical and chemical processes involved in gas-solid interaction on silicon single crystal surfaces, and (ii) the physical and chemical properties of metal-oxide interfaces. The particular systems reported in this dissertation are: NH_3, PH_3 and B_ {10}H_{14} on Si(111)-(7 x 7); NH_3 on Si(100) -(2 x 1); atomic H on Si(111)-(7 x 7) and boron-modified Si(111); Al on Al_2O_3 and Sn on SiO_2.. On silicon surfaces, the surface dangling bonds function as the primary adsorption sites where surface chemical processes take place. The unambiguous identification of surface species by vibrational spectroscopy allows the elementary steps involved in these surface chemical processes to be followed on a molecular level. For adsorbate molecules such as NH_3 and PH_3, the nature of the initial low temperature (100 -300 K) adsorption is found to be dissociative, while that for B_{10}H_ {14} is non-dissociative. This has been deduced based upon the presence (or absence) of specific characteristic vibrational mode(s) on surface. By following the evolution of surface species as a function of temperature, the elementary steps leading to silicon nitride thin film growth and doping of silicon are elucidated. In the case of NH_3 on Si(111)-(7 x 7) and Si(100)-(2 x 1), a detailed understanding on the role of substrate surface structure in controlling the surface reactivity has been gained on the basis of a Si adatom backbond-strain relief mechanism on the Si(111) -(7 x 7). The electronic modification to Si(111) surface by subsurface boron doping has been shown to quench its surface chemistry, even for the most aggressive atomic H. This discovery is potentially meaningful to the technology of gas-phase silicon etching. The

  6. Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

    Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

    2001-01-01

    We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

  7. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2011-10-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

  8. The CMOS Integration of a Power Inverter

    Mannarino, Eric Francis

    2016-01-01

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this proce...

  9. Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

    Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

    2003-05-01

    Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

  10. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  11. Low Power Operation of Temperature-Modulated Metal Oxide Semiconductor Gas Sensors

    Javier Burgués

    2018-01-01

    Full Text Available Mobile applications based on gas sensing present new opportunities for low-cost air quality monitoring, safety, and healthcare. Metal oxide semiconductor (MOX gas sensors represent the most prominent technology for integration into portable devices, such as smartphones and wearables. Traditionally, MOX sensors have been continuously powered to increase the stability of the sensing layer. However, continuous power is not feasible in many battery-operated applications due to power consumption limitations or the intended intermittent device operation. This work benchmarks two low-power, duty-cycling, and on-demand modes against the continuous power one. The duty-cycling mode periodically turns the sensors on and off and represents a trade-off between power consumption and stability. On-demand operation achieves the lowest power consumption by powering the sensors only while taking a measurement. Twelve thermally modulated SB-500-12 (FIS Inc. Jacksonville, FL, USA sensors were exposed to low concentrations of carbon monoxide (0–9 ppm with environmental conditions, such as ambient humidity (15–75% relative humidity and temperature (21–27 °C, varying within the indicated ranges. Partial Least Squares (PLS models were built using calibration data, and the prediction error in external validation samples was evaluated during the two weeks following calibration. We found that on-demand operation produced a deformation of the sensor conductance patterns, which led to an increase in the prediction error by almost a factor of 5 as compared to continuous operation (2.2 versus 0.45 ppm. Applying a 10% duty-cycling operation of 10-min periods reduced this prediction error to a factor of 2 (0.9 versus 0.45 ppm. The proposed duty-cycling powering scheme saved up to 90% energy as compared to the continuous operating mode. This low-power mode may be advantageous for applications that do not require continuous and periodic measurements, and which can tolerate

  12. Low Power Operation of Temperature-Modulated Metal Oxide Semiconductor Gas Sensors.

    Burgués, Javier; Marco, Santiago

    2018-01-25

    Mobile applications based on gas sensing present new opportunities for low-cost air quality monitoring, safety, and healthcare. Metal oxide semiconductor (MOX) gas sensors represent the most prominent technology for integration into portable devices, such as smartphones and wearables. Traditionally, MOX sensors have been continuously powered to increase the stability of the sensing layer. However, continuous power is not feasible in many battery-operated applications due to power consumption limitations or the intended intermittent device operation. This work benchmarks two low-power, duty-cycling, and on-demand modes against the continuous power one. The duty-cycling mode periodically turns the sensors on and off and represents a trade-off between power consumption and stability. On-demand operation achieves the lowest power consumption by powering the sensors only while taking a measurement. Twelve thermally modulated SB-500-12 (FIS Inc. Jacksonville, FL, USA) sensors were exposed to low concentrations of carbon monoxide (0-9 ppm) with environmental conditions, such as ambient humidity (15-75% relative humidity) and temperature (21-27 °C), varying within the indicated ranges. Partial Least Squares (PLS) models were built using calibration data, and the prediction error in external validation samples was evaluated during the two weeks following calibration. We found that on-demand operation produced a deformation of the sensor conductance patterns, which led to an increase in the prediction error by almost a factor of 5 as compared to continuous operation (2.2 versus 0.45 ppm). Applying a 10% duty-cycling operation of 10-min periods reduced this prediction error to a factor of 2 (0.9 versus 0.45 ppm). The proposed duty-cycling powering scheme saved up to 90% energy as compared to the continuous operating mode. This low-power mode may be advantageous for applications that do not require continuous and periodic measurements, and which can tolerate slightly higher

  13. Bipolar resistive switching in metal-insulator-semiconductor nanostructures based on silicon nitride and silicon oxide

    Koryazhkina, M. N.; Tikhov, S. V.; Mikhaylov, A. N.; Belov, A. I.; Korolev, D. S.; Antonov, I. N.; Karzanov, V. V.; Gorshkov, O. N.; Tetelbaum, D. I.; Karakolis, P.; Dimitrakis, P.

    2018-03-01

    Bipolar resistive switching in metal-insulator-semiconductor (MIS) capacitor-like structures with an inert Au top electrode and a Si3N4 insulator nanolayer (6 nm thick) has been observed. The effect of a highly doped n +-Si substrate and a SiO2 interlayer (2 nm) is revealed in the changes in the semiconductor space charge region and small-signal parameters of parallel and serial equivalent circuit models measured in the high- and low-resistive capacitor states, as well as under laser illumination. The increase in conductivity of the semiconductor capacitor plate significantly reduces the charging and discharging times of capacitor-like structures.

  14. High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

    Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

    2014-05-21

    We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

  15. Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

    Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2012-04-01

    In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

  16. Linear analysis of signal and noise characteristics of a nonlinear CMOS active-pixel detector for mammography

    Yun, Seungman [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Kim, Ho Kyung, E-mail: hokyung@pusan.ac.kr [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Center for Advanced Medical Engineering Research, Pusan National University, Busan 46241 (Korea, Republic of); Han, Jong Chul; Kam, Soohwa [School of Mechanical Engineering, Pusan National University, Busan 46241 (Korea, Republic of); Youn, Hanbean [Department of Radiation Oncology, Pusan National University Yangsan Hospital, Yangsan, Gyeongsangnam-do 50612 (Korea, Republic of); Cunningham, Ian A. [Robarts Research Institute, Western University, London, Ontario N6A 5C1 (Canada)

    2017-03-01

    The imaging properties of a complementary metal-oxide-semiconductor (CMOS) active-pixel photodiode array coupled to a thin gadolinium-based granular phosphor screen with a fiber-optic faceplate are investigated. It is shown that this system has a nonlinear response at low detector exposure levels (<10 mR), resulting in an over-estimation of the detective quantum efficiency (DQE) by a factor of two in some cases. Errors in performance metrics on this scale make it difficult to compare new technologies with established systems and predict performance benchmarks that can be achieved in practice and help understand performance bottlenecks. It is shown the CMOS response is described by a power-law model that can be used to linearize image data. Linearization removed an unexpected dependence of the DQE on detector exposure level. - Highlights: • A nonlinear response of a CMOS detector at low exposure levels can overestimate DQE. • A power-law form can model the response of a CMOS detector at low exposure levels, and can be used to linearize image data. • Performance evaluation of nonlinear imaging systems must incorporate adequate linearizations.

  17. Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom

    Hang Song

    2017-01-01

    Full Text Available A digital breast cancer detection system using 65 nm technology complementary metal oxide semiconductor (CMOS integrated circuits with rotating 4 × 4 antenna array is presented. Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T switching matrices. Radar signals are received and converted to digital signals by CMOS equivalent time sampling circuits. By rotating the 4 × 4 antenna array, the reference signal is obtained by averaging the waveforms from various positions to extract the breast phantom target response. A signal alignment algorithm is proposed to compensate the phase shift of the signals caused by the system jitter. After extracting the scattered signal from the target, a bandpass filter is applied to reduce the noise caused by imperfect subtraction between original and the reference signals. The confocal imaging algorithm for rotating antennas is utilized to reconstruct the breast image. A 1 cm3 bacon block as a cancer phantom target in a rubber substrate as a breast fat phantom can be detected with reduced artifacts.

  18. Pick-and-place process for sensitivity improvement of the capacitive type CMOS MEMS 2-axis tilt sensor

    Chang, Chun-I.; Tsai, Ming-Han; Liu, Yu-Chia; Sun, Chih-Ming; Fang, Weileun

    2013-09-01

    This study exploits the foundry available complimentary metal-oxide-semiconductor (CMOS) process and the packaging house available pick-and-place technology to implement a capacitive type micromachined 2-axis tilt sensor. The suspended micro mechanical structures such as the spring, stage and sensing electrodes are fabricated using the CMOS microelectromechanical systems (MEMS) processes. A bulk block is assembled onto the suspended stage by pick-and-place technology to increase the proof-mass of the tilt sensor. The low temperature UV-glue dispensing and curing processes are employed to bond the block onto the stage. Thus, the sensitivity of the CMOS MEMS capacitive type 2-axis tilt sensor is significantly improved. In application, this study successfully demonstrates the bonding of a bulk solder ball of 100 µm in diameter with a 2-axis tilt sensor fabricated using the standard TSMC 0.35 µm 2P4M CMOS process. Measurements show the sensitivities of the 2-axis tilt sensor are increased for 2.06-fold (x-axis) and 1.78-fold (y-axis) after adding the solder ball. Note that the sensitivity can be further improved by reducing the parasitic capacitance and the mismatch of sensing electrodes caused by the solder ball.

  19. Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

    Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

    2011-01-01

    We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

  20. Sol–gel deposited ceria thin films as gate dielectric for CMOS ...

    Sol–gel deposited ceria thin films as gate dielectric for CMOS technology. ANIL G KHAIRNAR ... The semiconductor roadmap following Moore's law is responsible for ..... The financial support from University Grants Commi- ssion (UGC), New ...

  1. Searching Room Temperature Ferromagnetism in Wide Gap Semiconductors Fe-doped Strontium Titanate and Zinc Oxide

    Pereira, LMC; Wahl, U

    Scientific findings in the very beginning of the millennium are taking us a step further in the new paradigm of technology: spintronics. Upgrading charge-based electronics with the additional degree of freedom of the carriers spin-state, spintronics opens a path to the birth of a new generation of devices with the potential advantages of non-volatility and higher processing speed, integration densities and power efficiency. A decisive step towards this new age lies on the attribution of magnetic properties to semiconductors, the building block of today's electronics, that is, the realization of ferromagnetic semiconductors (FS) with critical temperatures above room temperature. Unfruitful search for intrinsic RT FS lead to the concept of Dilute(d) Magnetic Semiconductors (DMS): ordinary semiconductor materials where 3 d transition metals randomly substitute a few percent of the matrix cations and, by some long-range mechanism, order ferromagnetically. The times are of intense research activity and the last fe...

  2. Method to quantify the delocalization of electronic states in amorphous semiconductors and its application to assessing charge carrier mobility of p -type amorphous oxide semiconductors

    de Jamblinne de Meux, A.; Pourtois, G.; Genoe, J.; Heremans, P.

    2018-01-01

    Amorphous semiconductors are usually characterized by a low charge carrier mobility, essentially related to their lack of long-range order. The development of such material with higher charge carrier mobility is hence challenging. Part of the issue comes from the difficulty encountered by first-principles simulations to evaluate concepts such as the electron effective mass for disordered systems since the absence of periodicity induced by the disorder precludes the use of common concepts derived from condensed matter physics. In this paper, we propose a methodology based on first-principles simulations that partially solves this problem, by quantifying the degree of delocalization of a wave function and of the connectivity between the atomic sites within this electronic state. We validate the robustness of the proposed formalism on crystalline and molecular systems and extend the insights gained to disordered/amorphous InGaZnO4 and Si. We also explore the properties of p -type oxide semiconductor candidates recently reported to have a low effective mass in their crystalline phases [G. Hautier et al., Nat. Commun. 4, 2292 (2013), 10.1038/ncomms3292]. Although in their amorphous phase none of the candidates present a valence band with delocalization properties matching those found in the conduction band of amorphous InGaZnO4, three of the seven analyzed materials show some potential. The most promising candidate, K2Sn2O3 , is expected to possess in its amorphous phase a slightly higher hole mobility than the electron mobility in amorphous silicon.

  3. Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix

    Lee, Ja Bin; Kim, Ki Woong; Lee, Jun Seok; An, Gwang Guk; Hong, Jin Pyo

    2011-01-01

    Half-metallic Heusler material Co 2 FeAl 0.5 Si 0.5 (CFAS) nano-particles (NPs) embedded in metal-oxide-semiconductor (MOS) structures with thin HfO 2 tunneling and MgO control oxides were investigated. The CFAS NPs were prepared by rapid thermal annealing. The formation of well-controlled CFAS NPs on thin HfO 2 tunneling oxide was confirmed by atomic force microscopy (AFM). Memory characteristics of CFAS NPs in MOS devices exhibited a large memory window of 4.65 V, as well as good retention and endurance times of 10 5 cycles and 10 9 s, respectively, demonstrating the potential of CFAS NPs as promising candidates for use in charge storage.

  4. Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

    Tan Zhen; Zhao Lian-Feng; Wang Jing; Xu Jun

    2014-01-01

    Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density D it of the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness (EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy (HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO 2 or Al 2 O 3 dielectric layers. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  5. Extending Moore’s Law for Silicon CMOS using More-Moore and More-than-Moore Technologies

    Hussain, Aftab M.

    2016-12-01

    With the advancement of silicon electronics under threat from physical limits to dimensional scaling, the International Technology Roadmap for Semiconductors (ITRS) released a white paper in 2008, detailing the ways in which the semiconductor industry can keep itself continually growing in the twenty-first century. Two distinct paths were proposed: More-Moore and More-than-Moore. While More-Moore approach focuses on the continued use of state-of-the-art, complementary metal oxide semiconductor (CMOS) technology for next generation electronics, More-than-Moore approach calls for a disruptive change in the system architecture and integration strategies. In this doctoral thesis, we investigate both the approaches to obtain performance improvement in the state-of-the-art, CMOS electronics. We present a novel channel material, SiSn, for fabrication of CMOS circuits. This investigation is in line with the More-Moore approach because we are relying on the established CMOS industry infrastructure to obtain an incremental change in the integrated circuit (IC) performance by replacing silicon channel with SiSn. We report a simple, low-cost and CMOS compatible process for obtaining single crystal SiSn wafers. Tin (Sn) is deposited on silicon wafers in the form of a metallic thin film and annealed to facilitate diffusion into the silicon lattice. This diffusion provides for sufficient SiSn layer at the top surface for fabrication of CMOS devices. We report a lowering of band gap and enhanced mobility for SiSn channel MOSFETs compared to silicon control devices. We also present a process for fabrication of vertically integrated flexible silicon to form 3D integrated circuits. This disruptive change in the state-of-the-art, in line with the More-than-Moore approach, promises to increase the performance per area of a silicon chip. We report a process for stacking and bonding these pieces with polymeric bonding and interconnecting them using copper through silicon vias (TSVs). We

  6. Experimental observation of the improvement in MTF from backthinning a CMOS direct electron detector

    McMullan, G.; Faruqi, A.R.; Henderson, R.; Guerrini, N.; Turchetta, R.; Jacobs, A.; Hoften, G. van

    2009-01-01

    The advantages of backthinning monolithic active pixel sensors (MAPS) based on complementary metal oxide semiconductor (CMOS) direct electron detectors for electron microscopy have been discussed previously; they include better spatial resolution (modulation transfer function or MTF) and efficiency at all spatial frequencies (detective quantum efficiency or DQE). It was suggested that a 'thin' CMOS detector would have the most outstanding properties because of a reduction in the proportion of backscattered electrons. In this paper we show, theoretically (using Monte Carlo simulations of electron trajectories) and experimentally that this is indeed the case. The modulation transfer functions of prototype backthinned CMOS direct electron detectors have been measured at 300 keV. At zero spatial frequency, in non-backthinned 700-μm-thick detectors, the backscattered component makes up over 40% of the total signal but, by backthinning to 100, 50 or 35 μm, this can be reduced to 25%, 15% and 10%, respectively. For the 35 μm backthinned detector, this reduction in backscatter increases the MTF by 40% for spatial frequencies between 0.1 and 1.0 Nyquist. As discussed in the main text, reducing backscattering in backthinned detectors should also improve DQE.

  7. An investigation of medical radiation detection using CMOS image sensors in smartphones

    Kang, Han Gyu [Department of Senior Healthcare, Graduate School of Eulji University, Daejeon 301-746 (Korea, Republic of); Song, Jae-Jun [Department of Otorhinolaryngology-Head & Neck Surgery, Korea University, Guro Hospital,148, Gurodong-ro, Guro-gu, Seoul 152-703 (Korea, Republic of); Lee, Kwonhee [Graduate Program in Bio-medical Science, Korea University, 2511 Sejong-ro, Sejong City 339-770 (Korea, Republic of); Nam, Ki Chang [Department of Medical Engineering, College of Medicine, Dongguk University, 32 Dongguk-ro, Goyang-si, Gyeonggi-do 410-820 (Korea, Republic of); Hong, Seong Jong; Kim, Ho Chul [Department of Radiological Science, Eulji University, 553 Yangji-dong, Sujeong-gu, Seongnam-si, Gyeonggi-do 431-713 (Korea, Republic of)

    2016-07-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  8. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    Ghoneim, Mohamed T.

    2016-05-18

    We present a comprehensive electrical performance assessment of hafnium silicate (HfSiOₓ) high-κ dielectric and titanium-nitride (TiN) metal-gate-integrated FinFET-based complementary-metal-oxide-semiconductor (CMOS) on flexible silicon on insulator. The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied along and across the transistor channel lengths through a bending range of 0.5-5 cm radii for n-type and p-type FinFETs. Electrical measurements were carried out before and after bending, and all the bending measurements were taken in the actual flexed (bent) state to avoid relaxation and stress recovery. Global stress from substrate bending affects the devices in different ways compared with the well-studied uniaxial/biaxial localized strain. The global stress is dependent on the type of channel charge carriers, the orientation of the bending axis, and the physical gate length of the device. We, therefore, outline useful insights on the design strategies of flexible FinFETs in future free-form electronic applications.

  9. CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications

    Hussain, Aftab M.

    2015-11-26

    Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today\\'s digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  10. Performance analysis and enhancement for visible light communication using CMOS sensors

    Guan, Weipeng; Wu, Yuxiang; Xie, Canyu; Fang, Liangtao; Liu, Xiaowei; Chen, Yingcong

    2018-03-01

    Complementary Metal-Oxide-Semiconductor (CMOS) sensors are widely used in mobile-phone and cameras. Hence, it is attractive if these camera can be used as the receivers of visible light communication (VLC). Using the rolling shutter mechanism can increase the data rate of VLC based on CMOS camera, and different techniques have been proposed to improve the demodulation of the rolling shutter mechanism. However, these techniques are too complexity. In this work, we demonstrate and analyze the performance of the VLC link using CMOS camera for different LED luminaires for the first time in our knowledge. Experimental evaluation to compare their bit-error-rate (BER) performances and demodulation are also performed, and it can be summarized that just need to change the LED luminaire with more uniformity light output, the blooming effect would not exist; which not only can reduce the complexity of the demodulation but also enhance the communication quality. In addition, we propose and demonstrate to use contrast limited adaptive histogram equalization to extend the transmission distance and mitigate the influence of the background noise. And the experimental results show that the BER can be decreased by an order of magnitude by using the proposed method.

  11. A High-Dynamic-Range Optical Remote Sensing Imaging Method for Digital TDI CMOS

    Taiji Lan

    2017-10-01

    Full Text Available The digital time delay integration (digital TDI technology of the complementary metal-oxide-semiconductor (CMOS image sensor has been widely adopted and developed in the optical remote sensing field. However, the details of targets that have low illumination or low contrast in scenarios of high contrast are often drowned out because of the superposition of multi-stage images in digital domain multiplies the read noise and the dark noise, thus limiting the imaging dynamic range. Through an in-depth analysis of the information transfer model of digital TDI, this paper attempts to explore effective ways to overcome this issue. Based on the evaluation and analysis of multi-stage images, the entropy-maximized adaptive histogram equalization (EMAHE algorithm is proposed to improve the ability of images to express the details of dark or low-contrast targets. Furthermore, in this paper, an image fusion method is utilized based on gradient pyramid decomposition and entropy weighting of different TDI stage images, which can improve the detection ability of the digital TDI CMOS for complex scenes with high contrast, and obtain images that are suitable for recognition by the human eye. The experimental results show that the proposed methods can effectively improve the high-dynamic-range imaging (HDRI capability of the digital TDI CMOS. The obtained images have greater entropy and average gradients.

  12. An investigation of medical radiation detection using CMOS image sensors in smartphones

    Kang, Han Gyu; Song, Jae-Jun; Lee, Kwonhee; Nam, Ki Chang; Hong, Seong Jong; Kim, Ho Chul

    2016-01-01

    Medical radiation exposure to patients has increased with the development of diagnostic X-ray devices and multi-channel computed tomography (CT). Despite the fact that the low-dose CT technique can significantly reduce medical radiation exposure to patients, the increasing number of CT examinations has increased the total medical radiation exposure to patients. Therefore, medical radiation exposure to patients should be monitored to prevent cancers caused by diagnostic radiation. However, without using thermoluminescence or glass dosimeters, it is hardly measure doses received by patients during medical examinations accurately. Hence, it is necessary to develop radiation monitoring devices and algorithms that are reasonably priced and have superior radiation detection efficiencies. The aim of this study is to investigate the feasibility of medical dose measurement using complementary metal oxide semiconductor (CMOS) sensors in smartphone cameras with an algorithm to extract the X-ray interacted pixels. We characterized the responses of the CMOS sensors in a smartphone with respect to the X-rays generated by a general diagnostic X-ray system. The characteristics of the CMOS sensors in a smartphone camera, such as dose response linearity, dose rate dependence, energy dependence, angular dependence, and minimum detectable activity were evaluated. The high energy gamma-ray of 662 keV from Cs-137 can be detected using the smartphone camera. The smartphone cameras which employ the developed algorithm can detect medical radiations.

  13. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer

    Sho Asano

    2017-10-01

    Full Text Available This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS with capacitive sensing circuits on a low temperature cofired ceramic (LTCC interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

  14. Application of CMOS charge-sensitive preamplifier in triple-GEM detector

    Lai Yongfang; Li Jin; Chinese Academy of Sciences, Beijing; Deng Zhi; Li Yulan; Liu Yinong; Li Yuanjing

    2006-01-01

    Among the various micro-pattern gas detectors (MPGD) that are available, the gas electron multiplier (GEM) detector is an attractive gas detector that has been used in particle physics experiments. However the GEM detector usually needs thousands of preamplifier units for its large number of micro-pattern readout strips or pads, which leads to considerable difficulties and complexities for front end electronics (FEE). Nowadays, by making use of complementary metal-oxide semiconductor (CMOS)-based application specific integrated circuit (ASIC), it is feasible to integrate hundreds of preamplifier units and other signal process circuits in a small-sized chip, which can be bound to the readout strips or pads of a micro-pattern particle detector (MPPD). Therefore, CMOS ASIC may provide an ideal solution to the readout problem of MPPD. In this article, a triple GEM detector is constructed and one of its readout strips is connected to a CMOS charge-sensitive preamplifier chip. The chip was exposed to an 55 Fe source of 5.9 kev X-ray, and the amplitude spectrum of the chip was tested, and it was found that the energy resolution was approximately 27%, which indicates that the chip can be used in triple GEM detectors. (authors)

  15. A research on radiation calibration of high dynamic range based on the dual channel CMOS

    Ma, Kai; Shi, Zhan; Pan, Xiaodong; Wang, Yongsheng; Wang, Jianghua

    2017-10-01

    The dual channel complementary metal-oxide semiconductor (CMOS) can get high dynamic range (HDR) image through extending the gray level of the image by using image fusion with high gain channel image and low gain channel image in a same frame. In the process of image fusion with dual channel, it adopts the coefficients of radiation response of a pixel from dual channel in a same frame, and then calculates the gray level of the pixel in the HDR image. For the coefficients of radiation response play a crucial role in image fusion, it has to find an effective method to acquire these parameters. In this article, it makes a research on radiation calibration of high dynamic range based on the dual channel CMOS, and designs an experiment to calibrate the coefficients of radiation response for the sensor it used. In the end, it applies these response parameters in the dual channel CMOS which calibrates, and verifies the correctness and feasibility of the method mentioned in this paper.

  16. A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

    Fu, Guoqing; Sonkusale, Sameer R

    2018-06-01

    Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

  17. CMOS direct time interval measurement of long-lived luminescence lifetimes.

    Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-01-01

    We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

  18. The Intersection of CMOS Microsystems and Upconversion Nanoparticles for Luminescence Bioimaging and Bioassays

    Liping Wei

    2014-09-01

    Full Text Available Organic fluorophores and quantum dots are ubiquitous as contrast agents for bio-imaging and as labels in bioassays to enable the detection of biological targets and processes. Upconversion nanoparticles (UCNPs offer a different set of opportunities as labels in bioassays and for bioimaging. UCNPs are excited at near-infrared (NIR wavelengths where biological molecules are optically transparent, and their luminesce in the visible and ultraviolet (UV wavelength range is suitable for detection using complementary metal-oxide-semiconductor (CMOS technology. These nanoparticles provide multiple sharp emission bands, long lifetimes, tunable emission, high photostability, and low cytotoxicity, which render them particularly useful for bio-imaging applications and multiplexed bioassays. This paper surveys several key concepts surrounding upconversion nanoparticles and the systems that detect and process the corresponding luminescence signals. The principle of photon upconversion, tuning of emission wavelengths, UCNP bioassays, and UCNP time-resolved techniques are described. Electronic readout systems for signal detection and processing suitable for UCNP luminescence using CMOS technology are discussed. This includes recent progress in miniaturized detectors, integrated spectral sensing, and high-precision time-domain circuits. Emphasis is placed on the physical attributes of UCNPs that map strongly to the technical features that CMOS devices excel in delivering, exploring the interoperability between the two technologies.

  19. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer.

    Asano, Sho; Muroyama, Masanori; Nakayama, Takahiro; Hata, Yoshiyuki; Nonomura, Yutaka; Tanaka, Shuji

    2017-10-25

    This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively.

  20. A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

    Zhang, Fan; Niu, Hanben

    2016-06-29

    In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

  1. Towards real-time VMAT verification using a prototype, high-speed CMOS active pixel sensor.

    Zin, Hafiz M; Harris, Emma J; Osmond, John P F; Allinson, Nigel M; Evans, Philip M

    2013-05-21

    This work investigates the feasibility of using a prototype complementary metal oxide semiconductor active pixel sensor (CMOS APS) for real-time verification of volumetric modulated arc therapy (VMAT) treatment. The prototype CMOS APS used region of interest read out on the chip to allow fast imaging of up to 403.6 frames per second (f/s). The sensor was made larger (5.4 cm × 5.4 cm) using recent advances in photolithographic technique but retains fast imaging speed with the sensor's regional read out. There is a paradigm shift in radiotherapy treatment verification with the advent of advanced treatment techniques such as VMAT. This work has demonstrated that the APS can track multi leaf collimator (MLC) leaves moving at 18 mm s(-1) with an automatic edge tracking algorithm at accuracy better than 1.0 mm even at the fastest imaging speed. Evaluation of the measured fluence distribution for an example VMAT delivery sampled at 50.4 f/s was shown to agree well with the planned fluence distribution, with an average gamma pass rate of 96% at 3%/3 mm. The MLC leaves motion and linac pulse rate variation delivered throughout the VMAT treatment can also be measured. The results demonstrate the potential of CMOS APS technology as a real-time radiotherapy dosimeter for delivery of complex treatments such as VMAT.

  2. Complementary metal-oxide semiconductor compatible source of single photons at near-visible wavelengths

    Cernansky, Robert; Martini, Francesco; Politi, Alberto

    2018-02-01

    We demonstrate on chip generation of correlated pairs of photons in the near-visible spectrum using a CMOS compatible PECVD Silicon Nitride photonic device. Photons are generated via spontaneous four wave mixing enhanced by a ring resonator with high quality Q-factor of 320,000 resulting in a generation rate of 950,000 $\\frac{pairs}{mW}$. The high brightness of this source offers the opportunity to expand photonic quantum technologies over a broad wavelength range and provides a path to develop fully integrated quantum chips working at room temperature.

  3. A new metallic oxide semiconductor field effect transistor detector for use of in vivo dosimetry

    Qi Zhenyu; Deng Xiaowu; Huang Shaomin; Kang Dehua; Anatoly Rosenfeld

    2006-01-01

    Objective: To investigate the application of a recently developed metallic oxide semiconductor field effect transistor (MOSFET) detector for use in vivo dosimetry. Methods: The MOSFET detector was calibrated for X-ray beams of 8 MV and 15 MV, as well as electron beams with energy of 6,8,12 and 18 MeV. The dose linearity of the MOSFET detector was investigated for the doses ranging from 0 up to 50 Gy using 8 MV X-ray beams. Angular effect was evaluated as well in a cylindrical PMMA phantom by changing the beam entrance angle every 15 degree clockwise. The MOSFET detector was then used for a breast cancer patient in vivo dose measurement, after the treatment plan was verified in a water phantom using a NE-2571 ion chamber, in vivo measurements were performed in the first and last treatment, and once per week during the whole treatment. The measured doses were then compared with planning dose to evaluate the accuracy of each treatment. Results: The MOSFET detector represented a good energy response for X-ray beams of 8 MV and 15 MV, and for electron beams with energy of 6 MeV up to 18 MeV. With the 6 V bias, Dose linearity error of the MOSFET detector was within 3.0% up to approximately 50 Gy, which can be significantly reduced to 1% when the detector was calibrated before and after each measurement. The MOSFET response varied within 1.5% for angles from 270 degree to 90 degree. However, maximum error of 10.0% was recorded comparing MOSFET response between forward and backward direction. In vivo measurement for a breast cancer patient using 3DCRT showed that, the average dose deviation between measurement and calculation was 2.8%, and the maximum error was less then 5.0%. Conclusions: The new MOSFET detector, with its advantages of being in size, easy use, good energy response and dose linearity, can be used for in vivo dose measurement. (authors)

  4. Multichannel, time-resolved picosecond laser ultrasound imaging and spectroscopy with custom complementary metal-oxide-semiconductor detector

    Smith, Richard J.; Light, Roger A.; Johnston, Nicholas S.; Pitter, Mark C.; Somekh, Mike G.; Sharples, Steve D.

    2010-01-01

    This paper presents a multichannel, time-resolved picosecond laser ultrasound system that uses a custom complementary metal-oxide-semiconductor linear array detector. This novel sensor allows parallel phase-sensitive detection of very low contrast modulated signals with performance in each channel comparable to that of a discrete photodiode and a lock-in amplifier. Application of the instrument is demonstrated by parallelizing spatial measurements to produce two-dimensional thickness maps on a layered sample, and spectroscopic parallelization is demonstrated by presenting the measured Brillouin oscillations from a gallium arsenide wafer. This paper demonstrates the significant advantages of our approach to pump probe systems, especially picosecond ultrasonics.

  5. Multichannel, time-resolved picosecond laser ultrasound imaging and spectroscopy with custom complementary metal-oxide-semiconductor detector

    Smith, Richard J.; Light, Roger A.; Johnston, Nicholas S.; Pitter, Mark C.; Somekh, Mike G. [Institute of Biophysics, Imaging and Optical Science, University of Nottingham, Nottinghamshire NG7 2RD (United Kingdom); Sharples, Steve D. [Applied Optics Group, Electrical Systems and Optics Research Division, University of Nottingham, Nottinghamshire NG7 2RD (United Kingdom)

    2010-02-15

    This paper presents a multichannel, time-resolved picosecond laser ultrasound system that uses a custom complementary metal-oxide-semiconductor linear array detector. This novel sensor allows parallel phase-sensitive detection of very low contrast modulated signals with performance in each channel comparable to that of a discrete photodiode and a lock-in amplifier. Application of the instrument is demonstrated by parallelizing spatial measurements to produce two-dimensional thickness maps on a layered sample, and spectroscopic parallelization is demonstrated by presenting the measured Brillouin oscillations from a gallium arsenide wafer. This paper demonstrates the significant advantages of our approach to pump probe systems, especially picosecond ultrasonics.

  6. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-03-03

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

  7. High-performance carbon-nanotube-based complementary field-effect-transistors and integrated circuits with yttrium oxide

    Liang, Shibo; Zhang, Zhiyong, E-mail: zyzhang@pku.edu.cn; Si, Jia; Zhong, Donglai; Peng, Lian-Mao, E-mail: lmpeng@pku.edu.cn [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China)

    2014-08-11

    High-performance p-type carbon nanotube (CNT) transistors utilizing yttrium oxide as gate dielectric are presented by optimizing oxidization and annealing processes. Complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) are then fabricated on CNTs, and the p- and n-type devices exhibit symmetrical high performances, especially with low threshold voltage near to zero. The corresponding CMOS CNT inverter is demonstrated to operate at an ultra-low supply voltage down to 0.2 V, while displaying sufficient voltage gain, high noise margin, and low power consumption. Yttrium oxide is proven to be a competitive gate dielectric for constructing high-performance CNT CMOS FETs and integrated circuits.

  8. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-01-01

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  9. Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

    Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

    2015-07-10

    This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

  10. Iron oxide-mediated semiconductor photocatalysis vs. heterogeneous photo-Fenton treatment of viruses in wastewater. Impact of the oxide particle size.

    Giannakis, Stefanos; Liu, Siting; Carratalà, Anna; Rtimi, Sami; Talebi Amiri, Masoud; Bensimon, Michaël; Pulgarin, César

    2017-10-05

    The photo-Fenton process is recognized as a promising technique towards microorganism disinfection in wastewater, but its efficiency is hampered at near-neutral pH operating values. In this work, we overcome these obstacles by using the heterogeneous photo-Fenton process as the default disinfecting technique, targeting MS2 coliphage in wastewater. The use of low concentrations of iron oxides in wastewater without H 2 O 2 (wüstite, maghemite, magnetite) has demonstrated limited semiconductor-mediated MS2 inactivation. Changing the operational pH and the size of the oxide particles indicated that the isoelectric point of the iron oxides and the active surface area are crucial in the success of the process, and the possible underlying mechanisms are investigated. Furthermore, the addition of low amounts of Fe-oxides (1mgL -1 ) and H 2 O 2 in the system (1, 5 and 10mgL -1 ) greatly enhanced the inactivation process, leading to heterogeneous photo-Fenton processes on the surface of the magnetically separable oxides used. Additionally, photo-dissolution of iron in the bulk, lead to homogeneous photo-Fenton, further aided by the complexation by the dissolved organic matter in the solution. Finally, we assess the impact of the presence of the bacterial host and the difference caused by the different iron sources (salts, oxides) and the Fe-oxide size (normal, nano-sized). Copyright © 2017 Elsevier B.V. All rights reserved.

  11. Design of nanophotonic, hot-electron solar-blind ultraviolet detectors with a metal-oxide-semiconductor structure

    Wang, Zhiyuan; Wang, Xiaoxin; Liu, Jifeng

    2014-01-01

    Solar-blind ultraviolet (UV) detection refers to photon detection specifically in the wavelength range of 200 nm–320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. The most commonly used solid state devices for this application are wide band gap (WBG) semiconductor photodetectors (Eg > 3.5 eV). However, WBG semiconductors are difficult to grow and integrate with Si readout integrated circuits (ROICs). In this paper, we design a nanophotonic metal-oxide-semiconductor structure on Si for solar-blind UV detectors. Instead of using semiconductors as the active absorber, we use Sn nano-grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between the metal and the n-type Si region upon UV excitation. Moreover, the transported hot electron has an excess kinetic energy >3 eV, large enough to induce impact ionization and generate another free electron in the conduction band of n-Si. This process doubles the quantum efficiency. On the other hand, the large metal/oxide interfacial energy barrier (>3.5 eV) also enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, ∼75% UV absorption and hot electron excitation can be achieved within the mean free path of ∼20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. The simple geometry of the Sn nano-gratings and the MOS structure make it easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices. (paper)

  12. Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

    Abe, Y.; Umeda, T.; Okamoto, M.; Kosugi, R.; Harada, S.; Haruyama, M.; Kada, W.; Hanaizumi, O.; Onoda, S.; Ohshima, T.

    2018-01-01

    We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

  13. Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

    Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

    2016-07-18

    The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

  14. Semiconductor Metal Oxide Sensors in Water and Water Based Biological Systems

    Marina V. Strobkova

    2003-10-01

    Full Text Available The results of implementation of In2O3-based semiconductor sensors for oxygen concentration evaluation in water and the LB-nutrient media (15.5 g/l Luria Broth Base, Miller (Sigma, Lot-1900 and NaCl without bacteria and with E.coli bacteria before and after UV-irradiation are presented.

  15. Feigenbaum scenario in the dynamics of a metal-oxide semiconductor heterostructure under harmonic perturbation. Golden mean criticality

    Cristescu, C.P.; Mereu, B.; Stan, Cristina; Agop, M.

    2009-01-01

    Experimental investigations and theoretical analysis on the dynamics of a metal-oxide semiconductor heterostructure used as nonlinear capacity in a series RLC electric circuit are presented. A harmonic voltage perturbation can induce various nonlinear behaviours, particularly evolution to chaos by period doubling and torus destabilization. In this work we focus on the change in dynamics induced by a sinusoidal driving with constant frequency and variable amplitude. Theoretical treatment based on the microscopic mechanisms involved led us to a dynamic system with a piecewise behaviour. Consequently, a model consisting of a nonlinear oscillator described by a piecewise second order ordinary differential equation is proposed. This kind of treatment is required by the asymmetry in the behaviour of the metal-oxide semiconductor with respect to the polarization of the perturbing voltage. The dynamics of the theoretical model is in good agreement with the experimental results. A connection with El Naschie's E-infinity space-time is established based on the interpretation of our experimental results as evidence of the importance of the golden mean criticality in the microscopic world.

  16. A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

    Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

    2011-01-01

    A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38% reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40% of those of the superjunction MOSFET,respectively.

  17. A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

    Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

    2011-01-01

    A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R on,sp ), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R on,sp are investigated, and the optimized results with BV of 83 V and R on,sp of 54 mΩ·mm 2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior 'R on,sp /BV' trade-off to the conventional VDMOS (a 38% reduction of R on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively. (interdisciplinary physics and related areas of science and technology)

  18. Comparative analysis of oxide phase formation and its effects on electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor structures

    Lee, Jaeyel [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Sehun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Kim, Jungsub; Yang, Changjae; Kim, Sujin; Seok, Chulkyun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Jinsub [Department of Electronic Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Yoon, Euijoon, E-mail: eyoon@snu.ac.kr [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Department of Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, Suwon 443-270 (Korea, Republic of); Energy Semiconductor Research Center, Advanced Institutes of Convergence Technology, Seoul National University, Suwon 443-270 (Korea, Republic of)

    2012-06-01

    We report on the changes in the interfacial phases between SiO{sub 2} and InSb caused by various deposition temperatures and heat treatments. X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy were used to evaluate the relative amount of each phase present at the interface. The effect of interfacial phases on the electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor (MOS) structures was investigated by capacitance-voltage (C-V) measurements. The amount of both In and Sb oxides increased with the deposition temperature. The amount of interfacial In oxide was larger for all samples, regardless of the deposition and annealing temperatures and times. In particular, the annealed samples contained less than half the amount of Sb oxide compared with the as-deposited samples, indicating a strong interfacial reaction between Sb oxide and the InSb substrate during annealing. The interface trap density sharply increased for deposition temperatures above 240 Degree-Sign C. The C-V measurements and Raman spectroscopy indicated that elemental Sb accumulation due to the interfacial reaction of Sb oxide with InSb substrate was responsible for the increased interfacial trap densities in these SiO{sub 2}/InSb MOS structures. - Highlights: Black-Right-Pointing-Pointer We report the quantitative analysis of interfacial oxides at the SiO{sub 2}/InSb interface. Black-Right-Pointing-Pointer Interfacial oxides were measured quantitatively by X-ray Photoelectron Spectroscopy. Black-Right-Pointing-Pointer As-grown and annealed samples showed different compositions of oxide phases. Black-Right-Pointing-Pointer Considerable reduction of antimony oxide phases was observed during annealing. Black-Right-Pointing-Pointer Interface trap densities at the SiO{sub 2}/InSb interface were calculated.

  19. Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface

    McKee, Rodney A.; Walker, Frederick J.

    2003-11-25

    A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film consists of a first epitaxial stratum of single atomic plane layers of an alkaline earth oxide designated generally as (AO).sub.n and a second stratum of single unit cell layers of an oxide material designated as (A'BO.sub.3).sub.m so that the multilayer film arranged upon the substrate surface is designated (AO).sub.n (A'BO.sub.3).sub.m wherein n is an integer repeat of single atomic plane layers of the alkaline earth oxide AO and m is an integer repeat of single unit cell layers of the A'BO.sub.3 oxide material. Within the multilayer film, the values of n and m have been selected to provide the structure with a desired electrical structure at the substrate/thin film interface that can be optimized to control band offset and alignment.

  20. Combinatorial Discovery and Optimization of the Composition, Doping and Morphology of New Oxide Semiconductors for Efficient Photoelectrochemical Water Splitting

    Parkinson, Bruce A. [Univ. of Wyoming, Laramie, WY (United States); Jianghua, He [Univ. of Wyoming, Laramie, WY (United States)

    2015-01-06

    The increasing need for carbon free energy has focused renewed attention on solar energy conversion. Although photovoltaic cells excel at directly converting of solar energy to electricity, they do not directly produce stored energy or fuels that account for more than 75% of current energy use. Direct photoelectrolysis of water has the advantage of converting solar energy directly to hydrogen, an ideal non-carbon and nonpolluting energy carrier, by replacing both a photovoltaic array and an electrolysis unit with one potentially inexpensive device. Unfortunately no materials are currently known to efficiently photoelectrolyze water that are, efficient, inexpensive and stable under illumination in electrolytes for many years. Nanostructured semiconducting metal oxides could potentially fulfill these requirements, making them the most promising materials for solar water photoelectrolysis, however no oxide semiconductor has yet been discovered with all the required properties. We have developed a simple, high-throughput combinatorial approach to prepare and screen many multi component metal oxides for water photoelectrolysis activity. The approach uses ink jet printing of overlapping patterns of soluble metal oxide precursors onto conductive glass substrates. Subsequent pyrolysis produces metal oxide phases that are screened for photoelectrolysis activity by measuring photocurrents produced by scanning a laser over the printed patterns in aqueous electrolytes. Several promising and unexpected compositions have been identified.

  1. GaSe:Cd semiconductor - own oxide nanolamellar structures as a selective gas absorber; Structuri nanolamelare semiconductor GaSe:Cd - oxid propriu ca adsorbant selectiv de gaze

    Dmitroglo, Liliana; Evtodiev, Igor; Lazar, Gheorghe [Univ. de Stat din Moldova, Chisinau (Moldova, Republic of); Caraman, Iuliana [Univ. ' Vasile Alecsandri' din Bacau, Bacau (Romania); Dafinei, Adrian [Universitatea din Bucuresti, Bucuresti (Romania)

    2012-07-15

    A lamella with the thickness of 10-300 {mu}m and C6 axis oriented perpendicular to (001) surface were obtained from {epsilon}-GaSe single crystals grown by Bridgman method. By a heat treatment at the temperature of 450-580 degrees Celsius the lamella surfaces were coated with the own nanostructured (Ga{sub 2}O{sub 3}) oxide. The absorption of polar molecules from the (H{sub 2}O, CO, CON) atmosphere was studied by using absorptional IR spectroscopy. These molecules absorption bands and optical transparency dependence on the absorbed molecules concentration were determined. (authors)

  2. A 65 nm CMOS high efficiency 50 GHz VCO with regard to the coupling effect of inductors

    Ye Yu; Tian Tong

    2013-01-01

    A 50 GHz cross-coupled voltage controlled oscillator (VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor (CMOS) technology is reported. A pair of inductors has been fabricated, measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO's LC tank. By optimizing the tank voltage swing and the buffer's operation region, the VCO achieves a maximum efficiency of 11.4% by generating an average output power of 2.5 dBm while only consuming 19.7 mW (including buffers). The VCO exhibits a phase noise of −87 dBc/Hz at 1 MHz offset, leading to a figure of merit (FoM) of −167.5 dB/Hz and a tuning range of 3.8% (from 48.98 to 50.88 GHz). (semiconductor integrated circuits)

  3. Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material

    McKee, Rodney Allen; Walker, Frederick Joseph

    2000-01-01

    A crystalline structure and a semiconductor device includes a substrate of a semiconductor-based material and a thin film of an anisotropic crystalline material epitaxially arranged upon the surface of the substrate so that the thin film couples to the underlying substrate and so that the geometries of substantially all of the unit cells of the thin film are arranged in a predisposed orientation relative to the substrate surface. The predisposition of the geometries of the unit cells of the thin film is responsible for a predisposed orientation of a directional-dependent quality, such as the dipole moment, of the unit cells. The predisposed orientation of the unit cell geometries are influenced by either a stressed or strained condition of the lattice at the interface between the thin film material and the substrate surface.

  4. Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

    Wang, C.-C.; Chiou, Y.-K.; Chang, C.-H.; Tseng, J.-Y.; Wu, L.-J.; Chen, C.-Y.; Wu, T.-B.

    2007-01-01

    The nonvolatile memory characteristics of metal-oxide-semiconductor (MOS) structures containing Au nanocrystals in the Al 2 O 3 /SiO 2 matrix were studied. In this work, we have demonstrated that the use of Al 2 O 3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance-voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current-voltage relation of the MOS capacitors

  5. Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

    Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

    2018-01-01

    The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

  6. Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

    Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

    2006-01-01

    Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

  7. Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

    Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

    2018-01-01

    We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

  8. Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

    Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica; Tisa, Simone; Zappa, Franco [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo da Vinci 32, I-20133 Milano (Italy)

    2013-12-15

    We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

  9. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-01-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd_2O_2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  10. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

    2016-09-21

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  11. Influence of quantizing magnetic field and Rashba effect on indium arsenide metal-oxide-semiconductor structure accumulation capacitance

    Kovchavtsev, A. P.; Aksenov, M. S.; Tsarenko, A. V.; Nastovjak, A. E.; Pogosov, A. G.; Pokhabov, D. A.; Tereshchenko, O. E.; Valisheva, N. A.

    2018-05-01

    The accumulation capacitance oscillations behavior in the n-InAs metal-oxide-semiconductor structures with different densities of the built-in charge (Dbc) and the interface traps (Dit) at temperature 4.2 K in the magnetic field (B) 2-10 T, directed perpendicular to the semiconductor-dielectric interface, is studied. A decrease in the oscillation frequency and an increase in the capacitance oscillation amplitude are observed with the increase in B. At the same time, for a certain surface accumulation band bending, the influence of the Rashba effect, which is expressed in the oscillations decay and breakdown, is traced. The experimental capacitance-voltage curves are in a good agreement with the numeric simulation results of the self-consistent solution of Schrödinger and Poisson equations in the magnetic field, taking into account the quantization, nonparabolicity of dispersion law, and Fermi-Dirac electron statistics, with the allowance for the Rashba effect. The Landau quantum level broadening in a two-dimensional electron gas (Lorentzian-shaped density of states), due to the electron scattering mechanism, linearly depends on the magnetic field. The correlation between the interface electronic properties and the characteristic scattering times was established.

  12. Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

    Konrad Maier

    2015-09-01

    Full Text Available In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high.

  13. Beyond CMOS nanodevices 2

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  14. Beyond CMOS nanodevices 1

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  15. Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

    Hussain, Aftab M.

    2014-12-14

    We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well as experimentally by fabricating MOSFETs. Our study suggests that the alloy offers interesting possibilities in the realm of silicon band gap tuning. We have explored diffusion of tin (Sn) into the industry\\'s most widely used substrate, silicon (100), as it is the most cost effective, scalable and CMOS compatible way of obtaining SiSn. Our theoretical model predicts a higher mobility for p-channel SiSn MOSFETs, due to a lower effective mass of the holes, which has been experimentally validated using the fabricated MOSFETs. We report an increase of 13.6% in the average field effect hole mobility for SiSn devices compared to silicon control devices.

  16. Characterization study of an intensified complementary metal-oxide-semiconductor active pixel sensor

    Griffiths, J. A.; Chen, D.; Turchetta, R.; Royle, G. J.

    2011-03-01

    An intensified CMOS active pixel sensor (APS) has been constructed for operation in low-light-level applications: a high-gain, fast-light decay image intensifier has been coupled via a fiber optic stud to a prototype "VANILLA" APS, developed by the UK based MI3 consortium. The sensor is capable of high frame rates and sparse readout. This paper presents a study of the performance parameters of the intensified VANILLA APS system over a range of image intensifier gain levels when uniformly illuminated with 520 nm green light. Mean-variance analysis shows the APS saturating around 3050 Digital Units (DU), with the maximum variance increasing with increasing image intensifier gain. The system's quantum efficiency varies in an exponential manner from 260 at an intensifier gain of 7.45 × 103 to 1.6 at a gain of 3.93 × 101. The usable dynamic range of the system is 60 dB for intensifier gains below 1.8 × 103, dropping to around 40 dB at high gains. The conclusion is that the system shows suitability for the desired application.

  17. Defect-driven interfacial electronic structures at an organic/metal-oxide semiconductor heterojunction.

    Winget, Paul; Schirra, Laura K; Cornil, David; Li, Hong; Coropceanu, Veaceslav; Ndione, Paul F; Sigdel, Ajaya K; Ginley, David S; Berry, Joseph J; Shim, Jaewon; Kim, Hyungchui; Kippelen, Bernard; Brédas, Jean-Luc; Monti, Oliver L A

    2014-07-16

    The electronic structure of the hybrid interface between ZnO and the prototypical organic semiconductor PTCDI is investigated via a combination of ultraviolet and X-ray photoelectron spectroscopy (UPS/XPS) and density functional theory (DFT) calculations. The interfacial electronic interactions lead to a large interface dipole due to substantial charge transfer from ZnO to 3,4,9,10-perylenetetracarboxylicdiimide (PTCDI), which can be properly described only when accounting for surface defects that confer ZnO its n-type properties. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  18. Ultraviolet-visible electroluminescence from metal-oxide-semiconductor devices with CeO2 films on silicon

    Lv, Chunyan; Zhu, Chen; Wang, Canxing; Li, Dongsheng; Ma, Xiangyang; Yang, Deren

    2015-01-01

    We report on ultraviolet-visible (UV-Vis) electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with the CeO 2 films annealed at low temperatures. At the same injection current, the UV-Vis EL from the MOS device with the 550 °C-annealed CeO 2 film is much stronger than that from the counterpart with the 450 °C-annealed CeO 2 film. This is due to that the 550 °C-annealed CeO 2 film contains more Ce 3+ ions and oxygen vacancies. It is tentatively proposed that the recombination of the electrons in multiple oxygen-vacancy–related energy levels with the holes in Ce 4f 1 energy band pertaining to Ce 3+ ions leads to the UV-Vis EL

  19. Charge-flow structures as polymeric early-warning fire alarm devices. M.S. Thesis; [metal oxide semiconductors

    Sechen, C. M.; Senturia, S. D.

    1977-01-01

    The charge-flow transistor (CFT) and its applications for fire detection and gas sensing were investigated. The utility of various thin film polymers as possible sensing materials was determined. One polymer, PAPA, showed promise as a relative humidity sensor; two others, PFI and PSB, were found to be particularly suitable for fire detection. The behavior of the charge-flow capacitor, which is basically a parallel-plate capacitor with a polymer-filled gap in the metallic tip electrode, was successfully modeled as an RC transmission line. Prototype charge-flow transistors were fabricated and tested. The effective threshold voltage of this metal oxide semiconductor was found to be dependent on whether surface or bulk conduction in the thin film was dominant. Fire tests with a PFI-coated CFT indicate good sensitivity to smouldering fires.

  20. Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

    Spathis, C.; Birbas, A.; Georgakopoulou, K.

    2015-01-01

    Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices

  1. Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

    Spathis, C., E-mail: cspathis@ece.upatras.gr; Birbas, A.; Georgakopoulou, K. [Department of Electrical and Computer Engineering, University of Patras, Patras 26500 (Greece)

    2015-08-15

    Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

  2. Indium tin oxide films prepared by atmospheric plasma annealing and their semiconductor-metal conductivity transition around room temperature

    Li Yali; Li Chunyang; He Deyan; Li Junshuai

    2009-01-01

    We report the synthesis of indium tin oxide (ITO) films using the atmospheric plasma annealing (APA) technique combined with the spin-coating method. The ITO film with a low resistivity of ∼4.6 x 10 -4 Ω cm and a high visible light transmittance, above 85%, was achieved. Hall measurement indicates that compared with the optimized ITO films deposited by magnetron sputtering, the above-mentioned ITO film has a higher carrier concentration of ∼1.21 x 10 21 cm -3 and a lower mobility of ∼11.4 cm 2 V -1 s -1 . More interestingly, these electrical characteristics result in the semiconductor-metal conductivity transition around room temperature for the ITO films prepared by APA.

  3. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  4. Plasma-assisted atomic layer deposition of TiN/Al2O3 stacks for metal-oxide-semiconductor capacitor applications

    Hoogeland, D.; Jinesh, K.B.; Roozeboom, F.; Besling, W.F.A.; Sanden, van de M.C.M.; Kessels, W.M.M.

    2009-01-01

    By employing plasma-assisted atomic layer deposition, thin films of Al2O3 and TiN are subsequently deposited in a single reactor at a single substrate temperature with the objective of fabricating high-quality TiN/Al2O3 / p-Si metal-oxide-semiconductor capacitors. Transmission electron microscopy

  5. Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field-effect transistor (MOSFET) dosemeters: a comparative study

    Koivisto, J.; Schulze, D.; Wolff, J.E.H.; Rottke, D.

    2014-01-01

    Objectives: The objective of this study was to compare the performance of metal oxide semiconductor field-effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. Methods: Organ and effective

  6. Controlling the interface charge density in GaN-based metal-oxide-semiconductor heterostructures by plasma oxidation of metal layers

    Hahn, Herwig; Kalisch, Holger; Vescan, Andrei; Pécz, Béla; Kovács, András; Heuken, Michael

    2015-01-01

    In recent years, investigating and engineering the oxide-semiconductor interface in GaN-based devices has come into focus. This has been driven by a large effort to increase the gate robustness and to obtain enhancement mode transistors. Since it has been shown that deep interface states act as fixed interface charge in the typical transistor operating regime, it appears desirable to intentionally incorporate negative interface charge, and thus, to allow for a positive shift in threshold voltage of transistors to realise enhancement mode behaviour. A rather new approach to obtain such negative charge is the plasma-oxidation of thin metal layers. In this study, we present transmission electron microscopy and energy dispersive X-ray spectroscopy analysis as well as electrical data for Al-, Ti-, and Zr-based thin oxide films on a GaN-based heterostructure. It is shown that the plasma-oxidised layers have a polycrystalline morphology. An interfacial amorphous oxide layer is only detectable in the case of Zr. In addition, all films exhibit net negative charge with varying densities. The Zr layer is providing a negative interface charge density of more than 1 × 10 13  cm –2 allowing to considerably shift the threshold voltage to more positive values

  7. Structural, optical and electrical properties of tin oxide thin films for application as a wide band gap semiconductor

    Sethi, Riti; Ahmad, Shabir; Aziz, Anver; Siddiqui, Azher Majid, E-mail: amsiddiqui@jmi.ac.in [Department of Physics, Jamia Millia Islamia, New Delhi-110025 (India)

    2015-08-28

    Tin oxide (SnO) thin films were synthesized using thermal evaporation technique. Ultra pure metallic tin was deposited on glass substrates using thermal evaporator under high vacuum. The thickness of the tin deposited films was kept at 100nm. Subsequently, the as-deposited tin films were annealed under oxygen environment for a period of 3hrs to obtain tin oxide films. To analyse the suitability of the synthesized tin oxide films as a wide band gap semiconductor, various properties were studied. Structural parameters were studied using XRD and SEM-EDX. The optical properties were studied using UV-Vis Spectrophotometry and the electrical parameters were calculated using the Hall-setup. XRD and SEM confirmed the formation of SnO phase. Uniform texture of the film can be seen through the SEM images. Presence of traces of unoxidised Sn has also been confirmed through the XRD spectra. The band gap calculated was around 3.6eV and the optical transparency around 50%. The higher value of band gap and lower value of optical transparency can be attributed to the presence of unoxidised Sn. The values of resistivity and mobility as measured by the Hall setup were 78Ωcm and 2.92cm{sup 2}/Vs respectively. The reasonable optical and electrical parameters make SnO a suitable candidate for optoelectronic and electronic device applications.

  8. In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

    Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

    2018-04-01

    The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

  9. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  10. Cytotoxicity of semiconductor nanoparticles in A549 cells is attributable to their intrinsic oxidant activity

    Escamilla-Rivera, Vicente; Uribe-Ramirez, Marisela [Centro de Investigación y de Estudios Avanzados del IPN (CINVESTAV-IPN), Departamento de Toxicología (Mexico); Gonzalez-Pozos, Sirenia [CINVESTAV-IPN, Unidad de Microscopia Electrónica (LaNSE) (Mexico); Velumani, Subramaniam [CINVESTAV-IPN, Departamento de Ingeniería Eléctrica (Mexico); Arreola-Mendoza, Laura [Centro Interdisciplinario de Investigaciones y Estudios sobre Medio Ambiente y Desarrollo del Instituto Politécnico Nacional (CIIEMAD-IPN), Departamento de Biociencias e Ingeniería (Mexico); Vizcaya-Ruiz, Andrea De, E-mail: avizcaya@cinvestav.mx [Centro de Investigación y de Estudios Avanzados del IPN (CINVESTAV-IPN), Departamento de Toxicología (Mexico)

    2016-04-15

    Copper indium gallium diselenide (CIGS) and cadmium sulfide (CdS) nanoparticles (NP) are next generation semiconductors used in photovoltaic cells (PV). They possess high quantum efficiency, absorption coefficient, and cheaper manufacturing costs compared to silicon. Due to their potential for an industrial development and the lack of information about the risk associated in their use, we investigated the influence of the physicochemical characteristics of CIGS (9 nm) and CdS (20 nm) in relation to the induction of cytotoxicity in human alveolar A549 cells through ROS generation and mitochondrial dysfunction. CIGS induced cytotoxicity in a dose dependent manner in lower concentrations than CdS; both NP were able to induce ROS in A549. Moreover, CIGS interact directly with mitochondria inducing depolarization that leads to the induction of apoptosis compared to CdS. Antioxidant pretreatment significantly prevented the loss of mitochondrial membrane potential and cytotoxicity, suggesting ROS generation as the main cytotoxic mechanism. These results demonstrate that semiconductor characteristics of NP are crucial for the type and intensity of the cytotoxic effects. Our work provides relevant information that may help guide the production of a safer NP-based PV technologies, and would be a valuable resource on future risk assessment for a safer use of nanotechnology in the development of clean sources of renewable energy.

  11. Accuracy of dielectric-dependent hybrid functionals in the prediction of optoelectronic properties of metal oxide semiconductors: a comprehensive comparison with many-body GW and experiments

    Gerosa, M.; E Bottani, C.; Di Valentin, C.; Onida, G.; Pacchioni, G.

    2018-01-01

    Understanding the electronic structure of metal oxide semiconductors is crucial to their numerous technological applications, such as photoelectrochemical water splitting and solar cells. The needed experimental and theoretical knowledge goes beyond that of pristine bulk crystals, and must include the effects of surfaces and interfaces, as well as those due to the presence of intrinsic defects (e.g. oxygen vacancies), or dopants for band engineering. In this review, we present an account of the recent efforts in predicting and understanding the optoelectronic properties of oxides using ab initio theoretical methods. In particular, we discuss the performance of recently developed dielectric-dependent hybrid functionals, providing a comparison against the results of many-body GW calculations, including G 0 W 0 as well as more refined approaches, such as quasiparticle self-consistent GW. We summarize results in the recent literature for the band gap, the band level alignment at surfaces, and optical transition energies in defective oxides, including wide gap oxide semiconductors and transition metal oxides. Correlated transition metal oxides are also discussed. For each method, we describe successes and drawbacks, emphasizing the challenges faced by the development of improved theoretical approaches. The theoretical section is preceded by a critical overview of the main experimental techniques needed to characterize the optoelectronic properties of semiconductors, including absorption and reflection spectroscopy, photoemission, and scanning tunneling spectroscopy (STS).

  12. Single Event Effects (SEE) for Power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)

    Lauenstein, Jean-Marie

    2011-01-01

    Single-event gate rupture (SEGR) continues to be a key failure mode in power MOSFETs. (1) SEGR is complex, making rate prediction difficult SEGR mechanism has two main components: (1) Oxide damage-- Reduces field required for rupture (2) Epilayer response -- Creates transient high field across the oxide.

  13. CMOS-compatible photonic devices for single-photon generation

    Xiong Chunle

    2016-09-01

    Full Text Available Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal–oxide–semiconductor (CMOS-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

  14. UV lithography-based protein patterning on silicon: Towards the integration of bioactive surfaces and CMOS electronics

    Lenci, S., E-mail: silvia.lenci@iet.unipi.it [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Tedeschi, L. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy); Pieri, F. [Dipartimento di Ingegneria dell' Informazione, via G.Caruso 16, Pisa I-56122 (Italy); Domenici, C. [Istituto di Fisiologia Clinica - CNR, via G. Moruzzi 1, Pisa I-56124 (Italy)

    2011-08-01

    A simple and fast methodology for protein patterning on silicon substrates is presented, providing an insight into possible issues related to the interaction between biological and microelectronic technologies. The method makes use of standard photoresist lithography and is oriented towards the implementation of biosensors containing Complementary Metal-Oxide-Semiconductor (CMOS) conditioning circuitry. Silicon surfaces with photoresist patterns were prepared and hydroxylated by means of resist- and CMOS backend-compatible solutions. Subsequent aminosilane deposition and resist lift-off in organic solvents resulted into well-controlled amino-terminated geometries. The discussion is focused on resist- and CMOS-compatibility problems related to the used chemicals. Some samples underwent gold nanoparticle (Au NP) labeling and Scanning Electron Microscopy (SEM) observation, in order to investigate the quality of the silane layer. Antibodies were immobilized on other samples, which were subsequently exposed to a fluorescently labeled antigen. Fluorescence microscopy observation showed that this method provides spatially selective immobilization of protein layers onto APTES-patterned silicon samples, while preserving protein reactivity inside the desired areas and low non-specific adsorption elsewhere. Strong covalent biomolecule binding was achieved, giving stable protein layers, which allows stringent binding conditions and a good binding specificity, really useful for biosensing.

  15. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  16. A novel CMOS image sensor system for quantitative loop-mediated isothermal amplification assays to detect food-borne pathogens.

    Wang, Tiantian; Kim, Sanghyo; An, Jeong Ho

    2017-02-01

    Loop-mediated isothermal amplification (LAMP) is considered as one of the alternatives to the conventional PCR and it is an inexpensive portable diagnostic system with minimal power consumption. The present work describes the application of LAMP in real-time photon detection and quantitative analysis of nucleic acids integrated with a disposable complementary-metal-oxide semiconductor (CMOS) image sensor. This novel system works as an amplification-coupled detection platform, relying on a CMOS image sensor, with the aid of a computerized circuitry controller for the temperature and light sources. The CMOS image sensor captures the light which is passing through the sensor surface and converts into digital units using an analog-to-digital converter (ADC). This new system monitors the real-time photon variation, caused by the color changes during amplification. Escherichia coli O157 was used as a proof-of-concept target for quantitative analysis, and compared with the results for Staphylococcus aureus and Salmonella enterica to confirm the efficiency of the system. The system detected various DNA concentrations of E. coli O157 in a short time (45min), with a detection limit of 10fg/μL. The low-cost, simple, and compact design, with low power consumption, represents a significant advance in the development of a portable, sensitive, user-friendly, real-time, and quantitative analytic tools for point-of-care diagnosis. Copyright © 2016 Elsevier B.V. All rights reserved.

  17. 3-Axis Fully-Integrated Capacitive Tactile Sensor with Flip-Bonded CMOS on LTCC Interposer †

    Asano, Sho; Nakayama, Takahiro; Hata, Yoshiyuki; Tanaka, Shuji

    2017-01-01

    This paper reports a 3-axis fully integrated differential capacitive tactile sensor surface-mountable on a bus line. The sensor integrates a flip-bonded complementary metal-oxide semiconductor (CMOS) with capacitive sensing circuits on a low temperature cofired ceramic (LTCC) interposer with Au through vias by Au-Au thermo-compression bonding. The CMOS circuit and bonding pads on the sensor backside were electrically connected through Au bumps and the LTCC interposer, and the differential capacitive gap was formed by an Au sealing frame. A diaphragm for sensing 3-axis force was formed in the CMOS substrate. The dimensions of the completed sensor are 2.5 mm in width, 2.5 mm in length, and 0.66 mm in thickness. The fabricated sensor output coded 3-axis capacitive sensing data according to applied 3-axis force by three-dimensional (3D)-printed pins. The measured sensitivity was as high as over 34 Count/mN for normal force and 14 to 15 Count/mN for shear force with small noise, which corresponds to less than 1 mN. The hysteresis and the average cross-sensitivity were also found to be less than 2% full scale and 11%, respectively. PMID:29068429

  18. Solar light assisted photocatalysis of water using a zinc oxide semiconductor

    Shinde, S. S.; Bhosale, C. H.; Rajpure, K. Y.

    2013-01-01

    The photocatalytic decomposition of an eco-persistent AO7 dye with sunlight in an oxygenated aqueous suspension has been studied under a nano-crystalline hexagonal ZnO photocatalyst. The effect of substrate temperature on the structural, morphological and photoactive properties has been investigated. The degradation of the AO7 dye is achieved using a photoelectrochemical reactor module equipped with ZnO synthesized electrodes. Kinetic parameters have been investigated in terms of a first order rate equation. The rate constant for this heterogeneous photocatalysis was evaluated as a function of the initial concentration of original species. A substantial reduction in AO7 dye is achieved as analyzed from COD and TOC studies. The mechanism for the degradation could be explained on the basis of the Langmuir-Hinshelwood mechanism. (semiconductor materials)

  19. Atomic origin of high-temperature electron trapping in metal-oxide-semiconductor devices

    Shen, Xiao, E-mail: xiao.shen@vanderbilt.edu [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States); Pantelides, Sokrates T. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Department of Electrical Engineering and Computer Science, Vanderbilt University, Nashville, Tennessee 37235 (United States); Materials Science and Technology Division, Oak Ridge National Laboratory, Oak Ridge, Tennessee 37831 (United States)

    2015-04-06

    MOSFETs based on wide-band-gap semiconductors are suitable for operation at high temperature, at which additional atomic-scale processes that are benign at lower temperatures can get activated, resulting in device degradation. Recently, significant enhancement of electron trapping was observed under positive bias in SiC MOSFETs at temperatures higher than 150 °C. Here, we report first-principles calculations showing that the enhanced electron trapping is associated with thermally activated capturing of a second electron by an oxygen vacancy in SiO{sub 2} by which the vacancy transforms into a structure that comprises one Si dangling bond and a bond between a five-fold and a four-fold Si atoms. The results suggest a key role of oxygen vacancies and their structural reconfigurations in the reliability of high-temperature MOS devices.

  20. Issues in first-principles calculations for defects in semiconductors and oxides

    Nieminen, Risto M

    2009-01-01

    Recent advances in density-functional theory (DFT) calculations of defect electronic properties in semiconductors and insulators are discussed. In particular, two issues are addressed: the band-gap underestimation of standard density-functional methods with its harmful consequences for the positioning of defect-related levels in the band-gap region, and the slow convergence of calculated defect properties when the periodic supercell approach is used. Systematic remedies for both of these deficiencies are now available, and are being implemented in the context of popular DFT codes. This should help in improving the parameter-free accuracy and thus the predictive power of the methods to enable unambiguous explanation of defect-related experimental observations. These include not only the various fingerprint spectroscopies for defects but also their thermochemistry and dynamics, i.e. the temperature-dependent concentration and diffusivities of defects under various doping conditions and in different stoichiometries

  1. Multiple-valued logic design based on the multiple-peak BiCMOS-NDR circuits

    Kwang-Jow Gan

    2016-06-01

    Full Text Available Three different multiple-valued logic (MVL designs using the multiple-peak negative-differential-resistance (NDR circuits are investigated. The basic NDR element, which is made of several Si-based metal-oxide-semiconductor field-effect-transistor (MOS and SiGe-based heterojunction-bipolar-transistor (HBT devices, can be implemented by using a standard BiCMOS process. These MVL circuits are designed based on the triggering-pulse control, saw-tooth input signal, and peak-control methods, respectively. However, there are some transient states existing between the multiple stable levels for the first two methods. These states might affect the circuit function in practical application. As a result, our proposed peak-control method for the MVL design can be used to overcome these transient states.

  2. CMOS-compatible batch processing of monolayer MoS2 MOSFETs

    Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

    2018-04-01

    Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

  3. A Monolithic CMOS Magnetic Hall Sensor with High Sensitivity and Linearity Characteristics.

    Huang, Haiyun; Wang, Dejun; Xu, Yue

    2015-10-27

    This paper presents a fully integrated linear Hall sensor by means of 0.8 μm high voltage complementary metal-oxide semiconductor (CMOS) technology. This monolithic Hall sensor chip features a highly sensitive horizontal switched Hall plate and an efficient signal conditioner using dynamic offset cancellation technique. An improved cross-like Hall plate achieves high magnetic sensitivity and low offset. A new spinning current modulator stabilizes the quiescent output voltage and improves the reliability of the signal conditioner. The tested results show that at the 5 V supply voltage, the maximum Hall output voltage of the monolithic Hall sensor microsystem, is up to ±2.1 V and the linearity of Hall output voltage is higher than 99% in the magnetic flux density range from ±5 mT to ±175 mT. The output equivalent residual offset is 0.48 mT and the static power consumption is 20 mW.

  4. Study of non-stoichiometric BaSrTiFeO3 oxide dedicated to semiconductor gas sensors

    Fasquelle, D.; Verbrugghe, N.; Deputier, S.

    2016-01-01

    Developing instrumentation systems compatible with the European RoHS directive (restriction of hazardous substances) to monitor our environment is of great interest for our society. Our research therefore aims at developing innovating integrated systems of detection dedicated to the characterization of various environmental exposures. These systems, which integrate new gas sensors containing lead-free oxides, are dedicated to the detection of flammable and toxic gases. We have firstly chosen to study semiconductor gas sensors implemented with lead-free oxides in view to develop RoHS devices. Therefore thick films deposited by spin-coating and screen-printing have been chosen for their robustness, ease to realize and ease to finally obtain cost-effective sensors. As crystalline defects and ionic vacancies are of great interest for gas detection, we have decided to study a non-stoichiometric composition of the BaSrTiFeO 3 sensible oxide. Nonstoichiometric BaSrTiFeO 3 lead-free oxide thick films were deposited by screen-printing on polycrystalline AFO 3 substrates covered by a layer of Ag-Pd acting as bottom electrode. The physical characterizations have revealed a crystalline structure mainly composed of BaTiO 3 pseudo-cubic phase and Ba 4 Ti 12 O 27 monoclinic phase for the powder, and a porous microstructure for the thick films. When compared to a BSTF thick film with a stoichiometric composition, a notable increase in the BSTF dielectric constant value was observed when taking into account of a similar microstructure and grain size. The loss tangent mean value varies more softly for the non-stoichiometric BaSrTiFeO 3 films than for the perovskite BSTF film as tanδ decreases from 0.45 to 0.04 when the frequency increases from 100 Hz to 1 MHz. (paper)

  5. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-01-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  6. p-Type Transparent Conducting Oxide/n-Type Semiconductor Heterojunctions for Efficient and Stable Solar Water Oxidation.

    Chen, Le; Yang, Jinhui; Klaus, Shannon; Lee, Lyman J; Woods-Robinson, Rachel; Ma, Jie; Lum, Yanwei; Cooper, Jason K; Toma, Francesca M; Wang, Lin-Wang; Sharp, Ian D; Bell, Alexis T; Ager, Joel W

    2015-08-05

    Achieving stable operation of photoanodes used as components of solar water splitting devices is critical to realizing the promise of this renewable energy technology. It is shown that p-type transparent conducting oxides (p-TCOs) can function both as a selective hole contact and corrosion protection layer for photoanodes used in light-driven water oxidation. Using NiCo2O4 as the p-TCO and n-type Si as a prototypical light absorber, a rectifying heterojunction capable of light driven water oxidation was created. By placing the charge separating junction in the Si using a np(+) structure and by incorporating a highly active heterogeneous Ni-Fe oxygen evolution catalyst, efficient light-driven water oxidation can be achieved. In this structure, oxygen evolution under AM1.5G illumination occurs at 0.95 V vs RHE, and the current density at the reversible potential for water oxidation (1.23 V vs RHE) is >25 mA cm(-2). Stable operation was confirmed by observing a constant current density over 72 h and by sensitive measurements of corrosion products in the electrolyte. In situ Raman spectroscopy was employed to investigate structural transformation of NiCo2O4 during electrochemical oxidation. The interface between the light absorber and p-TCO is crucial to produce selective hole conduction to the surface under illumination. For example, annealing to produce more crystalline NiCo2O4 produces only small changes in its hole conductivity, while a thicker SiOx layer is formed at the n-Si/p-NiCo2O4 interface, greatly reducing the PEC performance. The generality of the p-TCO protection approach is demonstrated by multihour, stable, water oxidation with n-InP/p-NiCo2O4 heterojunction photoanodes.

  7. Single InAs/GaSb nanowire low-power CMOS inverter.

    Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

    2012-11-14

    III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

  8. Nanomorphology Effects in Semiconductors with Native Ferromagnetism: Hierarchical Europium (II) Oxide Tubes Prepared via a Topotactic Nanostructure Transition.

    Trepka, Bastian; Erler, Philipp; Selzer, Severin; Kollek, Tom; Boldt, Klaus; Fonin, Mikhail; Nowak, Ulrich; Wolf, Daniel; Lubk, Axel; Polarz, Sebastian

    2018-01-01

    Semiconductors with native ferromagnetism barely exist and defined nanostructures are almost unknown. This lack impedes the exploration of a new class of materials characterized by a direct combination of effects on the electronic system caused by quantum confinement effects with magnetism. A good example is EuO for which currently no reliable routes for nanoparticle synthesis can be established. Bottom-up approaches applicable to other oxides fail because of the labile oxidation state +II. Instead of targeting a direct synthesis, the two steps-"structure control" and "chemical transformation"-are separated. The generation of a transitional, hybrid nanophase is followed by its conversion into EuO under full conservation of all morphological features. Hierarchical EuO materials are now accessible in the shape of oriented nanodisks stacked to tubular particles. Magnetically, the coupling of either vortex or onion states has been found. An unexpected temperature dependence is governed by thermally activated transitions between these states. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. Investigation of structural and electrical properties on substrate material for high frequency metal-oxide-semiconductor (MOS) devices

    Kumar, M.; Yang, Sung-Hyun; Janardhan Reddy, K.; JagadeeshChandra, S. V.

    2017-04-01

    Hafnium oxide (HfO2) thin films were grown on cleaned P-type Ge and Si substrates by using atomic layer deposition technique (ALD) with thickness of 8 nm. The composition analysis of as-deposited and annealed HfO2 films was characterized by XPS, further electrical measurements; we fabricated the metal-oxide-semiconductor (MOS) devices with Pt electrode. Post deposition annealing in O2 ambient at 500 °C for 30 min was carried out on both Ge and Si devices. Capacitance-voltage (C-V) and conductance-voltage (G-V) curves measured at 1 MHz. The Ge MOS devices showed improved interfacial and electrical properties, high dielectric constant (~19), smaller EOT value (0.7 nm), and smaller D it value as Si MOS devices. The C-V curves shown significantly high accumulation capacitance values from Ge devices, relatively when compare with the Si MOS devices before and after annealing. It could be due to the presence of very thin interfacial layer at HfO2/Ge stacks than HfO2/Si stacks conformed by the HRTEM images. Besides, from current-voltage (I-V) curves of the Ge devices exhibited similar leakage current as Si devices. Therefore, Ge might be a reliable substrate material for structural, electrical and high frequency applications.

  10. Unified model of damage annealing in CMOS, from freeze-in to transient annealing

    Sander, H.H.; Gregory, B.L.

    Results of an experimental study at 76 0 K, are presented showing that radiation-produced holes in SiO 2 are immobile at this temperature. If an electric field is present in the SiO 2 during low temperature (76 0 K) irradiation to sweep out the mobile electrons, the holes will virtually all be trapped where created and produce a uniform positive charge density in the oxide. These results are the basis for concluding that if a complimentary p,n metal-oxide semiconductor (CMOS) device is irradiated for sufficient time at 76 0 K to build-in an appreciable field, further irradiation with gate bias removed will produce very little additional change in V/sub th/, since the field in the oxide tends to keep all generated electrons in the oxide where they recombine with trapped holes. Hence the hole trapping rate = the hole annihilation rate. The room-temperature annealing following a pulsed gamma exposure occurs in two regimes. The first recovery of V/sub th/ occurs prior to 10 -4 seconds. The magnitude of this very early-time recovery, at room temperature, is oxide-dependent, and oxide process dependent. The rate-of-annealing is what is truly different between a rad-hard and a rad-soft device, since annealing in the hardest devices occurs very quickly at room temperature. (U.S.)

  11. Study of Si/Si, Si/SiO2, and metal-oxide-semiconductor (MOS) using positrons

    Leung, To Chi.

    1991-01-01

    A variable-energy positron beam is used to study Si/Si, Si/SiO 2 , and metal-oxide-semiconductor (MOS) structures. The capability of depth resolution and the remarkable sensitivity to defects have made the positron annihilation technique a unique tool in detecting open-volume defects in the newly innovated low temperature (300C) molecular-beam-epitaxy (MBE) Si/Si. These two features of the positron beam have further shown its potential role in the study of the Si/SiO 2 . Distinct annihilation characteristics has been observed at the interface and has been studied as a function of the sample growth conditions, annealing (in vacuum), and hydrogen exposure. The MOS structure provides an effective way to study the electrical properties of the Si/SiO 2 interface as a function of applied bias voltage. The annihilation characteristics show a large change as the device condition is changed from accumulation to inversion. The effect of forming gas (FG) anneal is studied using positron annihilation and the result is compared with capacitance-voltage (C-V) measurements. The reduction in the number of interface states is found correlated with the changes in the positron spectra. The present study shows the importance of the positron annihilation technique as a non-contact, non-destructive, and depth-sensitive characterization tool to study the Si-related systems, in particular, the Si/SiO 2 interface which is of crucial importance in semiconductor technology, and fundamental understanding of the defects responsible for degradation of the electrical properties

  12. Theoretical aspects of studies of oxide and semiconductor surfaces using low energy positrons

    Fazleev, N. G.; Maddox, W. B.; Weiss, A. H.

    2011-01-01

    This paper presents the results of a theoretical study of positron surface and bulk states and annihilation characteristics of surface trapped positrons at the oxidized Cu(100) single crystal and at both As- and Ga-rich reconstructed GaAs(100) surfaces. The variations in atomic structure and chemical composition of the topmost layers of the surfaces associated with oxidation and reconstructions and the charge redistribution at the surfaces are found to affect localization and spatial extent of the positron surface-state wave functions. The computed positron binding energy, work function, and annihilation characteristics reveal their sensitivity to charge transfer effects, atomic structure and chemical composition of the topmost layers of the surfaces. Theoretical positron annihilation probabilities with relevant core electrons computed for the oxidized Cu(100) surface and the As- and Ga-rich reconstructed GaAs(100) surfaces are compared with experimental ones estimated from the positron annihilation induced Auger peak intensities measured from these surfaces.

  13. Key Topics in Producing New Ultraviolet Led and Laser Devices Based on Transparent Semiconductor Zinc Oxide

    Tuezemen, S.

    2004-01-01

    Recently, it has been introduced that ZnO as II-VI semiconductor is promising various technological applications, especially for optoelectronic short wavelength light emitting devices due to its wide and direct band gap profile. The most important advantage of ZnO over the other currently used wide band gap semiconductors such as GaN is that its nearly 3 times higher exciton binding energy (60 meV), which permits efficient excitonic emission at room temperature and above. As-grown ZnO is normally n-type because of the Zn-rich defects such as zinc interstitials (Zn i ) oxygen vacancies (Vo), natively acting as shallow donors and main source of n-type conductivity in as-grown material. Therefore, making p-type ZnO has been more difficult due to unintentional compensation of possible acceptors by these residual donors. In order to develop electro luminescent and laser devices based on the ultraviolet (UV) exciton emission of ZnO, it will be important to fabricate good p-n junctions. Attempts to observe p-type conductivity in ours and our collaborators' laboratories in USA, either by co-doping with N or tuning O pressure have been first successful achievements, resulting in hole concentrations up to 10 1 9 cm - 3 in reactively sputtered thin layers of ZnO. Moreover, in order to produce ZnO based quantum well lasers similar to the previously introduced n-AlGaAs/GaAs/p-AlGaAs structures; we have attempted to grow Zn 1 -xSn x O thin films to enlarge the band gap energy. An increase up to 170 meV has been observed in Zn 1 -xSn x O thin films and this is enough barrier to be able to trap electron-hole pairs in quantum well structures. As a result, two important key issues; p-type conductivity and enhancement of the band gap energy in order to step forward towards the production of electro luminescent UV LEDs and quantum well lasers have been investigated and will be presented in this study

  14. Epitaxial heterojunctions of oxide semiconductors and metals on high temperature superconductors

    Vasquez, Richard P. (Inventor); Hunt, Brian D. (Inventor); Foote, Marc C. (Inventor)

    1994-01-01

    Epitaxial heterojunctions formed between high temperature superconductors and metallic or semiconducting oxide barrier layers are provided. Metallic perovskites such as LaTiO3, CaVO3, and SrVO3 are grown on electron-type high temperature superconductors such as Nd(1.85)Ce(0.15)CuO(4-x). Alternatively, transition metal bronzes of the form A(x)MO(3) are epitaxially grown on electron-type high temperature superconductors. Also, semiconducting oxides of perovskite-related crystal structures such as WO3 are grown on either hole-type or electron-type high temperature superconductors.

  15. WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

    Cao, Q; Brehler, M; Sisniega, A; Marinetto, E; Stayman, J; Siewerdsen, J; Zbijewski, W [Johns Hopkins University, Baltimore, MD (United States); Zyazin, A; Peters, I [Teledyne DALSA, Eindhoven (Netherlands); Yorkston, J [Carestream Health, Inc, Penfield, NY (United States)

    2016-06-15

    Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection) using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high

  16. An acetone microsensor with a ring oscillator circuit fabricated using the commercial 0.18 μm CMOS process.

    Yang, Ming-Zhi; Dai, Ching-Liang; Shih, Po-Jen

    2014-07-17

    This study investigates the fabrication and characterization of an acetone microsensor with a ring oscillator circuit using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The acetone microsensor contains a sensitive material, interdigitated electrodes and a polysilicon heater. The sensitive material is α-Fe2O3 synthesized by the hydrothermal method. The sensor requires a post-process to remove the sacrificial oxide layer between the interdigitated electrodes and to coat the α-Fe2O3 on the electrodes. When the sensitive material adsorbs acetone vapor, the sensor produces a change in capacitance. The ring oscillator circuit converts the capacitance of the sensor into the oscillation frequency output. The experimental results show that the output frequency of the acetone sensor changes from 128 to 100 MHz as the acetone concentration increases 1 to 70 ppm.

  17. WE-AB-207A-01: BEST IN PHYSICS (IMAGING): High-Resolution Cone-Beam CT of the Extremities and Cancellous Bone Architecture with a CMOS Detector

    Cao, Q; Brehler, M; Sisniega, A; Marinetto, E; Stayman, J; Siewerdsen, J; Zbijewski, W; Zyazin, A; Peters, I; Yorkston, J

    2016-01-01

    Purpose: Extremity cone-beam CT (CBCT) with an amorphous silicon (aSi) flat-panel detector (FPD) provides low-dose volumetric imaging with high spatial resolution. We investigate the performance of the newer complementary metal-oxide semiconductor (CMOS) detectors to enhance resolution of extremities CBCT to ∼0.1 mm, enabling morphological analysis of trabecular bone. Quantitative in-vivo imaging of bone microarchitecture could present an important advance for osteoporosis and osteoarthritis diagnosis and therapy assessment. Methods: Cascaded systems models of CMOS- and FPD-based extremities CBCT were implemented. Performance was compared for a range of pixel sizes (0.05–0.4 mm), focal spot sizes (0.3–0.6 FS), and x-ray techniques (0.05–0.8 mAs/projection) using detectability of high-, low-, and all-frequency tasks for a nonprewhitening observer. Test-bench implementation of CMOS-based extremity CBCT involved a Teledyne DALSA Xineos3030HR detector with 0.099 mm pixels and a compact rotating anode x-ray source with 0.3 FS (IMD RTM37). Metrics of bone morphology obtained using CMOS-based CBCT were compared in cadaveric specimens to FPD-based system using a Varian PaxScan4030 (0.194 mm pixels). Results: Finer pixel size and reduced electronic noise for CMOS (136 e compared to 2000 e for FPD) resulted in ∼1.9× increase in detectability for high-frequency tasks and ∼1.1× increase for all-frequency tasks. Incorporation of the new x-ray source with reduced focal spot size (0.3 FS vs. 0.5 FS used on current extremities CBCT) improved detectability for CMOS-based CBCT by ∼1.7× for high-frequency tasks. Compared to FPD CBCT, the CMOS detector yielded improved agreement with micro-CT in measurements of trabecular thickness (∼1.7× reduction in relative error), bone volume (∼1.5× reduction), and trabecular spacing (∼3.5× reduction). Conclusion: Imaging performance modelling and experimentation indicate substantial improvements for high

  18. Wideband CMOS receivers

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  19. Positron annihilation spectroscopic characterization of defects in wide band gap oxide semiconductors

    Sarkar, A.; Luitel, Homnath; Gogurla, N.; Sanyal, D.

    2017-03-01

    Annealing effect of granular ZnO has been studied by Doppler broadened electron positron annihilated γ-ray (0.511 MeV) line shape measurement. Ratio curve analysis shows that granular ZnO samples contain both Zn and O vacancies. Such defects exist as agglomerates of several vacancies and start to recover above 400 °C annealing. It has also been observed that due to annealing temperature difference of 125 °C (from 325 °C to 450 °C), huge change occurs in low temperature photoluminescence (PL) of ZnO. Significant reduction of free to bound (FB) transition ~3.315 eV is observed for increasing the annealing temperature. It has been conjectured that ~3.315 eV PL in ZnO is related to particular decoration (unknown) of both Zn and O vacancies. The methodology of revealing defect-property correlation as employed here can also be applied to other types of semiconductors.

  20. Radiation-hardened CMOS integrated circuits

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  1. Crystalline oxides on semiconductors: A structural transition of the interface phase

    Walker, F. J.; Buongiorno-Nardelli, Marco; Billman, C. A.; McKee, R. A.

    2004-03-01

    The growth of crystalline oxides on silicon is facilitated by the preparation of a surface phase of alkaline earth silicide. We describe how the surface phase serves as a precursor of the final interface phase using reflection high energy electron diffraction (RHEED) and density functional theory (DFT). RHEED intensity oscillations of the growth of BaSrO show layer-by-layer build up of the oxide on the interface. The 2x1 symmetry of the surface precursor persists up to 3 ML BaSrO coverage at which point a 1x1 pattern characteristic of the rock-salt structure of BaSrO is observed. Prior to 3 ML growth of alkaline earth oxide, DFT calculations and RHEED show that the surface precursor persists as the interface phase and induces large displacements in the growing oxide layer away from the rock-salt structure and having a 2x1 symmetry. These distortions of the rock-salt structure are energetically unfavorable and become more unfavorable as the oxide thickness increases. At 3 ML, the stability of the rock-salt structure drives a structural transformation of the film and the interface phase to a structure that is distinct from the surface precursor. Research sponsored jointly by the Division of Materials Sciences and Engineering, Office of Basic Energy Sciences, U.S. Department of Energy at Oak Ridge National Laboratory under contract DE-AC05-00OR22725 with UT-Battelle, LLC and at the University of Tennessee under contract DE-FG02-01ER45937. Calculations have been performed on CCS supercomputers at Oak Ridge National Laboratory.

  2. An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors

    Jiangwei Liu

    2018-06-01

    Full Text Available Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond for metal-oxide-semiconductor (MOS capacitors and MOS field-effect transistors (MOSFETs is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD and sputtering deposition (SD techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2, ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD-TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H-diamond and SD-HfO2/ALD-HfO2/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H-diamond, SD-HfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

  3. Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

    Senyukov, Serhiy; Besson, Auguste; Claus, Giles; Cousin, Loic; Dulinski, Wojciech; Goffe, Mathieu; Hippolyte, Boris; Maria, Robert; Molnar, Levente; Sanchez Castro, Xitzel; Winter, Marc

    2014-01-01

    CMOS pixel sensors (CPS) represent a novel technological approach to building charged particle detectors. CMOS processes allow to integrate a sensing volume and readout electronics in a single silicon die allowing to build sensors with a small pixel pitch ($\\sim 20 \\mu m$) and low material budget ($\\sim 0.2-0.3\\% X_0$) per layer. These characteristics make CPS an attractive option for vertexing and tracking systems of high energy physics experiments. Moreover, thanks to the mass production industrial CMOS processes used for the manufacturing of CPS the fabrication construction cost can be significantly reduced in comparison to more standard semiconductor technologies. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential. The permanent evolution of commercial CMOS processes towards smaller feature sizes and high resistivity ...

  4. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    Hu Rongbin; Wang Yuxin; Lu Wu

    2014-01-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  5. Silicon CMOS architecture for a spin-based quantum computer.

    Veldhorst, M; Eenink, H G J; Yang, C H; Dzurak, A S

    2017-12-15

    Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

  6. CMOS Image Sensor with a Built-in Lane Detector

    Li-Chen Fu

    2009-03-01

    Full Text Available This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC or Digital Signal Processor (DSP, the proposed imager, without extra Analog to Digital Converter (ADC circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 x 2,389.8 mm, and the package uses 40 pin Dual-In-Package (DIP. The pixel cell size is 18.45 x 21.8 mm and the core size of photodiode is 12.45 x 9.6 mm; the resulting fill factor is 29.7%.

  7. CMOS Image Sensor with a Built-in Lane Detector.

    Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

    2009-01-01

    This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

  8. Fully CMOS-compatible titanium nitride nanoantennas

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  9. Plasmonic Modulator Using CMOS Compatible Material Platform

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation i...... for integration with existing insulator-metal-insu lator plasmonic waveguides as well as novel photonic/electronic hybrid circuits...

  10. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  11. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  12. Using polynomials to simplify fixed pattern noise and photometric correction of logarithmic CMOS image sensors.

    Li, Jing; Mahmoodi, Alireza; Joseph, Dileepan

    2015-10-16

    An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient.

  13. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  14. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  15. Simulation of pulsed-ionizing-radiation-induced errors in CMOS memory circuits

    Massengill, L.W.

    1987-01-01

    Effects of transient ionizing radiation on complementary metal-oxide-semiconductor (CMOS) memory circuits was studied by computer simulation. Simulation results have uncovered the dominant mechanism leading to information loss (upset) in dense (CMOS) circuits: rail span collapse. This effect is the catastrophic reduction in the local power supply at a RAM cell location due to the conglomerate radiation-induced photocurrents from all other RAM cells flowing through the power-supply-interconnect distribution. Rail-span collapse leads to reduced RAM cell-noise margins and can predicate upset. Results show that rail-span collapse in the dominant pulsed radiation effect in many memory circuits, preempting local circuit responses to the radiation. Several techniques to model power-supply noise, such as that arising from rail span collapse, are presented in this work. These include an analytical model for design optimization against these effects, a hierarchical computer-analysis technique for efficient power bus noise simulation in arrayed circuits, such as memories, and a complete circuit-simulation tool for noise margin analysis of circuits with arbitrary topologies

  16. Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

    Xiaoliang Ge

    2018-02-01

    Full Text Available This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

  17. Fabrication of a Micromachined Capacitive Switch Using the CMOS-MEMS Technology

    Cheng-Yang Lin

    2015-11-01

    Full Text Available The study investigates the design and fabrication of a micromachined radio frequency (RF capacitive switch using the complementary metal oxide semiconductor-microelectromechanical system (CMOS-MEMS technology. The structure of the micromachined switch is composed of a membrane, eight springs, four inductors, and coplanar waveguide (CPW lines. In order to reduce the actuation voltage of the switch, the springs are designed as low stiffness. The finite element method (FEM software CoventorWare is used to simulate the actuation voltage and displacement of the switch. The micromachined switch needs a post-CMOS process to release the springs and membrane. A wet etching is employed to etch the sacrificial silicon dioxide layer, and to release the membrane and springs of the switch. Experiments show that the pull-in voltage of the switch is 12 V. The switch has an insertion loss of 0.8 dB at 36 GHz and an isolation of 19 dB at 36 GHz.

  18. Sonocatalytic degradation of malachite green oxalate by a semiconductor metal oxide nanocatalyst.

    Bhavani, R; Sivasamy, A

    2016-12-01

    Advanced Oxidation Process (AOP) technologies are considered to be better technique for the degradation or mineralization of many recalcitrant compounds and pollutants. In the present study heterogeneous sonocatalytic degradation of a model organic compound such as Malachite green oxalate (MGO) was carried out in the aqueous phase. Zinc oxide nanorods were prepared by precipitation method employing zinc acetates as precursors and were characterized by FT-IR, XRD, FE-SEM and EDAX analysis. Degradation of MGO in the aqueous phase was studied in detail under the sonocatalytic process. Effects of pH, dye concentration, oxidant concentration, kinetics and effect of electrolytes on dye degradation were carried out to check the efficiency of the sonocatalyst. Effect of energy input on the degradation processes was also investigated. The degradation of dye molecules were monitored by UV-visible spectrophotometer and Chemical Oxygen demand (COD). The dye molecules were readily degraded at above 90% in the pH range 5.0-7.0 under ultrasound with zinc oxide nanorods. The interference of electrolytes like NaCl, KCl, Na 2 CO 3 , NaHCO 3 and MgSO 4 on the degradation of dye molecules were also studied on the sonocatalytic degradation of MGO. From the kinetic studies it was observed that at lower initial concentration of dye molecules the degradation efficiency was above 90%. The rate of the reaction decreased on increasing the initial dye concentrations of the dye molecules. It was observed that the complete mineralization of dye molecules was achieved without the formation of toxic by-products. The reusability of the catalyst also showed the effective degradation of the dye molecules up to five cycles without loss of the catalytic activities. Copyright © 2015 Elsevier Inc. All rights reserved.

  19. Three-dimensional cascaded system analysis of a 50 µm pixel pitch wafer-scale CMOS active pixel sensor x-ray detector for digital breast tomosynthesis.

    Zhao, C; Vassiljev, N; Konstantinidis, A C; Speller, R D; Kanicki, J

    2017-03-07

    High-resolution, low-noise x-ray detectors based on the complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been developed and proposed for digital breast tomosynthesis (DBT). In this study, we evaluated the three-dimensional (3D) imaging performance of a 50 µm pixel pitch CMOS APS x-ray detector named DynAMITe (Dynamic Range Adjustable for Medical Imaging Technology). The two-dimensional (2D) angle-dependent modulation transfer function (MTF), normalized noise power spectrum (NNPS), and detective quantum efficiency (DQE) were experimentally characterized and modeled using the cascaded system analysis at oblique incident angles up to 30°. The cascaded system model was extended to the 3D spatial frequency space in combination with the filtered back-projection (FBP) reconstruction method to calculate the 3D and in-plane MTF, NNPS and DQE parameters. The results demonstrate that the beam obliquity blurs the 2D MTF and DQE in the high spatial frequency range. However, this effect can be eliminated after FBP image reconstruction. In addition, impacts of the image acquisition geometry and detector parameters were evaluated using the 3D cascaded system analysis for DBT. The result shows that a wider projection angle range (e.g.  ±30°) improves the low spatial frequency (below 5 mm -1 ) performance of the CMOS APS detector. In addition, to maintain a high spatial resolution for DBT, a focal spot size of smaller than 0.3 mm should be used. Theoretical analysis suggests that a pixelated scintillator in combination with the 50 µm pixel pitch CMOS APS detector could further improve the 3D image resolution. Finally, the 3D imaging performance of the CMOS APS and an indirect amorphous silicon (a-Si:H) thin-film transistor (TFT) passive pixel sensor (PPS) detector was simulated and compared.

  20. Use and imaging performance of CMOS flat panel imager with LiF/ZnS(Ag) and Gadox scintillation screens for neutron radiography

    Cha, B. K.; kim, J. Y.; Kim, T. J.; Sim, C.; Cho, G.; Lee, D. H.; Seo, C.-W.; Jeon, S.; Huh, Y.

    2011-01-01

    In digital neutron radiography system, a thermal neutron imaging detector based on neutron-sensitive scintillating screens with CMOS(complementary metal oxide semiconductor) flat panel imager is introduced for non-destructive testing (NDT) application. Recently, large area CMOS APS (active-pixel sensor) in conjunction with scintillation films has been widely used in many digital X-ray imaging applications. Instead of typical imaging detectors such as image plates, cooled-CCD cameras and amorphous silicon flat panel detectors in combination with scintillation screens, we tried to apply a scintillator-based CMOS APS to neutron imaging detection systems for high resolution neutron radiography. In this work, two major Gd2O2S:Tb and 6LiF/ZnS:Ag scintillation screens with various thickness were fabricated by a screen printing method. These neutron converter screens consist of a dispersion of Gd2O2S:Tb and 6LiF/ZnS:Ag scintillating particles in acrylic binder. These scintillating screens coupled-CMOS flat panel imager with 25x50mm2 active area and 48μm pixel pitch was used for neutron radiography. Thermal neutron flux with 6x106n/cm2/s was utilized at the NRF facility of HANARO in KAERI. The neutron imaging characterization of the used detector was investigated in terms of relative light output, linearity and spatial resolution in detail. The experimental results of scintillating screen-based CMOS flat panel detectors demonstrate possibility of high sensitive and high spatial resolution imaging in neutron radiography system.

  1. An ultrasensitive method of real time pH monitoring with complementary metal oxide semiconductor image sensor.

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2015-02-09

    CMOS sensors are becoming a powerful tool in the biological and chemical field. In this work, we introduce a new approach on quantifying various pH solutions with a CMOS image sensor. The CMOS image sensor based pH measurement produces high-accuracy analysis, making it a truly portable and user friendly system. pH indicator blended hydrogel matrix was fabricated as a thin film to the accurate color development. A distinct color change of red, green and blue (RGB) develops in the hydrogel film by applying various pH solutions (pH 1-14). The semi-quantitative pH evolution was acquired by visual read out. Further, CMOS image sensor absorbs the RGB color intensity of the film and hue value converted into digital numbers with the aid of an analog-to-digital converter (ADC) to determine the pH ranges of solutions. Chromaticity diagram and Euclidean distance represent the RGB color space and differentiation of pH ranges, respectively. This technique is applicable to sense the various toxic chemicals and chemical vapors by situ sensing. Ultimately, the entire approach can be integrated into smartphone and operable with the user friendly manner. Copyright © 2014 Elsevier B.V. All rights reserved.

  2. Direct observation of both contact and remote oxygen scavenging of GeO2 in a metal-oxide-semiconductor stack

    Fadida, S.; Shekhter, P.; Eizenberg, M.; Cvetko, D.; Floreano, L.; Verdini, A.; Nyns, L.; Van Elshocht, S.; Kymissis, I.

    2014-01-01

    In the path to incorporating Ge based metal-oxide-semiconductor into modern nano-electronics, one of the main issues is the oxide-semiconductor interface quality. Here, the reactivity of Ti on Ge stacks and the scavenging effect of Ti were studied using synchrotron X-ray photoelectron spectroscopy measurements, with an in-situ metal deposition and high resolution transmission electron microscopy imaging. Oxygen removal from the Ge surface was observed both in direct contact as well as remotely through an Al 2 O 3 layer. The scavenging effect was studied in situ at room temperature and after annealing. We find that the reactivity of Ti can be utilized for improved scaling of Ge based devices.

  3. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    Rojas, Jhonathan Prieto

    2013-02-12

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  4. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

    2013-01-01

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  5. Modeling and evaluation of a high-resolution CMOS detector for cone-beam CT of the extremities.

    Cao, Qian; Sisniega, Alejandro; Brehler, Michael; Stayman, J Webster; Yorkston, John; Siewerdsen, Jeffrey H; Zbijewski, Wojciech

    2018-01-01

    Quantitative assessment of trabecular bone microarchitecture in extremity cone-beam CT (CBCT) would benefit from the high spatial resolution, low electronic noise, and fast scan time provided by complementary metal-oxide semiconductor (CMOS) x-ray detectors. We investigate the performance of CMOS sensors in extremity CBCT, in particular with respect to potential advantages of thin (CMOS x-ray detector incorporating the effects of CsI:Tl scintillator thickness was developed. Simulation studies were performed using nominal extremity CBCT acquisition protocols (90 kVp, 0.126 mAs/projection). A range of scintillator thickness (0.35-0.75 mm), pixel size (0.05-0.4 mm), focal spot size (0.05-0.7 mm), magnification (1.1-2.1), and dose (15-40 mGy) was considered. The detectability index was evaluated for both CMOS and a-Si:H flat-panel detector (FPD) configurations for a range of imaging tasks emphasizing spatial frequencies associated with feature size aobj. Experimental validation was performed on a CBCT test bench in the geometry of a compact orthopedic CBCT system (SAD = 43.1 cm, SDD = 56.0 cm, matching that of the Carestream OnSight 3D system). The test-bench studies involved a 0.3 mm focal spot x-ray source and two CMOS detectors (Dalsa Xineos-3030HR, 0.099 mm pixel pitch) - one with the standard CsI:Tl thickness of 0.7 mm (C700) and one with a custom 0.4 mm thick scintillator (C400). Measurements of modulation transfer function (MTF), detective quantum efficiency (DQE), and CBCT scans of a cadaveric knee (15 mGy) were obtained for each detector. Optimal detectability for high-frequency tasks (feature size of ~0.06 mm, consistent with the size of trabeculae) was ~4× for the C700 CMOS detector compared to the a-Si:H FPD at nominal system geometry of extremity CBCT. This is due to ~5× lower electronic noise of a CMOS sensor, which enables input quantum-limited imaging at smaller pixel size. Optimal pixel size for high-frequency tasks was CMOS

  6. Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

    Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

    2018-05-01

    Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

  7. First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

    Mao, L.F.; Wang, Z.O.

    2008-01-01

    HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  8. Fully-Coupled Thermo-Electrical Modeling and Simulation of Transition Metal Oxide Memristors

    Mamaluy, Denis [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gao, Xujiao [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tierney, Brian David [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Marinella, Matthew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Mickel, Patrick [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tierney, Brian D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-11-01

    Transition metal oxide (TMO) memristors have recently attracted special attention from the semiconductor industry and academia. Memristors are one of the strongest candidates to replace flash memory, and possibly DRAM and SRAM in the near future. Moreover, memristors have a high potential to enable beyond-CMOS technology advances in novel architectures for high performance computing (HPC). The utility of memristors has been demonstrated in reprogrammable logic (cross-bar switches), brain-inspired computing and in non-CMOS complementary logic. Indeed, the potential use of memristors as logic devices is especially important considering the inevitable end of CMOS technology scaling that is anticipated by 2025. In order to aid the on-going Sandia memristor fabrication effort with a memristor design tool and establish a clear physical picture of resistance switching in TMO memristors, we have created and validated with experimental data a simulation tool we name the Memristor Charge Transport (MCT) Simulator.

  9. Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

    Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

    2015-07-01

    Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

  10. Characteristics of drain-modulated generation current in n-type metal-oxide-semiconductor field-effect transistor

    Chen Hai-Feng; Guo Li-Xin; Zheng Pu-Yang; Dong Zhao; Zhang Qian

    2015-01-01

    Drain-modulated generation current I DMG induced by interface traps in an n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) is investigated. The formation of I DMG ascribes to the change of the Si surface potential φ s . This change makes the channel suffer transformation from the inversion state, depletion I state to depletion II state. The simulation result agrees with the experiment in the inversion and depletion I states. In the depletion II state, the theoretical curve goes into saturation, while the experimental curve drops quickly as V D increases. The reason for this unconformity is that the drain-to-gate voltage V DG lessens φ s around the drain corner and controls the falling edge of the I DMG curve. The experiments of gate-modulated generation and recombination currents are also applied to verify the reasonability of the mechanism. Based on this mechanism, a theoretical model of the I DMG falling edge is set up in which I DMG has an exponential attenuation relation with V DG . Finally, the critical fitting coefficient t of the experimental curves is extracted. It is found that t = 80 mV = 3kT/q. This result fully shows the accuracy of the above mechanism. (paper)

  11. Single-electron regime and Pauli spin blockade in a silicon metal-oxide-semiconductor double quantum dot

    Rochette, Sophie; Ten Eyck, Gregory A.; Pluym, Tammy; Lilly, Michael P.; Carroll, Malcolm S.; Pioro-Ladrière, Michel

    2015-03-01

    Silicon quantum dots are promising candidates for quantum information processing as spin qubits with long coherence time. We present electrical transport measurements on a silicon metal-oxide-semiconductor (MOS) double quantum dot (DQD). First, Coulomb diamonds measurements demonstrate the one-electron regime at a relatively high temperature of 1.5 K. Then, the 8 mK stability diagram shows Pauli spin blockade with a large singlet-triplet separation of approximatively 0.40 meV, pointing towards a strong lifting of the valley degeneracy. Finally, numerical simulations indicate that by integrating a micro-magnet to those devices, we could achieve fast spin rotations of the order of 30 ns. Those results are part of the recent body of work demonstrating the potential of Si MOS DQD as reliable and long-lived spin qubits that could be ultimately integrated into modern electronic facilities. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. DOE's National Nuclear Security Administration under Contract DE-AC04-94AL85000.

  12. Impact of process temperature on GaSb metal-oxide-semiconductor interface properties fabricated by ex-situ process

    Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi [Department of Electrical Engineering and Information Systems, The University of Tokyo, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); JST-CREST, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); Asakura, Yuji [Department of Electrical Engineering and Information Systems, The University of Tokyo, Yayoi 2-11-16, Bunkyo, Tokyo 113-0032 (Japan); Yokoyama, Haruki [NTT Photonics Laboratories, NTT Corporation, Atsugi 243-0198 (Japan)

    2014-06-30

    We have studied the impact of process temperature on interface properties of GaSb metal-oxide-semiconductor (MOS) structures fabricated by an ex-situ atomic-layer-deposition (ALD) process. We have found that the ALD temperature strongly affects the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The Al{sub 2}O{sub 3}/GaSb MOS interfaces fabricated at the low ALD temperature of 150 °C have the minimum interface-trap density (D{sub it}) of ∼4.5 × 10{sup 13 }cm{sup −2} eV{sup −1}. We have also found that the post-metalization annealing at temperature higher than 200 °C degrades the Al{sub 2}O{sub 3}/GaSb MOS interface properties. The low-temperature process is preferable in fabricating GaSb MOS interfaces in the ex-situ ALD process to avoid the high-temperature-induced degradations.

  13. Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

    Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

    2015-10-01

    Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

  14. A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

    Tharun Konduru

    2015-01-01

    Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

  15. Temperature Modulation with Specified Detection Point on Metal Oxide Semiconductor Gas Sensors for E-Nose Application

    Arief SUDARMAJI

    2015-03-01

    Full Text Available Temperature modulation technique, some called dynamic measurement mode, on Metal-Oxide Semiconductor (MOS/MOX gas sensor has been widely observed and employed in many fields. We present its development, a Specified Detection Point (SDP on modulated sensing element of MOS sensor is applied which associated to its temperature modulation, temperature modulation-SDP so-named. We configured the rectangular modulation signal for MOS gas sensors (TGSs and FISs using PSOC CY8C28445-24PVXI (Programmable System on Chip which also functioned as acquisition unit and interface to a computer. Initial responses and selectivity evaluations were performed using statistical tool and Principal Component Analysis (PCA to differ sample gases (Toluene, Ethanol and Ammonia on dynamic chamber measurement under various frequencies (0.25 Hz, 1 Hz, 4 Hz and duty-cycles (25 %, 50 %, 75 %. We found that at lower frequency the response waveform of the sensors becomes more sloping and distinct, and selected modulations successfully increased the selectivity either on singular or array sensors rather than static temperature measurement.

  16. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon assisted tunneling

    Koswatta, Siyuranga O.; Lundstrom, Mark S.; Nikonov, Dmitri E.

    2007-01-01

    Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the non-equilibrium Green's functions formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (Y. Lu et al, J. Am. Chem. Soc.,...

  17. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  18. Effect of titanium oxide-polystyrene nanocomposite dielectrics on morphology and thin film transistor performance for organic and polymeric semiconductors

    Della Pelle, Andrea M. [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States); Maliakal, Ashok, E-mail: maliakal@lgsinnovations.com [LGS Innovations, 15 Vreeland Rd., Florham Park, NJ 07932 (United States); Sidorenko, Alexander [Department of Chemistry and Biochemistry, University of the Sciences, 600 South 43rd St., Philadelphia, PA 191034 (United States); Thayumanavan, S. [Department of Chemistry, University of Massachusetts Amherst, 710 N. Pleasant St. Amherst, MA 01003 (United States)

    2012-07-31

    Previous studies have shown that organic thin film transistors with pentacene deposited on gate dielectrics composed of a blend of high K titanium oxide-polystyrene core-shell nanocomposite (TiO{sub 2}-PS) with polystyrene (PS) perform with an order of magnitude increase in saturation mobility for TiO{sub 2}-PS (K = 8) as compared to PS devices (K = 2.5). The current study finds that this performance enhancement can be translated to alternative small single crystal organics such as {alpha}-sexithiophene ({alpha}-6T) (enhancement factor for field effect mobility ranging from 30-100 Multiplication-Sign higher on TiO{sub 2}-PS/PS blended dielectrics as compared to homogenous PS dielectrics). Interestingly however, in the case of semicrystalline polymers such as (poly-3-hexylthiophene) P3HT, this dramatic enhancement is not observed, possibly due to the difference in processing conditions used to fabricate these devices (film transfer as opposed to thermal evaporation). The morphology for {alpha}-sexithiophene ({alpha}-6T) grown by thermal evaporation on TiO{sub 2}-PS/PS blended dielectrics parallels that observed in pentacene devices. Smaller grain size is observed for films grown on dielectrics with higher TiO{sub 2}-PS content. In the case of poly(3-hexylthiophene) (P3HT) devices, constructed via film transfer, morphological differences exist for the P3HT on different substrates, as discerned by atomic force microscopy studies. However, these devices only exhibit a modest (2 Multiplication-Sign ) increase in mobility with increasing TiO{sub 2}-PS content in the films. After annealing of the transferred P3HT thin film transistor (TFT) devices, no appreciable enhancement in mobility is observed across the different blended dielectrics. Overall the results support the hypothesis that nucleation rate is responsible for changes in film morphology and device performance in thermally evaporated small molecule crystalline organic semiconductor TFTs. The increased nucleation

  19. Intrinsic electronic defects and multiple-atom processes in the oxidic semiconductor Ga2O3

    Schmeißer, Dieter; Henkel, Karsten

    2018-04-01

    We report on the electronic structure of gallium oxide (Ga2O3) single crystals as studied by resonant photoelectron spectroscopy (resPES). We identify intrinsic electronic defects that are formed by mixed-atomic valence states. We differentiate three coexisting defect states that differ in their electronic correlation energy and their spatial localization lengths. Their relative abundance is described by a fractional ionicity with covalent and ionic bonding contributions. For Ga2O3, our analyses of the resPES data enable us to derive two main aspects: first, experimental access is given to determine the ionicity based on the original concepts of Pauling and Phillips. Second, we report on multi-atomic energy loss processes in the Ga2p core level and X-ray absorption data. The two experimental findings can be explained consistently in the same context of mixed-atomic valence states and intrinsic electronic defects.

  20. Determining the thermal expansion coefficient of thin films for a CMOS MEMS process using test cantilevers

    Cheng, Chao-Lin; Fang, Weileun; Tsai, Ming-Han

    2015-01-01

    Many standard CMOS processes, provided by existing foundries, are available. These standard CMOS processes, with stacking of various metal and dielectric layers, have been extensively applied in integrated circuits as well as micro-electromechanical systems (MEMS). It is of importance to determine the material properties of the metal and dielectric films to predict the performance and reliability of micro devices. This study employs an existing approach to determine the coefficients of thermal expansion (CTEs) of metal and dielectric films for standard CMOS processes. Test cantilevers with different stacking of metal and dielectric layers for standard CMOS processes have been designed and implemented. The CTEs of standard CMOS films can be determined from measurements of the out-of-plane thermal deformations of the test cantilevers. To demonstrate the feasibility of the present approach, thin films prepared by the Taiwan Semiconductor Manufacture Company 0.35 μm 2P4M CMOS process are characterized. Eight test cantilevers with different stacking of CMOS layers and an auxiliary Si cantilever on a SOI wafer are fabricated. The equivalent elastic moduli and CTEs of the CMOS thin films including the metal and dielectric layers are determined, respectively, from the resonant frequency and static thermal deformation of the test cantilevers. Moreover, thermal deformations of cantilevers with stacked layers different to those of the test beams have been employed to verify the measured CTEs and elastic moduli. (paper)

  1. An integrated semiconductor device enabling non-optical genome sequencing.

    Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

    2011-07-20

    The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

  2. Highly Transparent, Visible-Light Photodetector Based on Oxide Semiconductors and Quantum Dots.

    Shin, Seung Won; Lee, Kwang-Ho; Park, Jin-Seong; Kang, Seong Jun

    2015-09-09

    Highly transparent phototransistors that can detect visible light have been fabricated by combining indium-gallium-zinc oxide (IGZO) and quantum dots (QDs). A wide-band-gap IGZO film was used as a transparent semiconducting channel, while small-band-gap QDs were adopted to absorb and convert visible light to an electrical signal. Typical IGZO thin-film transistors (TFTs) did not show a photocurrent with illumination of visible light. However, IGZO TFTs decorated with QDs showed enhanced photocurrent upon exposure to visible light. The device showed a responsivity of 1.35×10(4) A/W and an external quantum efficiency of 2.59×10(4) under illumination by a 635 nm laser. The origin of the increased photocurrent in the visible light was the small band gap of the QDs combined with the transparent IGZO films. Therefore, transparent phototransistors based on IGZO and QDs were fabricated and characterized in detail. The result is relevant for the development of highly transparent photodetectors that can detect visible light.

  3. Defects in Amorphous Semiconductors: The Case of Amorphous Indium Gallium Zinc Oxide

    de Jamblinne de Meux, A.; Pourtois, G.; Genoe, J.; Heremans, P.

    2018-05-01

    Based on a rational classification of defects in amorphous materials, we propose a simplified model to describe intrinsic defects and hydrogen impurities in amorphous indium gallium zinc oxide (a -IGZO). The proposed approach consists of organizing defects into two categories: point defects, generating structural anomalies such as metal—metal or oxygen—oxygen bonds, and defects emerging from changes in the material stoichiometry, such as vacancies and interstitial atoms. Based on first-principles simulations, it is argued that the defects originating from the second group always act as perfect donors or perfect acceptors. This classification simplifies and rationalizes the nature of defects in amorphous phases. In a -IGZO, the most important point defects are metal—metal bonds (or small metal clusters) and peroxides (O - O single bonds). Electrons are captured by metal—metal bonds and released by the formation of peroxides. The presence of hydrogen can lead to two additional types of defects: metal-hydrogen defects, acting as acceptors, and oxygen-hydrogen defects, acting as donors. The impact of these defects is linked to different instabilities observed in a -IGZO. Specifically, the diffusion of hydrogen and oxygen is connected to positive- and negative-bias stresses, while negative-bias illumination stress originates from the formation of peroxides.

  4. Numerical Simulation of Tunneling Current in an Anisotropic Metal-Oxide-Semiconductor Capacitor

    Khairurrijal khairurrijal

    2012-09-01

    Full Text Available In this paper, we have developed a model of the tunneling currents through a high-k dielectric stack in MOS capacitors with anisotropic masses. The transmittance was numerically calculated by employing a transfer matrix method and including longitudinal-transverse kinetic energy coupling which is represented by an electron phase velocity in the gate. The transmittance was then applied to calculate tunneling currents in TiN/HfSiOxN/SiO2/p-Si MOS capacitors. The calculated results show that as the gate electron velocity increases, the transmittance decreases and therefore the tunneling current reduces. The tunneling current becomes lower as the effective oxide thickness (EOT of HfSiOxN layer increases. When the incident electron passed through the barriers in the normal incident to the interface, the electron tunneling process becomes easier. It was also shown that the tunneling current was independent of the substrate orientation. Moreover, the model could be used in designing high speed MOS devices with low tunneling currents.

  5. CMOS analog circuit design

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  6. Nitrogen doped nanocrystalline semiconductor metal oxide: An efficient UV active photocatalyst for the oxidation of an organic dye using slurry Photoreactor.

    Ramachandran, Saranya; Sivasamy, A; Kumar, B Dinesh

    2016-12-01

    Water pollution is a cause for serious concern in today's world. A major contributor to water pollution is industrial effluents containing dyes and other organic molecules. Waste water treatment has become a priority area in today's applied scientific research as it seeks to minimize the toxicity of the effluents being discharged and increase the possibility of water recycling. An efficient and eco-friendly way of degrading toxic molecules is to use nano metal-oxide photocatalysts. The present study aims at enhancing the photocatalytic activity of a semiconductor metal oxide by doping it with nitrogen. A sol-gel cum combustion method was employed to synthesize the catalyst. The prepared catalyst was characterized by FT-IR, XRD, UV-DRS, FESEM and AFM techniques. UV-DRS result showed the catalyst to possess band gap energy of 2.97eV, thus making it active in the UV region of the spectrum. Its photocatalytic activity was evaluated by the degradation of a model pollutant-Orange G dye, under UV light irradiation. Preliminary experiments were carried out to study the effects of pH, catalyst dosage and initial dye concentration on the extent of dye degradation. Kinetic studies revealed that the reaction followed pseudo first order kinetics. The effect of electrolytes on catalyst efficiency was also studied. The progress of the reaction was monitored by absorption studies and measuring the reduction in COD. The catalyst thus prepared was seen to have a high photocatalytic efficiency. The use of this catalyst is a promising means of waste water treatment. Copyright © 2016 Elsevier Inc. All rights reserved.

  7. Composite metal oxide semiconductor based photodiodes for solar panel tracking applications

    Al-Ghamdi, Ahmed A., E-mail: aghamdi90@hotmail.com [Department of Physics, Faculty of Science, King Abdulaziz University, Jeddah (Saudi Arabia); Dere, A. [Department of Physics, Faculty of Science, Firat University, Elazig (Turkey); Tataroğlu, A. [Department of Physics, Faculty of Science, Gazi University, Ankara (Turkey); Arif, Bilal [Department of Physics, Faculty of Science, Firat University, Elazig (Turkey); Yakuphanoglu, F. [Department of Physics, Faculty of Science, King Abdulaziz University, Jeddah (Saudi Arabia); Department of Physics, Faculty of Science, Firat University, Elazig (Turkey); El-Tantawy, Farid [Department of Physics, Faculty of Science, Suez Canal University, Ismailia (Egypt); Farooq, W.A. [Physics and Astronomy Department, College of Science, King Saud University, Riyadh (Saudi Arabia)

    2015-11-25

    The Zn{sub 1−x}Al{sub x}O:Cu{sub 2}O composite films were synthesized by the sol gel method to fabricate photodiodes. The transparent metal oxide Zn{sub 1−x}Al{sub x}O:Cu{sub 2}O thin films were grown on p-Si substrates by spin coating technique. Electrical characterization of the p-Si/AZO:Cu{sub 2}O photodiodes was performed by current–voltage and capacitance–conductance–voltage characteristics under dark and various illumination conditions. The transient photocurrent of the diodes increases with increase in illumination intensity. The photoconducting mechanism of the diodes is controlled by the continuous distribution of trap levels. The photocapacitance and photoconductivity of the diodes are decreased with increasing Cu{sub 2}O content. The series resistance–voltage behavior confirms the presence of the interface states in the interface of the diodes. The photoresponse properties of the diodes indicate that the p-Si/Zn{sub 1−x}Al{sub x}O–Cu{sub 2}O diodes can be used as a photosensor in solar panel tracking applications. - Highlights: • Zn{sub 1−x}Al{sub x}O:Cu{sub 2}O composite films were synthesized by the sol gel method. • p-Si/Zn{sub 1−x}Al{sub x}O–Cu{sub 2}O diodes were fabricated. • p-Si/Zn{sub 1−x}Al{sub x}O–Cu{sub 2}O diodes can be used in the optoelectronic applications.

  8. Sol-gel zinc oxide humidity sensors integrated with a ring oscillator circuit on-a-chip.

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2014-10-28

    The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  9. Sol-Gel Zinc Oxide Humidity Sensors Integrated with a Ring Oscillator Circuit On-a-Chip

    Ming-Zhi Yang

    2014-10-01

    Full Text Available The study develops an integrated humidity microsensor fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated humidity sensor consists of a humidity sensor and a ring oscillator circuit on-a-chip. The humidity sensor is composed of a sensitive film and branch interdigitated electrodes. The sensitive film is zinc oxide prepared by sol-gel method. After completion of the CMOS process, the sensor requires a post-process to remove the sacrificial oxide layer and to coat the zinc oxide film on the interdigitated electrodes. The capacitance of the sensor changes when the sensitive film adsorbs water vapor. The circuit is used to convert the capacitance of the humidity sensor into the oscillation frequency output. Experimental results show that the output frequency of the sensor changes from 84.3 to 73.4 MHz at 30 °C as the humidity increases 40 to 90%RH.

  10. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-01-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

  11. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    Jovanović, B., E-mail: bojan.jovanovic@lirmm.fr, E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L. [LIRMM—University of Montpellier 2/UMR CNRS 5506, 161 Rue Ada, 34095 Montpellier (France)

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  12. Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

    Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

    2015-08-24

    Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

  13. Practical Use of Metal Oxide Semiconductor Gas Sensors for Measuring Nitrogen Dioxide and Ozone in Urban Environments.

    Peterson, Philip J D; Aujla, Amrita; Grant, Kirsty H; Brundle, Alex G; Thompson, Martin R; Vande Hey, Josh; Leigh, Roland J

    2017-07-19

    The potential of inexpensive Metal Oxide Semiconductor (MOS) gas sensors to be used for urban air quality monitoring has been the topic of increasing interest in the last decade. This paper discusses some of the lessons of three years of experience working with such sensors on a novel instrument platform (Small Open General purpose Sensor (SOGS)) in the measurement of atmospheric nitrogen dioxide and ozone concentrations. Analytic methods for increasing long-term accuracy of measurements are discussed, which permit nitrogen dioxide measurements with 95% confidence intervals of 20.0 μ g m - 3 and ozone precision of 26.8 μ g m - 3 , for measurements over a period one month away from calibration, averaged over 18 months of such calibrations. Beyond four months from calibration, sensor drift becomes significant, and accuracy is significantly reduced. Successful calibration schemes are discussed with the use of controlled artificial atmospheres complementing deployment on a reference weather station exposed to the elements. Manufacturing variation in the attributes of individual sensors are examined, an experiment possible due to the instrument being equipped with pairs of sensors of the same kind. Good repeatability (better than 0.7 correlation) between individual sensor elements is shown. The results from sensors that used fans to push air past an internal sensor element are compared with mounting the sensors on the outside of the enclosure, the latter design increasing effective integration time to more than a day. Finally, possible paths forward are suggested for improving the reliability of this promising sensor technology for measuring pollution in an urban environment.

  14. Verification of the plan dosimetry for high dose rate brachytherapy using metal-oxide-semiconductor field effect transistor detectors

    Qi Zhenyu; Deng Xiaowu; Huang Shaomin; Lu Jie; Lerch, Michael; Cutajar, Dean; Rosenfeld, Anatoly

    2007-01-01

    The feasibility of a recently designed metal-oxide-semiconductor field effect transistor (MOSFET) dosimetry system for dose verification of high dose rate (HDR) brachytherapy treatment planning was investigated. MOSFET detectors were calibrated with a 0.6 cm 3 NE-2571 Farmer-type ionization chamber in water. Key characteristics of the MOSFET detectors, such as the energy dependence, that will affect phantom measurements with HDR 192 Ir sources were measured. The MOSFET detector was then applied to verify the dosimetric accuracy of HDR brachytherapy treatments in a custom-made water phantom. Three MOSFET detectors were calibrated independently, with the calibration factors ranging from 0.187 to 0.215 cGy/mV. A distance dependent energy response was observed, significant within 2 cm from the source. The new MOSFET detector has a good reproducibility ( 2 =1). It was observed that the MOSFET detectors had a linear response to dose until the threshold voltage reached approximately 24 V for 192 Ir source measurements. Further comparison of phantom measurements using MOSFET detectors with dose calculations by a commercial treatment planning system for computed tomography-based brachytherapy treatment plans showed that the mean relative deviation was 2.2±0.2% for dose points 1 cm away from the source and 2.0±0.1% for dose points located 2 cm away. The percentage deviations between the measured doses and the planned doses were below 5% for all the measurements. The MOSFET detector, with its advantages of small physical size and ease of use, is a reliable tool for quality assurance of HDR brachytherapy. The phantom verification method described here is universal and can be applied to other HDR brachytherapy treatments

  15. Metal-oxide-semiconductor capacitors and Schottky diodes studied with scanning microwave microscopy at 18 GHz

    Kasper, M. [Christian Doppler Laboratory for Nanoscale Methods in Biophysics, Johannes Kepler University of Linz, Gruberstrasse 40, 4020 Linz (Austria); Gramse, G. [Biophysics Institute, Johannes Kepler University of Linz, Gruberstrasse 40, 4020 Linz (Austria); Hoffmann, J. [METAS, National Metrology Institute of Switzerland, Lindenweg 50, 3003 Bern-Wabern (Switzerland); Gaquiere, C. [MC2 technologies, 5 rue du Colibri, 59650 Villeneuve D' ascq (France); Feger, R.; Stelzer, A. [Institute for Communications Engineering and RF-Systems, Johannes Kepler University, Altenberger Str. 69, 4040 Linz (Austria); Smoliner, J. [Vienna University of Technology, Institute for Solid State Electronics, Floragasse 7, 1040 Vienna (Austria); Kienberger, F., E-mail: ferry-kienberger@keysight.com [Keysight Technologies Austria, Measurement Research Lab, Gruberstrasse 40, 4020 Linz (Austria)

    2014-11-14

    We measured the DC and RF impedance characteristics of micrometric metal-oxide-semiconductor (MOS) capacitors and Schottky diodes using scanning microwave microscopy (SMM). The SMM consisting of an atomic force microscopy (AFM) interfaced with a vector network analyser (VNA) was used to measure the reflection S11 coefficient of the metallic MOS and Schottky contact pads at 18 GHz as a function of the tip bias voltage. By controlling the SMM biasing conditions, the AFM tip was used to bias the Schottky contacts between reverse and forward mode. In reverse bias direction, the Schottky contacts showed mostly a change in the imaginary part of the admittance while in forward bias direction the change was mostly in the real part of the admittance. Reference MOS capacitors which are next to the Schottky diodes on the same sample were used to calibrate the SMM S11 data and convert it into capacitance values. Calibrated capacitance between 1–10 fF and 1/C{sup 2} spectroscopy curves were acquired on the different Schottky diodes as a function of the DC bias voltage following a linear behavior. Additionally, measurements were done directly with the AFM-tip in contact with the silicon substrate forming a nanoscale Schottky contact. Similar capacitance-voltage curves were obtained but with smaller values (30–300 aF) due to the corresponding smaller AFM-tip diameter. Calibrated capacitance images of both the MOS and Schottky contacts were acquired with nanoscale resolution at different tip-bias voltages.

  16. A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

    Yuan, Yang; Yong, Gao; Peng-Liang, Gong

    2008-01-01

    A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  17. Enhanced electrical properties of oxide semiconductor thin-film transistors with high conductivity thin layer insertion for the channel region

    Nguyen, Cam Phu Thi; Raja, Jayapal; Kim, Sunbo; Jang, Kyungsoo; Le, Anh Huy Tuan; Lee, Youn-Jung; Yi, Junsin, E-mail: junsin@skku.edu

    2017-02-28

    Highlights: • The characteristics of thin film transistors using double active layers are examined. • Electrical characteristics have been improved for the double active layers devices. • The total trap density can be decreased by insert-ion of ultrathin ITO film. - Abstract: This study examined the performance and the stability of indium tin zinc oxide (ITZO) thin film transistors (TFTs) by inserting an ultra-thin indium tin oxide (ITO) layer at the active/insulator interface. The electrical properties of the double channel device (ITO thickness of 5 nm) were improved in comparison with the single channel ITZO or ITO devices. The TFT characteristics of the device with an ITO thickness of less than 5 nm were degraded due to the formation of an island-like morphology and the carriers scattering at the active/insulator interface. The 5 nm-thick ITO inserted ITZO TFTs (optimal condition) exhibited a superior field effect mobility (∼95 cm{sup 2}/V·s) compared with the ITZO-only TFTs (∼34 cm{sup 2}/V·s). The best characteristics of the TFT devices with double channel layer are due to the lowest surface roughness (0.14 nm) and contact angle (50.1°) that result in the highest hydrophicility, and the most effective adhesion at the surface. Furthermore, the threshold voltage shifts for the ITO/ITZO double layer device decreased to 0.80 and −2.39 V compared with 6.10 and −6.79 V (for the ITZO only device) under positive and negative bias stress, respectively. The falling rates of E{sub A} were 0.38 eV/V and 0.54 eV/V for the ITZO and ITO/ITZO bi-layer devices, respectively. The faster falling rate of the double channel devices suggests that the trap density, including interface trap and semiconductor bulk trap, can be decreased by the ion insertion of a very thin ITO film into the ITZO/SiO{sub 2} reference device. These results demonstrate that the double active layer TFT can potentially be applied to the flat panel display.

  18. Defects in semiconductors

    Romano, Lucia; Jagadish, Chennupati

    2015-01-01

    This volume, number 91 in the Semiconductor and Semimetals series, focuses on defects in semiconductors. Defects in semiconductors help to explain several phenomena, from diffusion to getter, and to draw theories on materials' behavior in response to electrical or mechanical fields. The volume includes chapters focusing specifically on electron and proton irradiation of silicon, point defects in zinc oxide and gallium nitride, ion implantation defects and shallow junctions in silicon and germanium, and much more. It will help support students and scientists in their experimental and theoret

  19. Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

    Kanaki, Toshiki, E-mail: kanaki@cryst.t.u-tokyo.ac.jp; Asahara, Hirokatsu; Ohya, Shinobu, E-mail: ohya@cryst.t.u-tokyo.ac.jp; Tanaka, Masaaki, E-mail: masaaki@ee.t.u-tokyo.ac.jp [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan)

    2015-12-14

    We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I{sub DS} by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I{sub DS} by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

  20. Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

    Kanaki, Toshiki; Asahara, Hirokatsu; Ohya, Shinobu; Tanaka, Masaaki

    2015-01-01

    We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I DS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I DS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale

  1. Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

    Chyan-Chyi Wu

    2009-02-01

    Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

  2. High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

    Ohara, Tetsuo

    2012-01-01

    A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

  3. The CMOS integration of a power inverter

    Mannarino, Eric Francis

    Due to their falling costs, the use of renewable energy systems is expanding around the world. These systems require the conversion of DC power into grid-synchronous AC power. Currently, the inverters that carry out this task are built using discrete transistors. TowerJazz Semiconductor Corp. has created a commercial CMOS process that allows for blocking voltages of up to 700 V, effectively removing the barrier to integrating power inverters onto a single chip. This thesis explores this process using two topologies. The first is a cell-based switched-capacitor topology first presented by Ke Zou. The second is a novel topology that explores the advantage of using a bused input-output system, as in digital electronics. Simulations run on both topologies confirm the high-efficiency demonstrated in Zou’s process as well as the advantage the bus-based system has in output voltage levels.

  4. Selective, electrochemical etching of a semiconductor

    Dahal, Rajendra P.; Bhat, Ishwara B.; Chow, Tat-Sing

    2018-03-20

    Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

  5. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

    2011-01-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

  6. Structured Analog CMOS Design

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  7. High efficiency grating couplers based on shared process with CMOS MOSFETs

    Qiu Chao; Sheng Zhen; Wu Ai-Min; Wang Xi; Zou Shi-Chang; Gan Fu-Wan; Li Le; Albert Pang

    2013-01-01

    Grating couplers are widely investigated as coupling interfaces between silicon-on-insulator waveguides and optical fibers. In this work, a high-efficiency and complementary metal—oxide—semiconductor (CMOS) process compatible grating coupler is proposed. The poly-Si layer used as a gate in the CMOS metal—oxide—semiconductor field effect transistor (MOSFET) is combined with a normal fully etched grating coupler, which greatly enhances its coupling efficiency. With optimal structure parameters, a coupling efficiency can reach as high as ∼ 70% at a wavelength of 1550 nm as indicated by simulation. From the angle of fabrication, all masks and etching steps are shared between MOSFETs and grating couplers, thereby making the high performance grating couplers easily integrated with CMOS circuits. Fabrication errors such as alignment shift are also simulated, showing that the device is quite tolerant in fabrication. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  8. Semiconductor statistics

    Blakemore, J S

    1987-01-01

    In-depth exploration of the implications of carrier populations and Fermi energies examines distribution of electrons in energy bands and impurity levels of semiconductors. Also: kinetics of semiconductors containing excess carriers, particularly in terms of trapping, excitation, and recombination.

  9. Comparison of the electronic structure of amorphous versus crystalline indium gallium zinc oxide semiconductor: structure, tail states and strain effects

    De Jamblinne de Meux, A; Genoe, J; Heremans, P; Pourtois, G

    2015-01-01

    We study the evolution of the structural and electronic properties of crystalline indium gallium zinc oxide (IGZO) upon amorphization by first-principles calculation. The bottom of the conduction band (BCB) is found to be constituted of a pseudo-band of molecular orbitals that resonate at the same energy on different atomic sites. They display a bonding character between the s orbitals of the metal sites and an anti-bonding character arising from the interaction between the oxygen and metal s orbitals. The energy level of the BCB shifts upon breaking of the crystal symmetry during the amorphization process, which may be attributed to the reduction of the coordination of the cationic centers. The top of the valence band (TVB) is constructed from anti-bonding oxygen p orbitals. In the amorphous state, they have random orientation, in contrast to the crystalline state. This results in the appearance of localized tail states in the forbidden gap above the TVB. Zinc is found to play a predominant role in the generation of these tail states, while gallium hinders their formation. Last, we study the dependence of the fundamental gap and effective mass of IGZO on mechanical strain. The variation of the gap under strain arises from the enhancement of the anti-bonding interaction in the BCB due to the modification of the length of the oxygen–metal bonds and/or to a variation of the cation coordination. This effect is less pronounced for the amorphous material compared to the crystalline material, making amorphous IGZO a semiconductor of choice for flexible electronics. Finally, the effective mass is found to increase upon strain, in contrast to regular materials. This counterintuitive variation is due to the reduction of the electrostatic shielding of the cationic centers by oxygen, leading to an increase of the overlaps between the metal orbitals at the origin of the delocalization of the BCB. For the range of strain typically met in flexible electronics, the induced

  10. Magnesium Oxide (MgO) pH-sensitive Sensing Membrane in Electrolyte-Insulator-Semiconductor Structures with CF4 Plasma Treatment.

    Kao, Chyuan-Haur; Chang, Chia Lung; Su, Wei Ming; Chen, Yu Tzu; Lu, Chien Cheng; Lee, Yu Shan; Hong, Chen Hao; Lin, Chan-Yu; Chen, Hsiang

    2017-08-03

    Magnesium oxide (MgO) sensing membranes in pH-sensitive electrolyte-insulator-semiconductor structures were fabricated on silicon substrate. To optimize the sensing capability of the membrane, CF 4 plasma was incorporated to improve the material quality of MgO films. Multiple material analyses including FESEM, XRD, AFM, and SIMS indicate that plasma treatment might enhance the crystallization and increase the grain size. Therefore, the sensing behaviors in terms of sensitivity, linearity, hysteresis effects, and drift rates might be improved. MgO-based EIS membranes with CF 4 plasma treatment show promise for future industrial biosensing applications.

  11. Standard-free electron-probe microanalysis of thin films of HTSC-oxide and semiconductors (h<1μm)

    Kvardakov, A.M.; Mikhajlova, A.Ya.; San'gin, V.P.; Lazarev, V.B.

    1993-01-01

    A simplified variant of the standard-free electron-probe microanalysis is elaborated to carry out rapid analysis of chemical composition of >1μm thickness thin films of high-temperature superconductor oxides and semiconductors on alien substrates. The suggested technique has increased the efficiency of search for optimal conditions of preparation YBa 2 Cu 3 O x thin films existing in magnetron and InSb ion-beam techniques of spraying on SrTiO 3 and α-Al 2 O 3 monocrystal base substrates

  12. Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

    Liu, Siyang; Zhang, Chunwei; Sun, Weifeng; Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu

    2014-01-01

    Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic

  13. Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

    Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

    2014-04-14

    Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

  14. Bias-induced migration of ionized donors in amorphous oxide semiconductor thin-film transistors with full bottom-gate and partial top-gate structures

    Mallory Mativenga

    2012-09-01

    Full Text Available Bias-induced charge migration in amorphous oxide semiconductor thin-film transistors (TFTs confirmed by overshoots of mobility after bias stressing dual gated TFTs is presented. The overshoots in mobility are reversible and only occur in TFTs with a full bottom-gate (covers the whole channel and partial top-gate (covers only a portion of the channel, indicating a bias-induced uneven distribution of ionized donors: Ionized donors migrate towards the region of the channel that is located underneath the partial top-gate and the decrease in the density of ionized donors in the uncovered portion results in the reversible increase in mobility.

  15. Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

    Yoshikawa, Masanobu; Kosaka, Kenichi; Seki, Hirohumi; Kimoto, Tsunenobu

    2016-07-01

    We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET. © The Author(s) 2016.

  16. Semiconductor physics

    Böer, Karl W

    2018-01-01

    This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

  17. Nano-CMOS gate dielectric engineering

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  18. Study of CMOS micromachined self-oscillating loop utilizing a phase-locked loop-driving circuit

    Li, Hsin-Chih; Tseng, Sheng-Hsiang; Lu, Michael S.-C.; Huang, Po-Chiun

    2012-01-01

    This work describes the design and characterization of integrated CMOS (complementary metal oxide semiconductor) oscillators comprising a capacitively transduced micromechanical resonator and a phase-locked loop (PLL) driving circuit. Three oscillator schemes are studied and compared, including direct feedback, direct feedback containing a PLL and hybrid direct feedback plus a PLL. PLL is known for its capability in automatic tuning and tracking of a reference signal. Inclusion of a PLL is beneficial for sustaining oscillations at resonant frequencies within its capture range. The micromechanical resonator has a measured resonant frequency of 117.3 kHz. The CMOS PLL circuit has a closed-loop bandwidth of 1.8 kHz with a capture range between 111 kHz and 118.4 kHz. The start-up times for oscillation are shortened in the two schemes utilizing a PLL, since it provides an initial driving signal at its free-running frequency. The lock-in time is also reduced by increasing the proportion of PLL drive in the hybrid scheme. The measured noises for the three oscillator schemes are similar with a value of −75 dB below the resonant peak at a 10 Hz offset. (paper)

  19. Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

    Jong-Ryul Yang

    2016-03-01

    Full Text Available A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

  20. A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

    Sheng, Duo; Hong, Min-Rong

    2016-10-14

    This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

  1. Development of CMOS MEMS inductive type tactile sensor with the integration of chrome steel ball force interface

    Yeh, Sheng-Kai; Chang, Heng-Chung; Fang, Weileun

    2018-04-01

    This study presents an inductive tactile sensor with a chrome steel ball sensing interface based on the commercially available standard complementary metal-oxide-semiconductor (CMOS) process (the TSMC 0.18 µm 1P6M CMOS process). The tactile senor has a deformable polymer layer as the spring of the device and no fragile suspended thin film structures are required. As a tactile force is applied on the chrome steel ball, the polymer would deform. The distance between the chrome steel ball and the sensing coil would changed. Thus, the tactile force can be detected by the inductance change of the sensing coil. In short, the chrome steel ball acts as a tactile bump as well as the sensing interface. Experimental results show that the proposed inductive tactile sensor has a sensing range of 0-1.4 N with a sensitivity of 9.22(%/N) and nonlinearity of 2%. Preliminary wireless sensing test is also demonstrated. Moreover, the influence of the process and material issues on the sensor performances have also been investigated.

  2. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization.

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C; Patel, Tushita

    2015-11-01

    Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50-300 e-) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). In this study, imaging performance of a large area (29×23 cm2) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165-400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. The LFW mode shows better DQE at low air kerma (Ka<10 μGy) and should be used for DBT. At current DBT applications, air kerma (Ka∼10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165-400 μm in size can be resolved using a MGD range of 0.3-1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 mGy), an increased CNR (by ∼10) for

  3. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    Zhao, Chumin; Kanicki, Jerzy; Konstantinidis, Anastasios C.; Patel, Tushita

    2015-01-01

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e − ) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm 2 ) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K a < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K a ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at MGD of 2.5 m

  4. Large area CMOS active pixel sensor x-ray imager for digital breast tomosynthesis: Analysis, modeling, and characterization

    Zhao, Chumin; Kanicki, Jerzy, E-mail: kanicki@eecs.umich.edu [Solid-State Electronics Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109 (United States); Konstantinidis, Anastasios C. [Department of Medical Physics and Biomedical Engineering, University College London, London WC1E 6BT, United Kingdom and Diagnostic Radiology and Radiation Protection, Christie Medical Physics and Engineering, The Christie NHS Foundation Trust, Manchester M20 4BX (United Kingdom); Patel, Tushita [Department of Physics, University of Virginia, Charlottesville, Virginia 22908 (United States)

    2015-11-15

    Purpose: Large area x-ray imagers based on complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology have been proposed for various medical imaging applications including digital breast tomosynthesis (DBT). The low electronic noise (50–300 e{sup −}) of CMOS APS x-ray imagers provides a possible route to shrink the pixel pitch to smaller than 75 μm for microcalcification detection and possible reduction of the DBT mean glandular dose (MGD). Methods: In this study, imaging performance of a large area (29 × 23 cm{sup 2}) CMOS APS x-ray imager [Dexela 2923 MAM (PerkinElmer, London)] with a pixel pitch of 75 μm was characterized and modeled. The authors developed a cascaded system model for CMOS APS x-ray imagers using both a broadband x-ray radiation and monochromatic synchrotron radiation. The experimental data including modulation transfer function, noise power spectrum, and detective quantum efficiency (DQE) were theoretically described using the proposed cascaded system model with satisfactory consistency to experimental results. Both high full well and low full well (LFW) modes of the Dexela 2923 MAM CMOS APS x-ray imager were characterized and modeled. The cascaded system analysis results were further used to extract the contrast-to-noise ratio (CNR) for microcalcifications with sizes of 165–400 μm at various MGDs. The impact of electronic noise on CNR was also evaluated. Results: The LFW mode shows better DQE at low air kerma (K{sub a} < 10 μGy) and should be used for DBT. At current DBT applications, air kerma (K{sub a} ∼ 10 μGy, broadband radiation of 28 kVp), DQE of more than 0.7 and ∼0.3 was achieved using the LFW mode at spatial frequency of 0.5 line pairs per millimeter (lp/mm) and Nyquist frequency ∼6.7 lp/mm, respectively. It is shown that microcalcifications of 165–400 μm in size can be resolved using a MGD range of 0.3–1 mGy, respectively. In comparison to a General Electric GEN2 prototype DBT system (at

  5. Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

    Tseng, Sheng-Hsiang; Lu, Michael S-C; Wu, Po-Chang; Teng, Yu-Chen; Tsai, Hann-Huei; Juang, Ying-Zong

    2012-01-01

    This paper describes the design, fabrication and characterization of a complementary metal-oxide-semiconductor (CMOS) micro-electro-mechanical-system (MEMS) accelerometer implemented in a 0.18 µm multi-project wafer (MPW) CMOS MEMS process. In addition to the standard CMOS process, an additional aluminum layer and a thick photoresist masking layer are employed to achieve etching and microstructural release. The structural thickness of the accelerometer is up to 9 µm and the minimum structural spacing is 2.3 µm. The out-of-plane deflection resulted from the vertical stress gradient over the whole device is controlled to be under 0.2 µm. The chip area containing the micromechanical structure and switched-capacitor sensing circuit is 1.18 × 0.9 mm 2 , and the total power consumption is only 0.7 mW. Within the sensing range of ±6 G, the measured nonlinearity is 1.07% and the cross-axis sensitivities with respect to the in-plane and out-of-plane are 0.5% and 5.8%, respectively. The average sensitivity of five tested accelerometers is 191.4 mV G −1 with a standard deviation of 2.5 mV G −1 . The measured output noise floor is 354 µG Hz −1/2 , corresponding to a 100 Hz 1 G sinusoidal acceleration. The measured output offset voltage is about 100 mV at 27 °C, and the zero-G temperature coefficient of the accelerometer output is 0.94 mV °C −1 below 85 °C. (paper)

  6. A CMOS IC–based multisite measuring system for stimulation and recording in neural preparations in vitro

    Takashi eTateno

    2014-10-01

    Full Text Available In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS integrated circuit (IC chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 mm × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA, and a PC. To test the system, microelectrode arrays (MEAs were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μV root mean square (10 Hz to 100 kHz, which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μVpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

  7. Thread-Like CMOS Logic Circuits Enabled by Reel-Processed Single-Walled Carbon Nanotube Transistors via Selective Doping.

    Heo, Jae Sang; Kim, Taehoon; Ban, Seok-Gyu; Kim, Daesik; Lee, Jun Ho; Jur, Jesse S; Kim, Myung-Gil; Kim, Yong-Hoon; Hong, Yongtaek; Park, Sung Kyu

    2017-08-01

    The realization of large-area electronics with full integration of 1D thread-like devices may open up a new era for ultraflexible and human adaptable electronic systems because of their potential advantages in demonstrating scalable complex circuitry by a simply integrated weaving technology. More importantly, the thread-like fiber electronic devices can be achieved using a simple reel-to-reel process, which is strongly required for low-cost and scalable manufacturing technology. Here, high-performance reel-processed complementary metal-oxide-semiconductor (CMOS) integrated circuits are reported on 1D fiber substrates by using selectively chemical-doped single-walled carbon nanotube (SWCNT) transistors. With the introduction of selective n-type doping and a nonrelief photochemical patterning process, p- and n-type SWCNT transistors are successfully implemented on cylindrical fiber substrates under air ambient, enabling high-performance and reliable thread-like CMOS inverter circuits. In addition, it is noteworthy that the optimized reel-coating process can facilitate improvement in the arrangement of SWCNTs, building uniformly well-aligned SWCNT channels, and enhancement of the electrical performance of the devices. The p- and n-type SWCNT transistors exhibit field-effect mobility of 4.03 and 2.15 cm 2 V -1 s -1 , respectively, with relatively narrow distribution. Moreover, the SWCNT CMOS inverter circuits demonstrate a gain of 6.76 and relatively good dynamic operation at a supply voltage of 5.0 V. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  8. A CMOS Morlet Wavelet Generator

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  9. Comparison of modification strategies towards enhanced charge carrier separation and photocatalytic degradation activity of metal oxide semiconductors (TiO2, WO3 and ZnO)

    Kumar, S. Girish; Rao, K. S. R. Koteswara

    2017-01-01

    Metal oxide semiconductors (TiO2, WO3 and ZnO) finds unparalleled opportunity in wastewater purification under UV/visible light, largely encouraged by their divergent admirable features like stability, non-toxicity, ease of preparation, suitable band edge positions and facile generation of active oxygen species in the aqueous medium. However, the perennial failings of these photocatalysts emanates from the stumbling blocks like rapid charge carrier recombination and meager visible light response. In this review, tailoring the surface-bulk electronic structure through the calibrated and veritable approaches such as impurity doping, deposition with noble metals, sensitizing with other compounds (dyes, polymers, inorganic complexes and simple chelating ligands), hydrogenation process (annealing under hydrogen atmosphere), electronic integration with other semiconductors, modifying with carbon nanostructures, designing with exposed facets and tailoring with hierarchical morphologies to overcome their critical drawbacks are summarized. Taking into account the materials intrinsic properties, the pros and cons together with similarities and striking differences for each strategy in specific to TiO2, WO3 & ZnO are highlighted. These subtlety enunciates the primacy for improving the structure-electronic properties of metal oxides and credence to its fore in the practical applications. Future research must focus on comparing the performances of ZnO, TiO2 and WO3 in parallel to get insight into their photocatalytic behaviors. Such comparisons not only reveal the changed surface-electronic structure upon various modifications, but also shed light on charge carrier dynamics, free radical generation, structural stability and compatibility for photocatalytic reactions. It is envisioned that these cardinal tactics have profound implications and can be replicated to other semiconductor photocatalysts like CeO2, In2O3, Bi2O3, Fe2O3, BiVO4, AgX, BiOX (X = Cl, Br & I), Bi2WO6, Bi2MoO6

  10. Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

    McWilliams, B.M.; Herman, I.P.; Mitlitsky, F.; Hyde, R.A.; Wood, L.L.

    1983-01-01

    A complete set of processes sufficient for manufacture of n-metal-oxide-semiconductor (n-MOS) transistors by a laser-induced direct-write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n-doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1-μm and 1-μm-thick gate oxides were micromachined with and without etchant gas, and the exposed p-Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser-induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n-MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser-induced surface reactions that have not been reported previously

  11. Homostructured ZnO-based metal-oxide-semiconductor field-effect transistors deposited at low temperature by vapor cooling condensation system

    Lin, Tzu-Shun [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Lee, Ching-Ting, E-mail: ctlee@ee.ncku.edu.tw [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Institute of Microelectronics, Department of Electrical Engineering, Advanced Optoelectronic Technology Center, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China)

    2015-11-01

    Highlights: • The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors. • The resulting homostructured ZnO-based MOSFETs operated at a reverse voltage of −6 V had a very low gate leakage current of 24 nA. • The associated I{sub DSS} and the g{sub m(max)} were 5.64 mA/mm and 1.31 mS/mm, respectively. - Abstract: The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors (MOSFETs) on sapphire substrates. Owing to the high quality of the deposited, various ZnO films and interfaces, the resulting MOSFETs manifested attractive characteristics, such as the low gate leakage current of 24 nA, the low average interface state density of 2.92 × 10{sup 11} cm{sup −2} eV{sup −1}, and the complete pinch-off performance. The saturation drain–source current, the maximum transconductance, and the gate voltage swing of the resulting homostructured ZnO-based MOSFETs were 5.64 mA/mm, 1.31 mS/mm, and 3.2 V, respectively.

  12. High-speed nonvolatile CMOS/MNOS RAM

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  13. Semiconductor technology program. Progress briefs

    Bullis, W. M.

    1980-01-01

    Measurement technology for semiconductor materials, process control, and devices is reviewed. Activities include: optical linewidth and thermal resistance measurements; device modeling; dopant density profiles; resonance ionization spectroscopy; and deep level measurements. Standardized oxide charge terminology is also described.

  14. Modeling the dark current histogram induced by gold contamination in complementary-metal-oxide-semiconductor image sensors

    Domengie, F., E-mail: florian.domengie@st.com; Morin, P. [STMicroelectronics Crolles 2 (SAS), 850 Rue Jean Monnet, 38926 Crolles Cedex (France); Bauza, D. [CNRS, IMEP-LAHC - Grenoble INP, Minatec: 3, rue Parvis Louis Néel, CS 50257, 38016 Grenoble Cedex 1 (France)

    2015-07-14

    We propose a model for dark current induced by metallic contamination in a CMOS image sensor. Based on Shockley-Read-Hall kinetics, the expression of dark current proposed accounts for the electric field enhanced emission factor due to the Poole-Frenkel barrier lowering and phonon-assisted tunneling mechanisms. To that aim, we considered the distribution of the electric field magnitude and metal atoms in the depth of the pixel. Poisson statistics were used to estimate the random distribution of metal atoms in each pixel for a given contamination dose. Then, we performed a Monte-Carlo-based simulation for each pixel to set the number of metal atoms the pixel contained and the enhancement factor each atom underwent, and obtained a histogram of the number of pixels versus dark current for the full sensor. Excellent agreement with the dark current histogram measured on an ion-implanted gold-contaminated imager has been achieved, in particular, for the description of the distribution tails due to the pixel regions in which the contaminant atoms undergo a large electric field. The agreement remains very good when increasing the temperature by 15 °C. We demonstrated that the amplification of the dark current generated for the typical electric fields encountered in the CMOS image sensors, which depends on the nature of the metal contaminant, may become very large at high electric field. The electron and hole emissions and the resulting enhancement factor are described as a function of the trap characteristics, electric field, and temperature.

  15. Life-cycle assessment of semiconductors

    Boyd, Sarah B

    2012-01-01

    Life-Cycle Assessment of Semiconductors presents the first and thus far only available transparent and complete life cycle assessment of semiconductor devices. A lack of reliable semiconductor LCA data has been a major challenge to evaluation of the potential environmental benefits of information technologies (IT). The analysis and results presented in this book will allow a higher degree of confidence and certainty in decisions concerning the use of IT in efforts to reduce climate change and other environmental effects. Coverage includes but is not limited to semiconductor manufacturing trends by product type and geography, unique coverage of life-cycle assessment, with a focus on uncertainty and sensitivity analysis of energy and global warming missions for CMOS logic devices, life cycle assessment of flash memory and life cycle assessment of DRAM. The information and conclusions discussed here will be highly relevant and useful to individuals and institutions. The book also: Provides a detailed, complete a...

  16. Oxide Thin-Film Electronics using All-MXene Electrical Contacts

    Wang, Zhenwei

    2018-02-23

    2D MXenes have shown great promise in electrochemical and electromagnetic shielding applications. However, their potential use in electronic devices is significantly less explored. The unique combination of metallic conductivity and hydrophilic surface suggests that MXenes can also be promising in electronics and sensing applications. Here, it is shown that metallic Ti3C2 MXene with work function of 4.60 eV can make good electrical contact with both zinc oxide (ZnO) and tin monoxide (SnO) semiconductors, with negligible band offsets. Consequently, both n-type ZnO and p-type SnO thin-film transistors (TFTs) have been fabricated entirely using large-area MXene (Ti3C2) electrical contacts, including gate, source, and drain. The n- and p-type TFTs show balanced performance, including field-effect mobilities of 2.61 and 2.01 cm2 V−1 s−1 and switching ratios of 3.6 × 106 and 1.1 × 103, respectively. Further, complementary metal oxide semiconductor (CMOS) inverters are demonstrated. The CMOS inverters show large voltage gain of 80 and excellent noise margin of 3.54 V, which is 70.8% of the ideal value. Moreover, the operation of CMOS inverters is shown to be very stable under a 100 Hz square waveform input. The current results suggest that MXene (Ti3C2) can play an important role as contact material in nanoelectronics.

  17. NIOSH Field Studies Team Assessment: Worker Exposure to Aerosolized Metal Oxide Nanoparticles in a Semiconductor Fabrication Facility

    Brenner, Sara A.; Neu-Baker, Nicole M.; Eastlake, Adrienne C.; Beaucham, Catherine C.; Geraci, Charles L.

    2016-01-01

    The ubiquitous use of engineered nanomaterials – particulate materials measuring approximately 1–100 nanometers (nm) on their smallest axis, intentionally engineered to express novel properties – in semiconductor fabrication poses unique issues for protecting worker health and safety. Use of new substances or substances in a new form may present hazards that have yet to be characterized for their acute or chronic health effects. Uncharacterized or emerging occupational health hazards may exis...

  18. Properties of InGaAs/GaAs metal-oxide-semiconductor heterostructure field-effect transistors modified by surface treatment

    Gregušová, D., E-mail: Dagmar.Gregusova@savba.sk [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Gucmann, F.; Kúdela, R. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Mičušík, M. [Polymer Institute of Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84541 (Slovakia); Stoklas, R.; Válik, L. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Greguš, J. [Faculty of Mathematics, Physics and Informatics, Comenius University, Mlynská dolina, Bratislava SK-84248 (Slovakia); Blaho, M. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology STU, Ilkovičova 3, Bratislava SK-81219 (Slovakia)

    2017-02-15

    Highlights: • AlGaAs/InGaAs/GaAs-based metal oxide semiconductor transistors-MOSHFET. • Thin Al-layer deposited in-situ and oxidize in air – gate insulator. • MOSHFET vs HFET transistor properties, density of traps evaluated. - Abstract: GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10{sup 11} cm{sup −2} eV{sup −1}. Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs.

  19. A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

    Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

    2017-04-01

    The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

  20. Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

    Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

    2015-10-01

    In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

  1. Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

    Swain, Basudev, E-mail: Swain@iae.re.kr [Institute for Advanced Engineering (IAE), Advanced Materials & Processing Center, Yongin-Si 449-863 (Korea, Republic of); Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo [Institute for Advanced Engineering (IAE), Advanced Materials & Processing Center, Yongin-Si 449-863 (Korea, Republic of); Lee, Kun-Jae [Department of Energy Engineering, Dankook University, Cheonan 330-714 (Korea, Republic of)

    2015-07-15

    Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.

  2. Electrical characteristics of metal–insulator–semiconductor and ...

    Future CMOS technology nodes will require the introduc- tion of these alternative high-k ... (MISIM) structures with (100)-oriented p-type silicon as substrate. The oxide ... The analysis conducted is applicable to inversion-type transistors.

  3. CMOS Voltage-Controlled Oscillator Resilient Design for Wireless Communication Applications

    Ekavut Kritchanchai

    2015-08-01

    Full Text Available Semiconductor process variation and reliability aging effect on CMOS VCO performance has been studied. A technique to mitigate the effect of process variations on the performances of nano-scale CMOS LC-VCO is presented. The LC-VCO compensation uses a process invariant current source. VCO parameters such as phase noise and core power before and after compensation over a wide range of variability are examined. Analytical equations are derived for physical insight. ADS and Monte-Carlo simulation results show that the use of invariant current source improves the robustness of the VCO performance against process variations and device aging.

  4. Superconductivity in doped semiconductors

    Bustarret, E., E-mail: Etienne.bustarret@neel.cnrs.fr

    2015-07-15

    A historical survey of the main normal and superconducting state properties of several semiconductors doped into superconductivity is proposed. This class of materials includes selenides, tellurides, oxides and column-IV semiconductors. Most of the experimental data point to a weak coupling pairing mechanism, probably phonon-mediated in the case of diamond, but probably not in the case of strontium titanate, these being the most intensively studied materials over the last decade. Despite promising theoretical predictions based on a conventional mechanism, the occurrence of critical temperatures significantly higher than 10 K has not been yet verified. However, the class provides an enticing playground for testing theories and devices alike.

  5. Studies on surface structures and mechanism of photocatalytic action of semiconductor oxides; Handotai hikari shokubai no hyomen kozo seigyo to sayo kiko kaimei ni kansuru kenkyu

    Takeuchi, H; Sona, S; Koike, H; Hori, H; Negishi, N; Kohara, H; Ibusuki, A [National Institute for Resources and Environment, Tsukuba (Japan); Vakhtin, A; Borovkov, V [New Energy and Industrial Technology Development Organization, Tokyo, (Japan)

    1997-02-01

    Studies are made to define the working mechanism of semiconductor photocatalysts such as TiO2 and to establish designing guidelines for improving on their activity and functions. TiO2 in the air actively produces oxygen seeds for the oxidation and removal of NOx, etc. It is desired that a catalyst have a specific surface area large enough to retain the product of its action. To meet the need, a thin-film photocatalyst which is an aggregate of TiO2 crystals is produced by burning a film of a sol/gel system of reaction doped with macromolecules. This product has a larger specific surface area and is higher in pollutant-removing performance, and may be put into practical use. In another experiment, metal-carrying particles TiO2 suspended in water are employed for the reduction of CO2. Though the main product of catalysts carrying Pt or Pd is methane, a photocatalyst carrying RuO2 produces acetic acid mainly and loses less activity with the passage of time. A hybrid photocatalyst is composed of an organic pigment and inorganic semiconductor, synthesized through a covalent bond between a sililated-surface thin TiO2 film and porphyrin. It is confirmed that the newly developed process brings about an increase in electron migration efficiency. 3 figs.

  6. Spectroscopic Studies of Semiconductor Materials for Aggressive-scaled Micro- and Opto-electronic Devices: nc-SiO2, GeO2; ng-Si, Ge and ng-Transition metal (TM) oxides

    Cheng, Cheng

    Non-crystalline thin film materials are widely used in the semiconductor industry (micro- and optoelectronics) and in green energy, e.g., photovolatic applications. This dissertation under-pins these device application with studies of their electronic structures using derivative X-ray Absorption Spectroscopy (XAS) and derivative Spectroscopic Ellipsometry (SE) for the first time to experimentally determine electronic and intrinsic defect structures. Differences between electron and hole mobilities in c- (and ng-Si) and c- (and ng- Ge), make Ge channels superior to Si channels in for aggressively scaled CMOS field effect transistors (FETs). Bonding between Si and Ge substrates and gate dielectric oxides is the focus this dissertation. The primary objective of this research is to measure and interpret by ab-initio theory the electronic and intrinsic electronic defect structures mirco-electronic thin film materials. This is accomplished for the first time by combining (i) derivative XAS TEY data obtained at the Stanford Synchrotron Radiation Light Source (SSRL) with (ii) derivative Spectroscopic Ellipsometry results obtained at the J.A. Woollam Co. laboratory. All the oxides were deposited in RPECVD system with in-line AES and RHEED. Thins films and gate stacks were annealed in RTA system in Ar to determine temperature dependent changes. 2nd derivative analysis is applied on XAS and SE spectra emphasizing the conduction band (CB) and virtual bound state (VBS) regimes. 2nd derivative SE spectra for ng-Si and ng-Ge each have 3 distinct regimes: (i) 3 excitons, (ii) 2 features in the CB edge region, and (iii) 3 additional exciton features above the IP. Excitonic spectral width provides conductivity electron masses (em0*) and hence electron mobilities. The wider the energy range, the higher the electron mobility in that CB. Spectra of high-K dielectrics have an additional energy regime between the CB edge regime, and the higher eV excitons. This regime has 4 intra-d state

  7. E-Beam Effects on CMOS Active Pixel Sensors

    Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

    2011-01-01

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  8. 5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

    2013-01-01

    The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

  9. A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

    Ming-Zhi Yang

    2013-03-01

    Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

  10. Characterization of a fully resonant, 1-MHz, 25-watt, DC/DC converter fabricated in a rad-hard BiCMOS/high-voltage process

    Titus, J.L.; Gehlhausen, M.A.; Desko, J.C. Jr.; Nguyen, T.T.; Roberts, D.J.; Shibib, M.A.; Hollenbach, K.E.

    1995-01-01

    This paper presents the characterization of a DC/DC converter prototype when its power integrated circuit (PIC) chip is exposed to total dose, dose rate, neutron, and heavy ion environments. This fully resonant, 1-MHZ, 25-Watt, DC/DC converter is composed of a brassboard, populated with input/output filters, isolation transformers, output rectifier, capacitors, resistors, and PIC chip, integrating the primary-side control circuitry, secondary-side control circuitry, power switch, gate-drive circuitry, and voltage references. The brassboard is built using commercial off-the-shelf components; and the PIC chip is fabricated using AT and T's rad-hard, bipolar complementary metal-oxide semiconductor (BiCMOS)/high-voltage process. The intent of this paper is to demonstrate that the PIC chip is fabricated with a radiation-hardened process and to demonstrate that various analog, digital, and power functions can be effectively integrated

  11. Synthesis and characterization of three-dimensional transition metal ions doped zinc oxide based dilute magnetic semiconductor thin films

    Samanta, Kousik

    Dilute magnetic semiconductors (DMS), especially 3d-transition metal (TM) doped ZnO based DMS materials are the most promising candidates for optoelectronics and spintronics applications; e.g. in spin light emitting diode (SLED), spin transistors, and spin field effect transistors (SFET), etc. In the present dissertation, thin films of Zn1-xTMxO (TM = Co2+, Cu2+, and Mn2+) were grown on (0001) oriented Al2O3 substrates by pulsed laser deposition (PLD) technique. The films were highly c-axis oriented, nearly single crystalline, and defects free for a limited concentration of the dilution of transition metal ions. In particular, we have obtained single crystalline phases of Zn1-xTMxO thin films for up to 10, 3, and 5 stoichiometric percentages of Co2+, Cu2+, and Mn2+ respectively. Raman micro-probe system was used to understand the structural and lattice dynamical properties at different physical conditions. The confinement of optical phonons in the disorder lattice was explained by alloy potential fluctuation (APF) using a spatial correlation (SC) model. The detailed analysis of the optical phonon behavior in disorder lattice confirmed the substitution of the transition metal ions in Zn 2+ site of the ZnO host lattice. The secondary phases of ZnCo 2O4, CuO, and ZnMn2O4 were detected in higher Co, Cu, and Mn doped ZnO thin films respectively; where as, XRD did not detect these secondary phases in the same samples. Room temperature ferromagnetism was observed in Co2+ and Cu2+ ions doped ZnO thin films with maximum saturation magnetization (Ms) of 1.0 and 0.76 muB respectively. The origin of the observed ferromagnetism in Zn1-xCoxO thin films was tested by the controlled introduction of shallow donors (Al) in Zn0.9-x Co0.1O:Alx (x = 0.005 and 0.01) thin films. The saturation magnetization for the 10% Co-doped ZnO (1.0 muB /Co) at 300K reduced (˜0.25 muB/Co) due to Al doping. The observed ferromagnetism and the reduction due to Al doping can be explained by the Bound

  12. Thin film transistor performance of amorphous indium–zinc oxide semiconductor thin film prepared by ultraviolet photoassisted sol–gel processing

    Kodzasa, Takehito; Nobeshima, Taiki; Kuribara, Kazunori; Yoshida, Manabu

    2018-05-01

    We have fabricated an amorphous indium–zinc oxide (IZO, In/Zn = 3/1) semiconductor thin-film transistor (AOS-TFT) by the sol–gel technique using ultraviolet (UV) photoirradiation and post-treatment in high-pressure O2 at 200 °C. The obtained TFT showed a hole carrier mobility of 0.02 cm2 V‑1 s‑1 and an on/off current ratio of 106. UV photoirradiation leads to the decomposition of the organic agents and hydroxide group in the IZO gel film. Furthermore, the post-treatment annealing at a high O2 pressure of more than 0.6 MPa leads to the filling of the oxygen vacancies in a poor metal–oxygen network in the IZO film.

  13. Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

    Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

    2007-05-01

    Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

  14. A Wide-Range Tunable Level-Keeper Using Vertical Metal-Oxide-Semiconductor Field-Effect Transistors for Current-Reuse Systems

    Tanoi, Satoru; Endoh, Tetsuo

    2012-04-01

    A wide-range tunable level-keeper using vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed for current-reuse analog systems. The design keys for widening tunable range of the operation are a two-path feed-back and a vertical MOSFET with back-bias-effect free. The proposed circuit with the vertical MOSFETs shows the 1.23-V tunable-range of the input level with the 2.4-V internal-supply voltage (VDD) in the simulation. This tunable-range of the proposed circuit is 4.7 times wider than that of the conventional. The achieved current efficiency of the proposed level-keeper is 66% at the 1.2-V output with the 2.4-V VDD. This efficiency of the proposed circuit is twice higher than that of the traditional voltage down converter.

  15. Non-Stoichiometric SixN Metal-Oxide-Semiconductor Field-Effect Transistor for Compact Random Number Generator with 0.3 Mbit/s Generation Rate

    Matsumoto, Mari; Ohba, Ryuji; Yasuda, Shin-ichi; Uchida, Ken; Tanamoto, Tetsufumi; Fujita, Shinobu

    2008-08-01

    The demand for random numbers for security applications is increasing. A conventional random number generator using thermal noise can generate unpredictable high-quality random numbers, but the circuit is extremely large because of large amplifier circuit for a small thermal signal. On the other hand, a pseudo-random number generator is small but the quality of randomness is bad. For a small circuit and a high quality of randomness, we purpose a non-stoichiometric SixN metal-oxide-semiconductor field-effect transistor (MOSFET) noise source device. This device generates a very large noise signal without an amplifier circuit. As a result, it is shown that, utilizing a SiN MOSFET, we can attain a compact random number generator with a high generation rate near 1 Mbit/s, which is suitable for almost all security applications.

  16. A comparison of ionizing radiation and high field stress effects in n-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors

    Park, Mun-Soo; Na, Inmook; Wie, Chu R.

    2005-01-01

    n-channel power vertical double-diffused metal-oxide-semiconductor field-effect-transistor (VDMOSFET) devices were subjected to a high electric field stress or to a x-ray radiation. The current-voltage and capacitance-voltage measurements show that the channel-side interface and the drain-side interface are affected differently in the case of high electric field stress, whereas the interfaces are nearly uniformly affected in the case of x-ray radiation. This paper also shows that for the gated diode structure of VDMOSFET, the direct-current current-voltage technique measures only the drain-side interface; the subthreshold current-voltage technique measures only the channel-side interface; and the capacitance-voltage technique measures both interfaces simultaneously and clearly distinguishes the two interfaces. The capacitance-voltage technique is suggested to be a good quantitative method to examine both interface regions by a single measurement

  17. Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

    Pang Liang; Kim, Kyekyoon

    2012-01-01

    A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO 2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO 2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10 -9 A mm -1 and high breakdown voltage of 634 V for a gate-drain distance of 6 µm, demonstrating the promise of bimodal-SiO 2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application. (paper)

  18. Temperature Dependent Electrical Transport in Al/Poly(4-vinyl phenol/p-GaAs Metal-Oxide-Semiconductor by Sol-Gel Spin Coating Method

    Şadan Özden

    2016-01-01

    Full Text Available Deposition of poly(4-vinyl phenol insulator layer is carried out by applying the spin coating technique onto p-type GaAs substrate so as to create Al/poly(4-vinyl phenol/p-GaAs metal-oxide-semiconductor (MOS structure. Temperature was set to 80–320 K while the current-voltage (I-V characteristics of the structure were examined in the study. Ideality factor (n and barrier height (ϕb values found in the experiment ranged from 3.13 and 0.616 eV (320 K to 11.56 and 0.147 eV (80 K. Comparing the thermionic field emission theory and thermionic emission theory, the temperature dependent ideality factor behavior displayed that thermionic field emission theory is more valid than the latter. The calculated tunneling energy was 96 meV.

  19. Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

    Djara, V.; Cherkaoui, K.; Negara, M. A.; Hurley, P. K., E-mail: paul.hurley@tyndall.ie [Tyndall National Institute, University College Cork, Dyke Parade, Cork (Ireland)

    2015-11-28

    An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N{sub inv}) from the trapped charge density in high-k/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I{sub d}-V{sub g} measurements enabled an accurate effective mobility vs N{sub inv} extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs.

  20. Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

    Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

    2018-01-01

    The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.