Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

Science.gov (United States)

McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

2000-01-01

A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

Energy Technology Data Exchange (ETDEWEB)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji-Won; Rondinone, Adam Justin; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2017-09-19

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component comprising at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles

Science.gov (United States)

Phelps, Tommy J.; Lauf, Robert J.; Moon, Ji Won; Rondinone, Adam J.; Love, Lonnie J.; Duty, Chad Edward; Madden, Andrew Stephen; Li, Yiliang; Ivanov, Ilia N.; Rawn, Claudia Jeanette

2014-06-24

The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction components to conditions conducive to microbially-mediated formation of non-oxide semiconductor nanoparticles, wherein said combination of reaction components comprises i) anaerobic microbes, ii) a culture medium suitable for sustaining said anaerobic microbes, iii) a metal component comprising at least one type of metal ion, iv) a non-metal component containing at least one non-metal selected from the group consisting of S, Se, Te, and As, and v) one or more electron donors that provide donatable electrons to said anaerobic microbes during consumption of the electron donor by said anaerobic microbes; and (b) isolating said non-oxide semiconductor nanoparticles, which contain at least one of said metal ions and at least one of said non-metals. The invention is also directed to non-oxide semiconductor nanoparticle compositions produced as above and having distinctive properties.

Dual passivation of intrinsic defects at the compound semiconductor/oxide interface using an oxidant and a reductant.

Science.gov (United States)

Kent, Tyler; Chagarov, Evgeniy; Edmonds, Mary; Droopad, Ravi; Kummel, Andrew C

2015-05-26

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

Semiconductor photocatalysts for water oxidation: current status and challenges.

Science.gov (United States)

Yang, Lingling; Zhou, Han; Fan, Tongxiang; Zhang, Di

2014-04-21

Artificial photosynthesis is a highly-promising strategy to convert solar energy into hydrogen energy for the relief of the global energy crisis. Water oxidation is the bottleneck for its kinetic and energetic complexity in the further enhancement of the overall efficiency of the artificial photosystem. Developing efficient and cost-effective photocatalysts for water oxidation is a growing desire, and semiconductor photocatalysts have recently attracted more attention due to their stability and simplicity. This article reviews the recent advancement of semiconductor photocatalysts with a focus on the relationship between material optimization and water oxidation efficiency. A brief introduction to artificial photosynthesis and water oxidation is given first, followed by an explanation of the basic rules and mechanisms of semiconductor particulate photocatalysts for water oxidation as theoretical references for discussions of componential, surface structure, and crystal structure modification. O2-evolving photocatalysts in Z-scheme systems are also introduced to demonstrate practical applications of water oxidation photocatalysts in artificial photosystems. The final part proposes some challenges based on the dynamics and energetics of photoholes which are fundamental to the enhancement of water oxidation efficiency, as well as on the simulation of natural water oxidation that will be a trend in future research.

Metal oxide semiconductor thin-film transistors for flexible electronics

Energy Technology Data Exchange (ETDEWEB)

Petti, Luisa; Vogt, Christian; Büthe, Lars; Cantarella, Giuseppe; Tröster, Gerhard [Electronics Laboratory, Swiss Federal Institute of Technology, Zürich (Switzerland); Münzenrieder, Niko [Electronics Laboratory, Swiss Federal Institute of Technology, Zürich (Switzerland); Sensor Technology Research Centre, University of Sussex, Falmer (United Kingdom); Faber, Hendrik; Bottacchi, Francesca; Anthopoulos, Thomas D. [Department of Physics and Centre for Plastic Electronics, Imperial College London, London (United Kingdom)

2016-06-15

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In

Plastic lab-on-a-chip for fluorescence excitation with integrated organic semiconductor lasers.

Science.gov (United States)

Vannahme, Christoph; Klinkhammer, Sönke; Lemmer, Uli; Mappes, Timo

2011-04-25

Laser light excitation of fluorescent markers offers highly sensitive and specific analysis for bio-medical or chemical analysis. To profit from these advantages for applications in the field or at the point-of-care, a plastic lab-on-a-chip with integrated organic semiconductor lasers is presented here. First order distributed feedback lasers based on the organic semiconductor tris(8-hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2-methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM), deep ultraviolet induced waveguides, and a nanostructured microfluidic channel are integrated into a poly(methyl methacrylate) (PMMA) substrate. A simple and parallel fabrication process is used comprising thermal imprint, DUV exposure, evaporation of the laser material, and sealing by thermal bonding. The excitation of two fluorescent marker model systems including labeled antibodies with light emitted by integrated lasers is demonstrated.

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

Directory of Open Access Journals (Sweden)

Ching-Liang Dai

2010-03-01

Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

A contact-lens-shaped IC chip technology

International Nuclear Information System (INIS)

Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

2014-01-01

We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

Directory of Open Access Journals (Sweden)

Shantonu Biswas

2016-03-01

Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

Electro-mechanical coupling of semiconductor film grown on stainless steel by oxidation

Science.gov (United States)

Lin, M. C.; Wang, G.; Guo, L. Q.; Qiao, L. J.; Volinsky, Alex A.

2013-09-01

Electro-mechanical coupling phenomenon in oxidation film on stainless steel has been discovered by using current-sensing atomic force microscopy, along with the I-V curves measurements. The oxidation films exhibit either ohmic, n-type, or p-type semiconductor properties, according to the obtained I-V curves. This technique allows characterizing oxidation films with high spatial resolution. Semiconductor properties of oxidation films must be considered as additional stress corrosion cracking mechanisms.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

Directory of Open Access Journals (Sweden)

Paul C. McIntyre

2012-07-01

Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

Science.gov (United States)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

Semiconductors: Still a Wide Open Frontier for Scientists/Engineers

Science.gov (United States)

Seiler, David G.

1997-10-01

A 1995 Business Week article described several features of the explosive use of semiconductor chips today: ``Booming'' personal computer markets are driving high demand for microprocessors and memory chips; (2) New information superhighway markets will `ignite' sales of multimedia and communication chips; and (3) Demand for digital-signal-processing and data-compression chips, which speed up video and graphics, is `red hot.' A Washington Post article by Stan Hinden said that technology is creating an unstoppable demand for electronic elements. This ``digital pervasiveness'' means that a semiconductor chip is going into almost every high-tech product that people buy - cars, televisions, video recorders, telephones, radios, alarm clocks, coffee pots, etc. ``Semiconductors are everywhere.'' Silicon and compound semiconductors are absolutely essential and are pervasive enablers for DoD operations and systems. DoD's Critical Technologies Plan of 1991 says that ``Semiconductor materials and microelectronics are critically important and appropriately lead the list of critical defense technologies.'' These trends continue unabated. This talk describes some of the frontiers of semiconductors today and shows how scientists and engineers can effectively contribute to its advancement. Cooperative, multidisciplinary efforts are increasing. Specific examples will be given for scanning capacitance microscopy and thin-film metrology.

Multifunctional Organic-Semiconductor Interfacial Layers for Solution-Processed Oxide-Semiconductor Thin-Film Transistor.

Science.gov (United States)

Kwon, Guhyun; Kim, Keetae; Choi, Byung Doo; Roh, Jeongkyun; Lee, Changhee; Noh, Yong-Young; Seo, SungYong; Kim, Myung-Gil; Kim, Choongik

2017-06-01

The stabilization and control of the electrical properties in solution-processed amorphous-oxide semiconductors (AOSs) is crucial for the realization of cost-effective, high-performance, large-area electronics. In particular, impurity diffusion, electrical instability, and the lack of a general substitutional doping strategy for the active layer hinder the industrial implementation of copper electrodes and the fine tuning of the electrical parameters of AOS-based thin-film transistors (TFTs). In this study, the authors employ a multifunctional organic-semiconductor (OSC) interlayer as a solution-processed thin-film passivation layer and a charge-transfer dopant. As an electrically active impurity blocking layer, the OSC interlayer enhances the electrical stability of AOS TFTs by suppressing the adsorption of environmental gas species and copper-ion diffusion. Moreover, charge transfer between the organic interlayer and the AOS allows the fine tuning of the electrical properties and the passivation of the electrical defects in the AOS TFTs. The development of a multifunctional solution-processed organic interlayer enables the production of low-cost, high-performance oxide semiconductor-based circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

On-chip digital power supply control for system-on-chip applications

NARCIS (Netherlands)

Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

2005-01-01

The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

Optical and Electric Multifunctional CMOS Image Sensors for On-Chip Biosensing Applications

Directory of Open Access Journals (Sweden)

Kiyotaka Sasagawa

2010-12-01

Full Text Available In this review, the concept, design, performance, and a functional demonstration of multifunctional complementary metal-oxide-semiconductor (CMOS image sensors dedicated to on-chip biosensing applications are described. We developed a sensor architecture that allows flexible configuration of a sensing pixel array consisting of optical and electric sensing pixels, and designed multifunctional CMOS image sensors that can sense light intensity and electric potential or apply a voltage to an on-chip measurement target. We describe the sensors’ architecture on the basis of the type of electric measurement or imaging functionalities.

Review of recent developments in amorphous oxide semiconductor thin-film transistor devices

International Nuclear Information System (INIS)

Park, Joon Seok; Maeng, Wan-Joo; Kim, Hyun-Suk; Park, Jin-Seong

2012-01-01

The present article is a review of the recent progress and major trends in the field of thin-film transistor (TFT) research involving the use of amorphous oxide semiconductors (AOS). First, an overview is provided on how electrical performance may be enhanced by the adoption of specific device structures and process schemes, the combination of various oxide semiconductor materials, and the appropriate selection of gate dielectrics and electrode metals in contact with the semiconductor. As metal oxide TFT devices are excellent candidates for switching or driving transistors in next generation active matrix liquid crystal displays (AMLCD) or active matrix organic light emitting diode (AMOLED) displays, the major parameters of interest in the electrical characteristics involve the field effect mobility (μ FE ), threshold voltage (V th ), and subthreshold swing (SS). A study of the stability of amorphous oxide TFT devices is presented next. Switching or driving transistors in AMLCD or AMOLED displays inevitably involves voltage bias or constant current stress upon prolonged operation, and in this regard many research groups have examined and proposed device degradation mechanisms under various stress conditions. The most recent studies involve stress experiments in the presence of visible light irradiating the semiconductor, and different degradation mechanisms have been proposed with respect to photon radiation. The last part of this review consists of a description of methods other than conventional vacuum deposition techniques regarding the formation of oxide semiconductor films, along with some potential application fields including flexible displays and information storage.

A study on oxidation treatment of uranium metal chip under controlling atmosphere for safe storage

International Nuclear Information System (INIS)

Kim, Chang Kyu; Ji, Chul Goo; Bae, Sang Oh; Woo, Yoon Myeoung; Kim, Jong Goo; Ha, Yeong Keong

2011-01-01

The U metal chips generated in developing nuclear fuel and a gamma radioisotope shield have been stored under immersion of water in KAERI. When the water of the storing vessels vaporizes or drains due to unexpected leaking, the U metal chips are able to open to air. A new oxidation treatment process was raised for a long time safe storage with concepts of drying under vacuum, evaporating the containing water and organic material with elevating temperature, and oxidizing the uranium metal chips at an appropriate high temperature under conditions of controlling the feeding rate of oxygen gas. In order to optimize the oxidation process the uranium metal chips were completely dried at higher temperature than 300 .deg. C and tested for oxidation at various temperatures, which are 300 .deg. C, 400 .deg. C, and 500 .deg. C. When the oxidation temperature was 400 .deg. C, the oxidized sample for 7 hours showed a temperature rise of 60 .deg. C in the self-ignition test. But the oxidized sample for 14 hours revealed a slight temperature rise of 7 .deg. C representing a stable behavior in the self-ignition test. When the temperature was 500 .deg. C, the shorter oxidation for 7 hours appeared to be enough because the self-ignition test represented no temperature rise. By using several chemical analyses such as carbon content determination, X-ray deflection (XRD), Infrared spectra (IR) and Thermal gravimetric analysis (TGA) on the oxidation treated samples, the results of self-ignition test of new oxidation treatment process for U metal chip were interpreted and supported

Electron Band Alignment at Interfaces of Semiconductors with Insulating Oxides: An Internal Photoemission Study

Directory of Open Access Journals (Sweden)

Valeri V. Afanas'ev

2014-01-01

Full Text Available Evolution of the electron energy band alignment at interfaces between different semiconductors and wide-gap oxide insulators is examined using the internal photoemission spectroscopy, which is based on observations of optically-induced electron (or hole transitions across the semiconductor/insulator barrier. Interfaces of various semiconductors ranging from the conventional silicon to the high-mobility Ge-based (Ge, Si1-xGex, Ge1-xSnx and AIIIBV group (GaAs, InxGa1-xAs, InAs, GaP, InP, GaSb, InSb materials were studied revealing several general trends in the evolution of band offsets. It is found that in the oxides of metals with cation radii larger than ≈0.7 Å, the oxide valence band top remains nearly at the same energy (±0.2 eV irrespective of the cation sort. Using this result, it becomes possible to predict the interface band alignment between oxides and semiconductors as well as between dissimilar insulating oxides on the basis of the oxide bandgap width which are also affected by crystallization. By contrast, oxides of light elements, for example, Be, Mg, Al, Si, and Sc exhibit significant shifts of the valence band top. General trends in band lineup variations caused by a change in the composition of semiconductor photoemission material are also revealed.

Synthesis, Characterization, and Ultrafast Dynamics of Metal, Metal Oxide, and Semiconductor Nanomaterials

OpenAIRE

Wheeler, Damon Andreas

2013-01-01

SYNTHESIS, CHARACTERIZATION, AND ULTRAFAST DYNAMICS OF METAL, METAL OXIDE, AND SEMICONDUCTOR NANOMATERIALSABSTRACTThe optical properties of each of the three main classes of inorganic nanomaterials, metals, metal oxides, and semiconductors differ greatly due to the intrinsically different nature of the materials. These optical properties are among the most fascinating and useful aspects of nanomaterials with applications spanning cancer treatment, sensors, lasers, and solar cells. One techn...

Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

International Nuclear Information System (INIS)

Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

2013-01-01

A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

Positron studies of metal-oxide-semiconductor structures

Science.gov (United States)

Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-03-01

Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

A Customized Metal Oxide Semiconductor-Based Gas Sensor Array for Onion Quality Evaluation: System Development and Characterization

Directory of Open Access Journals (Sweden)

Tharun Konduru

2015-01-01

Full Text Available A gas sensor array, consisting of seven Metal Oxide Semiconductor (MOS sensors that are sensitive to a wide range of organic volatile compounds was developed to detect rotten onions during storage. These MOS sensors were enclosed in a specially designed Teflon chamber equipped with a gas delivery system to pump volatiles from the onion samples into the chamber. The electronic circuit mainly comprised a microcontroller, non-volatile memory chip, and trickle-charge real time clock chip, serial communication chip, and parallel LCD panel. User preferences are communicated with the on-board microcontroller through a graphical user interface developed using LabVIEW. The developed gas sensor array was characterized and the discrimination potential was tested by exposing it to three different concentrations of acetone (ketone, acetonitrile (nitrile, ethyl acetate (ester, and ethanol (alcohol. The gas sensor array could differentiate the four chemicals of same concentrations and different concentrations within the chemical with significant difference. Experiment results also showed that the system was able to discriminate two concentrations (196 and 1964 ppm of methlypropyl sulfide and two concentrations (145 and 1452 ppm of 2-nonanone, two key volatile compounds emitted by rotten onions. As a proof of concept, the gas sensor array was able to achieve 89% correct classification of sour skin infected onions. The customized low-cost gas sensor array could be a useful tool to detect onion postharvest diseases in storage.

Radiation-induced effects on the XAA1.2 ASIC chip for space application

Energy Technology Data Exchange (ETDEWEB)

Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

2005-02-11

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

Radiation-induced effects on the XAA1.2 ASIC chip for space application

International Nuclear Information System (INIS)

Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

2005-01-01

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

High performance high-κ/metal gate complementary metal oxide semiconductor circuit element on flexible silicon

KAUST Repository

Sevilla, Galo T.

2016-02-29

Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.

Where science fiction meets reality? With oxide semiconductors.

Energy Technology Data Exchange (ETDEWEB)

Fortunato, E.; Martins, R. [CENIMAT/I3N, Departamento de Ciencia dos Materiais, Faculdade de Ciencias e Tecnologia, FCT, Universidade Nova de Lisboa, CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

2011-09-15

Transparent electronics is today one of the most advanced topics for a wide range of device applications, where the key components are wide band gap semiconductors, where oxides of different origin play an important role, not only as passive components but also as active components similar to what we observe in conventional semiconductors. As passive components they include the use of these materials as dielectrics for a wide range of electronic devices and also as transparent electrical conductors for use in several optoelectronic applications, such as liquid crystal displays, organic light emitting diodes, solar cells, optical sensors etc. As active materials, they exploit the use of truly electronic semiconductors where the main emphasis is being put on transparent thin film transistors, light emitting diodes, lasers, ultraviolet sensors and integrated circuits among others. (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Metal/oxide/semiconductor interface investigated by monoenergetic positrons

Science.gov (United States)

Uedono, A.; Tanigawa, S.; Ohji, Y.

1988-10-01

Variable-energy positron-beam studies have been carried out for the first time on a metal/oxide/semiconductor (MOS) structure of polycrystalline Si/SiO 2/Si-substrate. We were successful in collecting injected positrons at the SiO 2/Si interface by the application of an electric field between the MOS electrodes.

K-band single-chip electron spin resonance detector.

Science.gov (United States)

Anders, Jens; Angerhofer, Alexander; Boero, Giovanni

2012-04-01

We report on the design, fabrication, and characterization of an integrated detector for electron spin resonance spectroscopy operating at 27 GHz. The microsystem, consisting of an LC-oscillator and a frequency division module, is integrated onto a single silicon chip using a conventional complementary metal-oxide-semiconductor technology. The achieved room temperature spin sensitivity is about 10(8)spins/G Hz(1/2), with a sensitive volume of about (100 μm)(3). Operation at 77K is also demonstrated. Copyright © 2012 Elsevier Inc. All rights reserved.

Semiconductor

International Nuclear Information System (INIS)

2000-01-01

This book deals with process and measurement of semiconductor. It contains 20 chapters, which goes as follows; semiconductor industry, introduction of semiconductor manufacturing, yield of semiconductor process, materials, crystal growth and a wafer forming, PN, control pollution, oxidation, photomasking photoresist chemistry, photomasking technologies, diffusion and ion injection, chemical vapor deposition, metallization, wafer test and way of evaluation, semiconductor elements, integrated circuit and semiconductor circuit technology.

Oxide semiconductors

CERN Document Server

Svensson, Bengt G; Jagadish, Chennupati

2013-01-01

Semiconductors and Semimetals has distinguished itself through the careful selection of well-known authors, editors, and contributors. Originally widely known as the ""Willardson and Beer"" Series, it has succeeded in publishing numerous landmark volumes and chapters. The series publishes timely, highly relevant volumes intended for long-term impact and reflecting the truly interdisciplinary nature of the field. The volumes in Semiconductors and Semimetals have been and will continue to be of great interest to physicists, chemists, materials scientists, and device engineers in academia, scient

Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

Science.gov (United States)

Kao, Wei-Chieh

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

Simulation of the selective oxidation process of semiconductors

International Nuclear Information System (INIS)

Chahoud, M.

2012-01-01

A new approach to simulate the selective oxidation of semiconductors is presented. This approach is based on the so-called b lack box simulation method . This method is usually used to simulate complex processes. The chemical and physical details within the process are not considered. Only the input and output data of the process are relevant for the simulation. A virtual function linking the input and output data has to be found. In the case of selective oxidation the input data are the mask geometry and the oxidation duration whereas the output data are the oxidation thickness distribution. The virtual function is determined as four virtual diffusion processes between the masked und non-masked areas. Each process delivers one part of the oxidation profile. The method is applied successfully on the oxidation system silicon-silicon nitride (Si-Si 3 N 4 ). The fitting parameters are determined through comparison of experimental and simulation results two-dimensionally.(author)

Conductivity in transparent oxide semiconductors.

Science.gov (United States)

King, P D C; Veal, T D

2011-08-24

Despite an extensive research effort for over 60 years, an understanding of the origins of conductivity in wide band gap transparent conducting oxide (TCO) semiconductors remains elusive. While TCOs have already found widespread use in device applications requiring a transparent contact, there are currently enormous efforts to (i) increase the conductivity of existing materials, (ii) identify suitable alternatives, and (iii) attempt to gain semiconductor-engineering levels of control over their carrier density, essential for the incorporation of TCOs into a new generation of multifunctional transparent electronic devices. These efforts, however, are dependent on a microscopic identification of the defects and impurities leading to the high unintentional carrier densities present in these materials. Here, we review recent developments towards such an understanding. While oxygen vacancies are commonly assumed to be the source of the conductivity, there is increasing evidence that this is not a sufficient mechanism to explain the total measured carrier concentrations. In fact, many studies suggest that oxygen vacancies are deep, rather than shallow, donors, and their abundance in as-grown material is also debated. We discuss other potential contributions to the conductivity in TCOs, including other native defects, their complexes, and in particular hydrogen impurities. Convincing theoretical and experimental evidence is presented for the donor nature of hydrogen across a range of TCO materials, and while its stability and the role of interstitial versus substitutional species are still somewhat open questions, it is one of the leading contenders for yielding unintentional conductivity in TCOs. We also review recent work indicating that the surfaces of TCOs can support very high carrier densities, opposite to the case for conventional semiconductors. In thin-film materials/devices and, in particular, nanostructures, the surface can have a large impact on the total

Testing of modern semiconductor memory structures

NARCIS (Netherlands)

Gaydadjiev, G.N.

2007-01-01

In this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application

α-particle shielding of semiconductor device

International Nuclear Information System (INIS)

McKeown, P.J.A.; Perry, J.P.; Waddell, J.M.; Barker, K.D.

1981-01-01

Soft errors in semiconductor devices, e.g. random access memories, arising from the bombardment of the device by alpha particles produced by the disintegration of minute traces of uranium or thorium in the packaging materials are prevented by coating the active surface of the semiconductor chip with a thin layer, e.g. 20 to 100 microns of an organic polymeric material, this layer being of sufficient thickness to absorb the particles. Typically, the polymer is a poly-imide formed by u.v. electron-beam or thermal curing of liquid monomer applied to the chip surface. (author)

Atomic layer deposition of perovskite oxides and their epitaxial integration with Si, Ge, and other semiconductors

Energy Technology Data Exchange (ETDEWEB)

McDaniel, Martin D.; Ngo, Thong Q.; Hu, Shen; Ekerdt, John G., E-mail: ekerdt@utexas.edu [Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Posadas, Agham; Demkov, Alexander A. [Department of Physics, The University of Texas at Austin, Austin, Texas 78712 (United States)

2015-12-15

Atomic layer deposition (ALD) is a proven technique for the conformal deposition of oxide thin films with nanoscale thickness control. Most successful industrial applications have been with binary oxides, such as Al{sub 2}O{sub 3} and HfO{sub 2}. However, there has been much effort to deposit ternary oxides, such as perovskites (ABO{sub 3}), with desirable properties for advanced thin film applications. Distinct challenges are presented by the deposition of multi-component oxides using ALD. This review is intended to highlight the research of the many groups that have deposited perovskite oxides by ALD methods. Several commonalities between the studies are discussed. Special emphasis is put on precursor selection, deposition temperatures, and specific property performance (high-k, ferroelectric, ferromagnetic, etc.). Finally, the monolithic integration of perovskite oxides with semiconductors by ALD is reviewed. High-quality epitaxial growth of oxide thin films has traditionally been limited to physical vapor deposition techniques (e.g., molecular beam epitaxy). However, recent studies have demonstrated that epitaxial oxide thin films may be deposited on semiconductor substrates using ALD. This presents an exciting opportunity to integrate functional perovskite oxides for advanced semiconductor applications in a process that is economical and scalable.

Atomic layer deposition of perovskite oxides and their epitaxial integration with Si, Ge, and other semiconductors

International Nuclear Information System (INIS)

McDaniel, Martin D.; Ngo, Thong Q.; Hu, Shen; Ekerdt, John G.; Posadas, Agham; Demkov, Alexander A.

2015-01-01

Atomic layer deposition (ALD) is a proven technique for the conformal deposition of oxide thin films with nanoscale thickness control. Most successful industrial applications have been with binary oxides, such as Al 2 O 3 and HfO 2 . However, there has been much effort to deposit ternary oxides, such as perovskites (ABO 3 ), with desirable properties for advanced thin film applications. Distinct challenges are presented by the deposition of multi-component oxides using ALD. This review is intended to highlight the research of the many groups that have deposited perovskite oxides by ALD methods. Several commonalities between the studies are discussed. Special emphasis is put on precursor selection, deposition temperatures, and specific property performance (high-k, ferroelectric, ferromagnetic, etc.). Finally, the monolithic integration of perovskite oxides with semiconductors by ALD is reviewed. High-quality epitaxial growth of oxide thin films has traditionally been limited to physical vapor deposition techniques (e.g., molecular beam epitaxy). However, recent studies have demonstrated that epitaxial oxide thin films may be deposited on semiconductor substrates using ALD. This presents an exciting opportunity to integrate functional perovskite oxides for advanced semiconductor applications in a process that is economical and scalable

Color sensor and neural processor on one chip

Science.gov (United States)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

Epitaxy of Polar Oxides and Semiconductors

Science.gov (United States)

Shelton, Christopher Tyrel

Integrating polar oxide materials with wide-bandgap nitride semiconductors offers the possibility of a tunable 2D carrier gas (2DCG) - provided defect densities are low and interfaces are abrupt. This dissertation investigates a portion of the synthesis science necessary to produce a "semiconductor-grade" interface between these highly dissimilar materials. A significant portion of this work is aligned with efforts to engineer a step-free GaN substrate to produce single in-plane oriented rocksalt oxide films. Initially, we explore the homoepitaxial MOCVD growth conditions necessary to produce highquality GaN films on ammonothermally grown substrates. Ammono substrates are only recently available for purchase and are the market leader in low-dislocation density material. Their novelty requires development of an understanding of morphology trade-offs in processing space. This includes preservation of the epi-polished surface in aggressive MOCVD environments and an understanding of the kinetic barriers affecting growth morphologies. Based on several factors, it was determined that GaN exhibits an 'uphill' diffusion bias that may likely be ascribed to a positive Ehrlich-Schwoebel (ES) barrier. This barrier should have a stabilizing effect against step-bunching but, for many growth conditions, regular step bunching was observed. One possible explanation for the step-bunching instability is the presence of impurities. Experimentally, conditions which incorporate more carbon into GaN homoepitaxial layers are correlated with step-bunching while conditions that suppress carbon produce bilayer stepped morphologies. These observations lead us to the conclusion that GaN homoepitaxial morphology is a competition between impurity induced step-bunching and a stabilizing diffusion bias due to a positive ES barrier. Application of the aforementioned homoepitaxial growth techniques to discrete substrate regions using selected- and confined area epitaxy (SAE,CAE) produces some

Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

International Nuclear Information System (INIS)

Chen Haijin; Lu Shengli; Shi Longxing

2009-01-01

A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

KAUST Repository

Wang, Zhenwei

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Binary copper oxide semiconductors: From materials towards devices

Energy Technology Data Exchange (ETDEWEB)

Meyer, B.K.; Polity, A.; Reppin, D.; Becker, M.; Hering, P.; Klar, P.J.; Sander, T.; Reindl, C.; Benz, J.; Eickhoff, M.; Heiliger, C.; Heinemann, M. [1. Physics Institute, Justus-Liebig University of Giessen (Germany); Blaesing, J.; Krost, A. [Institute of Experimental Physics (IEP), Otto-von-Guericke University Magdeburg (Germany); Shokovets, S. [Institute of Physics, Ilmenau University of Technology (Germany); Mueller, C.; Ronning, C. [Institute of Solid State Physics, Friedrich Schiller University Jena (Germany)

2012-08-15

Copper-oxide compound semiconductors provide a unique possibility to tune the optical and electronic properties from insulating to metallic conduction, from bandgap energies of 2.1 eV to the infrared at 1.40 eV, i.e., right into the middle of the efficiency maximum for solar-cell applications. Three distinctly different phases, Cu{sub 2}O, Cu{sub 4}O{sub 3}, and CuO, of this binary semiconductor can be prepared by thin-film deposition techniques, which differ in the oxidation state of copper. Their material properties as far as they are known by experiment or predicted by theory are reviewed. They are supplemented by new experimental results from thin-film growth and characterization, both will be critically discussed and summarized. With respect to devices the focus is on solar-cell performances based on Cu{sub 2}O. It is demonstrated by photoelectron spectroscopy (XPS) that the heterojunction system p-Cu{sub 2}O/n-AlGaN is much more promising for the application as efficient solar cells than that of p-Cu{sub 2}O/n-ZnO heterojunction devices that have been favored up to now. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Temperature Modulation with Specified Detection Point on Metal Oxide Semiconductor Gas Sensors for E-Nose Application

Directory of Open Access Journals (Sweden)

Arief SUDARMAJI

2015-03-01

Full Text Available Temperature modulation technique, some called dynamic measurement mode, on Metal-Oxide Semiconductor (MOS/MOX gas sensor has been widely observed and employed in many fields. We present its development, a Specified Detection Point (SDP on modulated sensing element of MOS sensor is applied which associated to its temperature modulation, temperature modulation-SDP so-named. We configured the rectangular modulation signal for MOS gas sensors (TGSs and FISs using PSOC CY8C28445-24PVXI (Programmable System on Chip which also functioned as acquisition unit and interface to a computer. Initial responses and selectivity evaluations were performed using statistical tool and Principal Component Analysis (PCA to differ sample gases (Toluene, Ethanol and Ammonia on dynamic chamber measurement under various frequencies (0.25 Hz, 1 Hz, 4 Hz and duty-cycles (25 %, 50 %, 75 %. We found that at lower frequency the response waveform of the sensors becomes more sloping and distinct, and selected modulations successfully increased the selectivity either on singular or array sensors rather than static temperature measurement.

Where the chips fall: environmental health in the semiconductor industry.

Science.gov (United States)

Chepesiuk, R

1999-09-01

Three recent lawsuits are focusing public attention on the environmental and occupational health effects of the world's largest and fastest growing manufacturing sector-the $150 billion semiconductor industry. The suits allege that exposure to toxic chemicals in semiconductor manufacturing plants led to adverse health effects such as miscarriage and cancer among workers. To manufacture computer components, the semiconductor industry uses large amounts of hazardous chemicals including hydrochloric acid, toxic metals and gases, and volatile solvents. Little is known about the long-term health consequences of exposure to chemicals by semiconductor workers. According to industry critics, the semiconductor industry also adversely impacts the environment, causing groundwater and air pollution and generating toxic waste as a by-product of the semiconductor manufacturing process. In contrast, the U.S. Bureau of Statistics shows the semiconductor industry as having a worker illness rate of about one-third of the average of all manufacturers, and advocates defend the industry, pointing to recent research collaborations and product replacement as proof that semiconductor manufacturers adequately protect both their employees and the environment.

Ultrawide band gap amorphous oxide semiconductor, Ga–Zn–O

Energy Technology Data Exchange (ETDEWEB)

Kim, Junghwan, E-mail: JH.KIM@lucid.msl.titech.ac.jp [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Miyokawa, Norihiko; Sekiya, Takumi; Ide, Keisuke [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Toda, Yoshitake [Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Hiramatsu, Hidenori; Hosono, Hideo; Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox SE-6, 4259 Nagatsuta, Midori-ku, Yokohama (Japan)

2016-09-01

We fabricated amorphous oxide semiconductor films, a-(Ga{sub 1–x}Zn{sub x})O{sub y}, at room temperature on glass, which have widely tunable band gaps (E{sub g}) ranging from 3.47–4.12 eV. The highest electron Hall mobility ~ 7 cm{sup 2} V{sup −1} s{sup −1} was obtained for E{sub g} = ~ 3.8 eV. Ultraviolet photoemission spectroscopy revealed that the increase in E{sub g} with increasing the Ga content comes mostly from the deepening of the valence band maximum level while the conduction band minimum level remains almost unchanged. These characteristics are explained by their electronic structures. As these films can be fabricated at room temperature on plastic, this achievement extends the applications of flexible electronics to opto-electronic integrated circuits associated with deep ultraviolet region. - Highlights: • Incorporation of H/H{sub 2}O stabilizes the amorphous phase. • Ultrawide band gap (~ 3.8 eV) amorphous oxide semiconductor was fabricated. • The increase in band gap comes mostly from the deepening of the valence band maximum level. • Donor level is more likely aligned to the valence band maximum level.

Bacteria inside semiconductors as potential sensor elements: biochip progress.

Science.gov (United States)

Sah, Vasu R; Baier, Robert E

2014-06-24

It was discovered at the beginning of this Century that living bacteria-and specifically the extremophile Pseudomonas syzgii-could be captured inside growing crystals of pure water-corroding semiconductors-specifically germanium-and thereby initiated pursuit of truly functional "biochip-based" biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs) and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities' features at the time of first production of these potential biochips.

Color-selective photodetection from intermediate colloidal quantum dots buried in amorphous-oxide semiconductors.

Science.gov (United States)

Cho, Kyung-Sang; Heo, Keun; Baik, Chan-Wook; Choi, Jun Young; Jeong, Heejeong; Hwang, Sungwoo; Lee, Sang Yeol

2017-10-10

We report color-selective photodetection from intermediate, monolayered, quantum dots buried in between amorphous-oxide semiconductors. The proposed active channel in phototransistors is a hybrid configuration of oxide-quantum dot-oxide layers, where the gate-tunable electrical property of silicon-doped, indium-zinc-oxide layers is incorporated with the color-selective properties of quantum dots. A remarkably high detectivity (8.1 × 10 13 Jones) is obtained, along with three major findings: fast charge separation in monolayered quantum dots; efficient charge transport through high-mobility oxide layers (20 cm 2  V -1  s -1 ); and gate-tunable drain-current modulation. Particularly, the fast charge separation rate of 3.3 ns -1 measured with time-resolved photoluminescence is attributed to the intermediate quantum dots buried in oxide layers. These results facilitate the realization of efficient color-selective detection exhibiting a photoconductive gain of 10 7 , obtained using a room-temperature deposition of oxide layers and a solution process of quantum dots. This work offers promising opportunities in emerging applications for color detection with sensitivity, transparency, and flexibility.The development of highly sensitive photodetectors is important for image sensing and optical communication applications. Cho et al., report ultra-sensitive photodetectors based on monolayered quantum dots buried in between amorphous-oxide semiconductors and demonstrate color-detecting logic gates.

On-chip single photon filtering and multiplexing in hybrid quantum photonic circuits.

Science.gov (United States)

Elshaari, Ali W; Zadeh, Iman Esmaeil; Fognini, Andreas; Reimer, Michael E; Dalacu, Dan; Poole, Philip J; Zwiller, Val; Jöns, Klaus D

2017-08-30

Quantum light plays a pivotal role in modern science and future photonic applications. Since the advent of integrated quantum nanophotonics different material platforms based on III-V nanostructures-, colour centers-, and nonlinear waveguides as on-chip light sources have been investigated. Each platform has unique advantages and limitations; however, all implementations face major challenges with filtering of individual quantum states, scalable integration, deterministic multiplexing of selected quantum emitters, and on-chip excitation suppression. Here we overcome all of these challenges with a hybrid and scalable approach, where single III-V quantum emitters are positioned and deterministically integrated in a complementary metal-oxide-semiconductor-compatible photonic circuit. We demonstrate reconfigurable on-chip single-photon filtering and wavelength division multiplexing with a foot print one million times smaller than similar table-top approaches, while offering excitation suppression of more than 95 dB and efficient routing of single photons over a bandwidth of 40 nm. Our work marks an important step to harvest quantum optical technologies' full potential.Combining different integration platforms on the same chip is currently one of the main challenges for quantum technologies. Here, Elshaari et al. show III-V Quantum Dots embedded in nanowires operating in a CMOS compatible circuit, with controlled on-chip filtering and tunable routing.

Group IIB-VIA semiconductor oxide cluster ions

Science.gov (United States)

Jayasekharan, Thankan

2018-05-01

Metal oxide cluster ions, MnOm± (M = Zn, Cd) and HgnOm- of various stoichiometry have been generated from solid IIB-VIA semiconductor oxides targets, (ZnO(s), CdO(s), and HgO(s)) by using pulse laser desorption ionization time of flight mass spectrometry with a laser of λ = 355 nm. Analysis of mass spectral data indicates the formation of stoichiometric cluster ions viz., (ZnO)n=1-30+ and (CdO)n=1-40+ along with -O bound anions, (ZnO)n=1-30O-, (CdO)n=1-40O- and (HgO)n=1-36O- from their respective solids. Further, metal oxoanions such as ZnOn=2,3-, CdOn=2,3,6-, and HgOn=2,3,6,7- have also been noted signifying the higher coordination ability of both Cd and Hg with O/O2/O3 species.

Metal-oxide-semiconductor devices based on epitaxial germanium-carbon layers grown directly on silicon substrates by ultra-high-vacuum chemical vapor deposition

Science.gov (United States)

Kelly, David Quest

After the integrated circuit was invented in 1959, complementary metal-oxide-semiconductor (CMOS) technology soon became the mainstay of the semiconductor industry. Silicon-based CMOS has dominated logic technologies for decades. During this time, chip performance has grown at an exponential rate at the cost of higher power consumption and increased process complexity. The performance gains have been made possible through scaling down circuit dimensions by improvements in lithography capabilities. Since scaling cannot continue forever, researchers have vigorously pursued new ways of improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs) without having to shrink gate lengths and reduce the gate insulator thickness. Strained silicon, with its ability to boost transistor current by improving the channel mobility, is one of the methods that has already found its way into production. Although not yet in production, high-kappa dielectrics have also drawn wide interest in industry since they allow for the reduction of the electrical oxide thickness of the gate stack without having to reduce the physical thickness of the dielectric. Further out on the horizon is the incorporation of high-mobility materials such as germanium (Ge), silicon-germanium (Si1-xGe x), and the III-V semiconductors. Among the high-mobility materials, Ge has drawn the most attention because it has been shown to be compatible with high-kappa dielectrics and to produce high drive currents compared to Si. Among the most difficult challenges for integrating Ge on Si is finding a suitable method for reducing the number of crystal defects. The use of strain-relaxed Si1- xGex buffers has proven successful for reducing the threading dislocation density in Ge epitaxial layers, but questions remain as to the viability of this method in terms of cost and process complexity. This dissertation presents research on thin germanium-carbon (Ge 1-yCy layers on Si for the fabrication

Bi-component semiconductor oxide photoanodes for the photoelectrocatalytic oxidation of organic solutes and vapours: a short review with emphasis to TiO2-WO3 photoanodes.

Science.gov (United States)

Georgieva, J; Valova, E; Armyanov, S; Philippidis, N; Poulios, I; Sotiropoulos, S

2012-04-15

The use of binary semiconductor oxide anodes for the photoelectrocatalytic oxidation of organic species (both in solution and gas phase) is reviewed. In the first part of the review, the principle of electrically assisted photocatalysis is presented, the preparation methods for the most common semiconductor oxide catalysts are briefly mentioned, while the advantages of appropriately chosen semiconductor combinations for efficient UV and visible (vis) light utilization are highlighted. The second part of the review focuses on the discussion of TiO(2)-WO(3) photoanodes (among the most studied bi-component semiconductor oxide systems) and in particular on coatings prepared by electrodeposition/electrosynthesis or powder mixtures (the focus of the authors' research during recent years). Studies concerning the microscopic, spectroscopic and photoelectrochemical characterization of the catalysts are presented and examples of photoanode activity towards typical dissolved organic contaminants as well as organic vapours are given. Particular emphasis is paid to: (a) The dependence of photoactivity on catalyst morphology and composition and (b) the possibility of carrying out photoelectrochemistry in all-solid cells, thus opening up the opportunity for photoelectrocatalytic air treatment. Copyright © 2011 Elsevier B.V. All rights reserved.

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.; Kutbee, Arwa T.; Ghodsi Nasseri, Seyed Faizelldin; Bersuker, G.; Hussain, Muhammad Mustafa

2014-01-01

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect

Synchronization of Integrated Systems on a Chip

Directory of Open Access Journals (Sweden)

González-Díaz O.

2012-04-01

Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

Metal-semiconductor interface in extreme temperature conditions

International Nuclear Information System (INIS)

Bulat, L.P.; Erofeeva, I.A.; Vorobiev, Yu.V.; Gonzalez-Hernandez, J.

2008-01-01

We present an investigation of electrons' and phonons' temperatures in the volume of a semiconductor (or metal) sample and at the interface between metal and semiconductor. Two types of mismatch between electrons' and phonons' temperatures take place: at metal-semiconductor interfaces and in the volume of the sample. The temperature mismatch leads to nonlinear terms in expressions for heat and electricity transport. The nonlinear effects should be taken into consideration in the study of electrical and heat transport in composites and in electronic chips

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

Science.gov (United States)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Opening of K+ channels by capacitive stimulation from silicon chip

Science.gov (United States)

Ulbrich, M. H.; Fromherz, P.

2005-10-01

The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

Introduction to semiconductor manufacturing technology

CERN Document Server

2012-01-01

IC chip manufacturing processes, such as photolithography, etch, CVD, PVD, CMP, ion implantation, RTP, inspection, and metrology, are complex methods that draw upon many disciplines. [i]Introduction to Semiconductor Manufacturing Technologies, Second Edition[/i] thoroughly describes the complicated processes with minimal mathematics, chemistry, and physics; it covers advanced concepts while keeping the contents accessible to readers without advanced degrees. Designed as a textbook for college students, this book provides a realistic picture of the semiconductor industry and an in-depth discuss

STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

Directory of Open Access Journals (Sweden)

Ireneusz Zagórski

2016-12-01

Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal - oxide - semiconductor field-effect transistors: Effective electron mobility

International Nuclear Information System (INIS)

Ragnarsson, L.-A degree.; Guha, S.; Copel, M.; Cartier, E.; Bojarczuk, N. A.; Karasinski, J.

2001-01-01

We report on high effective mobilities in yttrium-oxide-based n-channel metal - oxide - semiconductor field-effect transistors (MOSFETs) with aluminum gates. The yttrium oxide was grown in ultrahigh vacuum using a reactive atomic-beam-deposition system. Medium-energy ion-scattering studies indicate an oxide with an approximate composition of Y 2 O 3 on top of a thin layer of interfacial SiO 2 . The thickness of this interfacial oxide as well as the effective mobility are found to be dependent on the postgrowth anneal conditions. Optimum conditions result in mobilities approaching that of SiO 2 -based MOSFETs at higher fields with peak mobilities at approximately 210 cm 2 /Vs. [copyright] 2001 American Institute of Physics

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.

2012-03-12

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

Covalent functionalization of carbon nanotube forests grown in situ on a metal-silicon chip

KAUST Repository

Johansson, Johan R.; Bosaeus, Niklas; Kann, Nina; Å kerman, Bjö rn; Nordé n, Bengt; Khalid, Waqas

2012-01-01

We report on the successful covalent functionalization of carbon nanotube (CNT) forests, in situ grown on a silicon chip with thin metal contact film as the buffer layer between the CNT forests and the substrate. The CNT forests were successfully functionalized with active amine and azide groups, which can be used for further chemical reactions. The morphology of the CNT forests was maintained after the functionalization. We thus provide a promising foundation for a miniaturized biosensor arrays system that can be easily integrated with Complementary Metal-Oxide Semiconductor (CMOS) technology.

X-ray imaging with photon counting hybrid semiconductor pixel detectors

CERN Document Server

Manolopoulos, S; Campbell, M; Snoeys, W; Heijne, Erik H M; Pernigotti, E; Raine, C; Smith, K; Watt, J; O'Shea, V; Ludwig, J; Schwarz, C

1999-01-01

Semiconductor pixel detectors, originally developed for particle physics experiments, have been studied as X-ray imaging devices. The performance of devices using the OMEGA 3 read-out chip bump-bonded to pixellated silicon semiconductor detectors is characterised in terms of their signal-to-noise ratio when exposed to 60 kVp X-rays. Although parts of the devices achieve values of this ratio compatible with the noise being photon statistics limited, this is not found to hold for the whole pixel matrix, resulting in the global signal-to-noise ratio being compromised. First results are presented of X-ray images taken with a gallium arsenide pixel detector bump-bonded to a new read-out chip, (MEDIPIX), which is a single photon counting read-out chip incorporating a 15-bit counter in every pixel. (author)

Laser Doppler perfusion imaging with a complimentary metal oxide semiconductor image sensor

NARCIS (Netherlands)

Serov, Alexander; Steenbergen, Wiendelt; de Mul, F.F.M.

2002-01-01

We utilized a complimentary metal oxide semiconductor video camera for fast f low imaging with the laser Doppler technique. A single sensor is used for both observation of the area of interest and measurements of the interference signal caused by dynamic light scattering from moving particles inside

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

Science.gov (United States)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Chemically-modified electrodes in photoelectrochemical cells. [Tin oxide and TiO/sub 2/ semiconductor electrodes

Energy Technology Data Exchange (ETDEWEB)

Fox, M A; Hohman, J R; Kamat, P V

1893-01-01

Tin oxide and titanium dioxide semiconductor electrodes hae been covalently modified by the attachment of functionalized olefins and arenes through surface silanation or via a cyanuric chloride linkage. The excited state and electrochemical properties of the molecules so attached are significantly affected by the semiconductor. Photocurrent measurements and time-resolved laser coulostatic monitoring have been employed to elucidate the mechanism of charge injection on these modified surfaces. 17 references, 7 figures.

Bacteria Inside Semiconductors as Potential Sensor Elements: Biochip Progress

Directory of Open Access Journals (Sweden)

Vasu R. Sah

2014-06-01

Full Text Available It was discovered at the beginning of this Century that living bacteria—and specifically the extremophile Pseudomonas syzgii—could be captured inside growing crystals of pure water-corroding semiconductors—specifically germanium—and thereby initiated pursuit of truly functional “biochip-based” biosensors. This observation was first made at the inside ultraviolet-illuminated walls of ultrapure water-flowing semiconductor fabrication facilities (fabs and has since been, not as perfectly, replicated in simpler flow cell systems for chip manufacture, described here. Recognizing the potential importance of these adducts as optical switches, for example, or probes of metabolic events, the influences of the fabs and their components on the crystal nucleation and growth phenomena now identified are reviewed and discussed with regard to further research needs. For example, optical beams of current photonic circuits can be more easily modulated by integral embedded cells into electrical signals on semiconductors. Such research responds to a recently published Grand Challenge in ceramic science, designing and synthesizing oxide electronics, surfaces, interfaces and nanoscale structures that can be tuned by biological stimuli, to reveal phenomena not otherwise possible with conventional semiconductor electronics. This short review addresses only the fabrication facilities’ features at the time of first production of these potential biochips.

What's A Pixel Particle Sensor Chip?

CERN Multimedia

2008-01-01

ATLAS particle physics experiment aided with collaboration ON Semiconductor was recently honored by the European Council for Nuclear Research (CERN), with an Industrial Award recognizing the company's contribution in supplying complex "Pixel Particle Sensor" chips for use in CERN's ATLAS particle physics experiment.

Solid-Phase Immunoassay of Polystyrene-Encapsulated Semiconductor Coreshells for Cardiac Marker Detection

Directory of Open Access Journals (Sweden)

Sanghee Kim

2012-01-01

Full Text Available A solid-phase immunoassay of polystyrene-encapsulated semiconductor nanoparticles was demonstrated for cardiac troponin I (cTnI detection. CdSe/ZnS coreshells were encapsulated with a carboxyl-functionalized polystyrene nanoparticle to capture the target antibody through a covalent bonding and to eliminate the photoblinking and toxicity of semiconductor luminescent immunosensor. The polystyrene-encapsulated CdSe/ZnS fluorophores on surface-modified glass chip identified cTnI antigens at the level of ~ng/mL. It was an initial demonstration of diagnostic chip for monitoring a cardiovascular disease.

P-type Oxide Semiconductors for Transparent & Energy Efficient Electronics

KAUST Repository

Wang, Zhenwei

2018-03-11

Emerging transparent semiconducting oxide (TSO) materials have achieved their initial commercial success in the display industry. Due to the advanced electrical performance, TSOs have been adopted either to improve the performance of traditional displays or to demonstrate the novel transparent and flexible displays. However, due to the lack of feasible p-type TSOs, the applications of TSOs is limited to unipolar (n-type TSOs) based devices. Compared with the prosperous n-type TSOs, the performance of p-type counterparts is lag behind. However, after years of discovery, several p-type TSOs are confirmed with promising performance, for example, tin monoxide (SnO). By using p-type SnO, excellent transistor field-effect mobility of 6.7 cm2 V-1 s-1 has been achieved. Motivated by this encouraging performance, this dissertation is devoted to further evaluate the feasibility of integrating p-type SnO in p-n junctions and complementary metal oxide semiconductor (CMOS) devices. CMOS inverters are fabricated using p-type SnO and in-situ formed n-type tin dioxide (SnO2). The semiconductors are simultaneously sputtered, which simplifies the process of CMOS inverters. The in-situ formation of SnO2 phase is achieved by selectively sputtering additional capping layer, which serves as oxygen source and helps to balance the process temperature for both types of semiconductors. Oxides based p-n junctions are demonstrated between p-type SnO and n-type SnO2 by magnetron sputtering method. Diode operating ideality factor of 3.4 and rectification ratio of 103 are achieved. A large temperature induced knee voltage shift of 20 mV oC-1 is observed, and explained by the large band gap and shallow states in SnO, which allows minor adjustment of band structure in response to the temperature change. Finally, p-type SnO is used to demonstrating the hybrid van der Waals heterojunctions (vdWHs) with two-dimensional molybdenum disulfide (2D MoS2) by mechanical exfoliation. The hybrid vdWHs show

Emission channeling with short-lived isotopes lattice location of impurities in semiconductors and oxides

CERN Multimedia

We propose to perform emission channeling lattice location experiments in a number of semiconductor and oxide systems of technological relevance: \\\\- The lattice location of the transition metal probes $^{56}$Mn ($\\textit{t}_{1/2}$=2.6 h), $^{59}$Fe (45 d), $^{61}$Co (1.6 h) and $^{65}$Ni (2.5 h) is to be investigated in materials of interest as dilute magnetic semiconductors, such as GaMnAs, GaMnN, GaFeN, AlGaN, SiC, and in a number of oxides that are candidates for “single ion ferromagnetism”, in particular SrTiO$_3$ and LiNbO$_3$.\\\\- The topic of $\\textit{p}$-type doping of nitride semiconductors shall be addressed by studying the lattice sites of the acceptor dopants Mg and Be in GaN and AlN using the short-lived probes $^{27}$Mg (9.5 min) and $^{11}$Be (13.8 s). The aim is to reach a lattice location precision around 0.05 Å in order to provide critical tests for recent theoretical models which e.g. have predicted displacements of the Mg atom from the ideal substitutional Ga and Al sites of the order...

Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

KAUST Repository

Labram, John G.

2015-02-13

Physical phenomena such as energy quantization have to-date been overlooked in solution-processed inorganic semiconducting layers, owing to heterogeneity in layer thickness uniformity unlike some of their vacuum-deposited counterparts. Recent reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization in inorganic semiconductor layers with appreciable surface roughness, as compared to the mean layer thickness, and present experimental evidence of the existence of quantized energy states in spin-cast layers of zinc oxide (ZnO). As-grown ZnO layers are found to be remarkably continuous and uniform with controllable thicknesses in the range 2-24 nm and exhibit a characteristic widening of the energy bandgap with reducing thickness in agreement with theoretical predictions. Using sequentially spin-cast layers of ZnO as the bulk semiconductor and quantum well materials, and gallium oxide or organic self-assembled monolayers as the barrier materials, two terminal electronic devices are demonstrated, the current-voltage characteristics of which resemble closely those of double-barrier resonant-tunneling diodes. As-fabricated all-oxide/hybrid devices exhibit a characteristic negative-differential conductance region with peak-to-valley ratios in the range 2-7.

SETEC/Semiconductor Manufacturing Technologies Program: 1999 Annual and Final Report

Energy Technology Data Exchange (ETDEWEB)

MCBRAYER,JOHN D.

2000-12-01

This report summarizes the results of work conducted by the Semiconductor Manufacturing Technologies Program at Sandia National Laboratories (Sandia) during 1999. This work was performed by one working group: the Semiconductor Equipment Technology Center (SETEC). The group's projects included Numerical/Experimental Characterization of the Growth of Single-Crystal Calcium Fluoride (CaF{sub 2}); The Use of High-Resolution Transmission Electron Microscopy (HRTEM) Imaging for Certifying Critical-Dimension Reference Materials Fabricated with Silicon Micromachining; Assembly Test Chip for Flip Chip on Board; Plasma Mechanism Validation: Modeling and Experimentation; and Model-Based Reduction of Contamination in Gate-Quality Nitride Reactor. During 1999, all projects focused on meeting customer needs in a timely manner and ensuring that projects were aligned with the goals of the National Technology Roadmap for Semiconductors sponsored by the Semiconductor Industry Association and with Sandia's defense mission. This report also provides a short history of the Sandia/SEMATECH relationship and a brief on all projects completed during the seven years of the program.

Atomic layer deposited TiO2 for implantable brain-chip interfacing devices

International Nuclear Information System (INIS)

Cianci, E.; Lattanzio, S.; Seguini, G.; Vassanelli, S.; Fanciulli, M.

2012-01-01

In this paper we investigated atomic layer deposition (ALD) TiO 2 thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 °C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al 2 O 3 buffer layer between TiO 2 and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

NARCIS (Netherlands)

Jin, J.W.; Nathan, A.; Barquinha, P.; Pereira, L.; Fortunato, E.; Martins, R.; Cobb, B.

2016-01-01

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We

Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

International Nuclear Information System (INIS)

Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

2016-01-01

This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

International Nuclear Information System (INIS)

Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

2015-01-01

Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10 17  m −2 . We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching

Inherent polarization entanglement generated from a monolithic semiconductor chip

DEFF Research Database (Denmark)

Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

2013-01-01

Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

Method to induce a conductivity type in a semiconductor

International Nuclear Information System (INIS)

Aboaf, J.A.; Sedgwick, T.O.

1977-01-01

The invention deals with a method in which one can produce a region of a desired type of conductivity in a semiconductor as is required for, e.g., field effect transistors. A metal oxide layer combination consisting of several metal oxides is thus deposited on the semiconductor. This is carried out according to the invention in a non-oxidizing atmosphere at temperatures at which the metal oxides do not diffuse into the semiconductor. The sign and degree of the induced conductivity type is adjusted by dosed depositing of the individual metal oxides related to one another. The gaseous metal oxides due to heating, mixed with a non-oxidizing gas are added in compounds to the semiconductor heated to depositing temperature. These compounds decompose at the depositing temperature into the metal oxide and a gaseous residual component. The semiconductor consists of silicon, and nitrogen is used as carrier gas; when depositing aluminium oxide, gaseous aluminium isopropoxide is added; when depositing silicon dioxide, gaseous tetra-ethyl orthosilicate. (ORU) [de

Atomic Layer Deposited Thin Films for Dielectrics, Semiconductor Passivation, and Solid Oxide Fuel Cells

Science.gov (United States)

Xu, Runshen

Atomic layer deposition (ALD) utilizes sequential precursor gas pulses to deposit one monolayer or sub-monolayer of material per cycle based on its self-limiting surface reaction, which offers advantages, such as precise thickness control, thickness uniformity, and conformality. ALD is a powerful means of fabricating nanoscale features in future nanoelectronics, such as contemporary sub-45 nm metal-oxide-semiconductor field effect transistors, photovoltaic cells, near- and far-infrared detectors, and intermediate temperature solid oxide fuel cells. High dielectric constant, kappa, materials have been recognized to be promising candidates to replace traditional SiO2 and SiON, because they enable good scalability of sub-45 nm MOSFET (metal-oxide-semiconductor field-effect transistor) without inducing additional power consumption and heat dissipation. In addition to high dielectric constant, high-kappa materials must meet a number of other requirements, such as low leakage current, high mobility, good thermal and structure stability with Si to withstand high-temperature source-drain activation annealing. In this thesis, atomic layer deposited Er2O3 doped TiO2 is studied and proposed as a thermally stable amorphous high-kappa dielectric on Si substrate. The stabilization of TiO2 in its amorphous state is found to achieve a high permittivity of 36, a hysteresis voltage of less than 10 mV, and a low leakage current density of 10-8 A/cm-2 at -1 MV/cm. In III-V semiconductors, issues including unsatisfied dangling bonds and native oxides often result in inferior surface quality that yields non-negligible leakage currents and degrades the long-term performance of devices. The traditional means for passivating the surface of III-V semiconductors are based on the use of sulfide solutions; however, that only offers good protection against oxidation for a short-term (i.e., one day). In this work, in order to improve the chemical passivation efficacy of III-V semiconductors

Organic semiconductors in sensor applications

CERN Document Server

Malliaras, George; Owens, Róisín

2008-01-01

Organic semiconductors offer unique characteristics such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing, and facile integration with chemical and biological functionalities. These characteristics have prompted the application of organic semiconductors and their devices in physical, chemical, and biological sensors. This book covers this rapidly emerging field by discussing both optical and electrical sensor concepts. Novel transducers based on organic light-emitting diodes and organic thin-film transistors, as well as systems-on-a-chip architectures are presented. Functionalization techniques to enhance specificity are outlined, and models for the sensor response are described.

Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

Energy Technology Data Exchange (ETDEWEB)

Bratkovsky, A M [Hewlett-Packard Laboratories, 1501 Page Mill Road, MS 1123, Palo Alto, CA 94304 (United States)

2008-02-15

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

Spintronic effects in metallic, semiconductor, metal-oxide and metal-semiconductor heterostructures

International Nuclear Information System (INIS)

Bratkovsky, A M

2008-01-01

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field

Spintronic effects in metallic, semiconductor, metal oxide and metal semiconductor heterostructures

Science.gov (United States)

Bratkovsky, A. M.

2008-02-01

Spintronics is a rapidly growing field focusing on phenomena and related devices essentially dependent on spin transport. Some of them are already an established part of microelectronics. We review recent theoretical and experimental advances in achieving large spin injection efficiency (polarization of current) and accumulated spin polarization. These include tunnel and giant magnetoresistance, spin-torque and spin-orbit effects on electron transport in various heterostructures. We give a microscopic description of spin tunneling through oxide and modified Schottky barriers between a ferromagnet (FM) and a semiconductor (S). It is shown that in such FM-S junctions electrons with a certain spin projection can be efficiently injected into (or extracted from) S, while electrons with the opposite spin can accumulate in S near the interface. The criterion for efficient injection is opposite to a known Rashba criterion, since the barrier should be rather transparent. In degenerate semiconductors, extraction of spin can proceed at low temperatures. We mention a few novel spin-valve ultrafast devices with small dissipated power: a magnetic sensor, a spin transistor, an amplifier, a frequency multiplier, a square-law detector and a source of polarized radiation. We also discuss effects related to spin-orbital interactions, such as the spin Hall effect (SHE) and a recently predicted positive magnetoresistance accompanying SHE. Some esoteric devices such as 'spinFET', interacting spin logic and spin-based quantum computing are discussed and problems with their realization are highlighted. We demonstrate that the so-called 'ferroelectric tunnel junctions' are unlikely to provide additional functionality because in all realistic situations the ferroelectric barrier would be split into domains by the depolarizing field.

A fast template matching method for LED chip Localization

Directory of Open Access Journals (Sweden)

Zhong Fuqiang

2015-01-01

Full Text Available Efficiency determines the profits of the semiconductor producers. So the producers spare no effort to enhance the efficiency of every procedure. The purpose of the paper is to present a method to shorten the time to locate the LED chips on wafer. The method consists of 3 steps. Firstly, image segmentation and blob analyzation are used to predict the positions of potential chips. Then predict the orientations of potential chips based on their dominant orientations. Finally, according to the positions and orientations predicted above, locate the chips precisely based on gradient orientation features. Experiments show that the algorithm is faster than the traditional method we choose to locate the LED chips. Besides, even the orientations of the chips on wafer are of big deviation to the orientation of the template, the efficiency of this method won't be affected.

Atomic layer deposited TiO{sub 2} for implantable brain-chip interfacing devices

Energy Technology Data Exchange (ETDEWEB)

Cianci, E., E-mail: elena.cianci@mdm.imm.cnr.it [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (MB) (Italy); Lattanzio, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Dipartimento di Ingegneria dell' Informazione, Universita di Padova, 35131 Padova (Italy); Seguini, G. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Vassanelli, S. [Istituto di Fisiologia, Dipartimento di Anatomia Umana e Fisiologia, Universita di Padova, 35131 Padova (Italy); Fanciulli, M. [Laboratorio MDM, IMM-CNR, 20864 Agrate Brianza (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano-Bicocca, 20126 Milano (Italy)

2012-05-01

In this paper we investigated atomic layer deposition (ALD) TiO{sub 2} thin films deposited on implantable neuro-chips based on electrolyte-oxide-semiconductor (EOS) junctions, implementing both efficient capacitive neuron-silicon coupling and biocompatibility for long-term implantable functionality. The ALD process was performed at 295 Degree-Sign C using titanium tetraisopropoxide and ozone as precursors on needle-shaped silicon substrates. Engineering of the capacitance of the EOS junctions introducing a thin Al{sub 2}O{sub 3} buffer layer between TiO{sub 2} and silicon resulted in a further increase of the specific capacitance. Biocompatibility for long-term implantable neuroprosthetic systems was checked upon in-vitro treatment.

Development of semiconductor electronics

International Nuclear Information System (INIS)

Bardeen, John.

1977-01-01

In 1931, Wilson applied Block's theory about the energy bands for the motion of electrons in a crystal lattice to semiconductors and showed that conduction can take place in two different ways, by electrons and by holes. Not long afterwards Frenkel showed that these carriers can flow by diffusion in a concentration gradient as well as under the influence of an electric field and wrote down equations for the current flow. The third major contribution, in the late 1930's was the explanation of rectification at a metalsemiconductor contact by Mott and more completely by Schottky. In late 1947 the first transistor of the point contact type was invented by Brattin, Shockley and Bardeen. Then after single crystals of Ge were grown, the junction transistor was developed by the same group. The first silicon transistors appeared in 1954. Then an important step was discovery of the planar transistor by Hoenri in 1960 which led to development of integrated circuits by 1962. Many transistors are produced by batch processing on a slice of silicon. Then in 1965 Mos (Metal-Oxide Semiconductor) transistor and in 1968 LSI (Large Scale Intergration circuits) were developed. Aside from electronic circuits, there are many other applications of semiconductors, including junction power rectifiers, junction luminescence (including lasers), solar batteries, radiation detectors, microwave oscillators and charged-coupled devices for computer memories and devices. One of the latest developments is a microprocessor with thousands of transistors and associated circuitry on a single small chip of silicon. It can be programmed to provide a variety of circuit functions, thus it is not necessary to go through the great expense of LSI's for each desired function, but to use standard microprocessors and program to do the job

Cu2O-based solar cells using oxide semiconductors

International Nuclear Information System (INIS)

Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

2016-01-01

We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu 2 O heterojunction solar cells fabricated using p-type Cu 2 O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu 2 O sheets under various deposition conditions using a pulsed laser deposition method. In Cu 2 O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa 2 O 4 thin-film layer. In most of the Cu 2 O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga 2 O 3 -Al 2 O 3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (V oc ) were obtained by using a relatively small amount of MgO or Al 2 O 3 , e.g., (ZnO) 0.91 –(MgO) 0.09 and (Ga 2 O 3 ) 0.975 –(Al 2 O 3 ) 0.025 , respectively. When Cu 2 O-based heterojunction solar cells were fabricated using Al 2 O 3 –Ga 2 O 3 –MgO–ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high V oc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu 2 O heterojunction solar cells fabricated using Na-doped Cu 2 O (Cu 2 O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a V oc of 0.84 V were obtained in a MgF 2 /AZO/n-(Ga 2 O 3 –Al 2 O 3 )/p-Cu 2 O:Na heterojunction solar cell fabricated using

Cu2O-based solar cells using oxide semiconductors

Science.gov (United States)

Minami, Tadatsugu; Nishi, Yuki; Miyata, Toshihiro

2016-01-01

We describe significant improvements of the photovoltaic properties that were achieved in Al-doped ZnO (AZO)/n-type oxide semiconductor/p-type Cu2O heterojunction solar cells fabricated using p-type Cu2O sheets prepared by thermally oxidizing Cu sheets. The multicomponent oxide thin film used as the n-type semiconductor layer was prepared with various chemical compositions on non-intentionally heated Cu2O sheets under various deposition conditions using a pulsed laser deposition method. In Cu2O-based heterojunction solar cells fabricated using various ternary compounds as the n-type oxide thin-film layer, the best photovoltaic performance was obtained with an n-ZnGa2O4 thin-film layer. In most of the Cu2O-based heterojunction solar cells using multicomponent oxides composed of combinations of various binary compounds, the obtained photovoltaic properties changed gradually as the chemical composition was varied. However, with the ZnO-MgO and Ga2O3-Al2O3 systems, higher conversion efficiencies (η) as well as a high open circuit voltage (Voc) were obtained by using a relatively small amount of MgO or Al2O3, e.g., (ZnO)0.91-(MgO)0.09 and (Ga2O3)0.975-(Al2O3)0.025, respectively. When Cu2O-based heterojunction solar cells were fabricated using Al2O3-Ga2O3-MgO-ZnO (AGMZO) multicomponent oxide thin films deposited with metal atomic ratios of 10, 60, 10 and 20 at.% for the Al, Ga, Mg and Zn, respectively, a high Voc of 0.98 V and an η of 4.82% were obtained. In addition, an enhanced η and an improved fill factor could be achieved in AZO/n-type multicomponent oxide/p-type Cu2O heterojunction solar cells fabricated using Na-doped Cu2O (Cu2O:Na) sheets that featured a resistivity controlled by optimizing the post-annealing temperature and duration. Consequently, an η of 6.25% and a Voc of 0.84 V were obtained in a MgF2/AZO/n-(Ga2O3-Al2O3)/p-Cu2O:Na heterojunction solar cell fabricated using a Cu2O:Na sheet with a resistivity of approximately 10 Ω·cm and a (Ga0.975Al0

Potential roughness near lithographically fabricated atom chips

DEFF Research Database (Denmark)

Krüger, Peter; Andersson, L. M.; Wildermuth, Stefan

2007-01-01

Potential roughness has been reported to severely impair experiments in magnetic microtraps. We show that these obstacles can be overcome as we measure disorder potentials that are reduced by two orders of magnitude near lithographically patterned high-quality gold layers on semiconductor atom chip...

Field testing for cosmic ray soft errors in semiconductor memories

International Nuclear Information System (INIS)

O'Gorman, T.J.; Ross, J.M.; Taber, A.H.; Ziegler, J.F.; Muhlfeld, H.P.; Montrose, C.J.; Curtis, H.W.; Walsh, J.L.

1996-01-01

This paper presents a review of experiments performed by IBM to investigate the causes of soft errors in semiconductor memory chips under field test conditions. The effects of alpha-particles and cosmic rays are separated by comparing multiple measurements of the soft-error rate (SER) of samples of memory chips deep underground and at various altitudes above the earth. The results of case studies on four different memory chips show that cosmic rays are an important source of the ionizing radiation that causes soft errors. The results of field testing are used to confirm the accuracy of the modeling and the accelerated testing of chips

Digitally tunable dual wavelength emission from semiconductor ring lasers with filtered optical feedback

International Nuclear Information System (INIS)

Khoder, Mulham; Verschaffelt, Guy; Nguimdo, Romain Modeste; Danckaert, Jan; Leijtens, Xaveer; Bolk, Jeroen

2013-01-01

We report on a novel integrated approach to obtain dual wavelength emission from a semiconductor laser based on on-chip filtered optical feedback. Using this approach, we show experiments and numerical simulations of dual wavelength emission of a semiconductor ring laser. The filtered optical feedback is realized on-chip by employing two arrayed waveguide gratings to split/recombine light into different wavelength channels. Semiconductor optical amplifiers are placed in the feedback loop in order to control the feedback strength of each wavelength channel independently. By tuning the current injected into each of the amplifiers, we can effectively cancel the gain difference between the wavelength channels due to fabrication and material dichroism, thus resulting in stable dual wavelength emission. We also explore the accuracy needed in the operational parameters to maintain this dual wavelength emission. (letter)

Silicon carbide: A unique platform for metal-oxide-semiconductor physics

Energy Technology Data Exchange (ETDEWEB)

Liu, Gang [Institute for Advanced Materials, Devices and Nanotechnology, Rutgers University, Piscataway, New Jersey 08854 (United States); Tuttle, Blair R. [Department of Physics and Astronomy, Vanderbilt University, Nashville, Tennessee 37235 (United States); Dhar, Sarit [Department of Physics, Auburn University, Auburn, Alabama 36849 (United States)

2015-06-15

A sustainable energy future requires power electronics that can enable significantly higher efficiencies in the generation, distribution, and usage of electrical energy. Silicon carbide (4H-SiC) is one of the most technologically advanced wide bandgap semiconductor that can outperform conventional silicon in terms of power handling, maximum operating temperature, and power conversion efficiency in power modules. While SiC Schottky diode is a mature technology, SiC power Metal Oxide Semiconductor Field Effect Transistors are relatively novel and there is large room for performance improvement. Specifically, major initiatives are under way to improve the inversion channel mobility and gate oxide stability in order to further reduce the on-resistance and enhance the gate reliability. Both problems relate to the defects near the SiO{sub 2}/SiC interface, which have been the focus of intensive studies for more than a decade. Here we review research on the SiC MOS physics and technology, including its brief history, the state-of-art, and the latest progress in this field. We focus on the two main scientific problems, namely, low channel mobility and bias temperature instability. The possible mechanisms behind these issues are discussed at the device physics level as well as the atomic scale, with the support of published physical analysis and theoretical studies results. Some of the most exciting recent progress in interface engineering for improving the channel mobility and fundamental understanding of channel transport is reviewed.

Mechanical anomaly impact on metal-oxide-semiconductor capacitors on flexible silicon fabric

KAUST Repository

Ghoneim, Mohamed T.

2014-06-09

We report the impact of mechanical anomaly on high-κ/metal-oxide-semiconductor capacitors built on flexible silicon (100) fabric. The mechanical tests include studying the effect of bending radius up to 5 mm minimum bending radius with respect to breakdown voltage and leakage current of the devices. We also report the effect of continuous mechanical stress on the breakdown voltage over extended periods of times.

Near-chip compliant layer for reducing perimeter stress during assembly process

Energy Technology Data Exchange (ETDEWEB)

Schultz, Mark D.; Takken, Todd E.; Tian, Shurong; Yao, Yuan

2018-03-20

A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

Directory of Open Access Journals (Sweden)

Mitsumasa Koyanagi

2011-02-01

Full Text Available New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D and hetero integration of complementary metal-oxide semiconductors (CMOS and microelectromechanical systems (MEMS. By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

Electronic structure of semiconductor interfaces

Energy Technology Data Exchange (ETDEWEB)

Herman, F

1983-02-01

The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered.

Electronic structure of semiconductor interfaces

International Nuclear Information System (INIS)

Herman, F.

1983-01-01

The study of semiconductor interfaces is one of the most active and exciting areas of current semiconductor research. Because interfaces play a vital role in modern semiconductor technology (integrated circuits, heterojunction lasers, solar cells, infrared detectors, etc.), there is a strong incentive to understand interface properties at a fundamental level and advance existing technology thereby. At the same time, technological advances such as molecular beam epitaxy have paved the way for the fabrication of semiconductor heterojunctions and superlattices of novel design which exhibit unusual electronic, optical, and magnetic properties and offer unique opportunities for fundamental scientific research. A general perspective on this subject is offered treating such topics as the atomic and electronic structure of semiconductor surfaces and interfaces; oxidation and oxide layers; semiconductor heterojunctions and superlattices; rectifying metal-semiconductor contacts; and interface reactions. Recent progress is emphasized and some future directions are indicated. In addition, the role that large-scale scientific computation has played in furthering our theoretical understanding of semiconductor surfaces and interfaces is discussed. Finally, the nature of theoretical models, and the role they play in describing the physical world is considered. (Author) [pt

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

Science.gov (United States)

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

Influence of semiconductor barrier tunneling on the current-voltage characteristics of tunnel metal-oxide-semiconductor diodes

DEFF Research Database (Denmark)

Nielsen, Otto M.

1983-01-01

of multistep tunneling recombination current and injected minority carrier diffusion current. This can explain the observed values of the diode quality factor n. The results also show that the voltage drop across the oxide Vox is increased with increased NA, with the result that the lowering of the minority...... carrier diode current Jmin is greater than in the usual theory. The conclusion drawn is that the increase in Vox and lowering of Jmin is due to multistep tunneling of majority carriers through the semiconductor barrier. Journal of Applied Physics is copyrighted by The American Institute of Physics.......Current–voltage characteristics have been examined for Al–SiO2–pSi diodes with an interfacial oxide thickness of delta[approximately-equal-to]20 Å. The diodes were fabricated on and oriented substrates with an impurity concentration in the range of NA=1014–1016 cm−3. The results show that for low...

Rapid antibiotic efficacy screening with aluminum oxide nanoporous membrane filter-chip and optical detection system.

Science.gov (United States)

Tsou, Pei-Hsiang; Sreenivasappa, Harini; Hong, Sungmin; Yasuike, Masayuki; Miyamoto, Hiroshi; Nakano, Keiyo; Misawa, Takeyuki; Kameoka, Jun

2010-09-15

We have developed a filter-chip and optical detection system for rapid antibiotic efficacy screening. The filter-chip consisted of a 1-mL reservoir and an anodic aluminum oxide (AAO) nanoporous membrane. Sample solution with liquid growth media, bacteria, and antibiotics was incubated in the reservoir for a specific period of time. The number of live bacteria on the surface of membrane was counted after the incubation with antibiotics and filtration. Using this biosensing system, we have demonstrated a 1-h antibiotic screening for patients' clinical samples, significantly faster than the conventional antibiotic susceptibility tests that typically take more than 24h. This rapid screening nature makes the filter-chip and detection system ideal for tailoring antibiotic treatment to individual patients by reducing the microbial antibiotic resistance, and improving the survival rate for patients suffering from postoperative infections. Published by Elsevier B.V.

Design and evaluation of basic standard encryption algorithm modules using nanosized complementary metal oxide semiconductor molecular circuits

Science.gov (United States)

Masoumi, Massoud; Raissi, Farshid; Ahmadian, Mahmoud; Keshavarzi, Parviz

2006-01-01

We are proposing that the recently proposed semiconductor-nanowire-molecular architecture (CMOL) is an optimum platform to realize encryption algorithms. The basic modules for the advanced encryption standard algorithm (Rijndael) have been designed using CMOL architecture. The performance of this design has been evaluated with respect to chip area and speed. It is observed that CMOL provides considerable improvement over implementation with regular CMOS architecture even with a 20% defect rate. Pseudo-optimum gate placement and routing are provided for Rijndael building blocks and the possibility of designing high speed, attack tolerant and long key encryptions are discussed.

Analysis and simulation of semiconductor devices

CERN Document Server

Selberherr, Siegfried

1984-01-01

The invention of semiconductor devices is a fairly recent one, considering classical time scales in human life. The bipolar transistor was announced in 1947, and the MOS transistor, in a practically usable manner, was demonstrated in 1960. From these beginnings the semiconductor device field has grown rapidly. The first integrated circuits, which contained just a few devices, became commercially available in the early 1960s. Immediately thereafter an evolution has taken place so that today, less than 25 years later, the manufacture of integrated circuits with over 400.000 devices per single chip is possible. Coincident with the growth in semiconductor device development, the literature concerning semiconductor device and technology issues has literally exploded. In the last decade about 50.000 papers have been published on these subjects. The advent of so called Very-Large-Scale-Integration (VLSI) has certainly revealed the need for a better understanding of basic device behavior. The miniaturization of the s...

Design of nanophotonic, hot-electron solar-blind ultraviolet detectors with a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Wang, Zhiyuan; Wang, Xiaoxin; Liu, Jifeng

2014-01-01

Solar-blind ultraviolet (UV) detection refers to photon detection specifically in the wavelength range of 200 nm–320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. The most commonly used solid state devices for this application are wide band gap (WBG) semiconductor photodetectors (Eg > 3.5 eV). However, WBG semiconductors are difficult to grow and integrate with Si readout integrated circuits (ROICs). In this paper, we design a nanophotonic metal-oxide-semiconductor structure on Si for solar-blind UV detectors. Instead of using semiconductors as the active absorber, we use Sn nano-grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between the metal and the n-type Si region upon UV excitation. Moreover, the transported hot electron has an excess kinetic energy >3 eV, large enough to induce impact ionization and generate another free electron in the conduction band of n-Si. This process doubles the quantum efficiency. On the other hand, the large metal/oxide interfacial energy barrier (>3.5 eV) also enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, ∼75% UV absorption and hot electron excitation can be achieved within the mean free path of ∼20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. The simple geometry of the Sn nano-gratings and the MOS structure make it easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices. (paper)

Hysteresis phenomena at metal-semiconductor phase transformation in vanadium oxides

International Nuclear Information System (INIS)

Lanskaya, T.G.; Merkulov, I.A.; Chudnovski , F.A.

1978-01-01

The hysteresis phenomena during the metal-semiconductor phase transformation (MSPT) in vanadium oxides are investigated. It is shown experimentally that the hysteresis effects during MSPT in vanadium oxides are associated not only with the martensite nature of the transformation, but also with activation processes. It is shown that the hysteresis phenomena during MSPT may be described by the distribution function of microregions of the crystal in the phase transformation temperature T 0 and the coercive temperature Tsub(c). An experimental method for constructing this distribution function was worked out. An analysis of the experimental data shows that finely dispersed films are characterized by a wide range of values of T 0 and Tsub(c) (55 deg C 0 <65 deg C, 6 deg C< Tsub(c)<12 deg C). The peculiarities of the optical recording of information on monocrystal and finely dispersed films are considered

Defects in semiconductors

CERN Document Server

Romano, Lucia; Jagadish, Chennupati

2015-01-01

This volume, number 91 in the Semiconductor and Semimetals series, focuses on defects in semiconductors. Defects in semiconductors help to explain several phenomena, from diffusion to getter, and to draw theories on materials' behavior in response to electrical or mechanical fields. The volume includes chapters focusing specifically on electron and proton irradiation of silicon, point defects in zinc oxide and gallium nitride, ion implantation defects and shallow junctions in silicon and germanium, and much more. It will help support students and scientists in their experimental and theoret

Electrosprayed Metal Oxide Semiconductor Films for Sensitive and Selective Detection of Hydrogen Sulfide

Directory of Open Access Journals (Sweden)

Maryam Siadat

2009-11-01

Full Text Available Semiconductor metal oxide films of copper-doped tin oxide (Cu-SnO2, tungsten oxide (WO3 and indium oxide (In2O3 were deposited on a platinum coated alumina substrate employing the electrostatic spray deposition technique (ESD. The morphology studied with scanning electron microscopy (SEM and atomic force microscopy (AFM shows porous homogeneous films comprising uniformly distributed aggregates of nano particles. The X-ray diffraction technique (XRD proves the formation of crystalline phases with no impurities. Besides, the Raman cartographies provided information about the structural homogeneity. Some of the films are highly sensitive to low concentrations of H2S (10 ppm at low operating temperatures (100 and 200 °C and the best response in terms of Rair/Rgas is given by Cu-SnO2 films (2500 followed by WO3 (1200 and In2O3 (75. Moreover, all the films exhibit no cross-sensitivity to other reducing (SO2 or oxidizing (NO2 gases.

Dimensional optimization of nanowire--complementary metal oxide--semiconductor inverter.

Science.gov (United States)

Hashim, Yasir; Sidek, Othman

2013-01-01

This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.

Miniature interferometer for refractive index measurement in microfluidic chip

Science.gov (United States)

Chen, Minghui; Geiser, Martial; Truffer, Frederic; Song, Chengli

2012-12-01

The design and development of the miniaturized interferometer for measurement of the refractive index or concentration of sub-microliter volume aqueous solution in microfludic chip is presented. It is manifested by a successful measurement of the refractive index of sugar-water solution, by utilizing a laser diode for light source and the small robust instrumentation for practical implementation. Theoretically, the measurement principle and the feasibility of the system are analyzed. Experimental device is constructed with a diode laser, lens, two optical plate and a complementary metal oxide semiconductor (CMOS). Through measuring the positional changes of the interference fringes, the refractive index change are retrieved. A refractive index change of 10-4 is inferred from the measured image data. The entire system is approximately the size of half and a deck of cards and can operate on battery power for long time.

Modelling of Leakage Current Through Double Dielectric Gate Stack in Metal Oxide Semiconductor Capacitor

International Nuclear Information System (INIS)

Fatimah A Noor; Mikrajuddin Abdullah; Sukirno; Khairurrijal

2008-01-01

In this paper, we have derived analytical expression of leakage current through double barriers in Metal Oxide Semiconductor (MOS) capacitor. Initially, electron transmittance through the MOS capacitor was derived by including the coupling between the transverse and longitudinal energies. The transmittance was then employed to obtain leakage current through the double barrier. In this model, we observed the effect of electron velocity due to the coupling effect and the oxide thickness to the leakage current. The calculated results showed that the leakage current decreases as the electron velocity increases. (author)

Radiation effects in metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Collins, J.L.

1987-01-01

The effects of various radiations on commercially made Al-SiO 2 -Si Capacitors (MOSCs) have been investigated. Intrinsic dielectric breakdown in MOSCs has been shown to be a two-stage process dominated by charge injection in a pre-breakdown stage; this is associated with localised high-field injection of carriers from the semiconductor substrate to interfacial and bulk charge traps which, it is proposed, leads to the formation of conducting channels through the dielectric with breakdown occurring as a result of the dissipation of the conduction band energy. A study of radiation-induced dielectric breakdown has revealed the possibility of anomalous hot-electron injection to an excess of bulk oxide traps in the ionization channel produced by very heavily ionizing radiation, which leads to intrinsic breakdown in high-field stressed devices. This is interpreted in terms of a modified model for radiation-induced dielectric breakdown based upon the primary dependence of breakdown on charge injection rather than high-field mechanisms. A detailed investigation of charge trapping and interface state generation due to various radiations has revealed evidence of neutron induced interface states, and the generation of positive oxide charge in devices due to all the radiations tested. The greater the linear energy transfer of the radiation, the greater the magnitude of charge trapped in the oxide and the number of interface states generated. This is interpreted in terms of Si-H and Si-OH bond-breaking at the Si-SiO 2 interface which is enhanced by charge carrier transfer to the interface and by anomalous charge injection to compensate for the excess of charge carriers created by the radiation. (author)

Signatures of Quantized Energy States in Solution-Processed Ultrathin Layers of Metal-Oxide Semiconductors and Their Devices

KAUST Repository

Labram, John G.; Lin, Yenhung; Zhao, Kui; Li, Ruipeng; Thomas, Stuart R.; Semple, James; Androulidaki, Maria; Sygellou, Lamprini; McLachlan, Martyn A.; Stratakis, Emmanuel; Amassian, Aram; Anthopoulos, Thomas D.

2015-01-01

reports of the growth of uniform, ultrathin (<5 nm) metal-oxide semiconductors from solution, however, have potentially opened the door to such phenomena manifesting themselves. Here, a theoretical framework is developed for energy quantization

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Science.gov (United States)

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

Science.gov (United States)

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Microelectronics used for Semiconductor Imaging Detectors

CERN Document Server

Heijne, Erik H M

2010-01-01

Semiconductor crystal technology, microelectronics developments and nuclear particle detection have been in a relation of symbiosis, all the way from the beginning. The increase of complexity in electronics chips can now be applied to obtain much more information on the incident nuclear radiation. Some basic technologies are described, in order to acquire insight in possibilities and limitations for the most recent detectors.

Dry etching technology for semiconductors

CERN Document Server

Nojiri, Kazuo

2015-01-01

This book is a must-have reference to dry etching technology for semiconductors, which will enable engineers to develop new etching processes for further miniaturization and integration of semiconductor integrated circuits.  The author describes the device manufacturing flow, and explains in which part of the flow dry etching is actually used. The content is designed as a practical guide for engineers working at chip makers, equipment suppliers and materials suppliers, and university students studying plasma, focusing on the topics they need most, such as detailed etching processes for each material (Si, SiO2, Metal etc) used in semiconductor devices, etching equipment used in manufacturing fabs, explanation of why a particular plasma source and gas chemistry are used for the etching of each material, and how to develop etching processes.  The latest, key technologies are also described, such as 3D IC Etching, Dual Damascene Etching, Low-k Etching, Hi-k/Metal Gate Etching, FinFET Etching, Double Patterning ...

Legal Protection on IP Cores for System-on-Chip Designs

Science.gov (United States)

Kinoshita, Takahiko

The current semiconductor industry has shifted from vertical integrated model to horizontal specialization model in term of integrated circuit manufacturing. In this circumstance, IP cores as solutions for System-on-Chip (SoC) have become increasingly important for semiconductor business. This paper examines to what extent IP cores of SoC effectively can be protected by current intellectual property system including integrated circuit layout design law, patent law, design law, copyright law and unfair competition prevention act.

Selective, electrochemical etching of a semiconductor

Science.gov (United States)

Dahal, Rajendra P.; Bhat, Ishwara B.; Chow, Tat-Sing

2018-03-20

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

Integrated microelectronic capacitive readout subsystem for lab-on-a-chip applications

International Nuclear Information System (INIS)

Spathis, Christos; Georgakopoulou, Konstantina; Petrellis, Nikos; Efstathiou, Konstantinos; Birbas, Alexios

2014-01-01

A mixed-signal capacitive biosensor readout system is presented with its main readout functionality embedded in an integrated circuit, compatible with complementary metal oxide semiconductor-type biosensors. The system modularity allows its usage as a consumable since it eventually leads to a system-on-chip where sensor and readout circuitry are hosted on the same die. In this work, a constant current source is used for measuring the input capacitance. Compared to most capacitive biosensor readout circuits, this method offers the convenience of adjusting both the range and the resolution, depending on the requirements dictated by the application. The chip consumes less than 5 mW of power and the die area is 0.06 mm 2 . It shows a broad input capacitance range (capable of measuring bio-capacitances from 6 pF to 9.8 nF), configurable resolution (down to 1 fF), robustness to various biological experiments and good linearity. The integrated nature of the readout system is proven to be sufficient both for one-time in situ (consumable-type) bio-measurements and its incorporation into a point-of-care system. (paper)

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Science.gov (United States)

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-09-26

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

Energy Technology Data Exchange (ETDEWEB)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany); Miehler, Dominik [Department of Materials Science and Engineering, Friedrich-Alexander-Universität Erlangen-Nürnberg, Erlangen D-91058 (Germany); Zaumseil, Jana, E-mail: zaumseil@uni-heidelberg.de [Institute for Physical Chemistry, Universität Heidelberg, Heidelberg D-69120 (Germany)

2015-08-24

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.

75 FR 9438 - Samsung Austin Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation...

Science.gov (United States)

2010-03-02

... Semiconductor, LLC, DRAM Fab 1, a Subsidiary of Samsung Electronics Corporation, Including On-Site Leased... Semiconductor, LLC, a subsidiary of Samsung Electronics Corporation, DRAM Fab 1, including on-site leased.... The workers are engaged in activities related to the production of DRAM chips for use in electronics...

A divalent rare earth oxide semiconductor: Yttrium monoxide

Energy Technology Data Exchange (ETDEWEB)

Kaminaga, Kenichi; Sei, Ryosuke [Department of Chemistry, The University of Tokyo, Tokyo 113-0033 (Japan); Department of Chemistry, Tohoku University, Sendai 980-8578 (Japan); Hayashi, Kouichi [Department of Environmental and Materials Engineering, Nagoya Institute of Technology, Nagoya 466-8555 (Japan); Happo, Naohisa [School of Information Sciences, Hiroshima City University, Hiroshima 731-3194 (Japan); Tajiri, Hiroo [Japan Synchrotron Radiation Research Institute (JASRI)/SPring-8, Sayo 679-5198 (Japan); Oka, Daichi; Fukumura, Tomoteru, E-mail: tomoteru.fukumura.e4@tohoku.ac.jp [Department of Chemistry, Tohoku University, Sendai 980-8578 (Japan); Hasegawa, Tetsuya [Department of Chemistry, The University of Tokyo, Tokyo 113-0033 (Japan)

2016-03-21

Rare earth oxides are usually widegap insulators like Y{sub 2}O{sub 3} with closed shell trivalent rare earth ions. In this study, solid phase rock salt structure yttrium monoxide, YO, with unusual valence of Y{sup 2+} (4d{sup 1}) was synthesized in a form of epitaxial thin film by pulsed laser deposition method. YO has been recognized as gaseous phase in previous studies. In contrast with Y{sub 2}O{sub 3}, YO was dark-brown colored and narrow gap semiconductor. The tunable electrical conductivity ranging from 10{sup −1} to 10{sup 3} Ω{sup −1 }cm{sup −1} was attributed to the presence of oxygen vacancies serving as electron donor. Weak antilocalization behavior observed in magnetoresistance indicated significant role of spin-orbit coupling as a manifestation of 4d electron carrier.

Photocatalytic oxidation of organic compounds in a hybrid system composed of a molecular catalyst and visible light-absorbing semiconductor.

Science.gov (United States)

Zhou, Xu; Li, Fei; Li, Xiaona; Li, Hua; Wang, Yong; Sun, Licheng

2015-01-14

Photocatalytic oxidation of organic compounds proceeded efficiently in a hybrid system with ruthenium aqua complexes as catalysts, BiVO4 as a light absorber, [Co(NH3)5Cl](2+) as a sacrificial electron acceptor and water as an oxygen source. The photogenerated holes in the semiconductor are used to oxidize molecular catalysts into the high-valent Ru(IV)=O intermediates for 2e(-) oxidation.

Key techniques for space-based solar pumped semiconductor lasers

Science.gov (United States)

He, Yang; Xiong, Sheng-jun; Liu, Xiao-long; Han, Wei-hua

2014-12-01

In space, the absence of atmospheric turbulence, absorption, dispersion and aerosol factors on laser transmission. Therefore, space-based laser has important values in satellite communication, satellite attitude controlling, space debris clearing, and long distance energy transmission, etc. On the other hand, solar energy is a kind of clean and renewable resources, the average intensity of solar irradiation on the earth is 1353W/m2, and it is even higher in space. Therefore, the space-based solar pumped lasers has attracted much research in recent years, most research focuses on solar pumped solid state lasers and solar pumped fiber lasers. The two lasing principle is based on stimulated emission of the rare earth ions such as Nd, Yb, Cr. The rare earth ions absorb light only in narrow bands. This leads to inefficient absorption of the broad-band solar spectrum, and increases the system heating load, which make the system solar to laser power conversion efficiency very low. As a solar pumped semiconductor lasers could absorb all photons with energy greater than the bandgap. Thus, solar pumped semiconductor lasers could have considerably higher efficiencies than other solar pumped lasers. Besides, solar pumped semiconductor lasers has smaller volume chip, simpler structure and better heat dissipation, it can be mounted on a small satellite platform, can compose satellite array, which can greatly improve the output power of the system, and have flexible character. This paper summarizes the research progress of space-based solar pumped semiconductor lasers, analyses of the key technologies based on several application areas, including the processing of semiconductor chip, the design of small and efficient solar condenser, and the cooling system of lasers, etc. We conclude that the solar pumped vertical cavity surface-emitting semiconductor lasers will have a wide application prospects in the space.

Direct observation of both contact and remote oxygen scavenging of GeO2 in a metal-oxide-semiconductor stack

International Nuclear Information System (INIS)

Fadida, S.; Shekhter, P.; Eizenberg, M.; Cvetko, D.; Floreano, L.; Verdini, A.; Nyns, L.; Van Elshocht, S.; Kymissis, I.

2014-01-01

In the path to incorporating Ge based metal-oxide-semiconductor into modern nano-electronics, one of the main issues is the oxide-semiconductor interface quality. Here, the reactivity of Ti on Ge stacks and the scavenging effect of Ti were studied using synchrotron X-ray photoelectron spectroscopy measurements, with an in-situ metal deposition and high resolution transmission electron microscopy imaging. Oxygen removal from the Ge surface was observed both in direct contact as well as remotely through an Al 2 O 3 layer. The scavenging effect was studied in situ at room temperature and after annealing. We find that the reactivity of Ti can be utilized for improved scaling of Ge based devices.

Oxide Ferromagnetic Semiconductors for Spin-Electronic Transprt

International Nuclear Information System (INIS)

Pandey, R.K.

2008-01-01

The objective of this research was to investigate the viability of oxide magnetic semiconductors as potential materials for spintronics. We identified some members of the solid solution series of ilmenite (FeTiO3) and hematite (Fe2O3), abbreviated as (IH) for simplicity, for our investigations based on their ferromagnetic and semiconducting properties. With this objective in focus we limited our investigations to the following members of the modified Fe-titanates: IH33 (ilmenitehematite with 33 atomic percent hematite), IH45 (ilmenite-hematite with 45 atomic percent hematite), Mn-substituted ilmenite (Mn-FeTiO3), and Mn-substituted pseudobrookite (Mn- Fe2TiO5). All of them are: (1) wide bandgap semiconductors with band gaps ranging in values between 2.5 to 3.5 eV; (2) n-type semiconductors; (3) they exhibit well defined magnetic hysteresis loops and (4) their magnetic Curie points are greater than 400K. Ceramic, film and single crystal samples were studied and based on their properties we produced varistors (also known as voltage dependent resistors) for microelectronic circuit protection from power surges, three-terminal microelectronic devices capable of generating bipolar currents, and an integrated structured device with controlled magnetic switching of spins. Eleven refereed journal papers, three refereed conference papers and three invention disclosures resulted from our investigations. We also presented invited papers in three international conferences and one national conference. Furthermore two students graduated with Ph.D. degrees, three with M.S. degrees and one with B.S. degree. Also two post-doctoral fellows were actively involved in this research. We established the radiation hardness of our devices in collaboration with a colleague in an HBCU institution, at the Cyclotron Center at Texas A and M University, and at DOE National Labs (Los Alamos and Brookhaven). It is to be appreciated that we met most of our goals and expanded vastly the scope of

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

KAUST Repository

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, Mohamed N.; Wang, Q. X.; Alshareef, Husam N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling

Chip-based generation of carbon nanodots via electrochemical oxidation of screen printed carbon electrodes and the applications for efficient cell imaging and electrochemiluminescence enhancement.

Science.gov (United States)

Xu, Yuanhong; Liu, Jingquan; Zhang, Jizhen; Zong, Xidan; Jia, Xiaofang; Li, Dan; Wang, Erkang

2015-06-07

A portable lab-on-a-chip methodology to generate ionic liquid-functionalized carbon nanodots (CNDs) was developed via electrochemical oxidation of screen printed carbon electrodes. The CNDs can be successfully applied for efficient cell imaging and solid-state electrochemiluminescence sensor fabrication on the paper-based chips.

Photonics-on-a-chip: recent advances in integrated waveguides as enabling detection elements for real-world, lab-on-a-chip biosensing applications.

Science.gov (United States)

Washburn, Adam L; Bailey, Ryan C

2011-01-21

By leveraging advances in semiconductor microfabrication technologies, chip-integrated optical biosensors are poised to make an impact as scalable and multiplexable bioanalytical measurement tools for lab-on-a-chip applications. In particular, waveguide-based optical sensing technology appears to be exceptionally amenable to chip integration and miniaturization, and, as a result, the recent literature is replete with examples of chip-integrated waveguide sensing platforms developed to address a wide range of contemporary analytical challenges. As an overview of the most recent advances within this dynamic field, this review highlights work from the last 2-3 years in the areas of grating-coupled, interferometric, photonic crystal, and microresonator waveguide sensors. With a focus towards device integration, particular emphasis is placed on demonstrations of biosensing using these technologies within microfluidically controlled environments. In addition, examples of multiplexed detection and sensing within complex matrices--important features for real-world applicability--are given special attention.

Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

International Nuclear Information System (INIS)

Chakraborty, Gargi; Sarkar, C K; Lu, X B; Dai, J Y

2008-01-01

The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

Science.gov (United States)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

Science.gov (United States)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

A compact PE memory for vision chips

International Nuclear Information System (INIS)

Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

2014-01-01

This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

Solar hydrogen production with semiconductor metal oxides: new directions in experiment and theory

DEFF Research Database (Denmark)

Valdes, Alvaro; Brillet, Jeremie; Graetzel, Michael

2012-01-01

An overview of a collaborative experimental and theoretical effort toward efficient hydrogen production via photoelectrochemical splitting of water into di-hydrogen and di-oxygen is presented here. We present state-of-the-art experimental studies using hematite and TiO2 functionalized with gold n...... nanoparticles as photoanode materials, and theoretical studies on electro and photo-catalysis of water on a range of metal oxide semiconductor materials, including recently developed implementation of self-interaction corrected energy functionals....

Chip compacting press; Jido kirikuzu asshukuki

Energy Technology Data Exchange (ETDEWEB)

Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

1998-08-15

The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

Effects of oxide traps, interface traps, and ''border traps'' on metal-oxide-semiconductor devices

International Nuclear Information System (INIS)

Fleetwood, D.M.; Winokur, P.S.; Reber, R.A. Jr.; Meisenheimer, T.L.; Schwank, J.R.; Shaneyfelt, M.R.; Riewe, L.C.

1993-01-01

We have identified several features of the 1/f noise and radiation response of metal-oxide-semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ''oxide traps'' are simply defects in the SiO 2 layer of the MOS structure, and ''interface traps'' are defects at the Si/SiO 2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ''fixed states'' are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ''switching states'' can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface traps or near-interfacial oxide traps that can communicate with the Si, i.e., ''border traps'' [D. M. Fleetwood, IEEE Trans. Nucl. Sci. NS-39, 269 (1992)]. The effective density of border traps depends on the time scale and bias conditions of the measurements. We show the revised nomenclature can provide focus to discussions of the buildup and annealing of radiation-induced charge in non-radiation-hardened MOS transistors, and to changes in the 1/f noise of MOS devices through irradiation and elevated-temperature annealing

A study on the optical parts for a semiconductor laser module

Energy Technology Data Exchange (ETDEWEB)

Oh, Jun-Girl; Lee, Dong-Kil; Kim, Yang-Gyu; Lee, Kwang-Hoon; Park, Young-Sik [Korea Photonics Technology Institute, Gwangju (Korea, Republic of); Jang, Kwang-Ho [Hanvit Optoline, Gwangju (Korea, Republic of); Kang, Seung-Goo [COSET, Gwangju (Korea, Republic of)

2014-11-15

A semiconductor laser module consists of a LD (laser diode) chip that generates a laser beam, two cylindrical lenses to collimate the laser beam, a high-reflection mirror to produce a large output by collecting the laser beam, a collimator lens to guide the laser beam to an optical fiber and a protection filter to block reflected laser light that might damage the LD chip. The cylindrical lenses used in a semiconductor laser module are defined as FACs (fast axis collimators) and SACs (slow axis collimators) and are attached to the system module to control the shape of the laser beam. The FAC lens and the SAC lens are made of a glass material to protect the lenses from thermal deformation. In addition, they have aspheric shapes to improve optical performances. This paper presents a mold core grinding process for an asymmetrical aspheric lens and a GMP (glass molding press), what can be used to make aspheric cylindrical lenses for use as FACs or SACs, and a protection filter made by using IAD (ion-beam-assisted deposition). Finally, we developed the aspheric cylindrical lenses and the protection filter for a 10-W semiconductor laser module.

Optically coupled semiconductor device

Energy Technology Data Exchange (ETDEWEB)

Kumagaya, Naoki

1988-11-18

This invention concerns an optically coupled semiconductor device using the light as input signal and a MOS transistor for the output side in order to control on-off of the output side by the input signal which is insulated from the output. Concerning this sort of element, when a MOS transistor and a load resistance are planned to be accumulated on the same chip, a resistor and control of impurity concentration of the channel, etc. become necessary despite that the only formation of a simple P-N junction is enough, for a solar cell, hence cost reduction thereof cannot be done. In order to remove this defect, this invention offers an optically coupled semiconductor device featuring that two solar cells are connected in reverse parallel between the gate sources of the output MOS transistors and an operational light emitting element is individually set facing a respective solar cell. 4 figs.

Photochemistry Aspects of the Laser Pyrolysis Addressing the Preparation of Oxide Semiconductor Photocatalysts

Directory of Open Access Journals (Sweden)

R. Alexandrescu

2008-01-01

Full Text Available The laser pyrolysis is a powerful and a versatile tool for the gas-phase synthesis of nanoparticles. In this paper, some fundamental and applicative characteristics of this technique are outlined and recent results obtained in the preparation of gamma iron oxide (γ-Fe2O3 and titania (TiO2 semiconductor nanostructures are illustrated. Nanosized iron oxide particles (4 to 9 nm diameter values have been directly synthesized by the laser-induced pyrolysis of a mixture containing iron pentacarbonyl/air (as oxidizer/ethylene (as sensitizer. Temperature-dependent Mossbauer spectroscopy shows that mainly maghemite is present in the sample obtained at higher laser power. The use of selected Fe2O3 samples for the preparation of water-dispersed magnetic nanofluids is also discussed. TiO2 nanoparticles comprising a mixture of anatase and rutile phases were synthesized via the laser pyrolysis of TiCl4- (vapors based gas-phase mixtures. High precursor concentration of the oxidizer was found to favor the prevalent anatase phase (about 90% in the titania nanopowders.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

Directory of Open Access Journals (Sweden)

De-Hao Lu

2010-11-01

Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

International Nuclear Information System (INIS)

Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

2009-01-01

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

Institute of Scientific and Technical Information of China (English)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (Ron,sp),whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region,is proposed.The theoretical limit of its Ron,sp is deduced,the influence of structure parameters on the breakdown voltage (BV) and Ron,sp are investigated,and the optimized results with BV of 83 V and Ron,sp of 54 mΩ.mm2 are obtained.Simulations show that the inhomogencous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET)has a superior “Ron,sp/BV” trade-off to the conventional VDMOS (a 38％ reduction of Ron,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10％ reduction of Ron,sp with the same BV).The inhomogeneous-floatingislands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET.Its reverse recovery peak current,reverse recovery time and reverse recovery charge are about 50,80 and 40％ of those of the superjunction MOSFET,respectively.

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

Directory of Open Access Journals (Sweden)

Jong Woo Jin

2016-08-01

Full Text Available Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (VTH in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative VTH shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H2O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

Interpreting anomalies observed in oxide semiconductor TFTs under negative and positive bias stress

Energy Technology Data Exchange (ETDEWEB)

Jin, Jong Woo [LPICM, CNRS, Ecole Polytechnique, Université Paris Saclay, 91128, Palaiseau (France); Nathan, Arokia, E-mail: an299@cam.ac.uk [Engineering Department, University of Cambridge, Cambridge, CB3 0FA (United Kingdom); Barquinha, Pedro; Pereira, Luís; Fortunato, Elvira; Martins, Rodrigo [i3N/CENIMAT, Department of Materials Science, Faculty of Science and Technology, Universidade NOVA de Lisboa and CEMOP/UNINOVA, Campus de Caparica, 2829-516 Caparica (Portugal); Cobb, Brian [Holst Centre/TNO, Eindhoven, 5656 AE (Netherlands)

2016-08-15

Oxide semiconductor thin-film transistors can show anomalous behavior under bias stress. Two types of anomalies are discussed in this paper. The first is the shift in threshold voltage (V{sub TH}) in a direction opposite to the applied bias stress, and highly dependent on gate dielectric material. We attribute this to charge trapping/detrapping and charge migration within the gate dielectric. We emphasize the fundamental difference between trapping/detrapping events occurring at the semiconductor/dielectric interface and those occurring at gate/dielectric interface, and show that charge migration is essential to explain the first anomaly. We model charge migration in terms of the non-instantaneous polarization density. The second type of anomaly is negative V{sub TH} shift under high positive bias stress, with logarithmic evolution in time. This can be argued as electron-donating reactions involving H{sub 2}O molecules or derived species, with a reaction rate exponentially accelerated by positive gate bias and exponentially decreased by the number of reactions already occurred.

A CMOS analog front-end chip for amperometric electrochemical sensors

International Nuclear Information System (INIS)

Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

2015-01-01

This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

A scalable neural chip with synaptic electronics using CMOS integrated memristors

International Nuclear Information System (INIS)

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-01-01

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal–oxide–semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior. (paper)

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

Science.gov (United States)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

Local anodic oxidation by AFM tip developed for novel semiconductor nanodevices

International Nuclear Information System (INIS)

Cambel, Vladimir; Martaus, Jozef; Soltys, Jan; Kudela, Robert; Gregusova, Dagmar

2008-01-01

The local anodic oxidation (LAO) by the tip of atomic force microscope (AFM) is used for fabrication of nanometer-scaled structures and devices. We study the technology of LAO applied to semiconductor heterostructures, theoretically and experimentally as well. The goal is to improve the LAO process itself, i.e., to create narrow LAO lines that form high-energy barriers in the plane with the 2D electron gas. In the first part we show the electric field distribution in the system tip-sample during LAO. For samples with low-conductive cap layer the maximum electric field is shifted apart the tip apex, which leads to wide oxide lines. Our Monte Carlo (MC) calculations show how the height of the energy barrier in the system depends on the geometry of the created lines (trenches), and on voltage applied to the structure. Based on the calculations, we have proposed a novel LAO technology and applied it to InGaP/AlGaAs/GaAs heterostructure with doping layer only 6 nm beneath the surface. The doping layer can be oxidized easily by the AFM tip in this case, and the oxide objects can be removed by several etchants. This approach to the LAO technology leads to narrow LAO trenches (∼60 nm) and to energy barriers high enough for room- and low-temperature applications

Chips with everything

CERN Document Server

CERN. Geneva

2007-01-01

In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

Ergonomic risk factors of work processes in the semiconductor industry in Peninsular Malaysia.

Science.gov (United States)

Chee, Heng-Leng; Rampal, Krishna Gopal; Chandrasakaran, Abherhame

2004-07-01

A cross-sectional survey of semiconductor factories was conducted to identify the ergonomic risk factors in the work processes, the prevalence of body pain among workers, and the relationship between body pain and work processes. A total of 906 women semiconductor workers took part in the study. In wafer preparation and polishing, a combination of lifting weights and prolonged standing might have led to high pain prevalences in the low back (35.0% wafer preparation, 41.7% wafer polishing) and lower limbs (90.0% wafer preparation, 66.7% wafer polishing). Semiconductor front of line workers, who mostly walked around to operate machines in clean rooms, had the lowest prevalences of body pain. Semiconductor assembly middle of line workers, especially the molding workers, who did frequent lifting, had high pain prevalences in the neck/shoulders (54.8%) and upper back (43.5 %). In the semiconductor assembly end of line work section, chip inspection workers who were exposed to prolonged sitting without back support had high prevalences of neck/shoulder (62.2%) and upper back pain (50.0%), while chip testing workers who had to climb steps to load units had a high prevalence of lower limb pain (68.0%). Workers in the assembly of electronic components, carrying out repetitive tasks with hands and fingers, and standing in awkward postures had high pain prevalences in the neck/shoulders (61.5%), arms (38.5%), and hands/wrists (30.8%).

New approach to local anodic oxidation of semiconductor heterostructures

International Nuclear Information System (INIS)

Martaus, Jozef; Gregusova, Dagmar; Cambel, Vladimir; Kudela, Robert; Soltys, Jan

2008-01-01

We have experimentally explored a new approach to local anodic oxidation (LAO) of a semiconductor heterostructures by means of atomic force microscopy (AFM). We have applied LAO to an InGaP/AlGaAs/GaAs heterostructure. Although LAO is usually applied to oxidize GaAs/AlGaAs/GaAs-based heterostructures, the use of the InGaP/AlGaAs/GaAs system is more advantageous. The difference lies in the use of different cap layer materials: Unlike GaAs, InGaP acts like a barrier material with respect to the underlying AlGaAs layer and has almost one order of magnitude lower density of surface states than GaAs. Consequently, the InGaP/AlGaAs/GaAs heterostructure had the remote Si-δ doping layer only 6.5 nm beneath the surface and the two-dimensional electron gas (2DEG) was confined only 23.5 nm beneath the surface. Moreover, InGaP unaffected by LAO is a very durable material in various etchants and allows us to repeatedly remove thin portions of the underlying AlGaAs layer via wet etching. This approach influences LAO technology fundamentally: LAO was used only to oxidize InGaP cap layer to define very narrow (∼50 nm) patterns. Subsequent wet etching was used to form very narrow and high-energy barriers in the 2DEG patterns. This new approach is promising for the development of future nano-devices operated both at low and high temperatures

Integration of microelectronic chips in microfluidic systems on printed circuit board

International Nuclear Information System (INIS)

Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

2012-01-01

A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

Directory of Open Access Journals (Sweden)

Guo-Ming Sung

2018-01-01

Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

Science.gov (United States)

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

Accuracy of dielectric-dependent hybrid functionals in the prediction of optoelectronic properties of metal oxide semiconductors: a comprehensive comparison with many-body GW and experiments

Science.gov (United States)

Gerosa, M.; E Bottani, C.; Di Valentin, C.; Onida, G.; Pacchioni, G.

2018-01-01

Understanding the electronic structure of metal oxide semiconductors is crucial to their numerous technological applications, such as photoelectrochemical water splitting and solar cells. The needed experimental and theoretical knowledge goes beyond that of pristine bulk crystals, and must include the effects of surfaces and interfaces, as well as those due to the presence of intrinsic defects (e.g. oxygen vacancies), or dopants for band engineering. In this review, we present an account of the recent efforts in predicting and understanding the optoelectronic properties of oxides using ab initio theoretical methods. In particular, we discuss the performance of recently developed dielectric-dependent hybrid functionals, providing a comparison against the results of many-body GW calculations, including G 0 W 0 as well as more refined approaches, such as quasiparticle self-consistent GW. We summarize results in the recent literature for the band gap, the band level alignment at surfaces, and optical transition energies in defective oxides, including wide gap oxide semiconductors and transition metal oxides. Correlated transition metal oxides are also discussed. For each method, we describe successes and drawbacks, emphasizing the challenges faced by the development of improved theoretical approaches. The theoretical section is preceded by a critical overview of the main experimental techniques needed to characterize the optoelectronic properties of semiconductors, including absorption and reflection spectroscopy, photoemission, and scanning tunneling spectroscopy (STS).

Gigabit chips: A case history of a transfer of federal technology

Energy Technology Data Exchange (ETDEWEB)

Marcuse, W.

1987-01-01

This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs. (JDH)

Gigabit chips: A case history of a transfer of federal technology

International Nuclear Information System (INIS)

Marcuse, W.

1987-01-01

This report discusses the need for industry/government cooperation in developing new semiconductor technology. In order to increase memory density of chips from 1M bit, it is necessary to use a process other than optical lithography for production. The technique considered here is x-ray lithography. Industry is currently found to be unwilling or unable to finance research into this technology. If US industry is to remain competitive in the world semiconductor market, it is concluded that the government must cooperate and support work in this area. 16 refs

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Optically induced bistable states in metal/tunnel-oxide/semiconductor /MTOS/ junctions

Science.gov (United States)

Lai, S. K.; Dressendorfer, P. V.; Ma, T. P.; Barker, R. C.

1981-01-01

A new switching phenomenon in metal-oxide semiconductor tunnel junction has been discovered. With a sufficiently large negative bias applied to the electrode, incident visible light of intensity greater than about 1 microW/sq cm causes the reverse-biased junction to switch from a low-current to a high-current state. It is believed that hot-electron-induced impact ionization provides the positive feedback necessary for switching, and causes the junction to remain in its high-current state after the optical excitation is removed. The junction may be switched back to the low-current state electrically. The basic junction characteristics have been measured, and a simple model for the switching phenomenon has been developed.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

Directory of Open Access Journals (Sweden)

Shojan P. Pavunny

2014-03-01

Full Text Available A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS, bipolar (Bi and BiCMOS chips applications, is presented in this review article.

Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

OpenAIRE

Goel, Sandeep Kumar

2005-01-01

Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto

2013-02-12

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

KAUST Repository

Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

2013-01-01

In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

Feigenbaum scenario in the dynamics of a metal-oxide semiconductor heterostructure under harmonic perturbation. Golden mean criticality

International Nuclear Information System (INIS)

Cristescu, C.P.; Mereu, B.; Stan, Cristina; Agop, M.

2009-01-01

Experimental investigations and theoretical analysis on the dynamics of a metal-oxide semiconductor heterostructure used as nonlinear capacity in a series RLC electric circuit are presented. A harmonic voltage perturbation can induce various nonlinear behaviours, particularly evolution to chaos by period doubling and torus destabilization. In this work we focus on the change in dynamics induced by a sinusoidal driving with constant frequency and variable amplitude. Theoretical treatment based on the microscopic mechanisms involved led us to a dynamic system with a piecewise behaviour. Consequently, a model consisting of a nonlinear oscillator described by a piecewise second order ordinary differential equation is proposed. This kind of treatment is required by the asymmetry in the behaviour of the metal-oxide semiconductor with respect to the polarization of the perturbing voltage. The dynamics of the theoretical model is in good agreement with the experimental results. A connection with El Naschie's E-infinity space-time is established based on the interpretation of our experimental results as evidence of the importance of the golden mean criticality in the microscopic world.

Integration of Solar Cells on Top of CMOS Chips - Part II: CIGS Solar Cells

NARCIS (Netherlands)

Lu, J.; Liu, Wei; Kovalgin, Alexeij Y.; Sun, Yun; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with copper indium gallium (di)selenide (CIGS) solar cells. Solar cells are manufactured directly on unpackaged CMOS chips. The microchips maintain comparable electronic performance,

A comparative study of semiconductor-based plasmonic metamaterials

DEFF Research Database (Denmark)

Naik, Gururaj V.; Boltasseva, Alexandra

2011-01-01

and very large negative real permittivity values, and in addition, their optical properties cannot be tuned. These issues that put severe constraints on the device applications of MMs could be overcome if semiconductors are used as plasmonic materials instead of metals. Heavily doped, wide bandgap oxide...... semiconductors could exhibit both a small negative real permittivity and relatively small losses in the NIR. Heavily doped oxides of zinc and indium were already reported to be good, low loss alternatives to metals in the NIR range. Here, we consider these transparent conducting oxides (TCOs) as alternative...

A novel planar vertical double-diffused metal-oxide-semiconductor field-effect transistor with inhomogeneous floating islands

International Nuclear Information System (INIS)

Ren Min; Li Ze-Hong; Liu Xiao-Long; Xie Jia-Xiong; Deng Guang-Min; Zhang Bo

2011-01-01

A novel planar vertical double-diffused metal-oxide-semiconductor (VDMOS) structure with an ultra-low specific on-resistance (R on,sp ), whose distinctive feature is the use of inhomogeneous floating p-islands in the n-drift region, is proposed. The theoretical limit of its R on,sp is deduced, the influence of structure parameters on the breakdown voltage (BV) and R on,sp are investigated, and the optimized results with BV of 83 V and R on,sp of 54 mΩ·mm 2 are obtained. Simulations show that the inhomogeneous-floating-islands metal-oxide-semiconductor field-effect transistor (MOSFET) has a superior 'R on,sp /BV' trade-off to the conventional VDMOS (a 38% reduction of R on,sp with the same BV) and the homogeneous-floating-islands MOSFET (a 10% reduction of R on,sp with the same BV). The inhomogeneous-floating-islands MOSFET also has a much better body-diode characteristic than the superjunction MOSFET. Its reverse recovery peak current, reverse recovery time and reverse recovery charge are about 50, 80 and 40% of those of the superjunction MOSFET, respectively. (interdisciplinary physics and related areas of science and technology)

Oxidized Mn:Ge magnetic semiconductor: Observation of anomalous Hall effect and large magnetoresistance

Science.gov (United States)

Duc Dung, Dang; Choi, Jiyoun; Feng, Wuwei; Cao Khang, Nguyen; Cho, Sunglae

2018-03-01

We report on the structural and magneto-transport properties of the as-grown and oxidized Mn:Ge magnetic semiconductors. Based on X-ray diffraction and X-ray photoelectron spectroscopy results, the samples annealed at 650 and 700 °C became fully oxidized and the chemical binding energies of Mn was found to be Mn3O4. Thus, the system became Mn3O4 clusters embedded in Ge1-yOy. The as-grown sample showed positive linear Hall effect and negligible negative magnetoresistance (MR), which trend remained for the sample annealed up to 550 °C. Interestingly, for the samples annealed at above 650 °C, we observed the anomalous Hall effect around 45 K and the giant positive MR, which are respectively 59.2% and 78.5% at 7 kOe annealed at 650 °C and 700 °C.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

Science.gov (United States)

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Optical trapping with Bessel beams generated from semiconductor lasers

International Nuclear Information System (INIS)

Sokolovskii, G S; Dudelev, V V; Losev, S N; Soboleva, K K; Deryagin, A G; Kuchinskii, V I; Sibbett, W; Rafailov, E U

2014-01-01

In this paper, we study generation of Bessel beams from semiconductor lasers with high beam propagation parameter M 2 and their utilization for optical trapping and manipulation of microscopic particles including living cells. The demonstrated optical tweezing with diodegenerated Bessel beams paves the way to replace their vibronic-generated counterparts for a range of applications towards novel lab-on-a-chip configurations

Highly stable and imperceptible electronics utilizing photoactivated heterogeneous sol-gel metal-oxide dielectrics and semiconductors.

Science.gov (United States)

Jo, Jeong-Wan; Kim, Jaekyun; Kim, Kyung-Tae; Kang, Jin-Gu; Kim, Myung-Gil; Kim, Kwang-Ho; Ko, Hyungduk; Kim, Jiwan; Kim, Yong-Hoon; Park, Sung Kyu

2015-02-18

Incorporation of Zr into an AlOx matrix generates an intrinsically activated ZAO surface enabling the formation of a stable semiconducting IGZO film and good interfacial properties. Photochemically annealed metal-oxide devices and circuits with the optimized sol-gel ZAO dielectric and IGZO semiconductor layers demonstrate the high performance and electrically/mechanically stable operation of flexible electronics fabricated via a low-temperature solution process. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Superconducting detectors for semiconductor quantum photonics

International Nuclear Information System (INIS)

Reithmaier, Guenther M.

2015-01-01

In this thesis we present the first successful on-chip detection of quantum light, thereby demonstrating the monolithic integration of superconducting single photon detectors with individually addressable semiconductor quantum dots in a prototypical quantum photonic circuit. Therefore, we optimized both the deposition of high quality superconducting NbN thin films on GaAs substrates and the fabrication of superconducting detectors and successfully integrated these novel devices with GaAs/AlGaAs ridge waveguides loaded with self-assembled InGaAs quantum dots.

Nanoscale Metal Oxide Semiconductors for Gas Sensing

Science.gov (United States)

Hunter, Gary W.; Evans, Laura; Xu, Jennifer C.; VanderWal, Randy L.; Berger, Gordon M.; Kulis, Michael J.

2011-01-01

A report describes the fabrication and testing of nanoscale metal oxide semiconductors (MOSs) for gas and chemical sensing. This document examines the relationship between processing approaches and resulting sensor behavior. This is a core question related to a range of applications of nanotechnology and a number of different synthesis methods are discussed: thermal evaporation- condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed, providing a processing overview to developers of nanotechnology- based systems. The results of a significant amount of testing and comparison are also described. A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. The TECsynthesized single-crystal nanowires offer uniform crystal surfaces, resistance to sintering, and their synthesis may be done apart from the substrate. The TECproduced nanowire response is very low, even at the operating temperature of 200 C. In contrast, the electrospun polycrystalline nanofiber response is high, suggesting that junction potentials are superior to a continuous surface depletion layer as a transduction mechanism for chemisorption. Using a catalyst deposited upon the surface in the form of nanoparticles yields dramatic gains in sensitivity for both nanostructured, one-dimensional forms. For the nanowire materials, the response magnitude and response rate uniformly increase with increasing operating temperature. Such changes are interpreted in terms of accelerated surface diffusional processes, yielding greater access to chemisorbed oxygen species and faster dissociative chemisorption, respectively. Regardless of operating temperature, sensitivity of the nanofibers is a factor of 10 to 100 greater than that of nanowires with the same catalyst for the same test condition. In summary, nanostructure appears critical to governing the reactivity, as measured by electrical

Electrical memory features of ferromagnetic CoFeAlSi nano-particles embedded in metal-oxide-semiconductor matrix

International Nuclear Information System (INIS)

Lee, Ja Bin; Kim, Ki Woong; Lee, Jun Seok; An, Gwang Guk; Hong, Jin Pyo

2011-01-01

Half-metallic Heusler material Co 2 FeAl 0.5 Si 0.5 (CFAS) nano-particles (NPs) embedded in metal-oxide-semiconductor (MOS) structures with thin HfO 2 tunneling and MgO control oxides were investigated. The CFAS NPs were prepared by rapid thermal annealing. The formation of well-controlled CFAS NPs on thin HfO 2 tunneling oxide was confirmed by atomic force microscopy (AFM). Memory characteristics of CFAS NPs in MOS devices exhibited a large memory window of 4.65 V, as well as good retention and endurance times of 10 5 cycles and 10 9 s, respectively, demonstrating the potential of CFAS NPs as promising candidates for use in charge storage.

Towards a Chemiresistive Sensor-Integrated Electronic Nose: A Review

Directory of Open Access Journals (Sweden)

Kea-Tiong Tang

2013-10-01

Full Text Available Electronic noses have potential applications in daily life, but are restricted by their bulky size and high price. This review focuses on the use of chemiresistive gas sensors, metal-oxide semiconductor gas sensors and conductive polymer gas sensors in an electronic nose for system integration to reduce size and cost. The review covers the system design considerations and the complementary metal-oxide-semiconductor integrated technology for a chemiresistive gas sensor electronic nose, including the integrated sensor array, its readout interface, and pattern recognition hardware. In addition, the state-of-the-art technology integrated in the electronic nose is also presented, such as the sensing front-end chip, electronic nose signal processing chip, and the electronic nose system-on-chip.

75 FR 24742 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Science.gov (United States)

2010-05-05

... Semiconductor, Xiqing Integrated Semiconductor, Manufacturing Site, No. 15 Xinghua Road, Xiqing Economic... Malaysia Sdn. Bhd., NO. 2 Jalan SS 8/2, Free Industrial Zone, Sungai Way, 47300 Petaling Jaya, Selengor, Malaysia. Freescale Semiconductor Pte. Ltd., 7 Changi South Street 2, 03-00, Singapore 486415. Freescale...

Stannic Oxide-Titanium Dioxide Coupled Semiconductor Photocatalyst Loaded with Polyaniline for Enhanced Photocatalytic Oxidation of 1-Octene

Directory of Open Access Journals (Sweden)

Hadi Nur

2007-01-01

Full Text Available Stannic oxide-titanium dioxide (SnO2–TiO2 coupled semiconductor photocatalyst loaded with polyaniline (PANI, a conducting polymer, possesses a high photocatalytic activity in oxidation of 1-octene to 1,2-epoxyoctane with aqueous hydrogen peroxide. The photocatalyst was prepared by impregnation of SnO2 and followed by attachment of PANI onto a TiO2 powder to give sample PANI-SnO2–TiO2. The electrical conductivity of the system becomes high in the presence of PANI. Enhanced photocatalytic activity was observed in the case of PANI-SnO2–TiO2 compared to PANI-TiO2, SnO2–TiO2, and TiO2. A higher photocatalytic activity in the oxidation of 1-octene on PANI-SnO2–TiO2 than SnO2–TiO2, PANI-TiO2, and TiO2 can be considered as an evidence of enhanced charge separation of PANI-SnO2–TiO2 photocatalyst as confirmed by photoluminescence spectroscopy. It suggests that photoinjected electrons are tunneled from TiO2 to SnO2 and then to PANI in order to allow wider separation of excited carriers.

Cancer and reproductive risks in the semiconductor industry.

Science.gov (United States)

LaDou, Joseph; Bailar, John C

2007-01-01

Although many reproductive toxicants and carcinogens are used in the manufacture of semiconductor chips, and worrisome findings have been reported, no broad epidemiologic study has been conducted to define possible risks in a comprehensive way. With few exceptions, the American semiconductor industry has not supported access for independent studies. Older technologies are exported to newly industrialized countries as newer technologies are installed in Japan, the United States, and Europe. Thus there is particular concern about the many workers, mostly in countries that are still industrializing, who have jobs that use chemicals, technologies, and equipment that are no longer in use in developed countries. Since most countries lack cancer registries and have inadequate reproductive and cancer reporting mechanisms, industry efforts to control exposures to carcinogens are of particular importance. Government agencies, the courts, industry, publishers, and academia, on occasion, collude to ignore or to downplay the importance of occupational diseases. Examples of how this happens in the semiconductor industry are presented.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.; Rojas, Jhonathan Prieto; Young, Chadwin D.; Bersuker, Gennadi; Hussain, Muhammad Mustafa

2015-01-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard

Ceramic thermal wind sensor based on advanced direct chip attaching package

International Nuclear Information System (INIS)

Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

2014-01-01

An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

Semiconductor Ion Implanters

International Nuclear Information System (INIS)

MacKinnon, Barry A.; Ruffell, John P.

2011-01-01

In 1953 the Raytheon CK722 transistor was priced at $7.60. Based upon this, an Intel Xeon Quad Core processor containing 820,000,000 transistors should list at $6.2 billion! Particle accelerator technology plays an important part in the remarkable story of why that Intel product can be purchased today for a few hundred dollars. Most people of the mid twentieth century would be astonished at the ubiquity of semiconductors in the products we now buy and use every day. Though relatively expensive in the nineteen fifties they now exist in a wide range of items from high-end multicore microprocessors like the Intel product to disposable items containing 'only' hundreds or thousands like RFID chips and talking greeting cards. This historical development has been fueled by continuous advancement of the several individual technologies involved in the production of semiconductor devices including Ion Implantation and the charged particle beamlines at the heart of implant machines. In the course of its 40 year development, the worldwide implanter industry has reached annual sales levels around $2B, installed thousands of dedicated machines and directly employs thousands of workers. It represents in all these measures, as much and possibly more than any other industrial application of particle accelerator technology. This presentation discusses the history of implanter development. It touches on some of the people involved and on some of the developmental changes and challenges imposed as the requirements of the semiconductor industry evolved.

Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors

International Nuclear Information System (INIS)

Appenzeller, J.; Martel, R.; Solomon, P.; Chan, K.; Avouris, Ph.; Knoch, J.; Benedict, J.; Tanner, M.; Thomas, S.; Wang, K. L.

2000-01-01

We present a scheme for the fabrication of ultrashort channel length metal-oxide-semiconductor field-effect transistors (MOSFETs) involving nanolithography and molecular-beam epitaxy. The active channel is undoped and is defined by a combination of nanometer-scale patterning and anisotropic etching of an n ++ layer grown on a silicon on insulator wafer. The method is self-limiting and can produce MOSFET devices with channel lengths of less than 10 nm. Measurements on the first batch of n-MOSFET devices fabricated with this approach show very good output characteristics and good control of short-channel effects. (c) 2000 American Institute of Physics

Long-term research in Japan: amorphous metals, metal oxide varistors, high-power semiconductors and superconducting generators

Energy Technology Data Exchange (ETDEWEB)

Hane, G.J.; Yorozu, M.; Sogabe, T.; Suzuki, S.

1985-04-01

The review revealed that significant activity is under way in the research of amorphous metals, but that little fundamental work is being pursued on metal oxide varistors and high-power semiconductors. Also, the investigation of long-term research program plans for superconducting generators reveals that activity is at a low level, pending the recommendations of a study currently being conducted through Japan's Central Electric Power Council.

Thin film complementary metal oxide semiconductor (CMOS) device using a single-step deposition of the channel layer

KAUST Repository

Nayak, Pradipta K.

2014-04-14

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n-and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications.

Controlling the interface charge density in GaN-based metal-oxide-semiconductor heterostructures by plasma oxidation of metal layers

International Nuclear Information System (INIS)

Hahn, Herwig; Kalisch, Holger; Vescan, Andrei; Pécz, Béla; Kovács, András; Heuken, Michael

2015-01-01

In recent years, investigating and engineering the oxide-semiconductor interface in GaN-based devices has come into focus. This has been driven by a large effort to increase the gate robustness and to obtain enhancement mode transistors. Since it has been shown that deep interface states act as fixed interface charge in the typical transistor operating regime, it appears desirable to intentionally incorporate negative interface charge, and thus, to allow for a positive shift in threshold voltage of transistors to realise enhancement mode behaviour. A rather new approach to obtain such negative charge is the plasma-oxidation of thin metal layers. In this study, we present transmission electron microscopy and energy dispersive X-ray spectroscopy analysis as well as electrical data for Al-, Ti-, and Zr-based thin oxide films on a GaN-based heterostructure. It is shown that the plasma-oxidised layers have a polycrystalline morphology. An interfacial amorphous oxide layer is only detectable in the case of Zr. In addition, all films exhibit net negative charge with varying densities. The Zr layer is providing a negative interface charge density of more than 1 × 10 13  cm –2 allowing to considerably shift the threshold voltage to more positive values

Blasting detonators incorporating semiconductor bridge technology

Energy Technology Data Exchange (ETDEWEB)

Bickes, R.W. Jr.

1994-05-01

The enormity of the coal mine and extraction industries in Russia and the obvious need in both Russia and the US for cost savings and enhanced safety in those industries suggests that joint studies and research would be of mutual benefit. The author suggests that mine sites and well platforms in Russia offer an excellent opportunity for the testing of Sandia`s precise time-delay semiconductor bridge detonators, with the potential for commercialization of the detonators for Russian and other world markets by both US and Russian companies. Sandia`s semiconductor bridge is generating interest among the blasting, mining and perforation industries. The semiconductor bridge is approximately 100 microns long, 380 microns wide and 2 microns thick. The input energy required for semiconductor bridge ignition is one-tenth the energy required for conventional bridgewire devices. Because semiconductor bridge processing is compatible with other microcircuit processing, timing and logic circuits can be incorporated onto the chip with the bridge. These circuits can provide for the precise timing demanded for cast effecting blasting. Indeed tests by Martin Marietta and computer studies by Sandia have shown that such precise timing provides for more uniform rock fragmentation, less fly rock, reduce4d ground shock, fewer ground contaminants and less dust. Cost studies have revealed that the use of precisely timed semiconductor bridges can provide a savings of $200,000 per site per year. In addition to Russia`s vast mineral resources, the Russian Mining Institute outside Moscow has had significant programs in rock fragmentation for many years. He anticipated that collaborative studies by the Institute and Sandia`s modellers would be a valuable resource for field studies.

Iron oxide-mediated semiconductor photocatalysis vs. heterogeneous photo-Fenton treatment of viruses in wastewater. Impact of the oxide particle size.

Science.gov (United States)

Giannakis, Stefanos; Liu, Siting; Carratalà, Anna; Rtimi, Sami; Talebi Amiri, Masoud; Bensimon, Michaël; Pulgarin, César

2017-10-05

The photo-Fenton process is recognized as a promising technique towards microorganism disinfection in wastewater, but its efficiency is hampered at near-neutral pH operating values. In this work, we overcome these obstacles by using the heterogeneous photo-Fenton process as the default disinfecting technique, targeting MS2 coliphage in wastewater. The use of low concentrations of iron oxides in wastewater without H 2 O 2 (wüstite, maghemite, magnetite) has demonstrated limited semiconductor-mediated MS2 inactivation. Changing the operational pH and the size of the oxide particles indicated that the isoelectric point of the iron oxides and the active surface area are crucial in the success of the process, and the possible underlying mechanisms are investigated. Furthermore, the addition of low amounts of Fe-oxides (1mgL -1 ) and H 2 O 2 in the system (1, 5 and 10mgL -1 ) greatly enhanced the inactivation process, leading to heterogeneous photo-Fenton processes on the surface of the magnetically separable oxides used. Additionally, photo-dissolution of iron in the bulk, lead to homogeneous photo-Fenton, further aided by the complexation by the dissolved organic matter in the solution. Finally, we assess the impact of the presence of the bacterial host and the difference caused by the different iron sources (salts, oxides) and the Fe-oxide size (normal, nano-sized). Copyright © 2017 Elsevier B.V. All rights reserved.

Sensor development at the semiconductor laboratory of the Max-Planck-Society

Science.gov (United States)

Bähr, A.; Lechner, P.; Ninkovic, J.

2017-12-01

For more than twenty years the semiconductor laboratory of the Max-Planck Society (MPG-HLL) is developing high-performing, specialised, scientific silicon sensors including the integration of amplifying electronics on the sensor chip. This paper summarises the actual status of these devices like pnCCDs and DePFET Active Pixel Sensors and their applications.

High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

Science.gov (United States)

Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

2015-08-12

Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

Chip cleaning and regeneration for electrochemical sensor arrays

Energy Technology Data Exchange (ETDEWEB)

Bhalla, Vijayender [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Carrara, Sandro, E-mail: sandro.carrara@epfl.c [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Stagni, Claudio [Department DEIS, University of Bologna, viale Risorgimento 2, 40136 Bologna (Italy); Samori, Bruno [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy)

2010-04-02

Sensing systems based on electrochemical detection have generated great interest because electronic readout may replace conventional optical readout in microarray. Moreover, they offer the possibility to avoid labelling for target molecules. A typical electrochemical array consists of many sensing sites. An ideal micro-fabricated sensor-chip should have the same measured values for all the equivalent sensing sites (or spots). To achieve high reliability in electrochemical measurements, high quality in functionalization of the electrodes surface is essential. Molecular probes are often immobilized by using alkanethiols onto gold electrodes. Applying effective cleaning methods on the chip is a fundamental requirement for the formation of densely-packed and stable self-assembly monolayers. However, the available well-known techniques for chip cleaning may not be so reliable. Furthermore, it could be necessary to recycle the chip for reuse. Also in this case, an effective recycling technique is required to re-obtain well cleaned sensing surfaces on the chip. This paper presents experimental results on the efficacy and efficiency of the available techniques for initial cleaning and further recycling of micro-fabricated chips. Piranha, plasma, reductive and oxidative cleaning methods were applied and the obtained results were critically compared. Some interesting results were attained by using commonly considered cleaning methodologies. This study outlines oxidative electrochemical cleaning and recycling as the more efficient cleaning procedure for electrochemical based sensor arrays.

Semiconductors for plasmonics and metamaterials

DEFF Research Database (Denmark)

Naik, G.V.; Boltasseva, Alexandra

2010-01-01

Plasmonics has conventionally been in the realm of metal-optics. However, conventional metals as plasmonic elements in the near-infrared (NIR) and visible spectral ranges suffer from problems such as large losses and incompatibility with semiconductor technology. Replacing metals with semiconduct......Plasmonics has conventionally been in the realm of metal-optics. However, conventional metals as plasmonic elements in the near-infrared (NIR) and visible spectral ranges suffer from problems such as large losses and incompatibility with semiconductor technology. Replacing metals...... with semiconductors can alleviate these problems if only semiconductors could exhibit negative real permittivity. Aluminum doped zinc oxide (AZO) is a low loss semiconductor that can show negative real permittivity in the NIR. A comparative assessment of AZO-based plasmonic devices such as superlens and hyperlens...... with their metal-based counterparts shows that AZO-based devices significantly outperform at a wavelength of 1.55 µm. This provides a strong stimulus in turning to semiconductor plasmonics at the telecommunication wavelengths. (© 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)....

Empirical study of the metal-nitride-oxide-semiconductor device characteristics deduced from a microscopic model of memory traps

International Nuclear Information System (INIS)

Ngai, K.L.; Hsia, Y.

1982-01-01

A graded-nitride gate dielectric metal-nitride-oxide-semiconductor (MNOS) memory transistor exhibiting superior device characteristics is presented and analyzed based on a qualitative microscopic model of the memory traps. The model is further reviewed to interpret some generic properties of the MNOS memory transistors including memory window, erase-write speed, and the retention-endurance characteristic features

Electronics Industry Study Report: Semiconductors and Defense Electronics

Science.gov (United States)

2003-01-01

Access Memory (DRAM) chips and microprocessors. Samsung , Micron, Hynix, and Infineon control almost three-fourths of the DRAM market,8 while Intel alone...Country 2001 Sales ($B) 2002 Sales ($B) % Change % 2002 Mkt 1 1 Intel U.S. 23.7 24.0 1% 16.9% 2 3 Samsung Semiconductor S. Korea 6.3...located in four major regions: the United States, Europe, Japan, and the Asia-Pacific region (includes South Korea, China, Singapore, Malaysia , Taiwan

Structure and method for controlling band offset and alignment at a crystalline oxide-on-semiconductor interface

Science.gov (United States)

McKee, Rodney A.; Walker, Frederick J.

2003-11-25

A crystalline oxide-on-semiconductor structure and a process for constructing the structure involves a substrate of silicon, germanium or a silicon-germanium alloy and an epitaxial thin film overlying the surface of the substrate wherein the thin film consists of a first epitaxial stratum of single atomic plane layers of an alkaline earth oxide designated generally as (AO).sub.n and a second stratum of single unit cell layers of an oxide material designated as (A'BO.sub.3).sub.m so that the multilayer film arranged upon the substrate surface is designated (AO).sub.n (A'BO.sub.3).sub.m wherein n is an integer repeat of single atomic plane layers of the alkaline earth oxide AO and m is an integer repeat of single unit cell layers of the A'BO.sub.3 oxide material. Within the multilayer film, the values of n and m have been selected to provide the structure with a desired electrical structure at the substrate/thin film interface that can be optimized to control band offset and alignment.

Plasma-assisted atomic layer deposition of TiN/Al2O3 stacks for metal-oxide-semiconductor capacitor applications

NARCIS (Netherlands)

Hoogeland, D.; Jinesh, K.B.; Roozeboom, F.; Besling, W.F.A.; Sanden, van de M.C.M.; Kessels, W.M.M.

2009-01-01

By employing plasma-assisted atomic layer deposition, thin films of Al2O3 and TiN are subsequently deposited in a single reactor at a single substrate temperature with the objective of fabricating high-quality TiN/Al2O3 / p-Si metal-oxide-semiconductor capacitors. Transmission electron microscopy

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

Energy Technology Data Exchange (ETDEWEB)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun; Sonde, Sushant; Banerjee, Sanjay K. [Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, 10100 Burnet Road, Austin, Texas 78758 (United States); Kwon, Hyuk-Min [SK Hynix, Icheon, 2091, Gyeongchung-daero, Bubal-eub, Icheon-si, Gyeonggi-do 136-1 (Korea, Republic of); Orzali, Tommaso; Kim, Tae-Woo, E-mail: twkim78@gmail.com [SEMATECH Inc., 257 Fuller Rd #2200, Albany, New York 12203 (United States); Kim, Dae-Hyun [Kyungpook National University, 80, Daehak-ro, Buk-gu, Daegu 702-701 (Korea, Republic of)

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}), which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.

Integration of Solar Cells on Top of CMOS Chips Part I: a-Si Solar Cells

NARCIS (Netherlands)

Lu, J.; Kovalgin, Alexeij Y.; van der Werf, Karine H.M.; Schropp, Ruud E.I.; Schmitz, Jurriaan

2011-01-01

We present the monolithic integration of deepsubmicrometer complementary metal–oxide–semiconductor (CMOS) microchips with a-Si:H solar cells. Solar cells are manufactured directly on the CMOS chips. The microchips maintain comparable electronic performance, and the solar cells show efficiency values

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors

Directory of Open Access Journals (Sweden)

Jiangwei Liu

2018-06-01

Full Text Available Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond for metal-oxide-semiconductor (MOS capacitors and MOS field-effect transistors (MOSFETs is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD and sputtering deposition (SD techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2, ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD-TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H-diamond and SD-HfO2/ALD-HfO2/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H-diamond, SD-HfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

Science.gov (United States)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

Science.gov (United States)

Abe, Y.; Umeda, T.; Okamoto, M.; Kosugi, R.; Harada, S.; Haruyama, M.; Kada, W.; Hanaizumi, O.; Onoda, S.; Ohshima, T.

2018-01-01

We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

NARCIS (Netherlands)

Goel, Sandeep Kumar

2005-01-01

Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be

Miniature semiconductor detectors for in vivo dosimetry

International Nuclear Information System (INIS)

Rosenfeld, A. B.; Cutajar, D.; Lerch, M. L. F.; Takacs, G.; Cornelius, I. M.; Yudelev, M.; Zaider, M.

2006-01-01

Silicon mini-semiconductor detectors are found in wide applications for in vivo personal dosimetry and dosimetry and Micro-dosimetry of different radiation oncology modalities. These applications are based on integral and spectroscopy modes of metal oxide semiconductor field effect transistor and silicon p-n junction detectors. The advantages and limitations of each are discussed. (authors)

The role of metallic impurities in oxide semiconductors: first-principles calculations and PAC experiments

Energy Technology Data Exchange (ETDEWEB)

Errico, L.A.; Fabricius, G.; Renteria, M. [Departamento de Fisica, Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC 67, 1900 La Plata (Argentina)

2004-08-01

We report an ab-initio comparative study of the electric-field-gradient tensor (EFG) and structural relaxations introduced by acceptor (Cd) and donor (Ta) impurities when they replace cations in a series of binary oxides: TiO{sub 2}, SnO{sub 2}, and In{sub 2}O{sub 3}. Calculations were performed with the Full-Potential Linearized-Augmented Plane Waves method that allows us to treat the electronic structure and the atomic relaxations in a fully self-consistent way. We considered different charge states for each impurity and studied the dependence on these charge states of the electronic properties and the structural relaxations. Our results are compared with available data coming from PAC experiments and previous calculations, allowing us to obtain a new insight on the role that metal impurities play in oxide semiconductors. It is clear from our results that simple models can not describe the measured EFGs at impurities in oxides even approximately. (copyright 2004 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

The origin of magnetism in anatase Co-doped TiO2 magnetic semiconductors

NARCIS (Netherlands)

Lee, Y.J.

2010-01-01

Dilute magnetic semiconductors (DMS) can be tailored by doping a small amount of elements containing a magnetic moment into host semiconductors, which leads to a new class of semiconductors with the functionality of tunable magnetic properties. Recently, oxide semiconductors have attained interests

Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

Directory of Open Access Journals (Sweden)

Cheng-Yang Liu

2009-12-01

Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

Energy Technology Data Exchange (ETDEWEB)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori; Saito, Toshiki; Shibata, Masanobu; Matsumura, Daisuke; Kudo, Takuya; Hiraiwa, Atsushi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kawarada, Hiroshi [Graduate School of Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo 169-8555 (Japan); Kagami Memorial Laboratory for Materials Science and Technology, Waseda University, 2-8-26 Nishiwaseda, Shinjuku, Tokyo 169-0051 (Japan)

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulation by the gate and pinch off.

Mega-pixel PQR laser chips for interconnect, display ITS, and biocell-tweezers OEIC

Science.gov (United States)

Kwon, O'Dae; Yoon, J. H.; Kim, D. K.; Kim, Y. C.; Lee, S. E.; Kim, S. S.

2008-02-01

We describe a photonic quantum ring (PQR) laser device of three dimensional toroidal whispering gallery cavity. We have succeeded in fabricating the first genuine mega-pixel laser chips via regular semiconductor technology. This has been realized since the present injection laser emitting surface-normal dominant 3D whispering gallery modes (WGMs) can be operated CW with extremely low operating currents (μA-nA per pixel), together with the lasing temperature stabilities well above 140 deg C with minimal redshifts, which solves the well-known integration problems facing the conventional VCSEL. Such properties unusual for quantum well lasers become usual because the active region, involving vertically confining DBR structure in addition to the 2D concave WGM geometry, induces a 'photonic quantum ring (PQR)-like' carrier distribution through a photonic quantum corral effect. A few applications of such mega-pixel PQR chips are explained as follows: (A) Next-generation 3D semiconductor technologies demand a strategy on the inter-chip and intra-chip optical interconnect schemes with a key to the high-density emitter array. (B) Due to mounting traffic problems and fatalities ITS technology today is looking for a revolutionary change in the technology. We will thus outline how 'SLEEP-ITS' can emerge with the PQR's position-sensing capability. (C) We describe a recent PQR 'hole' laser of convex WGM: Mega-pixel PQR 'hole' laser chips are even easier to fabricate than PQR 'mesa' lasers. Genuine Laguerre-Gaussian (LG) beam patterns of PQR holes are very promising for biocell manipulations like sorting mouse myeloid leukemia (M1s) cells. (D) Energy saving and 3D speckle-free POR laser can outdo LEDs in view of red GaAs and blue GaN devices fabricated recently.

Microfluidic photoinduced chemical oxidation for Ru(bpy)33+ chemiluminescence - A comprehensive experimental comparison with on-chip direct chemical oxidation.

Science.gov (United States)

Kadavilpparampu, Afsal Mohammed; Al Lawati, Haider A J; Suliman, Fakhr Eldin O

2017-08-05

For the first time, the analytical figures of merit in detection capabilities of the very less explored photoinduced chemical oxidation method for Ru(bpy) 3 2+ CL has been investigated in detail using 32 structurally different analytes. It was carried out on-chip using peroxydisulphate and visible light and compared with well-known direct chemical oxidation approaches using Ce(IV). The analytes belong to various chemical classes such as tertiary amine, secondary amine, sulphonamide, betalactam, thiol and benzothiadiazine. Influence of detection environment on CL emission with respect to method of oxidation was evaluated by changing the buffers and pH. The photoinduced chemical oxidation exhibited more universal nature for Ru(bpy) 3 2+ CL in detection towards selected analytes. No additional enhancers, reagents, or modification in instrumental configuration were required. Wide detectability and enhanced emission has been observed for analytes from all the chemical classes when photoinduced chemical oxidation was employed. Some of these analytes are reported for the first time under photoinduced chemical oxidation like compounds from sulphonamide, betalactam, thiol and benzothiadiazine class. On the other hand, many of the selected analytes including tertiary and secondary amines such as cetirizine, azithromycin fexofenadine and proline did not produced any analytically useful CL signal (S/N=3 or above for 1μgmL -1 analyte) under chemical oxidation. The most fascinating observations was in the detection limits; for example ofloxacin was 15 times more intense with a detection limit of 5.81×10 -10 M compared to most lowest ever reported 6×10 -9 M. Earlier, penicillamine was detected at 0.1μgmL -1 after derivatization using photoinduced chemical oxidation, but in this study, we improved it to 5.82ngmL -1 without any prior derivatization. The detection limits of many other analytes were also found to be improved by several orders of magnitude under photoinduced

Microfluidic photoinduced chemical oxidation for Ru(bpy)33 + chemiluminescence - A comprehensive experimental comparison with on-chip direct chemical oxidation

Science.gov (United States)

Kadavilpparampu, Afsal Mohammed; Al Lawati, Haider A. J.; Suliman, Fakhr Eldin O.

2017-08-01

For the first time, the analytical figures of merit in detection capabilities of the very less explored photoinduced chemical oxidation method for Ru(bpy)32 + CL has been investigated in detail using 32 structurally different analytes. It was carried out on-chip using peroxydisulphate and visible light and compared with well-known direct chemical oxidation approaches using Ce(IV). The analytes belong to various chemical classes such as tertiary amine, secondary amine, sulphonamide, betalactam, thiol and benzothiadiazine. Influence of detection environment on CL emission with respect to method of oxidation was evaluated by changing the buffers and pH. The photoinduced chemical oxidation exhibited more universal nature for Ru(bpy)32 + CL in detection towards selected analytes. No additional enhancers, reagents, or modification in instrumental configuration were required. Wide detectability and enhanced emission has been observed for analytes from all the chemical classes when photoinduced chemical oxidation was employed. Some of these analytes are reported for the first time under photoinduced chemical oxidation like compounds from sulphonamide, betalactam, thiol and benzothiadiazine class. On the other hand, many of the selected analytes including tertiary and secondary amines such as cetirizine, azithromycin fexofenadine and proline did not produced any analytically useful CL signal (S/N = 3 or above for 1 μgmL- 1 analyte) under chemical oxidation. The most fascinating observations was in the detection limits; for example ofloxacin was 15 times more intense with a detection limit of 5.81 × 10- 10 M compared to most lowest ever reported 6 × 10- 9 M. Earlier, penicillamine was detected at 0.1 μg mL- 1 after derivatization using photoinduced chemical oxidation, but in this study, we improved it to 5.82 ng mL- 1 without any prior derivatization. The detection limits of many other analytes were also found to be improved by several orders of magnitude under

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

Science.gov (United States)

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

3D stacked chips from emerging processes to heterogeneous systems

CERN Document Server

Fettweis, Gerhard

2016-01-01

This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

Memory characteristics of Au nanocrystals embedded in metal-oxide-semiconductor structure by using atomic-layer-deposited Al2O3 as control oxide

International Nuclear Information System (INIS)

Wang, C.-C.; Chiou, Y.-K.; Chang, C.-H.; Tseng, J.-Y.; Wu, L.-J.; Chen, C.-Y.; Wu, T.-B.

2007-01-01

The nonvolatile memory characteristics of metal-oxide-semiconductor (MOS) structures containing Au nanocrystals in the Al 2 O 3 /SiO 2 matrix were studied. In this work, we have demonstrated that the use of Al 2 O 3 as control oxide prepared by atomic-layer-deposition enhances the erase speed of the MOS capacitors. A giant capacitance-voltage hysteresis loop and a very short erase time which is lower than 1 ms can be obtained. Compared with the conventional floating-gate electrically erasable programmable read-only memories, the erase speed was promoted drastically. In addition, very low leakage current and large turn-around voltage resulting from electrons or holes stored in the Au nanocrystals were found in the current-voltage relation of the MOS capacitors

Chip-to-chip SnO2 nanowire network sensors for room temperature H2 detection

Science.gov (United States)

Köck, A.; Brunet, E.; Mutinati, G. C.; Maier, T.; Steinhauer, S.

2012-06-01

The employment of nanowires is a very powerful strategy to improve gas sensor performance. We demonstrate a gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected SnO2 nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device is able to detect a H2 concentration of only 20 ppm in synthetic air with ~ 60% relative humidity at room temperature. At an operating temperature of 300°C a concentration of 50 ppm H2 results in a sensitivity of 5%. At this elevated temperature the sensor shows a linear response in a concentration range between 10 ppm and 100 ppm H2. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.

Semiconductor composition containing iron, dysprosium, and terbium

Science.gov (United States)

Pooser, Raphael C.; Lawrie, Benjamin J.; Baddorf, Arthur P.; Malasi, Abhinav; Taz, Humaira; Farah, Annettee E.; Kalyanaraman, Ramakrishnan; Duscher, Gerd Josef Mansfred; Patel, Maulik K.

2017-09-26

An amorphous semiconductor composition includes 1 to 70 atomic percent iron, 15 to 65 atomic percent dysprosium, 15 to 35 atomic percent terbium, balance X, wherein X is at least one of an oxidizing element and a reducing element. The composition has an essentially amorphous microstructure, an optical transmittance of at least 50% in at least the visible spectrum and semiconductor electrical properties.

Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation

Energy Technology Data Exchange (ETDEWEB)

Chou, Wei-Lung, E-mail: wlchou@sunrise.hk.edu.tw [Department of Safety, Health and Environmental Engineering, Hungkuang University, No. 34, Chung-Chie Road, Sha-Lu, Taichung 433, Taiwan (China); Wang, Chih-Ta [Department of Safety Health and Environmental Engineering, Chung Hwa University of Medical Technology, Tainan Hsien 717, Taiwan (China); Chang, Wen-Chun; Chang, Shih-Yu [Department of Safety, Health and Environmental Engineering, Hungkuang University, No. 34, Chung-Chie Road, Sha-Lu, Taichung 433, Taiwan (China)

2010-08-15

In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L{sup -1}). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K.

Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation

International Nuclear Information System (INIS)

Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

2010-01-01

In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L -1 ). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K.

Adsorption treatment of oxide chemical mechanical polishing wastewater from a semiconductor manufacturing plant by electrocoagulation.

Science.gov (United States)

Chou, Wei-Lung; Wang, Chih-Ta; Chang, Wen-Chun; Chang, Shih-Yu

2010-08-15

In this study, metal hydroxides generated during electrocoagulation (EC) were used to remove the chemical oxygen demand (COD) of oxide chemical mechanical polishing (oxide-CMP) wastewater from a semiconductor manufacturing plant by EC. Adsorption studies were conducted in a batch system for various current densities and temperatures. The COD concentration in the oxide-CMP wastewater was effectively removed and decreased by more than 90%, resulting in a final wastewater COD concentration that was below the Taiwan discharge standard (100 mg L(-1)). Since the processed wastewater quality exceeded the direct discharge standard, the effluent could be considered for reuse. The adsorption kinetic studies showed that the EC process was best described using the pseudo-second-order kinetic model at the various current densities and temperatures. The experimental data were also tested against different adsorption isotherm models to describe the EC process. The Freundlich adsorption isotherm model predictions matched satisfactorily with the experimental observations. Thermodynamic parameters, including the Gibbs free energy, enthalpy, and entropy, indicated that the COD adsorption of oxide-CMP wastewater on metal hydroxides was feasible, spontaneous and endothermic in the temperature range of 288-318 K. Copyright 2010 Elsevier B.V. All rights reserved.

A divalent rare earth oxide semiconductor: Yttrium monoxide

Science.gov (United States)

Kaminaga, Kenichi; Sei, Ryosuke; Hayashi, Kouichi; Happo, Naohisa; Tajiri, Hiroo; Oka, Daichi; Fukumura, Tomoteru; Hasegawa, Tetsuya

Rare earth sesquioxides like Y2O3 are known as widegap insulators with the highly stable closed shell trivalent rare earth ions. On the other hand, rare earth monoxides such as YO have been recognized as gaseous phase, and only EuO and YbO were thermodynamically stable solid-phase rock salt monoxides. In this study, solid-phase rock salt yttrium monoxide, YO, was synthesized in a form of epitaxial thin film by pulsed laser deposition method. YO possesses unusual valence of Y2+ ([Kr] 4d1) . In contrast with Y2O3, YO was narrow gap semiconductor with dark-brown color. The electrical conductivity was tunable from 10-1 to 103 Ω-1 cm-1 by introducing oxygen vacancies as electron donor. Weak antilocalization behavior was observed indicating significant spin-orbit coupling owing to 4 d electron carrier. The absorption spectral shape implies the Mott-Hubbard insulator character of YO. Rare earth monoixdes will be new platform of functional oxides. This work was supported by JST-CREST, the Japan Society for the Promotion of Science (JSPS) with Grant-in-Aid for Scientific Research on Innovative Areas (Nos. 26105002 and 26105006), and Nanotechnology Platform (Project No.12024046) of MEXT, Japan.

Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field-effect transistor (MOSFET) dosemeters: a comparative study

NARCIS (Netherlands)

Koivisto, J.; Schulze, D.; Wolff, J.E.H.; Rottke, D.

2014-01-01

Objectives: The objective of this study was to compare the performance of metal oxide semiconductor field-effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. Methods: Organ and effective

Fabrication of smooth patterned structures of refractory metals, semiconductors, and oxides via template stripping.

Science.gov (United States)

Park, Jong Hyuk; Nagpal, Prashant; McPeak, Kevin M; Lindquist, Nathan C; Oh, Sang-Hyun; Norris, David J

2013-10-09

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics.

High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

Energy Technology Data Exchange (ETDEWEB)

Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

2010-01-01

In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

Plasmonic doped semiconductor nanocrystals: Properties, fabrication, applications and perspectives

Science.gov (United States)

Kriegel, Ilka; Scotognella, Francesco; Manna, Liberato

2017-02-01

Degenerately doped semiconductor nanocrystals (NCs) are of recent interest to the NC community due to their tunable localized surface plasmon resonances (LSPRs) in the near infrared (NIR). The high level of doping in such materials with carrier densities in the range of 1021cm-3 leads to degeneracy of the doping levels and intense plasmonic absorption in the NIR. The lower carrier density in degenerately doped semiconductor NCs compared to noble metals enables LSPR tuning over a wide spectral range, since even a minor change of the carrier density strongly affects the spectral position of the LSPR. Two classes of degenerate semiconductors are most relevant in this respect: impurity doped semiconductors, such as metal oxides, and vacancy doped semiconductors, such as copper chalcogenides. In the latter it is the density of copper vacancies that controls the carrier concentration, while in the former the introduction of impurity atoms adds carriers to the system. LSPR tuning in vacancy doped semiconductor NCs such as copper chalcogenides occurs by chemically controlling the copper vacancy density. This goes in hand with complex structural modifications of the copper chalcogenide crystal lattice. In contrast the LSPR of degenerately doped metal oxide NCs is modified by varying the doping concentration or by the choice of host and dopant atoms, but also through the addition of capacitive charge carriers to the conduction band of the metal oxide upon post-synthetic treatments, such as by electrochemical- or photodoping. The NIR LSPRs and the option of their spectral fine-tuning make accessible important new features, such as the controlled coupling of the LSPR to other physical signatures or the enhancement of optical signals in the NIR, sensing application by LSPR tracking, energy production from the NIR plasmon resonance or bio-medical applications in the biological window. In this review we highlight the recent advances in the synthesis of various different plasmonic

76 FR 14688 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

Science.gov (United States)

2011-03-17

... existence of a domestic industry. The Commission's notice of investigation named several respondents...; Freescale Semiconductor Malaysia Sdn. Bhd. of Malaysia; Freescale Semiconductor Pte. Ltd. of Singapore; Mouser Electronics, Inc. of Mansfield, Texas; and Motorola Inc. of Schaumburg, Illinois. On August 16...

Semiconductor technology program. Progress briefs

Science.gov (United States)

Bullis, W. M.

1980-01-01

Measurement technology for semiconductor materials, process control, and devices is reviewed. Activities include: optical linewidth and thermal resistance measurements; device modeling; dopant density profiles; resonance ionization spectroscopy; and deep level measurements. Standardized oxide charge terminology is also described.

An AES chip with DPA resistance using hardware-based random order execution

International Nuclear Information System (INIS)

Yu Bo; Li Xiangyu; Chen Cong; Sun Yihe; Wu Liji; Zhang Xiangmin

2012-01-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm 2 . A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance. (semiconductor integrated circuits)

Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

International Nuclear Information System (INIS)

Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

2012-01-01

A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

Science.gov (United States)

Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

1992-06-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

International Nuclear Information System (INIS)

Asoka-Kumar, P.; Leung, T.C.; Lynn, K.G.; Nielsen, B.; Forcier, M.P.; Weinberg, Z.A.; Rubloff, G.W.

1992-01-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions

Resistance transition assisted geometry enhanced magnetoresistance in semiconductors

International Nuclear Information System (INIS)

Luo, Zhaochu; Zhang, Xiaozhong

2015-01-01

Magnetoresistance (MR) reported in some non-magnetic semiconductors (particularly silicon) has triggered considerable interest owing to the large magnitude of the effect. Here, we showed that MR in lightly doped n-Si can be significantly enhanced by introducing two diodes and proper design of the carrier path [Wan, Nature 477, 304 (2011)]. We designed a geometrical enhanced magnetoresistance (GEMR) device whose room-temperature MR ratio reaching 30% at 0.065 T and 20 000% at 1.2 T, respectively, approaching the performance of commercial MR devices. The mechanism of this GEMR is: the diodes help to define a high resistive state (HRS) and a low resistive state (LRS) in device by their openness and closeness, respectively. The ratio of apparent resistance between HRS and LRS is determined by geometry of silicon wafer and electrodes. Magnetic field could induce a transition from LRS to HRS by reshaping potential and current distribution among silicon wafer, resulting in a giant enhancement of intrinsic MR. We expect that this GEMR could be also realized in other semiconductors. The combination of high sensitivity to low magnetic fields and large high-field response should make this device concept attractive to the magnetic field sensing industry. Moreover, because this MR device is based on a conventional silicon/semiconductor platform, it should be possible to integrate this MR device with existing silicon/semiconductor devices and so aid the development of silicon/semiconductor-based magnetoelectronics. Also combining MR devices and semiconducting devices in a single Si/semiconductor chip may lead to some novel devices with hybrid function, such as electric-magnetic-photonic properties. Our work demonstrates that the charge property of semiconductor can be used in the magnetic sensing industry, where the spin properties of magnetic materials play a role traditionally

Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

Energy Technology Data Exchange (ETDEWEB)

Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

1997-12-01

Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

Tantalum-based semiconductors for solar water splitting.

Science.gov (United States)

Zhang, Peng; Zhang, Jijie; Gong, Jinlong

2014-07-07

Solar energy utilization is one of the most promising solutions for the energy crises. Among all the possible means to make use of solar energy, solar water splitting is remarkable since it can accomplish the conversion of solar energy into chemical energy. The produced hydrogen is clean and sustainable which could be used in various areas. For the past decades, numerous efforts have been put into this research area with many important achievements. Improving the overall efficiency and stability of semiconductor photocatalysts are the research focuses for the solar water splitting. Tantalum-based semiconductors, including tantalum oxide, tantalate and tantalum (oxy)nitride, are among the most important photocatalysts. Tantalum oxide has the band gap energy that is suitable for the overall solar water splitting. The more negative conduction band minimum of tantalum oxide provides photogenerated electrons with higher potential for the hydrogen generation reaction. Tantalates, with tunable compositions, show high activities owning to their layered perovskite structure. (Oxy)nitrides, especially TaON and Ta3N5, have small band gaps to respond to visible-light, whereas they can still realize overall solar water splitting with the proper positions of conduction band minimum and valence band maximum. This review describes recent progress regarding the improvement of photocatalytic activities of tantalum-based semiconductors. Basic concepts and principles of solar water splitting will be discussed in the introduction section, followed by the three main categories regarding to the different types of tantalum-based semiconductors. In each category, synthetic methodologies, influencing factors on the photocatalytic activities, strategies to enhance the efficiencies of photocatalysts and morphology control of tantalum-based materials will be discussed in detail. Future directions to further explore the research area of tantalum-based semiconductors for solar water splitting

Metal/Semiconductor and Transparent Conductor/Semiconductor Heterojunctions in High Efficient Photoelectric Devices: Progress and Features

Directory of Open Access Journals (Sweden)

M. Melvin David Kumar

2014-01-01

Full Text Available Metal/semiconductor and transparent conductive oxide (TCO/semiconductor heterojunctions have emerged as an effective modality in the fabrication of photoelectric devices. This review is following a recent shift toward the engineering of TCO layers and structured Si substrates, incorporating metal nanoparticles for the development of next-generation photoelectric devices. Beneficial progress which helps to increase the efficiency and reduce the cost, has been sequenced based on efficient technologies involved in making novel substrates, TCO layers, and electrodes. The electrical and optical properties of indium tin oxide (ITO and aluminum doped zinc oxide (AZO thin films can be enhanced by structuring the surface of TCO layers. The TCO layers embedded with Ag nanoparticles are used to enhance the plasmonic light trapping effect in order to increase the energy harvesting nature of photoelectric devices. Si nanopillar structures which are fabricated by photolithography-free technique are used to increase light-active surface region. The importance of the structure and area of front electrodes and the effect of temperature at the junction are the value added discussions in this review.

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

Science.gov (United States)

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

Science.gov (United States)

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation

International Nuclear Information System (INIS)

Tan Zhen; Zhao Lian-Feng; Wang Jing; Xu Jun

2014-01-01

Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with sulfur passivation were investigated and the chemical mechanisms of the sulfur passivation process were carefully studied. It was shown that the sulfur passivation treatment could reduce the interface trap density D it of the HfAlO/GaSb interface by 35% and reduce the equivalent oxide thickness (EOT) from 8 nm to 4 nm. The improved properties are due to the removal of the native oxide layer, as was proven by x-ray photoelectron spectroscopy measurements and high-resolution cross-sectional transmission electron microscopy (HRXTEM) results. It was also found that GaSb-based MOSCAPs with HfAlO gate dielectrics have interfacial properties superior to those using HfO 2 or Al 2 O 3 dielectric layers. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Homostructured ZnO-based metal-oxide-semiconductor field-effect transistors deposited at low temperature by vapor cooling condensation system

Energy Technology Data Exchange (ETDEWEB)

Lin, Tzu-Shun [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Lee, Ching-Ting, E-mail: ctlee@ee.ncku.edu.tw [Institute of Nanotechnology and Microsystems Engineering, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China); Institute of Microelectronics, Department of Electrical Engineering, Advanced Optoelectronic Technology Center, National Cheng Kung University, 701 Tainan, Taiwan, ROC (China)

2015-11-01

Highlights: • The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors. • The resulting homostructured ZnO-based MOSFETs operated at a reverse voltage of −6 V had a very low gate leakage current of 24 nA. • The associated I{sub DSS} and the g{sub m(max)} were 5.64 mA/mm and 1.31 mS/mm, respectively. - Abstract: The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors (MOSFETs) on sapphire substrates. Owing to the high quality of the deposited, various ZnO films and interfaces, the resulting MOSFETs manifested attractive characteristics, such as the low gate leakage current of 24 nA, the low average interface state density of 2.92 × 10{sup 11} cm{sup −2} eV{sup −1}, and the complete pinch-off performance. The saturation drain–source current, the maximum transconductance, and the gate voltage swing of the resulting homostructured ZnO-based MOSFETs were 5.64 mA/mm, 1.31 mS/mm, and 3.2 V, respectively.

A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

International Nuclear Information System (INIS)

Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua

2010-01-01

A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 μm CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 μm 2 . Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

Molecular coatings of nitride semiconductors for optoelectronics, electronics, and solar energy harvesting

KAUST Repository

Ng, Tien Khee; Zhao, Chao; Priante, Davide; Ooi, Boon S.; Hussein, Mohamed Ebaid Abdrabou

2018-01-01

Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and / or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and / or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided. Methods can include cleaning a native surface of a gallium nitride semiconductor to produce a cleaned surface, etching the cleaned surface to remove oxide layers on the surface, and applying single or multiple coatings of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof attached to the surface.

Molecular coatings of nitride semiconductors for optoelectronics, electronics, and solar energy harvesting

KAUST Repository

Ng, Tien Khee

2018-02-01

Gallium nitride based semiconductors are provided having one or more passivated surfaces. The surfaces can have a plurality of thiol compounds attached thereto for enhancement of optoelectronic properties and/or solar water splitting properties. The surfaces can also include wherein the surface has been treated with chemical solution for native oxide removal and / or wherein the surface has attached thereto a plurality of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof to create a treated surface for enhancement of optoelectronic properties and / or solar water splitting properties. Methods of making the gallium nitride based semiconductors are also provided. Methods can include cleaning a native surface of a gallium nitride semiconductor to produce a cleaned surface, etching the cleaned surface to remove oxide layers on the surface, and applying single or multiple coatings of nitrides, oxides, insulating compounds, thiol compounds, or a combination thereof attached to the surface.

Superconductivity in doped semiconductors

Energy Technology Data Exchange (ETDEWEB)

Bustarret, E., E-mail: Etienne.bustarret@neel.cnrs.fr

2015-07-15

A historical survey of the main normal and superconducting state properties of several semiconductors doped into superconductivity is proposed. This class of materials includes selenides, tellurides, oxides and column-IV semiconductors. Most of the experimental data point to a weak coupling pairing mechanism, probably phonon-mediated in the case of diamond, but probably not in the case of strontium titanate, these being the most intensively studied materials over the last decade. Despite promising theoretical predictions based on a conventional mechanism, the occurrence of critical temperatures significantly higher than 10 K has not been yet verified. However, the class provides an enticing playground for testing theories and devices alike.

Transparent p-type SnO nanowires with unprecedented hole mobility among oxide semiconductors

KAUST Repository

Caraveo-Frescas, J. A.

2013-11-25

p-type tin monoxide (SnO) nanowire field-effect transistors with stable enhancement mode behavior and record performance are demonstrated at 160 °C. The nanowire transistors exhibit the highest field-effect hole mobility (10.83 cm2 V−1 s−1) of any p-type oxide semiconductor processed at similar temperature. Compared to thin film transistors, the SnO nanowire transistors exhibit five times higher mobility and one order of magnitude lower subthreshold swing. The SnO nanowire transistors show three times lower threshold voltages (−1 V) than the best reported SnO thin film transistors and fifteen times smaller than p-type Cu 2O nanowire transistors. Gate dielectric and process temperature are critical to achieving such performance.

DNA-decorated carbon-nanotube-based chemical sensors on complementary metal oxide semiconductor circuitry

International Nuclear Information System (INIS)

Chen, Chia-Ling; Yang, Chih-Feng; Dokmeci, Mehmet R; Agarwal, Vinay; Sonkusale, Sameer; Kim, Taehoon; Busnaina, Ahmed; Chen, Michelle

2010-01-01

We present integration of single-stranded DNA (ss-DNA)-decorated single-walled carbon nanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry as nanoscale chemical sensors. SWNTs were assembled onto CMOS circuitry via a low voltage dielectrophoretic (DEP) process. Besides, bare SWNTs are reported to be sensitive to various chemicals, and functionalization of SWNTs with biomolecular complexes further enhances the sensing specificity and sensitivity. After decorating ss-DNA on SWNTs, we have found that the sensing response of the gas sensor was enhanced (up to ∼ 300% and ∼ 250% for methanol vapor and isopropanol alcohol vapor, respectively) compared with bare SWNTs. The SWNTs coupled with ss-DNA and their integration on CMOS circuitry demonstrates a step towards realizing ultra-sensitive electronic nose applications.

Study on VCSEL laser heating chip in nuclear magnetic resonance gyroscope

Science.gov (United States)

Liang, Xiaoyang; Zhou, Binquan; Wu, Wenfeng; Jia, Yuchen; Wang, Jing

2017-10-01

In recent years, atomic gyroscope has become an important direction of inertial navigation. Nuclear magnetic resonance gyroscope has a stronger advantage in the miniaturization of the size. In atomic gyroscope, the lasers are indispensable devices which has an important effect on the improvement of the gyroscope performance. The frequency stability of the VCSEL lasers requires high precision control of temperature. However, the heating current of the laser will definitely bring in the magnetic field, and the sensitive device, alkali vapor cell, is very sensitive to the magnetic field, so that the metal pattern of the heating chip should be designed ingeniously to eliminate the magnetic field introduced by the heating current. In this paper, a heating chip was fabricated by MEMS process, i.e. depositing platinum on semiconductor substrates. Platinum has long been considered as a good resistance material used for measuring temperature The VCSEL laser chip is fixed in the center of the heating chip. The thermometer resistor measures the temperature of the heating chip, which can be considered as the same temperature of the VCSEL laser chip, by turning the temperature signal into voltage signal. The FPGA chip is used as a micro controller, and combined with PID control algorithm constitute a closed loop control circuit. The voltage applied to the heating resistor wire is modified to achieve the temperature control of the VCSEL laser. In this way, the laser frequency can be controlled stably and easily. Ultimately, the temperature stability can be achieved better than 100mK.

Analysis of fluctuations in semiconductor devices

Science.gov (United States)

Andrei, Petru

The random nature of ion implantation and diffusion processes as well as inevitable tolerances in fabrication result in random fluctuations of doping concentrations and oxide thickness in semiconductor devices. These fluctuations are especially pronounced in ultrasmall (nanoscale) semiconductor devices when the spatial scale of doping and oxide thickness variations become comparable with the geometric dimensions of devices. In the dissertation, the effects of these fluctuations on device characteristics are analyzed by using a new technique for the analysis of random doping and oxide thickness induced fluctuations. This technique is universal in nature in the sense that it is applicable to any transport model (drift-diffusion, semiclassical transport, quantum transport etc.) and it can be naturally extended to take into account random fluctuations of the oxide (trapped) charges and channel length. The technique is based on linearization of the transport equations with respect to the fluctuating quantities. It is computationally much (a few orders of magnitude) more efficient than the traditional Monte-Carlo approach and it yields information on the sensitivity of fluctuations of parameters of interest (e.g. threshold voltage, small-signal parameters, cut-off frequencies, etc.) to the locations of doping and oxide thickness fluctuations. For this reason, it can be very instrumental in the design of fluctuation-resistant structures of semiconductor devices. Quantum mechanical effects are taken into account by using the density-gradient model as well as through self-consistent Poisson-Schrodinger computations. Special attention is paid to the presenting of the technique in a form that is suitable for implementation on commercial device simulators. The numerical implementation of the technique is discussed in detail and numerous computational results are presented and compared with those previously published in literature.

Catalyzed reactions at illuminated semiconductor interfaces

International Nuclear Information System (INIS)

Wrighton, M.S.

1984-01-01

Many desirable minority carrier chemical redox processes are too slow to compete with e - -h + recombination at illuminated semiconductor/liquid electrolyte junction interfaces. Reductions of H 2 O to H 2 or CO 2 to compounds having C--H bonds are too slow to compete with e - -h + recombination at illuminated p-type semiconductors, for example. Approaches to improve the rate of the desired processes involving surface modification techniques are described. Photoanodes are plagued by the additional problem of oxidative decomposition under illumination with > or =E/sub g/ illumination. The photo-oxidation of Cl - , Br - , and H 2 O is considered to illustrate the concepts involved. Proof of concept experiments establish that catalysis can be effective in dramatically improving direct solar fuel production; efficiencies of >10% have been demonstrated

Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

Science.gov (United States)

Wysocki, Gerard (Inventor); Tittel, Frank K. (Inventor); Curl, Robert F. (Inventor)

2010-01-01

A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

Dynamic spin polarization by orientation-dependent separation in a ferromagnet-semiconductor hybrid

Science.gov (United States)

Korenev, V. L.; Akimov, I. A.; Zaitsev, S. V.; Sapega, V. F.; Langer, L.; Yakovlev, D. R.; Danilov, Yu. A.; Bayer, M.

2012-07-01

Integration of magnetism into semiconductor electronics would facilitate an all-in-one-chip computer. Ferromagnet/bulk semiconductor hybrids have been, so far, mainly considered as key devices to read out the ferromagnetism by means of spin injection. Here we demonstrate that a Mn-based ferromagnetic layer acts as an orientation-dependent separator for carrier spins confined in a semiconductor quantum well that is set apart from the ferromagnet by a barrier only a few nanometers thick. By this spin-separation effect, a non-equilibrium electron-spin polarization is accumulated in the quantum well due to spin-dependent electron transfer to the ferromagnet. The significant advance of this hybrid design is that the excellent optical properties of the quantum well are maintained. This opens up the possibility of optical readout of the ferromagnet's magnetization and control of the non-equilibrium spin polarization in non-magnetic quantum wells.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

Science.gov (United States)

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

Purcell effect in an organic-inorganic halide perovskite semiconductor microcavity system

International Nuclear Information System (INIS)

Wang, Jun; Wang, Yafeng; Hu, Tao; Wu, Lin; Shen, Xuechu; Chen, Zhanghai; Cao, Runan; Xu, Fei; Da, Peimei; Zheng, Gengfeng; Lu, Jian

2016-01-01

Organic-inorganic halide perovskite semiconductors with the attractive physics properties, including strong photoluminescence (PL), huge oscillator strengths, and low nonradiative recombination losses, are ideal candidates for studying the light-matter interaction in nanostructures. Here, we demonstrate the coupling of the exciton state and the cavity mode in the lead halide perovskite microcavity system at room temperature. The Purcell effect in the coupling system is clearly observed by using angle-resolved photoluminescence spectra. Kinetic analysis based on time-resolved PL reveals that the spontaneous emission rate of the halide perovskite semiconductor is significantly enhanced at resonance of the exciton energy and the cavity mode. Our results provide the way for developing electrically driven organic polariton lasers, optical devices, and on-chip coherent quantum light sources

High-resolution X-ray imaging - a powerful nondestructive technique for applications in semiconductor industry

International Nuclear Information System (INIS)

Zschech, Ehrenfried; Yun, Wenbing; Schneider, Gerd

2008-01-01

The availability of high-brilliance X-ray sources, high-precision X-ray focusing optics and very efficient CCD area detectors has contributed essentially to the development of transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) with sub-50 nm resolution. Particularly, the fabrication of high aspect ratio Fresnel zone plates with zone widths approaching 15 nm has contributed to the enormous improvement in spatial resolution during the previous years. Currently, Fresnel zone plates give the ability to reach spatial resolutions of 15 to 20 nm in the soft and of about 30 to 50 nm in the hard X-ray energy range. X-ray microscopes with rotating anode X-ray sources that can be installed in an analytical lab next to a semiconductor fab have been developed recently. These unique TXM/XCT systems provide an important new capability of nondestructive 3D imaging of internal circuit structures without destructive sample preparation such as cross sectioning. These lab systems can be used for failure localization in micro- and nanoelectronic structures and devices, e.g., to visualize voids and residuals in on-chip metal interconnects without physical modification of the chip. Synchrotron radiation experiments have been used to study new processes and materials that have to be introduced into the semiconductor industry. The potential of TXM using synchrotron radiation in the soft X-ray energy range is shown for the nondestructive in situ imaging of void evolution in embedded on-chip copper interconnect structures during electromigration and for the imaging of different types of insulating thin films between the on-chip interconnects (spectromicroscopy). (orig.)

A full on-chip CMOS low-dropout voltage regulator with VCCS compensation

Energy Technology Data Exchange (ETDEWEB)

Gao Leisheng; Zhou Yumei; Wu Bin; Jiang Jianhua, E-mail: gaoleisheng@ime.ac.c [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

2010-08-15

A full on-chip CMOS low-dropout (LDO) voltage regulator with high PSR is presented. Instead of relying on the zero generated by the load capacitor and its equivalent series resistance, the proposed LDO generates a zero by voltage-controlled current sources for stability. The compensating capacitor for the proposed scheme is only 0.18 pF, which is much smaller than the capacitor of the conventional compensation scheme. The full on-chip LDO was fabricated in commercial 0.35 {mu}m CMOS technology. The active chip area of the LDO (including the bandgap voltage reference) is 400 x 270 {mu}m{sup 2}. Experimental results show that the PSR of the LDO is -58.7 dB at a frequency of 10 Hz and -20 dB at a frequency of 1 MHz. The proposed LDO is capable of sourcing an output current up to 50 mA. (semiconductor integrated circuits)

Atomic Level Cleaning of Poly Methyl Methacrylate Residues from the Graphene Surface Using Radiolized Water at High Temperatures (Postprint)

Science.gov (United States)

2017-09-05

arbitrary substrates like oxides, semiconductors , or even on other 2-D materials in order to make 2-D heterostructures.11–19 Poly-methyl...Following approaches utilized in semiconductor manufacturing, where PMMA is cleaned from the surface of semiconductors after lithographic patterning, wet...of these suggest the presence of significant amount of PMMA residue and inorganic particles made of SiOx and carbon in different places of the chip

Standard-free electron-probe microanalysis of thin films of HTSC-oxide and semiconductors (h<1μm)

International Nuclear Information System (INIS)

Kvardakov, A.M.; Mikhajlova, A.Ya.; San'gin, V.P.; Lazarev, V.B.

1993-01-01

A simplified variant of the standard-free electron-probe microanalysis is elaborated to carry out rapid analysis of chemical composition of >1μm thickness thin films of high-temperature superconductor oxides and semiconductors on alien substrates. The suggested technique has increased the efficiency of search for optimal conditions of preparation YBa 2 Cu 3 O x thin films existing in magnetron and InSb ion-beam techniques of spraying on SrTiO 3 and α-Al 2 O 3 monocrystal base substrates

JPL CMOS Active Pixel Sensor Technology

Science.gov (United States)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

Energy Technology Data Exchange (ETDEWEB)

Kanaki, Toshiki, E-mail: kanaki@cryst.t.u-tokyo.ac.jp; Asahara, Hirokatsu; Ohya, Shinobu, E-mail: ohya@cryst.t.u-tokyo.ac.jp; Tanaka, Masaaki, E-mail: masaaki@ee.t.u-tokyo.ac.jp [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan)

2015-12-14

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I{sub DS} by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I{sub DS} by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

International Nuclear Information System (INIS)

Kanaki, Toshiki; Asahara, Hirokatsu; Ohya, Shinobu; Tanaka, Masaaki

2015-01-01

We fabricate a vertical spin metal-oxide-semiconductor field-effect transistor (spin-MOSFET) structure, which is composed of an epitaxial single-crystal heterostructure with a ferromagnetic-semiconductor GaMnAs source/drain, and investigate its spin-dependent transport properties. We modulate the drain-source current I DS by ∼±0.5% with a gate-source voltage of ±10.8 V and also modulate I DS by up to 60% with changing the magnetization configuration of the GaMnAs source/drain at 3.5 K. The magnetoresistance ratio is more than two orders of magnitude higher than that obtained in the previous studies on spin MOSFETs. Our result shows that a vertical structure is one of the hopeful candidates for spin MOSFET when the device size is reduced to a sub-micron or nanometer scale

In situ ZnO-PVA nanocomposite coated microfluidic chips for biosensing

Science.gov (United States)

Habouti, Salah; Kunstmann-Olsen, Casper; Hoyland, James D.; Rubahn, Horst-Günter; Es-Souni, Mohammed

2014-05-01

Microfluidic chips with integrated fluid and optical connectors have been generated via a simple PDMS master-mould technique. In situ coating using a Zinc oxide polyvinylalcohol based sol-gel method results in ultrathin nanocomposite layers on the fluid channels, which makes them strongly hydrophilic and minimizes auto contamination of the chips by injected fluorescent biomarkers.

Comparative analysis of oxide phase formation and its effects on electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor structures

Energy Technology Data Exchange (ETDEWEB)

Lee, Jaeyel [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Sehun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Kim, Jungsub; Yang, Changjae; Kim, Sujin; Seok, Chulkyun [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Park, Jinsub [Department of Electronic Engineering, Hanyang University, Seoul 133-791 (Korea, Republic of); Yoon, Euijoon, E-mail: eyoon@snu.ac.kr [Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); WCU Hybrid Materials Program, Department of Materials Science and Engineering, Seoul National University, Seoul 151-744 (Korea, Republic of); Department of Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, Suwon 443-270 (Korea, Republic of); Energy Semiconductor Research Center, Advanced Institutes of Convergence Technology, Seoul National University, Suwon 443-270 (Korea, Republic of)

2012-06-01

We report on the changes in the interfacial phases between SiO{sub 2} and InSb caused by various deposition temperatures and heat treatments. X-ray photoelectron spectroscopy (XPS) and Raman spectroscopy were used to evaluate the relative amount of each phase present at the interface. The effect of interfacial phases on the electrical properties of SiO{sub 2}/InSb metal-oxide-semiconductor (MOS) structures was investigated by capacitance-voltage (C-V) measurements. The amount of both In and Sb oxides increased with the deposition temperature. The amount of interfacial In oxide was larger for all samples, regardless of the deposition and annealing temperatures and times. In particular, the annealed samples contained less than half the amount of Sb oxide compared with the as-deposited samples, indicating a strong interfacial reaction between Sb oxide and the InSb substrate during annealing. The interface trap density sharply increased for deposition temperatures above 240 Degree-Sign C. The C-V measurements and Raman spectroscopy indicated that elemental Sb accumulation due to the interfacial reaction of Sb oxide with InSb substrate was responsible for the increased interfacial trap densities in these SiO{sub 2}/InSb MOS structures. - Highlights: Black-Right-Pointing-Pointer We report the quantitative analysis of interfacial oxides at the SiO{sub 2}/InSb interface. Black-Right-Pointing-Pointer Interfacial oxides were measured quantitatively by X-ray Photoelectron Spectroscopy. Black-Right-Pointing-Pointer As-grown and annealed samples showed different compositions of oxide phases. Black-Right-Pointing-Pointer Considerable reduction of antimony oxide phases was observed during annealing. Black-Right-Pointing-Pointer Interface trap densities at the SiO{sub 2}/InSb interface were calculated.

A microprocessor based on a two-dimensional semiconductor

Science.gov (United States)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

On-chip high-voltage generator design design methodology for charge pumps

CERN Document Server

Tanzawa, Toru

2016-01-01

This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

International Nuclear Information System (INIS)

Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

2006-01-01

Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

Additional compound semiconductor nanowires for photonics

Science.gov (United States)

Ishikawa, F.

2016-02-01

GaAs related compound semiconductor heterostructures are one of the most developed materials for photonics. Those have realized various photonic devices with high efficiency, e. g., lasers, electro-optical modulators, and solar cells. To extend the functions of the materials system, diluted nitride and bismide has been paid attention over the past decade. They can largely decrease the band gap of the alloys, providing the greater tunability of band gap and strain status, eventually suppressing the non-radiative Auger recombinations. On the other hand, selective oxidation for AlGaAs is a vital technique for vertical surface emitting lasers. That enables precisely controlled oxides in the system, enabling the optical and electrical confinement, heat transfer, and mechanical robustness. We introduce the above functions into GaAs nanowires. GaAs/GaAsN core-shell nanowires showed clear redshift of the emitting wavelength toward infrared regime. Further, the introduction of N elongated the carrier lifetime at room temperature indicating the passivation of non-radiative surface recombinations. GaAs/GaAsBi nanowire shows the redshift with metamorphic surface morphology. Selective and whole oxidations of GaAs/AlGaAs core-shell nanowires produce semiconductor/oxide composite GaAs/AlGaOx and oxide GaOx/AlGaOx core-shell nanowires, respectively. Possibly sourced from nano-particle species, the oxide shell shows white luminescence. Those property should extend the functions of the nanowires for their application to photonics.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

Science.gov (United States)

Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

2015-07-01

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

Science.gov (United States)

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Effect of Water Vapor and Surface Morphology on the Low Temperature Response of Metal Oxide Semiconductor Gas Sensors

Directory of Open Access Journals (Sweden)

Konrad Maier

2015-09-01

Full Text Available In this work the low temperature response of metal oxide semiconductor gas sensors is analyzed. Important characteristics of this low-temperature response are a pronounced selectivity to acid- and base-forming gases and a large disparity of response and recovery time constants which often leads to an integrator-type of gas response. We show that this kind of sensor performance is related to the trend of semiconductor gas sensors to adsorb water vapor in multi-layer form and that this ability is sensitively influenced by the surface morphology. In particular we show that surface roughness in the nanometer range enhances desorption of water from multi-layer adsorbates, enabling them to respond more swiftly to changes in the ambient humidity. Further experiments reveal that reactive gases, such as NO2 and NH3, which are easily absorbed in the water adsorbate layers, are more easily exchanged across the liquid/air interface when the humidity in the ambient air is high.

Review on the dynamics of semiconductor nanowire lasers

Science.gov (United States)

Röder, Robert; Ronning, Carsten

2018-03-01

Semiconductor optoelectronic devices have contributed tremendously to the technological progress in the past 50-60 years. Today, they also play a key role in nanophotonics stimulated by the inherent limitations of electronic integrated circuits and the growing demand for faster communications on chip. In particular, the field of ‘nanowire photonics’ has emerged including the search for coherent light sources with a nano-scaled footprint. The past decade has been dedicated to find suitable semiconductor nanowire (NW) materials for such nanolasers. Nowadays, such NW lasers consistently work at room temperature covering a huge spectral range from the ultraviolet down to the mid-infrared depending on the band gap of the NW material. Furthermore, first approaches towards the modification and optimization of such NW laser devices have been demonstrated. The underlying dynamics of the electronic and photonic NW systems have also been studied very recently, as they need to be understood in order to push the technological relevance of nano-scaled coherent light sources. Therefore, this review will first present novel measurement approaches in order to study the ultrafast temporal and optical mode dynamics of individual NW laser devices. Furthermore, these fundamental new insights are reviewed and deeply discussed towards the efficient control and adjustment of the dynamics in semiconductor NW lasers.

Pr-O-Al-N dielectrics for metal insulator semiconductor stacks

Energy Technology Data Exchange (ETDEWEB)

Henkel, Karsten; Torche, Mohamed; Sohal, Rakesh; Karavaev, Konstantin; Burkov, Yevgen; Schwiertz, Carola; Schmeisser, Dieter [Brandenburg University of Technology, Chair of Applied Physics and Sensors, K.-Wachsmann-Allee 1, 03046 Cottbus (Germany)

2011-02-15

This work focuses on praseodymium oxide films as a high-k material on silicon and silicon carbide (SiC) in metal insulator semiconductor samples. The electrical results are correlated to spectroscopic findings on this material system. Strong interfacial reactions between the praseodymium oxide and the semiconductor as well as silicon inter-diffusion into the high-k material are observed. The importance of a buffer layer is discussed and its optimisation is addressed, too. In particular the improvement of the performance by the introduction of an aluminium oxynitride buffer layer, which acts as an inter-diffusion barrier and reduces the leakage current, the interface state density and the equivalent oxide thickness is demonstrated. (Copyright copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Deep electron traps in HfO_2-based metal-oxide-semiconductor capacitors

International Nuclear Information System (INIS)

Salomone, L. Sambuco; Lipovetzky, J.; Carbonetto, S.H.; García Inza, M.A.; Redin, E.G.; Campabadal, F.

2016-01-01

Hafnium oxide (HfO_2) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO_2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO_2 interface at an energy level E_t = 1.59 eV below the HfO_2 conduction band edge with density N_t = 1.36 × 10"1"9 cm"−"3. A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. - Highlights: • We characterized deep electron trapping/detrapping in HfO_2 structures. • We modeled the experimental results through a tunneling-based model. • We obtained an electron trap energy level of 1.59 eV below conduction band edge. • We obtained a spatial trap distribution extending 1.7 nm within the insulator. • A simplified tunneling front model is able to reproduce the experimental results.

Graphene Oxide-Poly(dimethylsiloxane)-Based Lab-on-a-Chip Platform for Heavy-Metals Preconcentration and Electrochemical Detection.

Science.gov (United States)

Chałupniak, Andrzej; Merkoçi, Arben

2017-12-27

Herein, we present the application of a novel graphene oxide-poly(dimethylsiloxane) (GO-PDMS) composite in reversible adsorption/desorption, including detection of heavy metals. GO-PDMS was fabricated by simple blending of GO with silicon monomer in the presence of tetrahydrofuran, followed by polymerization initiated upon the addition of curing agent. We found GO concentration, curing agent concentration, pH, and contact time among the most important factors affecting the adsorption of Pb(II) used as a model heavy metal. The mechanism of adsorption is based on surface complexation, where oxygen active groups of negative charge can bind with bivalent metal ions Me(II). To demonstrate a practical application of this material, we fabricated microfluidic lab-on-a-chip platform for heavy-metals preconcentration and detection. This device consists of a screen-printed carbon electrode, a PDMS chip, and a GO-PDMS chip. The use of GO-PDMS preconcentration platform significantly improves the sensitivity of electrochemical detection of heavy metals (an increase of current up to 30× was observed), without the need of modifying electrodes or special reagents addition. Therefore, samples being so far below the limit of detection (0.5 ppb) were successfully detected. This approach is compatible also with real samples (seawater) as ionic strength was found as indifferent for the adsorption process. To the best of our knowledge, GO-PDMS was used for the first time in sensing application. Moreover, due to mechanical resistance and outstanding durability, it can be used multiple times unlike other GO-based platforms for heavy-metals adsorption.

Carrier transport and electronic structure in amorphous oxide semiconductor, a-InGaZnO4

International Nuclear Information System (INIS)

Takagi, Akihiro; Nomura, Kenji; Ohta, Hiromichi; Yanagi, Hiroshi; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

2005-01-01

Carrier transport properties in amorphous oxide semiconductor InGaZnO 4 (a-IGZO) thin films were investigated in detail using temperature dependence of Hall measurements. It was found that Hall mobility increased distinctly as carrier concentration increased. Unlikely conventional amorphous semiconductors such as a-Si/H, definite normal Hall voltage signals were observed on the films with carrier concentrations (N e )>10 16 cm -3 , and Hall mobilities as large as 15 cm 2 (Vs) -1 were attained in the films with N e >10 20 cm -3 . When N e was less than 10 19 cm -3 , the temperature dependence of Hall mobility showed thermally-activated behavior in spite that carrier concentration was independent of temperature. While, it changed to almost degenerate conduction at N e >10 18 cm -3 . These behaviors are similar to those observed in single-crystalline IGZO, and are explained by percolation conduction through distributed potential barriers which are formed in the vicinity of the conduction band bottom due to the randomness of the amorphous structure. The effective mass of a-IGZO was estimated to be ∼0.34 m e (m e is the mass of free electron) from optical data, which is almost the same as that of crystalline IGZO (∼0.32 m e )

Interface Structure of MoO3 on Organic Semiconductors

Science.gov (United States)

White, Robin T.; Thibau, Emmanuel S.; Lu, Zheng-Hong

2016-01-01

We have systematically studied interface structure formed by vapor-phase deposition of typical transition metal oxide MoO3 on organic semiconductors. Eight organic hole transport materials have been used in this study. Ultraviolet photoelectron spectroscopy and X-ray photoelectron spectroscopy are used to measure the evolution of the physical, chemical and electronic structure of the interfaces at various stages of MoO3 deposition on these organic semiconductor surfaces. For the interface physical structure, it is found that MoO3 diffuses into the underlying organic layer, exhibiting a trend of increasing diffusion with decreasing molecular molar mass. For the interface chemical structure, new carbon and molybdenum core-level states are observed, as a result of interfacial electron transfer from organic semiconductor to MoO3. For the interface electronic structure, energy level alignment is observed in agreement with the universal energy level alignment rule of molecules on metal oxides, despite deposition order inversion. PMID:26880185

Positron annihilation in a metal-oxide semiconductor studied by using a pulsed monoenergetic positron beam

Science.gov (United States)

Uedono, A.; Wei, L.; Tanigawa, S.; Suzuki, R.; Ohgaki, H.; Mikado, T.; Ohji, Y.

1993-12-01

The positron annihilation in a metal-oxide semiconductor was studied by using a pulsed monoenergetic positron beam. Lifetime spectra of positrons were measured as a function of incident positron energy for a polycrystalline Si(100 nm)/SiO2(400 nm)/Si specimen. Applying a gate voltage between the polycrystalline Si film and the Si substrate, positrons implanted into the specimen were accumulated at the SiO2/Si interface. From the measurements, it was found that the annihilation probability of ortho-positronium (ortho-Ps) drastically decreased at the SiO2/Si interface. The observed inhibition of the Ps formation was attributed to an interaction between positrons and defects at the SiO2/Si interface.

A CMOS Gm-C complex filter with on-chip automatic tuning for wireless sensor network application

International Nuclear Information System (INIS)

Wan Chuanchuan; Li Zhiqun; Hou Ningbing

2011-01-01

A G m -C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 μm CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

Multichannel, time-resolved picosecond laser ultrasound imaging and spectroscopy with custom complementary metal-oxide-semiconductor detector

International Nuclear Information System (INIS)

Smith, Richard J.; Light, Roger A.; Johnston, Nicholas S.; Pitter, Mark C.; Somekh, Mike G.; Sharples, Steve D.

2010-01-01

This paper presents a multichannel, time-resolved picosecond laser ultrasound system that uses a custom complementary metal-oxide-semiconductor linear array detector. This novel sensor allows parallel phase-sensitive detection of very low contrast modulated signals with performance in each channel comparable to that of a discrete photodiode and a lock-in amplifier. Application of the instrument is demonstrated by parallelizing spatial measurements to produce two-dimensional thickness maps on a layered sample, and spectroscopic parallelization is demonstrated by presenting the measured Brillouin oscillations from a gallium arsenide wafer. This paper demonstrates the significant advantages of our approach to pump probe systems, especially picosecond ultrasonics.

Multichannel, time-resolved picosecond laser ultrasound imaging and spectroscopy with custom complementary metal-oxide-semiconductor detector

Energy Technology Data Exchange (ETDEWEB)

Smith, Richard J.; Light, Roger A.; Johnston, Nicholas S.; Pitter, Mark C.; Somekh, Mike G. [Institute of Biophysics, Imaging and Optical Science, University of Nottingham, Nottinghamshire NG7 2RD (United Kingdom); Sharples, Steve D. [Applied Optics Group, Electrical Systems and Optics Research Division, University of Nottingham, Nottinghamshire NG7 2RD (United Kingdom)

2010-02-15

This paper presents a multichannel, time-resolved picosecond laser ultrasound system that uses a custom complementary metal-oxide-semiconductor linear array detector. This novel sensor allows parallel phase-sensitive detection of very low contrast modulated signals with performance in each channel comparable to that of a discrete photodiode and a lock-in amplifier. Application of the instrument is demonstrated by parallelizing spatial measurements to produce two-dimensional thickness maps on a layered sample, and spectroscopic parallelization is demonstrated by presenting the measured Brillouin oscillations from a gallium arsenide wafer. This paper demonstrates the significant advantages of our approach to pump probe systems, especially picosecond ultrasonics.

Infrared rectification in a nanoantenna-coupled metal-oxide-semiconductor tunnel diode.

Science.gov (United States)

Davids, Paul S; Jarecki, Robert L; Starbuck, Andrew; Burckel, D Bruce; Kadlec, Emil A; Ribaudo, Troy; Shaner, Eric A; Peters, David W

2015-12-01

Direct rectification of electromagnetic radiation is a well-established method for wireless power conversion in the microwave region of the spectrum, for which conversion efficiencies in excess of 84% have been demonstrated. Scaling to the infrared or optical part of the spectrum requires ultrafast rectification that can only be obtained by direct tunnelling. Many research groups have looked to plasmonics to overcome antenna-scaling limits and to increase the confinement. Recently, surface plasmons on heavily doped Si surfaces were investigated as a way of extending surface-mode confinement to the thermal infrared region. Here we combine a nanostructured metallic surface with a heavily doped Si infrared-reflective ground plane designed to confine infrared radiation in an active electronic direct-conversion device. The interplay of strong infrared photon-phonon coupling and electromagnetic confinement in nanoscale devices is demonstrated to have a large impact on ultrafast electronic tunnelling in metal-oxide-semiconductor (MOS) structures. Infrared dispersion of SiO2 near a longitudinal optical (LO) phonon mode gives large transverse-field confinement in a nanometre-scale oxide-tunnel gap as the wavelength-dependent permittivity changes from 1 to 0, which leads to enhanced electromagnetic fields at material interfaces and a rectified displacement current that provides a direct conversion of infrared radiation into electric current. The spectral and electrical signatures of the nanoantenna-coupled tunnel diodes are examined under broadband blackbody and quantum-cascade laser (QCL) illumination. In the region near the LO phonon resonance, we obtained a measured photoresponsivity of 2.7 mA W(-1) cm(-2) at -0.1 V.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon assisted tunneling

OpenAIRE

Koswatta, Siyuranga O.; Lundstrom, Mark S.; Nikonov, Dmitri E.

2007-01-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the non-equilibrium Green's functions formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (Y. Lu et al, J. Am. Chem. Soc.,...

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

International Nuclear Information System (INIS)

Spathis, C.; Birbas, A.; Georgakopoulou, K.

2015-01-01

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices

Semi-classical noise investigation for sub-40nm metal-oxide-semiconductor field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Spathis, C., E-mail: cspathis@ece.upatras.gr; Birbas, A.; Georgakopoulou, K. [Department of Electrical and Computer Engineering, University of Patras, Patras 26500 (Greece)

2015-08-15

Device white noise levels in short channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) dictate the performance and reliability of high-frequency circuits ranging from high-speed microprocessors to Low-Noise Amplifiers (LNAs) and microwave circuits. Recent experimental noise measurements with very short devices demonstrate the existence of suppressed shot noise, contrary to the predictions of classical channel thermal noise models. In this work we show that, as the dimensions continue to shrink, shot noise has to be considered when the channel resistance becomes comparable to the barrier resistance at the source-channel junction. By adopting a semi-classical approach and taking retrospectively into account transport, short-channel and quantum effects, we investigate the partitioning between shot and thermal noise, and formulate a predictive model that describes the noise characteristics of modern devices.

Photoreduction of carbon dioxide and water into formaldehyde and methanol on semiconductor materials

Energy Technology Data Exchange (ETDEWEB)

Aurian-Blajeni, B; Halmann, M; Manassen, J

1980-01-01

Heterogeneous photoassisted reduction of aqueous carbon dioxide was achieved using semiconductor powders, with either high-pressure Hg-lamps or sunlight as energy sources. The products were methanol, formaldehyde and methane. The reaction was carried out either as a gas-solid process, by passing carbon dioxide and water vapor over illuminated semiconductor surfaces, or as a liquid-solid reaction, by illuminating aqueous suspensions of semiconductor powders through which carbon dioxide was bubbled. Best results, under illumination by Hg-lamps, were obtained with aqueous suspensions of strontium titanate, SrTiO3, tungsten oxide, WO3, and titanium oxide, TiO2, resulting in absorbed energy conversion efficiencies of 6, 5.9 and 1.2 per cent, respectively.

Widely bandgap tunable amorphous Cd–Ga–O oxide semiconductors exhibiting electron mobilities ≥10 cm{sup 2 }V{sup −1 }s{sup −1}

Energy Technology Data Exchange (ETDEWEB)

Yanagi, Hiroshi, E-mail: hyanagi@yamanashi.ac.jp [Graduate Faculty of Interdisciplinary Research, University of Yamanashi, 4-4-37 Takeda, Kofu, Yamanashi 400-8510 (Japan); Sato, Chiyuki; Kimura, Yota [Interdisciplinary Graduate School of Medicine and Engineering, University of Yamanashi, 4-4-37 Takeda, Kofu, Yamanashi 400-8510 (Japan); Suzuki, Issei; Omata, Takahisa [Division of Material and Manufacturing Science, Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Kamiya, Toshio [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox S2-16, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan); Hosono, Hideo [Materials and Structures Laboratory, Tokyo Institute of Technology, Mailbox R3-4, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan); Materials Research Center for Element Strategy, Tokyo Institute of Technology, Mailbox S2-16, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan); Frontier Research Center, Tokyo Institute of Technology, Mailbox S2-16, 4259 Nagatsuta, Midori-ku, Yokohama 226-8503 (Japan)

2015-02-23

Amorphous oxide semiconductors exhibit large electron mobilities; however, their bandgaps are either too large for solar cells or too small for deep ultraviolet applications depending on the materials system. Herein, we demonstrate that amorphous Cd–Ga–O semiconductors display bandgaps covering the entire 2.5–4.3 eV region while maintaining large electron mobilities ≥10 cm{sup 2 }V{sup −1 }s{sup −1}. The band alignment diagram obtained by ultraviolet photoemission spectroscopy and the bandgap values reveal that these semiconductors form type-II heterojunctions with p-type Cu{sub 2}O, which is suitable for solar cells and solar-blind ultraviolet sensors.

Low-NO{sub x}, wood chip combustion

Energy Technology Data Exchange (ETDEWEB)

Saastamoinen, J.; Oravainen, H.; Haemaelaeinen, J.; Paakkinen, K. [VTT Energy, Jyvaeskylae (Finland)

1997-10-01

The regulations for nitrogen oxide emissions vary in different countries, but the general trend in the future will probably be that the emissions limits will be lowered also for wood combustion plants, which are small or medium size units. Thus, the development of wood chip burning furnaces (grate furnaces, fluidized bed combustors, stoker furnaces) with lower nitrogen oxide emissions, is important. The wood used in the combustor, its particle size, moisture and fuel properties (nitrogen content) affect the nitrogen emissions. The nitrogen oxide release is also much affected by the design and operation of the combustor (air staging, fuel air preheat, flue gas circulation, air to fuel mass ratio). The fate of nitrogen compounds originally in the virgin wood depends much on the design of the combustor system and by proper planning it is possible to reduce the emission of nitrogen oxides. Basic knowledge of the release of nitrogen compounds from single wood particles is attained. The release of gaseous nitrogen compounds from wood particles during pyrolysis and combustion is studied experimentally and by modelling. Nitrogen release is studied experimentally by two ways, by analysing the gas and by quenching the particle and analysing the char residue. Formation of nitrogen oxide emissions in a fuel bed is studied by modelling and by combustion experiments with a pot furnace. This research gives general information of nitrogen oxide formation in wood bunting especially in fixed beds. The development of a horizontal stoker burner for wood chips with low emissions is the practical aim of the research. (orig.)

Semiconductor properties and protective role of passive films of iron base alloys

International Nuclear Information System (INIS)

Fujimoto, Shinji; Tsuchiya, Hiroaki

2007-01-01

Semiconductor properties of passive films formed on the Fe-18Cr alloy in a borate buffer solution (pH = 8.4) and 0.1 M H 2 SO 4 solution were examined using a photoelectrochemical spectroscopy and an electrochemical impedance spectroscopy. Photo current reveals two photo action spectra that derived from outer hydroxide and inner oxide layers. A typical n-type semiconductor behaviour is observed by both photo current and impedance for the passive films formed in the borate buffer solution. On the other hand, a negative photo current generated, the absolute value of which decreased as applied potential increased in the sulfuric acid solution. This indicates that the passive film behaves as a p-type semiconductor. However, Mott-Schottky plot revealed the typical n-type semiconductor property. It is concluded that the passive film on the Fe-18Cr alloy formed in the borate buffer solution is composed of both n-type outer hydroxide and inner oxide layers. On the other hand, the passive film of the Fe-18Cr alloy in the sulphuric acid consists of p-type oxide and n-type hydroxide layers. The behaviour of passive film growth and corrosion was discussed in terms of the electronic structure in the passive film

Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

Science.gov (United States)

Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

2009-12-15

Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

Science.gov (United States)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

Science.gov (United States)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

The physics of semiconductors an introduction including nanophysics and applications

CERN Document Server

Grundmann, Marius

2016-01-01

The 3rd edition of this successful textbook contains ample material for a comprehensive upper-level undergraduate or beginning graduate course, guiding readers to the point where they can choose a special topic and begin supervised research. The textbook provides a balance between essential aspects of solid-state and semiconductor physics, on the one hand, and the principles of various semiconductor devices and their applications in electronic and photonic devices, on the other. It highlights many practical aspects of semiconductors such as alloys, strain, heterostructures, nanostructures, that are necessary in modern semiconductor research but typically omitted in textbooks. Coverage also includes additional advanced topics, such as Bragg mirrors, resonators, polarized and magnetic semiconductors, nanowires, quantum dots, multi-junction solar cells, thin film transistors, carbon-based nanostructures and transparent conductive oxides. The text derives explicit formulas for many results to support better under...

An electrochromatography chip with integrated waveguides for UV absorbance detection

International Nuclear Information System (INIS)

Gustafsson, O; Mogensen, K B; Ohlsson, P D; Kutter, J P; Liu, Y; Jacobson, S C

2008-01-01

A silicon-based microchip for electrochromatographic separations is presented. Apart from a microfluidic network, the microchip has integrated UV-transparent waveguides for detection and integrated couplers for optical fibers on the chip, yielding the most complete chromatography microchip to date in terms of the integration of optical components. The microfluidic network and the optical components are fabricated in a single etching step in silicon and subsequently thermally oxidized. The separation column consists of a regular array of microfabricated solid support structures with a monolayer of an octylsilane covalently bonded to the surfaces to provide chromatographic interaction. The chip features a 1 mm long U-shaped detection cell and planar silicon dioxide waveguides that couple light to and from the detection cell. Microfabricated on-chip fiber couplers assure perfect alignment of optical fibers to the waveguides. The entire oxidized silicon microchip structure is sealed with a glass lid. Reversed phase electrochromatographic separation of three neutral compounds is demonstrated using UV absorbance detection at 254 nm. Baseline separation of the analytes is achieved in less than two minutes

Optically pumped semiconductor lasers for atomic and molecular physics

Science.gov (United States)

Burd, S.; Leibfried, D.; Wilson, A. C.; Wineland, D. J.

2015-03-01

Experiments in atomic, molecular and optical (AMO) physics rely on lasers at many different wavelengths and with varying requirements on spectral linewidth, power and intensity stability. Optically pumped semiconductor lasers (OPSLs), when combined with nonlinear frequency conversion, can potentially replace many of the laser systems currently in use. We are developing a source for laser cooling and spectroscopy of Mg+ ions at 280 nm, based on a frequency quadrupled OPSL with the gain chip fabricated at the ORC at Tampere Univ. of Technology, Finland. This OPSL system could serve as a prototype for many other sources used in atomic and molecular physics.

Influence of quantizing magnetic field and Rashba effect on indium arsenide metal-oxide-semiconductor structure accumulation capacitance

Science.gov (United States)

Kovchavtsev, A. P.; Aksenov, M. S.; Tsarenko, A. V.; Nastovjak, A. E.; Pogosov, A. G.; Pokhabov, D. A.; Tereshchenko, O. E.; Valisheva, N. A.

2018-05-01

The accumulation capacitance oscillations behavior in the n-InAs metal-oxide-semiconductor structures with different densities of the built-in charge (Dbc) and the interface traps (Dit) at temperature 4.2 K in the magnetic field (B) 2-10 T, directed perpendicular to the semiconductor-dielectric interface, is studied. A decrease in the oscillation frequency and an increase in the capacitance oscillation amplitude are observed with the increase in B. At the same time, for a certain surface accumulation band bending, the influence of the Rashba effect, which is expressed in the oscillations decay and breakdown, is traced. The experimental capacitance-voltage curves are in a good agreement with the numeric simulation results of the self-consistent solution of Schrödinger and Poisson equations in the magnetic field, taking into account the quantization, nonparabolicity of dispersion law, and Fermi-Dirac electron statistics, with the allowance for the Rashba effect. The Landau quantum level broadening in a two-dimensional electron gas (Lorentzian-shaped density of states), due to the electron scattering mechanism, linearly depends on the magnetic field. The correlation between the interface electronic properties and the characteristic scattering times was established.

Semiconductor electrolyte photovoltaic energy converter

Science.gov (United States)

Anderson, W. W.; Anderson, L. B.

1975-01-01

Feasibility and practicality of a solar cell consisting of a semiconductor surface in contact with an electrolyte are evaluated. Basic components and processes are detailed for photovoltaic energy conversion at the surface of an n-type semiconductor in contact with an electrolyte which is oxidizing to conduction band electrons. Characteristics of single crystal CdS, GaAs, CdSe, CdTe and thin film CdS in contact with aqueous and methanol based electrolytes are studied and open circuit voltages are measured from Mott-Schottky plots and open circuit photo voltages. Quantum efficiencies for short circuit photo currents of a CdS crystal and a 20 micrometer film are shown together with electrical and photovoltaic properties. Highest photon irradiances are observed with the GaAs cell.

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

International Nuclear Information System (INIS)

Ni Henan; Wu Liangcai; Song Zhitang; Hui Chun

2009-01-01

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO 2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time. (semiconductor devices)

Soft error modeling and analysis of the Neutron Intercepting Silicon Chip (NISC)

International Nuclear Information System (INIS)

Celik, Cihangir; Unlue, Kenan; Narayanan, Vijaykrishnan; Irwin, Mary J.

2011-01-01

Soft errors are transient errors caused due to excess charge carriers induced primarily by external radiations in the semiconductor devices. Soft error phenomena could be used to detect thermal neutrons with a neutron monitoring/detection system by enhancing soft error occurrences in the memory devices. This way, one can convert all semiconductor memory devices into neutron detection systems. Such a device is being developed at The Pennsylvania State University and named Neutron Intercepting Silicon Chip (NISC). The NISC is envisioning a miniature, power efficient, and active/passive operation neutron sensor/detector system. NISC aims to achieve this goal by introducing 10 B-enriched Borophosphosilicate Glass (BPSG) insulation layers in the semiconductor memories. In order to model and analyze the NISC, an analysis tool using Geant4 as the transport and tracking engine is developed for the simulation of the charged particle interactions in the semiconductor memory model, named NISC Soft Error Analysis Tool (NISCSAT). A simple model with 10 B-enriched layer on top of the lumped silicon region is developed in order to represent the semiconductor memory node. Soft error probability calculations were performed via the NISCSAT with both single node and array configurations to investigate device scaling by using different node dimensions in the model. Mono-energetic, mono-directional thermal and fast neutrons are used as the neutron sources. Soft error contribution due to the BPSG layer is also investigated with different 10 B contents and the results are presented in this paper.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

Science.gov (United States)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

International Nuclear Information System (INIS)

Moslehi, M.M.; Davis, C.

1989-01-01

Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

Combinatorial Discovery and Optimization of the Composition, Doping and Morphology of New Oxide Semiconductors for Efficient Photoelectrochemical Water Splitting

Energy Technology Data Exchange (ETDEWEB)

Parkinson, Bruce A. [Univ. of Wyoming, Laramie, WY (United States); Jianghua, He [Univ. of Wyoming, Laramie, WY (United States)

2015-01-06

The increasing need for carbon free energy has focused renewed attention on solar energy conversion. Although photovoltaic cells excel at directly converting of solar energy to electricity, they do not directly produce stored energy or fuels that account for more than 75% of current energy use. Direct photoelectrolysis of water has the advantage of converting solar energy directly to hydrogen, an ideal non-carbon and nonpolluting energy carrier, by replacing both a photovoltaic array and an electrolysis unit with one potentially inexpensive device. Unfortunately no materials are currently known to efficiently photoelectrolyze water that are, efficient, inexpensive and stable under illumination in electrolytes for many years. Nanostructured semiconducting metal oxides could potentially fulfill these requirements, making them the most promising materials for solar water photoelectrolysis, however no oxide semiconductor has yet been discovered with all the required properties. We have developed a simple, high-throughput combinatorial approach to prepare and screen many multi component metal oxides for water photoelectrolysis activity. The approach uses ink jet printing of overlapping patterns of soluble metal oxide precursors onto conductive glass substrates. Subsequent pyrolysis produces metal oxide phases that are screened for photoelectrolysis activity by measuring photocurrents produced by scanning a laser over the printed patterns in aqueous electrolytes. Several promising and unexpected compositions have been identified.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor

Energy Technology Data Exchange (ETDEWEB)

Moghadam, Reza M. [Department; Xiao, Zhiyong [Department; Ahmadi-Majlan, Kamyar [Department; Grimley, Everett D. [Department; Bowden, Mark [Environmental; amp, Biological Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352, United States; Ong, Phuong-Vu [Physical; amp, Computational Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352, United States; Chambers, Scott A. [Physical; amp, Computational Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352, United States; Lebeau, James M. [Department; Hong, Xia [Department; Sushko, Peter V. [Physical; amp, Computational Sciences Directorate, Pacific Northwest National Laboratory, Richland, Washington 99352, United States; Ngai, Joseph H. [Department

2017-09-13

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that the ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.

Platinum nanoparticles on gallium nitride surfaces: effect of semiconductor doping on nanoparticle reactivity.

Science.gov (United States)

Schäfer, Susanne; Wyrzgol, Sonja A; Caterino, Roberta; Jentys, Andreas; Schoell, Sebastian J; Hävecker, Michael; Knop-Gericke, Axel; Lercher, Johannes A; Sharp, Ian D; Stutzmann, Martin

2012-08-01

Platinum nanoparticles supported on n- and p-type gallium nitride (GaN) are investigated as novel hybrid systems for the electronic control of catalytic activity via electronic interactions with the semiconductor support. In situ oxidation and reduction were studied with high pressure photoemission spectroscopy. The experiments revealed that the underlying wide-band-gap semiconductor has a large influence on the chemical composition and oxygen affinity of supported nanoparticles under X-ray irradiation. For as-deposited Pt cuboctahedra supported on n-type GaN, a higher fraction of oxidized surface atoms was observed compared to cuboctahedral particles supported on p-type GaN. Under an oxygen atmosphere, immediate oxidation was recorded for nanoparticles on n-type GaN, whereas little oxidation was observed for nanoparticles on p-type GaN. Together, these results indicate that changes in the Pt chemical state under X-ray irradiation depend on the type of GaN doping. The strong interaction between the nanoparticles and the support is consistent with charge transfer of X-ray photogenerated free carriers at the semiconductor-nanoparticle interface and suggests that GaN is a promising wide-band-gap support material for photocatalysis and electronic control of catalysis.

A CMOS G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor network application

Energy Technology Data Exchange (ETDEWEB)

Wan Chuanchuan; Li Zhiqun; Hou Ningbing, E-mail: zhiqunli@seu.edu.cn [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

2011-05-15

A G{sub m}-C complex filter with on-chip automatic tuning for wireless sensor networks is designed and implemented using 0.18 {mu}m CMOS process. This filter is synthesized from a low-pass 5th-order Chebyshev RLC ladder filter prototype by means of capacitors and fully balanced transconductors. A conventional phase-locked loop is used to realize the on-chip automatic tuning for both center frequency and bandwidth control. The filter is centered at 2 MHz with a bandwidth of 2.4 MHz. The measured results show that the filter provides more than 45 dB image rejection while the ripple in the pass-band is less than 1.2 dB. The complete filter including on-chip tuning circuit consumes 4.9 mA with 1.8 V single supply voltage. (semiconductor integrated circuits)

An Ultrasensitive Organic Semiconductor NO2 Sensor Based on Crystalline TIPS-Pentacene Films.

Science.gov (United States)

Wang, Zi; Huang, Lizhen; Zhu, Xiaofei; Zhou, Xu; Chi, Lifeng

2017-10-01

Organic semiconductor gas sensor is one of the promising candidates of room temperature operated gas sensors with high selectivity. However, for a long time the performance of organic semiconductor sensors, especially for the detection of oxidizing gases, is far behind that of the traditional metal oxide gas sensors. Although intensive attempts have been made to address the problem, the performance and the understanding of the sensing mechanism are still far from sufficient. Herein, an ultrasensitive organic semiconductor NO 2 sensor based on 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-petacene) is reported. The device achieves a sensitivity over 1000%/ppm and fast response/recovery, together with a low limit of detection (LOD) of 20 ppb, all of which reach the level of metal oxide sensors. After a comprehensive analysis on the morphology and electrical properties of the organic films, it is revealed that the ultrahigh performance is largely related to the film charge transport ability, which was less concerned in the studies previously. And the combination of efficient charge transport and low original charge carrier concentration is demonstrated to be an effective access to obtain high performance organic semiconductor gas sensors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

Science.gov (United States)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Ultraviolet-visible electroluminescence from metal-oxide-semiconductor devices with CeO2 films on silicon

International Nuclear Information System (INIS)

Lv, Chunyan; Zhu, Chen; Wang, Canxing; Li, Dongsheng; Ma, Xiangyang; Yang, Deren

2015-01-01

We report on ultraviolet-visible (UV-Vis) electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with the CeO 2 films annealed at low temperatures. At the same injection current, the UV-Vis EL from the MOS device with the 550 °C-annealed CeO 2 film is much stronger than that from the counterpart with the 450 °C-annealed CeO 2 film. This is due to that the 550 °C-annealed CeO 2 film contains more Ce 3+ ions and oxygen vacancies. It is tentatively proposed that the recombination of the electrons in multiple oxygen-vacancy–related energy levels with the holes in Ce 4f 1 energy band pertaining to Ce 3+ ions leads to the UV-Vis EL

Wide-gap layered oxychalcogenide semiconductors: Materials, electronic structures and optoelectronic properties

International Nuclear Information System (INIS)

Ueda, Kazushige; Hiramatsu, Hidenori; Hirano, Masahiro; Kamiya, Toshio; Hosono, Hideo

2006-01-01

Applying the concept of materials design for transparent conductive oxides to layered oxychalcogenides, several p-type and n-type layered oxychalcogenides were proposed as wide-gap semiconductors and their basic optical and electrical properties were examined. The layered oxychalcogenides are composed of ionic oxide layers and covalent chalcogenide layers, which bring wide-gap and conductive properties to these materials, respectively. The electronic structures of the materials were examined by normal/inverse photoemission spectroscopy and energy band calculations. The results of the examinations suggested that these materials possess unique features more than simple wide-gap semiconductors. Namely, the layered oxychalcogenides are considered to be extremely thin quantum wells composed of the oxide and chalcogenide layers or 2D chalcogenide crystals/molecules embedded in an oxide matrix. Observation of step-like absorption edges, large band gap energy and large exciton binding energy demonstrated these features originating from 2D density of states and quantum size effects in these layered materials

Oxidation experiment of metal uranium waste for the treatment of depleted uranium waste

International Nuclear Information System (INIS)

Kang, K. H.; Kwac, K. I.; Kim, K. J.

2001-01-01

A study was conducted on the oxidation behavior of U-Ti chips(Depleted Uranium, DU chips) using an XRD and a thermogravimetric analyzer in the temperature range from 250 to 500 .deg. C in air. At the temperature lower than 400 .deg. C, DU chips were converted to UO 2 , U 3 O 7 and U 3 O 8 whereas at the temperature higher than 400 .deg. C, DU chips were completely converted to U 3 O 8 , the most stable form of uranium oxide. The activation energy for the oxidation of U-Ti chips is found, 44.9 kJ/mol and the oxidation rate in terms of weight gain (%) can be expressed as ; dW/dt=8.4 x 10 2 e(-44.9 kJ/mol /RT) wt %/min (250≤T(deg. C)≤500) where W=weight gain (%), t=time and T=temperature

Gallium nitride on gallium oxide substrate for integrated nonlinear optics

KAUST Repository

Awan, Kashif M.; Dolgaleva, Ksenia; Mumthaz Muhammed, Mufasila; Roqan, Iman S.

2017-01-01

Gallium Nitride (GaN), being a direct bandgap semiconductor with a wide bandgap and high thermal stability, is attractive for optoelectronic and electronic applications. Furthermore, due to its high optical nonlinearity — the characteristic of all 111-V semiconductors — GaN is also expected to be a suitable candidate for integrated nonlinear photonic circuits for a plethora of apphcations, ranging from on-chip wavelength conversion to quantum computing. Although GaN devices are in commercial production, it still suffers from lack of a suitable substrate material to reduce structural defects like high densities of threading dislocations (TDs), stacking faults, and grain boundaries. These defects significandy deteriorate the optical quality of the epi-grown GaN layer, since they act as non-radiative recombination centers. Recent studies have shown that GaN grown on (−201) β-Gallium Oxide (Ga2O3) has superior optical quality due to a better lattice matching as compared to GaN grown on Sapphire (Al2O3) [1-3]. In this work, we report on the fabrication of GaN waveguides on GaiOj substrate and their optical characterization to assess their feasibihty for efficient four-wave mixing (FWM).

Gallium nitride on gallium oxide substrate for integrated nonlinear optics

KAUST Repository

Awan, Kashif M.

2017-11-22

Gallium Nitride (GaN), being a direct bandgap semiconductor with a wide bandgap and high thermal stability, is attractive for optoelectronic and electronic applications. Furthermore, due to its high optical nonlinearity — the characteristic of all 111-V semiconductors — GaN is also expected to be a suitable candidate for integrated nonlinear photonic circuits for a plethora of apphcations, ranging from on-chip wavelength conversion to quantum computing. Although GaN devices are in commercial production, it still suffers from lack of a suitable substrate material to reduce structural defects like high densities of threading dislocations (TDs), stacking faults, and grain boundaries. These defects significandy deteriorate the optical quality of the epi-grown GaN layer, since they act as non-radiative recombination centers. Recent studies have shown that GaN grown on (−201) β-Gallium Oxide (Ga2O3) has superior optical quality due to a better lattice matching as compared to GaN grown on Sapphire (Al2O3) [1-3]. In this work, we report on the fabrication of GaN waveguides on GaiOj substrate and their optical characterization to assess their feasibihty for efficient four-wave mixing (FWM).

2012 Gordon Research Conference on Defects in Semiconductors - Formal Schedule and Speaker/Poster Program

Energy Technology Data Exchange (ETDEWEB)

Glaser, Evan [Naval Research Lab. (NRL), Washington, DC (United States)

2012-08-17

The meeting shall strive to develop and further the fundamental understanding of defects and their roles in the structural, electronic, optical, and magnetic properties of bulk, thin film, and nanoscale semiconductors and device structures. Point and extended defects will be addressed in a broad range of electronic materials of particular current interest, including wide bandgap semiconductors, metal-oxides, carbon-based semiconductors (e.g., diamond, graphene, etc.), organic semiconductors, photovoltaic/solar cell materials, and others of similar interest. This interest includes novel defect detection/imaging techniques and advanced defect computational methods.

First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

International Nuclear Information System (INIS)

Mao, L.F.; Wang, Z.O.

2008-01-01

HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

Silicon Chip-to-Chip Mode-Division Multiplexing

DEFF Research Database (Denmark)

Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

2018-01-01

A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

Transparent Oxide Semiconductors for Emerging Electronics

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2013-01-01

Transparent oxide electronics have emerged as promising materials to shape the future of electronics. While several n-type oxides have been already studied and demonstrated feasibility to be used as active materials in thin film transistors, high

Semiconductor devices for entangled photon pair generation: a review

Science.gov (United States)

Orieux, Adeline; Versteegh, Marijn A. M.; Jöns, Klaus D.; Ducci, Sara

2017-07-01

Entanglement is one of the most fascinating properties of quantum mechanical systems; when two particles are entangled the measurement of the properties of one of the two allows the properties of the other to be instantaneously known, whatever the distance separating them. In parallel with fundamental research on the foundations of quantum mechanics performed on complex experimental set-ups, we assist today with bourgeoning of quantum information technologies bound to exploit entanglement for a large variety of applications such as secure communications, metrology and computation. Among the different physical systems under investigation, those involving photonic components are likely to play a central role and in this context semiconductor materials exhibit a huge potential in terms of integration of several quantum components in miniature chips. In this article we review the recent progress in the development of semiconductor devices emitting entangled photons. We will present the physical processes allowing the generation of entanglement and the tools to characterize it; we will give an overview of major recent results of the last few years and highlight perspectives for future developments.

Synthesis of visible-light responsive graphene oxide/TiO(2) composites with p/n heterojunction.

Science.gov (United States)

Chen, Chao; Cai, Weimin; Long, Mingce; Zhou, Baoxue; Wu, Yahui; Wu, Deyong; Feng, Yujie

2010-11-23

Graphene oxide/TiO(2) composites were prepared by using TiCl(3) and graphene oxide as reactants. The concentration of graphene oxide in starting solution played an important role in photoelectronic and photocatalytic performance of graphene oxide/TiO(2) composites. Either a p-type or n-type semiconductor was formed by graphene oxide in graphene oxide/TiO(2) composites. These semiconductors could be excited by visible light with wavelengths longer than 510 nm and acted as sensitizer in graphene oxide/TiO(2) composites. Visible-light driven photocatalytic performance of graphene oxide/TiO(2) composites in degradation of methyl orange was also studied. Crystalline quality and chemical states of carbon elements from graphene oxide in graphene oxide/TiO(2) composites depended on the concentration of graphene oxide in the starting solution. This study shows a possible way to fabricate graphene oxide/semiconductor composites with different properties by using a tunable semiconductor conductivity type of graphene oxide.

Positron annihilation and Wheeler complexes in semiconductors

International Nuclear Information System (INIS)

Prokop'ev, E.P.

1995-01-01

Properties of Ps-Ex (positron-exciton) complex nature Wheeler complexes that may be formed at irradiation of semiconductors and ion crystals by positrons at low temperature under conditions of optical excitation by excitons are studied. Binding energy of similar and more complex systems regarding decomposition in Ps and Ex and/or Ex ± exceeds, at least, 0.1 eV, while lifetime regarding biquantum-self-annihilation constitutes τ 2γ ∼5.02x10 - 10 κ c 3 c (κ c -phenomenological parameter of the effective mass method). The lifetime estimations enabled to conclude that Ps-Ex complexes may be detected in some oxide semiconductors, in zinc sulfide, as well as, in alkaline-haloid crystals. At the same time, in silicon, gallium arsenide and in other semiconductors of A 3 B 5 and A 2 B 6 it is highly improbable to observe these complexes. 27 refs

Charged Semiconductor Defects Structure, Thermodynamics and Diffusion

CERN Document Server

Seebauer, Edmund G

2009-01-01

The technologically useful properties of a solid often depend upon the types and concentrations of the defects it contains. Not surprisingly, defects in semiconductors have been studied for many years, in many cases with a view towards controlling their behavior through various forms of "defect engineering." For example, in the bulk, charging significantly affects the total concentration of defects that are available to mediate phenomena such as solid-state diffusion. Surface defects play an important role in mediating surface mass transport during high temperature processing steps such as epitaxial film deposition, diffusional smoothing in reflow, and nanostructure formation in memory device fabrication. Charged Semiconductor Defects details the current state of knowledge regarding the properties of the ionized defects that can affect the behavior of advanced transistors, photo-active devices, catalysts, and sensors. Features: Group IV, III-V, and oxide semiconductors; Intrinsic and extrinsic defects; and, P...

Effect of chip size on mechanical property and microstructure of AZ91D magnesium alloy prepared by solid state recycling

International Nuclear Information System (INIS)

Hu Maoliang; Ji Zesheng; Chen Xiaoyu; Zhang Zhenkao

2008-01-01

In this study, different kinds of AZ91D magnesium alloy chips were prepared by solid state recycling. Mechanical properties and microstructures of the recycled specimens were investigated. Various microstructural analyses were performed using the techniques of optical microscopy, scanning electron microscopy and oxygen-nitrogen analysis. Microstructural observations revealed that all the recycled specimens consisted of fine grains due to dynamic recrystallization. The oxide precipitate content is closely related to the recycled chip size. Accumulated oxygen concentration linearly increases with the total surface area of the machined chips in the recycled specimens. Ambient oxide in the recycled specimen contributes to a higher ultimate tensile strength and a higher elongation to failure; however, excessive oxide in the recycled specimen may adversely affect the elongation to failure

Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

International Nuclear Information System (INIS)

Mishra, Vijay; Kataria, S.K.

2005-01-01

A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

PdO doping tunes band-gap energy levels as well as oxidative stress responses to a Co₃O₄ p-type semiconductor in cells and the lung.

Science.gov (United States)

Zhang, Haiyuan; Pokhrel, Suman; Ji, Zhaoxia; Meng, Huan; Wang, Xiang; Lin, Sijie; Chang, Chong Hyun; Li, Linjiang; Li, Ruibin; Sun, Bingbing; Wang, Meiying; Liao, Yu-Pei; Liu, Rong; Xia, Tian; Mädler, Lutz; Nel, André E

2014-04-30

We demonstrate through PdO doping that creation of heterojunctions on Co3O4 nanoparticles can quantitatively adjust band-gap and Fermi energy levels to study the impact of metal oxide nanoparticle semiconductor properties on cellular redox homeostasis and hazard potential. Flame spray pyrolysis (FSP) was used to synthesize a nanoparticle library in which the gradual increase in the PdO content (0-8.9%) allowed electron transfer from Co3O4 to PdO to align Fermi energy levels across the heterojunctions. This alignment was accompanied by free hole accumulation at the Co3O4 interface and production of hydroxyl radicals. Interestingly, there was no concomitant superoxide generation, which could reflect the hole dominance of a p-type semiconductor. Although the electron flux across the heterojunctions induced upward band bending, the E(c) levels of the doped particles showed energy overlap with the biological redox potential (BRP). This allows electron capture from the redox couples that maintain the BRP from -4.12 to -4.84 eV, causing disruption of cellular redox homeostasis and induction of oxidative stress. PdO/Co3O4 nanoparticles showed significant increases in cytotoxicity at 25, 50, 100, and 200 μg/mL, which was enhanced incrementally by PdO doping in BEAS-2B and RAW 264.7 cells. Oxidative stress presented as a tiered cellular response involving superoxide generation, glutathione depletion, cytokine production, and cytotoxicity in epithelial and macrophage cell lines. A progressive series of acute pro-inflammatory effects could also be seen in the lungs of animals exposed to incremental PdO-doped particles. All considered, generation of a combinatorial PdO/Co3O4 nanoparticle library with incremental heterojunction density allowed us to demonstrate the integrated role of E(v), E(c), and E(f) levels in the generation of oxidant injury and inflammation by the p-type semiconductor, Co3O4.

General Observation of Photocatalytic Oxygen Reduction to Hydrogen Peroxide by Organic Semiconductor Thin Films and Colloidal Crystals.

Science.gov (United States)

Gryszel, Maciej; Sytnyk, Mykhailo; Jakešová, Marie; Romanazzi, Giuseppe; Gabrielsson, Roger; Heiss, Wolfgang; Głowacki, Eric Daniel

2018-04-25

Low-cost semiconductor photocatalysts offer unique possibilities for industrial chemical transformations and energy conversion applications. We report that a range of organic semiconductors are capable of efficient photocatalytic oxygen reduction to H 2 O 2 in aqueous conditions. These semiconductors, in the form of thin films, support a 2-electron/2-proton redox cycle involving photoreduction of dissolved O 2 to H 2 O 2 , with the concurrent photooxidation of organic substrates: formate, oxalate, and phenol. Photochemical oxygen reduction is observed in a pH range from 2 to 12. In cases where valence band energy of the semiconductor is energetically high, autoxidation competes with oxidation of the donors, and thus turnover numbers are low. Materials with deeper valence band energies afford higher stability and also oxidation of H 2 O to O 2 . We found increased H 2 O 2 evolution rate for surfactant-stabilized nanoparticles versus planar thin films. These results evidence that photochemical O 2 reduction may be a widespread feature of organic semiconductors, and open potential avenues for organic semiconductors for catalytic applications.

Introduction to Open Core Protocol Fastpath to System-on-Chip Design

CERN Document Server

Schwaderer, W David

2012-01-01

This book introduces Open Core Protocol (OCP), not as a conventional hardware communications protocol but as a meta-protocol: a means for describing and capturing the communications requirements of an IP core, and mapping them to a specific set of signals with known semantics.  Readers will learn the capabilities of OCP as a semiconductor hardware interface specification that allows different System-On-Chip (SoC) cores to communicate.  The OCP methodology presented enables intellectual property designers to design core interfaces in standard ways. This facilitates reusing OCP-compliant cores across multiple SoC designs which, in turn, drastically reduces design times, support costs, and overall cost for electronics/SoCs. Provides a comprehensive introduction to Open Core Protocol, which is more accessible than the full specification; Designed as a hands-on, how-to guide to semiconductor design; Includes numerous, real “usage examples” which are not available in the full specification; Integrates coverag...

Silicon drift detectors with on-chip electronics for x-ray spectroscopy.

Science.gov (United States)

Fiorini, C; Longoni, A; Hartmann, R; Lechner, P; Strüder, L

1997-01-01

The silicon drift detector (SDD) is a semiconductor device based on high resistivity silicon fully depleted through junctions implanted on both sides of the semiconductor wafer. The electrons generated by the ionizing radiation are driven by means of a suitable electric field from the point of interaction toward a collecting anode of small capacitance, independent of the active area of the detector. A suitably designed front-end JFET has been directly integrated on the detector chip close to the anode region, in order to obtain a nearly ideal capacitive matching between detector and transistor and to minimize the stray capacitances of the connections. This feature allows it to reach high energy resolution also at high count rates and near room temperature. The present work describes the structure and the performance of SDDs specially designed for high resolution spectroscopy with soft x rays at high detection rate. Experimental results of SDDs used in spectroscopy applications are also reported.

Nanomorphology Effects in Semiconductors with Native Ferromagnetism: Hierarchical Europium (II) Oxide Tubes Prepared via a Topotactic Nanostructure Transition.

Science.gov (United States)

Trepka, Bastian; Erler, Philipp; Selzer, Severin; Kollek, Tom; Boldt, Klaus; Fonin, Mikhail; Nowak, Ulrich; Wolf, Daniel; Lubk, Axel; Polarz, Sebastian

2018-01-01

Semiconductors with native ferromagnetism barely exist and defined nanostructures are almost unknown. This lack impedes the exploration of a new class of materials characterized by a direct combination of effects on the electronic system caused by quantum confinement effects with magnetism. A good example is EuO for which currently no reliable routes for nanoparticle synthesis can be established. Bottom-up approaches applicable to other oxides fail because of the labile oxidation state +II. Instead of targeting a direct synthesis, the two steps-"structure control" and "chemical transformation"-are separated. The generation of a transitional, hybrid nanophase is followed by its conversion into EuO under full conservation of all morphological features. Hierarchical EuO materials are now accessible in the shape of oriented nanodisks stacked to tubular particles. Magnetically, the coupling of either vortex or onion states has been found. An unexpected temperature dependence is governed by thermally activated transitions between these states. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Proceedings of wide band gap semiconductors

International Nuclear Information System (INIS)

Moustakas, T.D.; Pankove, J.I.; Hamakawa, Y.

1992-01-01

This book contains the proceedings of wide band gap semiconductors. Wide band gap semiconductors are under intense study because of their potential applications in photonic devices in the visible and ultraviolet part of the electromagnetic spectrum, and devices for high temperature, high frequency and high power electronics. Additionally, due to their unique mechanical, thermal, optical, chemical, and electronic properties many wide band gap semiconductors are anticipated to find applications in thermoelectric, electrooptic, piezoelectric and acoustooptic devices as well as protective coatings, hard coatings and heat sinks. Material systems covered in this symposium include diamond, II-VI compounds, III-V nitrides, silicon carbide, boron compounds, amorphous and microcrystalline semiconductors, chalcopyrites, oxides and halides. The various papers addressed recent experimental and theoretical developments. They covered issues related to crystal growth (bulk and thin films), structure and microstructure, defects, doping, optoelectronic properties and device applications. A theoretical session was dedicated to identifying common themes in the heteroepitaxy and the role of defects in doping, compensation and phase stability of this unique class of materials. Important experimental milestones included the demonstrations of bright blue injection luminescence at room temperatures from junctions based on III-V nitrides and a similar result from multiple quantum wells in a ZnSe double heterojunction at liquid nitrogen temperatures

Neutron and gamma irradiation effects on power semiconductor switches

International Nuclear Information System (INIS)

Schwarze, G.E.; Frasca, A.J.

1990-01-01

The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN bipolar junction transistors (BJTs), and metal-oxide-semiconductor field effect transistors (MOSFETs)

Ultrasensitive NO2 gas sensors using hybrid heterojunctions of multi-walled carbon nanotubes and on-chip grown SnO2 nanowires

Science.gov (United States)

Nguyet, Quan Thi Minh; Van Duy, Nguyen; Manh Hung, Chu; Hoa, Nguyen Duc; Van Hieu, Nguyen

2018-04-01

Hybrid heterojunction devices are designed for ultrahigh response to NO2 toxic gas. The devices were constructed by assembling multi-walled carbon nanotubes (MWCNTs) on a microelectrode chip bridged bare Pt-electrode and a Pt-electrode with pre-grown SnO2 nanowires (NWs). All heterojunction devices were realized using different types of MWCNTs, which exhibit ultrahigh response to sub-ppm NO2 gas at 50 °C operated in the reverse bias mode. The response to 1 ppm NO2 gas reaches 11300, which is about 100 times higher than that of a back-to-back heterojunction device fabricated from SnO2 NWs and MWCNTs. In addition, the present device exhibits an ultralow detection limit of about 0.68 ppt. The modulation of trap-assisted tunneling current under reverse bias is the main gas-sensing mechanism. This principle device presents a concept for developing gas sensors made of a hybrid between semiconductor metal oxide NWs and CNTs.

Magnesium Oxide (MgO) pH-sensitive Sensing Membrane in Electrolyte-Insulator-Semiconductor Structures with CF4 Plasma Treatment.

Science.gov (United States)

Kao, Chyuan-Haur; Chang, Chia Lung; Su, Wei Ming; Chen, Yu Tzu; Lu, Chien Cheng; Lee, Yu Shan; Hong, Chen Hao; Lin, Chan-Yu; Chen, Hsiang

2017-08-03

Magnesium oxide (MgO) sensing membranes in pH-sensitive electrolyte-insulator-semiconductor structures were fabricated on silicon substrate. To optimize the sensing capability of the membrane, CF 4 plasma was incorporated to improve the material quality of MgO films. Multiple material analyses including FESEM, XRD, AFM, and SIMS indicate that plasma treatment might enhance the crystallization and increase the grain size. Therefore, the sensing behaviors in terms of sensitivity, linearity, hysteresis effects, and drift rates might be improved. MgO-based EIS membranes with CF 4 plasma treatment show promise for future industrial biosensing applications.

Characterization of advanced semiconductor materials by positron annihilation

International Nuclear Information System (INIS)

Uedono, Akira; Suzuki, Ryoichi; Ohdaira, Toshiyuki; Ishibashi, Shoji

2005-01-01

Positron annihilation is an established technique for investigating vacancy-type defects near surfaces or interfaces. Using this technique, one can identify defect species in a nondestructive manner. Because there is no restriction of sample conductivity or temperature, this technique can be applied to a various materials, such as semiconductors, metals, metal oxides, and polymers. The positron annihilation has been applied to the studies of Si-technology related materials, which show that it can provide useful information for the development of semiconductor devices. In this article, we report the results obtained for electroplated Cu, strained Si and high-k materials. (author)

Wafer-level chip-scale packaging analog and power semiconductor applications

CERN Document Server

Qu, Shichun

2015-01-01

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

Thermal oxidation of III-V compounds

International Nuclear Information System (INIS)

Monteiro, O.R.; Evans, J.W.

1988-01-01

The thermal oxidation of two important III-V compound semiconductor materials, namely GaAs and InP, has been studied between 300 and 600 0 C. In-situ TEM, cross-sectional TEM (XTEM) and SIMS analyses were used to characterize the reaction products. The first technique allows us to access the reactions at the very moment they are occurring. XTEM provides a clearer picture of the distribution of phases in the oxidized samples. SIMS gives us information on the dopant redistribution after oxidation as well as enrichment of group V element at the oxide semiconductor interface. Based on those results, the reaction products were characterized and reaction mechanisms proposed

Properties of InGaAs/GaAs metal-oxide-semiconductor heterostructure field-effect transistors modified by surface treatment

Energy Technology Data Exchange (ETDEWEB)

Gregušová, D., E-mail: Dagmar.Gregusova@savba.sk [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Gucmann, F.; Kúdela, R. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Mičušík, M. [Polymer Institute of Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84541 (Slovakia); Stoklas, R.; Válik, L. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Greguš, J. [Faculty of Mathematics, Physics and Informatics, Comenius University, Mlynská dolina, Bratislava SK-84248 (Slovakia); Blaho, M. [Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, Bratislava SK-84104 (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology STU, Ilkovičova 3, Bratislava SK-81219 (Slovakia)

2017-02-15

Highlights: • AlGaAs/InGaAs/GaAs-based metal oxide semiconductor transistors-MOSHFET. • Thin Al-layer deposited in-situ and oxidize in air – gate insulator. • MOSHFET vs HFET transistor properties, density of traps evaluated. - Abstract: GaAs-based heterostructures exhibit excellent carrier transport properties, mainly the high carrier velocity. An AlGaAs-GaAs heterostructure field-effect transistor (HFET) with an InGaAs channel was prepared using metal-organic chemical vapor deposition (MOVPE). An AlOx layer was formed on the AlGaAs barrier layer by the air-assisted oxidation of a thin Al layer deposited in-situ in an MOVPE reactor immediately after AlGaAs/InGaAs growth. The HFETs and MOSHFETs exhibited a very low trap state density in the order of 10{sup 11} cm{sup −2} eV{sup −1}. Capacitance measurement yielded no significant difference between the HFET and MOSHFET structures. The formation of an AlOx layer modified the surface by partially eliminating surface states that arise from Ga-and As-based native oxides. The presence of an AlOx layer reflected in a reduced gate leakage current, which was evidenced by the two-terminal transistor measurement. Presented preparation procedure and device properties show great potential of AlGaAs/InGaAs-based MOSHFETs.

How good is better? A comparison between the Medipix1 and the Medipix2 chip using mammographic phantoms

International Nuclear Information System (INIS)

Pfeiffer, K.F.G.

2003-01-01

Full text: The Mixed-up chip is the successor to the Medipix 1 chip and was also developed within the framework of the Medipix Colaboration. Both chips are pixel detector readout chips working in single photon counting mode and are designed for direct conversion X-ray imaging, for which they are bump-bonded to a pixelated semiconductor sensor layer. Both assemblies used in this comparison have a 300 μm thick sensor layer made of silicon. The main changes realized in the second chip generation are the smaller pixel size of 55 μm x 55 μm, the larger number of pixels (256 x 256) and a second adjustable energy threshold which facilitates energy windowing. For comparing the two detector generations, mammographic phantoms and a suitable X-ray tube have been used. By imaging selected parts of the phantoms with both detectors under the same conditions it is possible to make a direct comparison between the imaging properties of both chips. Main aspects of the experiments were the resolution of high-contrast details and low-contrast imaging. To provide a reference point for image quality the phantoms were also imaged using standard clinical equipment. Since these measurements have been made without an anti-scatter grid, additional simulations have been performed to estimate the influence of scattered photons on the image quality

Nano sulfide and oxide semiconductors as promising materials for studies by positron annihilation

International Nuclear Information System (INIS)

Nambissan, P M G

2013-01-01

A number of wide band gap sulfide and oxide semiconducting nanomaterial systems were investigated using the experimental techniques of positron lifetime and coincidence Doppler broadening measurements. The results indicated several features of the nanomaterial systems, which were found strongly related to the presence of vacancy-type defects and their clusters. Quantum confinement effects were displayed in these studies as remarkable changes in the positron lifetimes and the lineshape parameters around the same grain sizes below which characteristic blue shifts were observed in the optical absorption spectra. Considerable enhancement in the band gap and significant rise of the positron lifetimes were found occurring when the particle sizes were reduced to very low sizes. The results of doping or substitutions by other cations in semiconductor nanosystems were also interesting. Variously heat-treated TiO 2 nanoparticles were studied recently and change of positron annihilation parameters across the anatase to rutile structural transition are carefully analyzed. Preliminary results of positron annihilation studies on Eu-doped CeO nanoparticles are also presented.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

Science.gov (United States)

Leung, T. C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-01-01

Studies of SiO2-Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO2-Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

International Nuclear Information System (INIS)

Leung, T.C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K.G.

1993-01-01

Studies of SiO 2 -Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO 2 -Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown

Nano sulfide and oxide semiconductors as promising materials for studies by positron annihilation

Science.gov (United States)

Nambissan, P. M. G.

2013-06-01

A number of wide band gap sulfide and oxide semiconducting nanomaterial systems were investigated using the experimental techniques of positron lifetime and coincidence Doppler broadening measurements. The results indicated several features of the nanomaterial systems, which were found strongly related to the presence of vacancy-type defects and their clusters. Quantum confinement effects were displayed in these studies as remarkable changes in the positron lifetimes and the lineshape parameters around the same grain sizes below which characteristic blue shifts were observed in the optical absorption spectra. Considerable enhancement in the band gap and significant rise of the positron lifetimes were found occurring when the particle sizes were reduced to very low sizes. The results of doping or substitutions by other cations in semiconductor nanosystems were also interesting. Variously heat-treated TiO2 nanoparticles were studied recently and change of positron annihilation parameters across the anatase to rutile structural transition are carefully analyzed. Preliminary results of positron annihilation studies on Eu-doped CeO nanoparticles are also presented.

Polycrystalline silicon ring resonator photodiodes in a bulk complementary metal-oxide-semiconductor process.

Science.gov (United States)

Mehta, Karan K; Orcutt, Jason S; Shainline, Jeffrey M; Tehar-Zahav, Ofer; Sternberg, Zvi; Meade, Roy; Popović, Miloš A; Ram, Rajeev J

2014-02-15

We present measurements on resonant photodetectors utilizing sub-bandgap absorption in polycrystalline silicon ring resonators, in which light is localized in the intrinsic region of a p+/p/i/n/n+ diode. The devices, operating both at λ=1280 and λ=1550  nm and fabricated in a complementary metal-oxide-semiconductor (CMOS) dynamic random-access memory emulation process, exhibit detection quantum efficiencies around 20% and few-gigahertz response bandwidths. We observe this performance at low reverse biases in the range of a few volts and in devices with dark currents below 50 pA at 10 V. These results demonstrate that such photodetector behavior, previously reported by Preston et al. [Opt. Lett. 36, 52 (2011)], is achievable in bulk CMOS processes, with significant improvements with respect to the previous work in quantum efficiency, dark current, linearity, bandwidth, and operating bias due to additional midlevel doping implants and different material deposition. The present work thus offers a robust realization of a fully CMOS-fabricated all-silicon photodetector functional across a wide wavelength range.

Positron annihilation and Wheeler complexes in semiconductors

International Nuclear Information System (INIS)

Prokob'ev, E.P.

1995-01-01

The Wheeler complexes Ps-Ex (positronium-exciton) were studied. These complexes are formed during irradiation of semiconductors and ionic crystals with positrons at low temperatures under optical excitation by excitons. The binding energy of these and more complex entities preventing dissociation into Ps and Ex and/or Ex ± is at least 0.1 eV, and the lifetime for the two-photon self-annihilation is τ 2γ ∼ 5.02 x 10 -10 x c 3 s (x c is the phenomenological parameter of the effective-mass method). The estimation of lifetimes τ 2γ and τ 2γ t (the total lifetime of Ps-Ex complexes with account for positron annihilation on valence electrons) led to the conclusion that Ps-Ex complexes can be observed in a number of oxide semiconductors, in zinc sulfide, and in alkali halide crystals; however, it was difficult to observe such complexes in silicon, gallium arsenide, and other A 3 B 5 and A 2 B 6 semiconductors

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Recent Advances of Solution-Processed Metal Oxide Thin-Film Transistors.

Science.gov (United States)

Xu, Wangying; Li, Hao; Xu, Jian-Bin; Wang, Lei

2018-03-06

Solution-processed metal oxide thin-film transistors (TFTs) are considered as one of the most promising transistor technologies for future large-area flexible electronics. This review surveys the recent advances in solution-based oxide TFTs, including n-type oxide semiconductors, oxide dielectrics and p-type oxide semiconductors. Firstly, we provide an introduction on oxide TFTs and the TFT configurations and operating principles. Secondly, we present the recent progress in solution-processed n-type transistors, with a special focus on low-temperature and large-area solution processed approaches as well as novel non-display applications. Thirdly, we give a detailed analysis of the state-of-the-art solution-processed oxide dielectrics for low-voltage electronics. Fourthly, we discuss the recent progress in solution-based p-type oxide semiconductors, which will enable the highly desirable future low-cost large-area complementary circuits. Finally, we draw the conclusions and outline the perspectives over the research field.

Yarr: A PCIe based readout system for semiconductor tracking systems

Energy Technology Data Exchange (ETDEWEB)

Heim, Timon [Bergische Universitaet Wuppertal, Wuppertal (Germany); CERN, Geneva (Switzerland); Maettig, Peter [Bergische Universitaet Wuppertal, Wuppertal (Germany); Pernegger, Heinz [CERN, Geneva (Switzerland)

2015-07-01

The Yarr readout system is a novel DAQ concept, using an FPGA board connected via PCIe to a computer, to read out semiconductor tracking systems. The system uses the FPGA as a reconfigurable IO interface which, in conjunction with the very high speed of the PCIe bus, enables a focus of processing the data stream coming from the pixel detector in software. Modern computer system could potentially make the need of custom signal processing hardware in readout systems obsolete and the Yarr readout system showcases this for FE-I4 chips, which are state-of-the-art readout chips used in the ATLAS Pixel Insertable B-Layer and developed for tracking in high multiplicity environments. The underlying concept of the Yarr readout system tries to move intelligence from hardware into the software without the loss of performance, which is made possible by modern multi-core processors. The FPGA board firmware acts like a buffer and does no further processing of the data stream, enabling rapid integration of new hardware due to minimal firmware minimisation.

Nano integrated circuit process

International Nuclear Information System (INIS)

Yoon, Yung Sup

2004-02-01

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

Nano integrated circuit process

Energy Technology Data Exchange (ETDEWEB)

Yoon, Yung Sup

2004-02-15

This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

Reliability Studies of Micro-Relays for Logic Applications

OpenAIRE

Chen, Yenhao

2015-01-01

The semiconductor industry is now struggling with an integrated-circuit “chip” power density crisis due to the non-scalability of the thermal voltage (kBT/q), which sets the minimum subthreshold swing (SS) of a metal-oxide-semiconductor transistor and hence limits reductions in transistor threshold voltage and hence chip operating voltage. In contrast to electronic switches, mechanical switches (“relays”) operate by making/breaking physical contact and therefore offer the ideal characteristi...

Ratiometric, filter-free optical sensor based on a complementary metal oxide semiconductor buried double junction photodiode.

Science.gov (United States)

Yung, Ka Yi; Zhan, Zhiyong; Titus, Albert H; Baker, Gary A; Bright, Frank V

2015-07-16

We report a complementary metal oxide semiconductor integrated circuit (CMOS IC) with a buried double junction (BDJ) photodiode that (i) provides a real-time output signal that is related to the intensity ratio at two emission wavelengths and (ii) simultaneously eliminates the need for an optical filter to block Rayleigh scatter. We demonstrate the BDJ platform performance for gaseous NH3 and aqueous pH detection. We also compare the BDJ performance to parallel results obtained by using a slew scanned fluorimeter (SSF). The BDJ results are functionally equivalent to the SSF results without the need for any wavelength filtering or monochromators and the BDJ platform is not prone to errors associated with source intensity fluctuations or sensor signal drift. Copyright © 2015 Elsevier B.V. All rights reserved.

Charge-flow structures as polymeric early-warning fire alarm devices. M.S. Thesis; [metal oxide semiconductors

Science.gov (United States)

Sechen, C. M.; Senturia, S. D.

1977-01-01

The charge-flow transistor (CFT) and its applications for fire detection and gas sensing were investigated. The utility of various thin film polymers as possible sensing materials was determined. One polymer, PAPA, showed promise as a relative humidity sensor; two others, PFI and PSB, were found to be particularly suitable for fire detection. The behavior of the charge-flow capacitor, which is basically a parallel-plate capacitor with a polymer-filled gap in the metallic tip electrode, was successfully modeled as an RC transmission line. Prototype charge-flow transistors were fabricated and tested. The effective threshold voltage of this metal oxide semiconductor was found to be dependent on whether surface or bulk conduction in the thin film was dominant. Fire tests with a PFI-coated CFT indicate good sensitivity to smouldering fires.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

Energy Technology Data Exchange (ETDEWEB)

Swain, Basudev, E-mail: Swain@iae.re.kr [Institute for Advanced Engineering (IAE), Advanced Materials & Processing Center, Yongin-Si 449-863 (Korea, Republic of); Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo [Institute for Advanced Engineering (IAE), Advanced Materials & Processing Center, Yongin-Si 449-863 (Korea, Republic of); Lee, Kun-Jae [Department of Energy Engineering, Dankook University, Cheonan 330-714 (Korea, Republic of)

2015-07-15

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.

Method to quantify the delocalization of electronic states in amorphous semiconductors and its application to assessing charge carrier mobility of p -type amorphous oxide semiconductors

Science.gov (United States)

de Jamblinne de Meux, A.; Pourtois, G.; Genoe, J.; Heremans, P.

2018-01-01

Amorphous semiconductors are usually characterized by a low charge carrier mobility, essentially related to their lack of long-range order. The development of such material with higher charge carrier mobility is hence challenging. Part of the issue comes from the difficulty encountered by first-principles simulations to evaluate concepts such as the electron effective mass for disordered systems since the absence of periodicity induced by the disorder precludes the use of common concepts derived from condensed matter physics. In this paper, we propose a methodology based on first-principles simulations that partially solves this problem, by quantifying the degree of delocalization of a wave function and of the connectivity between the atomic sites within this electronic state. We validate the robustness of the proposed formalism on crystalline and molecular systems and extend the insights gained to disordered/amorphous InGaZnO4 and Si. We also explore the properties of p -type oxide semiconductor candidates recently reported to have a low effective mass in their crystalline phases [G. Hautier et al., Nat. Commun. 4, 2292 (2013), 10.1038/ncomms3292]. Although in their amorphous phase none of the candidates present a valence band with delocalization properties matching those found in the conduction band of amorphous InGaZnO4, three of the seven analyzed materials show some potential. The most promising candidate, K2Sn2O3 , is expected to possess in its amorphous phase a slightly higher hole mobility than the electron mobility in amorphous silicon.

Total Ionizing Dose Testing of the ABC130 ASIC for the ATLAS Phase-II Semiconductor Tracker Upgrade

CERN Document Server

Morningstar, Alan

2015-01-01

The Large Hadron Collider's (LHC) current inner detector was not built to withstand the radiation damage from the 3000 $\\text{fb}^{-1}$ of integrated luminosity that is planned for the high luminosity LHC (HL-LHC). Therefore, the ATLAS inner detector (ID) must be completely upgraded. As a part of this upgrade, the semiconductor tracker (SCT) and transition radiation tracker (TRT) will be replaced with new silicon microstrip sensors {[}1{]}. These silicon strips will be read out by the ABC130 chip and thus the ABC130 must be able to withstand an expected 30 Mrad of radiation over 10 years. The ABC130 chip was irradiated with 70 Mrad of x-ray radiation over the course of 2 days and the results are discussed in this report.

Study of Si/Si, Si/SiO2, and metal-oxide-semiconductor (MOS) using positrons

International Nuclear Information System (INIS)

Leung, To Chi.

1991-01-01

A variable-energy positron beam is used to study Si/Si, Si/SiO 2 , and metal-oxide-semiconductor (MOS) structures. The capability of depth resolution and the remarkable sensitivity to defects have made the positron annihilation technique a unique tool in detecting open-volume defects in the newly innovated low temperature (300C) molecular-beam-epitaxy (MBE) Si/Si. These two features of the positron beam have further shown its potential role in the study of the Si/SiO 2 . Distinct annihilation characteristics has been observed at the interface and has been studied as a function of the sample growth conditions, annealing (in vacuum), and hydrogen exposure. The MOS structure provides an effective way to study the electrical properties of the Si/SiO 2 interface as a function of applied bias voltage. The annihilation characteristics show a large change as the device condition is changed from accumulation to inversion. The effect of forming gas (FG) anneal is studied using positron annihilation and the result is compared with capacitance-voltage (C-V) measurements. The reduction in the number of interface states is found correlated with the changes in the positron spectra. The present study shows the importance of the positron annihilation technique as a non-contact, non-destructive, and depth-sensitive characterization tool to study the Si-related systems, in particular, the Si/SiO 2 interface which is of crucial importance in semiconductor technology, and fundamental understanding of the defects responsible for degradation of the electrical properties

Lack of enhanced photocatalytic formation of iodine on particulate semiconductor mixtures.

Science.gov (United States)

Karunakaran, C; Anilkumar, P; Vinayagamoorthy, P

2012-12-01

Under UV-A light illumination, formation of iodine from iodide ion on the surfaces of anatase TiO(2), ZnO, Fe(2)O(3), CeO(2), MoO(3), Bi(2)O(3), and Nb(2)O(5) increases with the concentration of iodide ion, airflow rate and light intensity and conform to the Langmuir-Hinshelwood kinetic model. Measurement of the particle size of the semiconductor oxides by light scattering method and deduction of the same from the determined specific surface area show that the oxide particles agglomerate in suspension. However, mixtures of any two listed particulate semiconductors do not show enhanced photocatalytic formation of iodine indicating absence of interparticle charge transfer. The results are rationalized. Copyright © 2012 Elsevier B.V. All rights reserved.

Hybrid artificial photosynthetic systems comprising semiconductors as light harvesters and biomimetic complexes as molecular cocatalysts.

Science.gov (United States)

Wen, Fuyu; Li, Can

2013-11-19

Solar fuel production through artificial photosynthesis may be a key to generating abundant and clean energy, thus addressing the high energy needs of the world's expanding population. As the crucial components of photosynthesis, the artificial photosynthetic system should be composed of a light harvester (e.g., semiconductor or molecular dye), a reduction cocatalyst (e.g., hydrogenase mimic, noble metal), and an oxidation cocatalyst (e.g., photosystem II mimic for oxygen evolution from water oxidation). Solar fuel production catalyzed by an artificial photosynthetic system starts from the absorption of sunlight by the light harvester, where charge separation takes place, followed by a charge transfer to the reduction and oxidation cocatalysts, where redox reaction processes occur. One of the most challenging problems is to develop an artificial photosynthetic solar fuel production system that is both highly efficient and stable. The assembly of cocatalysts on the semiconductor (light harvester) not only can facilitate the charge separation, but also can lower the activation energy or overpotential for the reactions. An efficient light harvester loaded with suitable reduction and oxidation cocatalysts is the key for high efficiency of artificial photosynthetic systems. In this Account, we describe our strategy of hybrid photocatalysts using semiconductors as light harvesters with biomimetic complexes as molecular cocatalysts to construct efficient and stable artificial photosynthetic systems. We chose semiconductor nanoparticles as light harvesters because of their broad spectral absorption and relatively robust properties compared with a natural photosynthesis system. Using biomimetic complexes as cocatalysts can significantly facilitate charge separation via fast charge transfer from the semiconductor to the molecular cocatalysts and also catalyze the chemical reactions of solar fuel production. The hybrid photocatalysts supply us with a platform to study the

Physics and Chemistry on Well-Defined Semiconductor and Oxide Surfaces

Science.gov (United States)

Chen, Peijun

High resolution electron energy loss spectroscopy (HREELS) and other surface spectroscopic techniques have been employed to investigate the following two classes of surface/interface phenomena on well-defined semiconductor and oxide surfaces: (i) the fundamental physical and chemical processes involved in gas-solid interaction on silicon single crystal surfaces, and (ii) the physical and chemical properties of metal-oxide interfaces. The particular systems reported in this dissertation are: NH_3, PH_3 and B_ {10}H_{14} on Si(111)-(7 x 7); NH_3 on Si(100) -(2 x 1); atomic H on Si(111)-(7 x 7) and boron-modified Si(111); Al on Al_2O_3 and Sn on SiO_2.. On silicon surfaces, the surface dangling bonds function as the primary adsorption sites where surface chemical processes take place. The unambiguous identification of surface species by vibrational spectroscopy allows the elementary steps involved in these surface chemical processes to be followed on a molecular level. For adsorbate molecules such as NH_3 and PH_3, the nature of the initial low temperature (100 -300 K) adsorption is found to be dissociative, while that for B_{10}H_ {14} is non-dissociative. This has been deduced based upon the presence (or absence) of specific characteristic vibrational mode(s) on surface. By following the evolution of surface species as a function of temperature, the elementary steps leading to silicon nitride thin film growth and doping of silicon are elucidated. In the case of NH_3 on Si(111)-(7 x 7) and Si(100)-(2 x 1), a detailed understanding on the role of substrate surface structure in controlling the surface reactivity has been gained on the basis of a Si adatom backbond-strain relief mechanism on the Si(111) -(7 x 7). The electronic modification to Si(111) surface by subsurface boron doping has been shown to quench its surface chemistry, even for the most aggressive atomic H. This discovery is potentially meaningful to the technology of gas-phase silicon etching. The

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices.

Science.gov (United States)

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F; Ross, Caroline A

2013-11-08

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO₂ -δ , Co- or Fe-substituted SrTiO 3- δ , as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti 0.2 Ga 0.4 Fe 0.4 )O 3- δ and polycrystalline (CeY₂)Fe₅O 12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY₂)Fe₅O 12 /silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Semiconductor apparatus and method of fabrication for a semiconductor apparatus

NARCIS (Netherlands)

2010-01-01

The invention relates to a semiconductor apparatus (1) and a method of fabrication for a semiconductor apparatus (1), wherein the semiconductor apparatus (1) comprises a semiconductor layer (2) and a passivation layer (3), arranged on a surface of the semiconductor layer (2), for passivating the

Nonresonant Faraday rotation in glassy semiconductors

Science.gov (United States)

van den Keybus, P.; Grevendonk, W.

1986-06-01

Nonresonant interband Faraday rotation in amorphous semiconductors, as a function of photon energy, may be described by an equation derived for direct transitions in crystalline semiconductors. In this paper it is shown how this equation may be obtained for the former case also, assuming a parabolic density of states function N(E) and a correlation between valence- and conduction-band states. The analysis of experiments on chalcogenide glasses reveals a Faraday-rotation energy gap EFRg that is significantly larger than the optical gap Eoptg. The effect is attributed to transitions between extended states, so that it is meaningful to compare EFRg with the mobility gap Eμg. For oxide glasses both gaps are comparable but for chalcogenide glasses EFRg is too large by a few tenths of 1 eV.

Indium tin oxide films prepared by atmospheric plasma annealing and their semiconductor-metal conductivity transition around room temperature

International Nuclear Information System (INIS)

Li Yali; Li Chunyang; He Deyan; Li Junshuai

2009-01-01

We report the synthesis of indium tin oxide (ITO) films using the atmospheric plasma annealing (APA) technique combined with the spin-coating method. The ITO film with a low resistivity of ∼4.6 x 10 -4 Ω cm and a high visible light transmittance, above 85%, was achieved. Hall measurement indicates that compared with the optimized ITO films deposited by magnetron sputtering, the above-mentioned ITO film has a higher carrier concentration of ∼1.21 x 10 21 cm -3 and a lower mobility of ∼11.4 cm 2 V -1 s -1 . More interestingly, these electrical characteristics result in the semiconductor-metal conductivity transition around room temperature for the ITO films prepared by APA.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

Science.gov (United States)

Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

2018-01-01

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

Science.gov (United States)

Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

2018-01-01

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

Complementary metal-oxide semiconductor compatible source of single photons at near-visible wavelengths

Science.gov (United States)

Cernansky, Robert; Martini, Francesco; Politi, Alberto

2018-02-01

We demonstrate on chip generation of correlated pairs of photons in the near-visible spectrum using a CMOS compatible PECVD Silicon Nitride photonic device. Photons are generated via spontaneous four wave mixing enhanced by a ring resonator with high quality Q-factor of 320,000 resulting in a generation rate of 950,000 $\\frac{pairs}{mW}$. The high brightness of this source offers the opportunity to expand photonic quantum technologies over a broad wavelength range and provides a path to develop fully integrated quantum chips working at room temperature.

A 3D Microfluidic Chip for Electrochemical Detection of Hydrolysed Nucleic Bases by a Modified Glassy Carbon Electrode

Directory of Open Access Journals (Sweden)

Jana Vlachova

2015-01-01

Full Text Available Modification of carbon materials, especially graphene-based materials, has wide applications in electrochemical detection such as electrochemical lab-on-chip devices. A glassy carbon electrode (GCE modified with chemically alternated graphene oxide was used as a working electrode (glassy carbon modified by graphene oxide with sulphur containing compounds and Nafion for detection of nucleobases in hydrolysed samples (HCl pH = 2.9, 100 °C, 1 h, neutralization by NaOH. It was found out that modification, especially with trithiocyanuric acid, increased the sensitivity of detection in comparison with pure GCE. All processes were finally implemented in a microfluidic chip formed with a 3D printer by fused deposition modelling technology. As a material for chip fabrication, acrylonitrile butadiene styrene was chosen because of its mechanical and chemical stability. The chip contained the one chamber for the hydrolysis of the nucleic acid and another for the electrochemical detection by the modified GCE. This chamber was fabricated to allow for replacement of the GCE.

A 3D microfluidic chip for electrochemical detection of hydrolysed nucleic bases by a modified glassy carbon electrode.

Science.gov (United States)

Vlachova, Jana; Tmejova, Katerina; Kopel, Pavel; Korabik, Maria; Zitka, Jan; Hynek, David; Kynicky, Jindrich; Adam, Vojtech; Kizek, Rene

2015-01-22

Modification of carbon materials, especially graphene-based materials, has wide applications in electrochemical detection such as electrochemical lab-on-chip devices. A glassy carbon electrode (GCE) modified with chemically alternated graphene oxide was used as a working electrode (glassy carbon modified by graphene oxide with sulphur containing compounds and Nafion) for detection of nucleobases in hydrolysed samples (HCl pH = 2.9, 100 °C, 1 h, neutralization by NaOH). It was found out that modification, especially with trithiocyanuric acid, increased the sensitivity of detection in comparison with pure GCE. All processes were finally implemented in a microfluidic chip formed with a 3D printer by fused deposition modelling technology. As a material for chip fabrication, acrylonitrile butadiene styrene was chosen because of its mechanical and chemical stability. The chip contained the one chamber for the hydrolysis of the nucleic acid and another for the electrochemical detection by the modified GCE. This chamber was fabricated to allow for replacement of the GCE.

Laser line scan underwater imaging by complementary metal-oxide-semiconductor camera

Science.gov (United States)

He, Zhiyi; Luo, Meixing; Song, Xiyu; Wang, Dundong; He, Ning

2017-12-01

This work employs the complementary metal-oxide-semiconductor (CMOS) camera to acquire images in a scanning manner for laser line scan (LLS) underwater imaging to alleviate backscatter impact of seawater. Two operating features of the CMOS camera, namely the region of interest (ROI) and rolling shutter, can be utilized to perform image scan without the difficulty of translating the receiver above the target as the traditional LLS imaging systems have. By the dynamically reconfigurable ROI of an industrial CMOS camera, we evenly divided the image into five subareas along the pixel rows and then scanned them by changing the ROI region automatically under the synchronous illumination by the fun beams of the lasers. Another scanning method was explored by the rolling shutter operation of the CMOS camera. The fun beam lasers were turned on/off to illuminate the narrow zones on the target in a good correspondence to the exposure lines during the rolling procedure of the camera's electronic shutter. The frame synchronization between the image scan and the laser beam sweep may be achieved by either the strobe lighting output pulse or the external triggering pulse of the industrial camera. Comparison between the scanning and nonscanning images shows that contrast of the underwater image can be improved by our LLS imaging techniques, with higher stability and feasibility than the mechanically controlled scanning method.

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

International Nuclear Information System (INIS)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng; Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu

2014-01-01

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Energy Technology Data Exchange (ETDEWEB)

Liu, Siyang; Zhang, Chunwei; Sun, Weifeng, E-mail: swffrog@seu.edu.cn [National ASIC System Engineering Research Center, Southeast University, Nanjing 210096 (China); Su, Wei; Wang, Shaorong; Ma, Shulang; Huang, Yu [CSMC Technologies Corporation, Wuxi 214061 (China)

2014-04-14

Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

KAUST Repository

Ghoneim, Mohamed T.

2015-06-01

We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

Operation of the ATLAS Semiconductor Tracker: commissioning and performance results with cosmic ray data

OpenAIRE

González-Sevilla, S

2009-01-01

The Semiconductor Tracker (SCT) is one of the three sub-systems of the ATLAS internal tracker. Its complete installation and sign-off took about 18 months and was finished at the beginning of 2008. Since then, the SCT has been run successfully taking data in combined mode with the other ATLAS sub-systems. The major problems related with cooling failures and the mortality of off-detector opto-chips have been solved. As in summer 2009, more than 99% of the main detector components are fully wor...

Optically Transparent Thin-Film Electrode Chip for Spectroelectrochemical Sensing

Energy Technology Data Exchange (ETDEWEB)

Branch, Shirmir D.; Lines, Amanda M.; Lynch, John A.; Bello, Job M.; Heineman, William R.; Bryan, Samuel A.

2017-07-03

The electrochemical and spectroelectrochemical applications of an optically transparent thin film electrode chip are investigated. The working electrode is composed of indium tin oxide (ITO); the counter and quasi-reference electrodes are composed of platinum. The stability of the platinum quasi-reference electrode is modified by coating it with a planar, solid state Ag/AgCl layer. The Ag/AgCl reference is characterized with scanning electron microscopy and energy-dispersive X-ray spectroscopy. Open circuit potential measurements indicate that the potential of the planar Ag/AgCl electrode varies a maximum of 20 mV over four days. Cyclic voltammetry measurements show that the electrode chip is comparable to a standard electrochemical cell. Randles-Sevcik analysis of 10 mM K3[Fe(CN)6] in 0.1 M KCl using the electrode chip shows a diffusion coefficient of 1.59 × 10-6 cm2/s, in comparison to the standard electrochemical cell value of 2.38 × 10-6 cm2/s. By using the electrode chip in an optically transparent thin layer electrode (OTTLE), the spectroelectrochemical modulation of [Ru(bpy)3]2+ florescence was demonstrated, achieving a detection limit of 36 nM.

PdO Doping Tunes Band-Gap Energy Levels as Well as Oxidative Stress Responses to a Co3O4p-Type Semiconductor in Cells and the Lung

Science.gov (United States)

2014-01-01

We demonstrate through PdO doping that creation of heterojunctions on Co3O4 nanoparticles can quantitatively adjust band-gap and Fermi energy levels to study the impact of metal oxide nanoparticle semiconductor properties on cellular redox homeostasis and hazard potential. Flame spray pyrolysis (FSP) was used to synthesize a nanoparticle library in which the gradual increase in the PdO content (0–8.9%) allowed electron transfer from Co3O4 to PdO to align Fermi energy levels across the heterojunctions. This alignment was accompanied by free hole accumulation at the Co3O4 interface and production of hydroxyl radicals. Interestingly, there was no concomitant superoxide generation, which could reflect the hole dominance of a p-type semiconductor. Although the electron flux across the heterojunctions induced upward band bending, the Ec levels of the doped particles showed energy overlap with the biological redox potential (BRP). This allows electron capture from the redox couples that maintain the BRP from −4.12 to −4.84 eV, causing disruption of cellular redox homeostasis and induction of oxidative stress. PdO/Co3O4 nanoparticles showed significant increases in cytotoxicity at 25, 50, 100, and 200 μg/mL, which was enhanced incrementally by PdO doping in BEAS-2B and RAW 264.7 cells. Oxidative stress presented as a tiered cellular response involving superoxide generation, glutathione depletion, cytokine production, and cytotoxicity in epithelial and macrophage cell lines. A progressive series of acute pro-inflammatory effects could also be seen in the lungs of animals exposed to incremental PdO-doped particles. All considered, generation of a combinatorial PdO/Co3O4 nanoparticle library with incremental heterojunction density allowed us to demonstrate the integrated role of Ev, Ec, and Ef levels in the generation of oxidant injury and inflammation by the p-type semiconductor, Co3O4. PMID:24673286

Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er2O3 as a gate dielectric

International Nuclear Information System (INIS)

Lin, Ray-Ming; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

2013-01-01

In this study, the rare earth erbium oxide (Er 2 O 3 ) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N t ) of the MOS–HEMT were 125 mV/decade and 4.3 × 10 12 cm −2 , respectively. The dielectric constant of the Er 2 O 3 layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er 2 O 3 MOS–HEMT. - Highlights: ► GaN/AlGaN/Er 2 O 3 metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er 2 O 3 with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I ON /I OFF ratio

Smart point-of-care systems for molecular diagnostics based on nanotechnology: whole blood glucose analysis

Science.gov (United States)

Devadhasan, Jasmine P.; Kim, Sanghyo

2015-07-01

Complementary metal oxide semiconductor (CMOS) image sensors are received great attention for their high efficiency in biological applications. The present work describes a CMOS image sensor-based whole blood glucose monitoring system through a point-of-care (POC) approach. A simple poly-ethylene terephthalate (PET) film chip was developed to carry out the enzyme kinetic reaction at various concentrations of blood glucose. In this technique, assay reagent was adsorbed onto amine functionalized silica (AFSiO2) nanoparticles in order to achieve glucose oxidation on the PET film chip. The AFSiO2 nanoparticles can immobilize the assay reagent with an electrostatic attraction and eased to develop the opaque platform which was technically suitable chip to analyze by the camera module. The oxidized glucose then produces a green color according to the glucose concentration and is analyzed by the camera module as a photon detection technique. The photon number decreases with increasing glucose concentration. The simple sensing approach, utilizing enzyme immobilized AFSiO2 nanoparticle chip and assay detection method was developed for quantitative glucose measurement.

Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

Energy Technology Data Exchange (ETDEWEB)

Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

2017-07-01

We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

Semiconductor Manufacturing equipment introduction

International Nuclear Information System (INIS)

Im, Jong Sun

2001-02-01

This book deals with semiconductor manufacturing equipment. It is comprised of nine chapters, which are manufacturing process of semiconductor device, history of semiconductor manufacturing equipment, kinds and role of semiconductor manufacturing equipment, construction and method of semiconductor manufacturing equipment, introduction of various semiconductor manufacturing equipment, spots of semiconductor manufacturing, technical elements of semiconductor manufacturing equipment, road map of technology of semiconductor manufacturing equipment and semiconductor manufacturing equipment in the 21st century.

Study of non-stoichiometric BaSrTiFeO3 oxide dedicated to semiconductor gas sensors

International Nuclear Information System (INIS)

Fasquelle, D.; Verbrugghe, N.; Deputier, S.

2016-01-01

Developing instrumentation systems compatible with the European RoHS directive (restriction of hazardous substances) to monitor our environment is of great interest for our society. Our research therefore aims at developing innovating integrated systems of detection dedicated to the characterization of various environmental exposures. These systems, which integrate new gas sensors containing lead-free oxides, are dedicated to the detection of flammable and toxic gases. We have firstly chosen to study semiconductor gas sensors implemented with lead-free oxides in view to develop RoHS devices. Therefore thick films deposited by spin-coating and screen-printing have been chosen for their robustness, ease to realize and ease to finally obtain cost-effective sensors. As crystalline defects and ionic vacancies are of great interest for gas detection, we have decided to study a non-stoichiometric composition of the BaSrTiFeO 3 sensible oxide. Nonstoichiometric BaSrTiFeO 3 lead-free oxide thick films were deposited by screen-printing on polycrystalline AFO 3 substrates covered by a layer of Ag-Pd acting as bottom electrode. The physical characterizations have revealed a crystalline structure mainly composed of BaTiO 3 pseudo-cubic phase and Ba 4 Ti 12 O 27 monoclinic phase for the powder, and a porous microstructure for the thick films. When compared to a BSTF thick film with a stoichiometric composition, a notable increase in the BSTF dielectric constant value was observed when taking into account of a similar microstructure and grain size. The loss tangent mean value varies more softly for the non-stoichiometric BaSrTiFeO 3 films than for the perovskite BSTF film as tanδ decreases from 0.45 to 0.04 when the frequency increases from 100 Hz to 1 MHz. (paper)

Comprehensive and fully self-consistent modeling of modern semiconductor lasers

International Nuclear Information System (INIS)

Nakwaski, W.; Sarzał, R. P.

2016-01-01

The fully self-consistent model of modern semiconductor lasers used to design their advanced structures and to understand more deeply their properties is given in the present paper. Operation of semiconductor lasers depends not only on many optical, electrical, thermal, recombination, and sometimes mechanical phenomena taking place within their volumes but also on numerous mutual interactions between these phenomena. Their experimental investigation is quite complex, mostly because of miniature device sizes. Therefore, the most convenient and exact method to analyze expected laser operation and to determine laser optimal structures for various applications is to examine the details of their performance with the aid of a simulation of laser operation in various considered conditions. Such a simulation of an operation of semiconductor lasers is presented in this paper in a full complexity of all mutual interactions between the above individual physical processes. In particular, the hole-burning effect has been discussed. The impacts on laser performance introduced by oxide apertures (their sizes and localization) have been analyzed in detail. Also, some important details concerning the operation of various types of semiconductor lasers are discussed. The results of some applications of semiconductor lasers are shown for successive laser structures. (paper)

In situ ZnO-PVA nanocomposite coated microfluidic chips for biosensing

DEFF Research Database (Denmark)

Habouti, S.; Kunstmann-Olsen, C.; Hoyland, J. D.

2014-01-01

Microfluidic chips with integrated fluid and optical connectors have been generated via a simple PDMS master-mould technique. In situ coating using a Zinc oxide polyvinylalcohol based sol-gel method results in ultrathin nanocomposite layers on the fluid channels, which makes them strongly...

[Application of next-generation semiconductor sequencing technologies in genetic diagnosis of inherited cardiomyopathies].

Science.gov (United States)

Zhao, Yue; Zhang, Hong; Xia, Xue-shan

2015-07-01

Inherited cardiomyopathy is the most common hereditary cardiac disease. It also causes a significant proportion of sudden cardiac deaths in young adults and athletes. So far, approximately one hundred genes have been reported to be involved in cardiomyopathies through different mechanisms. Therefore, the identification of the genetic basis and disease mechanisms of cardiomyopathies are important for establishing a clinical diagnosis and genetic testing. Next-generation semiconductor sequencing (NGSS) technology platform is a high-throughput sequencer capable of analyzing clinically derived genomes with high productivity, sensitivity and specificity. It was launched in 2010 by Life Technologies of USA, and it is based on a high density semiconductor chip, which was covered with tens of thousands of wells. NGSS has been successfully used in candidate gene mutation screening to identify hereditary disease. In this review, we summarize these genetic variations, challenge and application of NGSS in inherited cardiomyopathy, and its value in disease diagnosis, prevention and treatment.

Universal strategy for Ohmic hole injection into organic semiconductors with high ionization energies.

Science.gov (United States)

Kotadiya, Naresh B; Lu, Hao; Mondal, Anirban; Ie, Yutaka; Andrienko, Denis; Blom, Paul W M; Wetzelaer, Gert-Jan A H

2018-04-01

Barrier-free (Ohmic) contacts are a key requirement for efficient organic optoelectronic devices, such as organic light-emitting diodes, solar cells, and field-effect transistors. Here, we propose a simple and robust way of forming an Ohmic hole contact on organic semiconductors with a high ionization energy (IE). The injected hole current from high-work-function metal-oxide electrodes is improved by more than an order of magnitude by using an interlayer for which the sole requirement is that it has a higher IE than the organic semiconductor. Insertion of the interlayer results in electrostatic decoupling of the electrode from the semiconductor and realignment of the Fermi level with the IE of the organic semiconductor. The Ohmic-contact formation is illustrated for a number of material combinations and solves the problem of hole injection into organic semiconductors with a high IE of up to 6 eV.

Finite Element Analysis of Film Stack Architecture for Complementary Metal-Oxide-Semiconductor Image Sensors.

Science.gov (United States)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-05-02

Image sensors are the core components of computer, communication, and consumer electronic products. Complementary metal oxide semiconductor (CMOS) image sensors have become the mainstay of image-sensing developments, but are prone to leakage current. In this study, we simulate the CMOS image sensor (CIS) film stacking process by finite element analysis. To elucidate the relationship between the leakage current and stack architecture, we compare the simulated and measured leakage currents in the elements. Based on the analysis results, we further improve the performance by optimizing the architecture of the film stacks or changing the thin-film material. The material parameters are then corrected to improve the accuracy of the simulation results. The simulated and experimental results confirm a positive correlation between measured leakage current and stress. This trend is attributed to the structural defects induced by high stress, which generate leakage. Using this relationship, we can change the structure of the thin-film stack to reduce the leakage current and thereby improve the component life and reliability of the CIS components.

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

Directory of Open Access Journals (Sweden)

Mehmet Cengiz Onbasli

2013-11-01

Full Text Available Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4O3−δ and polycrystalline (CeY2Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

Si micro photonics for optical interconnection

International Nuclear Information System (INIS)

Wada, K.; Ahn, D.H.; Lim, D.R.; Michel, J.; Kimerling, L.C.

2006-01-01

This paper reviews current status of silicon microphotonics and the recent prototype of on-chip optical interconnection. Si microphotonics pursues complementary metal oxide semiconductor (CMOS)-compatibility of photonic devices to reduce the materials diversity eventually to integrate on Si chips. Fractal optical H-trees have been implemented on a chip and found to be a technology breakthrough beyond metal interconnection. It has shown that large RC time constants associated with metal can be eliminated at least long distant data communication on a chip, and eventually improve yield and power issues. This has become the world's first electronic and photonic integrated circuits (EPICs) and the possibility of at least 10 GHz clocking for personal computers has been demonstrated

Metabolomics on integrated circuit

OpenAIRE

Cheah, Boon Chong; MacDonald, Alasdair I.; Barrett, Michael P.; Cumming, David R.S.

2017-01-01

We have demonstrated a chip-based diagnostics tool for the quantification of metabolites, using specific enzymes, to study enzyme kinetics and calculate the Michaelis-Menten constant. An array of 256×256 ion-sensitive field effect transistors (ISFETs) fabricated in a complementary metal oxide semiconductor (CMOS) process is used for this prototype. We have used hexokinase enzyme reaction on the ISFET CMOS chip with glucose concentration in the physiological range of 0.05 mM – 231 mM and succe...

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity.

Science.gov (United States)

Kafi, Md Abdul; Cho, Hyeon-Yeol; Choi, Jeong Woo

2015-07-02

Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD) or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C), C(RGD)₄ ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot) or three dimensional (rod or pillar) like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD), graphene oxide (GO) and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity

Directory of Open Access Journals (Sweden)

Md. Abdul Kafi

2015-07-01

Full Text Available Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C, C(RGD4 ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot or three dimensional (rod or pillar like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD, graphene oxide (GO and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

Science.gov (United States)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Searching Room Temperature Ferromagnetism in Wide Gap Semiconductors Fe-doped Strontium Titanate and Zinc Oxide

CERN Document Server

Pereira, LMC; Wahl, U

Scientific findings in the very beginning of the millennium are taking us a step further in the new paradigm of technology: spintronics. Upgrading charge-based electronics with the additional degree of freedom of the carriers spin-state, spintronics opens a path to the birth of a new generation of devices with the potential advantages of non-volatility and higher processing speed, integration densities and power efficiency. A decisive step towards this new age lies on the attribution of magnetic properties to semiconductors, the building block of today's electronics, that is, the realization of ferromagnetic semiconductors (FS) with critical temperatures above room temperature. Unfruitful search for intrinsic RT FS lead to the concept of Dilute(d) Magnetic Semiconductors (DMS): ordinary semiconductor materials where 3 d transition metals randomly substitute a few percent of the matrix cations and, by some long-range mechanism, order ferromagnetically. The times are of intense research activity and the last fe...

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

International Nuclear Information System (INIS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-01-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

Thin film transistor performance of amorphous indium–zinc oxide semiconductor thin film prepared by ultraviolet photoassisted sol–gel processing

Science.gov (United States)

Kodzasa, Takehito; Nobeshima, Taiki; Kuribara, Kazunori; Yoshida, Manabu

2018-05-01

We have fabricated an amorphous indium–zinc oxide (IZO, In/Zn = 3/1) semiconductor thin-film transistor (AOS-TFT) by the sol–gel technique using ultraviolet (UV) photoirradiation and post-treatment in high-pressure O2 at 200 °C. The obtained TFT showed a hole carrier mobility of 0.02 cm2 V‑1 s‑1 and an on/off current ratio of 106. UV photoirradiation leads to the decomposition of the organic agents and hydroxide group in the IZO gel film. Furthermore, the post-treatment annealing at a high O2 pressure of more than 0.6 MPa leads to the filling of the oxygen vacancies in a poor metal–oxygen network in the IZO film.

A Robust and Low-Complexity Gas Recognition Technique for On-Chip Tin-Oxide Gas Sensor Array

Directory of Open Access Journals (Sweden)

Farid Flitti

2008-01-01

Full Text Available Gas recognition is a new emerging research area with many civil, military, and industrial applications. The success of any gas recognition system depends on its computational complexity and its robustness. In this work, we propose a new low-complexity recognition method which is tested and successfully validated for tin-oxide gas sensor array chip. The recognition system is based on a vector angle similarity measure between the query gas and the representatives of the different gas classes. The latter are obtained using a clustering algorithm based on the same measure within the training data set. Experimented results on our in-house gas sensors array show more than 98% of correct recognition. The robustness of the proposed method is tested by recognizing gas measurements with simulated drift. Less than 1% of performance degradation is noted at the worst case scenario which represents a significant improvement when compared to the current state-of-the-art.

Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

Science.gov (United States)

Nakazato, Kazuo

2014-03-28

By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

Structural, optical and electrical properties of tin oxide thin films for application as a wide band gap semiconductor

Energy Technology Data Exchange (ETDEWEB)

Sethi, Riti; Ahmad, Shabir; Aziz, Anver; Siddiqui, Azher Majid, E-mail: amsiddiqui@jmi.ac.in [Department of Physics, Jamia Millia Islamia, New Delhi-110025 (India)

2015-08-28

Tin oxide (SnO) thin films were synthesized using thermal evaporation technique. Ultra pure metallic tin was deposited on glass substrates using thermal evaporator under high vacuum. The thickness of the tin deposited films was kept at 100nm. Subsequently, the as-deposited tin films were annealed under oxygen environment for a period of 3hrs to obtain tin oxide films. To analyse the suitability of the synthesized tin oxide films as a wide band gap semiconductor, various properties were studied. Structural parameters were studied using XRD and SEM-EDX. The optical properties were studied using UV-Vis Spectrophotometry and the electrical parameters were calculated using the Hall-setup. XRD and SEM confirmed the formation of SnO phase. Uniform texture of the film can be seen through the SEM images. Presence of traces of unoxidised Sn has also been confirmed through the XRD spectra. The band gap calculated was around 3.6eV and the optical transparency around 50%. The higher value of band gap and lower value of optical transparency can be attributed to the presence of unoxidised Sn. The values of resistivity and mobility as measured by the Hall setup were 78Ωcm and 2.92cm{sup 2}/Vs respectively. The reasonable optical and electrical parameters make SnO a suitable candidate for optoelectronic and electronic device applications.

Hydrogen interactions with silicon-on-insulator materials

OpenAIRE

Rivera de Mena, A.J.

2003-01-01

The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

Loss in tocopherols and oxidative stability during the frying of frozen cassava chips

Directory of Open Access Journals (Sweden)

Corsini, Mara S.

2009-03-01

Full Text Available The present study was aimed at verifying tocopherols losses and oxidative stability changes in vegetable oils used in discontinuous frying. The frying of frozen cassava chips was carried out in a household electric frying pan, where the oil was heated to a temperature of 180°C for 25 hours, with fresh oil replacement. The results obtained from the analytical determinations were submitted to variance analysis, in a factorial scheme, using a completely randomized design, making it possible to determine the influence of the type of oil and frying times on changes in the oil. The data show that the smallest changes occur in palm oil, which is more saturated. For sunflower and cottonseed oils, which are more unsaturated, there was a clear decrease in both tocopherol concentration and oxidative stability.El objetivo de este trabajo fue analizar los cambios en la concentración de tocoferoles y la evolución de la alteración oxidativa en aceites vegetales utilizados en fritura discontinua. La fritura de palitos de mandioca congelados fue realizada en una freidora eléctrica doméstica, en la cual el aceite fue calentando a 180°C, durante 25 horas, con reposición de aceite fresco. Los resultados obtenidos de las determinaciones analíticas fueron sometidos a análisis de variancia, en esquema factorial para determinar la influencia de los factores aceite y tiempo de fritura sobre las alteraciones en los aceites. Los resultados muestran que las menores alteraciones ocurren para el aceite de palma, más saturado. Para los aceites de algodón y girasol, más insaturados, se verificó que, conforme disminuyó la concentración de tocoferoles, disminuye la estabilidad oxidativa.

Highly stable copper oxide composite as an effective photocathode for water splitting via a facile electrochemical synthesis strategy

KAUST Repository

Zhang, Zhonghai; Wang, Peng

2012-01-01

focused on n-type metal oxide semiconductors as photoanodes, whereas studies of p-type metal oxide semiconductors as photocathodes where hydrogen is generated are scarce. In this paper, highly efficient and stable copper oxide composite photocathode

Bipolar resistive switching in metal-insulator-semiconductor nanostructures based on silicon nitride and silicon oxide

Science.gov (United States)

Koryazhkina, M. N.; Tikhov, S. V.; Mikhaylov, A. N.; Belov, A. I.; Korolev, D. S.; Antonov, I. N.; Karzanov, V. V.; Gorshkov, O. N.; Tetelbaum, D. I.; Karakolis, P.; Dimitrakis, P.

2018-03-01

Bipolar resistive switching in metal-insulator-semiconductor (MIS) capacitor-like structures with an inert Au top electrode and a Si3N4 insulator nanolayer (6 nm thick) has been observed. The effect of a highly doped n +-Si substrate and a SiO2 interlayer (2 nm) is revealed in the changes in the semiconductor space charge region and small-signal parameters of parallel and serial equivalent circuit models measured in the high- and low-resistive capacitor states, as well as under laser illumination. The increase in conductivity of the semiconductor capacitor plate significantly reduces the charging and discharging times of capacitor-like structures.

Toward designing semiconductor-semiconductor heterojunctions for photocatalytic applications

Science.gov (United States)

Zhang, Liping; Jaroniec, Mietek

2018-02-01

Semiconductor photocatalysts show a great potential for environmental and energy-related applications, however one of the major disadvantages is their relatively low photocatalytic performance due to the recombination of electron-hole pairs. Therefore, intensive research is being conducted toward design of heterojunctions, which have been shown to be effective for improving the charge-transfer properties and efficiency of photocatalysts. According to the type of band alignment and direction of internal electric field, heterojunctions are categorized into five different types, each of which is associated with its own charge transfer characteristics. Since the design of heterojunctions requires the knowledge of band edge positions of component semiconductors, the commonly used techniques for the assessment of band edge positions are reviewed. Among them the electronegativity-based calculation method is applied for a large number of popular visible-light-active semiconductors, including some widely investigated bismuth-containing semiconductors. On basis of the calculated band edge positions and the type of component semiconductors reported, heterojunctions composed of the selected bismuth-containing semiconductors are proposed. Finally, the most popular synthetic techniques for the fabrication of heterojunctions are briefly discussed.

Chips 2020

CERN Document Server

2016-01-01

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

Comparison of modification strategies towards enhanced charge carrier separation and photocatalytic degradation activity of metal oxide semiconductors (TiO{sub 2}, WO{sub 3} and ZnO)

Energy Technology Data Exchange (ETDEWEB)

Kumar, S. Girish [Department of Physics, Indian Institute of Science, Bengaluru, 560012 Karnataka (India); Department of Chemistry, School of Engineering and Technology, CMR University, Bengaluru, 562149, Karnataka (India); Rao, K.S.R. Koteswara, E-mail: raoksrk@gmail.com [Department of Physics, Indian Institute of Science, Bengaluru, 560012 Karnataka (India)

2017-01-01

Graphical abstract: Semiconductor metal oxides: Modifications, charge carrier dynamics and photocatalysis. - Highlights: • TiO{sub 2}, WO{sub 3} and ZnO based photocatalysis is reviewed. • Advances to improve the efficiency are emphasized. • Differences and similarities in the modifications are highlighted. • Charge carrier dynamics for each strategy are discussed. - Abstract: Metal oxide semiconductors (TiO{sub 2}, WO{sub 3} and ZnO) finds unparalleled opportunity in wastewater purification under UV/visible light, largely encouraged by their divergent admirable features like stability, non-toxicity, ease of preparation, suitable band edge positions and facile generation of active oxygen species in the aqueous medium. However, the perennial failings of these photocatalysts emanates from the stumbling blocks like rapid charge carrier recombination and meager visible light response. In this review, tailoring the surface-bulk electronic structure through the calibrated and veritable approaches such as impurity doping, deposition with noble metals, sensitizing with other compounds (dyes, polymers, inorganic complexes and simple chelating ligands), hydrogenation process (annealing under hydrogen atmosphere), electronic integration with other semiconductors, modifying with carbon nanostructures, designing with exposed facets and tailoring with hierarchical morphologies to overcome their critical drawbacks are summarized. Taking into account the materials intrinsic properties, the pros and cons together with similarities and striking differences for each strategy in specific to TiO{sub 2}, WO{sub 3} & ZnO are highlighted. These subtlety enunciates the primacy for improving the structure-electronic properties of metal oxides and credence to its fore in the practical applications. Future research must focus on comparing the performances of ZnO, TiO{sub 2} and WO{sub 3} in parallel to get insight into their photocatalytic behaviors. Such comparisons not only reveal

Vapor-Liquid-Solid Etch of Semiconductor Surface Channels by Running Gold Nanodroplets.

Science.gov (United States)

Nikoobakht, Babak; Herzing, Andrew; Muramoto, Shin; Tersoff, Jerry

2015-12-09

We show that Au nanoparticles spontaneously move across the (001) surface of InP, InAs, and GaP when heated in the presence of water vapor. As they move, the particles etch crystallographically aligned grooves into the surface. We show that this process is a negative analogue of the vapor-liquid-solid (VLS) growth of semiconductor nanowires: the semiconductor dissolves into the catalyst and reacts with water vapor at the catalyst surface to create volatile oxides, depleting the dissolved cations and anions and thus sustaining the dissolution process. This VLS etching process provides a new tool for directed assembly of structures with sublithographic dimensions, as small as a few nanometers in diameter. Au particles above 100 nm in size do not exhibit this process but remain stationary, with oxide accumulating around the particles.

Wafer-scale laser pantography: Fabrication of n-metal-oxide-semiconductor transistors and small-scale integrated circuits by direct-write laser-induced pyrolytic reactions

International Nuclear Information System (INIS)

McWilliams, B.M.; Herman, I.P.; Mitlitsky, F.; Hyde, R.A.; Wood, L.L.

1983-01-01

A complete set of processes sufficient for manufacture of n-metal-oxide-semiconductor (n-MOS) transistors by a laser-induced direct-write process has been demonstrated separately, and integrated to yield functional transistors. Gates and interconnects were fabricated of various combinations of n-doped and intrinsic polysilicon, tungsten, and tungsten silicide compounds. Both 0.1-μm and 1-μm-thick gate oxides were micromachined with and without etchant gas, and the exposed p-Si [100] substrate was cleaned and, at times, etched. Diffusion regions were doped by laser-induced pyrolytic decomposition of phosphine followed by laser annealing. Along with the successful manufacture of working n-MOS transistors and a set of elementary digital logic gates, this letter reports the successful use of several laser-induced surface reactions that have not been reported previously

Semiconductor/dielectric interface engineering and characterization

Science.gov (United States)

Lucero, Antonio T.

The focus of this dissertation is the application and characterization of several, novel interface passivation techniques for III-V semiconductors, and the development of an in-situ electrical characterization. Two different interface passivation techniques were evaluated. The first is interface nitridation using a nitrogen radical plasma source. The nitrogen radical plasma generator is a unique system which is capable of producing a large flux of N-radicals free of energetic ions. This was applied to Si and the surface was studied using x-ray photoelectron spectroscopy (XPS). Ultra-thin nitride layers could be formed from 200-400° C. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using this passivation technique. Interface nitridation was able to reduce leakage current and improve the equivalent oxide thickness of the devices. The second passivation technique studied is the atomic layer deposition (ALD) diethylzinc (DEZ)/water treatment of sulfur treated InGaAs and GaSb. On InGaAs this passivation technique is able to chemically reduce higher oxidation states on the surface, and the process results in the deposition of a ZnS/ZnO interface passivation layer, as determined by XPS. Capacitance-voltage (C-V) measurements of MOSCAPs made on p-InGaAs reveal a large reduction in accumulation dispersion and a reduction in the density of interfacial traps. The same technique was applied to GaSb and the process was studied in an in-situ half-cycle XPS experiment. DEZ/H2O is able to remove all Sb-S from the surface, forming a stable ZnS passivation layer. This passivation layer is resistant to further reoxidation during dielectric deposition. The final part of this dissertation is the design and construction of an ultra-high vacuum cluster tool for in-situ electrical characterization. The system consists of three deposition chambers coupled to an electrical probe station. With this setup, devices can be processed and subsequently electrically characterized

Design and exploration of semiconductors from first principles: A review of recent advances

Science.gov (United States)

Oba, Fumiyasu; Kumagai, Yu

2018-06-01

Recent first-principles approaches to semiconductors are reviewed, with an emphasis on theoretical insight into emerging materials and in silico exploration of as-yet-unreported materials. As relevant theory and methodologies have developed, along with computer performance, it is now feasible to predict a variety of material properties ab initio at the practical level of accuracy required for detailed understanding and elaborate design of semiconductors; these material properties include (i) fundamental bulk properties such as band gaps, effective masses, dielectric constants, and optical absorption coefficients; (ii) the properties of point defects, including native defects, residual impurities, and dopants, such as donor, acceptor, and deep-trap levels, and formation energies, which determine the carrier type and density; and (iii) absolute and relative band positions, including ionization potentials and electron affinities at semiconductor surfaces, band offsets at heterointerfaces between dissimilar semiconductors, and Schottky barrier heights at metal–semiconductor interfaces, which are often discussed systematically using band alignment or lineup diagrams. These predictions from first principles have made it possible to elucidate the characteristics of semiconductors used in industry, including group III–V compounds such as GaN, GaP, and GaAs and their alloys with related Al and In compounds; amorphous oxides, represented by In–Ga–Zn–O transparent conductive oxides (TCOs), represented by In2O3, SnO2, and ZnO; and photovoltaic absorber and buffer layer materials such as CdTe and CdS among group II–VI compounds and chalcopyrite CuInSe2, CuGaSe2, and CuIn1‑ x Ga x Se2 (CIGS) alloys, in addition to the prototypical elemental semiconductors Si and Ge. Semiconductors attracting renewed or emerging interest have also been investigated, for instance, divalent tin compounds, including SnO and SnS; wurtzite-derived ternary compounds such as ZnSnN2 and Cu

Physicochemical and Electrophysical Properties of Metal/Semiconductor Containing Nanostructured Composites

Science.gov (United States)

Gerasimov, G. N.; Gromov, V. F.; Trakhtenberg, L. I.

2018-06-01

The properties of nanostructured composites based on metal oxides and metal-polymer materials are analyzed, along with ways of preparing them. The effect the interaction between metal and semiconductor nanoparticles has on the conductivity, photoconductivity, catalytic activity, and magnetic, dielectric, and sensor properties of nanocomposites is discussed. It is shown that as a result of this interaction, a material can acquire properties that do not exist in systems of isolated particles. The transfer of electrons between metal particles of different sizes in polymeric matrices leads to specific dielectric losses, and to an increase in the rate and a change in the direction of chemical reactions catalyzed by these particles. The interaction between metal-oxide semiconductor particles results in the electronic and chemical sensitization of sensor effects in nanostructured composite materials. Studies on creating molecular machines (Brownian motors), devices for magnetic recording of information, and high-temperature superconductors based on nanostructured systems are reviewed.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

Science.gov (United States)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-12-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Neutron and gamma irradiation effects on power semiconductor switches

Science.gov (United States)

Schwarze, G. E.; Frasca, A. J.

1990-01-01

The performance characteristics of high power semiconductor switches subjected to high levels of neutron fluence and gamma dose must be known by the designer of the power conditioning, control and transmission subsystem of space nuclear power systems. Location and the allowable shielding mass budget will determine the level of radiation tolerance required by the switches to meet performance and reliability requirements. Neutron and gamma ray interactions with semiconductor materials and how these interactions affect the electrical and switching characteristics of solid state power switches is discussed. The experimental measurement system and radiation facilities are described. Experimental data showing the effects of neutron and gamma irradiation on the performance characteristics are given for power-type NPN Bipolar Junction Transistors (BJTs), and Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs). BJTs show a rapid decrease in gain, blocking voltage, and storage time for neutron irradiation, and MOSFETs show a rapid decrease in the gate threshold voltage for gamma irradiation.

Investigation of structural and electrical properties on substrate material for high frequency metal-oxide-semiconductor (MOS) devices

Science.gov (United States)

Kumar, M.; Yang, Sung-Hyun; Janardhan Reddy, K.; JagadeeshChandra, S. V.

2017-04-01

Hafnium oxide (HfO2) thin films were grown on cleaned P-type Ge and Si substrates by using atomic layer deposition technique (ALD) with thickness of 8 nm. The composition analysis of as-deposited and annealed HfO2 films was characterized by XPS, further electrical measurements; we fabricated the metal-oxide-semiconductor (MOS) devices with Pt electrode. Post deposition annealing in O2 ambient at 500 °C for 30 min was carried out on both Ge and Si devices. Capacitance-voltage (C-V) and conductance-voltage (G-V) curves measured at 1 MHz. The Ge MOS devices showed improved interfacial and electrical properties, high dielectric constant (~19), smaller EOT value (0.7 nm), and smaller D it value as Si MOS devices. The C-V curves shown significantly high accumulation capacitance values from Ge devices, relatively when compare with the Si MOS devices before and after annealing. It could be due to the presence of very thin interfacial layer at HfO2/Ge stacks than HfO2/Si stacks conformed by the HRTEM images. Besides, from current-voltage (I-V) curves of the Ge devices exhibited similar leakage current as Si devices. Therefore, Ge might be a reliable substrate material for structural, electrical and high frequency applications.

A Wide-Range Tunable Level-Keeper Using Vertical Metal-Oxide-Semiconductor Field-Effect Transistors for Current-Reuse Systems

Science.gov (United States)

Tanoi, Satoru; Endoh, Tetsuo

2012-04-01

A wide-range tunable level-keeper using vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed for current-reuse analog systems. The design keys for widening tunable range of the operation are a two-path feed-back and a vertical MOSFET with back-bias-effect free. The proposed circuit with the vertical MOSFETs shows the 1.23-V tunable-range of the input level with the 2.4-V internal-supply voltage (VDD) in the simulation. This tunable-range of the proposed circuit is 4.7 times wider than that of the conventional. The achieved current efficiency of the proposed level-keeper is 66% at the 1.2-V output with the 2.4-V VDD. This efficiency of the proposed circuit is twice higher than that of the traditional voltage down converter.

Price of forest chips decreasing

International Nuclear Information System (INIS)

Hakkila, P.

2001-01-01

Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

Conductive Polymer Microelectrodes for on-chip measurement of transmitter release from living cells

DEFF Research Database (Denmark)

Larsen, Simon Tylsgaard; Matteucci, Marco; Taboryski, Rafael J.

2012-01-01

driven cell trapping inside closed chip devices. Conductive polymer microelectrodes were used to measure transmitter release using electrochemical methods such as cyclic voltammetry and constant potential amperometry. By measuring the oxidation current at a cyclic voltammogram, the concentration...

Fabrication of solid-state secondary battery using semiconductors and evaluation of its charge/discharge characteristics

Science.gov (United States)

Sasaki, Atsuya; Sasaki, Akito; Hirabayashi, Hideaki; Saito, Shuichi; Aoki, Katsuaki; Kataoka, Yoshinori; Suzuki, Koji; Yabuhara, Hidehiko; Ito, Takahiro; Takagi, Shigeyuki

2018-04-01

Li-ion batteries have attracted interest for use as storage batteries. However, the risk of fire has not yet been resolved. Although solid Li-ion batteries are possible alternatives, their performance characteristics are unsatisfactory. Recently, research on utilizing the accumulation of carriers at the trap levels of semiconductors has been performed. However, the detailed charge/discharge characteristics and principles have not been reported. In this report, we attempted to form new n-type oxide semiconductor/insulator/p-type oxide semiconductor structures. The battery characteristics of these structures were evaluated by charge/discharge measurements. The obtained results clearly indicated the characteristics of rechargeable batteries. Furthermore, the fabricated structure accumulated an approximately 5000 times larger number of carriers than a parallel plate capacitor. Additionally, by constructing circuit models based on the experimental results, the charge/discharge mechanisms were considered. This is the first detailed experimental report on a rechargeable battery that operates without the double injection of ions and electrons.

Mercuric iodide semiconductor detectors encapsulated in polymeric resin

Energy Technology Data Exchange (ETDEWEB)

Martins, Joao F. Trencher; Santos, Robinson A. dos; Ferraz, Caue de M.; Oliveira, Adriano S.; Velo, Alexandre F.; Mesquita, Carlos H. de; Hamada, Margarida M., E-mail: mmhamada@ipen.br [Instituto de Pesquisas Energeticas e Nucleares (IPEN/CNEN-SP), Sao Paulo, SP (Brazil); Disch, Christian; Fiederle, Michael [Albert-Ludwigs Universität Freiburg - UniFreibrug, Freiburg Materials Research Center - FMF, Freiburg (Germany)

2015-07-01

The development of new semiconductor radiation detectors always finds many setback factors, such as: high concentration of impurities in the start materials, poor long term stability, the surface oxidation and other difficulties discussed extensively in the literature, that limit their use. In this work was studied, the application of a coating resin on HgI2 detectors, in order to protect the semiconductor crystal reactions from atmospheric gases and to isolate electrically the surface of the crystals. Four polymeric resins were analyzed: Resin 1: 50% - 100%Heptane, 10% - 25% methylcyclohexane, <1% cyclohexane; Resin 2: 25% - 50% ethanol, 25% - 50% acetone, <2,5% ethylacetate; Resin 3: 50% - 100% methylacetate, 5% - 10% n-butylacetate; Resin 4: 50% - 100% ethyl-2-cyanacrylat. The influence of the polymeric resin type used on the spectroscopic performance of the HgI{sub 2} semiconductor detector is, clearly, demonstrated. The better result was found for the detector encapsulated with Resin 3. An increase of up to 26 times at the stability time was observed for the detectors encapsulated compared to that non-encapsulated detector. (author)

Strained silicon/silicon germanium heterojunction n-channel metal oxide semiconductor field effect transistors

International Nuclear Information System (INIS)

Olsen, Sarah H.

2002-01-01

Investigations into the performance of strained silicon/silicon-germanium (Si/SiGe) n-channel metal-oxide-semiconductor field effect transistors (MOSFETs) have been carried out. Theoretical predictions suggest that use of a strained Si/SiGe material system with advanced material properties compared with conventional silicon allows enhanced MOSFET device performance. This study has therefore investigated the practical feasibility of obtaining superior electrical performance using a Si/SiGe material system. The MOSFET devices consisted of a strained Si surface channel and were fabricated on relaxed SiGe material using a reduced thermal budget process in order to preserve the strain. Two batches of strained Si/SiGe devices fabricated on material grown by differing methods have been analysed and both showed good transistor action. A correlation of electrical and physical device data established that the electrical device behaviour was closely related to the SiGe material quality, which differed depending on growth technique. The cross-wafer variation in the electrical performance of the strained Si/SiGe devices was found to be a function of material quality, thus the viability of Si/SiGe MOSFET technology for commercial applications has been addressed. Of particular importance was the finding that large-scale 'cross-hatching' roughness associated with relaxed SiGe alloys led to degradation in the small-scale roughness at the gate oxide interface, which affects electrical device performance. The fabrication of strained Si MOSFET devices on high quality SiGe material thus enabled significant performance gains to be realised compared with conventional Si control devices. In contrast, the performance of devices fabricated on material with severe cross-hatching roughness was found to be diminished by the nanoscale oxide interface roughness. The effect of device processing on SiGe material with differing as-grown roughness has been carried out and compared with the reactions

Superconducting Switch for Fast On-Chip Routing of Quantum Microwave Fields

Science.gov (United States)

Pechal, M.; Besse, J.-C.; Mondal, M.; Oppliger, M.; Gasparinetti, S.; Wallraff, A.

2016-08-01

A switch capable of routing microwave signals at cryogenic temperatures is a desirable component for state-of-the-art experiments in many fields of applied physics, including but not limited to quantum-information processing, communication, and basic research in engineered quantum systems. Conventional mechanical switches provide low insertion loss but disturb operation of dilution cryostats and the associated experiments by heat dissipation. Switches based on semiconductors or microelectromechanical systems have a lower thermal budget but are not readily integrated with current superconducting circuits. Here we design and test an on-chip switch built by combining tunable transmission-line resonators with microwave beam splitters. The device is superconducting and as such dissipates a negligible amount of heat. It is compatible with current superconducting circuit fabrication techniques, operates with a bandwidth exceeding 100 MHz, is capable of handling photon fluxes on the order of 1 05 μ s-1 , equivalent to powers exceeding -90 dBm , and can be switched within approximately 6-8 ns. We successfully demonstrate operation of the device in the quantum regime by integrating it on a chip with a single-photon source and using it to route nonclassical itinerant microwave fields at the single-photon level.

Nitrogen doped nanocrystalline semiconductor metal oxide: An efficient UV active photocatalyst for the oxidation of an organic dye using slurry Photoreactor.

Science.gov (United States)

Ramachandran, Saranya; Sivasamy, A; Kumar, B Dinesh

2016-12-01

Water pollution is a cause for serious concern in today's world. A major contributor to water pollution is industrial effluents containing dyes and other organic molecules. Waste water treatment has become a priority area in today's applied scientific research as it seeks to minimize the toxicity of the effluents being discharged and increase the possibility of water recycling. An efficient and eco-friendly way of degrading toxic molecules is to use nano metal-oxide photocatalysts. The present study aims at enhancing the photocatalytic activity of a semiconductor metal oxide by doping it with nitrogen. A sol-gel cum combustion method was employed to synthesize the catalyst. The prepared catalyst was characterized by FT-IR, XRD, UV-DRS, FESEM and AFM techniques. UV-DRS result showed the catalyst to possess band gap energy of 2.97eV, thus making it active in the UV region of the spectrum. Its photocatalytic activity was evaluated by the degradation of a model pollutant-Orange G dye, under UV light irradiation. Preliminary experiments were carried out to study the effects of pH, catalyst dosage and initial dye concentration on the extent of dye degradation. Kinetic studies revealed that the reaction followed pseudo first order kinetics. The effect of electrolytes on catalyst efficiency was also studied. The progress of the reaction was monitored by absorption studies and measuring the reduction in COD. The catalyst thus prepared was seen to have a high photocatalytic efficiency. The use of this catalyst is a promising means of waste water treatment. Copyright © 2016 Elsevier Inc. All rights reserved.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

Science.gov (United States)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Semiconductor physics

CERN Document Server

Böer, Karl W

2018-01-01

This handbook gives a complete survey of the important topics and results in semiconductor physics. It addresses every fundamental principle and most research topics and areas of application in the field of semiconductor physics. Comprehensive information is provided on crystalline bulk and low-dimensional as well as amporphous semiconductors, including optical, transport, and dynamic properties.

Exploring SiSn as a performance enhancing semiconductor: A theoretical and experimental approach

KAUST Repository

Hussain, Aftab M.; Singh, Nirpendra; Fahad, Hossain M.; Rader, Kelly; Schwingenschlö gl, Udo; Hussain, Muhammad Mustafa

2014-01-01

We present a novel semiconducting alloy, silicon-tin (SiSn), as channel material for complementary metal oxide semiconductor (CMOS) circuit applications. The material has been studied theoretically using first principles analysis as well

Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

Science.gov (United States)

Yoshikawa, Masanobu; Kosaka, Kenichi; Seki, Hirohumi; Kimoto, Tsunenobu

2016-07-01

We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET. © The Author(s) 2016.

Defect identification in semiconductors with positron annihilation: experiment and theory

Science.gov (United States)

Tuomisto, Filip

2015-03-01

Positron annihilation spectroscopy is a very powerful technique for the detection, identification and quantification of vacancy-type defects in semiconductors. In the past decades, it has been used to reveal the relationship between opto-electronic properties and specific defects in a wide variety of materials - examples include parasitic yellow luminescence in GaN, dominant acceptor defects in ZnO and broad-band absorption causing brown coloration in natural diamond. In typical binary compound semiconductors, the selective sensitivity of the technique is rather strongly limited to cation vacancies that possess significant open volume and suitable charge (negative of neutral). On the other hand, oxygen vacancies in oxide semiconductors are a widely debated topic. The properties attributed to oxygen vacancies include the inherent n-type conduction, poor p-type dopability, coloration (absorption), deep level luminescence and non-radiative recombination, while the only direct experimental evidence of their existence has been obtained on the crystal surface. We will present recent advances in combining state-of-the-art positron annihilation experiments and ab initio computational approaches. The latter can be used to model both the positron lifetime and the electron-positron momentum distribution - quantities that can be directly compared with experimental results. We have applied these methods to study vacancy-type defects in III-nitride semiconductors (GaN, AlN, InN) and oxides such as ZnO, SnO2, In2O3andGa2O3. We will show that cation-vacancy-related defects are important compensating centers in all these materials when they are n-type. In addition, we will show that anion (N, O) vacancies can be detected when they appear as complexes with cation vacancies.

Tailoring Charge Recombination in Photoelectrodes Using Oxide Nanostructures

DEFF Research Database (Denmark)

Iandolo, Beniamino; Wickman, Björn; Svensson, Elin

2016-01-01

Optimizing semiconductor devices for solar energy conversion requires an explicit control of the recombination of photogenerated electron−hole pairs. Here we show how the recombination of charge carriers can be controlled in semiconductor thin films by surface patterning with oxide nanodisks....... The control mechanism relies on the formation of dipole-like electric fields at the interface that, depending on the field direction, attract or repel minority carriers from underneath the disks. The charge recombination rate can be controlled through the choice of oxide material and the surface coverage...... of nanodisks. We provide proof-of-principle demonstration of this approach by patterning the surface of Fe2O3, one of the most studied semiconductors for light-driven water splitting, with TiO2 and Cu2O nanodisks. We expect this method to be generally applicable to a range of semiconductor-based solar energy...

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

KAUST Repository

Almuslem, A. S.; Hanna, Amir; Yapici, Tahir; Wehbe, N.; Diallo, Elhadj; Kutbee, Arwa T.; Bahabry, Rabab R.; Hussain, Muhammad Mustafa

2017-01-01

, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

Science.gov (United States)

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Directory of Open Access Journals (Sweden)

Amlan Ganguly

2018-02-01

Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Photodiodes based on fullerene semiconductor

International Nuclear Information System (INIS)

Voz, C.; Puigdollers, J.; Cheylan, S.; Fonrodona, M.; Stella, M.; Andreu, J.; Alcubilla, R.

2007-01-01

Fullerene thin films have been deposited by thermal evaporation on glass substrates at room temperature. A comprehensive optical characterization was performed, including low-level optical absorption measured by photothermal deflection spectroscopy. The optical absorption spectrum reveals a direct bandgap of 2.3 eV and absorption bands at 2.8 and 3.6 eV, which are related to the creation of charge-transfer excitons. Various photodiodes on indium-tin-oxide coated glass substrates were also fabricated, using different metallic contacts in order to compare their respective electrical characteristics. The influence of a poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) buffer layer between the indium-tin-oxide electrode and the fullerene semiconductor is also demonstrated. These results are discussed in terms of the workfunction for each electrode. Finally, the behaviour of the external quantum efficiency is analyzed for the whole wavelength spectrum

Measurement stand for diagnosis of semiconductor detectors based on IBM PC/XT computer (4-way spectrometric analysis of pulses)

International Nuclear Information System (INIS)

Gruszecki, M.

1990-01-01

The technical assumptions and partial realization of our technological stand for quality inspection of semiconductor detectors for ionizing radiation manufactured in the INP in Cracow are described. To increase the efficiency of the measurements simultaneous checking of 4 semiconductor chips or finished products is suggested. In order to justify this measurement technique a review of possible variants of the measurement apparatus is presented for the systems consisting of home made units. Comparative parameters for the component modules and for complete measuring systems are given. The construction and operation of data acquisition system based on IBM PC/XT are described. The system ensures simultaneous registration of pulses obtained from 4 detectors with maximal rate of up to 500 x 10 3 pulses/s. 42 refs., 6 figs., 3 tabs. (author)

Transparent polymeric cell culture chip with integrated temperature control and uniform media perfusion

DEFF Research Database (Denmark)

Petronis, Sarunas; Stangegaard, Michael; Christensen, C.

2006-01-01

Modern microfabrication and microfluidic technologies offer new opportunities in the design and fabrication of miniaturized cell culture systems for online monitoring of living cells. We used laser micromachining and thermal bonding to fabricate an optically transparent, low-cost polymeric chip...... for long-term online cell culture observation under controlled conditions. The chip incorporated a microfluidic flow equalization system, assuring uniform perfusion of the cell culture media throughout the cell culture chamber. The integrated indium-tin-oxide heater and miniature temperature probe linked....... HeLa cells were cultured for up to 2 weeks within the cell culture chip and monitored using a time-lapse video recording microscopy setup. Cell attachment and spreading was observed during the first 10-20 h (lag phase). After approximately 20 h, cell growth gained exponential character...

Bio Organic-Semiconductor Field-Effect Transistor (BioFET) Based on Deoxyribonucleic Acid (DNA) Gate Dielectric

Science.gov (United States)

2010-03-31

floating gate devices and metal-insulator-oxide-semiconductor (MIOS) devices. First attempts to use polarizable gate insulators in combination with...bulk of the semiconductor (ii) Due to the polarizable gate dielectric (iii) dipole polarization and (iv)electret effect due to mobile ions in the...characterization was carried out under an argon environment inside the glove box. An Agilent model E5273A with a two source-measurement unit instrument was

Lg = 100 nm In0.7Ga0.3As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

International Nuclear Information System (INIS)

Koh, D.; Kwon, H. M.; Kim, T.-W.; Veksler, D.; Gilmer, D.; Kirsch, P. D.; Kim, D.-H.; Hudnall, Todd W.; Bielawski, Christopher W.; Maszara, W.; Banerjee, S. K.

2014-01-01

In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In 0.53 Ga 0.47 As MOS capacitors with BeO and Al 2 O 3 and compared their electrical characteristics. As interface passivation layer, BeO/HfO 2 bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In 0.7 Ga 0.3 As QW MOSFETs with a BeO/HfO 2 dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g m,max ) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond

Fabrication and operation methods of a one-time programmable (OTP) nonvolatile memory (NVM) based on a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Cho, Seongjae; Lee, Junghoon; Jung, Sunghun; Park, Sehwan; Park, Byunggook

2011-01-01

In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

Instrumentation for characterizing materials and composed semiconductors for ionizing radiation detectors

International Nuclear Information System (INIS)

Paschoal, Arquimedes J.A.; Leite, Adolfo M.B.; Nazzre, Fabio V.B.; Santos, Luiz A.P.

2007-01-01

The purpose of this work is the development of instrumentation for characterizing some type of ionizing radiation detectors. Those detectors are being manufactured by the Nuclear Instrumentation Laboratory at CRCN/Recife and can be used both on photon beam and with particles. Such detectors consist of semiconductor material in the form of films generated by oxide growing or by means of semiconductor material deposition in a substrate. Those materials can be made of metals, semi-metals, composites or semiconductor polymers. Prior to expose those detectors to ionizing radiation, it must be physically and electrically characterized. In this intention it was developed an electromechanical system. An electrical circuit was built to measure the signal from the detector and another circuit to control the movement of four probes (4-points technique) by using a stepper motor and the micro stepping technique avoiding damage to the detector. This system can be of interest to researchers that work with a sort of semiconductor materials in the form of thin film and in nanotechnological processes aiming the design of radiation ionizing detectors. (author)

Organic / IV, III-V Semiconductor Hybrid Solar Cells

Directory of Open Access Journals (Sweden)

Pang-Leen Ong

2010-03-01

Full Text Available We present a review of the emerging class of hybrid solar cells based on organic-semiconductor (Group IV, III-V, nanocomposites, which states separately from dye synthesized, polymer-metal oxides and organic-inorganic (Group II-VI nanocomposite photovoltaics. The structure of such hybrid cell comprises of an organic active material (p-type deposited by coating, printing or spraying technique on the surface of bulk or nanostructured semiconductor (n-type forming a heterojunction between the two materials. Organic components include various photosensitive monomers (e.g., phtalocyanines or porphyrines, conjugated polymers, and carbon nanotubes. Mechanisms of the charge separation at the interface and their transport are discussed. Also, perspectives on the future development of such hybrid cells and comparative analysis with other classes of photovoltaics of third generation are presented.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

Assessing the antimicrobial activity of zinc oxide thin films using disk diffusion and biofilm reactor

International Nuclear Information System (INIS)

Gittard, Shaun D.; Perfect, John R.; Monteiro-Riviere, Nancy A.; Wei Wei; Jin Chunming; Narayan, Roger J.

2009-01-01

The electronic and chemical properties of semiconductor materials may be useful in preventing growth of microorganisms. In this article, in vitro methods for assessing microbial growth on semiconductor materials will be presented. The structural and biological properties of silicon wafers coated with zinc oxide thin films were evaluated using atomic force microscopy, X-ray photoelectron spectroscopy, and MTT viability assay. The antimicrobial properties of zinc oxide thin films were established using disk diffusion and CDC Biofilm Reactor studies. Our results suggest that zinc oxide and other semiconductor materials may play a leading role in providing antimicrobial functionality to the next-generation medical devices

The Electrical Characteristics of The N-Organic Semiconductor/P-Inorganic Semiconductor Diode

International Nuclear Information System (INIS)

Aydin, M. E.

2008-01-01

n-organic semiconductor (PEDOT) / p-inorganic semiconductor Si diode was formed by deep coating method. The method has been achieved by coating n-inorganic semiconductor PEDOT on top of p-inorganic semiconductor. The n-organic semiconductor PEDOT/ p-inorganic semiconductor diode demonstrated rectifying behavior by the current-voltage (I-V) curves studied at room temperature. The barrier height , ideality factor values were obtained as of 0.88 eV and 1.95 respectively. The diode showed non-ideal I-V behavior with an ideality factor greater than unity that could be ascribed to the interfacial layer

Semiconductor Metal Oxide Sensors in Water and Water Based Biological Systems

Directory of Open Access Journals (Sweden)

Marina V. Strobkova

2003-10-01

Full Text Available The results of implementation of In2O3-based semiconductor sensors for oxygen concentration evaluation in water and the LB-nutrient media (15.5 g/l Luria Broth Base, Miller (Sigma, Lot-1900 and NaCl without bacteria and with E.coli bacteria before and after UV-irradiation are presented.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

Science.gov (United States)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Recent advances in photoelectrochemistry. Part 1. Preparation and photocatalytic activities of semiconductor microcrystals; Saikin no hikari denki kagaku. 1. Handotai chobiryushi no chosei to hikari shokubai kassei

Energy Technology Data Exchange (ETDEWEB)

Yoneyama, H; Torimoto, T [Osaka Univ., Osaka (Japan). Faculty of Engineering

1995-01-05

The energy structure of semiconductor microcrystals with less than 10nm particle size is different from that of bulk semiconductor, and the reducing force of electrons and the oxidizing force of holes produced by light in microcrystals are larger than those of bulk semiconductor. Focusing on the application of semiconductor microcrystals to photocatalysis, the effects of the particle size and surface conditions of particles on photocatalytic activity are discussed. It has been shown that the change in the characteristics of semiconductor microcrystals depends on particle size, and microcrystals with narrow distribution of particle sized is necessary for the study of the characteristics of semiconductor microcrystals. An example of high efficient progress of CO2 direct reduction by the use of semiconductor microcrystals is introduced. It has been made clear that the photocatalytic activity of semiconductor is improved when a small amount of electrode catalyst is supported in it. A unique photocatalytic reaction which can not be observed with bulk particles can be progressed by the use of high oxidation and reduction ability caused by quantum size effect of semiconductor microcrystals. 26 refs., 2 figs., 1 tab.

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

Energy Technology Data Exchange (ETDEWEB)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena; Roccaforte, Fabrizio [Consiglio Nazionale delle Ricerche-Istituto per la Microelettronica e Microsistemi (CNR-IMM), Strada VIII 5, Zona Industriale 95121 Catania (Italy)

2016-07-04

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{sup 11} cm{sup −2}).

Structure and magnetism of transition-metal implanted dilute magnetic semiconductors

CERN Document Server

Pereira, Lino; Temst, K; Araújo, JP; Wahl, U

The discovery of a dilute magnetic semiconductor (DMS) in which ferromagnetism is carrier-mediated and persists above room temperature is a critical step towards the development of semiconductor-based spintronics. Among the many types of DMS materials which have been investigated, the current research interest can be narrowed down to two main classes of materials: (1) narrow-gap III-V semiconductors, mostly GaAs and InAs, doped with Mn; (2) wide-gap oxides and nitrides doped with 3d transition metals, mostly Mn- and Co-doped ZnO and Mn-doped GaN. With a number of interesting functionalities deriving from the carrier-mediated ferromagnetism and demonstrated in various proof-of-concept devices, Mn-doped GaAs has become, among DMS materials, one of the best candidates for technological application. However, despite major developments over the last 15 years, the maximum Curie temperature (185 K) remains well below room temperature. On the other hand, wide-gap DMS materials appear to exhibit ferromagnetic behavior...

Photoelectrochemical processes in organic semiconductor: Ambipolar perylene diimide thin film

Science.gov (United States)

Kim, Jung Yong; Chung, In Jae

2018-03-01

A thin film of N,N‧-dioctadecyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C18) is spin-coated on indium tin oxide (ITO) glass. Using the PTCDI-C18/ITO electrode, we fabricate a photoelectrochemical cell with the ITO/PTCDI-C18/Redox Electrolyte/Pt configuration. The electrochemical properties of this device are investigated as a function of hydroquinone (HQ) concentration, bias voltage, and wavelength of light. Anodic photocurrent is observed at V ≥ -0.2 V vs. Ag/AgCl, indicating that the PTCDI-C18 film acts as an n-type semiconductor as usual. However, when benzoquinone (BQ) is inserted into the electrolyte system instead of HQ, cathodic photocurrent is observed at V ≤ 0.0 V, displaying that PTCDI-C18 abnormally serves as a p-type semiconductor. Hence the overall results reveal that the PTCDI-C18 film can be an ambipolar functional semiconductor depending on the redox couple in the appropriate voltage.

Demonstration of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with silicon-oxy-nitride as the gate insulator

International Nuclear Information System (INIS)

Balachander, K.; Arulkumaran, S.; Egawa, T.; Sano, Y.; Baskar, K.

2005-01-01

AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOSHEMTs) were fabricated with plasma enhanced chemical vapor deposited silicon oxy-nitride (SiON) as an insulating layer. The compositions of SiON thin films were confirmed using X-ray photoelectron spectroscopy. The fabricated MOSHEMTs exhibited a very high saturation current density of 1.1 A/mm coupled with high positive operational gate voltage up to +7 V. The MOSHEMTs also exhibited four orders of low gate leakage current and high forward-on voltage when compared with the conventional HEMTs. The drain current collapse using gate pulse measurements showed only a negligible difference in the saturation current density revealing the drastic improvement in passivation of the surface states due to the high quality of dielectric thin films deposited. Thus, based on the improved direct-current operation, SiON can be considered to be a potential gate oxide comparable with other dielectric insulators

The Impact of HCl Precleaning and Sulfur Passivation on the Al2O3/Ge Interface in Ge Metal-Oxide-Semiconductor Capacitors

International Nuclear Information System (INIS)

Xue Bai-Qing; Chang Hu-Dong; Sun Bing; Wang Sheng-Kai; Liu Hong-Gang

2012-01-01

Surface treatment for Ge substrates using hydrogen chlorine cleaning and chemical passivation are investigated on AuTi/Al 2 O 3 /Ge metal-oxide-semiconductor capacitors. After hydrogen chlorine cleaning, a smooth Ge surface almost free from native oxide is demonstrated by atomic force microscopy and x-ray photoelectron spectroscopy observations. Passivation using a hydrogen chlorine solution is found to form a chlorine-terminated surface, while aqueous ammonium sulfide pretreatment results in a surface terminated by Ge-S bonding. Compared with chlorine-passivated samples, the sulfur-passivated ones show less frequency dispersion and better thermal stability based on capacitance-voltage characterizations. The samples with HCl pre-cleaning and (NH 4 ) 2 S passivation show less frequency dispersion than the HF pre-cleaning and (NH 4 ) 2 S passivated ones. The surface treatment process using hydrogen chlorine cleaning followed by aqueous ammonium sulfide passivation demonstrates a promising way to improve gate dielectric/Ge interface quality. (condensed matter: structure, mechanical and thermal properties)

Photocatalysis of irradiated semiconductor surfaces: Its application to water splitting and some organic reactions

Energy Technology Data Exchange (ETDEWEB)

Sakata, T

1985-05-01

Hydrogen production from organic compounds and water was investigated using powdered semiconductor photocatalysts. The complete decomposition observed for several organic compounds demonstrated that water is involved in the reactions as an oxidizing agent. Photocatalyses of dyes and semiconductors were found to be applicable to amino acid synthesis. The quantum yields of photocatalytic amino acid synthesis using visible light are about 20%-40% in the absence of a metal catalyst such as platinum. Moreover the reactions are highly selective and depend strongly on the type of semiconductor. This method was applied to the asymmetric synthesis of amino acids using asymmetric catalysts. Rather high optical yields of 50% were achieved for the synthesis of L-phenylalanine.

Semiconductor Physical Electronics

CERN Document Server

Li, Sheng

2006-01-01

Semiconductor Physical Electronics, Second Edition, provides comprehensive coverage of fundamental semiconductor physics that is essential to an understanding of the physical and operational principles of a wide variety of semiconductor electronic and optoelectronic devices. This text presents a unified and balanced treatment of the physics, characterization, and applications of semiconductor materials and devices for physicists and material scientists who need further exposure to semiconductor and photonic devices, and for device engineers who need additional background on the underlying physical principles. This updated and revised second edition reflects advances in semicondutor technologies over the past decade, including many new semiconductor devices that have emerged and entered into the marketplace. It is suitable for graduate students in electrical engineering, materials science, physics, and chemical engineering, and as a general reference for processing and device engineers working in the semicondi...

Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

International Nuclear Information System (INIS)

Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

2015-01-01

Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

A micro-chip initiator with controlled combustion reactivity realized by integrating Al/CuO nanothermite composites on a microhotplate platform

International Nuclear Information System (INIS)

Ahn, Ji Young; Lee, Hyung Woo; Kim, Jong Man; Kim, Soo Hyung; Kim, Sang Beom; Kim, Ji Hoon; Jang, Nam Su; Kim, Dae Hyun

2016-01-01

The interfacial contact area between the fuel and oxidizer components plays an important role in determining the combustion reactivity of nanothermite composites. In addition, the development of compact and reliable ignition methods can extend the applicability of nanothermite composites to various thermal engineering fields. In this study we report the development of a micro-chip initiator with controlled combustion reactivity using concepts usually applied to microelectromechanical systems (MEMS) and simple nanofabrication processes. The nanothermite composites fabricated in this study consisted of aluminum nanoparticles (Al NPs) as the fuel and copper oxide nanoparticles (CuO NPs) as the oxidizer accumulated on a silicon oxide substrate with a serpentine-shaped gold (Au) electrode. The micro-chip initiator rapidly ignited and exploded when minimal current was supplied. The effects of stacking structures of Al and CuO-based multilayers on the combustion properties were systematically investigated in terms of the pressurization rate, peak explosion time, and heat flow. Pressurization rates of 0.004–0.025 MPa μs −1 and heat flows of 2.0–3.8 kJ g −1 with a commonly fast response time of less than 20 ms could be achieved by simply changing the interfacial structures of the Al and CuO multilayers. The controllability of combustion reactivity of micro-chip initiator can be made for general nanothermite composites composed of Al and various metal oxides (e.g. Fe 2 O 3 , CuO, KMnO 4 , etc). The micro-chip initiator fabricated in this study was reliable, compact, and proved to be a versatile platform, exhibiting controlled combustion reactivity and fast response time, which could be used for various civilian and military thermal engineering applications, such as in initiators and propulsion, welding, and ordinance systems. (paper)

The ignitability potential of uranium {open_quotes}roaster oxide{close_quotes}

Energy Technology Data Exchange (ETDEWEB)

Stakebake, J.L.

1994-11-01

The oxidation of uranium to form Uranium `roaster oxide` was investigated with respect to concerns of unreacted metal remaining in the roaster oxide matrix. It was found that ignition of unreacted uranium chips in the roaster oxide as synthesized is unlikely under normal storage conditions.

III-V semiconductors for photoelectrochemical applications: surface preparation and characterization

Energy Technology Data Exchange (ETDEWEB)

Fertig, Dominic; Schaechner, Birgit; Calvet, Wofram; Kaiser, Bernhard; Jaegermann, Wolfram [TU Darmstadt, Fachbereich Materialwissenschaft, Fachgebiet Oberflaechenforschung (Germany)