Nonvolatile Memory Technology for Space Applications

Science.gov (United States)

Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

2010-01-01

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Overview of emerging nonvolatile memory technologies.

Science.gov (United States)

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Overview of emerging nonvolatile memory technologies

Science.gov (United States)

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure

International Nuclear Information System (INIS)

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-01

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 μm 2 to 200 x 200 nm 2 . From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I ON /I OFF ∼10 4 ), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10 000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

Non-volatile memories

CERN Document Server

Lacaze, Pierre-Camille

2014-01-01

Written for scientists, researchers, and engineers, Non-volatile Memories describes the recent research and implementations in relation to the design of a new generation of non-volatile electronic memories. The objective is to replace existing memories (DRAM, SRAM, EEPROM, Flash, etc.) with a universal memory model likely to reach better performances than the current types of memory: extremely high commutation speeds, high implantation densities and retention time of information of about ten years.

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James; Wyatt-Moon, Gwenhivir; Georgiadou, Dimitra G.; McLachlan, Martyn A.; Anthopoulos, Thomas D.

2017-01-01

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

KAUST Repository

Semple, James

2017-01-02

Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

Design exploration of emerging nano-scale non-volatile memory

CERN Document Server

Yu, Hao

2014-01-01

This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices.  Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design, and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices.  Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design.   • Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; • Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design, and hybrid NVM memory system optimization; • Provides both theoretical analysis and pr...

Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

Institute of Scientific and Technical Information of China (English)

Young; Tea; Chun; Daping; Chu

2015-01-01

Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

International Nuclear Information System (INIS)

Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

2005-01-01

Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

Science.gov (United States)

Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

2011-06-01

Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

2015-01-01

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

Directory of Open Access Journals (Sweden)

Mohamed T. Ghoneim

2015-07-01

Full Text Available Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT, the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

KAUST Repository

Ghoneim, Mohamed T.

2015-07-23

Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

Anomalous Threshold Voltage Variability of Nitride Based Charge Storage Nonvolatile Memory Devices

Directory of Open Access Journals (Sweden)

Meng Chuan Lee

2013-01-01

Full Text Available Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM devices. In this study, effect of technology scaling to anomalous threshold voltage ( variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cell’s variability of each subsequent bake increases within stable distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous variability was derived through Arrhenius plots. Apparent activation energy (Eaa of this anomalous variability is 0.67 eV at sub-40 nm devices which is a reduction of approximately 2 times from 110 nm devices. Technology scaling clearly aggravates this anomalous variability, and this poses reliability challenges to applications that demand strict control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

Science.gov (United States)

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-01

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

Science.gov (United States)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

International Nuclear Information System (INIS)

Wang Guangli; Chen Yubin; Shi Yi; Pu Lin; Pan Lijia; Zhang Rong; Zheng Youdou

2010-01-01

A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method. (semiconductor devices)

Channel equalization techniques for non-volatile memristor memories

KAUST Repository

Naous, Rawan

2016-03-16

Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

Channel equalization techniques for non-volatile memristor memories

KAUST Repository

Naous, Rawan; Zidan, Mohammed A.; Salem, Ahmed Sultan; Salama, Khaled N.

2016-01-01

Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Alshareef, Husam N.

2012-01-01

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage

Phosphorene/ZnO Nano-Heterojunctions for Broadband Photonic Nonvolatile Memory Applications.

Science.gov (United States)

Hu, Liang; Yuan, Jun; Ren, Yi; Wang, Yan; Yang, Jia-Qin; Zhou, Ye; Zeng, Yu-Jia; Han, Su-Ting; Ruan, Shuangchen

2018-06-10

High-performance photonic nonvolatile memory combining photosensing and data storage with low power consumption ensures the energy efficiency of computer systems. This study first reports in situ derived phosphorene/ZnO hybrid heterojunction nanoparticles and their application in broadband-response photonic nonvolatile memory. The photonic nonvolatile memory consistently exhibits broadband response from ultraviolet (380 nm) to near infrared (785 nm), with controllable shifts of the SET voltage. The broadband resistive switching is attributed to the enhanced photon harvesting, a fast exciton separation, as well as the formation of an oxygen vacancy filament in the nano-heterojunction. In addition, the device exhibits an excellent stability under air exposure compared with reported pristine phosphorene-based nonvolatile memory. The superior antioxidation capacity is believed to originate from the fast transfer of lone-pair electrons of phosphorene. The unique assembly of phosphorene/ZnO nano-heterojunctions paves the way toward multifunctional broadband-response data-storage techniques. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile organic write-once-read-many-times memory devices based on hexadecafluoro-copper-phthalocyanine

Science.gov (United States)

Wang, Lidan; Su, Zisheng; Wang, Cheng

2012-05-01

Nonvolatile organic write-once-read-many-times memory device was demonstrated based on hexadecafluoro-copper-phthalocyanine (F16CuPc) single layer sandwiched between indium tin oxide (ITO) anode and Al cathode. The as fabricated device remains in ON state and it can be tuned to OFF state by applying a reverse bias. The ON/OFF current ratio of the device can reach up to 2.3 × 103. Simultaneously, the device shows long-term storage stability and long retention time in air. The ON/OFF transition is attributed to the formation and destruction of the interfacial dipole layer in the ITO/F16CuPc interface, and such a mechanism is different from previously reported ones.

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS2 quantum dot-polymethylmethacrylate nanocomposites

International Nuclear Information System (INIS)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

2014-01-01

Nonvolatile memory devices based on CuInS 2 (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10 −10 was maintained for 8 × 10 3 cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10 6 cycles converged to 2.40 × 10 −10 , indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams

Non-volatile memory based on the ferroelectric photovoltaic effect

Science.gov (United States)

Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

2013-01-01

The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

International Nuclear Information System (INIS)

Sung, Sihyun; Kim, Tae Whan

2017-01-01

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10 3 and 1.4 × 10 3 , respectively. The retention times of the devices before and after bending remained same 1 × 10 4 s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

Energy Technology Data Exchange (ETDEWEB)

Sung, Sihyun; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2017-07-31

Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10{sup 3} and 1.4 × 10{sup 3}, respectively. The retention times of the devices before and after bending remained same 1 × 10{sup 4} s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

Physical principles and current status of emerging non-volatile solid state memories

Science.gov (United States)

Wang, L.; Yang, C.-H.; Wen, J.

2015-07-01

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

Overview of radiation effects on emerging non-volatile memory technologies

Directory of Open Access Journals (Sweden)

Fetahović Irfan S.

2017-01-01

Full Text Available In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. 171007

Effect of Ag nanoparticles on resistive switching of polyfluorene-based organic non-volatile memory devices

International Nuclear Information System (INIS)

Kim, Tae-Wook; Oh, Seung-Hwan; Choi, Hye-Jung; Wang, Gun-Uk; Kim, Dong-Yu; Hwang, Hyun-Sang; Lee, Tak-Hee

2010-01-01

The effects of Ag nanoparticles on the switching behavior of polyfluorene-based organic nonvolatile memory devices were investigated. Polyfluorene-derivatives (WPF-oxy-F) with and without Ag nanoparticles were synthesized, and the presence of Ag nanoparticles in Ag-WPF-oxy-F was identified by transmission electron microscopy and X-ray photoelectron spectroscopy analyses. The Ag-nanoparticles did not significantly affect the basic switching performances, such as the current-voltage characteristics, the distribution of on/off resistance, and the retention. The pulse switching time of Ag-WPF-oxy-F was faster than that of WPF-oxy-F. Ag-WPF-oxy-F memory devices showed an area dependence in the high resistance state, implying that formation of a Ag metallic channel for current conduction.

A memristor-based nonvolatile latch circuit

International Nuclear Information System (INIS)

Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia Qiangfei; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2010-01-01

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Organic non-volatile memories from ferroelectric phase-separated blends

Science.gov (United States)

Asadi, Kamal; de Leeuw, Dago M.; de Boer, Bert; Blom, Paul W. M.

2008-07-01

New non-volatile memories are being investigated to keep up with the organic-electronics road map. Ferroelectric polarization is an attractive physical property as the mechanism for non-volatile switching, because the two polarizations can be used as two binary levels. However, in ferroelectric capacitors the read-out of the polarization charge is destructive. The functionality of the targeted memory should be based on resistive switching. In inorganic ferroelectrics conductivity and ferroelectricity cannot be tuned independently. The challenge is to develop a storage medium in which the favourable properties of ferroelectrics such as bistability and non-volatility can be combined with the beneficial properties provided by semiconductors such as conductivity and rectification. Here we present an integrated solution by blending semiconducting and ferroelectric polymers into phase-separated networks. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-metal contact. The combination of ferroelectric bistability with (semi)conductivity and rectification allows for solution-processed non-volatile memory arrays with a simple cross-bar architecture that can be read out non-destructively. The concept of an electrically tunable injection barrier as presented here is general and can be applied to other electronic devices such as light-emitting diodes with an integrated on/off switch.

A review of emerging non-volatile memory (NVM) technologies and applications

Science.gov (United States)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Poly (vinylidene fluoride-trifluoroethylene/barium titanate nanocomposite for ferroelectric nonvolatile memory devices

Directory of Open Access Journals (Sweden)

Uvais Valiyaneerilakkal

2013-04-01

Full Text Available The effect of barium titanate (BaTiO3 nanoparticles (particle size <100nm on the ferroelectric properties of poly (vinylidenefluoride-trifluoroethylene P(VDF-TrFE copolymer has been studied. Different concentrations of nanoparticles were added to P(VDF-TrFE using probe sonication, and uniform thin films were made. Polarisation - Electric field (P-E hysteresis analysis shows an increase in remnant polarization (Pr and decrease in coercive voltage (Vc. Piezo-response force microscopy analysis shows the switching capability of the polymer composite. The topography and surface roughness was studied using atomic force microscopy. It has been observed that this nanocomposite can be used for the fabrication of non-volatile ferroelectric memory devices.

Coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3/In memristive devices

International Nuclear Information System (INIS)

Yang, M; Bao, D H; Li, S W

2013-01-01

Memristive devices are triggering innovations in the fields of nonvolatile memory, digital logic, analogue circuits, neuromorphic engineering, and so on. Creating new memristive devices with unique characteristics would be significant for these emergent applications. Here we report the coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO 3 (NSTO)/In memristive devices. The Pt/NSTO interface contributes a nonvolatile resistive switching behaviour, whereas the NSTO/In interface displays a volatile hysteresis loop. Combining the two interfaces in the Pt/NSTO/In devices leads to the unique coexistence of nonvolatility and volatility. The results imply more opportunities to invent new memristive devices by engineering both interfaces in metal/insulator/metal structures. (paper)

Radiation evaluation of commercial ferroelectric nonvolatile memories

International Nuclear Information System (INIS)

Benedetto, J.M.; DeLancey, W.M.; Oldham, T.R.; McGarrity, J.M.; Tipton, C.W.; Brassington, M.; Fisch, D.E.

1991-01-01

This paper reports on ferroelectric (FE) on complementary metal-oxide semiconductor (CMOS) 4-kbit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips that were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-kbit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field- oxide effects in the underlying CMOS. No significant difference was observed between the radiation responses of devices with and without the FE film in this commercial process

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-07-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

Low-power non-volatile spintronic memory: STT-RAM and beyond

International Nuclear Information System (INIS)

Wang, K L; Alzate, J G; Khalili Amiri, P

2013-01-01

The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets. (paper)

High-performance non-volatile organic ferroelectric memory on banknotes

KAUST Repository

Khan, Yasser

2012-03-21

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance non-volatile organic ferroelectric memory on banknotes.

Science.gov (United States)

Khan, M A; Bhansali, Unnat S; Alshareef, H N

2012-04-24

High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

International Nuclear Information System (INIS)

Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

2006-01-01

Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Science.gov (United States)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Low-temperature process steps for realization of non-volatile memory devices

NARCIS (Netherlands)

Brunets, I.; Boogaard, A.; Aarnink, Antonius A.I.; Kovalgin, Alexeij Y.; Wolters, Robertus A.M.; Holleman, J.; Schmitz, Jurriaan

2007-01-01

In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

Science.gov (United States)

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

Science.gov (United States)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-01-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

Nonvolatile memory design magnetic, resistive, and phase change

CERN Document Server

Li, Hai

2011-01-01

The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances,

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

Energy Technology Data Exchange (ETDEWEB)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

International Nuclear Information System (INIS)

Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

2013-01-01

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices

Nonvolatile Rad-Hard Holographic Memory

Science.gov (United States)

Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

2001-01-01

We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

Science.gov (United States)

Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

2016-02-01

We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

Method for refreshing a non-volatile memory

Science.gov (United States)

Riekels, James E.; Schlesinger, Samuel

2008-11-04

A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

A study on electromechanical carbon nanotube memory devices

International Nuclear Information System (INIS)

Kang, Jeong Won; Hwang, Ho Jung

2005-01-01

Electromechanical operations of carbon-nanotube (CNT) bridge memory device were investigated by using atomistic simulations based on empirical potentials. The nanotube-bridge memory device was operated by the electrostatic and the van der Waals forces acting on the nanotube-bridge. For the CNT bridge memory device, the van der Waals interactions between the CNT bridge and the oxide were very important. As the distance between the CNT bridge and the oxide decreased and the van der Waals interaction energy increased, the pull-in bias of the CNT-bridge decreased and the nonvolatility of the nanotube-bridge memory device increased, while the pull-out voltages increased. When the materials composed of the oxide film are different, since the van der Waals interactions must be also different, the oxide materials must be carefully selected for the CNT-bridge memory device to work as a nonvolatile memory.

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

Energy Technology Data Exchange (ETDEWEB)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2014-10-20

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

International Nuclear Information System (INIS)

Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

2014-01-01

High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

Science.gov (United States)

Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

2018-01-01

In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer

International Nuclear Information System (INIS)

Cho, Sung Hwan; Lee, Dong Ik; Jung, Jae Hun; Kim, Tae Whan

2009-01-01

Current-voltage (I-V) measurements on Al/fullerene (C 60 ) molecules embedded in polymethyl methacrylate/Al devices at 300 K showed a current bistability due to the existence of the C 60 molecules. The on/off ratio of the current bistability for the memory devices was as large as 10 3 . The retention time of the devices was above 2.5 x 10 4 s at room temperature, and cycling endurance tests on these devices indicated that the ON and OFF currents showed no degradation until 50 000 cycles. Carrier transport mechanisms for the nonvolatile bistable devices are described on the basis of the I-V experimental and fitting results.

A direct metal transfer method for cross-bar type polymer non-volatile memory applications

International Nuclear Information System (INIS)

Kim, Tae-Wook; Lee, Kyeongmi; Oh, Seung-Hwan; Wang, Gunuk; Kim, Dong-Yu; Jung, Gun-Young; Lee, Takhee

2008-01-01

Polymer non-volatile memory devices in 8 x 8 array cross-bar architecture were fabricated by a non-aqueous direct metal transfer (DMT) method using a two-step thermal treatment. Top electrodes with a linewidth of 2 μm were transferred onto the polymer layer by the DMT method. The switching behaviour of memory devices fabricated by the DMT method was very similar to that of devices fabricated by the conventional shadow mask method. The devices fabricated using the DMT method showed three orders of magnitude of on/off ratio with stable resistance switching, demonstrating that the DMT method can be a simple process to fabricate organic memory array devices

Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

Science.gov (United States)

Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

2018-05-01

A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

International Nuclear Information System (INIS)

Miura, Atsushi; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi; Tsukamoto, Rikako; Yoshii, Shigeo

2008-01-01

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co 3 O 4 ) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

Science.gov (United States)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

The origin of traps and the effect of nitrogen plasma in oxide-nitride-oxide structures for non-volatile memories

International Nuclear Information System (INIS)

Kim, W. S.; Kwak, D. W.; Oh, J. S.; Lee, D. W.; Cho, H. Y.

2010-01-01

Ultrathin oxide-nitride-oxide (ONO) dielectric stacked layers are fundamental structures of silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory devices in which information is known to be stored as charges trapped in silicon nitride. Deep-level transient spectroscopy (DLTS) and a capacitance-voltage (CV) analysis were introduced to observe the trap behavior related to the memory effect in memory devices. The DLTS results verified that the nitride-related traps were a dominant factor in the memory effect. The energy of hole traps was 0.307 eV above the balance band. To improve the memory effects of the non-volatile memory devices with ONO structures, we introduced a nitrogen plasma treatment. After the N-plasma treatment, the flat-band voltage shift (ΔV FB ) was increased by about 1.5 times. The program and the erase (P-E) characteristics were also shown to be better than those for the as-ONO structure. In addition, the retention characteristics were improved by over 2.4 times.

The retention characteristics of nonvolatile SNOS memory transistors in a radiation environment: Experiment and model

International Nuclear Information System (INIS)

McWhorter, P.J.; Miller, S.L.; Dellin, T.A.; Axness, C.L.

1987-01-01

Experimental data and a model to accurately and quantitatively predict the data are presented for retention of SNOS memory devices over a wide range of dose rates. A wide range of SNOS stack geometries are examined. The model is designed to aid in screening nonvolatile memories for use in a radiation environment

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

International Nuclear Information System (INIS)

Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

2010-01-01

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

The MONOS memory transistor: application in a radiation-hard nonvolatile RAM

International Nuclear Information System (INIS)

Brown, W.D.

1985-01-01

The MONOS (metal-oxide-nitride-oxide-silicon) device is a prime candidate for use as the nonvolatile memory element in a radiation-hardened RAM (random-access memory). The endurance, retention and radiation properties of MONOS memory transistors have been studied as a function of post nitride deposition annealing. Following the nitride layer deposition, all devices were subjected to an 800 0 C oxidation step and some were then annealed at 900 0 C in nitrogen. The nitrogen anneal produces an increase in memory window size of approximately 40%. The memory window center of the annealed devices is shifted toward more positive voltages and is more stable with endurance cycling. Endurance cycling to 10 9 cycles produces a 20% increase in memory window size and a 60% increase in decay rate. For a radiation total dose of 10 6 rads (Si), the memory window size is essentially unchanged and the decay rate increases approximately 13%. A combination of 10 9 cycles and 10 6 rads (Si) reduces the decades of retention (in sec) from 6.3 to 4.3 for a +- 23-V 16-μsec write/erase pulse. (author)

Electrical bistabilities and memory mechanisms of nonvolatile organic bistable devices based on exfoliated muscovite-type mica nanoparticle/poly(methylmethacrylate) nanocomposites

Science.gov (United States)

Lim, Won Gyu; Lee, Dea Uk; Na, Han Gil; Kim, Hyoun Woo; Kim, Tae Whan

2018-02-01

Organic bistable devices (OBDs) with exfoliated mica nanoparticles (NPs) embedded into an insulating poly(methylmethacrylate) (PMMA) layer were fabricated by using a spin-coating method. Current-voltage (I-V) curves for the Al/PMMA/exfoliated mica NP/PMMA/indium-tin-oxide/glass devices at 300 K showed a clockwise current hysteresis behavior due to the existence of the exfoliated muscovite-type mica NPs, which is an essential feature for bistable devices. Write-read-erase-read data showed that the OBDs had rewritable nonvolatile memories and an endurance number of ON/OFF switching for the OBDs of 102 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times larger than 1 × 104 s. The memory mechanisms of the fabricated OBDs were described by using the trapping and the tunneling processes within a PMMA active layer containing exfoliated muscovite-type mica NPs on the basis of the energy band diagram and the I-V curves.

Active non-volatile memory post-processing

Energy Technology Data Exchange (ETDEWEB)

Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

2017-04-11

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

Science.gov (United States)

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

Science.gov (United States)

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

Energy Technology Data Exchange (ETDEWEB)

DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

1999-11-01

Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

Science.gov (United States)

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

Energy Technology Data Exchange (ETDEWEB)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P. [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India); Mukherjee, Rabibrata [Department of Chemical Engineering, Indian Institute of Technology, Kharagpur 721302 (India)

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

Development of novel nonvolatile memory devices using the colossal magnetoresistive oxide praseodymium-calcium-manganese trioxide

Science.gov (United States)

Papagianni, Christina

Pr0.7Ca0.3MnO3 (PCMO) manganese oxide belongs in the family of materials known as transition metal oxides. These compounds have received increased attention due to their perplexing properties such as Colossal Magnetoresistance effect, Charge-Ordered phase, existence of phase-separated states etc. In addition, it was recently discovered that short electrical pulses in amplitude and duration are sufficient to induce reversible and non-volatile resistance changes in manganese perovskite oxide thin films at room temperature, known as the EPIR effect. The existence of the EPIR effect in PCMO thin films at room temperature opens a viable way for the realization of fast, high-density, low power non-volatile memory devices in the near future. The purpose of this study is to investigate, optimize and understand the properties of Pr0.7Ca0.3MnO 3 (PCMO) thin film devices and to identify how these properties affect the EPIR effect. PCMO thin films were deposited on various substrates, such as metals, and conducting and insulating oxides, by pulsed laser and radio frequency sputtering methods. Our objective was to understand and compare the induced resistive states. We attempted to identify the induced resistance changes by considering two resistive models to be equivalent to our devices. Impedance spectroscopy was also utilized in a wide temperature range that was extended down to 70K. Fitted results of the temperature dependence of the resistance states were also included in this study. In the same temperature range, we probed the resistance changes in PCMO thin films and we examined whether the phase transitions affect the EPIR effect. In addition, we included a comparison of devices with electrodes consisting of different size and different materials. We demonstrated a direct relation between the EPIR effect and the phase diagram of bulk PCMO samples. A model that could account for the observed EPIR effect is presented.

Organic non-volatile memories from ferroelectric phase separated blends

Science.gov (United States)

Asadi, Kamal; de Leeuw, Dago; de Boer, Bert; Blom, Paul

2009-03-01

Ferroelectric polarisation is an attractive physical property for non-volatile binary switching. The functionality of the targeted memory should be based on resistive switching. Conductivity and ferroelectricity however cannot be tuned independently. The challenge is to develop a storage medium in which the favourable properties of ferroelectrics such as bistability and non-volatility can be combined with the beneficial properties provided by semiconductors such as conductivity and rectification. In this contribution we present an integrated solution by blending semiconducting and ferroelectric polymers into phase separated networks. The polarisation field of the ferroelectric modulates the injection barrier at the semiconductor--metal contact. This combination allows for solution-processed non-volatile memory arrays with a simple cross-bar architecture that can be read-out non-destructively. Based on this general concept a non-volatile, reversible switchable Schottky diode with relatively fast programming time of shorter than 100 microseconds, long information retention time of longer than 10^ days, and high programming cycle endurance with non-destructive read-out is demonstrated.

Ferroelectric-gate field effect transistor memories device physics and applications

CERN Document Server

Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

2016-01-01

This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

Ferroelectric memories: A possible answer to the hardened nonvolatile question

International Nuclear Information System (INIS)

Messenger, G.C.; Coppage, F.N.

1988-01-01

Ferroelectric memory cells have been fabricated using a process compatible with semiconductor VLSI (Very Large-Scale Integration) manufacturing techniques which are basically nonvolatile and radiation hard. The memory can be made NDRO (Nondestructive Readout) for strategic systems using several techniques; the most practical is probably a rapid read/restore in combination with EDAC software. This memory can replace plated wire and will have substantial advantages in cost, weight, size, power and speed. It provides a practical cost-competitive solution to the need for nonvolatile RAM in all hardened tactical, avionic, and space systems

A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

Science.gov (United States)

Liu, S. Q.; Wu, N. J.; Ignatiev, A.

2001-01-01

A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

A radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots

OpenAIRE

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; De Blauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO_2 is a critical aspect of the performance ...

A graphene-based non-volatile memory

Science.gov (United States)

Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

2015-09-01

We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

Energy Technology Data Exchange (ETDEWEB)

Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung, E-mail: mskang@ssu.ac.kr [Department of Chemical Engineering, Soongsil University, Seoul 156-743 (Korea, Republic of)

2015-02-09

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

Silicon nano crystal-based non-volatile memory devices

International Nuclear Information System (INIS)

Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

2006-01-01

In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

Nonvolatile memory effect of tungsten nanocrystals under oxygen plasma treatments

International Nuclear Information System (INIS)

Chen, Shih-Cheng; Chang, Ting-Chang; Chen, Wei-Ren; Lo, Yuan-Chun; Wu, Kai-Ting; Sze, S.M.; Chen, Jason; Liao, I.H.; Yeh, Fon-Shan

2010-01-01

In this work, an oxygen plasma treatment was used to improve the memory effect of nonvolatile W nanocrystal memory, including memory window, retention and endurance. To investigate the role of the oxygen plasma treatment in charge storage characteristics, the X-ray photon-emission spectra (XPS) were performed to analyze the variation of chemical composition for W nanocrystal embedded oxide both with and without the oxygen plasma treatment. In addition, the transmission electron microscopy (TEM) analyses were also used to identify the microstructure in the thin film and the size and density of W nanocrystals. The device with the oxygen plasma treatment shows a significant improvement of charge storage effect, because the oxygen plasma treatment enhanced the quality of silicon oxide surrounding the W nanocrystals. Therefore, the data retention and endurance characteristics were also improved by the passivation.

Intrinsic Ge nanowire nonvolatile memory based on a simple core–shell structure

International Nuclear Information System (INIS)

Chen, Wen-Hua; Liu, Chang-Hai; Li, Qin-Liang; Sun, Qi-Jun; Liu, Jie; Gao, Xu; Sun, Xuhui; Wang, Sui-Dong

2014-01-01

Intrinsic Ge nanowires (NWs) with a Ge core covered by a thick Ge oxide shell are utilized to achieve nanoscale field-effect transistor nonvolatile memories, which show a large memory window and a high ON/OFF ratio with good retention. The retainable surface charge trapping is considered to be responsible for the memory effect, and the Ge oxide shell plays a key role as the insulating tunneling dielectric which must be thick enough to prevent stored surface charges from leaking out. Annealing the device in air is demonstrated to be a simple and effective way to attain thick Ge oxide on the Ge NW surface, and the Ge-NW-based memory corresponding to thick Ge oxide exhibits a much better retention capability compared with the case of thin Ge oxide. (paper)

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

Science.gov (United States)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

Role of Non-Volatile Memories in Automotive and IoT Markets

Science.gov (United States)

2017-03-01

Standard Manufacturing Supply Long Term Short to Medium Term Density Up to 16MB Up to 2MB IO Configuration Up to x128 Up to x32 Design for Test...Role of Non-Volatile Memories in Automotive and IoT Markets Vipin Tiwari Director, Business Development and Product Marketing SST – A Wholly Own...microcontrollers (MCU) and certainly one of the most challenging elements to master. This paper addresses the role of non-volatile memories for

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

Science.gov (United States)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

Science.gov (United States)

Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

2018-09-01

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

2016-07-11

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

International Nuclear Information System (INIS)

Xian-Gao, Zhang; Kun-Ji, Chen; Zhong-Hui, Fang; Xin-Ye, Qian; Guang-Yuan, Liu; Xiao-Fan, Jiang; Zhong-Yuan, Ma; Jun, Xu; Xin-Fan, Huang; Jian-Xin, Ji; Fei, He; Kuang-Bao, Song; Jun, Zhang; Hui, Wan; Rong-Hua, Wang

2010-01-01

A nonvolatile memory device with nitrided Si nanocrystals embedded in a Boating gate was fabricated. The uniform Si nanocrystals with high density (3 × 10 11 cm −2 ) were deposited on ultra-thin tunnel oxide layer (∼ 3 nm) and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanocrystals, which slows the charge loss rate. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Science.gov (United States)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Directory of Open Access Journals (Sweden)

Fabrizio Riente

2017-05-01

Full Text Available Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

Energy Technology Data Exchange (ETDEWEB)

Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

2010-09-01

Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

The influence of thickness on memory characteristic based on nonvolatile tuning behavior in poly(N-vinylcarbazole) films

International Nuclear Information System (INIS)

Sun, Yanmei; Ai, Chunpeng; Lu, Junguo; Li, Lei; Wen, Dianzhong; Bai, Xuduo

2016-01-01

The memory characteristic based on nonvolatile tuning behavior in indium tin oxide/poly(N-vinylcarbazole)/aluminum (ITO/PVK/Al) was investigated, the different memory behaviors were first observed in PVK film as the film thickness changing. By control of PVK film thickness with different spinning speeds, the nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned in a controlled manner. Obviously different nonvolatile behaviors, such as (i) flash memory behavior and (ii) write-once-read-many times (WORM) memory behavior are from the current–voltage (I–V) characteristics of the PVK films. The results suggest that the film thickness plays a key part in determining the memory type of the PVK. - Highlights: • The different memory behaviors were observed in PVK film. • The nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned. • The film thickness plays a key part in determining the memory type of the PVK.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

Science.gov (United States)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

International Nuclear Information System (INIS)

Tang Zhen-Jie; Li Rong; Yin Jiang

2013-01-01

ZrO 2 nanocrystallite-based charge trap flash memory capacitors incorporating a (ZrO 2 ) 0.6 (SiO 2 ) 0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated. The precipitation reaction in the charge trapping layer, forming ZrO 2 nanocrystallites during rapid thermal annealing, was investigated by transmission electron microscopy and X-ray diffraction. It was observed that a ZrO 2 nanocrystallite-based memory capacitor after post-annealing at 850 °C for 60 s exhibits a maximum memory window of about 6.8 V, good endurance and a low charge loss of ∼25% over a period of 10 years (determined by extrapolating the charge loss curve measured experimentally), even at 85 °C. Such 850 °C-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications

Future Trend of Non-Volatile Semiconductor Memory and Feasibility Study of BiCS Type Stacked Structure

OpenAIRE

渡辺, 重佳

2009-01-01

Future trend of non-volatile semiconductor memory—FeRAM, MRAM, PRAM, ReRAM—compared with NAND typeflash memory has been described based on its history, application and performance. In the realistic point of view,FeRAM and MRAM are suitable for embedded memory and main memory, and PRAM and ReRAM are promising candidatesfor main memory and mass-storage memory for multimedia. Furthermore, the feasibility study of aggressiveultra-low-cost high-speed universal non-volatile semiconductor memory has...

Solution-processed flexible NiO resistive random access memory device

Science.gov (United States)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

ZnO as dielectric for optically transparent non-volatile memory

International Nuclear Information System (INIS)

Salim, N. Tjitra; Aw, K.C.; Gao, W.; Wright, Bryon E.

2009-01-01

This paper discusses the application of a DC sputtered ZnO thin film as a dielectric in an optically transparent non-volatile memory. The main motivation for using ZnO as a dielectric is due to its optical transparency and mechanical flexibility. We have established the relationship between the electrical resistivity (ρ) and the activation energy (E a ) of the electron transport in the conduction band of the ZnO film. The ρ of 2 x 10 4 -5 x 10 7 Ω-cm corresponds to E a of 0.36-0.76 eV, respectively. The k-value and optical band-gap for films sputtered with Ar:O 2 ratio of 4:1 are 53 ± 3.6 and 3.23 eV, respectively. In this paper, the basic charge storage element for a non-volatile memory is a triple layer dielectric structure in which a 50 nm thick ZnO film is sandwiched between two layers of methyl silsesquioxane sol-gel dielectric of varying thickness. A pronounced clockwise capacitance-voltage (C-V) hysteresis was observed with a memory window of 6 V. The integration with a solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene resulted in an optically transparent organic field effect transistor non-volatile memory (OFET-NVM). We have demonstrated that this OFET-NVM can be electrically programmed and erased at low voltage (± 10 V) with a threshold voltage shift of 4.0 V.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

International Nuclear Information System (INIS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-01-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

Energy Technology Data Exchange (ETDEWEB)

Jovanović, B., E-mail: bojan.jovanovic@lirmm.fr, E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L. [LIRMM—University of Montpellier 2/UMR CNRS 5506, 161 Rue Ada, 34095 Montpellier (France)

2014-04-07

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Three-terminal resistive switching memory in a transparent vertical-configuration device

International Nuclear Information System (INIS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies

Soluble dendrimers europium(III) β-diketonate complex for organic memory devices

International Nuclear Information System (INIS)

Wang Binbin; Fang Junfeng; Li Bin; You Han; Ma Dongge; Hong Ziruo; Li Wenlian; Su Zhongmin

2008-01-01

We report the synthesis of a soluble dendrimers europium(III) complex, tris(dibenzoylmethanato)(1,3,5-tris[2-(2'-pyridyl) benzimidazoly]methylbenzene)-europium(III), and its application in organic electrical bistable memory device. Excellent stability that ensured more than 10 6 write-read-erase-reread cycles has been performed in ambient conditions without current-induced degradation. High-density, low-cost memory, good film-firming property, fascinating thermal and morphological stability allow the application of the dendrimers europium(III) complex as an active medium in non-volatile memory devices

A graphene integrated highly transparent resistive switching memory device

Science.gov (United States)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Dependence of the organic nonvolatile memory performance on the location of ultra-thin Ag film

International Nuclear Information System (INIS)

Jiao Bo; Wu Zhaoxin; He Qiang; Mao Guilin; Hou Xun; Tian Yuan

2010-01-01

We demonstrated organic nonvolatile memory devices based on 4,4',4''-tris[N-(3-methylphenyl)-N-phenylamino] triphenylamine (m-MTDATA) inserted by an ultra-thin Ag film. The memory devices with different locations of ultra-thin Ag film in m-MTDATA were investigated, and it was found that the location of the Ag film could affect the performance of the organic memory, such as ON/OFF ratio, retention time and cycling endurance. When the Ag film was located at the ITO/m-MTDATA interface, the largest ON/OFF ratio (about 10 5 ) could be achieved, but the cycling endurance was poor. When the Ag film was located in the middle region of the m-MTDATA layer, the ON/OFF ratios came down by about 10 3 , but better performance of cycling endurance was exhibited. When the Ag film was located close to the Al electrode, the ON/OFF ratios and the retention time of this device decreased sharply and the bistable phenomenon almost disappeared. Our works show a simple approach to improve the performance of organic memory by adjusting the location of the metal film.

Laser Nanosoldering of Golden and Magnetite Particles and its Possible Application in 3D Printing Devices and Four-Valued Non-Volatile Memories

Directory of Open Access Journals (Sweden)

Jaworski Jacek

2015-12-01

Full Text Available In recent years the 3D printing methods have been developing rapidly. This article presents researches about a new composite consisted of golden and magnetite nanoparticles which could be used for this technique. Preparation of golden nanoparticles by laser ablation and their soldering by laser green light irradiation proceeded in water environment. Magnetite was obtained on chemical way. During experiments it was tested a change of a size of nanoparticles during laser irradiation, surface plasmon resonance, zeta potential. The obtained golden - magnetite composite material was magnetic after laser irradiation. On the end there was considered the application it for 3D printing devices, water filters and four-valued non-volatile memories.

High-Speed Non-Volatile Optical Memory: Achievements and Challenges

Directory of Open Access Journals (Sweden)

Vadym Zayets

2017-01-01

Full Text Available We have proposed, fabricated, and studied a new design of a high-speed optical non-volatile memory. The recoding mechanism of the proposed memory utilizes a magnetization reversal of a nanomagnet by a spin-polarized photocurrent. It was shown experimentally that the operational speed of this memory may be extremely fast above 1 TBit/s. The challenges to realize both a high-speed recording and a high-speed reading are discussed. The memory is compact, integratable, and compatible with present semiconductor technology. If realized, it will advance data processing and computing technology towards a faster operation speed.

Fabrication of Nonvolatile Memory Effects in High-k Dielectric Thin Films Using Electron Irradiation

International Nuclear Information System (INIS)

Park, Chanrock; Cho, Daehee; Kim, Jeongeun; Hwang, Jinha

2010-01-01

Electron Irradiation can be applied towards nano-floating gate memories which are recognized as one of the next-generation nonvolatile memory semiconductors. NFGMs can overcome the preexisting limitations encountered in Dynamic Random Access Memories and Flash memories with the excellent advantages, i. e. high-density information storage, high response speed, high compactness, etc. The traditional nano-floating gate memories are fabricated through multi-layered nano structures of the dissimilar materials where the charge-trapping portions are sandwiched into the high-k dielectrics. However, this work reports the unique nonvolatile responses in single-layered high-k dielectric thin films if irradiated with highly accelerated electron beams. The implications of the electron irradiation will be discussed towards high-performance nano-floating gate memories

A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

International Nuclear Information System (INIS)

Wu, Ming-Chi; Tseng, Tseung-Yuen; Jang, Wen-Yueh; Lin, Chen-Hsi

2012-01-01

Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO 2 /Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO 2 /Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO 2 -based RRAM is a prospective alternative for nonvolatile multilevel memory device applications. (paper)

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

Science.gov (United States)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Crested Tunnel Barriers for Fast, Scalable, Nonvolatile Semiconductor Memories (Theme 3)

National Research Council Canada - National Science Library

Likharev, Konstantin K; Ma, Tso-Ping

2006-01-01

.... If demonstrated in silicon-compatible materials with sufficient endurance under electric stress, this effect may enable high-density, high-speed nonvolatile memories that may potentially replace DRAM...

Origami-based tunable truss structures for non-volatile mechanical memory operation.

Science.gov (United States)

Yasuda, Hiromi; Tachi, Tomohiro; Lee, Mia; Yang, Jinkyu

2017-10-17

Origami has recently received significant interest from the scientific community as a method for designing building blocks to construct metamaterials. However, the primary focus has been placed on their kinematic applications by leveraging the compactness and auxeticity of planar origami platforms. Here, we present volumetric origami cells-specifically triangulated cylindrical origami (TCO)-with tunable stability and stiffness, and demonstrate their feasibility as non-volatile mechanical memory storage devices. We show that a pair of TCO cells can develop a double-well potential to store bit information. What makes this origami-based approach more appealing is the realization of two-bit mechanical memory, in which two pairs of TCO cells are interconnected and one pair acts as a control for the other pair. By assembling TCO-based truss structures, we experimentally verify the tunable nature of the TCO units and demonstrate the operation of purely mechanical one- and two-bit memory storage prototypes.Origami is a popular method to design building blocks for mechanical metamaterials. Here, the authors assemble a volumetric origami-based structure, predict its axial and rotational movements during folding, and demonstrate the operation of mechanical one- and two-bit memory storage.

Bulk heterojunction polymer memory devices with reduced graphene oxide as electrodes.

Science.gov (United States)

Liu, Juqing; Yin, Zongyou; Cao, Xiehong; Zhao, Fei; Lin, Anping; Xie, Linghai; Fan, Quli; Boey, Freddy; Zhang, Hua; Huang, Wei

2010-07-27

A unique device structure with a configuration of reduced graphene oxide (rGO) /P3HT:PCBM/Al has been designed for the polymer nonvolatile memory device. The current-voltage (I-V) characteristics of the fabricated device showed the electrical bistability with a write-once-read-many-times (WORM) memory effect. The memory device exhibits a high ON/OFF ratio (10(4)-10(5)) and low switching threshold voltage (0.5-1.2 V), which are dependent on the sheet resistance of rGO electrode. Our experimental results confirm that the carrier transport mechanisms in the OFF and ON states are dominated by the thermionic emission current and ohmic current, respectively. The polarization of PCBM domains and the localized internal electrical field formed among the adjacent domains are proposed to explain the electrical transition of the memory device.

Radiation-hardened nonvolatile MNOS RAM

International Nuclear Information System (INIS)

Wrobel, T.F.; Dodson, W.H.; Hash, G.L.; Jones, R.V.; Nasby, R.D.; Olson, R.J.

1983-01-01

A radiation hardened nonvolatile MNOS RAM is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s

Design considerations for a radiation hardened nonvolatile memory

International Nuclear Information System (INIS)

Murray, J.R.

1993-01-01

Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

International Nuclear Information System (INIS)

Nedic, Stanko; Welland, Mark; Tea Chun, Young; Chu, Daping; Hong, Woong-Ki

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10 5 , a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10 4 s

Evaluation of Recent Technologies of Nonvolatile RAM

Science.gov (United States)

Nuns, Thierry; Duzellier, Sophie; Bertrand, Jean; Hubert, Guillaume; Pouget, Vincent; Darracq, FrÉdÉric; David, Jean-Pierre; Soonckindt, Sabine

2008-08-01

Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices.

Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

International Nuclear Information System (INIS)

Gelinck, Gerwin H; Cobb, Brian; Van Breemen, Albert J J M; Myny, Kris

2015-01-01

Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these. (paper)

Fabrication of Pb (Zr, Ti) O3 Thin Film for Non-Volatile Memory Device Application

International Nuclear Information System (INIS)

Mar Lar Win

2011-12-01

Ferroelectric lead zirconate titanate powder was composed of mainly the oxides of titanium, zirconium and lead. PZT powder was firstly prepared by thermal synthesis at different Zr/Ti ratios with various sintering temperatures. PZT thin film was fabricated on SiO2/Si substrate by using thermal evaporation method. Physical and elemental analysis were carried out by using SEM, EDX and XRD The ferroelectric properties and the switching behaviour of the PZT thin films were investigated. The ferroelectric properties and switching properties of the PZT thin film (near morphotropic phase boundary sintered at 800 C) could function as a nonvolatile memory.

Use of non-volatile memories for SSC detector readout

International Nuclear Information System (INIS)

Fennelly, A.J.; Woosley, J.K.; Johnson, M.B.

1990-01-01

Use of non-volatile memory units at the end of each fiber optic bunch/strand would substantially increase information available from experiments by providing a complete event history, in addition to easing real time processing requirements. This may be an alternative to enhancing technology to optical computing techniques. Available and low-risk projected technologies will be surveyed, with costing addressed. Some discussion will be given to covnersion of optical signals, to electronic information, concepts for providing timing pulses to the memory units, and to the magnetoresistive (MRAM) and ferroelectric (FERAM) random access memory technologies that may be utilized in the prototype system

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

Science.gov (United States)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

Science.gov (United States)

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

Science.gov (United States)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

International Nuclear Information System (INIS)

Avila-Nino, J.A.; Segura-Cardenas, E.; Sustaita, A.O.; Cruz-Cruz, I.; Lopez-Sandoval, R.; Reyes-Reyes, M.

2011-01-01

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

Energy Technology Data Exchange (ETDEWEB)

Avila-Nino, J.A.; Segura-Cardenas, E. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Sustaita, A.O. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Cruz-Cruz, I. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Lopez-Sandoval, R. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Reyes-Reyes, M., E-mail: reyesm@iico.uaslp.mx [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico)

2011-03-25

We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

Conjugated donor-acceptor-acceptor (D-A-A) molecule for organic nonvolatile resistor memory.

Science.gov (United States)

Dong, Lei; Li, Guangwu; Yu, An-Dih; Bo, Zhishan; Liu, Cheng-Liang; Chen, Wen-Chang

2014-12-01

A new donor-acceptor-acceptor (D-A-A) type of conjugated molecule, N-(4-(N',N'-diphenyl)phenylamine)-4-(4'-(2,2-dicyanovinyl)phenyl) naphthalene-1,8-dicarboxylic monoimide (TPA-NI-DCN), consisting of triphenylamine (TPA) donors and naphthalimide (NI)/dicyanovinylene (DCN) acceptors was synthesized and characterized. In conjunction with previously reported D-A based materials, the additional DCN moiety attached as end group in the D-A-A configuration can result in a stable charge transfer (CT) and charge-separated state to maintain the ON state current. The vacuum-deposited TPA-NI-DCN device fabricated as an active memory layer was demonstrated to exhibit write-once-read-many (WORM) switching characteristics of organic nonvolatile memory due to the strong polarity of the TPA-NI-DCN moiety. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

Science.gov (United States)

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

All-polymer bistable resistive memory device based on nanoscale phase-separated PCBM-ferroelectric blends

KAUST Repository

Khan, Yasser; Bhansali, Unnat Sampatraj; Cha, Dong Kyu; Alshareef, Husam N.

2012-01-01

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride-trifluoroethylene (P(VDF-TrFE)) and n-type semiconducting [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The nanoscale phase

Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate

International Nuclear Information System (INIS)

Cho, Seongjae; Shim, Wonbo; Park, Ilhan; Kim, Yoon; Park, Byunggook

2010-01-01

In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.

New memory devices based on the proton transfer process

Science.gov (United States)

Wierzbowska, Małgorzata

2016-01-01

Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices.

Nonvolatile Memory Elements Based on the Intercalation of Organic Molecules Inside Carbon Nanotubes

Science.gov (United States)

Meunier, Vincent; Kalinin, Sergei V.; Sumpter, Bobby G.

2007-02-01

We propose a novel class of nonvolatile memory elements based on the modification of the transport properties of a conducting carbon nanotube by the presence of an encapsulated molecule. The guest molecule has two stable orientational positions relative to the nanotube that correspond to conducting and nonconducting states. The mechanism, governed by a local gating effect of the molecule on the electronic properties of the nanotube host, is studied using density functional theory. The mechanisms of reversible reading and writing of information are illustrated with a F4TCNQ molecule encapsulated inside a metallic carbon nanotube. Our results suggest that this new type of nonvolatile memory element is robust, fatigue-free, and can operate at room temperature.

Highly Stretchable Non-volatile Nylon Thread Memory

Science.gov (United States)

Kang, Ting-Kuo

2016-04-01

Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

Science.gov (United States)

Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

2015-09-01

Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

Science.gov (United States)

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

A study on carbon nanotube bridge as a electromechanical memory device

Science.gov (United States)

Kang, Jeong Won; Ha Lee, Jun; Joo Lee, Hoong; Hwang, Ho Jung

2005-04-01

A nanoelectromechanical (NEM) nanotube random access memory (NRAM) device based on carbon nanotube (CNT) was investigated using atomistic simulations. For the CNT-based NEM memory, the mechanical properties of the CNT-bridge and van der Waals interactions between the CNT-bridge and substrate were very important. The critical amplitude of the CNT-bridge was 16% of the length of the CNT-bridge. As molecular dynamics time increased, the CNT-bridge went to the steady state under the electrostatic force with the damping of the potential and the kinetic energies of the CNT-bridge. The interatomic interaction between the CNT-bridge and substrate, value of the CNT-bridge slack, and damping rate of the CNT-bridge were very important for the operation of the NEM memory device as a nonvolatile memory.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso; Khan, M. A.; Alshareef, Husam N.

2014-01-01

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

KAUST Repository

Caraveo-Frescas, Jesus Alfonso

2014-06-10

Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm 2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Science.gov (United States)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Hybrid superconducting-magnetic memory device using competing order parameters.

Science.gov (United States)

Baek, Burm; Rippard, William H; Benz, Samuel P; Russek, Stephen E; Dresselhaus, Paul D

2014-05-28

In a hybrid superconducting-magnetic device, two order parameters compete, with one type of order suppressing the other. Recent interest in ultra-low-power, high-density cryogenic memories has spurred new efforts to simultaneously exploit superconducting and magnetic properties so as to create novel switching elements having these two competing orders. Here we describe a reconfigurable two-layer magnetic spin valve integrated within a Josephson junction. Our measurements separate the suppression in the superconducting coupling due to the exchange field in the magnetic layers, which causes depairing of the supercurrent, from the suppression due to the stray magnetic field. The exchange field suppression of the superconducting order parameter is a tunable and switchable behaviour that is also scalable to nanometer device dimensions. These devices demonstrate non-volatile, size-independent switching of Josephson coupling, in magnitude as well as phase, and they may enable practical nanoscale superconducting memory devices.

New memory devices based on the proton transfer process

International Nuclear Information System (INIS)

Wierzbowska, Małgorzata

2016-01-01

Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing  information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices. (paper)

Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

Science.gov (United States)

Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

2015-09-01

Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

Nonvolatile Memory Materials for Neuromorphic Intelligent Machines.

Science.gov (United States)

Jeong, Doo Seok; Hwang, Cheol Seong

2018-04-18

Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

2015-03-23

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

International Nuclear Information System (INIS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-01-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

Science.gov (United States)

Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F. Y.; Gao, X. S.; Dai, J. Y.

2015-08-01

Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure.

Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

Science.gov (United States)

Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

2017-12-01

Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

Fabrication and operation methods of a one-time programmable (OTP) nonvolatile memory (NVM) based on a metal-oxide-semiconductor structure

International Nuclear Information System (INIS)

Cho, Seongjae; Lee, Junghoon; Jung, Sunghun; Park, Sehwan; Park, Byunggook

2011-01-01

In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

Status and Prospects of ZnO-Based Resistive Switching Memory Devices

Science.gov (United States)

Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

2016-08-01

In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

WORM memory devices based on conformation change of a PVK derivative with a rigid spacer in side chain

International Nuclear Information System (INIS)

Liu Yuanhua; Li Najun; Xia Xuewei; Xu Qingfeng; Ge Jianfeng; Lu Jianmei

2010-01-01

A nonvolatile write-once-read-many-times (WORM) memory device based on poly((4-vinylbenzyl)-9H-carbazole) (PVCz) was fabricated by a simple and conventional process. The as-fabricated device was found to be at its OFF state and could be programmed irreversibly to the ON state with a low transition voltage of -1.7 V. The device exhibits a high ON/OFF current ratio of up to 10 6 , high stability in retention time up to 8 h and number of read cycles up to 10 8 under a read voltage of -1.0 V in both ON and OFF states. The results of X-ray diffraction (XRD) and fluorescence emission spectra in different states of PVCz indicate that the electrical bistable phenomenon is caused by the voltage-induced conformation change of the pendant carbazole groups. With high performance, low power consumption and low production cost, the device fabricated with PVCz has a potential application for nonvolatile memory.

Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

Science.gov (United States)

Singh, Kirandeep; Kaur, Davinder

2017-02-01

The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

Multistate nonvolatile straintronics controlled by a lateral electric field.

Science.gov (United States)

Iurchuk, V; Doudin, B; Kundys, B

2014-07-23

We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

International Nuclear Information System (INIS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

Energy Technology Data Exchange (ETDEWEB)

Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

2014-01-06

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Bipolar resistive switching in graphene oxide based metal insulator metal structure for non-volatile memory applications

Science.gov (United States)

Singh, Rakesh; Kumar, Ravi; Kumar, Anil; Kashyap, Rajesh; Kumar, Mukesh; Kumar, Dinesh

2018-05-01

Graphene oxide based devices have attracted much attention recently because of their possible application in next generation electronic devices. In this study, bipolar resistive switching characteristics of graphene oxide based metal insulator metal structure were investigated for nonvolatile memories. The graphene oxide was prepared by the conventional Hummer's method and deposited on ITO coated glass by spin-coating technique. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament inside the graphene oxide. The conduction mechanism for low and high resistance states are dominated by two mechanism the ohmic conduction and space charge limited current (SCLC) mechanism, respectively. Atomic Force Microscopy, X-ray diffraction, Cyclic-Voltammetry were conducted to observe the morphology, structure and behavior of the material. The fabricated device with Al/GO/ITO structure exhibited reliable bipolar resistive switching with set & reset voltage of -2.3 V and 3V respectively.

Graphene-quantum-dot nonvolatile charge-trap flash memories

International Nuclear Information System (INIS)

Sin Joo, Soong; Kim, Jungkil; Seok Kang, Soo; Kim, Sung; Choi, Suk-Ho; Won Hwang, Sung

2014-01-01

Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO 2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO 2 on a p-type wafer, spin-coating of GQDs on the SiO 2 layer, and IBSD of 20 nm SiO 2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO 2 /Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance–voltage curves is proportional to d for sweep voltages wider than  ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of  ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement. (papers)

A room-temperature non-volatile CNT-based molecular memory cell

Science.gov (United States)

Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

2013-04-01

Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

Multistate nonvolatile straintronics controlled by a lateral electric field

International Nuclear Information System (INIS)

Iurchuk, V; Doudin, B; Kundys, B

2014-01-01

We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications. (fast track communication)

Organic ferroelectric opto-electronic memories

NARCIS (Netherlands)

Asadi, K.; Li, M.; Blom, P.W.M.; Kemerink, M.; Leeuw, D.M. de

2011-01-01

Memory is a prerequisite for many electronic devices. Organic non-volatile memory devices based on ferroelectricity are a promising approach towards the development of a low-cost memory technology based on a simple cross-bar array. In this review article we discuss the latest developments in this

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

Energy Technology Data Exchange (ETDEWEB)

Mudge, Trevor [Univ. of Michigan, Ann Arbor, MI (United States)

2017-12-15

This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience, and energy efficiency in Exascale systems. Capacity and energy are the key drivers.

Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

Science.gov (United States)

Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

2015-03-14

The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels.

Nonvolatile flexible organic bistable devices fabricated utilizing CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole polymer layer

International Nuclear Information System (INIS)

Son, Dong-Ick; Kim, Ji-Hwan; Park, Dong-Hee; Choi, Won Kook; Li, Fushan; Ham, Jung Hun; Kim, Tae Whan

2008-01-01

The bistable effects of CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole (PVK) polymer layer by using flexible poly-vinylidene difluoride (PVDF) and polyethylene terephthalate (PET) substrates were investigated. Transmission electron microscopy (TEM) images revealed that CdSe/ZnS nanoparticles were formed inside the PVK polymer layer. Current-voltage (I-V) measurement on the Al/[CdSe/ZnS nanoparticles+ PVK]/ITO/PVDF and Al/[CdSe/ZnS nanoparticles+ PVK ]/ITO/PET structures at 300 K showed a nonvolatile electrical bistability behavior with a flat-band voltage shift due to the existence of the CdSe/ZnS nanoparticles, indicative of trapping, storing and emission of charges in the electronic states of the CdSe nanoparticles. A bistable behavior for the fabricated organic bistable device (OBD) structures is described on the basis of the I-V results. These results indicate that OBDs fabricated by embedding inorganic CdSe/ZnS nanoparticles in a conducting polymer matrix on flexible substrates are prospects for potential applications in flexible nonvolatile flash memory devices

Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

Science.gov (United States)

Jin, Zhiwen; Liu, Guo; Wang, Jizheng

2013-05-01

Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

Science.gov (United States)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Integration of ammonia-plasma-functionalized graphene nanodiscs as charge trapping centers for nonvolatile memory applications

KAUST Repository

Wang, Jer-Chyi

2016-11-23

Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated in this study. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 1011 cm−2 and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates Nsingle bondH+ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the memory window becomes more than 2.4 V and remains stable after 104 operating cycles. The charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

Science.gov (United States)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Four-state non-volatile memory in a multiferroic spin filter tunnel junction

Science.gov (United States)

Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

2016-12-01

We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al2O3 film as the tunnel and blocking oxides for nonvolatile memory applications

International Nuclear Information System (INIS)

Lee, Jaesang; Kim, Hyungchul; Park, Taeyong; Ko, Youngbin; Ryu, Jaehun; Jeon, Heeyoung; Park, Jingyu; Jeon, Hyeongtag

2012-01-01

Remote plasma atomic layer deposited (RPALD) Al 2 O 3 films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al 2 O 3 film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si +3 and Si +4 , indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/-10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 10 4 s. These results indicate that Al 2 O 3 films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

Non-volatile nano-floating gate memory with Pt-Fe{sub 2}O{sub 3} composite nanoparticles and indium gallium zinc oxide channel

Energy Technology Data Exchange (ETDEWEB)

Hu, Quanli [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Lee, Seung Chang; Baek, Yoon-Jae [Myongji University, Department of Materials Science and Engineering (Korea, Republic of); Lee, Hyun Ho [Myongji University, Department of Chemical Engineering (Korea, Republic of); Kang, Chi Jung [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Kim, Hyun-Mi; Kim, Ki-Bum [Seoul National University, Department of Materials Science and Engineering (Korea, Republic of); Yoon, Tae-Sik, E-mail: tsyoon@mju.ac.kr [Myongji University, Department of Nano Science and Engineering (Korea, Republic of)

2013-02-15

Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe{sub 2}O{sub 3} composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe{sub 2}O{sub 3} nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of {approx}3 Multiplication-Sign 10{sup 11} cm{sup -2} by a solution-based dip-coating process. The Pt core ({approx}3 nm in diameter) and Fe{sub 2}O{sub 3}-shell ({approx}6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of {approx}4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of {approx}0.66 V after pulse programming at +20 V for 1 s with retention > {approx}65 % after 10{sup 4} s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

Science.gov (United States)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

Science.gov (United States)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

In-chip optical CD measurements for non-volatile memory devices

Science.gov (United States)

Vasconi, Mauro; Kremer, Stephanie; Polli, M.; Severgnini, Ermes; Trovati, Silvia S.

2006-03-01

A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

Directory of Open Access Journals (Sweden)

Sparsh Mittal

2017-02-01

Full Text Available Non-volatile memories (NVMs offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory and STT-RAM (spin transfer torque RAM. We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

Preparation of NiFe binary alloy nanocrystals for nonvolatile memory applications

Institute of Scientific and Technical Information of China (English)

无

2010-01-01

In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theoretically.A nanocrystal floating gate structure with NiFe nanocrystals embedded in SiO2 dielectric layers was fabricated by magnetron sputtering.The micro-structure and composition deviation of the prepared NiFe nanocrystals were also investigated by TEM and EDS.

Non-volatile resistive switching in the Mott insulator (V1-xCrx)2O3

Science.gov (United States)

Querré, M.; Tranchant, J.; Corraze, B.; Cordier, S.; Bouquet, V.; Députier, S.; Guilloux-Viry, M.; Besland, M.-P.; Janod, E.; Cario, L.

2018-05-01

The discovery of non-volatile resistive switching in Mott insulators related to an electric-field-induced insulator to metal transition (IMT) has paved the way for their use in a new type of non-volatile memories, the Mott memories. While most of the previous studies were dedicated to uncover the resistive switching mechanism and explore the memory potential of chalcogenide Mott insulators, we present here a comprehensive study of resistive switching in the canonical oxide Mott insulator (V1-xCrx)2O3. Our work demonstrates that this compound undergoes a non-volatile resistive switching under electric field. This resistive switching is induced by a Mott transition at the local scale which creates metallic domains closely related to existing phases of the temperature-pressure phase diagram of (V1-xCrx)2O3. Our work demonstrates also reversible resistive switching in (V1-xCrx)2O3 crystals and thin film devices. Preliminary performances obtained on 880 nm thick layers with 500 nm electrodes show the strong potential of Mott memories based on the Mott insulator (V1-xCrx)2O3.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

Science.gov (United States)

Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

2017-03-01

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

Science.gov (United States)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

KAUST Repository

Nayak, Pradipta K.

2012-06-22

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin filmtransistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectrictransistors, which is very promising for low-power non-volatile memory applications.

Device and methods for writing and erasing analog information in small memory units via voltage pulses

Science.gov (United States)

El Gabaly Marquez, Farid; Talin, Albert Alec

2018-04-17

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

Science.gov (United States)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

Review of radiation effects on ReRAM devices and technology

Science.gov (United States)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction

International Nuclear Information System (INIS)

Karimov, Khasan S.; Muqeet Rehman, M.; Zameer Abbas, S.; Ahmad, Zubair; Touati, Farid; Mahroof-Tahir, M.

2015-01-01

A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H 2 Pc are fabricated by vacuum deposition of the CuPc and H 2 Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30–40 μm. For the current–voltage (I–V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120–150. Under the switching condition, the electric current increases ∼ 80–100 times. A comparison between the forward and reverse I–V characteristics shows the presence of rectifying behavior. (paper)

Novel Organic Phototransistor-Based Nonvolatile Memory Integrated with UV-Sensing/Green-Emissive Aggregation Enhanced Emission (AEE)-Active Aromatic Polyamide Electret Layer.

Science.gov (United States)

Cheng, Shun-Wen; Han, Ting; Huang, Teng-Yung; Chang Chien, Yu-Hsin; Liu, Cheng-Liang; Tang, Ben Zhong; Liou, Guey-Sheng

2018-05-30

A novel aggregation enhanced emission (AEE)-active polyamide TPA-CN-TPE with a high photoluminesence characteristic was successfully synthesized by the direct polymerization of 4-cyanotriphenyl diamine (TPA-CN) and tetraphenylethene (TPE)-containing dicarboxylic acid. The obtained luminescent polyamide plays a significant role as the polymer electret layer in organic field-effect transistors (OFETs)-type memory. The strong green emission of TPA-CN-TPE under ultraviolet (UV) irradiation can be directly absorbed by the pentacene channel, displaying a light-induced programming and voltage-driven erasing organic phototransistor-based nonvolatile memory. Memory window can be effectively manipulated between the programming and erasing states by applying UV light illumination and electrical field, respectively. The photoinduced memory behavior can be maintained for over 10 4 s between these two states with an on/off ratio of 10 4 , and the memory switching can be steadily operated for many cycles. With high photoresponsivity ( R) and photosensitivity ( S), this organic phototransistor integrated with AEE-active polyamide electret layer could serve as an excellent candidate for UV photodetectors in optical applications. For comparison, an AEE-inactive aromatic polyimide TPA-PIS electret with much weaker solid-state emission was also applied in the same OFETs device architecture, but this device did not show any UV-sensitive and UV-induced memory characteristics, which further confirmed the significance of the light-emitting capability of the electret layer.

Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

Energy Technology Data Exchange (ETDEWEB)

Shinde, Sachin M.; Tanemura, Masaki [Department of Frontier Materials, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan); Kalita, Golap, E-mail: kalita.golap@nitech.ac.jp [Department of Frontier Materials, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan); Center for Fostering Young and Innovative Researchers, Nagoya Institute of Technology, Gokiso-cho, Showa-ku, Nagoya 466-8555 (Japan)

2014-12-07

Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

KAUST Repository

Wu, S.

2013-12-12

Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures, where the conducting layer near the LaAlO3/SrTiO3 interface serves as the "unconventional"bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO3/SrTiO3 interface and the creation of defect-induced gap states within the ultrathin LaAlO3 layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

Science.gov (United States)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

International Nuclear Information System (INIS)

Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

2015-01-01

Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10 17  m −2 . We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching

Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

Science.gov (United States)

Huh, In; Cheon, Woo Young; Choi, Woo Young

2016-04-01

A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

Non-volatile main memory management methods based on a file system.

Science.gov (United States)

Oikawa, Shuichi

2014-01-01

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

Effect of AlN layer on the bipolar resistive switching behavior in TiN thin film based ReRAM device for non-volatile memory application

Science.gov (United States)

Prakash, Ravi; Kaur, Davinder

2018-05-01

The effect of an additional AlN layer in the Cu/TiN/AlN/Pt stack configuration deposited using sputtering has been investigated. The Cu/TiN/AlN/Pt device shows a tristate resistive switching. Multilevel switching is facilitated by ionic and metallic filament formation, and the nature of the filaments formed is confirmed by performing a resistance vs. temperature measurement. Ohmic behaviour and trap controlled space charge limited current (SCLC) conduction mechanisms are confirmed as dominant conduction mechanism at low resistance state (LRS) and high resistance state (HRS). High resistance ratio (102) corresponding to HRS and LRS, good write/erase endurance (105) and non-volatile long retention (105s) are also observed. Higher thermal conductivity of the AlN layer is the main reasons for the enhancement of resistive switching performance in Cu/TiN/AlN/Pt cell. The above result suggests the feasibility of Cu/TiN/AlN/Pt devices for multilevel nonvolatile ReRAM application.

Next generation spin torque memories

CERN Document Server

Kaushik, Brajesh Kumar; Kulkarni, Anant Aravind; Prajapati, Sanjay

2017-01-01

This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality.

Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

Science.gov (United States)

Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

2016-02-24

Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nonvolatile Resistive Switching in Pt/LaAlO_{3}/SrTiO_{3} Heterostructures

Directory of Open Access Journals (Sweden)

Shuxiang Wu

2013-12-01

Full Text Available Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO_{3}/SrTiO_{3} heterostructures, where the conducting layer near the LaAlO_{3}/SrTiO_{3} interface serves as the “unconventional” bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO_{3}/SrTiO_{3} interface and the creation of defect-induced gap states within the ultrathin LaAlO_{3} layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

Atomic crystals resistive switching memory

International Nuclear Information System (INIS)

Liu Chunsen; Zhang David Wei; Zhou Peng

2017-01-01

Facing the growing data storage and computing demands, a high accessing speed memory with low power and non-volatile character is urgently needed. Resistive access random memory with 4F 2 cell size, switching in sub-nanosecond, cycling endurances of over 10 12 cycles, and information retention exceeding 10 years, is considered as promising next-generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory. (topical reviews)

Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

Science.gov (United States)

Erlbacher, T.; Huerner, A.; Bauer, A. J.; Frey, L.

2012-09-01

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

Transparent and flexible write-once-read-many (WORM) memory device based on egg albumen

International Nuclear Information System (INIS)

Qu, Bo; Lin, Qianru; Wan, Tao; Du, Haiwei; Chen, Nan; Lin, Xi; Chu, Dewei

2017-01-01

Egg albumen, as an important protein resource in nature, is an interesting dielectric material exhibiting many fascinating properties for the development of environmentally friendly electronic devices. Taking advantage of their extraordinary transparency and flexibility, this paper presents an innovative preparation approach for albumen thin film based write-once-read-many-times (WORM) memory devices in a simple, cost-effective manner. The fabricated device shows superior data retention properties including non-volatile character (over 10 5 s) and promising great read durability (10 6 times). Furthermore, our results suggested that the electric-field-induced trap-controlled space charge limited current (SCLC) conduction is responsible for the observed resistance switching effect. The present study may likely reveal another pathway towards complete see-through electrical devices. (paper)

Transparent and flexible write-once-read-many (WORM) memory device based on egg albumen

Science.gov (United States)

Qu, Bo; Lin, Qianru; Wan, Tao; Du, Haiwei; Chen, Nan; Lin, Xi; Chu, Dewei

2017-08-01

Egg albumen, as an important protein resource in nature, is an interesting dielectric material exhibiting many fascinating properties for the development of environmentally friendly electronic devices. Taking advantage of their extraordinary transparency and flexibility, this paper presents an innovative preparation approach for albumen thin film based write-once-read-many-times (WORM) memory devices in a simple, cost-effective manner. The fabricated device shows superior data retention properties including non-volatile character (over 105 s) and promising great read durability (106 times). Furthermore, our results suggested that the electric-field-induced trap-controlled space charge limited current (SCLC) conduction is responsible for the observed resistance switching effect. The present study may likely reveal another pathway towards complete see-through electrical devices.

Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for nonvolatile memories

International Nuclear Information System (INIS)

Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

2013-01-01

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO 2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories

Comparison of discrete-storage nonvolatile memories: advantage of hybrid method for fabrication of Au nanocrystal nonvolatile memory

International Nuclear Information System (INIS)

Wang Qin; Jia Rui; Guan Weihua; Li Weilong; Liu Qi; Hu Yuan; Long Shibing; Chen Baoqin; Liu Ming; Ye Tianchun; Lu Wensheng; Jiang Long

2008-01-01

In this paper, the memory characteristics of two kinds of metal-oxide-semiconductor (MOS) capacitors embedded with Au nanocrytals are investigated: hybrid MOS with nanocrystals (NCs) fabricated by chemical syntheses and rapid thermal annealing (RTA) MOS with NCs fabricated by RTA. For both kinds of devices, the capacitance versus voltage (C-V) curves clearly indicate the charge storage in the NCs. The hybrid MOS, however, shows a larger memory window, as compared with RTA MOS. The retention characteristics of the two MOS devices are also investigated. The capacitance versus time (C-t) measurement shows that the hybrid MOS capacitor embedded with Au nanocrystals has a longer retention time. The mechanism of longer retention time for hybrid MOS capacitor is qualitatively discussed

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

A study of selenium nanoparticles as charge storage element for flexible semi-transparent memory devices

Science.gov (United States)

Alotaibi, Sattam; Nama Manjunatha, Krishna; Paul, Shashi

2017-12-01

Flexible Semi-Transparent electronic memory would be useful in coming years for integrated flexible transparent electronic devices. However, attaining such flexibility and semi-transparency leads to the boundaries in material composition. Thus, impeding processing speed and device performance. In this work, we present the use of inorganic stable selenium nanoparticles (Se-NPs) as a storage element and hydrogenated amorphous carbon (a-C:H) as an insulating layer in two terminal non-volatile physically flexible and semi-transparent capacitive memory devices (2T-NMDs). Furthermore, a-C:H films can be deposited at very low temperature (industrial technique called Plasma Enhanced Chemical Vapour Deposition (PECVD) which is available in many existing fabrication labs. Self-assembled Se-NPs has several unique features including deposition at room temperature by simple vacuum thermal evaporation process without the need for further optimisation. This facilitates the fabrication of memory on a flexible substrate. Moreover, the memory behaviour of the Se-NPs was found to be more distinct than those of the semiconductor and metal nanostructures due to higher work function compared to the commonly used semiconductor and metal species. The memory behaviour was observed from the hysteresis of current-voltage (I-V) measurements while the two distinguishable electrical conductivity states (;0; and "1") were studied by current-time (I-t) measurements.

Atomically Smooth Epitaxial Ferroelectric Thin Films for the Development of a Nonvolatile, Ultrahigh Density, Fast, Low Voltage, Radiation-Hard Memory

National Research Council Canada - National Science Library

Ahn, Charles H

2006-01-01

The goal of this research is to fabricate atomically smooth, single crystalline, complex oxide thin film nanostructures for use in a nonvolatile, ultrahigh density, fast, low voltage, radiation-hard memory...

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

Science.gov (United States)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse Cedex 04 (France); Spiegel, Y.; Torregrosa, F. [IBS, Rue G Imbert Prolongée, ZI Peynier-Rousset, 13790 Peynier (France); Normand, P.; Dimitrakis, P.; Kapetanakis, E. [NCSRD, Terma Patriarchou Gregoriou, 15310 Aghia Paraskevi (Greece); Sahu, B. S.; Slaoui, A. [ICube, 23 Rue du Loess, 67037 Strasbourg Cedex 2 (France)

2013-12-16

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

Science.gov (United States)

Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

2014-09-01

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

Energy Technology Data Exchange (ETDEWEB)

De, Arup [Univ. of California, San Diego, CA (United States)

2014-01-01

Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

Phase change memory

CERN Document Server

Qureshi, Moinuddin K

2011-01-01

As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions t

Influence of Thermal Annealing Treatment on Bipolar Switching Properties of Vanadium Oxide Thin-Film Resistance Random-Access Memory Devices

Science.gov (United States)

Chen, Kai-Huang; Cheng, Chien-Min; Kao, Ming-Cheng; Chang, Kuan-Chang; Chang, Ting-Chang; Tsai, Tsung-Ming; Wu, Sean; Su, Feng-Yi

2017-04-01

The bipolar switching properties and electrical conduction mechanism of vanadium oxide thin-film resistive random-access memory (RRAM) devices obtained using a rapid thermal annealing (RTA) process have been investigated in high-resistive status/low-resistive status (HRS/LRS) and are discussed herein. In addition, the resistance switching properties and quality improvement of the vanadium oxide thin-film RRAM devices were measured by x-ray diffraction (XRD) analysis, x-ray photoelectron spectrometry (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM), and current-voltage ( I- V) measurements. The activation energy of the hopping conduction mechanism in the devices was investigated based on Arrhenius plots in HRS and LRS. The hopping conduction distance and activation energy barrier were obtained as 12 nm and 45 meV, respectively. The thermal annealing process is recognized as a candidate method for fabrication of thin-film RRAM devices, being compatible with integrated circuit technology for nonvolatile memory devices.

Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

International Nuclear Information System (INIS)

Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

2009-01-01

Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

Two-dimensional non-volatile programmable p-n junctions

Science.gov (United States)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

KAUST Repository

Ghoneim, Mohamed T.

2015-04-24

A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol-gel coating cycles required (i.e., more cost-effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano-scale due to the larger feature size-to-depth aspect ratio (critical for ultra-high density non-volatile memory applications). Utilizing the inverse proportionality between substrate\\'s thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer-less manufacturable process into a flexible form that matches organic electronics\\' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

Nanoscale memory devices

International Nuclear Information System (INIS)

Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M

2010-01-01

This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO 2 . (topical review)

Application of nanomaterials in two-terminal resistive-switching memory devices

Directory of Open Access Journals (Sweden)

Jianyong Ouyang

2010-05-01

Full Text Available Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs, nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. Dr. Jianyong Ouyang received his bachelor degree from the Tsinghua University in Beijing, China, and MSc from the Institute of Chemistry, Chinese Academy of Science. He received his PhD from the Institute for Molecular

Semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

Science.gov (United States)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

International Nuclear Information System (INIS)

Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

2014-01-01

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm 2 /V s. The unidirectional shift of turn-on voltage (V on ) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V P /V E ) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm 2 /V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V P /V E of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V on shift. As a result, an enlarged memory window of 28.6 V at the V P /V E of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

Observing the amorphous-to-crystalline phase transition in Ge{sub 2}Sb{sub 2}Te{sub 5} non-volatile memory materials from ab initio molecular-dynamics simulations

Energy Technology Data Exchange (ETDEWEB)

Lee, T.H.; Elliott, S.R. [Department of Chemistry, University of Cambridge, Lensfield Road, CB2 1EW Cambridge (United Kingdom)

2012-10-15

Phase-change memory is a promising candidate for the next generation of non-volatile memory devices. This technology utilizes reversible phase transitions between amorphous and crystalline phases of a recording material, and has been successfully used in rewritable optical data storage, revealing its feasibility. In spite of the importance of understanding the nucleation and growth processes that play a critical role in the phase transition, this understanding is still incomplete. Here, we present observations of the early stages of crystallization in Ge{sub 2}Sb{sub 2}Te{sub 5} materials through ab initio molecular-dynamics simulations. Planar structures, including fourfold rings and planes, play an important role in the formation and growth of crystalline clusters in the amorphous matrix. At the same time, vacancies facilitate crystallization by providing space at the glass-crystalline interface for atomic diffusion, which results in fast crystal growth, as observed in simulations and experiments. The microscopic mechanism of crystallization presented here may deepen our understanding of the phase transition occurring in real devices, providing an opportunity to optimize the memory performance of phase-change materials. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

Migration of interfacial oxygen ions modulated resistive switching in oxide-based memory devices

Science.gov (United States)

Chen, C.; Gao, S.; Zeng, F.; Tang, G. S.; Li, S. Z.; Song, C.; Fu, H. D.; Pan, F.

2013-07-01

Oxides-based resistive switching memory induced by oxygen ions migration is attractive for future nonvolatile memories. Numerous works had focused their attentions on the sandwiched oxide materials for depressing the characteristic variations, but the comprehensive studies of the dependence of electrodes on the migration behavior of oxygen ions are overshadowed. Here, we investigated the interaction of various metals (Ni, Co, Al, Ti, Zr, and Hf) with oxygen atoms at the metal/Ta2O5 interface under electric stress and explored the effect of top electrode on the characteristic variations of Ta2O5-based memory device. It is demonstrated that chemically inert electrodes (Ni and Co) lead to the scattering switching characteristics and destructive gas bubbles, while the highly chemically active metals (Hf and Zr) formed a thick and dense interfacial intermediate oxide layer at the metal/Ta2O5 interface, which also degraded the resistive switching behavior. The relatively chemically active metals (Al and Ti) can absorb oxygen ions from the Ta2O5 film and avoid forming the problematic interfacial layer, which is benefit to the formation of oxygen vacancies composed conduction filaments in Ta2O5 film thus exhibit the minimum variations of switching characteristics. The clarification of oxygen ions migration behavior at the interface can lead further optimization of resistive switching performance in Ta2O5-based memory device and guide the rule of electrode selection for other oxide-based resistive switching memories.

The future of memory

Science.gov (United States)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

Science.gov (United States)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

Science.gov (United States)

Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

2016-06-01

We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

KAUST Repository

Wu, S.; Luo, X.; Turner, S.; Peng, H.; Lin, W.; Ding, J.; David, A.; Wang, B.; Van, Tendeloo, G.; Wang, J.; Wu, Tao

2013-01-01

Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures

An ultrafast programmable electrical tester for enabling time-resolved, sub-nanosecond switching dynamics and programming of nanoscale memory devices

Science.gov (United States)

Shukla, Krishna Dayal; Saxena, Nishant; Manivannan, Anbarasu

2017-12-01

Recent advancements in commercialization of high-speed non-volatile electronic memories including phase change memory (PCM) have shown potential not only for advanced data storage but also for novel computing concepts. However, an in-depth understanding on ultrafast electrical switching dynamics is a key challenge for defining the ultimate speed of nanoscale memory devices that demands for an unconventional electrical setup, specifically capable of handling extremely fast electrical pulses. In the present work, an ultrafast programmable electrical tester (PET) setup has been developed exceptionally for unravelling time-resolved electrical switching dynamics and programming characteristics of nanoscale memory devices at the picosecond (ps) time scale. This setup consists of novel high-frequency contact-boards carefully designed to capture extremely fast switching transient characteristics within 200 ± 25 ps using time-resolved current-voltage measurements. All the instruments in the system are synchronized using LabVIEW, which helps to achieve various programming characteristics such as voltage-dependent transient parameters, read/write operations, and endurance test of memory devices systematically using short voltage pulses having pulse parameters varied from 1 ns rise/fall time and 1.5 ns pulse width (full width half maximum). Furthermore, the setup has successfully demonstrated strikingly one order faster switching characteristics of Ag5In5Sb60Te30 (AIST) PCM devices within 250 ps. Hence, this novel electrical setup would be immensely helpful for realizing the ultimate speed limits of various high-speed memory technologies for future computing.

Semiconductor-based, large-area, flexible, electronic devices on {110} oriented substrates

Science.gov (United States)

Goyal, Amit

2014-08-05

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110} textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit

2015-03-24

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

International Nuclear Information System (INIS)

Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Kim, Sowon; Choi, Kyung Hyun

2017-01-01

Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al 2 O 3 ) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications. (paper)

Nanoscale observations of the operational failure for phase-change-type nonvolatile memory devices using Ge2Sb2Te5 chalcogenide thin films

International Nuclear Information System (INIS)

Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Lee, Seung-Yun; Park, Young-Sam; Yu, Byoung-Gon

2007-01-01

In this study, a phase-change memory device was fabricated and the origin of device failure mode was examined using transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). Ge 2 Sb 2 Te 5 (GST) was used as the active phase-change material in the memory device and the active pore size was designed to be 0.5 μm. After the programming signals of more than 2x10 6 cycles were repeatedly applied to the device, the high-resistance memory state (reset) could not be rewritten and the cell resistance was fixed at the low-resistance state (set). Based on TEM and EDS studies, Sb excess and Ge deficiency in the device operating region had a strong effect on device reliability, especially under endurance-demanding conditions. An abnormal segregation and oxidation of Ge also was observed in the region between the device operating and inactive peripheral regions. To guarantee an data endurability of more than 1x10 10 cycles of PRAM, it is very important to develop phase-change materials with more stable compositions and to reduce the current required for programming

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

Science.gov (United States)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Memory properties of a Ge nanoring MOS device fabricated by pulsed laser deposition.

Science.gov (United States)

Ma, Xiying

2008-07-09

The non-volatile charge-storage properties of memory devices with MOS structure based on Ge nanorings have been studied. The two-dimensional Ge nanorings were prepared on a p-Si(100) matrix by means of pulsed laser deposition (PLD) using the droplet technique combined with rapid annealing. Complete planar nanorings with well-defined sharp inner and outer edges were formed via an elastic self-transformation droplet process, which is probably driven by the lateral strain of the Ge/Si layers and the surface tension in the presence of Ar gas. The low leakage current was attributed to the small roughness and the few interface states in the planar Ge nanorings, and also to the effect of Coulomb blockade preventing injection. A significant threshold-voltage shift of 2.5 V was observed when an operating voltage of 8 V was implemented on the device.

Materials and Physics Challenges for Spin Transfer Torque Magnetic Random Access Memories

Energy Technology Data Exchange (ETDEWEB)

Heinonen, O.

2014-10-05

Magnetic random access memories utilizing the spin transfer torque effect for writing information are a strong contender for non-volatile memories scalable to the 20 nm node, and perhaps beyond. I will here examine how these devices behave as the device size is scaled down from 70 nm size to 20 nm. As device sizes go below ~50 nm, the size becomes comparable to intrinsic magnetic length scales and the device behavior does not simply scale with size. This has implications for the device design and puts additional constraints on the materials in the device.

NVL-C: Static Analysis Techniques for Efficient, Correct Programming of Non-Volatile Main Memory Systems

Energy Technology Data Exchange (ETDEWEB)

Lee, Seyong [ORNL; Vetter, Jeffrey S [ORNL

2016-01-01

Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard against a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.

High-performance and low-power rewritable SiOx 1 kbit one diode-one resistor crossbar memory array.

Science.gov (United States)

Wang, Gunuk; Lauchner, Adam C; Lin, Jian; Natelson, Douglas; Palem, Krishna V; Tour, James M

2013-09-14

An entire 1-kilobit crossbar device based upon SiOx resistive memories with integrated diodes has been made. The SiOx -based one diode-one resistor device system has promise to satisfy the prerequisite conditions for next generation non-volatile memory applications. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Field-effect transistor memories based on ferroelectric polymers

Science.gov (United States)

Zhang, Yujia; Wang, Haiyang; Zhang, Lei; Chen, Xiaomeng; Guo, Yu; Sun, Huabin; Li, Yun

2017-11-01

Field-effect transistors based on ferroelectrics have attracted intensive interests, because of their non-volatile data retention, rewritability, and non-destructive read-out. In particular, polymeric materials that possess ferroelectric properties are promising for the fabrications of memory devices with high performance, low cost, and large-area manufacturing, by virtue of their good solubility, low-temperature processability, and good chemical stability. In this review, we discuss the material characteristics of ferroelectric polymers, providing an update on the current development of ferroelectric field-effect transistors (Fe-FETs) in non-volatile memory applications. Program supported partially by the NSFC (Nos. 61574074, 61774080), NSFJS (No. BK20170075), and the Open Partnership Joint Projects of NSFC-JSPS Bilateral Joint Research Projects (No. 61511140098).

{100} or 45.degree.-rotated {100}, semiconductor-based, large-area, flexible, electronic devices

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2012-05-15

Novel articles and methods to fabricate the same resulting in flexible, {100} or 45.degree.-rotated {100} oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

NARCIS (Netherlands)

Cai, R.; Kassa, H.G.; Haouari, R.; Marrani, A.; Geerts, Y.H.; Ruzié, C.; Breemen, A.J.J.M. van; Gelinck, G.H.; Nysten, B.; Hu, Z.; Jonas, A.M.

2016-01-01

Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and

Organic bistable light-emitting devices

Science.gov (United States)

Ma, Liping; Liu, Jie; Pyo, Seungmoon; Yang, Yang

2002-01-01

An organic bistable device, with a unique trilayer structure consisting of organic/metal/organic sandwiched between two outmost metal electrodes, has been invented. [Y. Yang, L. P. Ma, and J. Liu, U.S. Patent Pending, U.S. 01/17206 (2001)]. When the device is biased with voltages beyond a critical value (for example 3 V), the device suddenly switches from a high-impedance state to a low-impedance state, with a difference in injection current of more than 6 orders of magnitude. When the device is switched to the low-impedance state, it remains in that state even when the power is off. (This is called "nonvolatile" phenomenon in memory devices.) The high-impedance state can be recovered by applying a reverse bias; therefore, this bistable device is ideal for memory applications. In order to increase the data read-out rate of this type of memory device, a regular polymer light-emitting diode has been integrated with the organic bistable device, such that it can be read out optically. These features make the organic bistable light-emitting device a promising candidate for several applications, such as digital memories, opto-electronic books, and recordable papers.

Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

Science.gov (United States)

Wang, Jian-Ping

An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

Large non-volatile tuning of magnetism mediated by electric field in Fe–Al/Pb(Mg1/3Nb2/3)O3–PbTiO3 heterostructure

International Nuclear Information System (INIS)

Chen, Zhendong; Gao, Cunxu; Wei, Yanping; Zhang, Peng; Wang, Yutian; Zhang, Chao; Ma, Zhikun

2017-01-01

Electric-field control of magnetism is now an attractive trend to approach a new kind of fast, low-power-cost memory device. In this work, we report a strong non-volatile electric control of magnetism in an Fe–Al/Pb(Mg 1/3 Nb 2/3 )O 3 –PbTiO 3 heterostructure. In this system, a 90° rotation of the in-plane uniaxial magnetic anisotropy is exhibited during the increase of the external electric field, which means the easy axis turns into a hard axis and the hard axis turns into an easy one. Additionally, a non-volatile switch of the remanence is observed after a sweeping of the electric field from 0 kV cm −1 to  ±  10 kV cm −1 , then back to 0 kV cm −1 . More interestingly, a 20% non-volatile magnetic state tuning driven by individual pulse electric fields is shown in contrast to large tuning up to 120% caused by pulse electric fields with small assistant pulse magnetic fields, which means a 180° reverse of the magnetization. These remarkable behaviors demonstrated in this heterostructure reveal a promising potential application in magnetic memory devices mediated by electric fields. (paper)

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

Science.gov (United States)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Nonvolatile field effect transistors based on protons and Si/SiO2Si structures

International Nuclear Information System (INIS)

Warren, W.L.; Vanheusden, K.; Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Knoll, M.G.; Devine, R.A.B.

1997-01-01

Recently, the authors have demonstrated that annealing Si/SiO 2 /Si structures in a hydrogen containing ambient introduces mobile H + ions into the buried SiO 2 layer. Changes in the H + spatial distribution within the SiO 2 layer were electrically monitored by current-voltage (I-V) measurements. The ability to directly probe reversible protonic motion in Si/SiO 2 /Si structures makes this an exemplar system to explore the physics and chemistry of hydrogen in the technologically relevant Si/SiO 2 structure. In this work, they illustrate that this effect can be used as the basis for a programmable nonvolatile field effect transistor (NVFET) memory that may compete with other Si-based memory devices. The power of this novel device is its simplicity; it is based upon standard Si/SiO 2 /Si technology and forming gas annealing, a common treatment used in integrated circuit processing. They also briefly discuss the effects of radiation on its retention properties

Role of Al2O3 thin layer on improving the resistive switching properties of Ta5Si3-based conductive bridge random accesses memory device

Science.gov (United States)

Kumar, Dayanand; Aluguri, Rakesh; Chand, Umesh; Tseng, Tseung-Yuen

2018-04-01

Ta5Si3-based conductive bridge random access memory (CBRAM) devices have been investigated to improve their resistive switching characteristics for their application in future nonvolatile memory technology. Changes in the switching characteristics by the addition of a thin Al2O3 layer of different thicknesses at the bottom electrode interface of a Ta5Si3-based CBRAM devices have been studied. The double-layer device with a 1 nm Al2O3 layer has shown improved resistive switching characteristics over the single layer one with a high on/off resistance ratio of 102, high endurance of more than 104 cycles, and good retention for more than 105 s at the temperature of 130 °C. The higher thermal conductivity of Al2O3 over Ta5Si3 has been attributed to the enhanced switching properties of the double-layer devices.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

Science.gov (United States)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Nonvolatile memory characteristics influenced by the different crystallization of Ni-Si and Ni-N nanocrystals

International Nuclear Information System (INIS)

Chen, W.-R.; Yeh, J.-L.; Chang, C.-Y.; Chang, T.-C.; Chen, S.-C.

2008-01-01

The formation of Ni-Si and Ni-N nanocrystals by sputtering a Ni 0.3 Si 0.7 target in argon and nitrogen environment were proposed in this paper. A transmission electron microscope analysis shows the nanocrystals embedded in the nitride layer. X-ray photoelectron spectroscopy and x-ray diffraction also offer the chemical material analysis of nanocrystals with surrounding dielectric and the crystallization of nanocrystals for different thermal annealing treatments. Nonvolatile Ni-Si nanocrystal memories reveal superior electrical characteristics for charge storage capacity and reliability due to the improvement of thermal annealing treatment. In addition, we used energy band diagrams to explain the significance of surrounding dielectric for reliability

Projected phase-change memory devices.

Science.gov (United States)

Koelmans, Wabe W; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

2015-09-03

Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states.

All-polymer bistable resistive memory device based on nanoscale phase-separated PCBM-ferroelectric blends

KAUST Repository

Khan, Yasser

2012-11-21

All polymer nonvolatile bistable memory devices are fabricated from blends of ferroelectric poly(vinylidenefluoride-trifluoroethylene (P(VDF-TrFE)) and n-type semiconducting [6,6]-phenyl-C61-butyric acid methyl ester (PCBM). The nanoscale phase separated films consist of PCBM domains that extend from bottom to top electrode, surrounded by a ferroelectric P(VDF-TrFE) matrix. Highly conducting poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) polymer electrodes are used to engineer band offsets at the interfaces. The devices display resistive switching behavior due to modulation of this injection barrier. With careful optimization of the solvent and processing conditions, it is possible to spin cast very smooth blend films (Rrms ≈ 7.94 nm) and with good reproducibility. The devices exhibit high Ion/I off ratios (≈3 × 103), low read voltages (≈5 V), excellent dielectric response at high frequencies (Ïμr ≈ 8.3 at 1 MHz), and excellent retention characteristics up to 10 000 s. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

Science.gov (United States)

Ascenso Simões, Bruno

Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values

High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

Energy Technology Data Exchange (ETDEWEB)

Xiang, Lanyi; Ying, Jun; Han, Jinhua; Zhang, Letian, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn; Wang, Wei, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

2016-04-25

In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (V{sub on}) and severe degradation of the memory window (ΔV{sub on}) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electrons transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of V{sub on} at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔV{sub on} of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.

Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

Science.gov (United States)

Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

2010-11-01

When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

Science.gov (United States)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

Energy Technology Data Exchange (ETDEWEB)

Campbell, Philip Montgomery; Wix, Steven D.

2017-04-01

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models and compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.

Giant magneto-resistance devices

CERN Document Server

Hirota, Eiichi; Inomata, Koichiro

2002-01-01

This book deals with the application of giant magneto-resistance (GMR) effects to electronic devices. It will appeal to engineers and graduate students in the fields of electronic devices and materials. The main subjects are magnetic sensors with high resolution and magnetic read heads with high sensitivity, required for hard-disk drives with recording densities of several gigabytes. Another important subject is novel magnetic random-access memories (MRAM) with non-volatile non-destructive and radiation-resistant characteristics. Other topics include future GMR devices based on bipolar spin transistors, spin field-effect transistors (FETs) and double-tunnel junctions.

PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

Directory of Open Access Journals (Sweden)

Sanam Shahla Rizvi

2009-12-01

Full Text Available Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS. This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

Science.gov (United States)

Rizvi, Sanam Shahla; Chung, Tae-Sun

2010-01-01

Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

Electric Field Tuning Non-volatile Magnetism in Half-Metallic Alloys Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 Heterostructure

Science.gov (United States)

Dunzhu, Gesang; Wang, Fenglong; Zhou, Cai; Jiang, Changjun

2018-03-01

We reported the non-volatile electric field-mediated magnetic properties in the half-metallic Heusler alloy Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 heterostructure at room temperature. The remanent magnetization with different applied electric field along [100] and [01-1] directions was achieved, which showed the non-volatile remanent magnetization driven by an electric field. The two giant reversible and stable remanent magnetization states were obtained by applying pulsed electric field. This can be attributed to the piezostrain effect originating from the piezoelectric substrate, which can be used for magnetoelectric-based memory devices.

Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO2 for non-volatile memory device

International Nuclear Information System (INIS)

Stepina, N.P.; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V.

2008-01-01

A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO 2 , have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO 2 /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots

Self-formed conductive nanofilaments in (Bi, Mn)Ox for ultralow-power memory devices

KAUST Repository

Kang, Chen Fang

2015-04-01

Resistive random access memory (RRAM) is one of the most promising candidates as a next generation nonvolatile memory (NVM), owing to its superior scalability, low power consumption and high speed. From the materials science point of view, to explore optimal RRAM materials is still essential for practical application. In this work, a new material (Bi, Mn)Ox (BMO) is investigated and several key performance characteristics of Pt/BMO/Pt structured device, including switching performance, retention and endurance, are examined in details. Furthermore, it has been confirmed by high-resolution transmission electron microscopy that the underlying switching mechanism is attributed to formation and disruption of metallic conducting nanofilaments (CNFs). More importantly, the power dissipation for each CNF is as low as 3.8/20fJ for set/reset process, and a realization of cross-bar structure memory cell is demonstrated to prove the downscaling ability of proposed RRAM. These distinctive properties have important implications for understanding switching mechanisms and implementing ultralow power-dissipation RRAM based on BMO. •Self-formed conductive nanofilaments in BMO show ultralow-power memory feature.•The feature of 10nm in diameter and an average 20-30nm spacing of CNFs suggests the compatibility with the current CMOS technologies.•Power dissipation for each CNF is as low as 3.8/20fJ for set/reset process•A realization of cross-bar structure memory cell is demonstrated to prove the downscaling ability of proposed RRAM. © 2015 Elsevier Ltd.

A two-step annealing process for enhancing the ferroelectric properties of poly(vinylidene fluoride) (PVDF) devices

KAUST Repository

Park, Jihoon; Kurra, Narendra; AlMadhoun, M. N.; Odeh, Ihab N.; Alshareef, Husam N.

2015-01-01

We report a simple two-step annealing scheme for the fabrication of stable non-volatile memory devices employing poly(vinylidene fluoride) (PVDF) polymer thin-films. The proposed two-step annealing scheme comprises the crystallization

Smoothing type buffer memory device

International Nuclear Information System (INIS)

Podorozhnyj, D.M.; Yashin, I.V.

1990-01-01

The layout of the micropower 4-bit smoothing type buffer memory device allowing one to record without counting the sequence of input randomly distributed pulses in multi-channel devices with serial poll, is given. The power spent by a memory cell for one binary digit recording is not greater than 0.15 mW, the device dead time is 10 mus

Atomic layer-deposited Al–HfO{sub 2}/SiO{sub 2} bi-layers towards 3D charge trapping non-volatile memory

Energy Technology Data Exchange (ETDEWEB)

Congedo, Gabriele, E-mail: gabriele.congedo@mdm.imm.cnr.it; Wiemer, Claudia; Lamperti, Alessio; Cianci, Elena; Molle, Alessandro; Volpe, Flavio G.; Spiga, Sabina, E-mail: sabina.spiga@mdm.imm.cnr

2013-04-30

A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO{sub 2} as tunnel oxide, Al–HfO{sub 2} as charge trapping layer, SiO{sub 2} as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 °C in N{sub 2}, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ± 20 V to ± 12 V. When compared to a benchmark structure including thin Si{sub 3}N{sub 4} as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices. - Highlights: ► Charge trapping device with Al–HfO{sub 2} storage layer is fabricated and characterized. ► Al–HfO{sub 2} and SiO{sub 2} blocking oxides are deposited by atomic layer deposition. ► The oxide stack shows a good thermal stability after annealing at 900 °C. ► The device can be efficiently programmed/erased and retention is excellent. ► The oxide stack could be used for 3D-stacked Flash non-volatile memories.

High-Density Stacked Ru Nanocrystals for Nonvolatile Memory Application

International Nuclear Information System (INIS)

Ping, Mao; Zhi-Gang, Zhang; Li-Yang, Pan; Jun, Xu; Pei-Yi, Chen

2009-01-01

Stacked ruthenium (Ru) nanocrystals (NCs) are formed by rapid thermal annealing for the whole gate stacks and embedded in memory structure, which is compatible with conventional CMOS technology. Ru NCs with high density (3 × 10 12 cm −2 ), small size (2–4 nm) and good uniformity both in aerial distribution and morphology are formed. Attributed to the higher surface trap density, a memory window of 5.2 V is obtained with stacked Ru NCs in comparison to that of 3.5 V with single-layer samples. The stacked Ru NCs device also exhibits much better retention performance because of Coulomb blockade and vertical uniformity between stacked Ru NCs

Bipolar one diode-one resistor integration for high-density resistive memory applications.

Science.gov (United States)

Li, Yingtao; Lv, Hangbing; Liu, Qi; Long, Shibing; Wang, Ming; Xie, Hongwei; Zhang, Kangwei; Huo, Zongliang; Liu, Ming

2013-06-07

Different from conventional unipolar-type 1D-1R RRAM devices, a bipolar-type 1D-1R memory device concept is proposed and successfully demonstrated by the integration of Ni/TiOx/Ti diode and Pt/HfO2/Cu bipolar RRAM cell to suppress the undesired sneak current in a cross-point array. The bipolar 1D-1R memory device not only achieves self-compliance resistive switching characteristics by the reverse bias current of the Ni/TiOx/Ti diode, but also exhibits excellent bipolar resistive switching characteristics such as uniform switching, satisfactory data retention, and excellent scalability, which give it high potentiality for high-density integrated nonvolatile memory applications.

Strain-controlled nonvolatile magnetization switching

Science.gov (United States)

Geprägs, S.; Brandlmaier, A.; Brandt, M. S.; Gross, R.; Goennenwein, S. T. B.

2014-11-01

We investigate different approaches towards a nonvolatile switching of the remanent magnetization in single-crystalline ferromagnets at room temperature via elastic strain using ferromagnetic thin film/piezoelectric actuator hybrids. The piezoelectric actuator induces a voltage-controllable strain along different crystalline directions of the ferromagnetic thin film, resulting in modifications of its magnetization by converse magnetoelastic effects. We quantify the magnetization changes in the hybrids via ferromagnetic resonance spectroscopy and superconducting quantum interference device magnetometry. These measurements demonstrate a significant strain-induced change of the magnetization, limited by an inefficient strain transfer and domain formation in the particular system studied. To overcome these obstacles, we address practicable engineering concepts and use a model to demonstrate that a strain-controlled, nonvolatile magnetization switching should be possible in appropriately engineered ferromagnetic/piezoelectric actuator hybrids.

Nonvolatile Resistive Switching Memory Utilizing Cobalt Embedded in Gelatin

Directory of Open Access Journals (Sweden)

Cheng-Jung Lee

2017-12-01

Full Text Available This study investigates the preparation and electrical properties of Al/cobalt-embedded gelatin (CoG/ indium tin oxide (ITO resistive switching memories. Co. elements can be uniformly distributed in gelatin without a conventional dispersion procedure, as confirmed through energy dispersive X-ray analyzer and X-ray photoelectron spectroscopy observations. With an appropriate Co. concentration, Co. ions can assist the formation of an interfacial AlOx layer and improve the memory properties. High ON/OFF ratio, good retention capability, and good endurance switching cycles are demonstrated with 1 M Co. concentration, in contrast to 0.5 M and 2 M memory devices. This result can be attributed to the suitable thickness of the interfacial AlOx layer, which acts as an oxygen reservoir and stores and releases oxygen during switching. The Co. element in a solution-processed gelatin matrix has high potential for bio-electronic applications.

Hybrid dual gate ferroelectric memory for multilevel information storage

KAUST Repository

Khan, Yasser

2015-01-01

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200°C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V-1 s-1, large memory window of ∼18 V, and a low sub-threshold swing ∼-4 V dec-1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

Science.gov (United States)

Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

2017-10-01

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Static memory devices

NARCIS (Netherlands)

2012-01-01

A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one

Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO{sub 2} for non-volatile memory device

Energy Technology Data Exchange (ETDEWEB)

Stepina, N.P. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)], E-mail: nstepina@mail.ru; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)

2008-11-03

A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO{sub 2}, have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO{sub 2} /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots.

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

Science.gov (United States)

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

Science.gov (United States)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

Silicon-based thin films as bottom electrodes in chalcogenide nonvolatile memories

Energy Technology Data Exchange (ETDEWEB)

Lee, Seung-Yun [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)], E-mail: seungyun@etri.re.kr; Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Park, Young-Sam; Ryu, Sang-Ouk; Yu, Byoung-Gon; Kim, Sang-Hoon; Lee, Sang-Heung [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)

2007-10-31

The effect of the electrical resistivity of a silicon-germanium (SiGe) thin film on the phase transition in a GeSbTe (GST) chalcogenide alloy and the manufacturing aspect of the fabrication process of a chalcogenide memory device employing the SiGe film as bottom electrodes were investigated. While p-type SiGe bottom electrodes were formed using in situ doping techniques, n-type ones could be made in a different manner where phosphorus atoms diffused from highly doped silicon underlayers to undoped SiGe films. The p-n heterojunction did not form between the p-type GST and n-type SiGe layers, and the semiconduction type of the SiGe alloys did not influence the memory device switching. It was confirmed that an optimum resistivity value existed for memory operation in spite of proportionality of Joule heating to electrical resistivity. The very high resistivity of the SiGe film had no effect on the reduction of reset current, which might result from the resistance decrease of the SiGe alloy at high temperatures.

From silicon to organic nanoparticle memory devices.

Science.gov (United States)

Tsoukalas, D

2009-10-28

After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

Introduction to magnetic random-access memory

CERN Document Server

Dieny, Bernard; Lee, Kyung-Jin

2017-01-01

Magnetic random-access memory (MRAM) is poised to replace traditional computer memory based on complementary metal-oxide semiconductors (CMOS). MRAM will surpass all other types of memory devices in terms of nonvolatility, low energy dissipation, fast switching speed, radiation hardness, and durability. Although toggle-MRAM is currently a commercial product, it is clear that future developments in MRAM will be based on spin-transfer torque, which makes use of electrons’ spin angular momentum instead of their charge. MRAM will require an amalgamation of magnetics and microelectronics technologies. However, researchers and developers in magnetics and in microelectronics attend different technical conferences, publish in different journals, use different tools, and have different backgrounds in condensed-matter physics, electrical engineering, and materials science. This book is an introduction to MRAM for microelectronics engineers written by specialists in magnetic mat rials and devices. It presents the bas...

Multicolour fluorescent memory based on the interaction of hydroxy terphenyls with fluoride anions.

Science.gov (United States)

Akamatsu, Masaaki; Mori, Taizo; Okamoto, Ken; Sakai, Hideki; Abe, Masahiko; Hill, Jonathan P; Ariga, Katsuhiko

2014-12-01

Memory operations based on variation of a molecule's properties are important because they may lead to device miniaturization to the molecular scale or increasingly complex information processing protocols beyond the binary level. Molecular memory also introduces possibilities related to information-storage security where chemical information (or reagents) might be used as an encryption key, in this case, acidic/basic reagents. Chemical memory that possesses both volatile and non-volatile functionality requires reversible conversion between at least two chemically different stable or quasi-stable states. Here we have developed the phenol-phenoxide equilibrium of phenol fluorophores as a data storage element, which can be used to write or modulate data using chemical reagents. The properties of this system allow data to be stored and erased either in non-volatile or volatile modes. We also demonstrate non-binary switching of states made possible by preparation of  a composite containing the molecular memory elements. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Logic computation in phase change materials by threshold and memory switching.

Science.gov (United States)

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transport and Fatigue Properties of Ferroelectric Polymer P(VDF-TrFE) For Nonvolatile Memory Applications

KAUST Repository

Hanna, Amir

2012-06-01

Organic ferroelectrics polymers have recently received much interest for use in nonvolatile memory devices. The ferroelectric copolymer poly(vinylidene fluoride- trifluoroethylene) , P(VDF-TrFE), is a promising candidate due to its relatively high remnant polarization, low coercive field, fast switching times, easy processability, and low Curie transition. However, no detailed study of charge injection and current transport properties in P(VDF-TrFE) have been reported in the literature yet. Charge injection and transport are believed to affect various properties of ferroelectric films such as remnant polarization values and polarization fatigue behavior.. Thus, this thesis aims to study charge injection in P(VDF-TrFE) and its transport properties as a function of electrode material. Injection was studied for Al, Ag, Au and Pt electrodes. Higher work function metals such as Pt have shown less leakage current compared to lower work function metals such as Al for more than an order of magnitude. That implied n-type conduction behavior for P(VDF-TrFE), as well as electrons being the dominant injected carrier type. Charge transport was also studied as a function of temperature, and two major transport regimes were identified: 1) Thermionic emission over a Schottky barrier for low fields (E < 25 MV/m). 2) Space-Charge-Limited regime at higher fields (25 < E <120 MV/m). We have also studied the optical imprint phenomenon, the polarization fatigue resulting from a combination of broad band optical illumination and DC bias near the switching field. A setup was designed for the experiment, and validated by reproducing the reported effect in polycrystalline Pb(Zr,Ti)O3 , PZT, film. On the other hand, P(VDF-TrFE) film showed no polarization fatigue as a result of optical imprint test, which could be attributed to the large band gap of the material, and the low intensity of the UV portion of the arc lamp white light used for the experiment. Results suggest using high work

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

Science.gov (United States)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

Science.gov (United States)

Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

2009-01-01

We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

Science.gov (United States)

Swift, G.

2002-01-01

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

Science.gov (United States)

Sahay, Shubham; Suri, Manan

2017-12-01

This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

Phase change materials in non-volatile storage

OpenAIRE

Ielmini, Daniele; Lacaita, Andrea L.

2011-01-01

After revolutionizing the technology of optical data storage, phase change materials are being adopted in non-volatile semiconductor memories. Their success in electronic storage is mostly due to the unique properties of the amorphous state where carrier transport phenomena and thermally-induced phase change cooperate to enable high-speed, low-voltage operation and stable data retention possible within the same material. This paper reviews the key physical properties that make this phase so s...

Emerging memory technologies design, architecture, and applications

CERN Document Server

2014-01-01

This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits. • Provides a comprehensive reference on designing modern circuits with emerging, non-volatile memory technologies, such as MRAM and PCRAM; • Explores new design opportunities offered by emerging memory technologies, from a holistic perspective; • Describes topics in technology, modeling, architecture and applications; • Enables circuit designers to ex...

Switching behavior of resistive change memory using oxide nanowires

Science.gov (United States)

Aono, Takashige; Sugawa, Kosuke; Shimizu, Tomohiro; Shingubara, Shoso; Takase, Kouichi

2018-06-01

Resistive change random access memory (ReRAM), which is expected to be the next-generation nonvolatile memory, often has wide switching voltage distributions due to many kinds of conductive filaments. In this study, we have tried to suppress the distribution through the structural restriction of the filament-forming area using NiO nanowires. The capacitor with Ni metal nanowires whose surface is oxidized showed good switching behaviors with narrow distributions. The knowledge gained from our study will be very helpful in producing practical ReRAM devices.

The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric

Science.gov (United States)

Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel

2004-06-01

The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.

Magnetization Dynamics in Two Novel Current-Driven Spintronic Memory Cell Structures

KAUST Repository

Velazquez-Rizo, Martin

2017-07-01

In this work, two new spintronic memory cell structures are proposed. The first cell uses the diffusion of polarized spins into ferromagnets with perpendicular anisotropy to tilt their magnetization followed by their dipolar coupling to a fixed magnet (Bhowmik et al., 2014). The possibility of setting the magnetization to both stable magnetization states in a controlled manner using a similar concept remains unknown, but the proposed structure poses to be a solution to this difficulty. The second cell proposed takes advantage of the multiple stable magnetic states that exist in ferromagnets with configurational anisotropy and also uses spin torques to manipulate its magnetization. It utilizes a square-shaped ferromagnet whose stable magnetization has preferred directions along the diagonals of the square, giving four stable magnetic states allowing to use the structure as a multi-bit memory cell. Both devices use spin currents generated in heavy metals by the Spin Hall effect present in these materials. Among the advantages of the structures proposed are their inherent non-volatility and the fact that there is no need for applying external magnetic fields during their operation, which drastically improves the energy efficiency of the devices. Computational simulations using the Object Oriented Micromagnetic Framework (OOMMF) software package were performed to study the dynamics of the magnetization process in both structures and predict their behavior. Besides, we fabricated a 4-terminal memory cell with configurational anisotropy similar to the device proposed, and found four stable resistive states on the structure, proving the feasibility of this technology for implementation of high-density, non-volatile memory cells.

Low temperature synthesis and electrical characterization of germanium doped Ti-based nanocrystals for nonvolatile memory

International Nuclear Information System (INIS)

Feng, Li-Wei; Chang, Chun-Yen; Chang, Ting-Chang; Tu, Chun-Hao; Wang, Pai-Syuan; Lin, Chao-Cheng; Chen, Min-Chen; Huang, Hui-Chun; Gan, Der-Shin; Ho, New-Jin; Chen, Shih-Ching; Chen, Shih-Cheng

2011-01-01

Chemical and electrical characteristics of Ti-based nanocrystals containing germanium, fabricated by annealing the co-sputtered thin film with titanium silicide and germanium targets, were demonstrated for low temperature applications of nonvolatile memory. Formation and composition characteristics of nanocrystals (NCs) at various annealing temperatures were examined by transmission electron microscopy and X-ray photon-emission spectroscopy, respectively. It was observed that the addition of germanium (Ge) significantly reduces the proposed thermal budget necessary for Ti-based NC formation due to the rise of morphological instability and agglomeration properties during annealing. NC structures formed after annealing at 500 °C, and separated well at 600 °C annealing. However, it was also observed that significant thermal desorption of Ge atoms occurs at 600 °C due to the sublimation of formatted GeO phase and results in a serious decrease of memory window. Therefore, an approach to effectively restrain Ge thermal desorption is proposed by encapsulating the Ti-based trapping layer with a thick silicon oxide layer before 600 °C annealing. The electrical characteristics of data retention in the sample with the 600 °C annealing exhibited better performance than the 500 °C-annealed sample, a result associated with the better separation and better crystallization of the NC structures.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

Science.gov (United States)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

Science.gov (United States)

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

Science.gov (United States)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity

International Nuclear Information System (INIS)

Kang, S.H.; Lee, K.

2013-01-01

A spintronic integrated circuit (IC) is made of a combination of a semiconductor IC and a dense array of nanometer-scale magnetic tunnel junctions. This emerging field is of growing scientific and engineering interest, owing to its potential to bring disruptive device innovation to the world of electronics. This technology is currently being pursued not only for scalable non-volatile spin-transfer-torque magnetoresistive random access memory, but also for various forms of non-volatile logic (Spin-Logic). This paper reviews recent advances in spintronic IC. Key discoveries and breakthroughs in materials and devices are highlighted in light of the broader perspective of their application in low-energy mobile computing and connectivity systems, which have emerged as leading drivers for the prevailing electronics ecosystem

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Directory of Open Access Journals (Sweden)

Sukru Burc Eryilmaz

2014-07-01

Full Text Available Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

Science.gov (United States)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Non-volatile MOS RAM cell with capacitor-isolated nodes that are radiation accessible for rendering a non-permanent programmed information in the cell of a non-volatile one

NARCIS (Netherlands)

Widdershoven, Franciscus P.; Annema, Anne J.; Storms, Maurits M.N.; Pelgrom, Marcellinus J.M.; Pelgrom, Marcel J M

2001-01-01

A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of

Scientific developments of liquid crystal-based optical memory: a review

Science.gov (United States)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

International Nuclear Information System (INIS)

Tang Zhen-Jie; Li Rong; Yin Jiang

2013-01-01

A composition-modulated (HfO 2 ) x (Al 2 O3) 1−x charge trapping layer is proposed for charge trap flash memory by controlling the Al atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated (HfO 2 ) x (Al 2 O 3 ) 1−x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

Leading research report for fiscal 1999. Fundamental technology of spin electronic device; 1999 nendo spin toronikusu soshi kiban gijutsu kenkyu hokokusho

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

The project, with attention paid to both spin and charge of electrons, aims to draw the best of the said two attributes of electrons by use of the state of the art in manufacturing technology for the creation of novel electronic devices. The nonvolatile MRAM (magnetic random access memory), which is the nearest to commercialization, is a tunnel device consisting of two sheet-shape ferromagnetic metal electrodes and an insulator film sandwiched between the said two electrodes, with the lower electrode magnetized only in one direction. The tunnel resistance changes when the magnetization direction in the upper electrode changes left and right (1, 0) according to an external writing magnetic field, and this enables nondestructive readout. The upper electrode magnetization direction remains unchanged thanks to hysteresis when the external writing magnetic field is turned off, and this allows the device to serve as a nonvolatile memory device. The device has a potential for higher speeds and enhanced integration. Much is also expected from a spin conduction functional device utilizing spin-dependent electric conduction, spin optical function device, spin quantum calculation directly utilizing quantum state, magnetic field sensor, etc. Their importance is great economically and socially, and technologies relating to magnetism and semiconductor should be merged for their further development. (NEDO)

Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

International Nuclear Information System (INIS)

Jang, Byung Chul; Kim, Jong Yun; Koo, Beom Jun; Yang, Sang Yoon; Choi, Sung-Yool; Seong, Hyejeong; Im, Sung Gap; Kim, Sung Kyu

2015-01-01

Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices. (paper)

Transmission electron microscopy assessment of conductive-filament formation in Ni-HfO2-Si resistive-switching operational devices

Science.gov (United States)

Martín, Gemma; González, Mireia B.; Campabadal, Francesca; Peiró, Francesca; Cornet, Albert; Estradé, Sònia

2018-01-01

Resistive random-access memory (ReRAM) devices are currently the object of extensive research to replace flash non-volatile memory. However, elucidation of the conductive-filament formation mechanisms in ReRAM devices at nanoscale is mandatory. In this study, the different states created under real operation conditions of HfO2-based ReRAM devices are characterized through transmission electron microscopy and electron energy-loss spectroscopy. The physical mechanism behind the conductive-filament formation in Ni/HfO2/Si ReRAM devices based on the diffusion of Ni from the electrode to the Si substrate and of Si from the substrate to the electrode through the HfO2 layer is demonstrated.

An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

International Nuclear Information System (INIS)

Jia Xiaoyun; Feng Peng; Zhang Shengguang; Wu Nanjian; Zhao Baiqin; Liu Su

2013-01-01

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm 2 and 0.12 mm 2 , respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s). (semiconductor integrated circuits)

C-RAM: breaking mobile device memory barriers using the cloud

OpenAIRE

Pamboris, A; Pietzuch, P

2015-01-01

?Mobile applications are constrained by the available memory of mobile devices. We present C-RAM, a system that uses cloud-based memory to extend the memory of mobile devices. It splits application state and its associated computation between a mobile device and a cloud node to allow applications to consume more memory, while minimising the performance impact. C-RAM thus enables developers to realise new applications or port legacy desktop applications with a large memory footprint to mobile ...

Resistive switching memories in MoS{sub 2} nanosphere assemblies

Energy Technology Data Exchange (ETDEWEB)

Xu, Xiao-Yong, E-mail: xxxy@yzu.edu.cn, E-mail: xcxseu@seu.edu.cn, E-mail: jghu@yzu.edu.cn [School of Physics Science and Technology, Yangzhou University, Yangzhou 225002 (China); State Key Laboratory of Bioelectronics and School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China); School of Materials Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore, Singapore 639798 (Singapore); Yin, Zong-You [School of Materials Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore, Singapore 639798 (Singapore); Xu, Chun-Xiang, E-mail: xxxy@yzu.edu.cn, E-mail: xcxseu@seu.edu.cn, E-mail: jghu@yzu.edu.cn; Dai, Jun [State Key Laboratory of Bioelectronics and School of Electronic Science and Engineering, Southeast University, Nanjing 210096 (China); Hu, Jing-Guo, E-mail: xxxy@yzu.edu.cn, E-mail: xcxseu@seu.edu.cn, E-mail: jghu@yzu.edu.cn [School of Physics Science and Technology, Yangzhou University, Yangzhou 225002 (China)

2014-01-20

A resistive switching memory device consisting of reduced graphene oxide and indium tin oxide as top/bottom two electrodes, separated by dielectric MoS{sub 2} nanosphere assemblies as the active interlayer, was fabricated. This device exhibits the rewritable nonvolatile resistive switching with low SET/RESET voltage (∼2 V), high ON/OFF resistance ratio (∼10{sup 4}), and superior electrical bistability, introducing a potential application in data storage field. The resistance switching mechanism was analyzed in the assumptive model of the electron tunneling across the polarized potential barriers.

A Retina-Like Dual Band Organic Photosensor Array for Filter-Free Near-Infrared-to-Memory Operations.

Science.gov (United States)

Wang, Hanlin; Liu, Hongtao; Zhao, Qiang; Ni, Zhenjie; Zou, Ye; Yang, Jie; Wang, Lifeng; Sun, Yanqiu; Guo, Yunlong; Hu, Wenping; Liu, Yunqi

2017-08-01

Human eyes use retina photoreceptor cells to absorb and distinguish photons from different wavelengths to construct an image. Mimicry of such a process and extension of its spectral response into the near-infrared (NIR) is indispensable for night surveillance, retinal prosthetics, and medical imaging applications. Currently, NIR organic photosensors demand optical filters to reduce visible interference, thus making filter-free and anti-visible NIR imaging a challenging task. To solve this limitation, a filter-free and conformal, retina-inspired NIR organic photosensor is presented. Featuring an integration of photosensing and floating-gate memory modules, the device possesses an acute color distinguishing capability. In general, the retina-like photosensor transduces NIR (850 nm) into nonvolatile memory and acts as a dynamic photoswitch under green light (550 nm). In doing this, a filter-free but color-distinguishing photosensor is demonstrated that selectively converts NIR optical signals into nonvolatile memory. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Impact of time and space evolution of ion tracks in nonvolatile memory cells approaching nanoscale

International Nuclear Information System (INIS)

Cellere, G.; Paccagnella, A.; Murat, M.; Barak, J.; Akkerman, A.; Harboe-Sorensen, R.; Virtanen, A.; Visconti, A.; Bonanomi, M.

2010-01-01

Swift heavy ions impacting on matter lose energy through the creation of dense tracks of charges. The study of the space and time evolution of energy exchange allows understanding the single event effects behavior in advanced microelectronic devices. In particular, the shrinking of minimum feature size of most advanced memory devices makes them very interesting test vehicles to study these effects since the device and the track dimensions are comparable; hence, measured effects are directly correlated with the time and space evolution of the energy release. In this work we are studying the time and space evolution of ion tracks by using advanced non volatile memories and Monte Carlo simulations. Experimental results are very well explained by the theoretical calculations.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

Science.gov (United States)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Microscale memory characteristics of virus-quantum dot hybrids

Science.gov (United States)

Portney, Nathaniel G.; Tseng, Ricky J.; Destito, Giuseppe; Strable, Erica; Yang, Yang; Manchester, Marianne; Finn, M. G.; Ozkan, Mihrimah

2007-05-01

An electrical multi stability effect was observed for a single layer device fabricated, comprising a hybrid virus-semiconducting quantum dot (CdSe /ZnS core/shell Qds) assembled onto icosahedral-mutant-virus template (CPMV-T184C). A substrate based bottom-up pathway was used to conjugate two different color emitting Qds for fluorescence visualization and to insert a charging/decharging factor. Pulsed wave measurements depicted distinct conductive states with repeatable and nonvolatile behavior as a functioning memory element.

In search of the next memory inside the circuitry from the oldest to the emerging non-volatile memories

CERN Document Server

Campardo, Giovanni

2017-01-01

This book provides students and practicing chip designers with an easy-to-follow yet thorough, introductory treatment of the most promising emerging memories under development in the industry. Focusing on the chip designer rather than the end user, this book offers expanded, up-to-date coverage of emerging memories circuit design. After an introduction on the old solid-state memories and the fundamental limitations soon to be encountered, the working principle and main technology issues of each of the considered technologies (PCRAM, MRAM, FeRAM, ReRAM) are reviewed and a range of topics related to design is explored: the array organization, sensing and writing circuitry, programming algorithms and error correction techniques are reviewed comparing the approach followed and the constraints for each of the technologies considered. Finally the issue of radiation effects on memory devices has been briefly treated. Additionally some considerations are entertained about how emerging memories can find a place in the...

Electronic polymer memory devices-Easy to fabricate, difficult to understand

International Nuclear Information System (INIS)

Paul, Shashi; Salaoru, Iulia

2010-01-01

There has been a number reports on polymer memory devices for the last one decade. Polymer memory devices are fabricated by depositing a blend (an admixture of organic polymer, small organic molecules and nanoparticles) between two metal electrodes. These devices show two electrical conductance states ('1' and '0') when voltage is applied, thus rendering the structures suitable for data retention. These two states can be viewed as the realisation of memory devices. However, polymer memory devices reported so far suffer from multiple drawbacks that render their industrial implementation premature. There is a large discrepancy in the results reported by different groups. This article attempts to answer some of the questions.

An overview of Experimental Condensed Matter Physics in Argentina by 2014, and Oxides for Non Volatile Memory Devices: The MeMOSat Project

Science.gov (United States)

Levy, Pablo

2015-03-01

In the first part of my talk, I will describe the status of the experimental research in Condensed Matter Physics in Argentina, biased towards developments related to micro and nanotechnology. In the second part, I will describe the MeMOSat Project, a consortium aimed at producing non-volatile memory devices to work in aggressive environments, like those found in the aerospace and nuclear industries. Our devices rely on the Resistive Switching mechanism, which produces a permanent but reversible change in the electrical resistance across a metal-insulator-metal structure by means of a pulsed protocol of electrical stimuli. Our project is devoted to the study of Memory Mechanisms in Oxides (MeMO) in order to establish a technological platform that tests the Resistive RAM (ReRAM) technology for aerospace applications. A review of MeMOSat's activities is presented, covering the initial Proof of Concept in ceramic millimeter sized samples; the study of different oxide-metal couples including (LaPr)2/3Ca1/3MnO, La2/3Ca1/3MnO3, YBa2Cu3O7, TiO2, HfO2, MgO and CuO; and recent miniaturized arrays of micrometer sized devices controlled by in-house designed electronics, which were launched with the BugSat01 satellite in June2014 by the argentinian company Satellogic.

Transparent resistive switching memory using aluminum oxide on a flexible substrate

International Nuclear Information System (INIS)

Yeom, Seung-Won; Kim, Tan-Young; Ha, Hyeon Jun; Ju, Byeong-Kwon; Shin, Sang-Chul; Shim, Jae Won; Lee, Yun-Hi

2016-01-01

Resistive switching memory (ReRAM) has attracted much attention in recent times owing to its fast switching, simple structure, and non-volatility. Flexible and transparent electronic devices have also attracted considerable attention. We therefore fabricated an Al 2 O 3 -based ReRAM with transparent indium-zinc-oxide (IZO) electrodes on a flexible substrate. The device transmittance was found to be higher than 80% in the visible region (400–800 nm). Bended states (radius = 10 mm) of the device also did not affect the memory performance because of the flexibility of the two transparent IZO electrodes and the thin Al 2 O 3 layer. The conduction mechanism of the resistive switching of our device was explained by ohmic conduction and a Poole–Frenkel emission model. The conduction mechanism was proved by oxygen vacancies in the Al 2 O 3 layer, as analyzed by x-ray photoelectron spectroscopy analysis. These results encourage the application of ReRAM in flexible and transparent electronic devices. (letter)

Transparent resistive switching memory using aluminum oxide on a flexible substrate

Science.gov (United States)

Yeom, Seung-Won; Shin, Sang-Chul; Kim, Tan-Young; Ha, Hyeon Jun; Lee, Yun-Hi; Shim, Jae Won; Ju, Byeong-Kwon

2016-02-01

Resistive switching memory (ReRAM) has attracted much attention in recent times owing to its fast switching, simple structure, and non-volatility. Flexible and transparent electronic devices have also attracted considerable attention. We therefore fabricated an Al2O3-based ReRAM with transparent indium-zinc-oxide (IZO) electrodes on a flexible substrate. The device transmittance was found to be higher than 80% in the visible region (400-800 nm). Bended states (radius = 10 mm) of the device also did not affect the memory performance because of the flexibility of the two transparent IZO electrodes and the thin Al2O3 layer. The conduction mechanism of the resistive switching of our device was explained by ohmic conduction and a Poole-Frenkel emission model. The conduction mechanism was proved by oxygen vacancies in the Al2O3 layer, as analyzed by x-ray photoelectron spectroscopy analysis. These results encourage the application of ReRAM in flexible and transparent electronic devices.

One bipolar transistor selector - One resistive random access memory device for cross bar memory array

Science.gov (United States)

Aluguri, R.; Kumar, D.; Simanjuntak, F. M.; Tseng, T.-Y.

2017-09-01

A bipolar transistor selector was connected in series with a resistive switching memory device to study its memory characteristics for its application in cross bar array memory. The metal oxide based p-n-p bipolar transistor selector indicated good selectivity of about 104 with high retention and long endurance showing its usefulness in cross bar RRAM devices. Zener tunneling is found to be the main conduction phenomena for obtaining high selectivity. 1BT-1R device demonstrated good memory characteristics with non-linearity of 2 orders, selectivity of about 2 orders and long retention characteristics of more than 105 sec. One bit-line pull-up scheme shows that a 650 kb cross bar array made with this 1BT1R devices works well with more than 10 % read margin proving its ability in future memory technology application.

3D Printed Photoresponsive Devices Based on Shape Memory Composites.

Science.gov (United States)

Yang, Hui; Leow, Wan Ru; Wang, Ting; Wang, Juan; Yu, Jiancan; He, Ke; Qi, Dianpeng; Wan, Changjin; Chen, Xiaodong

2017-09-01

Compared with traditional stimuli-responsive devices with simple planar or tubular geometries, 3D printed stimuli-responsive devices not only intimately meet the requirement of complicated shapes at macrolevel but also satisfy various conformation changes triggered by external stimuli at the microscopic scale. However, their development is limited by the lack of 3D printing functional materials. This paper demonstrates the 3D printing of photoresponsive shape memory devices through combining fused deposition modeling printing technology and photoresponsive shape memory composites based on shape memory polymers and carbon black with high photothermal conversion efficiency. External illumination triggers the shape recovery of 3D printed devices from the temporary shape to the original shape. The effect of materials thickness and light density on the shape memory behavior of 3D printed devices is quantified and calculated. Remarkably, sunlight also triggers the shape memory behavior of these 3D printed devices. This facile printing strategy would provide tremendous opportunities for the design and fabrication of biomimetic smart devices and soft robotics. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Role of nanorods insertion layer in ZnO-based electrochemical metallization memory cell

Science.gov (United States)

Mangasa Simanjuntak, Firman; Singh, Pragya; Chandrasekaran, Sridhar; Juanda Lumbantoruan, Franky; Yang, Chih-Chieh; Huang, Chu-Jie; Lin, Chun-Chieh; Tseng, Tseung-Yuen

2017-12-01

An engineering nanorod array in a ZnO-based electrochemical metallization device for nonvolatile memory applications was investigated. A hydrothermally synthesized nanorod layer was inserted into a Cu/ZnO/ITO device structure. Another device was fabricated without nanorods for comparison, and this device demonstrated a diode-like behavior with no switching behavior at a low current compliance (CC). The switching became clear only when the CC was increased to 75 mA. The insertion of a nanorods layer induced switching characteristics at a low operation current and improve the endurance and retention performances. The morphology of the nanorods may control the switching characteristics. A forming-free electrochemical metallization memory device having long switching cycles (>104 cycles) with a sufficient memory window (103 times) for data storage application, good switching stability and sufficient retention was successfully fabricated by adjusting the morphology and defect concentration of the inserted nanorod layer. The nanorod layer not only contributed to inducing resistive switching characteristics but also acted as both a switching layer and a cation diffusion control layer.

Architecture and performance of radiation-hardened 64-bit SOS/MNOS memory

International Nuclear Information System (INIS)

Kliment, D.C.; Ronen, R.S.; Nielsen, R.L.; Seymour, R.N.; Splinter, M.R.

1976-01-01

This paper discusses the circuit architecture and performance of a nonvolatile 64-bit MNOS memory fabricated on silicon on sapphire (SOS). The circuit is a test vehicle designed to demonstrate the feasibility of a high-performance, high-density, radiation-hardened MNOS/SOS memory. The array is organized as 16 words by 4 bits and is fully decoded. It utilizes a two-(MNOS) transistor-per-bit cell and differential sensing scheme and is realized in PMOS static resistor load logic. The circuit was fabricated and tested as both a fast write random access memory (RAM) and an electrically alterable read only memory (EAROM) to demonstrate design and process flexibility. Discrete device parameters such as retention, circuit electrical characteristics, and tolerance to total dose and transient radiation are presented

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

Science.gov (United States)

Zand, Ramtin; DeMara, Ronald F.

2017-12-01

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

Energy Technology Data Exchange (ETDEWEB)

Normand, P. E-mail: p.normand@imel.demokritos.gr; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M

2004-02-01

An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications.

Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

International Nuclear Information System (INIS)

Normand, P.; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M.

2004-01-01

An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications

Dual-functional Memory and Threshold Resistive Switching Based on the Push-Pull Mechanism of Oxygen Ions

KAUST Repository

Huang, Yi-Jen

2016-04-07

The combination of nonvolatile memory switching and volatile threshold switching functions of transition metal oxides in crossbar memory arrays is of great potential for replacing charge-based flash memory in very-large-scale integration. Here, we show that the resistive switching material structure, (amorphous TiOx)/(Ag nanoparticles)/(polycrystalline TiOx), fabricated on the textured-FTO substrate with ITO as the top electrode exhibits both the memory switching and threshold switching functions. When the device is used for resistive switching, it is forming-free for resistive memory applications with low operation voltage (<±1 V) and self-compliance to current up to 50 μA. When it is used for threshold switching, the low threshold current is beneficial for improving the device selectivity. The variation of oxygen distribution measured by energy dispersive X-ray spectroscopy and scanning transmission electron microscopy indicates the formation or rupture of conducting filaments in the device at different resistance states. It is therefore suggested that the push and pull actions of oxygen ions in the amorphous TiOx and polycrystalline TiOx films during the voltage sweep account for the memory switching and threshold switching properties in the device.

Transparent Memory For Harsh Electronics

KAUST Repository

Ho, C. H.; Duran Retamal, Jose Ramon; Yang, P. K.; Lee, C. P.; Tsai, M. L.; Kang, C. F.; He, Jr-Hau

2017-01-01

As a new class of non-volatile memory, resistive random access memory (RRAM) offers not only superior electronic characteristics, but also advanced functionalities, such as transparency and radiation hardness. However, the environmental tolerance

Different Steric-Twist-Induced Ternary Memory Characteristics in Nonconjugated Copolymers with Pendant Naphthalene and 1,8-Naphthalimide Moieties.

Science.gov (United States)

Wang, Ming; Li, Zhuang; Li, Hua; He, Jinghui; Li, Najun; Xu, Qingfeng; Lu, Jianmei

2017-10-18

Herein, novel random copolymers PMNN and PMNB were designed and synthesized, and the memory devices Al/PMNN and PMNB/ITO both exhibited ternary memory performance. The switching voltages of the OFF-ON1 and ON1-ON2 transitions for both memory devices are around -2.0 and -3.5 V, respectively, and the ON1/OFF, ON2/ON1 current ratios are both up to 10 3 . The observed tristable electrical conductivity switching could be attributed to field-induced conformational ordering of the naphthalene rings in the side chains, and subsequent charge trapping by 1,8-naphthalimide moieties. More interestingly, by adjusting the connection sites of 1,8-naphthalimide moieties to tune the steric-twist effect, different memory properties were achieved (PMNN showed nonvolatile write once, read many (WORM) memory behavior, whereas PMNB showed volatile static RAM (SRAM) memory behavior). This result will offer a guideline for the design of different high-performance multilevel memory devices by tuning the steric effects of the chemical moieties. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of CuPc layer insertion on the memory performance of CdS nanocomposite diodes

Energy Technology Data Exchange (ETDEWEB)

Tripathi, S.K., E-mail: surya@pu.ac.in; Kaur, Ramneek; Jyoti

2016-09-15

Highlights: • CdS nanocomposite as an active layer investigated for memory device application. • Effect of copper phthalocyanine layer insertion on the memory performance studied. • Bipolar switching behaviour with high ON/OFF ratio ∼1.4 × 10{sup 4}. • Series resistance and interface states dominate the electrical properties of the device. - Abstract: In the present work, semiconductor diodes with CdS nanocomposite as an active layer have been fabricated and investigated for memory device applications. The effect of copper phthalocyanine (CuPc) layer insertion between the bottom electrode and CdS nanocomposite has been studied. I–V characteristics show electrical hysteresis behaviour vital for memory storage application. The as-fabricated devices exhibit bipolar switching behaviour with OFF to ON state transition at positive bias and vice versa. Device with CuPc layer exhibits I{sub ON}/I{sub OFF} ratio ∼ 1.4 × 10{sup 4}. Possible conduction mechanism has been described on the basis of theoretical current conduction models. The frequency dispersion capacitance, series resistance and conductance of the devices have been studied and discussed. At low frequency, the series resistance and the interface states dominate the electrical properties of the device. The results indicate that the multilayered devices open up the possibility of new generation non-volatile memory devices with low cost, high density and stability.

Direct observation of conductive filament formation in Alq3 based organic resistive memories

Energy Technology Data Exchange (ETDEWEB)

Busby, Y., E-mail: yan.busby@unamur.be; Pireaux, J.-J. [Research Center in the Physics of Matter and Radiation (PMR), Laboratoire Interdisciplinaire de Spectroscopie Electronique (LISE), University of Namur, B-5000 Namur (Belgium); Nau, S.; Sax, S. [NanoTecCenter Weiz Forschungsgesellschaft mbH, Franz-Pichler Straße 32, A-8160 Weiz (Austria); List-Kratochvil, E. J. W. [NanoTecCenter Weiz Forschungsgesellschaft mbH, Franz-Pichler Straße 32, A-8160 Weiz (Austria); Institute of Solid State Physics, Graz University of Technology, A-8010 Graz (Austria); Novak, J.; Banerjee, R.; Schreiber, F. [Institute of Applied Physics, Eberhard-Karls-Universität Tübingen, D-72076 Tübingen (Germany)

2015-08-21

This work explores resistive switching mechanisms in non-volatile organic memory devices based on tris(8-hydroxyquinolie)aluminum (Alq{sub 3}). Advanced characterization tools are applied to investigate metal diffusion in ITO/Alq{sub 3}/Ag memory device stacks leading to conductive filament formation. The morphology of Alq{sub 3}/Ag layers as a function of the metal evaporation conditions is studied by X-ray reflectivity, while depth profile analysis with X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry is applied to characterize operational memory elements displaying reliable bistable current-voltage characteristics. 3D images of the distribution of silver inside the organic layer clearly point towards the existence of conductive filaments and allow for the identification of the initial filament formation and inactivation mechanisms during switching of the device. Initial filament formation is suggested to be driven by field assisted diffusion of silver from abundant structures formed during the top electrode evaporation, whereas thermochemical effects lead to local filament inactivation.

An UV photochromic memory effect in proton-based WO3 electrochromic devices

International Nuclear Information System (INIS)

Zhang Yong; Lee, S.-H.; Mascarenhas, A.; Deb, S. K.

2008-01-01

We report an UV photochromic memory effect on a standard proton-based WO 3 electrochromic device. It exhibits two memory states, associated with the colored and bleached states of the device, respectively. Such an effect can be used to enhance device performance (increasing the dynamic range), re-energize commercial electrochromic devices, and develop memory devices

An UV photochromic memory effect in proton-based WO3 electrochromic devices

Science.gov (United States)

Zhang, Yong; Lee, S.-H.; Mascarenhas, A.; Deb, S. K.

2008-11-01

We report an UV photochromic memory effect on a standard proton-based WO3 electrochromic device. It exhibits two memory states, associated with the colored and bleached states of the device, respectively. Such an effect can be used to enhance device performance (increasing the dynamic range), re-energize commercial electrochromic devices, and develop memory devices.

CMOS-compatible spintronic devices: a review

Science.gov (United States)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Silicon integrated circuits part A : supplement 2

CERN Document Server

Kahng, Dawon

1981-01-01

Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

Cell characteristics of FePt nano-dot memories with a high-k Al2O3 blocking oxide

International Nuclear Information System (INIS)

Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Cheol; Tanaka, Testsu

2012-01-01

The cell characteristics of an alloy FePt nano-dot (ND) charge trapping memory with a high-k dielectric as a blocking oxide was investigated. Adoption of a high-k Al 2 O 3 material as a blocking oxide for the metal nano-dot memory provided a superior scaling of the operation voltage compared to silicon oxide under a similar gate leakage level. For the 40-nm-thick high-k (Al 2 O 3 ) blocking oxide, we confirmed an operation voltage reduction of ∼7 V under the same memory window on for silicon dioxide. Also, this device showed a large memory window of 7.8 V and a low leakage current under 10 -10 A in an area of Φ 0.25 mm. From these results, the use of a dielectric (Al 2 O 3 ) as a blocking oxide for a metal nano-dot device is essential, and a metal nano-dot memory with a high-k dielectric will be one of the candidates for a high-density non-volatile memory device.

A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

International Nuclear Information System (INIS)

Zhang Junyu; Wang Yong; Liu Jing; Zhang Manhong; Xu Zhongguang; Huo Zongliang; Liu Ming

2012-01-01

We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the 'erased states' can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications. (semiconductor devices)

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

Science.gov (United States)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

International Nuclear Information System (INIS)

Ando, K.; Yuasa, S.; Fujita, S.; Ito, J.; Yoda, H.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.

2014-01-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

Science.gov (United States)

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A chiral-based magnetic memory device without a permanent magnet.

Science.gov (United States)

Ben Dor, Oren; Yochelis, Shira; Mathew, Shinto P; Naaman, Ron; Paltiel, Yossi

2013-01-01

Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices.

Resistive switching memory properties of layer-by-layer assembled enzyme multilayers

International Nuclear Information System (INIS)

Baek, Hyunhee; Cho, Jinhan; Lee, Chanwoo; Lim, Kwang-il

2012-01-01

The properties of enzymes, which can cause reversible changes in currents through redox reactions in solution, are of fundamental and practical importance in bio-electrochemical applications. These redox properties of enzymes are often associated with their charge-trap sites. Here, we demonstrate that reversible changes in resistance in dried lysozyme (LYS) films can be generated by an externally applied voltage as a result of charge trap/release. Based on such changes, LYS can be used as resistive switching active material for nonvolatile memory devices. In this study, cationic LYS and anionic poly(styrene sulfonate) (PSS) layers were alternately deposited onto Pt-coated silicon substrates using a layer-by-layer assembly method. Then, top electrodes were deposited onto the top of LYS/PSS multilayers to complete the fabrication of the memory-like device. The LYS/PSS multilayer devices exhibited typical resistive switching characteristics with an ON/OFF current ratio above 10 2 , a fast switching speed of 100 ns and stable performance. Furthermore, the insertion of insulating polyelectrolytes (PEs) between the respective LYS layers significantly enhanced the memory performance of the devices showing a high ON/OFF current ratio of ∼10 6 and low levels of power consumption. (paper)

High performance devices enabled by epitaxial, preferentially oriented, nanodots and/or nanorods

Science.gov (United States)

Goyal, Amit [Knoxville, TN

2011-10-11

Novel articles and methods to fabricate same with self-assembled nanodots and/or nanorods of a single or multicomponent material within another single or multicomponent material for use in electrical, electronic, magnetic, electromagnetic, superconducting and electrooptical devices is disclosed. Self-assembled nanodots and/or nanorods are ordered arrays wherein ordering occurs due to strain minimization during growth of the materials. A simple method to accomplish this when depositing in-situ films is also disclosed. Device applications of resulting materials are in areas of superconductivity, photovoltaics, ferroelectrics, magnetoresistance, high density storage, solid state lighting, non-volatile memory, photoluminescence, thermoelectrics and in quantum dot lasers.

Broadband nonvolatile photonic switching based on optical phase change materials: beyond the classical figure-of-merit.

Science.gov (United States)

Zhang, Qihang; Zhang, Yifei; Li, Junying; Soref, Richard; Gu, Tian; Hu, Juejun

2018-01-01

In this Letter, we propose a broadband, nonvolatile on-chip switch design in the telecommunication C-band with record low loss and crosstalk. The unprecedented device performance builds on: 1) a new optical phase change material (O-PCM) Ge 2 Sb 2 Se 4 Te 1 (GSST), which exhibits significantly reduced optical attenuation compared to traditional O-PCMs, and 2) a nonperturbative design that enables low-loss device operation beyond the classical figure-of-merit (FOM) limit. We further demonstrate that the 1-by-2 and 2-by-2 switches can serve as basic building blocks to construct nonblocking and nonvolatile on-chip switching fabric supporting arbitrary numbers of input and output ports.

Plasticity in memristive devices for Spiking Neural Networks

Directory of Open Access Journals (Sweden)

Sylvain eSaïghi

2015-03-01

Full Text Available Memristive devices present a new device technology allowing for the realization of compact nonvolatile memories. Some of them are already in the process of industrialization. Additionally, they exhibit complex multilevel and plastic behaviors, which make them good candidates for the implementation of artificial synapses in neuromorphic engineering. However, memristive effects rely on diverse physical mechanisms, and their plastic behaviors differ strongly from one technology to another. Here, we present measurements performed on different memristive devices and the opportunities that they provide. We show that they can be used to implement different learning rules whose properties emerge directly from device physics: real time or accelerated operation, deterministic or stochastic behavior, long term or short term plasticity. We then discuss how such devices might be integrated into a complete architecture. These results highlight that there is no unique way to exploit memristive devices in neuromorphic systems. Understanding and embracing device physics is the key for their optimal use.

Nanoscale superconducting memory based on the kinetic inductance of asymmetric nanowire loops

Science.gov (United States)

Murphy, Andrew; Averin, Dmitri V.; Bezryadin, Alexey

2017-06-01

The demand for low-dissipation nanoscale memory devices is as strong as ever. As Moore’s law is staggering, and the demand for a low-power-consuming supercomputer is high, the goal of making information processing circuits out of superconductors is one of the central goals of modern technology and physics. So far, digital superconducting circuits could not demonstrate their immense potential. One important reason for this is that a dense superconducting memory technology is not yet available. Miniaturization of traditional superconducting quantum interference devices is difficult below a few micrometers because their operation relies on the geometric inductance of the superconducting loop. Magnetic memories do allow nanometer-scale miniaturization, but they are not purely superconducting (Baek et al 2014 Nat. Commun. 5 3888). Our approach is to make nanometer scale memory cells based on the kinetic inductance (and not geometric inductance) of superconducting nanowire loops, which have already shown many fascinating properties (Aprili 2006 Nat. Nanotechnol. 1 15; Hopkins et al 2005 Science 308 1762). This allows much smaller devices and naturally eliminates magnetic-field cross-talk. We demonstrate that the vorticity, i.e., the winding number of the order parameter, of a closed superconducting loop can be used for realizing a nanoscale nonvolatile memory device. We demonstrate how to alter the vorticity in a controlled fashion by applying calibrated current pulses. A reliable read-out of the memory is also demonstrated. We present arguments that such memory can be developed to operate without energy dissipation.

Impacts of post-metallization annealing on the memory performance of Ti/HfO2-based resistive memory

International Nuclear Information System (INIS)

Chen, Pang-Shiu; Chen, Yu-Sheng; Lee, Heng-Yuan

2013-01-01

Impacts of post-metallization annealing (PMA) on bipolar resistance switching of Ti/HfO x stacked films were investigated. A Ti capping film as a scavenging layer with assistance of PMA is used to tune the dielectric strength of the 10-nm-thick HfO x layer. The polycrystalline microstructure of 10-nm-thick HfO x seems immune to the temperature of PMA in this work. The initial resistance and forming voltage in the Ti/HfO x devices mitigate as the increment of the annealing temperature. With enough annealing temperature (>450 °C), the device shows a good on/off ratio, high temperature operation ability and robust endurance (>10 6 cycles). Through the reaction between Ti and HfO x at 500 °C, the abundant oxygen ions are depleted from the insulator and the left charge-defects building conductive percolative paths in the dielectric layer. The operation-polarity independence of the form-free HfO x device in initial state is demonstrated. The forming-free memory with initial low resistance of 800 Ω at 0.1 V can be operated with stable bipolar resistance switching via initially positive or negative voltage sweep. The formless device with 10 nm thick HfO x also exhibits excellent nonvolatile memory performances, including enough on/off ratio, improved HRS uniformity and good high temperature retention (3 × 10 4 s at 200 °C). The results of this work suggest that the PMA temperature will affect the memory window and cycling reliability of the Ti/HfO x -based resistive memory. Optimum temperature (450 °C) will improve the memory performance of the Ti/HfO x stacked layer. (paper)

Writing to and reading from a nano-scale crossbar memory based on memristors

International Nuclear Information System (INIS)

Vontobel, Pascal O; Robinett, Warren; Kuekes, Philip J; Stewart, Duncan R; Straznicky, Joseph; Stanley Williams, R

2009-01-01

We present a design study for a nano-scale crossbar memory system that uses memristors with symmetrical but highly nonlinear current-voltage characteristics as memory elements. The memory is non-volatile since the memristors retain their state when un-powered. In order to address the nano-wires that make up this nano-scale crossbar, we use two coded demultiplexers implemented using mixed-scale crossbars (in which CMOS-wires cross nano-wires and in which the crosspoint junctions have one-time configurable memristors). This memory system does not utilize the kind of devices (diodes or transistors) that are normally used to isolate the memory cell being written to and read from in conventional memories. Instead, special techniques are introduced to perform the writing and the reading operation reliably by taking advantage of the nonlinearity of the type of memristors used. After discussing both writing and reading strategies for our memory system in general, we focus on a 64 x 64 memory array and present simulation results that show the feasibility of these writing and reading procedures. Besides simulating the case where all device parameters assume exactly their nominal value, we also simulate the much more realistic case where the device parameters stray around their nominal value: we observe a degradation in margins, but writing and reading is still feasible. These simulation results are based on a device model for memristors derived from measurements of fabricated devices in nano-scale crossbars using Pt and Ti nano-wires and using oxygen-depleted TiO 2 as the switching material.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Science.gov (United States)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2016-04-01

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Fast, Capacious Disk Memory Device

Science.gov (United States)

Muller, Ronald M.

1990-01-01

Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

Printing an ITO-free flexible poly (4-vinylphenol) resistive switching device

Science.gov (United States)

Ali, Junaid; Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Aziz, Shahid; Choi, Kyung Hyun

2018-02-01

Resistive switching in a sandwich structure of silver (Ag)/Polyvinyl phenol (PVP)/carbon nanotube (CNTs)-silver nanowires (AgNWs) coated on a flexible PET substrate is reported in this work. Densely populated networks of one dimensional nano materials (1DNM), CNTs-AgNWs have been used as the conductive bottom electrode with the prominent features of high flexibility and low sheet resistance of 90 Ω/sq. Thin, yet uniform active layer of PVP was deposited on top of the spin coated 1DNM thin film through state of the art printing technique of electrohydrodynamic atomization (EHDA) with an average thickness of 170 ± 28 nm. Ag dots with an active area of ∼0.1 mm2 were deposited through roll to plate printing system as the top electrodes to complete the device fabrication of flexible memory device. Our memory device exhibited suitable electrical characteristics with OFF/ON ratio of 100:1, retention time of 60 min and electrical endurance for 100 voltage sweeps without any noticeable decay in performance. The resistive switching characteristics at a low current compliance of 3 nA were also evaluated for the application of low power consumption. This memory device is flexible and can sustain more than 100 bending cycles at a bending diameter of 2 cm with stable HRS and LRS values. Our proposed device shows promise to be used as a future potential nonvolatile memory device in flexible electronics.

High performance superconducting devices enabled by three dimensionally ordered nanodots and/or nanorods

Science.gov (United States)

Goyal, Amit

2013-09-17

Novel articles and methods to fabricate same with self-assembled nanodots and/or nanorods of a single or multicomponent material within another single or multicomponent material for use in electrical, electronic, magnetic, electromagnetic and electrooptical devices is disclosed. Self-assembled nanodots and/or nanorods are ordered arrays wherein ordering occurs due to strain minimization during growth of the materials. A simple method to accomplish this when depositing in-situ films is also disclosed. Device applications of resulting materials are in areas of superconductivity, photovoltaics, ferroelectrics, magnetoresistance, high density storage, solid state lighting, non-volatile memory, photoluminescence, thermoelectrics and in quantum dot lasers.

A stacked memory device on logic 3D technology for ultra-high-density data storage

International Nuclear Information System (INIS)

Kim, Jiyoung; Hong, Augustin J; Kim, Sung Min; Shin, Kyeong-Sik; Song, Emil B; Hwang, Yongha; Xiu, Faxian; Galatsis, Kosmas; Chui, Chi On; Candler, Rob N; Wang, Kang L; Choi, Siyoung; Moon, Joo-Tae

2011-01-01

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

A stacked memory device on logic 3D technology for ultra-high-density data storage

Energy Technology Data Exchange (ETDEWEB)

Kim, Jiyoung; Hong, Augustin J; Kim, Sung Min; Shin, Kyeong-Sik; Song, Emil B; Hwang, Yongha; Xiu, Faxian; Galatsis, Kosmas; Chui, Chi On; Candler, Rob N; Wang, Kang L [Device Research Laboratory, Department of Electrical Engineering, University of California, Los Angeles, CA 90095 (United States); Choi, Siyoung; Moon, Joo-Tae, E-mail: hbt100@ee.ucla.edu [Advanced Technology Development Team and Process Development Team, Memory R and D Center, Samsung Electronics Co. Ltd (Korea, Republic of)

2011-06-24

We have demonstrated, for the first time, a novel three-dimensional (3D) memory chip architecture of stacked-memory-devices-on-logic (SMOL) achieving up to 95% of cell-area efficiency by directly building up memory devices on top of front-end CMOS devices. In order to realize the SMOL, a unique 3D Flash memory device and vertical integration structure have been successfully developed. The SMOL architecture has great potential to achieve tera-bit level memory density by stacking memory devices vertically and maximizing cell-area efficiency. Furthermore, various emerging devices could replace the 3D memory device to develop new 3D chip architectures.

Flexible spin-orbit torque devices

Energy Technology Data Exchange (ETDEWEB)

Lee, OukJae; You, Long; Jang, Jaewon; Subramanian, Vivek [Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, California 94720 (United States); Salahuddin, Sayeef [Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, California 94720 (United States); Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720 (United States)

2015-12-21

We report on state-of-the-art spintronic devices synthesized and fabricated directly on a flexible organic substrate. Large perpendicular magnetic anisotropy was achieved in ultrathin ferromagnetic heterostructures of Pt/Co/MgO sputtered on a non-rigid plastic substrate at room temperature. Subsequently, a full magnetic reversal of the Co was observed by exploiting the spin orbit coupling in Pt that leads to a spin accumulation at the Pt/Co interface when an in-plane current is applied. Quasi-static measurements show the potential for operating these devices at nano-second speeds. Importantly, the behavior of the devices remained unchanged under varying bending conditions (up to a bending radius of ≈ ±20–30 mm). Furthermore, the devices showed robust operation even after application of 10{sup 6} successive pulses, which is likely sufficient for many flexible applications. Thus, this work demonstrates the potential for integrating high performance spintronic devices on flexible substrates, which could lead to many applications ranging from flexible non-volatile magnetic memory to local magnetic resonance imaging.

Flexible spin-orbit torque devices

International Nuclear Information System (INIS)

Lee, OukJae; You, Long; Jang, Jaewon; Subramanian, Vivek; Salahuddin, Sayeef

2015-01-01

We report on state-of-the-art spintronic devices synthesized and fabricated directly on a flexible organic substrate. Large perpendicular magnetic anisotropy was achieved in ultrathin ferromagnetic heterostructures of Pt/Co/MgO sputtered on a non-rigid plastic substrate at room temperature. Subsequently, a full magnetic reversal of the Co was observed by exploiting the spin orbit coupling in Pt that leads to a spin accumulation at the Pt/Co interface when an in-plane current is applied. Quasi-static measurements show the potential for operating these devices at nano-second speeds. Importantly, the behavior of the devices remained unchanged under varying bending conditions (up to a bending radius of ≈ ±20–30 mm). Furthermore, the devices showed robust operation even after application of 10 6 successive pulses, which is likely sufficient for many flexible applications. Thus, this work demonstrates the potential for integrating high performance spintronic devices on flexible substrates, which could lead to many applications ranging from flexible non-volatile magnetic memory to local magnetic resonance imaging

Demonstration of Novel Sampling Techniques for Measurement of Turbine Engine Volatile and Non-Volatile Particulate Matter (PM) Emissions

Science.gov (United States)

2017-03-06

WP-201317) Demonstration of Novel Sampling Techniques for Measurement of Turbine Engine Volatile and Non-volatile Particulate Matter (PM... Engine Volatile and Non-Volatile Particulate Matter (PM) Emissions 6. AUTHOR(S) E. Corporan, M. DeWitt, C. Klingshirn, M.D. Cheng, R. Miake-Lye, J. Peck...the performance and viability of two devices to condition aircraft turbine engine exhaust to allow the accurate measurement of total (volatile and non

Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory

Science.gov (United States)

Wang, Yong; Zheng, Yonghui; Liu, Guangyu; Li, Tao; Guo, Tianqi; Cheng, Yan; Lv, Shilong; Song, Sannian; Ren, Kun; Song, Zhitang

2018-03-01

To bridge the gap of access time between memories and storage systems, the concept of storage class memory has been put forward based on emerging nonvolatile memory technologies. For all the nonvolatile memory candidates, the unpleasant tradeoff between operation speed and retention seems to be inevitable. To promote both the write speed and the retention of phase change memory (PCM), Sc doped Ge2Sb2Te5 (SGST) has been proposed as the storage medium. Octahedral Sc-Te motifs, acting as crystallization precursors to shorten the nucleation incubation period, are the possible reason for the high write speed of 6 ns in PCM cells, five-times faster than that of Ge2Sb2Te5 (GST) cells. Meanwhile, an enhanced 10-year data retention of 119 °C has been achieved. Benefiting from both the increased crystalline resistance and the inhibited formation of the hexagonal phase, the SGST cell has a 77% reduction in power consumption compared to the GST cell. Adhesion of the SGST/SiO2 interface has been strengthened, attributed to the reduced stress by forming smaller grains during crystallization, guaranteeing the reliability of the device. These improvements have made the SGST material a promising candidate for PCM application.

EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

Energy Technology Data Exchange (ETDEWEB)

Mittal, Sparsh [ORNL; Vetter, Jeffrey S [ORNL

2014-01-01

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item within a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.

Formation of the distributed NiSiGe nanocrystals nonvolatile memory formed by rapidly annealing in N2 and O2 ambient

International Nuclear Information System (INIS)

Hu, Chih-Wei; Chang, Ting-Chang; Tu, Chun-Hao; Chiang, Cheng-Neng; Lin, Chao-Cheng; Chen, Min-Chen; Chang, Chun-Yen; Sze, Simon M.; Tseng, Tseung-Yuen

2010-01-01

In this work, electrical characteristics of the Ge-incorporated Nickel silicide (NiSiGe) nanocrystals memory device formed by the rapidly thermal annealing in N 2 and O 2 ambient have been studied. The trapping layer was deposited by co-sputtering the NiSi 2 and Ge, simultaneously. Transmission electron microscope results indicate that the NiSiGe nanocrystals were formed obviously in both the samples. The memory devices show obvious charge-storage ability under capacitance-voltage measurement. However, it is found that the NiSiGe nanocrystals device formed by annealing in N 2 ambient has smaller memory window and better retention characteristics than in O 2 ambient. Then, related material analyses were used to confirm that the oxidized Ge elements affect the charge-storage sites and the electrical performance of the NCs memory.

Characterizations of MoTiO5 flash memory devices with post-annealing

International Nuclear Information System (INIS)

Kao, Chyuan Haur; Chen, Hsiang; Chen, Su Zhien; Chen, Yu Jie; Chu, Yu Cheng

2014-01-01

In this study, high-K MoTiO 5 dielectrics were applied as charge trapping layers in fabricated metal-oxide-high-K MoTiO 5 -oxide-Si-type memory devices. Among the applied MoTiO 5 trapping layer treatment conditions, annealing at 900 °C yielded devices that exhibited superior memory performance, such as a larger memory window and faster programming/erasing speed. Multiple material analyses, namely X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy, confirmed that annealing at 900 °C can improve the material quality as a result of crystallization. The fabricated MoTiO 5 -based memory devices show potential for future commercial memory device applications. - Highlights: • MoTiO5-based flash memories have been fabricated. • MoTiO5 trapping layers could be formed by co-sputtering. • MoTiO5 layers with annealing exhibited a good memory performance. • Multiple material analyses confirm that annealing enhanced crystallization

Leakage current characteristics of the multiple metal alloy nanodot memory

International Nuclear Information System (INIS)

Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Chel; Tanaka, Tetsu

2010-01-01

The leakage current characteristics of a multiple metal alloy nanodot device for a nonvolatile random access memory using FePt materials are investigated. Several annealing conditions are evaluated and optimized to suppress the leakage current and to better the memory characterisctics. This work confirmed that the annealing condition of 700 .deg. C in a high vacuum ambience (under 1 x 10 -5 Pa) simultaneously provided good cell characteristics from a high dot density of over 1 x 10 13 /cm 2 and a low leakage current. In addition, a smaller nanodot diameter was found to give a lower leakage current for the multiple nanodot memory. Finally, for the proposed annealing condition, the quadruple FePt multiple nanodot memory with a 2-nm dot diameter provided good leakage current characteristics, showing a threshold voltage shift of under 5% at an initial retention stage of 1000 sec.

Investigation on amorphous InGaZnO based resistive switching memory with low-power, high-speed, high reliability

Energy Technology Data Exchange (ETDEWEB)

Fan, Yang-Shun [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China); Liu, Po-Tsun, E-mail: ptliu@mail.nctu.edu.tw [Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China); Hsu, Ching-Hui [Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China)

2013-12-31

Recently, non-volatile memory (NVM) has been widely used in electronic devices. Nowadays, the prevailing NVM is Flash memory. However, it is generally believed that the conventional Flash memory will approach its scaling limit within about a decade. The resistive random access memory (RRAM) is emerging as one of the potential candidates for future memory replacement because of its high storage density, low power consumption as well as simple structure. The purpose of this work is to develop a reliable a-InGaZnO based resistive switching memory. We investigate the resistive switching characteristics of TiN/Ti/IGZO/Pt structure and TiN/IGZO/Pt structure. The device with TiN/Ti/IGZO/Pt structure exhibits stable bipolar resistive switching. The impact of inserting a Ti interlayer is studied by material analyses. The device shows excellent resistive switching properties. For example, the DC sweep endurance can achieve over 1000 times; and the pulse induced switching cycles can reach at least 10,000 times. Furthermore, the impact of different sputtering ambience, the variable temperature measurement, and the conduction mechanisms are also investigated. According to our experiments, we propose a model to explain the resistive switching phenomenon observed in our devices.

Demonstration of Ultra-Fast Switching in Nano metallic Resistive Switching Memory Devices

International Nuclear Information System (INIS)

Yang, Y.

2016-01-01

Interdependency of switching voltage and time creates a dilemma/obstacle for most resistive switching memories, which indicates low switching voltage and ultra-fast switching time cannot be simultaneously achieved. In this paper, an ultra-fast (sub-100 ns) yet low switching voltage resistive switching memory device (“nano metallic ReRAM”) was demonstrated. Experimental switching voltage is found independent of pulse width (intrinsic device property) when the pulse is long but shows abrupt time dependence (“cliff”) as pulse width approaches characteristic RC time of memory device (extrinsic device property). Both experiment and simulation show that the onset of cliff behavior is dependent on physical device size and parasitic resistance, which is expected to diminish as technology nodes shrink down. We believe this study provides solid evidence that nano metallic resistive switching memory can be reliably operated at low voltage and ultra-fast regime, thus beneficial to future memory technology.

Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials.

Science.gov (United States)

Wang, Weijie; Loke, Desmond; Shi, Luping; Zhao, Rong; Yang, Hongxin; Law, Leong-Tat; Ng, Lung-Tat; Lim, Kian-Guan; Yeo, Yee-Chia; Chong, Tow-Chong; Lacaita, Andrea L

2012-01-01

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory.

Resistively heated shape memory polymer device

Energy Technology Data Exchange (ETDEWEB)

Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

2017-09-05

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Resistively heated shape memory polymer device

Energy Technology Data Exchange (ETDEWEB)

Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

2016-10-25

A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

Magnetization switching schemes for nanoscale three-terminal spintronics devices

Science.gov (United States)

Fukami, Shunsuke; Ohno, Hideo

2017-08-01

Utilizing spintronics-based nonvolatile memories in integrated circuits offers a promising approach to realize ultralow-power and high-performance electronics. While two-terminal devices with spin-transfer torque switching have been extensively developed nowadays, there has been a growing interest in devices with a three-terminal structure. Of primary importance for applications is the efficient manipulation of magnetization, corresponding to information writing, in nanoscale devices. Here we review the studies of current-induced domain wall motion and spin-orbit torque-induced switching, which can be applied to the write operation of nanoscale three-terminal spintronics devices. For domain wall motion, the size dependence of device properties down to less than 20 nm will be shown and the underlying mechanism behind the results will be discussed. For spin-orbit torque-induced switching, factors governing the threshold current density and strategies to reduce it will be discussed. A proof-of-concept demonstration of artificial intelligence using an analog spin-orbit torque device will also be reviewed.

Nanoscale superconducting memory based on the kinetic inductance of asymmetric nanowire loops

International Nuclear Information System (INIS)

Murphy, Andrew; Bezryadin, Alexey; Averin, Dmitri V

2017-01-01

The demand for low-dissipation nanoscale memory devices is as strong as ever. As Moore’s law is staggering, and the demand for a low-power-consuming supercomputer is high, the goal of making information processing circuits out of superconductors is one of the central goals of modern technology and physics. So far, digital superconducting circuits could not demonstrate their immense potential. One important reason for this is that a dense superconducting memory technology is not yet available. Miniaturization of traditional superconducting quantum interference devices is difficult below a few micrometers because their operation relies on the geometric inductance of the superconducting loop. Magnetic memories do allow nanometer-scale miniaturization, but they are not purely superconducting (Baek et al 2014 Nat. Commun. 5 3888). Our approach is to make nanometer scale memory cells based on the kinetic inductance (and not geometric inductance) of superconducting nanowire loops, which have already shown many fascinating properties (Aprili 2006 Nat. Nanotechnol. 1 15; Hopkins et al 2005 Science 308 1762). This allows much smaller devices and naturally eliminates magnetic-field cross-talk. We demonstrate that the vorticity, i.e., the winding number of the order parameter, of a closed superconducting loop can be used for realizing a nanoscale nonvolatile memory device. We demonstrate how to alter the vorticity in a controlled fashion by applying calibrated current pulses. A reliable read-out of the memory is also demonstrated. We present arguments that such memory can be developed to operate without energy dissipation. (paper)

Subattoampere current induced by single ions in silicon oxide layers of nonvolatile memory cells

International Nuclear Information System (INIS)

Cellere, G.; Paccagnella, A.; Larcher, L.; Visconti, A.; Bonanomi, M.

2006-01-01

A single ion impinging on a thin silicon dioxide layer generates a number of electron/hole pairs proportional to its linear energy transfer coefficient. Defects generated by recombination can act as a conductive path for electrons that cross the oxide barrier, thanks to a multitrap-assisted mechanism. We present data on the dependence of this phenomenon on the oxide thickness by using floating gate memory arrays. The tiny number of excess electrons stored in these devices allows for extremely high sensitivity, impossible with any direct measurement of oxide leakage current. Results are of particular interest for next generation devices

Defect states and charge trapping characteristics of HfO2 films for high performance nonvolatile memory applications

International Nuclear Information System (INIS)

Zhang, Y.; Shao, Y. Y.; Lu, X. B.; Zeng, M.; Zhang, Z.; Gao, X. S.; Zhang, X. J.; Liu, J.-M.; Dai, J. Y.

2014-01-01

In this work, we present significant charge trapping memory effects of the metal-hafnium oxide-SiO 2 -Si (MHOS) structure. The devices based on 800 °C annealed HfO 2 film exhibit a large memory window of ∼5.1 V under ±10 V sweeping voltages and excellent charge retention properties with only small charge loss of ∼2.6% after more than 10 4  s retention. The outstanding memory characteristics are attributed to the high density of deep defect states in HfO 2 films. We investigated the defect states in the HfO 2 films by photoluminescence and photoluminescence excitation measurements and found that the defect states distributed in deep energy levels ranging from 1.1 eV to 2.9 eV below the conduction band. Our work provides further insights for the charge trapping mechanisms of the HfO 2 based MHOS devices.

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

International Nuclear Information System (INIS)

Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

2011-01-01

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO 2 /Ta 2 O 5 charge-trapping layer. In comparison to a memory capacitor with a single HfO 2 trapping layer, the erase speed of a memory capacitor with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔV FB = 4 V, the device with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO 2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application

Resistive switching characteristics of solution-processed organic-inorganic blended films for flexible memory applications

Science.gov (United States)

Baek, Il-Jin; Cho, Won-Ju

2018-02-01

We developed a hybrid organic-inorganic resistive random access memory (ReRAM) device that uses a solution-process to overcome the disadvantages of organic and inorganic materials for flexible memory applications. The drawbacks of organic and inorganic materials are a poor electrical characteristics and a lack of flexibility, respectively. We fabricated a hybrid organic-inorganic switching layer of ReRAM by blending HfOx or AlOx solution with PMMA solution and investigated the resistive switching behaviour in Ti/PMMA/Pt, Ti/PMMA-HfOx/Pt and Ti/PMMA-AlOx/Pt structures. It is found that PMMA-HfOx or PMMA-AlOx hybrid switching layer has a larger memory window, more stable durability and retention characteristics, and a better set/reset voltage distribution than PMMA layer. Further, it is confirmed that the flexibility of the PMMA-HfOx and PMMA-AlOx blended films was almost similar to that of the organic PMMA film. Thus, the solution-processed organic-inorganic blended films are considered a promising material for a non-volatile memory device on a flexible or wearable electronic system.

Ga-doped indium oxide nanowire phase change random access memory cells

International Nuclear Information System (INIS)

Jin, Bo; Lee, Jeong-Soo; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I; Kim, Hyoung Seop; Meyyappan, M

2014-01-01

Phase change random access memory (PCRAM) devices are usually constructed using tellurium based compounds, but efforts to seek other materials providing desirable memory characteristics have continued. We have fabricated PCRAM devices using Ga-doped In 2 O 3 nanowires with three different Ga compositions (Ga/(In+Ga) atomic ratio: 2.1%, 11.5% and 13.0%), and investigated their phase switching properties. The nanowires (∼40 nm in diameter) can be repeatedly switched between crystalline and amorphous phases, and Ga concentration-dependent memory switching behavior in the nanowires was observed with ultra-fast set/reset rates of 80 ns/20 ns, which are faster than for other competitive phase change materials. The observations of fast set/reset rates and two distinct states with a difference in resistance of two to three orders of magnitude appear promising for nonvolatile information storage. Moreover, we found that increasing the Ga concentration can reduce the power consumption and resistance drift; however, too high a level of Ga doping may cause difficulty in achieving the phase transition. (paper)

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

Science.gov (United States)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

International Nuclear Information System (INIS)

Riggert, C; Ziegler, M; Kohlstedt, H; Schroeder, D; Krautschneider, W H

2014-01-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit. (paper)

Impacts of Co doping on ZnO transparent switching memory device characteristics

Energy Technology Data Exchange (ETDEWEB)

Simanjuntak, Firman Mangasa; Wei, Kung-Hwa [Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Prasad, Om Kumar [Department of Electrical Engineering and Computer Science, National Chiao Tung University, Hsinchu 30010, Taiwan (China); Panda, Debashis [Department of Electronics Engineering, National Institute of Science and Technology, Berhampur, Odisha 761008 (India); Lin, Chun-An; Tsai, Tsung-Ling; Tseng, Tseung-Yuen, E-mail: tseng@cc.nctu.edu.tw [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010, Taiwan (China)

2016-05-02

The resistive switching characteristics of indium tin oxide (ITO)/Zn{sub 1−x}Co{sub x}O/ITO transparent resistive memory devices were investigated. An appropriate amount of cobalt dopant in ZnO resistive layer demonstrated sufficient memory window and switching stability. In contrast, pure ZnO devices demonstrated a poor memory window, and using an excessive dopant concentration led to switching instability. To achieve suitable memory performance, relying only on controlling defect concentrations is insufficient; the grain growth orientation of the resistive layer must also be considered. Stable endurance with an ON/OFF ratio of more than one order of magnitude during 5000 cycles confirmed that the Co-doped ZnO device is a suitable candidate for resistive random access memory application. Additionally, fully transparent devices with a high transmittance of up to 90% at wavelength of 550 nm have been fabricated.

High performance electrical, magnetic, electromagnetic and electrooptical devices enabled by three dimensionally ordered nanodots and nanorods

Science.gov (United States)

Goyal, Amit , Kang; Sukill, [Knoxville, TN

2012-02-21

Novel articles and methods to fabricate same with self-assembled nanodots and/or nanorods of a single or multicomponent material within another single or multicomponent material for use in electrical, electronic, magnetic, electromagnetic and electrooptical devices is disclosed. Self-assembled nanodots and/or nanorods are ordered arrays wherein ordering occurs due to strain minimization during growth of the materials. A simple method to accomplish this when depositing in-situ films is also disclosed. Device applications of resulting materials are in areas of superconductivity, photovoltaics, ferroelectrics, magnetoresistance, high density storage, solid state lighting, non-volatile memory, photoluminescence, thermoelectrics and in quantum dot lasers.

Flexible and twistable non-volatile memory cell array with all-organic one diode-one resistor architecture.

Science.gov (United States)

Ji, Yongsung; Zeigler, David F; Lee, Dong Su; Choi, Hyejung; Jen, Alex K-Y; Ko, Heung Cho; Kim, Tae-Wook

2013-01-01

Flexible organic memory devices are one of the integral components for future flexible organic electronics. However, high-density all-organic memory cell arrays on malleable substrates without cross-talk have not been demonstrated because of difficulties in their fabrication and relatively poor performances to date. Here we demonstrate the first flexible all-organic 64-bit memory cell array possessing one diode-one resistor architectures. Our all-organic one diode-one resistor cell exhibits excellent rewritable switching characteristics, even during and after harsh physical stresses. The write-read-erase-read output sequence of the cells perfectly correspond to the external pulse signal regardless of substrate deformation. The one diode-one resistor cell array is clearly addressed at the specified cells and encoded letters based on the standard ASCII character code. Our study on integrated organic memory cell arrays suggests that the all-organic one diode-one resistor cell architecture is suitable for high-density flexible organic memory applications in the future.

General observation of the memory effect in metal-insulator-ITO structures due to indium diffusion

International Nuclear Information System (INIS)

Wu, Xiaojing; Xu, Huihua; Zhao, Ni; Wang, Yu; Rogach, Andrey L; Shen, Yingzhong

2015-01-01

Resistive random access memory (RRAM) devices based on metal oxides, organic molecules and inorganic nanocrystals (NCs) have been studied extensively in recent years. Different memory switching mechanisms have been proposed and shown to be closely related to the device architectures. In this work, we demonstrate that the use of an ITO/active layer/InGa structure can yield nonvolatile resistive memory behavior in a variety of active materials, including polymers, organic small molecules, and colloidal NCs. Through the electrode material and thickness-dependent study, we show that the ON state of the devices is associated with filamentary conduction induced by indium diffusion from the ITO electrode, occurring mostly within around 40–50 nm from the ITO/active layer interface. A negative differential resistance (NDR) regime is observed during transition from the ON to OFF state, and is explained by the space charge limited current (SCLC) effect due to hole injection at the ITO/active layer interface. Our study reveals the impact of indium diffusion at the ITO/active layer interface, an important factor that should be taken into consideration when designing thin printed RRAM devices. (paper)

Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

International Nuclear Information System (INIS)

Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming

2017-01-01

The attractive usability of quantum phenomena in futuristic devices is possible by using zero-dimensional systems like nanocrystals (NCs). The performance of nonvolatile flash memory devices has greatly benefited from the use of NCs over recent decades. The quantum abilities of NCs have been used to improve the reliability of flash devices. Its appeal is extended to the design of emerging devices such as resistive random-access memory (RRAM), a technology where the use of silicon is optional. Here, we are going to review the recent progress in the design, characterization, and utilization of NCs in RRAM devices. We will first introduce the physical design of the RRAM devices using NCs and the improvement of electrical performance in NC-RRAM over conventional ones. In particular, special care has been taken to review the ways of development provided by the NCs in the RRAM devices. In a broad sense, the NCs can play a charge trapping role in the NC-RRAM structure or it can be responsible for the localization and improvement of the stability of the conductive filament or it can play a part in the formation of the conductive filament chain by the NC migration under applied bias. Finally, the scope of NCs in the RRAM devices has also been discussed. (topical review)

Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

Science.gov (United States)

Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming