WorldWideScience

Sample records for nonvolatile flash memories

  1. Graphene-quantum-dot nonvolatile charge-trap flash memories

    International Nuclear Information System (INIS)

    Sin Joo, Soong; Kim, Jungkil; Seok Kang, Soo; Kim, Sung; Choi, Suk-Ho; Won Hwang, Sung

    2014-01-01

    Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO 2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO 2 on a p-type wafer, spin-coating of GQDs on the SiO 2 layer, and IBSD of 20 nm SiO 2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO 2 /Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance–voltage curves is proportional to d for sweep voltages wider than  ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of  ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement. (papers)

  2. Non-volatile memories

    CERN Document Server

    Lacaze, Pierre-Camille

    2014-01-01

    Written for scientists, researchers, and engineers, Non-volatile Memories describes the recent research and implementations in relation to the design of a new generation of non-volatile electronic memories. The objective is to replace existing memories (DRAM, SRAM, EEPROM, Flash, etc.) with a universal memory model likely to reach better performances than the current types of memory: extremely high commutation speeds, high implantation densities and retention time of information of about ten years.

  3. Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

    International Nuclear Information System (INIS)

    Miura, Atsushi; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi; Tsukamoto, Rikako; Yoshii, Shigeo

    2008-01-01

    We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co 3 O 4 ) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented

  4. Nonvolatile Memory Technology for Space Applications

    Science.gov (United States)

    Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

    2010-01-01

    This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

  5. Nonvolatile memory design magnetic, resistive, and phase change

    CERN Document Server

    Li, Hai

    2011-01-01

    The manufacture of flash memory, which is the dominant nonvolatile memory technology, is facing severe technical barriers. So much so, that some emerging technologies have been proposed as alternatives to flash memory in the nano-regime. Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing introduces three promising candidates: phase-change memory, magnetic random access memory, and resistive random access memory. The text illustrates the fundamental storage mechanism of these technologies and examines their differences from flash memory techniques. Based on the latest advances,

  6. Emerging non-volatile memories

    CERN Document Server

    Hong, Seungbum; Wouters, Dirk

    2014-01-01

    This book is an introduction to the fundamentals of emerging non-volatile memories and provides an overview of future trends in the field. Readers will find coverage of seven important memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), Multiferroic RAM (MFRAM), Phase-Change Memories (PCM), Oxide-based Resistive RAM (RRAM), Probe Storage, and Polymer Memories. Chapters are structured to reflect diffusions and clashes between different topics. Emerging Non-Volatile Memories is an ideal book for graduate students, faculty, and professionals working in the area of non-volatile memory. This book also: Covers key memory technologies, including Ferroelectric Random Access Memory (FeRAM), Ferromagnetic RAM (FMRAM), and Multiferroic RAM (MFRAM), among others. Provides an overview of non-volatile memory fundamentals. Broadens readers' understanding of future trends in non-volatile memories.

  7. Overview of emerging nonvolatile memory technologies.

    Science.gov (United States)

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  8. Overview of emerging nonvolatile memory technologies

    Science.gov (United States)

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  9. GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

    Energy Technology Data Exchange (ETDEWEB)

    Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P. [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India); Mukherjee, Rabibrata [Department of Chemical Engineering, Indian Institute of Technology, Kharagpur 721302 (India)

    2015-06-24

    Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

  10. Non Volatile Flash Memory Radiation Tests

    Science.gov (United States)

    Irom, Farokh; Nguyen, Duc N.; Allen, Greg

    2012-01-01

    Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.

  11. NAND flash memory technologies

    CERN Document Server

    Aritome, Seiichi

    2016-01-01

    This book discusses basic and advanced NAND flash memory technologies, including the principle of NAND flash, memory cell technologies, multi-bits cell technologies, scaling challenges of memory cell, reliability, and 3-dimensional cell as the future technology. Chapter 1 describes the background and early history of NAND flash. The basic device structures and operations are described in Chapter 2. Next, the author discusses the memory cell technologies focused on scaling in Chapter 3, and introduces the advanced operations for multi-level cells in Chapter 4. The physical limitations for scaling are examined in Chapter 5, and Chapter 6 describes the reliability of NAND flash memory. Chapter 7 examines 3-dimensional (3D) NAND flash memory cells and discusses the pros and cons in structure, process, operations, scalability, and performance. In Chapter 8, challenges of 3D NAND flash memory are dis ussed. Finally, in Chapter 9, the author summarizes and describes the prospect of technologies and market for the fu...

  12. Non-volatile memory based on the ferroelectric photovoltaic effect

    Science.gov (United States)

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  13. Organic Nonvolatile Memory Devices Based on Ferroelectricity

    NARCIS (Netherlands)

    Naber, Ronald C. G.; Asadi, Kamal; Blom, Paul W. M.; de Leeuw, Dago M.; de Boer, Bert

    2010-01-01

    A memory functionality is a prerequisite for many applications of electronic devices. Organic nonvolatile memory devices based on ferroelectricity are a promising approach toward the development of a low-cost memory technology. In this Review Article we discuss the latest developments in this area

  14. Organic nonvolatile memory devices based on ferroelectricity

    NARCIS (Netherlands)

    Naber, R.C.G.; Asadi, K.; Blom, P.W.M.; Leeuw, D.M. de; Boer, B. de

    2010-01-01

    A memory functionality is a prerequisite for many applications of electronic devices. Organic nonvolatile memory devices based on ferroelectricity are a promising approach toward the development of a low-cost memory technology. In this Review Article we discuss the latest developments in this area

  15. Carbon nanomaterials for non-volatile memories

    Science.gov (United States)

    Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

    2018-03-01

    Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

  16. Flash memories economic principles of performance, cost and reliability optimization

    CERN Document Server

    Richter, Detlev

    2014-01-01

    The subject of this book is to introduce a model-based quantitative performance indicator methodology applicable for performance, cost and reliability optimization of non-volatile memories. The complex example of flash memories is used to introduce and apply the methodology. It has been developed by the author based on an industrial 2-bit to 4-bit per cell flash development project. For the first time, design and cost aspects of 3D integration of flash memory are treated in this book. Cell, array, performance and reliability effects of flash memories are introduced and analyzed. Key performance parameters are derived to handle the flash complexity. A performance and array memory model is developed and a set of performance indicators characterizing architecture, cost and durability is defined.   Flash memories are selected to apply the Performance Indicator Methodology to quantify design and technology innovation. A graphical representation based on trend lines is introduced to support a requirement based pr...

  17. Nonvolatile Rad-Hard Holographic Memory

    Science.gov (United States)

    Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

    2001-01-01

    We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

  18. Electrostatically telescoping nanotube nonvolatile memory device

    International Nuclear Information System (INIS)

    Kang, Jeong Won; Jiang Qing

    2007-01-01

    We propose a nonvolatile memory based on carbon nanotubes (CNTs) serving as the key building blocks for molecular-scale computers and investigate the dynamic operations of a double-walled CNT memory element by classical molecular dynamics simulations. The localized potential energy wells achieved from both the interwall van der Waals energy and CNT-metal binding energy make the bistability of the CNT positions and the electrostatic attractive forces induced by the voltage differences lead to the reversibility of this CNT memory. The material for the electrodes should be carefully chosen to achieve the nonvolatility of this memory. The kinetic energy of the CNT shuttle experiences several rebounds induced by the collisions of the CNT onto the metal electrodes, and this is critically important to the performance of such an electrostatically telescoping CNT memory because the collision time is sufficiently long to cause a delay of the state transition

  19. Physical principles and current status of emerging non-volatile solid state memories

    Science.gov (United States)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  20. Flexible graphene–PZT ferroelectric nonvolatile memory

    International Nuclear Information System (INIS)

    Lee, Wonho; Ahn, Jong-Hyun; Kahya, Orhan; Toh, Chee Tat; Özyilmaz, Barbaros

    2013-01-01

    We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr 0.35 ,Ti 0.65 )O 3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (P r ) of 30 μC cm −2 and a coercive voltage (V c ) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits. (paper)

  1. Flexible graphene-PZT ferroelectric nonvolatile memory.

    Science.gov (United States)

    Lee, Wonho; Kahya, Orhan; Toh, Chee Tat; Ozyilmaz, Barbaros; Ahn, Jong-Hyun

    2013-11-29

    We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr0.35,Ti0.65)O3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (Pr) of 30 μC cm−2 and a coercive voltage (Vc) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.

  2. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    Science.gov (United States)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  3. The influence of thickness on memory characteristic based on nonvolatile tuning behavior in poly(N-vinylcarbazole) films

    International Nuclear Information System (INIS)

    Sun, Yanmei; Ai, Chunpeng; Lu, Junguo; Li, Lei; Wen, Dianzhong; Bai, Xuduo

    2016-01-01

    The memory characteristic based on nonvolatile tuning behavior in indium tin oxide/poly(N-vinylcarbazole)/aluminum (ITO/PVK/Al) was investigated, the different memory behaviors were first observed in PVK film as the film thickness changing. By control of PVK film thickness with different spinning speeds, the nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned in a controlled manner. Obviously different nonvolatile behaviors, such as (i) flash memory behavior and (ii) write-once-read-many times (WORM) memory behavior are from the current–voltage (I–V) characteristics of the PVK films. The results suggest that the film thickness plays a key part in determining the memory type of the PVK. - Highlights: • The different memory behaviors were observed in PVK film. • The nonvolatile behavior of ITO/PVK/Al sandwich structure can be tuned. • The film thickness plays a key part in determining the memory type of the PVK.

  4. Radiation evaluation of commercial ferroelectric nonvolatile memories

    International Nuclear Information System (INIS)

    Benedetto, J.M.; DeLancey, W.M.; Oldham, T.R.; McGarrity, J.M.; Tipton, C.W.; Brassington, M.; Fisch, D.E.

    1991-01-01

    This paper reports on ferroelectric (FE) on complementary metal-oxide semiconductor (CMOS) 4-kbit nonvolatile memories, 8-bit octal latches (with and without FE), and process control test chips that were used to establish a baseline characterization of the radiation response of CMOS/FE integrated devices and to determine whether the additional FE processing caused significant degradation to the baseline CMOS process. Functional failure of all 4-kbit memories and octal latches occurred at total doses of between 2 and 4 krad(Si), most likely due to field- oxide effects in the underlying CMOS. No significant difference was observed between the radiation responses of devices with and without the FE film in this commercial process

  5. Fabrication of Nonvolatile Memory Effects in High-k Dielectric Thin Films Using Electron Irradiation

    International Nuclear Information System (INIS)

    Park, Chanrock; Cho, Daehee; Kim, Jeongeun; Hwang, Jinha

    2010-01-01

    Electron Irradiation can be applied towards nano-floating gate memories which are recognized as one of the next-generation nonvolatile memory semiconductors. NFGMs can overcome the preexisting limitations encountered in Dynamic Random Access Memories and Flash memories with the excellent advantages, i. e. high-density information storage, high response speed, high compactness, etc. The traditional nano-floating gate memories are fabricated through multi-layered nano structures of the dissimilar materials where the charge-trapping portions are sandwiched into the high-k dielectrics. However, this work reports the unique nonvolatile responses in single-layered high-k dielectric thin films if irradiated with highly accelerated electron beams. The implications of the electron irradiation will be discussed towards high-performance nano-floating gate memories

  6. The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

    International Nuclear Information System (INIS)

    Tang Zhen-Jie; Li Rong; Yin Jiang

    2013-01-01

    ZrO 2 nanocrystallite-based charge trap flash memory capacitors incorporating a (ZrO 2 ) 0.6 (SiO 2 ) 0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated. The precipitation reaction in the charge trapping layer, forming ZrO 2 nanocrystallites during rapid thermal annealing, was investigated by transmission electron microscopy and X-ray diffraction. It was observed that a ZrO 2 nanocrystallite-based memory capacitor after post-annealing at 850 °C for 60 s exhibits a maximum memory window of about 6.8 V, good endurance and a low charge loss of ∼25% over a period of 10 years (determined by extrapolating the charge loss curve measured experimentally), even at 85 °C. Such 850 °C-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications

  7. Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

    Science.gov (United States)

    Heidecker, Jason

    2010-01-01

    This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

  8. Nonvolatile Memory Materials for Neuromorphic Intelligent Machines.

    Science.gov (United States)

    Jeong, Doo Seok; Hwang, Cheol Seong

    2018-04-18

    Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  9. Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

    Science.gov (United States)

    Hong, Augustin Jinwoo

    Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

  10. A Durable Flash Memory Search Tree

    OpenAIRE

    Clay III, James; Wortman, Kevin

    2012-01-01

    We consider the task of optimizing the B-tree data structure, used extensively in operating systems and databases, for sustainable usage on multi-level flash memory. Empirical evidence shows that this new flash memory tree, or FM Tree, extends the operational lifespan of each block of flash memory by a factor of roughly 27 to 70 times, while still supporting logarithmic-time search tree operations.

  11. Ferroelectric memories: A possible answer to the hardened nonvolatile question

    International Nuclear Information System (INIS)

    Messenger, G.C.; Coppage, F.N.

    1988-01-01

    Ferroelectric memory cells have been fabricated using a process compatible with semiconductor VLSI (Very Large-Scale Integration) manufacturing techniques which are basically nonvolatile and radiation hard. The memory can be made NDRO (Nondestructive Readout) for strategic systems using several techniques; the most practical is probably a rapid read/restore in combination with EDAC software. This memory can replace plated wire and will have substantial advantages in cost, weight, size, power and speed. It provides a practical cost-competitive solution to the need for nonvolatile RAM in all hardened tactical, avionic, and space systems

  12. Method for refreshing a non-volatile memory

    Science.gov (United States)

    Riekels, James E.; Schlesinger, Samuel

    2008-11-04

    A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

  13. Active non-volatile memory post-processing

    Energy Technology Data Exchange (ETDEWEB)

    Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

    2017-04-11

    A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

  14. Organic non-volatile memories from ferroelectric phase separated blends

    Science.gov (United States)

    Asadi, Kamal; de Leeuw, Dago; de Boer, Bert; Blom, Paul

    2009-03-01

    Ferroelectric polarisation is an attractive physical property for non-volatile binary switching. The functionality of the targeted memory should be based on resistive switching. Conductivity and ferroelectricity however cannot be tuned independently. The challenge is to develop a storage medium in which the favourable properties of ferroelectrics such as bistability and non-volatility can be combined with the beneficial properties provided by semiconductors such as conductivity and rectification. In this contribution we present an integrated solution by blending semiconducting and ferroelectric polymers into phase separated networks. The polarisation field of the ferroelectric modulates the injection barrier at the semiconductor--metal contact. This combination allows for solution-processed non-volatile memory arrays with a simple cross-bar architecture that can be read-out non-destructively. Based on this general concept a non-volatile, reversible switchable Schottky diode with relatively fast programming time of shorter than 100 microseconds, long information retention time of longer than 10^ days, and high programming cycle endurance with non-destructive read-out is demonstrated.

  15. Method for programming a flash memory

    Energy Technology Data Exchange (ETDEWEB)

    Brosky, Alexander R.; Locke, William N.; Maher, Conrado M.

    2016-08-23

    A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device.

  16. Use of non-volatile memories for SSC detector readout

    International Nuclear Information System (INIS)

    Fennelly, A.J.; Woosley, J.K.; Johnson, M.B.

    1990-01-01

    Use of non-volatile memory units at the end of each fiber optic bunch/strand would substantially increase information available from experiments by providing a complete event history, in addition to easing real time processing requirements. This may be an alternative to enhancing technology to optical computing techniques. Available and low-risk projected technologies will be surveyed, with costing addressed. Some discussion will be given to covnersion of optical signals, to electronic information, concepts for providing timing pulses to the memory units, and to the magnetoresistive (MRAM) and ferroelectric (FERAM) random access memory technologies that may be utilized in the prototype system

  17. Novel applications of non-volatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Duthie, I

    1982-01-01

    The author reviews briefly the evolution of the programmable memory and the alternative technologies, before discussing the operation of a small EEPROM when used in conjunction with a microprocessor for typical applications. Some applications are reviewed and the opportunities which eeproms can offer for new applications are presented, together with the requirements for artificial intelligence to become a reality.

  18. Design considerations for a radiation hardened nonvolatile memory

    International Nuclear Information System (INIS)

    Murray, J.R.

    1993-01-01

    Sub-optimal design practices can reduce the radiation hardness of a circuit even though it is fabricated in a radiation hardened process. This is especially true for a nonvolatile memory, as compared to a standard digital circuit, where high voltages and unusual bias conditions are required. This paper will discuss the design technique's used in the development of a 64K EEPROM (Electrically Erasable Programmable Read Only Memory) to maximize radiation hardness. The circuit radiation test results will be reviewed in order to provide validation of the techniques

  19. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  20. Channel equalization techniques for non-volatile memristor memories

    KAUST Repository

    Naous, Rawan

    2016-03-16

    Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

  1. Channel equalization techniques for non-volatile memristor memories

    KAUST Repository

    Naous, Rawan; Zidan, Mohammed A.; Salem, Ahmed Sultan; Salama, Khaled N.

    2016-01-01

    Channel coding and information theoretic approaches have been utilized in conventional non-volatile memories to overcome their inherent design limitations of leakage, coupling and refresh rates. However, the continuous scaling and integration constraints set on the current devices directed the attention towards emerging memory technologies as suitable alternatives. Memristive devices are prominent candidates to replace the conventional electronics due to its non-volatility and small feature size. Nonetheless, memristor-based memories still encounter an accuracy limitation throughout the read operation addressed as the sneak path phenomenon. The readout data is corrupted with added distortion that increases significantly the bit error rate and jeopardizes the reliability of the read operation. A novel technique is applied to alleviate this distorting effect where the communication channel model is proposed for the memory array. Noise cancellation principles are applied with the aid of preset pilots to extract channel information and adjust the readout values accordingly. The proposed technique has the virtue of high speed, energy efficiency, and low complexity design while achieving high reliability and error-free decoding.

  2. Organic nonvolatile memory devices with charge trapping multilayer graphene film

    International Nuclear Information System (INIS)

    Ji, Yongsung; Choe, Minhyeok; Cho, Byungjin; Song, Sunghoon; Yoon, Jongwon; Ko, Heung Cho; Lee, Takhee

    2012-01-01

    We fabricated an array-type organic nonvolatile memory device with multilayer graphene (MLG) film embedded in polyimide (PI) layers. The memory devices showed a high ON/OFF ratio (over 10 6 ) and a long retention time (over 10 4 s). The switching of the Al/PI/MLG/PI/Al memory devices was due to the presence of the MLG film inserted into the PI layers. The double-log current–voltage characteristics could be explained by the space-charge-limited current conduction based on a charge-trap model. A conductive atomic force microscopy found that the conduction paths in the low-resistance ON state were distributed in a highly localized area, which was associated with a carbon-rich filamentary switching mechanism. (paper)

  3. Nonvolatile memory effect of tungsten nanocrystals under oxygen plasma treatments

    International Nuclear Information System (INIS)

    Chen, Shih-Cheng; Chang, Ting-Chang; Chen, Wei-Ren; Lo, Yuan-Chun; Wu, Kai-Ting; Sze, S.M.; Chen, Jason; Liao, I.H.; Yeh, Fon-Shan

    2010-01-01

    In this work, an oxygen plasma treatment was used to improve the memory effect of nonvolatile W nanocrystal memory, including memory window, retention and endurance. To investigate the role of the oxygen plasma treatment in charge storage characteristics, the X-ray photon-emission spectra (XPS) were performed to analyze the variation of chemical composition for W nanocrystal embedded oxide both with and without the oxygen plasma treatment. In addition, the transmission electron microscopy (TEM) analyses were also used to identify the microstructure in the thin film and the size and density of W nanocrystals. The device with the oxygen plasma treatment shows a significant improvement of charge storage effect, because the oxygen plasma treatment enhanced the quality of silicon oxide surrounding the W nanocrystals. Therefore, the data retention and endurance characteristics were also improved by the passivation.

  4. Non-volatile memory devices with redox-active diruthenium molecular compound

    International Nuclear Information System (INIS)

    Pookpanratana, S; Zhu, H; Bittle, E G; Richter, C A; Li, Q; Hacker, C A; Natoli, S N; Ren, T

    2016-01-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al 2 O 3 /molecule/SiO 2 /Si structure. The bulky ruthenium redox molecule is attached to the surface by using a ‘click’ reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The ‘click’ reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices. (paper)

  5. A hybrid ferroelectric-flash memory cells

    Science.gov (United States)

    Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

    2014-09-01

    A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

  6. Highly Stretchable Non-volatile Nylon Thread Memory

    Science.gov (United States)

    Kang, Ting-Kuo

    2016-04-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

  7. Bioorganic nanodots for non-volatile memory devices

    International Nuclear Information System (INIS)

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Natan, Amir; Rosenwaks, Yossi; Litsyn, Simon; Szwarcman, Daniel; Rosenman, Gil; Roizin, Yakov

    2013-01-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ∼2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO 2 surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device

  8. Bioorganic nanodots for non-volatile memory devices

    Energy Technology Data Exchange (ETDEWEB)

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Natan, Amir; Rosenwaks, Yossi [School of Electrical Engineering, Iby and Aladar Fleischman Faculty of Engineering, Tel Aviv University, Tel Aviv 69978 (Israel); Litsyn, Simon; Szwarcman, Daniel; Rosenman, Gil, E-mail: rgil@post.tau.ac.il [School of Electrical Engineering, Iby and Aladar Fleischman Faculty of Engineering, Tel Aviv University, Tel Aviv 69978 (Israel); StoreDot LTD, 16 Menahem Begin St., Ramat Gan (Israel); Roizin, Yakov [School of Electrical Engineering, Iby and Aladar Fleischman Faculty of Engineering, Tel Aviv University, Tel Aviv 69978 (Israel); TowerJazz, P.O. Box 619, Migdal HaEmek 23105 (Israel)

    2013-12-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ∼2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO{sub 2} surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device.

  9. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    Science.gov (United States)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  10. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation hardened nonvolatile memories for space is still primarily confined to EEPROM. There is high density effective or cost effective NVM solution available to...

  11. Anomalous Threshold Voltage Variability of Nitride Based Charge Storage Nonvolatile Memory Devices

    Directory of Open Access Journals (Sweden)

    Meng Chuan Lee

    2013-01-01

    Full Text Available Conventional technology scaling is implemented to meet the insatiable demand of high memory density and low cost per bit of charge storage nonvolatile memory (NVM devices. In this study, effect of technology scaling to anomalous threshold voltage ( variability is investigated thoroughly on postcycled and baked nitride based charge storage NVM devices. After long annealing bake of high temperature, cell’s variability of each subsequent bake increases within stable distribution and found exacerbate by technology scaling. Apparent activation energy of this anomalous variability was derived through Arrhenius plots. Apparent activation energy (Eaa of this anomalous variability is 0.67 eV at sub-40 nm devices which is a reduction of approximately 2 times from 110 nm devices. Technology scaling clearly aggravates this anomalous variability, and this poses reliability challenges to applications that demand strict control, for example, reference cells that govern fundamental program, erase, and verify operations of NVM devices. Based on critical evidence, this anomalous variability is attributed to lateral displacement of trapped charges in nitride storage layer. Reliability implications of this study are elucidated. Moreover, potential mitigation methods are proposed to complement technology scaling to prolong the front-runner role of nitride based charge storage NVM in semiconductor flash memory market.

  12. MoO3 trapping layers with CF4 plasma treatment in flash memory applications

    International Nuclear Information System (INIS)

    Kao, Chuyan Haur; Chen, Hsiang; Chen, Su-Zhien; Chen, Chian Yu; Lo, Kuang-Yu; Lin, Chun Han

    2014-01-01

    Highlights: • MoO 3 -based flash memories have been fabricated. • CF4 plasma treatment could enhance good memory performance. • Material analyses confirm that plasma treatment eliminated defects. • Fluorine atoms might fix the dangling bonds. - Abstract: In this research, we used MoO 3 with CF 4 plasma treatment as charge trapping layer in metal-oxide-high-k -oxide-Si-type memory. We analyzed material properties and electrical characteristics with multiple analyses. The plasma treatment could increase the trapping density, reduce the leakage current, expand band gap, and passivate the defect to enhance the memory performance. The MoO 3 charge trapping layer memory with suitable CF 4 plasma treatment is promising for future nonvolatile memory applications

  13. Silicon nano crystal-based non-volatile memory devices

    International Nuclear Information System (INIS)

    Ng, C.Y.; Chen, T.P.; Sreeduth, D.; Chen, Q.; Ding, L.; Du, A.

    2006-01-01

    In this work, we have investigated the performance and reliability of a Flash memory based on silicon nanocrystal synthesized with very-low energy ion beams. The devices are fabricated with a conventional CMOS process and the size of the nanocrystal is ∼ 4 nm as determined from TEM measurement. Electrical properties of the devices with a tunnel oxide of either 3 nm or 7 nm are evaluated. The devices exhibit good endurance up to 10 5 W/E cycles even at the high operation temperature of 85 deg. C for both the tunnel oxide thicknesses. For the thicker tunnel oxide (i.e., the 7-nm tunnel oxide), a good retention performance with an extrapolated 10-year memory window of ∼ 0.3 V (or ∼ 20% of charge lose after 10 years) is achieved. However, ∼ 70% of charge loss after 10 years is expected for the thinner tunnel oxide (i.e., the 3-nm tunnel oxide)

  14. Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

    Science.gov (United States)

    Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

    2018-01-01

    Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these

  15. High-performance non-volatile organic ferroelectric memory on banknotes

    KAUST Repository

    Khan, Yasser; Bhansali, Unnat Sampatraj; Alshareef, Husam N.

    2012-01-01

    High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage

  16. Crested Tunnel Barriers for Fast, Scalable, Nonvolatile Semiconductor Memories (Theme 3)

    National Research Council Canada - National Science Library

    Likharev, Konstantin K; Ma, Tso-Ping

    2006-01-01

    .... If demonstrated in silicon-compatible materials with sufficient endurance under electric stress, this effect may enable high-density, high-speed nonvolatile memories that may potentially replace DRAM...

  17. Role of Non-Volatile Memories in Automotive and IoT Markets

    Science.gov (United States)

    2017-03-01

    Standard Manufacturing Supply Long Term Short to Medium Term Density Up to 16MB Up to 2MB IO Configuration Up to x128 Up to x32 Design for Test...Role of Non-Volatile Memories in Automotive and IoT Markets Vipin Tiwari Director, Business Development and Product Marketing SST – A Wholly Own...microcontrollers (MCU) and certainly one of the most challenging elements to master. This paper addresses the role of non-volatile memories for

  18. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    Energy Technology Data Exchange (ETDEWEB)

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  19. Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

    Science.gov (United States)

    Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

    2009-01-01

    We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

  20. A graphene-based non-volatile memory

    Science.gov (United States)

    Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

    2015-09-01

    We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

  1. Radiation damage in flash memory cells

    International Nuclear Information System (INIS)

    Claeys, C.; Ohyama, H.; Simoen, E.; Nakabayashi, M.; Kobayashi, K.

    2002-01-01

    Results are presented of a study on the effects of total ionization dose and displacement damage, induced by high-energy electrons, protons and alphas, on the performance degradation of flash memory cells integrated in a microcomputer. A conventional stacked-gate n-channel flash memory cell using a 0.8 μm n-polysilicon gate technology is employed. Irradiations by 1-MeV electrons and 20-MeV protons and alpha particles were done at room temperature. The impact of the fluence on the input characteristics, threshold voltage shift and drain and gate leakage was investigated. The threshold voltage change for proton and alpha irradiations is about three orders of magnitude larger than that for electrons. The performance degradation is mainly caused by the total ionization dose (TID) damage in the tunnel oxide and in the interpoly dielectric layer and by the creation of interface traps at the Si-SiO 2 interface. The impact of the irradiation temperature on the device degradation was studied for electrons and gammas, pointing out that irradiation at room temperature is mostly the worst case. Finally, attention is given to the impact of isochronal and isothermal annealing on the recovery of the degradation introduced after room temperature proton and electron irradiation

  2. Space Qualified, Radiation Hardened, Dense Monolithic Flash Memory, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — Space Micro proposes to build a radiation hardened by design (RHBD) flash memory, using a modified version of our RH-eDRAM Memory Controller to solve all the single...

  3. Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

    International Nuclear Information System (INIS)

    Tang Zhen-Jie; Li Rong; Yin Jiang

    2013-01-01

    A composition-modulated (HfO 2 ) x (Al 2 O3) 1−x charge trapping layer is proposed for charge trap flash memory by controlling the Al atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated (HfO 2 ) x (Al 2 O 3 ) 1−x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  4. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  5. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    International Nuclear Information System (INIS)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-01-01

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  6. The retention characteristics of nonvolatile SNOS memory transistors in a radiation environment: Experiment and model

    International Nuclear Information System (INIS)

    McWhorter, P.J.; Miller, S.L.; Dellin, T.A.; Axness, C.L.

    1987-01-01

    Experimental data and a model to accurately and quantitatively predict the data are presented for retention of SNOS memory devices over a wide range of dose rates. A wide range of SNOS stack geometries are examined. The model is designed to aid in screening nonvolatile memories for use in a radiation environment

  7. Fault-tolerant NAND-flash memory module for next-generation scientific instruments

    Science.gov (United States)

    Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

    2015-10-01

    Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

  8. Models for Total-Dose Radiation Effects in Non-Volatile Memory

    Energy Technology Data Exchange (ETDEWEB)

    Campbell, Philip Montgomery; Wix, Steven D.

    2017-04-01

    The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models and compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.

  9. Overview of radiation effects on emerging non-volatile memory technologies

    Directory of Open Access Journals (Sweden)

    Fetahović Irfan S.

    2017-01-01

    Full Text Available In this paper we give an overview of radiation effects in emergent, non-volatile memory technologies. Investigations into radiation hardness of resistive random access memory, ferroelectric random access memory, magneto-resistive random access memory, and phase change memory are presented in cases where these memory devices were subjected to different types of radiation. The obtained results proved high radiation tolerance of studied devices making them good candidates for application in radiation-intensive environments. [Project of the Serbian Ministry of Education, Science and Technological Development, Grant no. 171007

  10. Flash memory in embedded Java programs

    DEFF Research Database (Denmark)

    Korsholm, Stephan Erbs

    This paper introduces a Java execution environment with the capability for storing constant heap data in Flash, thus saving valuable RAM. The extension is motivated by the structure of three industrial applications which demonstrate the need for storing constant data in Flash on small embedded...

  11. Low-power non-volatile spintronic memory: STT-RAM and beyond

    International Nuclear Information System (INIS)

    Wang, K L; Alzate, J G; Khalili Amiri, P

    2013-01-01

    The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets. (paper)

  12. High-performance non-volatile organic ferroelectric memory on banknotes

    KAUST Repository

    Khan, Yasser

    2012-03-21

    High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  13. Low-temperature process steps for realization of non-volatile memory devices

    NARCIS (Netherlands)

    Brunets, I.; Boogaard, A.; Aarnink, Antonius A.I.; Kovalgin, Alexeij Y.; Wolters, Robertus A.M.; Holleman, J.; Schmitz, Jurriaan

    2007-01-01

    In this work, the low-temperature process steps required for the realization of nano-crystal non-volatile memory cells are discussed. An amorphous silicon film, crystallized using a diode pumped solid state green laser irradiating at 532 nm, is proposed as an active layer. The deposition of the

  14. High-performance non-volatile organic ferroelectric memory on banknotes.

    Science.gov (United States)

    Khan, M A; Bhansali, Unnat S; Alshareef, H N

    2012-04-24

    High-performance non-volatile polymer ferroelectric memory are fabricated on banknotes using poly(vinylidene fluoride trifluoroethylene). The devices show excellent performance with high remnant polarization, low operating voltages, low leakage, high mobility, and long retention times. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  15. Phosphorene/ZnO Nano-Heterojunctions for Broadband Photonic Nonvolatile Memory Applications.

    Science.gov (United States)

    Hu, Liang; Yuan, Jun; Ren, Yi; Wang, Yan; Yang, Jia-Qin; Zhou, Ye; Zeng, Yu-Jia; Han, Su-Ting; Ruan, Shuangchen

    2018-06-10

    High-performance photonic nonvolatile memory combining photosensing and data storage with low power consumption ensures the energy efficiency of computer systems. This study first reports in situ derived phosphorene/ZnO hybrid heterojunction nanoparticles and their application in broadband-response photonic nonvolatile memory. The photonic nonvolatile memory consistently exhibits broadband response from ultraviolet (380 nm) to near infrared (785 nm), with controllable shifts of the SET voltage. The broadband resistive switching is attributed to the enhanced photon harvesting, a fast exciton separation, as well as the formation of an oxygen vacancy filament in the nano-heterojunction. In addition, the device exhibits an excellent stability under air exposure compared with reported pristine phosphorene-based nonvolatile memory. The superior antioxidation capacity is believed to originate from the fast transfer of lone-pair electrons of phosphorene. The unique assembly of phosphorene/ZnO nano-heterojunctions paves the way toward multifunctional broadband-response data-storage techniques. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

    Institute of Scientific and Technical Information of China (English)

    Young; Tea; Chun; Daping; Chu

    2015-01-01

    Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

  17. Organic non-volatile memories from ferroelectric phase-separated blends

    Science.gov (United States)

    Asadi, Kamal; de Leeuw, Dago M.; de Boer, Bert; Blom, Paul W. M.

    2008-07-01

    New non-volatile memories are being investigated to keep up with the organic-electronics road map. Ferroelectric polarization is an attractive physical property as the mechanism for non-volatile switching, because the two polarizations can be used as two binary levels. However, in ferroelectric capacitors the read-out of the polarization charge is destructive. The functionality of the targeted memory should be based on resistive switching. In inorganic ferroelectrics conductivity and ferroelectricity cannot be tuned independently. The challenge is to develop a storage medium in which the favourable properties of ferroelectrics such as bistability and non-volatility can be combined with the beneficial properties provided by semiconductors such as conductivity and rectification. Here we present an integrated solution by blending semiconducting and ferroelectric polymers into phase-separated networks. The polarization field of the ferroelectric modulates the injection barrier at the semiconductor-metal contact. The combination of ferroelectric bistability with (semi)conductivity and rectification allows for solution-processed non-volatile memory arrays with a simple cross-bar architecture that can be read out non-destructively. The concept of an electrically tunable injection barrier as presented here is general and can be applied to other electronic devices such as light-emitting diodes with an integrated on/off switch.

  18. PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Sanam Shahla Rizvi

    2009-12-01

    Full Text Available Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS. This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  19. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    Science.gov (United States)

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  20. High-Speed Non-Volatile Optical Memory: Achievements and Challenges

    Directory of Open Access Journals (Sweden)

    Vadym Zayets

    2017-01-01

    Full Text Available We have proposed, fabricated, and studied a new design of a high-speed optical non-volatile memory. The recoding mechanism of the proposed memory utilizes a magnetization reversal of a nanomagnet by a spin-polarized photocurrent. It was shown experimentally that the operational speed of this memory may be extremely fast above 1 TBit/s. The challenges to realize both a high-speed recording and a high-speed reading are discussed. The memory is compact, integratable, and compatible with present semiconductor technology. If realized, it will advance data processing and computing technology towards a faster operation speed.

  1. A review of emerging non-volatile memory (NVM) technologies and applications

    Science.gov (United States)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  2. Integration of ammonia-plasma-functionalized graphene nanodiscs as charge trapping centers for nonvolatile memory applications

    KAUST Repository

    Wang, Jer-Chyi

    2016-11-23

    Graphene nanodiscs (GNDs), functionalized using NH3 plasma, as charge trapping sites (CTSs) for non-volatile memory applications have been investigated in this study. The fabrication process relies on the patterning of Au nanoparticles (Au-NPs), whose thicknesses are tuned to adjust the GND density and size upon etching. A GND density as high as 8 × 1011 cm−2 and a diameter of approximately 20 nm are achieved. The functionalization of GNDs by NH3 plasma creates Nsingle bondH+ functional groups that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the memory window becomes more than 2.4 V and remains stable after 104 operating cycles. The charge loss is less than 10% for a 10-year data retention testing, making this low-temperature process suitable for low-cost non-volatile memory applications on flexible substrates.

  3. Future Trend of Non-Volatile Semiconductor Memory and Feasibility Study of BiCS Type Stacked Structure

    OpenAIRE

    渡辺, 重佳

    2009-01-01

    Future trend of non-volatile semiconductor memory—FeRAM, MRAM, PRAM, ReRAM—compared with NAND typeflash memory has been described based on its history, application and performance. In the realistic point of view,FeRAM and MRAM are suitable for embedded memory and main memory, and PRAM and ReRAM are promising candidatesfor main memory and mass-storage memory for multimedia. Furthermore, the feasibility study of aggressiveultra-low-cost high-speed universal non-volatile semiconductor memory has...

  4. Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

    Science.gov (United States)

    Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

    2016-09-01

    Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

  5. Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

    Science.gov (United States)

    Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F. Y.; Gao, X. S.; Dai, J. Y.

    2015-08-01

    Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure.

  6. Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-07-23

    Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

  7. Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

    Directory of Open Access Journals (Sweden)

    Mohamed T. Ghoneim

    2015-07-01

    Full Text Available Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT, the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

  8. Review on Physically Flexible Nonvolatile Memory for Internet of Everything Electronics

    KAUST Repository

    Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2015-01-01

    Solid-state memory is an essential component of the digital age. With advancements in healthcare technology and the Internet of Things (IoT), the demand for ultra-dense, ultra-low-power memory is increasing. In this review, we present a comprehensive perspective on the most notable approaches to the fabrication of physically flexible memory devices. With the future goal of replacing traditional mechanical hard disks with solid-state storage devices, a fully flexible electronic system will need two basic devices: transistors and nonvolatile memory. Transistors are used for logic operations and gating memory arrays, while nonvolatile memory (NVM) devices are required for storing information in the main memory and cache storage. Since the highest density of transistors and storage structures is manifested in memories, the focus of this review is flexible NVM. Flexible NVM components are discussed in terms of their functionality, performance metrics, and reliability aspects, all of which are critical components for NVM technology to be part of mainstream consumer electronics, IoT, and advanced healthcare devices. Finally, flexible NVMs are benchmarked and future prospects are provided.

  9. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

    Science.gov (United States)

    Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

  10. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    International Nuclear Information System (INIS)

    Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

    2014-01-01

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized

  11. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    Energy Technology Data Exchange (ETDEWEB)

    Han, Jinhua; Wang, Wei, E-mail: wwei99@jlu.edu.cn; Ying, Jun; Xie, Wenfa [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  12. Nonvolatile Memory Elements Based on the Intercalation of Organic Molecules Inside Carbon Nanotubes

    Science.gov (United States)

    Meunier, Vincent; Kalinin, Sergei V.; Sumpter, Bobby G.

    2007-02-01

    We propose a novel class of nonvolatile memory elements based on the modification of the transport properties of a conducting carbon nanotube by the presence of an encapsulated molecule. The guest molecule has two stable orientational positions relative to the nanotube that correspond to conducting and nonconducting states. The mechanism, governed by a local gating effect of the molecule on the electronic properties of the nanotube host, is studied using density functional theory. The mechanisms of reversible reading and writing of information are illustrated with a F4TCNQ molecule encapsulated inside a metallic carbon nanotube. Our results suggest that this new type of nonvolatile memory element is robust, fatigue-free, and can operate at room temperature.

  13. Preparation of NiFe binary alloy nanocrystals for nonvolatile memory applications

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    In this work,an idea which applies binary alloy nanocrystal floating gate to nonvolatile memory application was introduced.The relationship between binary alloy’s work function and its composition was discussed theoretically.A nanocrystal floating gate structure with NiFe nanocrystals embedded in SiO2 dielectric layers was fabricated by magnetron sputtering.The micro-structure and composition deviation of the prepared NiFe nanocrystals were also investigated by TEM and EDS.

  14. Metal-organic molecular device for non-volatile memory storage

    International Nuclear Information System (INIS)

    Radha, B.; Sagade, Abhay A.; Kulkarni, G. U.

    2014-01-01

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  15. BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

    Energy Technology Data Exchange (ETDEWEB)

    Mudge, Trevor [Univ. of Michigan, Ann Arbor, MI (United States)

    2017-12-15

    This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience, and energy efficiency in Exascale systems. Capacity and energy are the key drivers.

  16. Recovery of Flash Memories for Reliable Mobile Storages

    Directory of Open Access Journals (Sweden)

    Daesung Moon

    2010-01-01

    Full Text Available As the mobile appliance is applied to many ubiquitous services and the importance of the information stored in it is increased, the security issue to protect the information becomes one of the major concerns. However, most previous researches focused only on the communication security, not the storage security. Especially, a flash memory whose operational characteristics are different from those of HDD is used increasingly as a storage device for the mobile appliance because of its resistance to physical shock and lower power requirement. In this paper, we propose a flash memory management scheme targeted for guaranteeing the data integrity of the mobile storage. By maintaining the old data specified during the recovery window, we can recover the old data when the mobile appliance is attacked. Also, to reduce the storage requirement for the recovery, we restrict the number of versions to be copied, called Degree of Integrity (DoI. Especially, we consider both the reclaim efficiency and the wear leveling which is a unique characteristic of the flash memory. Based on the performance evaluation, we confirm that the proposed scheme can be acceptable to many applications as a flash memory management scheme for improving data integrity.

  17. Nonvolatile Resistive Switching Memory Utilizing Cobalt Embedded in Gelatin

    Directory of Open Access Journals (Sweden)

    Cheng-Jung Lee

    2017-12-01

    Full Text Available This study investigates the preparation and electrical properties of Al/cobalt-embedded gelatin (CoG/ indium tin oxide (ITO resistive switching memories. Co. elements can be uniformly distributed in gelatin without a conventional dispersion procedure, as confirmed through energy dispersive X-ray analyzer and X-ray photoelectron spectroscopy observations. With an appropriate Co. concentration, Co. ions can assist the formation of an interfacial AlOx layer and improve the memory properties. High ON/OFF ratio, good retention capability, and good endurance switching cycles are demonstrated with 1 M Co. concentration, in contrast to 0.5 M and 2 M memory devices. This result can be attributed to the suitable thickness of the interfacial AlOx layer, which acts as an oxygen reservoir and stores and releases oxygen during switching. The Co. element in a solution-processed gelatin matrix has high potential for bio-electronic applications.

  18. Multi-Level Bitmap Indexes for Flash Memory Storage

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Kesheng; Madduri, Kamesh; Canon, Shane

    2010-07-23

    Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data at the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.

  19. Non-volatile main memory management methods based on a file system.

    Science.gov (United States)

    Oikawa, Shuichi

    2014-01-01

    There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

  20. A room-temperature non-volatile CNT-based molecular memory cell

    Science.gov (United States)

    Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

    2013-04-01

    Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

  1. Microwave oven fabricated hybrid memristor devices for non-volatile memory storage

    International Nuclear Information System (INIS)

    Verrelli, E; Gray, R J; O’Neill, M; Kemp, N T; Kelly, S M

    2014-01-01

    Novel hybrid non-volatile memories made using an ultra-fast microwave heating method are reported for the first time. The devices, consisting of aligned ZnO nanorods embedded in poly (methyl methacrylate), require no forming step and exhibit reliable and reproducible bipolar resistive switching at low voltages and with low power usage. We attribute these properties to a combination of the high aspect ratio of the nanorods and the polymeric hybrid structure of the device. The extremely easy, fast and low-cost solution based method of fabrication makes possible the simple and quick production of cheap memory cells. (paper)

  2. Memory characteristics of silicon nitride with silicon nanocrystals as a charge trapping layer of nonvolatile memory devices

    International Nuclear Information System (INIS)

    Choi, Sangmoo; Yang, Hyundeok; Chang, Man; Baek, Sungkweon; Hwang, Hyunsang; Jeon, Sanghun; Kim, Juhyung; Kim, Chungwoo

    2005-01-01

    Silicon nitride with silicon nanocrystals formed by low-energy silicon plasma immersion ion implantation has been investigated as a charge trapping layer of a polycrystalline silicon-oxide-nitride-oxide-silicon-type nonvolatile memory device. Compared with the control sample without silicon nanocrystals, silicon nitride with silicon nanocrystals provides excellent memory characteristics, such as larger width of capacitance-voltage hysteresis, higher program/erase speed, and lower charge loss rate at elevated temperature. These improved memory characteristics are derived by incorporation of silicon nanocrystals into the charge trapping layer as additional accessible charge traps with a deeper effective trap energy level

  3. High-Density Stacked Ru Nanocrystals for Nonvolatile Memory Application

    International Nuclear Information System (INIS)

    Ping, Mao; Zhi-Gang, Zhang; Li-Yang, Pan; Jun, Xu; Pei-Yi, Chen

    2009-01-01

    Stacked ruthenium (Ru) nanocrystals (NCs) are formed by rapid thermal annealing for the whole gate stacks and embedded in memory structure, which is compatible with conventional CMOS technology. Ru NCs with high density (3 × 10 12 cm −2 ), small size (2–4 nm) and good uniformity both in aerial distribution and morphology are formed. Attributed to the higher surface trap density, a memory window of 5.2 V is obtained with stacked Ru NCs in comparison to that of 3.5 V with single-layer samples. The stacked Ru NCs device also exhibits much better retention performance because of Coulomb blockade and vertical uniformity between stacked Ru NCs

  4. A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

    Science.gov (United States)

    She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

    2017-02-01

    A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Li, E-mail: lizhang9@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Li, Ye; Shi, Jun [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China); Shi, Gaoquan [Department of Chemistry, Tsinghua University, Beijing 100084 (China); Cao, Shaokui, E-mail: Caoshaokui@zzu.edu.cn [School of Materials Science and Engineering, Zhengzhou University, Zhengzhou 450052 (China)

    2013-11-01

    An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10{sup 5}. Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states.

  6. Design exploration of emerging nano-scale non-volatile memory

    CERN Document Server

    Yu, Hao

    2014-01-01

    This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices.  Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design, and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices.  Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design.   • Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; • Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design, and hybrid NVM memory system optimization; • Provides both theoretical analysis and pr...

  7. Nonvolatile rewritable memory device based on solution-processable graphene/poly(3-hexylthiophene) nanocomposite

    International Nuclear Information System (INIS)

    Zhang, Li; Li, Ye; Shi, Jun; Shi, Gaoquan; Cao, Shaokui

    2013-01-01

    An electrically bistable device utilizing a nanocomposite of hexadecylamine-functionalized graphene oxide (HDAGO) with poly(3-hexylthiophene) (P3HT) is demonstrated. The device has an ITO/P3HT-HDAGO/Al sandwich structure, in which the composite film of P3HT-HDAGO was prepared by simple solution phase mixing of the exfoliated HDAGO monolayers with P3HT matrix and a spin-coating method. The memory device exhibits typical bistable electrical switching behavior and a nonvolatile rewritable memory effect, with a turn-on voltage of about 1.5 V and an ON/OFF-state current ratio of 10 5 . Under ambient conditions, both the ON and OFF states are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage of 1 V. The conduction mechanism is deduced from the modeling of the nature of currents in both states, and the electrical switching behavior can be attributed to the electric-field-induced charge transfer between P3HT and HDAGO nanosheets. - Highlights: • Nonvolatile rewritable memory effect in P3HT–graphene composite is demonstrated. • The memory device was fabricated through a simple solution processing technique. • The device shows a remarkable electrical bistable behavior and excellent stability. • Memory mechanism is deduced from the modeling of the currents in both states

  8. Intrinsic Ge nanowire nonvolatile memory based on a simple core–shell structure

    International Nuclear Information System (INIS)

    Chen, Wen-Hua; Liu, Chang-Hai; Li, Qin-Liang; Sun, Qi-Jun; Liu, Jie; Gao, Xu; Sun, Xuhui; Wang, Sui-Dong

    2014-01-01

    Intrinsic Ge nanowires (NWs) with a Ge core covered by a thick Ge oxide shell are utilized to achieve nanoscale field-effect transistor nonvolatile memories, which show a large memory window and a high ON/OFF ratio with good retention. The retainable surface charge trapping is considered to be responsible for the memory effect, and the Ge oxide shell plays a key role as the insulating tunneling dielectric which must be thick enough to prevent stored surface charges from leaking out. Annealing the device in air is demonstrated to be a simple and effective way to attain thick Ge oxide on the Ge NW surface, and the Ge-NW-based memory corresponding to thick Ge oxide exhibits a much better retention capability compared with the case of thin Ge oxide. (paper)

  9. ZnO as dielectric for optically transparent non-volatile memory

    International Nuclear Information System (INIS)

    Salim, N. Tjitra; Aw, K.C.; Gao, W.; Wright, Bryon E.

    2009-01-01

    This paper discusses the application of a DC sputtered ZnO thin film as a dielectric in an optically transparent non-volatile memory. The main motivation for using ZnO as a dielectric is due to its optical transparency and mechanical flexibility. We have established the relationship between the electrical resistivity (ρ) and the activation energy (E a ) of the electron transport in the conduction band of the ZnO film. The ρ of 2 x 10 4 -5 x 10 7 Ω-cm corresponds to E a of 0.36-0.76 eV, respectively. The k-value and optical band-gap for films sputtered with Ar:O 2 ratio of 4:1 are 53 ± 3.6 and 3.23 eV, respectively. In this paper, the basic charge storage element for a non-volatile memory is a triple layer dielectric structure in which a 50 nm thick ZnO film is sandwiched between two layers of methyl silsesquioxane sol-gel dielectric of varying thickness. A pronounced clockwise capacitance-voltage (C-V) hysteresis was observed with a memory window of 6 V. The integration with a solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene resulted in an optically transparent organic field effect transistor non-volatile memory (OFET-NVM). We have demonstrated that this OFET-NVM can be electrically programmed and erased at low voltage (± 10 V) with a threshold voltage shift of 4.0 V.

  10. Comparison of discrete-storage nonvolatile memories: advantage of hybrid method for fabrication of Au nanocrystal nonvolatile memory

    International Nuclear Information System (INIS)

    Wang Qin; Jia Rui; Guan Weihua; Li Weilong; Liu Qi; Hu Yuan; Long Shibing; Chen Baoqin; Liu Ming; Ye Tianchun; Lu Wensheng; Jiang Long

    2008-01-01

    In this paper, the memory characteristics of two kinds of metal-oxide-semiconductor (MOS) capacitors embedded with Au nanocrytals are investigated: hybrid MOS with nanocrystals (NCs) fabricated by chemical syntheses and rapid thermal annealing (RTA) MOS with NCs fabricated by RTA. For both kinds of devices, the capacitance versus voltage (C-V) curves clearly indicate the charge storage in the NCs. The hybrid MOS, however, shows a larger memory window, as compared with RTA MOS. The retention characteristics of the two MOS devices are also investigated. The capacitance versus time (C-t) measurement shows that the hybrid MOS capacitor embedded with Au nanocrystals has a longer retention time. The mechanism of longer retention time for hybrid MOS capacitor is qualitatively discussed

  11. Flash memory management system and method utilizing multiple block list windows

    Science.gov (United States)

    Chow, James (Inventor); Gender, Thomas K. (Inventor)

    2005-01-01

    The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.

  12. Zinc Cadmium Selenide Cladded Quantum Dot Based Electroluminescent and Nonvolatile Memory Devices

    Science.gov (United States)

    Al-Amody, Fuad H.

    This dissertation presents electroluminescent (EL) and nonvolatile memory devices fabricated using pseudomorphic ZnCdSe-based cladded quantum dots (QDs). These dots were grown using our own in-school built novel reactor. The EL device was fabricated on a substrate of ITO (indium tin oxide) coated glass with the quantum dots sandwiched between anode and cathode contacts with a small barrier layer on top of the QDs. The importance of these cladded dots is to increase the quantum yield of device. This device is unique as they utilize quantum dots that are pseudomorphic (nearly lattice-matched core and the shell of the dot). In the case of floating quantum dot gate nonvolatile memory, cladded ZnCdSe quantum dots are deposited on single crystalline gate insulator (ZnMgS/ZnMgSe), which is grown using metal-organic chemical vapor deposition (MOCVD). The control gate dielectric layer of the nonvolatile memory is Si3N4 or SiO2 and is grown using plasma enhanced chemical vapor deposition (PECVD). The cladded dots are grown using an improved methodology of photo-assisted microwave plasma metal-organic chemical vapor deposition (PMP-MOCVD) enhanced reactor. The cladding composition of the core and shell of the dots was engineered by the help of ultraviolet light which changed the incorporation of zinc (and hence composition of ZnCdSe). This makes ZnxCd1--xSe-ZnyCd1--y Se QDs to have a low composition of zinc in the core than the cladding (x

  13. Dual-functional Memory and Threshold Resistive Switching Based on the Push-Pull Mechanism of Oxygen Ions

    KAUST Repository

    Huang, Yi-Jen; Chao, Shih-Chun; Lien, Der-Hsien; Wen, Cheng-Yen; He, Jr-Hau; Lee, Si-Chen

    2016-01-01

    The combination of nonvolatile memory switching and volatile threshold switching functions of transition metal oxides in crossbar memory arrays is of great potential for replacing charge-based flash memory in very-large-scale integration. Here, we

  14. Negative effect of Au nanoparticles on an IGZO TFT-based nonvolatile memory device

    Energy Technology Data Exchange (ETDEWEB)

    Lim, Myunghoon; Yoo, Gwangwe; Lee, Jongtaek; Jeong, Seokwon; Roh, Yonghan; Park, Jinhong; Kwon, Namyong [Sungkyunkwan University, Suwon (Korea, Republic of); Jung, Wooshik [Stanford University, Stanford, CA (United States)

    2014-02-15

    In this letter, the electrical characteristics of nonvolatile memory devices based on back gate type indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) are investigated in terms of the Au nanoparticles (NPs) employed in the floating gate-stack of the device. The size of the Au NPs is controlled using a by 500 .deg. C annealing process after the Au thin-film deposition. The size and the roughness of the Au NPs were observed by using scanning electron microscopy, atomic force microscopy, and transmission electron microscopy. In order to analyze the electrical properties according to Au NP size, we measured the current-voltage (I{sub D}-V{sub G}) characteristics of the nonvolatile memory devices fabricated without Au NPs and with Au NPs of various sizes. The size of the Au NP increased, so did the surface roughness of the gate. This resulted in increased carrier scattering, which subsequently degraded the on-current of the memory device. In addition, inter-diffusion between the Au and the α-IGZO through the non-uniform Al{sub 2}O{sub 3} tunneling layer seemed to further degrade the device performance.

  15. Flexible All-Inorganic Perovskite CsPbBr3 Nonvolatile Memory Device.

    Science.gov (United States)

    Liu, Dongjue; Lin, Qiqi; Zang, Zhigang; Wang, Ming; Wangyang, Peihua; Tang, Xiaosheng; Zhou, Miao; Hu, Wei

    2017-02-22

    All-inorganic perovskite CsPbX 3 (X = Cl, Br, or I) is widely used in a variety of photoelectric devices such as solar cells, light-emitting diodes, lasers, and photodetectors. However, studies to understand the flexible CsPbX 3 electrical application are relatively scarce, mainly due to the limitations of the low-temperature fabricating process. In this study, all-inorganic perovskite CsPbBr 3 films were successfully fabricated at 75 °C through a two-step method. The highly crystallized films were first employed as a resistive switching layer in the Al/CsPbBr 3 /PEDOT:PSS/ITO/PET structure for flexible nonvolatile memory application. The resistive switching operations and endurance performance demonstrated the as-prepared flexible resistive random access memory devices possess reproducible and reliable memory characteristics. Electrical reliability and mechanical stability of the nonvolatile device were further tested by the robust current-voltage curves under different bending angles and consecutive flexing cycles. Moreover, a model of the formation and rupture of filaments through the CsPbBr 3 layer was proposed to explain the resistive switching effect. It is believed that this study will offer a new setting to understand and design all-inorganic perovskite materials for future stable flexible electronic devices.

  16. Fabrication of Pb (Zr, Ti) O3 Thin Film for Non-Volatile Memory Device Application

    International Nuclear Information System (INIS)

    Mar Lar Win

    2011-12-01

    Ferroelectric lead zirconate titanate powder was composed of mainly the oxides of titanium, zirconium and lead. PZT powder was firstly prepared by thermal synthesis at different Zr/Ti ratios with various sintering temperatures. PZT thin film was fabricated on SiO2/Si substrate by using thermal evaporation method. Physical and elemental analysis were carried out by using SEM, EDX and XRD The ferroelectric properties and the switching behaviour of the PZT thin films were investigated. The ferroelectric properties and switching properties of the PZT thin film (near morphotropic phase boundary sintered at 800 C) could function as a nonvolatile memory.

  17. Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

    Science.gov (United States)

    Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

    2017-05-01

    Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

  18. A Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories

    Directory of Open Access Journals (Sweden)

    Sparsh Mittal

    2017-02-01

    Full Text Available Non-volatile memories (NVMs offer superior density and energy characteristics compared to the conventional memories; however, NVMs suffer from severe reliability issues that can easily eclipse their energy efficiency advantages. In this paper, we survey architectural techniques for improving the soft-error reliability of NVMs, specifically PCM (phase change memory and STT-RAM (spin transfer torque RAM. We focus on soft-errors, such as resistance drift and write disturbance, in PCM and read disturbance and write failures in STT-RAM. By classifying the research works based on key parameters, we highlight their similarities and distinctions. We hope that this survey will underline the crucial importance of addressing NVM reliability for ensuring their system integration and will be useful for researchers, computer architects and processor designers.

  19. A direct metal transfer method for cross-bar type polymer non-volatile memory applications

    International Nuclear Information System (INIS)

    Kim, Tae-Wook; Lee, Kyeongmi; Oh, Seung-Hwan; Wang, Gunuk; Kim, Dong-Yu; Jung, Gun-Young; Lee, Takhee

    2008-01-01

    Polymer non-volatile memory devices in 8 x 8 array cross-bar architecture were fabricated by a non-aqueous direct metal transfer (DMT) method using a two-step thermal treatment. Top electrodes with a linewidth of 2 μm were transferred onto the polymer layer by the DMT method. The switching behaviour of memory devices fabricated by the DMT method was very similar to that of devices fabricated by the conventional shadow mask method. The devices fabricated using the DMT method showed three orders of magnitude of on/off ratio with stable resistance switching, demonstrating that the DMT method can be a simple process to fabricate organic memory array devices

  20. Effects of tunnel oxide process on SONOS flash memory characteristics

    International Nuclear Information System (INIS)

    Li, Dong Hua; Park, Il Han; Yun, Jang-Gn; Park, Byung-Gook

    2010-01-01

    In this paper, various process conditions of tunnel oxides are applied in SONOS flash memory to investigate their effects on charge transport during the program/erase operations. We focus the key point of analysis on Fermi-level (E F ) variation at the interface of silicon substrate and tunnel oxide. The Si-O chemical bonding information which describes the interface oxidation states at the Si/SiO 2 is obtained by the core-level X-ray photoelectron spectroscopy (XPS). Moreover, relative E F position is determined by measuring the Si 2p energy shift from XPS spectrums. Experimental results from memory characteristic measurement show that MTO tunnel oxide structure exhibits faster erase speed, and larger memory window during P/E cycle compared to FTO and RTO tunnel oxide structures. Finally, we examine long-term charge retention characteristic and find that the memory windows of all the capacitors remain wider than 2 V after 10 5 s.

  1. The MONOS memory transistor: application in a radiation-hard nonvolatile RAM

    International Nuclear Information System (INIS)

    Brown, W.D.

    1985-01-01

    The MONOS (metal-oxide-nitride-oxide-silicon) device is a prime candidate for use as the nonvolatile memory element in a radiation-hardened RAM (random-access memory). The endurance, retention and radiation properties of MONOS memory transistors have been studied as a function of post nitride deposition annealing. Following the nitride layer deposition, all devices were subjected to an 800 0 C oxidation step and some were then annealed at 900 0 C in nitrogen. The nitrogen anneal produces an increase in memory window size of approximately 40%. The memory window center of the annealed devices is shifted toward more positive voltages and is more stable with endurance cycling. Endurance cycling to 10 9 cycles produces a 20% increase in memory window size and a 60% increase in decay rate. For a radiation total dose of 10 6 rads (Si), the memory window size is essentially unchanged and the decay rate increases approximately 13%. A combination of 10 9 cycles and 10 6 rads (Si) reduces the decades of retention (in sec) from 6.3 to 4.3 for a +- 23-V 16-μsec write/erase pulse. (author)

  2. Nonvolatile memory characteristics in metal-oxide-semiconductors containing metal nanoparticles fabricated by using a unique laser irradiation method

    International Nuclear Information System (INIS)

    Yang, JungYup; Yoon, KapSoo; Kim, JuHyung; Choi, WonJun; Do, YoungHo; Kim, ChaeOk; Hong, JinPyo

    2006-01-01

    Metal-oxide-semiconductor (MOS) capacitors with metal nanoparticles (Co NP) were successfully fabricated by utilizing an external laser exposure technique for application of non-volatile memories. Images of high-resolution transmission electron microscopy reveal that the spherically shaped Co NP are clearly embedded in the gate oxide layer. Capacitance-voltage measurements exhibit typical charging and discharging effects with a large flat-band shift. The effects of the tunnel oxide thickness and the different tunnel materials are analyzed using capacitance-voltage and retention characteristics. In addition, the memory characteristics of the NP embedded in a high-permittivity material are investigated because the thickness of conventionally available SiO 2 gates is approaching the quantum tunneling limit as devices are scaled down. Finally, the suitability of NP memory devices for nonvolatile memory applications is also discussed. The present results suggest that our unique laser exposure technique holds promise for the NP formation as floating gate elements in nonvolatile NP memories and that the quality of the tunnel oxide is very important for enhancing the retention properties of nonvolatile memory.

  3. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn [Institute of Functional Nano and Soft Materials (FUNSOM), Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Soochow University, Suzhou, Jiangsu 215123 (China)

    2016-07-11

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  4. Discrete Charge Storage Nonvolatile Memory Based on Si Nanocrystals with Nitridation Treatment

    International Nuclear Information System (INIS)

    Xian-Gao, Zhang; Kun-Ji, Chen; Zhong-Hui, Fang; Xin-Ye, Qian; Guang-Yuan, Liu; Xiao-Fan, Jiang; Zhong-Yuan, Ma; Jun, Xu; Xin-Fan, Huang; Jian-Xin, Ji; Fei, He; Kuang-Bao, Song; Jun, Zhang; Hui, Wan; Rong-Hua, Wang

    2010-01-01

    A nonvolatile memory device with nitrided Si nanocrystals embedded in a Boating gate was fabricated. The uniform Si nanocrystals with high density (3 × 10 11 cm −2 ) were deposited on ultra-thin tunnel oxide layer (∼ 3 nm) and followed by a nitridation treatment in ammonia to form a thin silicon nitride layer on the surface of nanocrystals. A memory window of 2.4 V was obtained and it would be larger than 1.3 V after ten years from the extrapolated retention data. The results can be explained by the nitrogen passivation of the surface traps of Si nanocrystals, which slows the charge loss rate. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  5. Conjugated donor-acceptor-acceptor (D-A-A) molecule for organic nonvolatile resistor memory.

    Science.gov (United States)

    Dong, Lei; Li, Guangwu; Yu, An-Dih; Bo, Zhishan; Liu, Cheng-Liang; Chen, Wen-Chang

    2014-12-01

    A new donor-acceptor-acceptor (D-A-A) type of conjugated molecule, N-(4-(N',N'-diphenyl)phenylamine)-4-(4'-(2,2-dicyanovinyl)phenyl) naphthalene-1,8-dicarboxylic monoimide (TPA-NI-DCN), consisting of triphenylamine (TPA) donors and naphthalimide (NI)/dicyanovinylene (DCN) acceptors was synthesized and characterized. In conjunction with previously reported D-A based materials, the additional DCN moiety attached as end group in the D-A-A configuration can result in a stable charge transfer (CT) and charge-separated state to maintain the ON state current. The vacuum-deposited TPA-NI-DCN device fabricated as an active memory layer was demonstrated to exhibit write-once-read-many (WORM) switching characteristics of organic nonvolatile memory due to the strong polarity of the TPA-NI-DCN moiety. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung, E-mail: mskang@ssu.ac.kr [Department of Chemical Engineering, Soongsil University, Seoul 156-743 (Korea, Republic of)

    2015-02-09

    Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

  7. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    Science.gov (United States)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  8. The imaging performance of flash memory masks characterized with AIMS

    Science.gov (United States)

    van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

    2009-04-01

    Flash memory is an important driver of the lithography roadmap, with its dramatic acceleration in dimensional shrink, pushing for ever smaller feature sizes. The introduction of hyper-NA immersion lithography has brought the 45nm node and below within reach for memory makers using single exposure. At these feature sizes mask topology and the material properties of the film stack on the mask play an important role on imaging performance. Furthermore, the break up of the array pitch regularity in the NAND-type flash memory cell by two thick wordlines and a central space, leads to feature-center placement (overlay) errors, that are inherent to the design. An integral optimization approach is needed to mitigate these effects and to control both the CD and placement errors tightly. In this paper we will show that aerial image measurements at mask-level are useful for characterizing the gate layer of a NAND-Flash design before exposure. The aerial image measurements are performed with the AIMSTM 45-193i. and compared to CD measurements on the wafer obtained with an XT:1900Gi hyper-NA immersion system. An excellent correlation is demonstrated for feature-center placement errors and CD variations across the mask (see Figure 1) for several features in the gate layer down to 40nm half pitch. This shows the potential to use aerial image measurements at mask-level in combination with correction techniques on the photomask, like the CDC200 tool in combination with exposure tool correction techniques, such as DoseMapperTM, to improve both across field and across wafer CD uniformity of critical layers.

  9. Origami-based tunable truss structures for non-volatile mechanical memory operation.

    Science.gov (United States)

    Yasuda, Hiromi; Tachi, Tomohiro; Lee, Mia; Yang, Jinkyu

    2017-10-17

    Origami has recently received significant interest from the scientific community as a method for designing building blocks to construct metamaterials. However, the primary focus has been placed on their kinematic applications by leveraging the compactness and auxeticity of planar origami platforms. Here, we present volumetric origami cells-specifically triangulated cylindrical origami (TCO)-with tunable stability and stiffness, and demonstrate their feasibility as non-volatile mechanical memory storage devices. We show that a pair of TCO cells can develop a double-well potential to store bit information. What makes this origami-based approach more appealing is the realization of two-bit mechanical memory, in which two pairs of TCO cells are interconnected and one pair acts as a control for the other pair. By assembling TCO-based truss structures, we experimentally verify the tunable nature of the TCO units and demonstrate the operation of purely mechanical one- and two-bit memory storage prototypes.Origami is a popular method to design building blocks for mechanical metamaterials. Here, the authors assemble a volumetric origami-based structure, predict its axial and rotational movements during folding, and demonstrate the operation of mechanical one- and two-bit memory storage.

  10. Dependence of the organic nonvolatile memory performance on the location of ultra-thin Ag film

    International Nuclear Information System (INIS)

    Jiao Bo; Wu Zhaoxin; He Qiang; Mao Guilin; Hou Xun; Tian Yuan

    2010-01-01

    We demonstrated organic nonvolatile memory devices based on 4,4',4''-tris[N-(3-methylphenyl)-N-phenylamino] triphenylamine (m-MTDATA) inserted by an ultra-thin Ag film. The memory devices with different locations of ultra-thin Ag film in m-MTDATA were investigated, and it was found that the location of the Ag film could affect the performance of the organic memory, such as ON/OFF ratio, retention time and cycling endurance. When the Ag film was located at the ITO/m-MTDATA interface, the largest ON/OFF ratio (about 10 5 ) could be achieved, but the cycling endurance was poor. When the Ag film was located in the middle region of the m-MTDATA layer, the ON/OFF ratios came down by about 10 3 , but better performance of cycling endurance was exhibited. When the Ag film was located close to the Al electrode, the ON/OFF ratios and the retention time of this device decreased sharply and the bistable phenomenon almost disappeared. Our works show a simple approach to improve the performance of organic memory by adjusting the location of the metal film.

  11. Resistance Switching Characteristics in ZnO-Based Nonvolatile Memory Devices

    Directory of Open Access Journals (Sweden)

    Fu-Chien Chiu

    2013-01-01

    Full Text Available Bipolar resistance switching characteristics are demonstrated in Pt/ZnO/Pt nonvolatile memory devices. A negative differential resistance or snapback characteristic can be observed when the memory device switches from a high resistance state to a low resistance state due to the formation of filamentary conducting path. The dependence of pulse width and temperature on set/reset voltages was examined in this work. The exponentially decreasing trend of set/reset voltage with increasing pulse width is observed except when pulse width is larger than 1 s. Hence, to switch the ZnO memory devices, a minimum set/reset voltage is required. The set voltage decreases linearly with the temperature whereas the reset voltage is nearly temperature-independent. In addition, the ac cycling endurance can be over 106 switching cycles, whereas, the dependence of HRS/LRS resistance distribution indicates that a significant memory window closure may take place after about 102  dc switching cycles.

  12. Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-04-24

    A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational voltages to achieve coercive electric fields, reduces the sol-gel coating cycles required (i.e., more cost-effective), and, fabrication wise, is more suitable for further scaling of lateral dimensions to the nano-scale due to the larger feature size-to-depth aspect ratio (critical for ultra-high density non-volatile memory applications). Utilizing the inverse proportionality between substrate\\'s thickness and its flexibility, traditional PZT based FeRAM on silicon is transformed through a transfer-less manufacturable process into a flexible form that matches organic electronics\\' flexibility while preserving the superior performance of silicon CMOS electronics. Each memory cell in a FeRAM array consists of two main elements; a select/access transistor, and a storage ferroelectric capacitor. Flexible transistors on silicon have already been reported. In this work, we focus on the storage ferroelectric capacitors, and report, for the first time, its performance after transformation into a flexible version, and assess its key memory parameters while bent at 0.5 cm minimum bending radius.

  13. Simulation of trapping properties of high κ material as the charge storage layer for flash memory application

    International Nuclear Information System (INIS)

    Yeo, Yee Ngee; Wang Yingqian; Samanta, Santanu Kumar; Yoo, Won Jong; Samudra, Ganesh; Gao, Dongyue; Chong, Chee Ching

    2006-01-01

    We investigated the trapping properties of high κ material as the charge storage layer in non-volatile flash memory devices using a two-dimensional device simulator, Medici. The high κ material is sandwiched between two silicon oxide layers, resulting in the Silicon-Oxide-High κ-Oxide-Silicon (SOHOS) structure. The trap energy levels of the bulk electron traps in high κ material were determined. The programming and erasing voltage and time using Fowler Nordheim tunneling were estimated by simulation. The effect of deep level traps on erasing was investigated. Also, the effect of bulk traps density, thickness of block oxide and thickness of high κ material on the threshold voltage of the device was simulated

  14. Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

    Science.gov (United States)

    Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

    2010-07-01

    This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

  15. Nonvolatile organic write-once-read-many-times memory devices based on hexadecafluoro-copper-phthalocyanine

    Science.gov (United States)

    Wang, Lidan; Su, Zisheng; Wang, Cheng

    2012-05-01

    Nonvolatile organic write-once-read-many-times memory device was demonstrated based on hexadecafluoro-copper-phthalocyanine (F16CuPc) single layer sandwiched between indium tin oxide (ITO) anode and Al cathode. The as fabricated device remains in ON state and it can be tuned to OFF state by applying a reverse bias. The ON/OFF current ratio of the device can reach up to 2.3 × 103. Simultaneously, the device shows long-term storage stability and long retention time in air. The ON/OFF transition is attributed to the formation and destruction of the interfacial dipole layer in the ITO/F16CuPc interface, and such a mechanism is different from previously reported ones.

  16. The floating-gate non-volatile semiconductor memory--from invention to the digital age.

    Science.gov (United States)

    Sze, S M

    2012-10-01

    In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

  17. Poly (vinylidene fluoride-trifluoroethylene/barium titanate nanocomposite for ferroelectric nonvolatile memory devices

    Directory of Open Access Journals (Sweden)

    Uvais Valiyaneerilakkal

    2013-04-01

    Full Text Available The effect of barium titanate (BaTiO3 nanoparticles (particle size <100nm on the ferroelectric properties of poly (vinylidenefluoride-trifluoroethylene P(VDF-TrFE copolymer has been studied. Different concentrations of nanoparticles were added to P(VDF-TrFE using probe sonication, and uniform thin films were made. Polarisation - Electric field (P-E hysteresis analysis shows an increase in remnant polarization (Pr and decrease in coercive voltage (Vc. Piezo-response force microscopy analysis shows the switching capability of the polymer composite. The topography and surface roughness was studied using atomic force microscopy. It has been observed that this nanocomposite can be used for the fabrication of non-volatile ferroelectric memory devices.

  18. Optimal proximity correction: application for flash memory design

    Science.gov (United States)

    Chen, Y. O.; Huang, D. L.; Sung, K. T.; Chiang, J. J.; Yu, M.; Teng, F.; Chu, Lung; Rey, Juan C.; Bernard, Douglas A.; Li, Jiangwei; Li, Junling; Moroz, V.; Boksha, Victor V.

    1998-06-01

    Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

  19. A radiation-tolerant, low-power non-volatile memory based on silicon nanocrystal quantum dots

    OpenAIRE

    Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; De Blauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO_2 is a critical aspect of the performance ...

  20. A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

    Energy Technology Data Exchange (ETDEWEB)

    De, Arup [Univ. of California, San Diego, CA (United States)

    2014-01-01

    Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

  1. Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

    Directory of Open Access Journals (Sweden)

    Fabrizio Riente

    2017-05-01

    Full Text Available Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

  2. Development of novel nonvolatile memory devices using the colossal magnetoresistive oxide praseodymium-calcium-manganese trioxide

    Science.gov (United States)

    Papagianni, Christina

    Pr0.7Ca0.3MnO3 (PCMO) manganese oxide belongs in the family of materials known as transition metal oxides. These compounds have received increased attention due to their perplexing properties such as Colossal Magnetoresistance effect, Charge-Ordered phase, existence of phase-separated states etc. In addition, it was recently discovered that short electrical pulses in amplitude and duration are sufficient to induce reversible and non-volatile resistance changes in manganese perovskite oxide thin films at room temperature, known as the EPIR effect. The existence of the EPIR effect in PCMO thin films at room temperature opens a viable way for the realization of fast, high-density, low power non-volatile memory devices in the near future. The purpose of this study is to investigate, optimize and understand the properties of Pr0.7Ca0.3MnO 3 (PCMO) thin film devices and to identify how these properties affect the EPIR effect. PCMO thin films were deposited on various substrates, such as metals, and conducting and insulating oxides, by pulsed laser and radio frequency sputtering methods. Our objective was to understand and compare the induced resistive states. We attempted to identify the induced resistance changes by considering two resistive models to be equivalent to our devices. Impedance spectroscopy was also utilized in a wide temperature range that was extended down to 70K. Fitted results of the temperature dependence of the resistance states were also included in this study. In the same temperature range, we probed the resistance changes in PCMO thin films and we examined whether the phase transitions affect the EPIR effect. In addition, we included a comparison of devices with electrodes consisting of different size and different materials. We demonstrated a direct relation between the EPIR effect and the phase diagram of bulk PCMO samples. A model that could account for the observed EPIR effect is presented.

  3. An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

    Science.gov (United States)

    Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

    2018-02-01

    Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

  4. Low temperature synthesis and electrical characterization of germanium doped Ti-based nanocrystals for nonvolatile memory

    International Nuclear Information System (INIS)

    Feng, Li-Wei; Chang, Chun-Yen; Chang, Ting-Chang; Tu, Chun-Hao; Wang, Pai-Syuan; Lin, Chao-Cheng; Chen, Min-Chen; Huang, Hui-Chun; Gan, Der-Shin; Ho, New-Jin; Chen, Shih-Ching; Chen, Shih-Cheng

    2011-01-01

    Chemical and electrical characteristics of Ti-based nanocrystals containing germanium, fabricated by annealing the co-sputtered thin film with titanium silicide and germanium targets, were demonstrated for low temperature applications of nonvolatile memory. Formation and composition characteristics of nanocrystals (NCs) at various annealing temperatures were examined by transmission electron microscopy and X-ray photon-emission spectroscopy, respectively. It was observed that the addition of germanium (Ge) significantly reduces the proposed thermal budget necessary for Ti-based NC formation due to the rise of morphological instability and agglomeration properties during annealing. NC structures formed after annealing at 500 °C, and separated well at 600 °C annealing. However, it was also observed that significant thermal desorption of Ge atoms occurs at 600 °C due to the sublimation of formatted GeO phase and results in a serious decrease of memory window. Therefore, an approach to effectively restrain Ge thermal desorption is proposed by encapsulating the Ti-based trapping layer with a thick silicon oxide layer before 600 °C annealing. The electrical characteristics of data retention in the sample with the 600 °C annealing exhibited better performance than the 500 °C-annealed sample, a result associated with the better separation and better crystallization of the NC structures.

  5. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    Science.gov (United States)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  6. Atomically Smooth Epitaxial Ferroelectric Thin Films for the Development of a Nonvolatile, Ultrahigh Density, Fast, Low Voltage, Radiation-Hard Memory

    National Research Council Canada - National Science Library

    Ahn, Charles H

    2006-01-01

    The goal of this research is to fabricate atomically smooth, single crystalline, complex oxide thin film nanostructures for use in a nonvolatile, ultrahigh density, fast, low voltage, radiation-hard memory...

  7. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    International Nuclear Information System (INIS)

    Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

    2015-01-01

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10 17  m −2 . We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching

  8. Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

    Science.gov (United States)

    Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

    2016-02-01

    We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

  9. Solution-Processed Wide-Bandgap Organic Semiconductor Nanostructures Arrays for Nonvolatile Organic Field-Effect Transistor Memory.

    Science.gov (United States)

    Li, Wen; Guo, Fengning; Ling, Haifeng; Liu, Hui; Yi, Mingdong; Zhang, Peng; Wang, Wenjun; Xie, Linghai; Huang, Wei

    2018-01-01

    In this paper, the development of organic field-effect transistor (OFET) memory device based on isolated and ordered nanostructures (NSs) arrays of wide-bandgap (WBG) small-molecule organic semiconductor material [2-(9-(4-(octyloxy)phenyl)-9H-fluoren-2-yl)thiophene]3 (WG 3 ) is reported. The WG 3 NSs are prepared from phase separation by spin-coating blend solutions of WG 3 /trimethylolpropane (TMP), and then introduced as charge storage elements for nonvolatile OFET memory devices. Compared to the OFET memory device with smooth WG 3 film, the device based on WG 3 NSs arrays exhibits significant improvements in memory performance including larger memory window (≈45 V), faster switching speed (≈1 s), stable retention capability (>10 4 s), and reliable switching properties. A quantitative study of the WG 3 NSs morphology reveals that enhanced memory performance is attributed to the improved charge trapping/charge-exciton annihilation efficiency induced by increased contact area between the WG 3 NSs and pentacene layer. This versatile solution-processing approach to preparing WG 3 NSs arrays as charge trapping sites allows for fabrication of high-performance nonvolatile OFET memory devices, which could be applicable to a wide range of WBG organic semiconductor materials. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  10. Transparent Flash Memory using Single Ta2O5 Layer for both Charge Trapping and Tunneling Dielectrics

    KAUST Repository

    Hota, Mrinal Kanti

    2017-06-08

    We report reproducible multibit transparent flash memory in which a single solution-derived Ta2O5 layer is used simultaneously as charge trapping and tunneling layer. This is different from conventional flash cells, where two different dielectric layers are typically used. Under optimized programming/erasing operations, the memory device shows excellent programmable memory characteristics with a maximum memory window of ~10 V. Moreover, the flash memory device shows a stable 2-bit memory performance, good reliability, including data retention for more than 104 sec and endurance performance for more than 100 cycles. The use of a common charge trapping and tunneling layer can simplify advanced flash memory fabrication.

  11. Transparent Flash Memory using Single Ta2O5 Layer for both Charge Trapping and Tunneling Dielectrics

    KAUST Repository

    Hota, Mrinal Kanti; Alshammari, Fwzah H.; Salama, Khaled N.; Alshareef, Husam N.

    2017-01-01

    We report reproducible multibit transparent flash memory in which a single solution-derived Ta2O5 layer is used simultaneously as charge trapping and tunneling layer. This is different from conventional flash cells, where two different dielectric layers are typically used. Under optimized programming/erasing operations, the memory device shows excellent programmable memory characteristics with a maximum memory window of ~10 V. Moreover, the flash memory device shows a stable 2-bit memory performance, good reliability, including data retention for more than 104 sec and endurance performance for more than 100 cycles. The use of a common charge trapping and tunneling layer can simplify advanced flash memory fabrication.

  12. Flash!

    Science.gov (United States)

    Schilling, Govert

    2002-04-01

    About three times a day our sky flashes with a powerful pulse of gamma ray bursts (GRB), invisible to human eyes but not to astronomers' instruments. The sources of this intense radiation are likely to be emitting, within the span of seconds or minutes, more energy than the sun will in its entire 10 billion years of life. Where these bursts originate, and how they come to have such incredible energies, is a mystery scientists have been trying to solve for three decades. The phenomenon has resisted study -- the flashes come from random directions in space and vanish without trace -- until very recently. In what could be called a cinematic conflation of Flash Gordon and The Hunt for Red October, Govert Schilling's Flash!: The Hunt for the Biggest Explosions in the Universe describes the exciting and ever-changing field of GRB research. Based on interviews with leading scientists, Flash! provides an insider's account of the scientific challenges involved in unravelling the enigmatic nature of GRBs. A science writer who has followed the drama from the very start, Schilling describes the ambition and jealousy, collegiality and competition, triumph and tragedy, that exists among those who have embarked on this recherche. Govert Schilling is a Dutch science writer and astronomy publicist. He is a contributing editor of Sky and Telescope magazine, and regularly writes for the news sections of Science and New Scientist. Schilling is the astronomy writer for de Volkskrant, one of the largest national daily newspapers in The Netherlands, and frequently talks about the Universe on Dutch radio broadcasts. He is the author of more than twenty popular astronomy books, and hundreds of newspaper and magazine articles on astronomy.

  13. Four-state non-volatile memory in a multiferroic spin filter tunnel junction

    Science.gov (United States)

    Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

    2016-12-01

    We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

  14. Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

    International Nuclear Information System (INIS)

    Wang Guangli; Chen Yubin; Shi Yi; Pu Lin; Pan Lijia; Zhang Rong; Zheng Youdou

    2010-01-01

    A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method. (semiconductor devices)

  15. Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure

    International Nuclear Information System (INIS)

    Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

    2009-01-01

    The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 μm 2 to 200 x 200 nm 2 . From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I ON /I OFF ∼10 4 ), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10 000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

  16. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    Energy Technology Data Exchange (ETDEWEB)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  17. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    International Nuclear Information System (INIS)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-01-01

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices

  18. Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

    KAUST Repository

    Semple, James

    2017-01-02

    Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

  19. Semiconductor-Free Nonvolatile Resistive Switching Memory Devices Based on Metal Nanogaps Fabricated on Flexible Substrates via Adhesion Lithography

    KAUST Repository

    Semple, James; Wyatt-Moon, Gwenhivir; Georgiadou, Dimitra G.; McLachlan, Martyn A.; Anthopoulos, Thomas D.

    2017-01-01

    Electronic memory cells are of critical importance in modern-day computing devices, including emerging technology sectors such as large-area printed electronics. One technology that has being receiving significant interest in recent years is resistive switching primarily due to its low dimensionality and nonvolatility. Here, we describe the development of resistive switching memory device arrays based on empty aluminum nanogap electrodes. By employing adhesion lithography, a low-temperature and large-area compatible nanogap fabrication technique, dense arrays of memory devices are demonstrated on both rigid and flexible plastic substrates. As-prepared devices exhibit nonvolatile memory operation with stable endurance, resistance ratios >10⁴ and retention times of several months. An intermittent analysis of the electrode microstructure reveals that controlled resistive switching is due to migration of metal from the electrodes into the nanogap under the application of an external electric field. This alternative form of resistive random access memory is promising for use in emerging sectors such as large-area electronics as well as in electronics for harsh environments, e.g., space, high/low temperature, magnetic influences, radiation, vibration, and pressure.

  20. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    Energy Technology Data Exchange (ETDEWEB)

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  1. High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

    Science.gov (United States)

    Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

    2017-08-01

    Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

  2. Memristive behavior in a junctionless flash memory cell

    Energy Technology Data Exchange (ETDEWEB)

    Orak, Ikram [Vocational School of Health Services, Bingöl University, 12000 Bingöl (Turkey); Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl (Turkey); Ürel, Mustafa; Dana, Aykutlu, E-mail: aykutlu@unam.bilkent.edu.tr [UNAM Institute of Materials Science and Nanotechnology, Bilkent University, 06800 Ankara (Turkey); Bakan, Gokhan [Faculty of Engineering, Antalya International University, 07190 Antalya (Turkey)

    2015-06-08

    We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits the pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.

  3. Novel ferroelectric capacitor for non-volatile memory storage and biomedical tactile sensor applications

    International Nuclear Information System (INIS)

    Liu, Shi Yang; Chua, Lynn; Tan, Kian Chuan; Valavan, S.E.

    2010-01-01

    We report on novel ferroelectric thin film compositions for use in non-volatile memory storage and biomedical tactile sensor applications. The lead zirconate titanate (PZT) composition was modified by lanthanum (La 3+ ) (PLZT) and vanadium (V 5+ ) (PZTV, PLZTV) doping. Hybrid films with PZTV and PLZTV as top layers are also made using seed layers of differing compositions using sol-gel and spin coating methods. La 3+ doping decreased the coercive field, polarization and leakage current, while increasing the relative permittivity. V 5+ doping, while having similar effects, results in an enhanced polarization, with comparable dielectric loss characteristics. Complex doping of both La 3+ and V 5+ in PLZTV, while reducing the polarization relative to PZTV, significantly decreases the coercive field. Hybrid films have a greater uniformity of grain formation than non-hybrid films, thus decreasing the coercive field, leakage current and polarization fatigue while increasing the relative permittivity. Analysis using X-ray diffraction (XRD) verified the retention of the PZT perovskite structure in the novel films. PLZT/PZTV has been identified as an optimal ferroelectric film composition due to its desirable ferroelectric, fatigue and dielectric properties, including the highest observed remnant polarization (P r ) of ∼ 25 μC/cm 2 , saturation polarization (P sat ) of ∼ 58 μC/cm 2 and low coercive field (E c ) of ∼ 60 kV/cm at an applied field of ∼ 1000 kV/cm, as well as a low leakage current density of ∼ 10 -5 A/cm 2 at 500 kV/cm and fatigue resistance of up to ∼ 10 10 switching cycles.

  4. Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

    Science.gov (United States)

    Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

    2016-01-01

    Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

  5. Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al2O3 film as the tunnel and blocking oxides for nonvolatile memory applications

    International Nuclear Information System (INIS)

    Lee, Jaesang; Kim, Hyungchul; Park, Taeyong; Ko, Youngbin; Ryu, Jaehun; Jeon, Heeyoung; Park, Jingyu; Jeon, Hyeongtag

    2012-01-01

    Remote plasma atomic layer deposited (RPALD) Al 2 O 3 films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al 2 O 3 film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si +3 and Si +4 , indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/-10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 10 4 s. These results indicate that Al 2 O 3 films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

  6. Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

    Science.gov (United States)

    Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

    2018-01-01

    A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

  7. Transport and Fatigue Properties of Ferroelectric Polymer P(VDF-TrFE) For Nonvolatile Memory Applications

    KAUST Repository

    Hanna, Amir

    2012-06-01

    Organic ferroelectrics polymers have recently received much interest for use in nonvolatile memory devices. The ferroelectric copolymer poly(vinylidene fluoride- trifluoroethylene) , P(VDF-TrFE), is a promising candidate due to its relatively high remnant polarization, low coercive field, fast switching times, easy processability, and low Curie transition. However, no detailed study of charge injection and current transport properties in P(VDF-TrFE) have been reported in the literature yet. Charge injection and transport are believed to affect various properties of ferroelectric films such as remnant polarization values and polarization fatigue behavior.. Thus, this thesis aims to study charge injection in P(VDF-TrFE) and its transport properties as a function of electrode material. Injection was studied for Al, Ag, Au and Pt electrodes. Higher work function metals such as Pt have shown less leakage current compared to lower work function metals such as Al for more than an order of magnitude. That implied n-type conduction behavior for P(VDF-TrFE), as well as electrons being the dominant injected carrier type. Charge transport was also studied as a function of temperature, and two major transport regimes were identified: 1) Thermionic emission over a Schottky barrier for low fields (E < 25 MV/m). 2) Space-Charge-Limited regime at higher fields (25 < E <120 MV/m). We have also studied the optical imprint phenomenon, the polarization fatigue resulting from a combination of broad band optical illumination and DC bias near the switching field. A setup was designed for the experiment, and validated by reproducing the reported effect in polycrystalline Pb(Zr,Ti)O3 , PZT, film. On the other hand, P(VDF-TrFE) film showed no polarization fatigue as a result of optical imprint test, which could be attributed to the large band gap of the material, and the low intensity of the UV portion of the arc lamp white light used for the experiment. Results suggest using high work

  8. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    International Nuclear Information System (INIS)

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-01-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption

  9. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    Energy Technology Data Exchange (ETDEWEB)

    Jovanović, B., E-mail: bojan.jovanovic@lirmm.fr, E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L. [LIRMM—University of Montpellier 2/UMR CNRS 5506, 161 Rue Ada, 34095 Montpellier (France)

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  10. Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

    Science.gov (United States)

    Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

    2018-02-01

    We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

  11. In-chip optical CD measurements for non-volatile memory devices

    Science.gov (United States)

    Vasconi, Mauro; Kremer, Stephanie; Polli, M.; Severgnini, Ermes; Trovati, Silvia S.

    2006-03-01

    A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

  12. A Fault-Tolerant Radiation-Robust Mass Storage Concept for Highly Scaled Flash Memory

    Science.gov (United States)

    Fuchs, Cristian M.; Trinitis, Carsten; Appel, Nicolas; Langer, Martin

    2015-09-01

    Future spacemissions will require vast amounts of data to be stored and processed aboard spacecraft. While satisfying operational mission requirements, storage systems must guarantee data integrity and recover damaged data throughout the mission. NAND-flash memories have become popular for space-borne high performance mass memory scenarios, though future storage concepts will rely upon highly scaled flash or other memory technologies. With modern flash memory, single bit erasure coding and RAID based concepts are insufficient. Thus, a fully run-time configurable, high performance, dependable storage concept, requiring a minimal set of logic or software. The solution is based on composite erasure coding and can be adjusted for altered mission duration or changing environmental conditions.

  13. Atomic layer-deposited Al–HfO{sub 2}/SiO{sub 2} bi-layers towards 3D charge trapping non-volatile memory

    Energy Technology Data Exchange (ETDEWEB)

    Congedo, Gabriele, E-mail: gabriele.congedo@mdm.imm.cnr.it; Wiemer, Claudia; Lamperti, Alessio; Cianci, Elena; Molle, Alessandro; Volpe, Flavio G.; Spiga, Sabina, E-mail: sabina.spiga@mdm.imm.cnr

    2013-04-30

    A metal/oxide/high-κ dielectric/oxide/silicon (MOHOS) planar charge trapping memory capacitor including SiO{sub 2} as tunnel oxide, Al–HfO{sub 2} as charge trapping layer, SiO{sub 2} as blocking oxide and TaN metal gate was fabricated and characterized as test vehicle in the view of integration into 3D cells. The thin charge trapping layer and blocking oxide were grown by atomic layer deposition, the technique of choice for the implementation of these stacks into 3D structures. The oxide stack shows a good thermal stability for annealing temperature of 900 °C in N{sub 2}, as required for standard complementary metal–oxide–semiconductor processes. MOHOS capacitors can be efficiently programmed and erased under the applied voltages of ± 20 V to ± 12 V. When compared to a benchmark structure including thin Si{sub 3}N{sub 4} as charge trapping layer, the MOHOS cell shows comparable program characteristics, with the further advantage of the equivalent oxide thickness scalability due to the high dielectric constant (κ) value of 32, and an excellent retention even for strong testing conditions. Our results proved that high-κ based oxide structures grown by atomic layer deposition can be of interest for the integration into three dimensionally stacked charge trapping devices. - Highlights: ► Charge trapping device with Al–HfO{sub 2} storage layer is fabricated and characterized. ► Al–HfO{sub 2} and SiO{sub 2} blocking oxides are deposited by atomic layer deposition. ► The oxide stack shows a good thermal stability after annealing at 900 °C. ► The device can be efficiently programmed/erased and retention is excellent. ► The oxide stack could be used for 3D-stacked Flash non-volatile memories.

  14. Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

    Science.gov (United States)

    Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

    2009-08-01

    This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

  15. Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

    Science.gov (United States)

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-01-01

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

  16. Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

    Science.gov (United States)

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-07-01

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

  17. Effect of Ag nanoparticles on resistive switching of polyfluorene-based organic non-volatile memory devices

    International Nuclear Information System (INIS)

    Kim, Tae-Wook; Oh, Seung-Hwan; Choi, Hye-Jung; Wang, Gun-Uk; Kim, Dong-Yu; Hwang, Hyun-Sang; Lee, Tak-Hee

    2010-01-01

    The effects of Ag nanoparticles on the switching behavior of polyfluorene-based organic nonvolatile memory devices were investigated. Polyfluorene-derivatives (WPF-oxy-F) with and without Ag nanoparticles were synthesized, and the presence of Ag nanoparticles in Ag-WPF-oxy-F was identified by transmission electron microscopy and X-ray photoelectron spectroscopy analyses. The Ag-nanoparticles did not significantly affect the basic switching performances, such as the current-voltage characteristics, the distribution of on/off resistance, and the retention. The pulse switching time of Ag-WPF-oxy-F was faster than that of WPF-oxy-F. Ag-WPF-oxy-F memory devices showed an area dependence in the high resistance state, implying that formation of a Ag metallic channel for current conduction.

  18. A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

    Science.gov (United States)

    Liu, S. Q.; Wu, N. J.; Ignatiev, A.

    2001-01-01

    A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

  19. 76 FR 40931 - In the Matter of Certain Flash Memory and Products Containing Same; Notice of Commission...

    Science.gov (United States)

    2011-07-12

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-685] In the Matter of Certain Flash Memory and... for importation, and the sale within the United States after importation of certain flash memory and... other agreements, written or oral, express or implied, between the parties concerning the subject matter...

  20. Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

    International Nuclear Information System (INIS)

    Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

    2011-01-01

    This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO 2 /Ta 2 O 5 charge-trapping layer. In comparison to a memory capacitor with a single HfO 2 trapping layer, the erase speed of a memory capacitor with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔV FB = 4 V, the device with a stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO 2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO 2 /Ta 2 O 5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application

  1. Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

    Science.gov (United States)

    Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

    2017-10-11

    The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

  2. NVL-C: Static Analysis Techniques for Efficient, Correct Programming of Non-Volatile Main Memory Systems

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seyong [ORNL; Vetter, Jeffrey S [ORNL

    2016-01-01

    Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard against a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.

  3. Bipolar resistive switching in graphene oxide based metal insulator metal structure for non-volatile memory applications

    Science.gov (United States)

    Singh, Rakesh; Kumar, Ravi; Kumar, Anil; Kashyap, Rajesh; Kumar, Mukesh; Kumar, Dinesh

    2018-05-01

    Graphene oxide based devices have attracted much attention recently because of their possible application in next generation electronic devices. In this study, bipolar resistive switching characteristics of graphene oxide based metal insulator metal structure were investigated for nonvolatile memories. The graphene oxide was prepared by the conventional Hummer's method and deposited on ITO coated glass by spin-coating technique. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament inside the graphene oxide. The conduction mechanism for low and high resistance states are dominated by two mechanism the ohmic conduction and space charge limited current (SCLC) mechanism, respectively. Atomic Force Microscopy, X-ray diffraction, Cyclic-Voltammetry were conducted to observe the morphology, structure and behavior of the material. The fabricated device with Al/GO/ITO structure exhibited reliable bipolar resistive switching with set & reset voltage of -2.3 V and 3V respectively.

  4. Nonvolatile memory characteristics influenced by the different crystallization of Ni-Si and Ni-N nanocrystals

    International Nuclear Information System (INIS)

    Chen, W.-R.; Yeh, J.-L.; Chang, C.-Y.; Chang, T.-C.; Chen, S.-C.

    2008-01-01

    The formation of Ni-Si and Ni-N nanocrystals by sputtering a Ni 0.3 Si 0.7 target in argon and nitrogen environment were proposed in this paper. A transmission electron microscope analysis shows the nanocrystals embedded in the nitride layer. X-ray photoelectron spectroscopy and x-ray diffraction also offer the chemical material analysis of nanocrystals with surrounding dielectric and the crystallization of nanocrystals for different thermal annealing treatments. Nonvolatile Ni-Si nanocrystal memories reveal superior electrical characteristics for charge storage capacity and reliability due to the improvement of thermal annealing treatment. In addition, we used energy band diagrams to explain the significance of surrounding dielectric for reliability

  5. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Chi, Li-Feng, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn; Wang, Sui-Dong, E-mail: wangsd@suda.edu.cn, E-mail: chilf@suda.edu.cn, E-mail: bdong@suda.edu.cn [Jiangsu Key Laboratory for Carbon-Based Functional Materials and Devices, Institute of Functional Nano and Soft Materials (FUNSOM), Soochow University, Suzhou, Jiangsu 215123 (China)

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  6. Electrical bistabilities and memory stabilities of nonvolatile bistable devices fabricated utilizing C60 molecules embedded in a polymethyl methacrylate layer

    International Nuclear Information System (INIS)

    Cho, Sung Hwan; Lee, Dong Ik; Jung, Jae Hun; Kim, Tae Whan

    2009-01-01

    Current-voltage (I-V) measurements on Al/fullerene (C 60 ) molecules embedded in polymethyl methacrylate/Al devices at 300 K showed a current bistability due to the existence of the C 60 molecules. The on/off ratio of the current bistability for the memory devices was as large as 10 3 . The retention time of the devices was above 2.5 x 10 4 s at room temperature, and cycling endurance tests on these devices indicated that the ON and OFF currents showed no degradation until 50 000 cycles. Carrier transport mechanisms for the nonvolatile bistable devices are described on the basis of the I-V experimental and fitting results.

  7. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    International Nuclear Information System (INIS)

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

    2015-01-01

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process

  8. Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture

    OpenAIRE

    senni , sophiane; Torres , Lionel; Sassatelli , Gilles; Gamatié , Abdoulaye; Mussard , Bruno

    2015-01-01

    International audience; Most die area of today's systems-on-chips is occupied by memories. Hence, a significant proportion of total power is spent on memory systems. Moreover, since processing elements have to be fed with instructions and data from memories, memory plays a key role for system's performance. As a result, memories are a critical part of future embedded systems. Continuing CMOS scaling leads to manufacturing constraints and power consumption issues for the current three main mem...

  9. Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

    International Nuclear Information System (INIS)

    Sung, Sihyun; Kim, Tae Whan

    2017-01-01

    Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10 3 was maintained for retention times longer than 1 × 10 4 s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10 3 and 1.4 × 10 3 , respectively. The retention times of the devices before and after bending remained same 1 × 10 4 s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

  10. Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

    Energy Technology Data Exchange (ETDEWEB)

    Sung, Sihyun; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

    2017-07-31

    Highlights: • Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a PMMA layer were fabricated. • The insertion of the PEDOT:PSS layer enhanced the surface uniformity of the AgNW bottom electrode, resulting in improved device performances. • Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices showed clockwise current hysteresis behaviors. • ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. • Memory characteristics of the NVM devices before and after bending were similar. - Abstract: Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 10{sup 3} was maintained for retention times longer than 1 × 10{sup 4} s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 10{sup 3} and 1.4 × 10{sup 3}, respectively. The retention times of the devices before and after bending remained same 1 × 10{sup 4} s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

  11. Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

    Science.gov (United States)

    Natsui, Masanori; Hanyu, Takahiro

    2018-04-01

    In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

  12. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    International Nuclear Information System (INIS)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-01-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm 2 /V s. The unidirectional shift of turn-on voltage (V on ) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V P /V E ) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm 2 /V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V P /V E of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V on shift. As a result, an enlarged memory window of 28.6 V at the V P /V E of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  13. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    Science.gov (United States)

    Wang, Wei; Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-01

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm2/V s. The unidirectional shift of turn-on voltage (Von) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (VP/VE) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm2/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the VP/VE of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional Von shift. As a result, an enlarged memory window of 28.6 V at the VP/VE of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  14. Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

    International Nuclear Information System (INIS)

    Son, Dang Ngoc; Van Duy, Nguyen; Jung, Sungwook; Yi, Junsin

    2010-01-01

    Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiN x films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application

  15. High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

    Science.gov (United States)

    Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

    2017-01-01

    Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

  16. Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

    Science.gov (United States)

    Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

    2017-10-01

    The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

  17. Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction

    International Nuclear Information System (INIS)

    Karimov, Khasan S.; Muqeet Rehman, M.; Zameer Abbas, S.; Ahmad, Zubair; Touati, Farid; Mahroof-Tahir, M.

    2015-01-01

    A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H 2 Pc are fabricated by vacuum deposition of the CuPc and H 2 Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30–40 μm. For the current–voltage (I–V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120–150. Under the switching condition, the electric current increases ∼ 80–100 times. A comparison between the forward and reverse I–V characteristics shows the presence of rectifying behavior. (paper)

  18. Process Qualification Strategy for Advances Embedded Non Volatile Memory Technology : The Philips' 0.18um Embedded Flash Case

    NARCIS (Netherlands)

    Tao, Guoqiao; Scarpa, Andrea; van Dijk, Kitty; Kuper, Fred G.

    2003-01-01

    A qualification strategy for advanced embedded non-volatile memory technology has been revealed. This strategy consists of: a thorough understanding of the requirements, extensive use and frequent update of the FMEA (failure mode effect analysis), a qualification plan with excellent coverage of all

  19. Crossbar memory array of organic bistable rectifying diodes for nonvolatile data storage

    NARCIS (Netherlands)

    Asadi, Kamal; Li, Mengyuan; Stingelin, Natalie; Blom, Paul W. M.; de Leeuw, Dago M.

    2010-01-01

    Cross-talk in memories using resistive switches in a cross-bar geometry can be prevented by integration of a rectifying diode. We present a functional cross bar memory array using a phase separated blend of a ferroelectric and a semiconducting polymer as storage medium. Each intersection acts

  20. Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

    Science.gov (United States)

    Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

    2015-09-01

    Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

  1. A novel sourceline voltage compensation circuit for embedded NOR flash memory

    International Nuclear Information System (INIS)

    Zhang Shengbo; Yang Guangjun; Hu Jian; Xiao Jun

    2014-01-01

    A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data “0”. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data “0” are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process. (semiconductor integrated circuits)

  2. Modeling of apparent activation energy and lifetime estimation in NAND flash memory

    International Nuclear Information System (INIS)

    Lee, Kyunghwan; Shin, Hyungcheol; Kang, Myounggon; Hwang, Yuchul

    2015-01-01

    Misunderstanding apparent activation energy (E aa ) can cause serious error in lifetime predictions. In this paper, the E aa is investigated for sub 20 nm NAND flash memory. In a high-temperature (HT) regime, the interface trap (N it ) recovery mechanism has the greatest impact on the charge loss. However, the values of E aa and E a(Nit) have a wide difference. Also, the lifetime of the device cannot be estimated by the Arrhenius model due to the E aa roll-off behavior. For the first time, we reveal the origin of abnormal characteristics on E aa and derive a mathematical formula for E aa as a function of each E a(mechanism) in NAND flash memory. Using the proposed E aa equation, the accurate lifetime for the device is estimated. (paper)

  3. TID and SEE Response of an Advanced Samsung 4G NAND Flash Memory

    Science.gov (United States)

    Oldham, Timothy R.; Friendlich, M.; Howard, J. W.; Berg, M. D.; Kim, H. S.; Irwin, T. L.; LaBel, K. A.

    2007-01-01

    Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment.

  4. Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

    Science.gov (United States)

    Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

    2016-07-01

    Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

  5. Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

    International Nuclear Information System (INIS)

    Avila-Nino, J.A.; Segura-Cardenas, E.; Sustaita, A.O.; Cruz-Cruz, I.; Lopez-Sandoval, R.; Reyes-Reyes, M.

    2011-01-01

    We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

  6. Nonvolatile write-once-read-many-times memory device with functionalized-nanoshells/PEDOT:PSS nanocomposites

    Energy Technology Data Exchange (ETDEWEB)

    Avila-Nino, J.A.; Segura-Cardenas, E. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Sustaita, A.O. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Cruz-Cruz, I. [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico); Lopez-Sandoval, R. [Instituto Potosino de Investigacion Cientifica y Tecnologica, Camino a la presa San Jose 2055, CP 78216, San Luis Potosi (Mexico); Reyes-Reyes, M., E-mail: reyesm@iico.uaslp.mx [Universidad Autonoma de San Luis Potosi, Instituto de Investigacion en Comunicacion Optica, Alvaro Obregon 64 Zona Centro, 78000 SLP (Mexico)

    2011-03-25

    We have investigated the memory effect of the nanocomposites of functionalized carbon nanoshells (f-CNSs) mixed with poly(3,4-ethylenedioxythiophene) doped with polystyrenesulfonate (PEDOT:PSS) polymer. The f-CNSs were synthesized by the spray pyrolysis method and functionalized in situ with functional groups (OH, COOH, C-H, C-OH) with the aim of improving their compatibility in the aqueous dispersion of PEDOT:PSS. The current-voltage (I-V) sweep curves at room temperature for the Al/f-CNSs, for certain concentrations range, embedded in a PEDOT:PSS layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. The memory effect observed in the devices can be explained due to the existence of trapped charges in the f-CNSs/PEDOT:PSS layer. The carrier transport mechanisms for the memory devices is studied and discussed.

  7. Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface

    Science.gov (United States)

    2016-03-17

    SSDs), in order to evaluate advanced Flash memory devices that are not available as individual components on the open market and for which no...measurable changes due to memory cell stress is shown in Figure 3 for a 42 nm SLC Samsung K9K8G08U0D device. Two logical pages were characterized... Samsung K9K8G08U0D device to change from a logical ‘0’ to a logical ‘1’ were measured. Three bits on the page were then fully programmed and erased

  8. Analysis of the X-ray microbeam test result of the flash memories

    International Nuclear Information System (INIS)

    Yan Yihua; Ding Lili; Chen Wei; Guo Hongxia; Guo Xiaoqiang; Lin Dongsheng; Zhang Keying; Zhang Fengqi; Deng Yuliang; Fan Ruyu

    2013-01-01

    Background: The failure phenomenon is difficult to analyze for the flash memories when the whole chip is exposed to irradiation since both the memory array and the peripheral circuits might be degraded. Purpose: In order to detect the radiation susceptibility and corresponding phenomenon of the related circuits that included in the flash memories, the X-ray microbeam is used as the radiation source instead of 60 Co. Methods: The failure phenomenon is studied respectively when the memory array, decoder circuits, the charge pump circuits as well as the I/O circuits are exposed to radiation. The errors are mapped according to the logical address and the failure mechanism is analyzed based on the circuits. Results: Irradiated on the memory .array win lead to regularly distributed 0→1 bit flips, while only 1→0 are found when the row decoder is under exposure. Degradation of the charge pump circuits would lead to the erase/program functional failure. Conclusions: The results suggest that the X-ray microbeam radiation test is a good method for detecting the radiation susceptibility of the integrated circuits that contains lots of circuit modules. (authors)

  9. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    International Nuclear Information System (INIS)

    Che, Yongli; Zhang, Yating; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

    2016-01-01

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV th  ∼ 15 V) and a long retention time (>10 5  s). The magnitude of ΔV th depended on both P/E voltages and the bias voltage (V DS ): ΔV th was a cubic function to V P/E and linearly depended on V DS . Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  10. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    Energy Technology Data Exchange (ETDEWEB)

    Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); Cao, Xiaolong [Institute of Laser and Opto-Electronics, College of Precision Instruments and Opto-Electronics Engineering, Tianjin University, Tianjin 300072 (China); Key Laboratory of Opto-Electronics Information Technology, Ministry of Education, Tianjin University, Tianjin 300072 (China); College of Mechanical and Electronic Engineering, Shandong University of Science and Technology, Qingdao 266590 (China); Dai, Haitao [Tianjin Key Laboratory of Low Dimensional Materials Physics and Preparing Technology, School of Science, Tianjin University, Tianjin 300072 (China); Yang, Junbo [Center of Material Science, National University of Defense Technology, Changsha 410073 (China)

    2016-07-04

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  11. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  12. Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

    Science.gov (United States)

    Matsui, Chihiro; Kinoshita, Reika; Takeuchi, Ken

    2018-04-01

    A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

  13. The origin of traps and the effect of nitrogen plasma in oxide-nitride-oxide structures for non-volatile memories

    International Nuclear Information System (INIS)

    Kim, W. S.; Kwak, D. W.; Oh, J. S.; Lee, D. W.; Cho, H. Y.

    2010-01-01

    Ultrathin oxide-nitride-oxide (ONO) dielectric stacked layers are fundamental structures of silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory devices in which information is known to be stored as charges trapped in silicon nitride. Deep-level transient spectroscopy (DLTS) and a capacitance-voltage (CV) analysis were introduced to observe the trap behavior related to the memory effect in memory devices. The DLTS results verified that the nitride-related traps were a dominant factor in the memory effect. The energy of hole traps was 0.307 eV above the balance band. To improve the memory effects of the non-volatile memory devices with ONO structures, we introduced a nitrogen plasma treatment. After the N-plasma treatment, the flat-band voltage shift (ΔV FB ) was increased by about 1.5 times. The program and the erase (P-E) characteristics were also shown to be better than those for the as-ONO structure. In addition, the retention characteristics were improved by over 2.4 times.

  14. An integrated lithography concept with application on 45-nm ½ pitch flash memory devices

    Science.gov (United States)

    Dusa, Mircea; Engelen, Andre; Finders, Jo

    2006-03-01

    It is well accepted to judge imaging capability of an exposure tool primarily on printing equal line-spaces, at a minimum ½ pitch. Further on, combining line-space minimum ½ pitches with scanner maximum NA, defines the process k I. From a lithographer viewpoint, flash memory device is the perfect candidate to achieve lowest k I lithography for a given NA. This is justified by flash layout specific, with regular and relative simple 1-D topology of the critical layers that look like line-space gratings. In reality, flash layout presents a subtle topology and cannot be considered a simple 1-D line-space problem. Uniqueness to flash layout is the array-end zones, where pattern regularity is broken up by features with dimensions and separation of n x ½ pitch, where n is an integer number that we used in this work to manipulate litho process latitudes. Integrated lithography concept seeks to tweak flash pattern details and tune it with scanner control parameters. We introduce feature-center placement through focus and dose as the metric to characterize a cross-coupling phenomena occurring between adjacent features located at array-end of typical flash poly wordline layer. We comparedthe metric behavior with usual litho process window parameters and identified interactions with scanner CDU control parameters. We show how feature-center placement errors are direct functions of optical and physical characteristics of mask materials, attenuated PSM or binary, and of layout array-end topology. Imaging at extreme low-k I, effects from layout specifics and mask materials are best characterized by full vector, rigorous EM simulation, instead of scalar approach, typically used for OPC treatment. Predicted CDU performance of 1.2NA scanner, based on integrated lithography concept, matched very well the experimental results in printing 45nm ½ pitch flash wordline layer. Results show that 1.2NA scanner, operating at 0.28 k I could be an effective lithography solution for 45nm

  15. Studies on nonvolatile resistance memory switching in ZnO thin films

    Indian Academy of Sciences (India)

    Six decades of research on ZnO has recently sprouted a new branch in the domain of resistive random access memories. Highly resistive and c-axis oriented ZnO thin films were grown by us using d.c. discharge assisted pulsed laser deposition on Pt/Ti/SiO2/Si substrates at room temperature. The resistive switching ...

  16. Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications

    KAUST Repository

    Ghoneim, Mohamed T.; Zidan, Mohammed A.; Al-Nassar, Mohammed Y.; Hanna, Amir; Kosel, Jü rgen; Salama, Khaled N.; Hussain, Muhammad Mustafa

    2015-01-01

    A flexible version of traditional thin lead zirconium titanate ((Pb1.1Zr0.48Ti0.52O3)-(PZT)) based ferroelectric random access memory (FeRAM) on silicon shows record performance in flexible arena. The thin PZT layer requires lower operational

  17. Studies on nonvolatile resistance memory switching in ZnO thin films

    Indian Academy of Sciences (India)

    Administrator

    (Kund et al 2005), phase change random access memory. (PRAM) (Lai 2003) and ..... 2008) and can be explained in terms of the aforemen- tioned filamentary ... Zhang S, Long S, Guan W, Liu Q, Wang Q and Liu M 2009 J. Phys. D: Appl. Phys.

  18. Integration of ammonia-plasma-functionalized graphene nanodiscs as charge trapping centers for nonvolatile memory applications

    KAUST Repository

    Wang, Jer-Chyi; Chang, Kai-Ping; Lin, Chih-Ting; Su, Ching-Yuan; Gü neş, Fethullah; Boutchich, Mohamed; Chen, Chang-Hsiao; Chen, Ching-Hsiang; Chen, Ching-Shiun; Li, Lain-Jong; Lai, Chao-Sung

    2016-01-01

    that act as CTSs, as observed by Raman and Fourier transform infrared spectroscopy. This inherently enhances the density of CTSs in the GNDs, as a result, the memory window becomes more than 2.4 V and remains stable after 104 operating cycles. The charge

  19. Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS2 quantum dot-polymethylmethacrylate nanocomposites

    International Nuclear Information System (INIS)

    Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

    2014-01-01

    Nonvolatile memory devices based on CuInS 2 (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10 −10 was maintained for 8 × 10 3 cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10 6 cycles converged to 2.40 × 10 −10 , indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams

  20. Impact of time and space evolution of ion tracks in nonvolatile memory cells approaching nanoscale

    International Nuclear Information System (INIS)

    Cellere, G.; Paccagnella, A.; Murat, M.; Barak, J.; Akkerman, A.; Harboe-Sorensen, R.; Virtanen, A.; Visconti, A.; Bonanomi, M.

    2010-01-01

    Swift heavy ions impacting on matter lose energy through the creation of dense tracks of charges. The study of the space and time evolution of energy exchange allows understanding the single event effects behavior in advanced microelectronic devices. In particular, the shrinking of minimum feature size of most advanced memory devices makes them very interesting test vehicles to study these effects since the device and the track dimensions are comparable; hence, measured effects are directly correlated with the time and space evolution of the energy release. In this work we are studying the time and space evolution of ion tracks by using advanced non volatile memories and Monte Carlo simulations. Experimental results are very well explained by the theoretical calculations.

  1. Silicon-based thin films as bottom electrodes in chalcogenide nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seung-Yun [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)], E-mail: seungyun@etri.re.kr; Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Park, Young-Sam; Ryu, Sang-Ouk; Yu, Byoung-Gon; Kim, Sang-Hoon; Lee, Sang-Heung [IT Convergence and Components Laboratory, Electronics and Telecommunications Research Institute (ETRI), Yuseong-gu, Daejeon 305-350 (Korea, Republic of)

    2007-10-31

    The effect of the electrical resistivity of a silicon-germanium (SiGe) thin film on the phase transition in a GeSbTe (GST) chalcogenide alloy and the manufacturing aspect of the fabrication process of a chalcogenide memory device employing the SiGe film as bottom electrodes were investigated. While p-type SiGe bottom electrodes were formed using in situ doping techniques, n-type ones could be made in a different manner where phosphorus atoms diffused from highly doped silicon underlayers to undoped SiGe films. The p-n heterojunction did not form between the p-type GST and n-type SiGe layers, and the semiconduction type of the SiGe alloys did not influence the memory device switching. It was confirmed that an optimum resistivity value existed for memory operation in spite of proportionality of Joule heating to electrical resistivity. The very high resistivity of the SiGe film had no effect on the reduction of reset current, which might result from the resistance decrease of the SiGe alloy at high temperatures.

  2. In search of the next memory inside the circuitry from the oldest to the emerging non-volatile memories

    CERN Document Server

    Campardo, Giovanni

    2017-01-01

    This book provides students and practicing chip designers with an easy-to-follow yet thorough, introductory treatment of the most promising emerging memories under development in the industry. Focusing on the chip designer rather than the end user, this book offers expanded, up-to-date coverage of emerging memories circuit design. After an introduction on the old solid-state memories and the fundamental limitations soon to be encountered, the working principle and main technology issues of each of the considered technologies (PCRAM, MRAM, FeRAM, ReRAM) are reviewed and a range of topics related to design is explored: the array organization, sensing and writing circuitry, programming algorithms and error correction techniques are reviewed comparing the approach followed and the constraints for each of the technologies considered. Finally the issue of radiation effects on memory devices has been briefly treated. Additionally some considerations are entertained about how emerging memories can find a place in the...

  3. A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

    International Nuclear Information System (INIS)

    Wu, Ming-Chi; Tseng, Tseung-Yuen; Jang, Wen-Yueh; Lin, Chen-Hsi

    2012-01-01

    Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO 2 /Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO 2 /Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO 2 -based RRAM is a prospective alternative for nonvolatile multilevel memory device applications. (paper)

  4. Emerging memory technologies design, architecture, and applications

    CERN Document Server

    2014-01-01

    This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits. • Provides a comprehensive reference on designing modern circuits with emerging, non-volatile memory technologies, such as MRAM and PCRAM; • Explores new design opportunities offered by emerging memory technologies, from a holistic perspective; • Describes topics in technology, modeling, architecture and applications; • Enables circuit designers to ex...

  5. Characterizations of MoTiO5 flash memory devices with post-annealing

    International Nuclear Information System (INIS)

    Kao, Chyuan Haur; Chen, Hsiang; Chen, Su Zhien; Chen, Yu Jie; Chu, Yu Cheng

    2014-01-01

    In this study, high-K MoTiO 5 dielectrics were applied as charge trapping layers in fabricated metal-oxide-high-K MoTiO 5 -oxide-Si-type memory devices. Among the applied MoTiO 5 trapping layer treatment conditions, annealing at 900 °C yielded devices that exhibited superior memory performance, such as a larger memory window and faster programming/erasing speed. Multiple material analyses, namely X-ray diffraction, X-ray photoelectron spectroscopy, and atomic force microscopy, confirmed that annealing at 900 °C can improve the material quality as a result of crystallization. The fabricated MoTiO 5 -based memory devices show potential for future commercial memory device applications. - Highlights: • MoTiO5-based flash memories have been fabricated. • MoTiO5 trapping layers could be formed by co-sputtering. • MoTiO5 layers with annealing exhibited a good memory performance. • Multiple material analyses confirm that annealing enhanced crystallization

  6. Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device

    Directory of Open Access Journals (Sweden)

    W. J. Liu

    2016-01-01

    Full Text Available We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

  7. 75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

    Science.gov (United States)

    2010-12-29

    ... Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ's Final... flash memory chips and products containing the same by reason of infringement of various claims of... practices or exploits the '877 patent does not exist, nor is such an industry in the process of being...

  8. A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure

    International Nuclear Information System (INIS)

    Wu Dake; Huang Ru; Wang Pengfei; Tang Poren; Wang Yangyuan

    2008-01-01

    In this paper, a low-voltage recessed channel SONOS flash memory using the gate-injection program/erase method is proposed and investigated for NAND application. It is shown that the proposed flash memory can achieve 8 V lower programming voltage compared with planar flash memory, due to the effective capacitance coupling and the electric-field enhancement by combining the recessed channel structure and the gate-injection program/erase method. In addition, more than 30% larger threshold voltage window and improved short channel effects can be obtained in the proposed flash memory

  9. Subattoampere current induced by single ions in silicon oxide layers of nonvolatile memory cells

    International Nuclear Information System (INIS)

    Cellere, G.; Paccagnella, A.; Larcher, L.; Visconti, A.; Bonanomi, M.

    2006-01-01

    A single ion impinging on a thin silicon dioxide layer generates a number of electron/hole pairs proportional to its linear energy transfer coefficient. Defects generated by recombination can act as a conductive path for electrons that cross the oxide barrier, thanks to a multitrap-assisted mechanism. We present data on the dependence of this phenomenon on the oxide thickness by using floating gate memory arrays. The tiny number of excess electrons stored in these devices allows for extremely high sensitivity, impossible with any direct measurement of oxide leakage current. Results are of particular interest for next generation devices

  10. Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

    International Nuclear Information System (INIS)

    Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

    2012-01-01

    Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH 3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH 3 -annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO 2 interface.

  11. The microstructure investigation of GeTi thin film used for non-volatile memory

    International Nuclear Information System (INIS)

    Shen Jie; Liu Bo; Song Zhitang; Xu Cheng; Liang Shuang; Feng Songlin; Chen Bomy

    2008-01-01

    GeTi thin film has been found to have the reversible resistance switching property in our previous work. In this paper, the microstructure of this material with a given composition was investigated. The film was synthesized by magnetron sputtering and treated by the rapid temperature process. The results indicate a coexist status of amorphous and polycrystalline states in the as-deposited GeTi film, and the grains in the film are extremely fine. Furthermore, not until the film annealed at 600 deg. C, can the polycrystalline state be detected by X-ray diffraction. Based on the morphological analysis, the sputtered GeTi has the column growth tendency, and the column structure vanishes with the temperature increasing. The microstructure and thermal property analysis indicate that GeTi does not undergo evident phase change process during the annealing process, which makes the switching mechanism of GeTi different from that of chalcogenide memory material, the most widely used phase change memory material

  12. Operational method of a ferroelectric (Fe)-NAND flash memory array

    International Nuclear Information System (INIS)

    Wang, Shouyu; Takahashi, Mitue; Li, Qiu-Hong; Sakai, Shigeki; Takeuchi, Ken

    2009-01-01

    Operations of arrayed ferroelectric (Fe)-NAND flash memory cells: erase, program and read were demonstrated for the first time using a small cell array of four word lines by two NAND strings. The memory cells and select-gate transistors were all n-channel Pt/SrBi 2 Ta 2 O 9 /Hf-Al-O/Si ferroelectric-gate field effect transistors. The erase was performed by applying 10 µs wide 7 V pulses to n- and p-wells. The program was performed by applying 10 µs wide 7 V pulses to selected word lines. Accumulated read currents of 51 programmed patterns in the Fe-NAND flash memory cell array successfully showed distribution of the two distinguishable '0' and '1' states. The margin between the two states became wider by applying a verification technique in programming a cell out of the eight. Retention times of bit-line currents were obtained over 33 h for both the '0' and '1' states in a program pattern

  13. A light writable microfluidic "flash memory": optically addressed actuator array with latched operation for microfluidic applications.

    Science.gov (United States)

    Hua, Zhishan; Pal, Rohit; Srivannavit, Onnop; Burns, Mark A; Gulari, Erdogan

    2008-03-01

    This paper presents a novel optically addressed microactuator array (microfluidic "flash memory") with latched operation. Analogous to the address-data bus mediated memory address protocol in electronics, the microactuator array consists of individual phase-change based actuators addressed by localized heating through focused light patterns (address bus), which can be provided by a modified projector or high power laser pointer. A common pressure manifold (data bus) for the entire array is used to generate large deflections of the phase change actuators in the molten phase. The use of phase change material as the working media enables latched operation of the actuator array. After the initial light "writing" during which the phase is temporarily changed to molten, the actuated status is self-maintained by the solid phase of the actuator without power and pressure inputs. The microfluidic flash memory can be re-configured by a new light illumination pattern and common pressure signal. The proposed approach can achieve actuation of arbitrary units in a large-scale array without the need for complex external equipment such as solenoid valves and electrical modules, which leads to significantly simplified system implementation and compact system size. The proposed work therefore provides a flexible, energy-efficient, and low cost multiplexing solution for microfluidic applications based on physical displacements. As an example, the use of the latched microactuator array as "normally closed" or "normally open" microvalves is demonstrated. The phase-change wax is fully encapsulated and thus immune from contamination issues in fluidic environments.

  14. Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

    Science.gov (United States)

    Jin, Zhiwen; Liu, Guo; Wang, Jizheng

    2013-05-01

    Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

  15. Fatigue-free lead zirconate titanate-based capacitors for nonvolatile memories

    International Nuclear Information System (INIS)

    Shannigrahi, S. R.; Jang, Hyun M.

    2001-01-01

    The development of lead zirconate titanate (PZT)-based capacitors has been a long time goal of ferroelectric random access memories (FRAM). However, PZT-based perovskites with common platinum (Pt) electrodes have suffered from a significant reduction of the remanent polarization (P r ) after a certain number of read/write cycles (electrical fatigue). We now report the development of fatigue-free lanthanum-modified PZT capacitors using common Pt electrodes. The capacitors fabricated at 580 o C by applying a PZT seed layer exhibited fatigue-free behavior up to 6.5 x 10 10 switching cycles, a quite stable charge retention profile with time, and comparatively high P r values, all of which assure their suitability for practical FRAM applications. Copyright 2001 American Institute of Physics

  16. High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

    Energy Technology Data Exchange (ETDEWEB)

    Xiang, Lanyi; Ying, Jun; Han, Jinhua; Zhang, Letian, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn; Wang, Wei, E-mail: zlt@jlu.edu.cn, E-mail: wwei99@jlu.edu.cn [State Key Laboratory on Integrated Optoelectronics, College of Electronic Science and Engineering, Jilin University, 2699 Qianjin Street, Changchun 130012 (China)

    2016-04-25

    In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (V{sub on}) and severe degradation of the memory window (ΔV{sub on}) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electrons transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of V{sub on} at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔV{sub on} of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.

  17. Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

    Science.gov (United States)

    Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Kim, Hak; Phan, Anthony; Seidleck, Christina; LaBel, Kenneth

    2016-01-01

    We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

  18. The influence of Ti doping and annealing on Ce_2Ti_2O_7 flash memory devices

    International Nuclear Information System (INIS)

    Kao, Chyuan Haur; Chen, Su Zhien; Luo, Yang; Chiu, Wang Ting; Chiu, Shih Wei; Chen, I Chien; Lin, Chan-Yu; Chen, Hsiang

    2017-01-01

    Highlights: • Ce_2Ti_2O_7 flash memories have been fabricated. • Material quality can be improved by annealing. • The memory performance can be enhanced by Ti doping. • Ti doping and annealing can reinforce crystallization. - Abstract: In this research, a CeO_2 film with Ti doping was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. Since incorporation of Ti atoms into the film could fix dangling bonds and defects, the Ce_2Ti_2O_7 trapping layer with annealing treatment could have a larger memory window and a faster programming/erasing speed. To confirm the origin, multiple material analyses indicate that annealing at an appropriate temperature and Ti doping could enhance crystallization. The Ce_2Ti_2O_7-based memory device is promising for future industrial flash memory applications.

  19. A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

    Science.gov (United States)

    Guo, Jiarong

    2017-04-01

    A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 °C. Project supported by the National Natural Science Fundation of China (No. 61376028).

  20. Fast neutron irradiation tests of flash memories used in space environment at the ISIS spallation neutron source

    Directory of Open Access Journals (Sweden)

    C. Andreani

    2018-02-01

    Full Text Available This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source. The two neutron beam lines are set up to mimic the space environment spectra and allow neutron irradiation tests on Flash memories in the neutron energy range above 10 MeV and up to 800 MeV. The ISIS neutron energy spectrum is similar to the one occurring in the atmospheric as well as in space and planetary environments, with intensity enhancements varying in the range 108- 10 9 and 106- 10 7 respectively. Such conditions are suitable for the characterization of the atmospheric, space and planetary neutron radiation environments, and are directly applicable for accelerated tests of electronic components as demonstrated here in benchmark measurements performed on flash memories.

  1. Fast neutron irradiation tests of flash memories used in space environment at the ISIS spallation neutron source

    Science.gov (United States)

    Andreani, C.; Senesi, R.; Paccagnella, A.; Bagatin, M.; Gerardin, S.; Cazzaniga, C.; Frost, C. D.; Picozza, P.; Gorini, G.; Mancini, R.; Sarno, M.

    2018-02-01

    This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source. The two neutron beam lines are set up to mimic the space environment spectra and allow neutron irradiation tests on Flash memories in the neutron energy range above 10 MeV and up to 800 MeV. The ISIS neutron energy spectrum is similar to the one occurring in the atmospheric as well as in space and planetary environments, with intensity enhancements varying in the range 108- 10 9 and 106- 10 7 respectively. Such conditions are suitable for the characterization of the atmospheric, space and planetary neutron radiation environments, and are directly applicable for accelerated tests of electronic components as demonstrated here in benchmark measurements performed on flash memories.

  2. Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

    Energy Technology Data Exchange (ETDEWEB)

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M. [CEMES-CNRS and Université de Toulouse, 29 rue J. Marvig, 31055 Toulouse Cedex 04 (France); Spiegel, Y.; Torregrosa, F. [IBS, Rue G Imbert Prolongée, ZI Peynier-Rousset, 13790 Peynier (France); Normand, P.; Dimitrakis, P.; Kapetanakis, E. [NCSRD, Terma Patriarchou Gregoriou, 15310 Aghia Paraskevi (Greece); Sahu, B. S.; Slaoui, A. [ICube, 23 Rue du Loess, 67037 Strasbourg Cedex 2 (France)

    2013-12-16

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

  3. Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

    Science.gov (United States)

    Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

    2015-03-14

    The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels.

  4. Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for nonvolatile memories

    International Nuclear Information System (INIS)

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

    2013-01-01

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO 2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories

  5. High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

    International Nuclear Information System (INIS)

    Nedic, Stanko; Welland, Mark; Tea Chun, Young; Chu, Daping; Hong, Woong-Ki

    2014-01-01

    A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10 5 , a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10 4 s

  6. Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

    Science.gov (United States)

    Huang, Min; Liu, Zhaoqing; Qiao, Liyan

    2014-01-01

    While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme. PMID:25310473

  7. Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

    Directory of Open Access Journals (Sweden)

    Min Huang

    2014-10-01

    Full Text Available While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it’s critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB pages which are more reliable than least significant bit (LSB pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme.

  8. Scaling Techniques for Massive Scale-Free Graphs in Distributed (External) Memory

    KAUST Repository

    Pearce, Roger; Gokhale, Maya; Amato, Nancy M.

    2013-01-01

    We present techniques to process large scale-free graphs in distributed memory. Our aim is to scale to trillions of edges, and our research is targeted at leadership class supercomputers and clusters with local non-volatile memory, e.g., NAND Flash

  9. Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

    International Nuclear Information System (INIS)

    Gelinck, Gerwin H; Cobb, Brian; Van Breemen, Albert J J M; Myny, Kris

    2015-01-01

    Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these. (paper)

  10. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    Science.gov (United States)

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-04

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  11. Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

    Science.gov (United States)

    Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

    2011-08-01

    This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

  12. Non-volatile nano-floating gate memory with Pt-Fe{sub 2}O{sub 3} composite nanoparticles and indium gallium zinc oxide channel

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Quanli [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Lee, Seung Chang; Baek, Yoon-Jae [Myongji University, Department of Materials Science and Engineering (Korea, Republic of); Lee, Hyun Ho [Myongji University, Department of Chemical Engineering (Korea, Republic of); Kang, Chi Jung [Myongji University, Department of Nano Science and Engineering (Korea, Republic of); Kim, Hyun-Mi; Kim, Ki-Bum [Seoul National University, Department of Materials Science and Engineering (Korea, Republic of); Yoon, Tae-Sik, E-mail: tsyoon@mju.ac.kr [Myongji University, Department of Nano Science and Engineering (Korea, Republic of)

    2013-02-15

    Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe{sub 2}O{sub 3} composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe{sub 2}O{sub 3} nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of {approx}3 Multiplication-Sign 10{sup 11} cm{sup -2} by a solution-based dip-coating process. The Pt core ({approx}3 nm in diameter) and Fe{sub 2}O{sub 3}-shell ({approx}6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of {approx}4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of {approx}0.66 V after pulse programming at +20 V for 1 s with retention > {approx}65 % after 10{sup 4} s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

  13. Novel Organic Phototransistor-Based Nonvolatile Memory Integrated with UV-Sensing/Green-Emissive Aggregation Enhanced Emission (AEE)-Active Aromatic Polyamide Electret Layer.

    Science.gov (United States)

    Cheng, Shun-Wen; Han, Ting; Huang, Teng-Yung; Chang Chien, Yu-Hsin; Liu, Cheng-Liang; Tang, Ben Zhong; Liou, Guey-Sheng

    2018-05-30

    A novel aggregation enhanced emission (AEE)-active polyamide TPA-CN-TPE with a high photoluminesence characteristic was successfully synthesized by the direct polymerization of 4-cyanotriphenyl diamine (TPA-CN) and tetraphenylethene (TPE)-containing dicarboxylic acid. The obtained luminescent polyamide plays a significant role as the polymer electret layer in organic field-effect transistors (OFETs)-type memory. The strong green emission of TPA-CN-TPE under ultraviolet (UV) irradiation can be directly absorbed by the pentacene channel, displaying a light-induced programming and voltage-driven erasing organic phototransistor-based nonvolatile memory. Memory window can be effectively manipulated between the programming and erasing states by applying UV light illumination and electrical field, respectively. The photoinduced memory behavior can be maintained for over 10 4 s between these two states with an on/off ratio of 10 4 , and the memory switching can be steadily operated for many cycles. With high photoresponsivity ( R) and photosensitivity ( S), this organic phototransistor integrated with AEE-active polyamide electret layer could serve as an excellent candidate for UV photodetectors in optical applications. For comparison, an AEE-inactive aromatic polyimide TPA-PIS electret with much weaker solid-state emission was also applied in the same OFETs device architecture, but this device did not show any UV-sensitive and UV-induced memory characteristics, which further confirmed the significance of the light-emitting capability of the electret layer.

  14. Sentinel 2 MMFU: The first European Mass Memory System Based on NAND-Flash Storage Technology

    Science.gov (United States)

    Staehle, M.; Cassel, M.; Lonsdorfer, U.; Gliem, F.; Walter, D.; Fichna, T.

    2011-08-01

    Sentinel-2 is the multispectral optical mission of the EU-ESA GMES (Global Monitoring for Environment and Security) program, currently under development by Astrium-GmbH in Friedrichshafen (Germany) for a launch in 2013. The mission features a 490 Mbit/s optical sensor operating at high duty cycles, requiring in turn a large 2.4 Tbit on-board storage capacity.The required storage capacity motivated the selection of the NAND-Flash technology which was already secured by a lengthy period (2004-2009) of detailed testing, analysis and qualification by Astrium GmbH, IDA and ESTEC. The mass memory system is currently being realized by Astrium GmbH.

  15. Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

    Science.gov (United States)

    Chen, Dakai; Wilcox, Edward; Ladbury, Raymond L.; Kim, Hak; Phan, Anthony; Seidleck, Christina; Label, Kenneth

    2016-01-01

    We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

  16. Phase change memory

    CERN Document Server

    Qureshi, Moinuddin K

    2011-01-01

    As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the requirements for a next generation memory technology and briefly surveys the landscape of novel non-volatile memories. Among these, Phase Change Memory (PCM) is emerging as a leading contender, and the authors discuss the material, device, and circuit advances underlying this exciting technology. The lecture then describes architectural solutions t

  17. An Analysis of MARSIS Radar Flash Memory Data from Lunae Planum, Mars: Searching for Subsurface Structures.

    Science.gov (United States)

    Caprarelli, G.; Orosei, R.; Mastrogiuseppe, M.; Cartacci, M.

    2017-12-01

    Lunae Planum is a Martian plain measuring approximately 1000 km in width and 2000 km in length, centered at coordinates 294°E-11°N. MOLA elevations range from +2500 m to +500 m in the south, gently sloping northward to -500 m. The plain is part of a belt of terrains located between the southern highlands and the northern lowlands, that are transitional in character (e.g., by elevation, age and morphology). These transitional terrains are poorly understood, in part because of their relative lack of major geomorphological features. They record however a very significant part of Mars's geologic history. The most evident features on Lunae Planum's Hesperian surface are regularly spaced, longitudinally striking, wrinkle ridges. These indicate the presence of blind thrust faults cutting through thick stacks of layers of volcanic or sedimentary rocks. The presence of fluidized ejecta craters scattered all over the region suggests also the presence of ice or volatiles in the subsurface. In a preliminary study of Lunae Planum's subsurface we used the Mars Express ground penetrating radar MARSIS dataset [1], in order to detect reflectors that could indicate the presence of fault planes or layering. Standard radargrams however, provided no evidence of changes in value of dielectric constant that could indicate possible geologic discontinuities or stratification of physically diverse materials. We thus started a new investigation based on processing of raw MARSIS data. Here we report on the preliminary results of this study. We searched the MARSIS archive for raw data stored in flash memory. When operating with flash storage, the radar collects 2 frequency bands along-track covering a distance = 100-250 km, depending on the orbiter altitude [2]. We found flash memory data from 24 orbits over the area. We processed the data focusing radar returns in off-nadir directions, to maximize the likelihood of detecting sloping subsurface structures, including those striking parallel

  18. Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

    Science.gov (United States)

    Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

    2012-08-01

    The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

  19. Fabrication and operation methods of a one-time programmable (OTP) nonvolatile memory (NVM) based on a metal-oxide-semiconductor structure

    International Nuclear Information System (INIS)

    Cho, Seongjae; Lee, Junghoon; Jung, Sunghun; Park, Sehwan; Park, Byunggook

    2011-01-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array based on a metal-insulator-semiconductor (MIS) structure is proposed. The Iindividual memory device has a vertical channel of a silicon diode. Historically, OTP memories were widely used for read-only-memories (ROMs), in which the most basic system architecture model was to store central processing unit (CPU) instructions. By grafting the nanoscale fabrication technology and novel structuring onto the concept of the OTP memory, innovative high-density NVM appliances for mobile storage media may be possible. The program operation is performed by breaking down the thin oxide layer between the pn diode structure and the wordline (WL). The programmed state can be identified by an operation that reads the leakage currents through the broken oxide. Since the proposed OTP NVM is based on neither a transistor structure nor a charge storing mechanism, it is highly reliable and functional for realizing the ultra-large scale integration. The operation physics and the fabrication processes are also explained in detail.

  20. Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

    Science.gov (United States)

    Singh, Kirandeep; Kaur, Davinder

    2017-02-01

    The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

  1. A memristor-based nonvolatile latch circuit

    International Nuclear Information System (INIS)

    Robinett, Warren; Pickett, Matthew; Borghetti, Julien; Xia Qiangfei; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

    2010-01-01

    Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

  2. Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

    Science.gov (United States)

    Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

    2018-05-01

    A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

  3. Laser Nanosoldering of Golden and Magnetite Particles and its Possible Application in 3D Printing Devices and Four-Valued Non-Volatile Memories

    Directory of Open Access Journals (Sweden)

    Jaworski Jacek

    2015-12-01

    Full Text Available In recent years the 3D printing methods have been developing rapidly. This article presents researches about a new composite consisted of golden and magnetite nanoparticles which could be used for this technique. Preparation of golden nanoparticles by laser ablation and their soldering by laser green light irradiation proceeded in water environment. Magnetite was obtained on chemical way. During experiments it was tested a change of a size of nanoparticles during laser irradiation, surface plasmon resonance, zeta potential. The obtained golden - magnetite composite material was magnetic after laser irradiation. On the end there was considered the application it for 3D printing devices, water filters and four-valued non-volatile memories.

  4. Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

    Science.gov (United States)

    Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

    2017-08-01

    A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

  5. Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

    Science.gov (United States)

    Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

    2017-07-01

    As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

  6. Atomic-layer deposited IrO2 nanodots for charge-trap flash-memory devices

    International Nuclear Information System (INIS)

    Choi, Sangmoo; Cha, Young-Kwan; Seo, Bum-Seok; Park, Sangjin; Park, Ju-Hee; Shin, Sangmin; Seol, Kwang Soo; Park, Jong-Bong; Jung, Young-Soo; Park, Youngsoo; Park, Yoondong; Yoo, In-Kyeong; Choi, Suk-Ho

    2007-01-01

    Charge-trap flash- (CTF) memory structures have been fabricated by employing IrO 2 nanodots (NDs) grown by atomic-layer deposition. A band of isolated IrO 2 NDs of about 3 nm lying almost parallel to Si/SiO 2 interface is confirmed by transmission electron microscopy and x-ray photoelectron spectroscopy. The memory device with IrO 2 NDs shows much larger capacitance-voltage (C-V) hysteresis and memory window compared with the control sample without IrO 2 NDs. After annealing at 800 deg. C for 20 min, the ND device shows almost no change in the width of C-V hysteresis and the ND distribution. These results indicate that the IrO 2 NDs embedded in SiO 2 can be utilized as thermally stable, discrete charge traps, promising for metal oxide-ND-based CTF memory devices

  7. Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

    Science.gov (United States)

    Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

    2018-02-01

    In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

  8. Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

    Science.gov (United States)

    Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

    2017-10-01

    Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

  9. Electrical bistabilities and memory mechanisms of nonvolatile organic bistable devices based on exfoliated muscovite-type mica nanoparticle/poly(methylmethacrylate) nanocomposites

    Science.gov (United States)

    Lim, Won Gyu; Lee, Dea Uk; Na, Han Gil; Kim, Hyoun Woo; Kim, Tae Whan

    2018-02-01

    Organic bistable devices (OBDs) with exfoliated mica nanoparticles (NPs) embedded into an insulating poly(methylmethacrylate) (PMMA) layer were fabricated by using a spin-coating method. Current-voltage (I-V) curves for the Al/PMMA/exfoliated mica NP/PMMA/indium-tin-oxide/glass devices at 300 K showed a clockwise current hysteresis behavior due to the existence of the exfoliated muscovite-type mica NPs, which is an essential feature for bistable devices. Write-read-erase-read data showed that the OBDs had rewritable nonvolatile memories and an endurance number of ON/OFF switching for the OBDs of 102 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times larger than 1 × 104 s. The memory mechanisms of the fabricated OBDs were described by using the trapping and the tunneling processes within a PMMA active layer containing exfoliated muscovite-type mica NPs on the basis of the energy band diagram and the I-V curves.

  10. Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

    Science.gov (United States)

    Shin, Hyun Wook; Son, Jong Yeog

    2018-01-01

    We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

  11. Highly scalable 3-D NAND-NOR hybrid-type dual bit per cell flash memory devices with an additional cut-off gate

    International Nuclear Information System (INIS)

    Cho, Seongjae; Shim, Wonbo; Park, Ilhan; Kim, Yoon; Park, Byunggook

    2010-01-01

    In this work, a nonvolatile memory (NVM) device of novel structure in 3 dimensions is introduced, and its operation physics is validated. It is based on a pillar structure in which two identical storage nodes are located for dual-bit operation. The two storage nodes on neighboring pillars are controlled by using one common control gate so that the space between silicon pillars can be further reduced. For compatibility with conventional memory operations, an additional cut-off gate is constructed under the common control gate. This is considered as the ultimate form for a 3-D nonvolatile memory device based on a double-gate structure. The underlying physics is explained, and the operational schemes are validated in various aspects by using a numerical device simulation. Also, critical issues in device design for higher reliability are discussed.

  12. Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

    KAUST Repository

    Wu, S.; Luo, X.; Turner, S.; Peng, H.; Lin, W.; Ding, J.; David, A.; Wang, B.; Van, Tendeloo, G.; Wang, J.; Wu, Tao

    2013-01-01

    Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures

  13. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    Science.gov (United States)

    Di Pendina, G.; Zianbetov, E.; Beigne, E.

    2015-05-01

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  14. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    Energy Technology Data Exchange (ETDEWEB)

    Di Pendina, G., E-mail: gregory.dipendina@cea.fr, E-mail: eldar.zianbetov@cea.fr, E-mail: edith.beigne@cea.fr; Zianbetov, E., E-mail: gregory.dipendina@cea.fr, E-mail: eldar.zianbetov@cea.fr, E-mail: edith.beigne@cea.fr [Univ. Grenoble Alpes, INAC-SPINTEC, F-38000 Grenoble (France); CNRS, SPINTEC, F-38000 Grenoble (France); CEA, INAC-SPINTEC, F-38000 Grenoble (France); Beigne, E., E-mail: gregory.dipendina@cea.fr, E-mail: eldar.zianbetov@cea.fr, E-mail: edith.beigne@cea.fr [Univ. Grenoble Alpes, CEA, LETI, F-38000 Grenoble (France)

    2015-05-07

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  15. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    International Nuclear Information System (INIS)

    Di Pendina, G.; Zianbetov, E.; Beigne, E.

    2015-01-01

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes

  16. Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

    Energy Technology Data Exchange (ETDEWEB)

    Normand, P. E-mail: p.normand@imel.demokritos.gr; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M

    2004-02-01

    An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications.

  17. Nanocrystals manufacturing by ultra-low-energy ion-beam-synthesis for non-volatile memory applications

    International Nuclear Information System (INIS)

    Normand, P.; Kapetanakis, E.; Dimitrakis, P.; Skarlatos, D.; Beltsios, K.; Tsoukalas, D.; Bonafos, C.; Ben Assayag, G.; Cherkashin, N.; Claverie, A.; Berg, J.A. van den; Soncini, V.; Agarwal, A.; Ameen, M.; Perego, M.; Fanciulli, M.

    2004-01-01

    An overview of recent developments regarding the fabrication and structure of thin silicon dioxide films with embedded nanocrystals through ultra-low-energy ion-beam-synthesis (ULE-IBS) is presented. Advances in fabrication, increased understanding of structure formation processes and ways to control them allow for the fabrication of reproducible and attractive silicon-nanocrystal memory devices for a wide-range of memory applications as herein demonstrated in the case of low-voltage EEPROM-like applications

  18. Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

    Science.gov (United States)

    Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

    2016-05-01

    We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

  19. Flexible and twistable non-volatile memory cell array with all-organic one diode-one resistor architecture.

    Science.gov (United States)

    Ji, Yongsung; Zeigler, David F; Lee, Dong Su; Choi, Hyejung; Jen, Alex K-Y; Ko, Heung Cho; Kim, Tae-Wook

    2013-01-01

    Flexible organic memory devices are one of the integral components for future flexible organic electronics. However, high-density all-organic memory cell arrays on malleable substrates without cross-talk have not been demonstrated because of difficulties in their fabrication and relatively poor performances to date. Here we demonstrate the first flexible all-organic 64-bit memory cell array possessing one diode-one resistor architectures. Our all-organic one diode-one resistor cell exhibits excellent rewritable switching characteristics, even during and after harsh physical stresses. The write-read-erase-read output sequence of the cells perfectly correspond to the external pulse signal regardless of substrate deformation. The one diode-one resistor cell array is clearly addressed at the specified cells and encoded letters based on the standard ASCII character code. Our study on integrated organic memory cell arrays suggests that the all-organic one diode-one resistor cell architecture is suitable for high-density flexible organic memory applications in the future.

  20. Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

    Science.gov (United States)

    Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

    2017-12-01

    Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

  1. Capacitance characteristics of metal-oxide-semiconductor capacitors with a single layer of embedded nickel nanoparticles for the application of nonvolatile memory

    International Nuclear Information System (INIS)

    Wei, Li; Ling, Xu; Wei-Ming, Zhao; Hong-Lin, Ding; Zhong-Yuan, Ma; Jun, Xu; Kun-Ji, Chen

    2010-01-01

    This paper reports that metal-oxide-semiconductor (MOS) capacitors with a single layer of Ni nanoparticles were successfully fabricated by using electron-beam evaporation and rapid thermal annealing for application to nonvolatile memory. Experimental scanning electron microscopy images showed that Ni nanoparticles of about 5 nm in diameter were clearly embedded in the SiO 2 layer on p-type Si (100). Capacitance–voltage measurements of the MOS capacitor show large flat-band voltage shifts of 1.8 V, which indicate the presence of charge storage in the nickel nanoparticles. In addition, the charge-retention characteristics of MOS capacitors with Ni nanoparticles were investigated by using capacitance–time measurements. The results showed that there was a decay of the capacitance embedded with Ni nanoparticles for an electron charge after 10 4 s. But only a slight decay of the capacitance originating from hole charging was observed. The present results indicate that this technique is promising for the efficient formation or insertion of metal nanoparticles inside MOS structures. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  2. Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

    Science.gov (United States)

    Kim, Do-Bin; Kwon, Dae Woong; Kim, Seunghyun; Lee, Sang-Ho; Park, Byung-Gook

    2018-02-01

    To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.

  3. A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

    Science.gov (United States)

    Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

    2011-08-01

    Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

  4. Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

    Science.gov (United States)

    Swift, G.

    2002-01-01

    JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

  5. Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

    Science.gov (United States)

    Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

    2010-11-01

    When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

  6. Surface directed phase separation of semiconductor ferroelectric polymer blends and their use in non-volatile memories

    NARCIS (Netherlands)

    Breemen, A.J.J.M. van; Zaba, T.; Khikhlovskyi, V.; Michels, J.; Janssen, R.; Kemerink, M.; Gelinck, G.

    2015-01-01

    The polymer phase separation of P(VDF-TrFE):F8BT blends is studied in detail. Its morphology is key to the operation and performance of memory diodes. In this study, it is demonstrated that it is possible to direct the semiconducting domains of a phase-separating mixture of P(VDF-TrFE) and F8BT in a

  7. Modeling of SONOS Memory Cell Erase Cycle

    Science.gov (United States)

    Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

    2011-01-01

    Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

  8. Defect states and charge trapping characteristics of HfO2 films for high performance nonvolatile memory applications

    International Nuclear Information System (INIS)

    Zhang, Y.; Shao, Y. Y.; Lu, X. B.; Zeng, M.; Zhang, Z.; Gao, X. S.; Zhang, X. J.; Liu, J.-M.; Dai, J. Y.

    2014-01-01

    In this work, we present significant charge trapping memory effects of the metal-hafnium oxide-SiO 2 -Si (MHOS) structure. The devices based on 800 °C annealed HfO 2 film exhibit a large memory window of ∼5.1 V under ±10 V sweeping voltages and excellent charge retention properties with only small charge loss of ∼2.6% after more than 10 4  s retention. The outstanding memory characteristics are attributed to the high density of deep defect states in HfO 2 films. We investigated the defect states in the HfO 2 films by photoluminescence and photoluminescence excitation measurements and found that the defect states distributed in deep energy levels ranging from 1.1 eV to 2.9 eV below the conduction band. Our work provides further insights for the charge trapping mechanisms of the HfO 2 based MHOS devices.

  9. Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

    Science.gov (United States)

    Liu, Yu-Heng; Jiang, Cheng-Min; Lin, Hsiao-Yi; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan

    2017-07-01

    We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport.

  10. In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

    Science.gov (United States)

    Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

    2018-04-01

    The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

  11. Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO2 for non-volatile memory device

    International Nuclear Information System (INIS)

    Stepina, N.P.; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V.

    2008-01-01

    A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO 2 , have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO 2 /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots

  12. Evaluation of Recent Technologies of Nonvolatile RAM

    Science.gov (United States)

    Nuns, Thierry; Duzellier, Sophie; Bertrand, Jean; Hubert, Guillaume; Pouget, Vincent; Darracq, FrÉdÉric; David, Jean-Pierre; Soonckindt, Sabine

    2008-08-01

    Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices.

  13. Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

    Science.gov (United States)

    Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

    2012-11-01

    We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

  14. Effect of ZnO channel thickness on the device behaviour of nonvolatile memory thin film transistors with double-layered gate insulators of Al2O3 and ferroelectric polymer

    International Nuclear Information System (INIS)

    Yoon, Sung-Min; Yang, Shin-Hyuk; Ko Park, Sang-Hee; Jung, Soon-Won; Cho, Doo-Hee; Byun, Chun-Won; Kang, Seung-Youl; Hwang, Chi-Sun; Yu, Byoung-Gon

    2009-01-01

    Poly(vinylidene fluoride trifluoroethylene) and ZnO were employed for nonvolatile memory thin film transistors as ferroelectric gate insulator and oxide semiconducting channel layers, respectively. It was proposed that the thickness of the ZnO layer be carefully controlled for realizing the lower programming voltage, because the serially connected capacitor by the formation of a fully depleted ZnO channel had a critical effect on the off programming voltage. The fabricated memory transistor with Al/P(VDF-TrFE) (80 nm)/Al 2 O 3 (4 nm)/ZnO (5 nm) exhibits encouraging behaviour such as a memory window of 3.8 V at the gate voltage of -10 to 12 V, and 10 7 on/off ratio, and a gate leakage current of 10 -11 A.

  15. Design of SMART alarm system using main memory database

    International Nuclear Information System (INIS)

    Jang, Kue Sook; Seo, Yong Seok; Park, Keun Oak; Lee, Jong Bok; Kim, Dong Hoon

    2001-01-01

    To achieve design goal of SMART alarm system, first of all we have to decide on how to handle and manage alarm information and how to use database. So this paper analyses concepts and deficiencies of main memory database applied in real time system. And this paper sets up structure and processing principles of main memory database using nonvolatile memory such as flash memory and develops recovery strategy and process board structures using these. Therefore this paper shows design of SMART alarm system is suited functions and requirements

  16. The future of memory

    Science.gov (United States)

    Marinella, M.

    In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

  17. Multi-layered metal nanocrystals in a sol-gel spin-on-glass matrix for flash memory applications

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Meiyu Stella [Department of Chemical and Biomolecular Engineering, National University of Singapore, Block E5, 4 Engineering Drive 4, 117576 (Singapore); Globalfoundries Singapore Pte Ltd, 60 Woodlands Industrial Park D, 738406 (Singapore); Suresh, Vignesh [Department of Chemical and Biomolecular Engineering, National University of Singapore, Block E5, 4 Engineering Drive 4, 117576 (Singapore); Agency for Science, Technology and Research - A*Star, Institute of Materials Research and Engineering (IMRE), #08-03, 2 Fusionopolis Way, Innovis, 138634 (Singapore); Chan, Mei Yin [School of Materials Science and Engineering (MSE), Nanyang Technological University (NTU), 50 Nanyang Avenue, 639798 (Singapore); Ma, Yu Wei [Globalfoundries Singapore Pte Ltd, 60 Woodlands Industrial Park D, 738406 (Singapore); Lee, Pooi See [School of Materials Science and Engineering (MSE), Nanyang Technological University (NTU), 50 Nanyang Avenue, 639798 (Singapore); Krishnamoorthy, Sivashankar [Agency for Science, Technology and Research - A*Star, Institute of Materials Research and Engineering (IMRE), #08-03, 2 Fusionopolis Way, Innovis, 138634 (Singapore); Science et Analyse des Materiaux Unit (SAM), Centre de Recherche Public-Gabriel Lippmann, 41, rue du Brill, Belvaux, 4422 (Luxembourg); Srinivasan, M.P., E-mail: srinivasan.madapusi@rmit.edu.au [Department of Chemical and Biomolecular Engineering, National University of Singapore, Block E5, 4 Engineering Drive 4, 117576 (Singapore); School of Engineering, RMIT University, Building 10, Level 11, Room 14, 376-392 Swanston Street, Melbourne, Victoria, 3001 (Australia)

    2017-01-15

    A simple and low-cost process of embedding metal nanocrystals as charge storage centers within a dielectric is demonstrated to address leakage issues associated with the scaling of the tunnelling oxide in flash memories. Metal nanocrystals with high work functions (nickel, platinum and palladium) were prepared as embedded species in methyl siloxane spin-on-glass (SOG) films on silicon substrates. Sub-10 nm-sized, well-isolated, uniformly distributed, multi-layered nanocrystals with high particle densities (10{sup 11}–10{sup 12} cm{sup −2}) were formed in the films by thermal curing of the spin-coated SOG films containing the metal precursors. Capacitance-Voltage measurements performed on metal-insulator-semiconductor capacitors with the SOG films show that the presence of metal nanocrystals enhanced the memory window of the films to 2.32 V at low operating voltages of ±5 V. These SOG films demonstrated the ability to store both holes and electrons. Capacitance-time measurements show good charge retention of more than 75% after 10{sup 4} s of discharging. This work demonstrates the applicability of the low-cost in-situ sol-gel preparation in contrast to conventional methods that involve multiple and expensive processing steps. - Highlights: • Sub-10 nm sized, well-isolated, uniformly distributed nanoparticle based charge trap memories. • Preparation of multi-layer high work function metal nanocrystals at low cost. • Large memory window of 2.32 V at low operating voltages of ±5 V. • Good charge retention of more than 90% and 75% after 10{sup 3} and 10{sup 4} s of discharging respectively. • Use of a 3 nm thick tunnelling oxide in compliance with ITRS specifications.

  18. Multi-layered metal nanocrystals in a sol-gel spin-on-glass matrix for flash memory applications

    International Nuclear Information System (INIS)

    Huang, Meiyu Stella; Suresh, Vignesh; Chan, Mei Yin; Ma, Yu Wei; Lee, Pooi See; Krishnamoorthy, Sivashankar; Srinivasan, M.P.

    2017-01-01

    A simple and low-cost process of embedding metal nanocrystals as charge storage centers within a dielectric is demonstrated to address leakage issues associated with the scaling of the tunnelling oxide in flash memories. Metal nanocrystals with high work functions (nickel, platinum and palladium) were prepared as embedded species in methyl siloxane spin-on-glass (SOG) films on silicon substrates. Sub-10 nm-sized, well-isolated, uniformly distributed, multi-layered nanocrystals with high particle densities (10"1"1–10"1"2 cm"−"2) were formed in the films by thermal curing of the spin-coated SOG films containing the metal precursors. Capacitance-Voltage measurements performed on metal-insulator-semiconductor capacitors with the SOG films show that the presence of metal nanocrystals enhanced the memory window of the films to 2.32 V at low operating voltages of ±5 V. These SOG films demonstrated the ability to store both holes and electrons. Capacitance-time measurements show good charge retention of more than 75% after 10"4 s of discharging. This work demonstrates the applicability of the low-cost in-situ sol-gel preparation in contrast to conventional methods that involve multiple and expensive processing steps. - Highlights: • Sub-10 nm sized, well-isolated, uniformly distributed nanoparticle based charge trap memories. • Preparation of multi-layer high work function metal nanocrystals at low cost. • Large memory window of 2.32 V at low operating voltages of ±5 V. • Good charge retention of more than 90% and 75% after 10"3 and 10"4 s of discharging respectively. • Use of a 3 nm thick tunnelling oxide in compliance with ITRS specifications.

  19. Hot Flashes

    Science.gov (United States)

    Hot flashes Overview Hot flashes are sudden feelings of warmth, which are usually most intense over the face, neck and chest. Your skin might redden, as if you're blushing. Hot flashes can also cause sweating, and if you ...

  20. High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

    Science.gov (United States)

    Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

    2018-02-01

    In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

  1. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Science.gov (United States)

    2011-09-07

    ... Bldg. 3F, 2-1 Yaesu 2- chome Chuo-ku, Tokyo 104-0028, Japan. Elpida Memory (USA) Inc., 1175 Sonora..., Round Rock, TX 78682. Hewlett-Packard Company, 3000 Hanover Street, Palo Alto, CA 94304. Kingston...

  2. A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

    Science.gov (United States)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2016-04-01

    A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

  3. Improved charge trapping properties by embedded graphene oxide quantum-dots for flash memory application

    Science.gov (United States)

    Jia, Xinlei; Yan, Xiaobing; Wang, Hong; Yang, Tao; Zhou, Zhenyu; Zhao, Jianhui

    2018-06-01

    In this work, we have investigated two kinds of charge trapping memory devices with Pd/Al2O3/ZnO/SiO2/p-Si and Pd/Al2O3/ZnO/graphene oxide quantum-dots (GOQDs)/ZnO/SiO2/p-Si structure. Compared with the single ZnO sample, the memory window of the ZnO-GOQDs-ZnO sample reaches a larger value (more than doubled) of 2.7 V under the sweeping gate voltage ± 7 V, indicating a better charge storage capability and the significant charge trapping effects by embedding the GOQDs trapping layer. The ZnO-GOQDs-ZnO devices have better date retention properties with the high and low capacitances loss of ˜ 1.1 and ˜ 6.9%, respectively, as well as planar density of the trapped charges of 1.48 × 1012 cm- 2. It is proposed that the GOQDs play an important role in the outstanding memory characteristics due to the deep quantum potential wells and the discrete distribution of the GOQDs. The long date retention time might have resulted from the high potential barrier which suppressed both the back tunneling and the leakage current. Intercalating GOQDs in the memory device is a promising method to realize large memory window, low-power consumption and excellent retention properties.

  4. Radiation-hardened nonvolatile MNOS RAM

    International Nuclear Information System (INIS)

    Wrobel, T.F.; Dodson, W.H.; Hash, G.L.; Jones, R.V.; Nasby, R.D.; Olson, R.J.

    1983-01-01

    A radiation hardened nonvolatile MNOS RAM is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s

  5. The influence of Ti doping and annealing on Ce{sub 2}Ti{sub 2}O{sub 7} flash memory devices

    Energy Technology Data Exchange (ETDEWEB)

    Kao, Chyuan Haur [Department of Electronic Engineering, Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC (China); Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Department of Electronic Engineering, Ming Chi University of Technology, Taiwan, ROC (China); Chen, Su Zhien [Department of Electronic Engineering, Chang Gung University, No. 259, Wenhua 1st Rd., Guishan Dist., Taoyuan City 33302, Taiwan, ROC (China); Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Luo, Yang; Chiu, Wang Ting; Chiu, Shih Wei; Chen, I Chien [Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, No. 1, University Rd., Puli, Nantou Country 54561, Taiwan, ROC (China); Lin, Chan-Yu [Kidney Research Center, Department of Nephrology, Chang Gung Memorial Hospital, Chang Gung University, College of Medicine, Taoyuan, Taiwan, ROC (China); Chen, Hsiang, E-mail: hchen@ncnu.edu.tw [Department of Applied Materials and Optoelectronic Engineering, National Chi Nan University, No. 1, University Rd., Puli, Nantou Country 54561, Taiwan, ROC (China)

    2017-02-28

    Highlights: • Ce{sub 2}Ti{sub 2}O{sub 7} flash memories have been fabricated. • Material quality can be improved by annealing. • The memory performance can be enhanced by Ti doping. • Ti doping and annealing can reinforce crystallization. - Abstract: In this research, a CeO{sub 2} film with Ti doping was used as a trapping layer in metal oxide high-K-oxide-Si (MOHOS)-type memory devices. Since incorporation of Ti atoms into the film could fix dangling bonds and defects, the Ce{sub 2}Ti{sub 2}O{sub 7} trapping layer with annealing treatment could have a larger memory window and a faster programming/erasing speed. To confirm the origin, multiple material analyses indicate that annealing at an appropriate temperature and Ti doping could enhance crystallization. The Ce{sub 2}Ti{sub 2}O{sub 7}-based memory device is promising for future industrial flash memory applications.

  6. InAs quantum dots as charge storing elements for applications in flash memory devices

    Energy Technology Data Exchange (ETDEWEB)

    Islam, Sk Masiul; Biswas, Pranab [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Banerji, P., E-mail: pallab@matsc.iitkgp.ernet.in [Materials Science Centre, Indian Institute of Technology, Kharagpur 721 302 (India); Chakraborty, S. [Applied Materials Science Division, Saha Institute of Nuclear Physics, 1/AF Bidhannagar, Sector-I, Kolkata 700 064 (India)

    2015-08-15

    Graphical abstract: - Highlights: • Catalyst-free growth of InAs quantum dots was carried out on high-k ZrO{sub 2}. • Memory device with InAs quantum dots as charge storage nodes are fabricated. • Superior memory window, low leakage and reasonably good retention were observed. • Carrier transport phenomena are explained in both program and erase operations. - Abstract: InAs quantum dots (QDs) were grown by metal organic chemical vapor deposition technique to use them as charge storage nodes. Uniform QDs were formed with average diameter 5 nm and height 5–10 nm with a density of 2 × 10{sup 11} cm{sup −2}. The QDs were grown on high-k dielectric layer (ZrO{sub 2}), which was deposited onto ultra-thin GaP passivated p-GaAs (1 0 0) substrate. A charge storage device with the structure Metal/ZrO{sub 2}/InAs QDs/ZrO{sub 2}/(GaP)GaAs/Metal was fabricated. The devices containing InAs QDs exhibit superior memory window, low leakage current density along with reasonably good charge retention. A suitable electronic band diagram corresponding to programming and erasing operations was proposed to explain the operation.

  7. An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

    International Nuclear Information System (INIS)

    Jia Xiaoyun; Feng Peng; Zhang Shengguang; Wu Nanjian; Zhao Baiqin; Liu Su

    2013-01-01

    This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm 2 and 0.12 mm 2 , respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s). (semiconductor integrated circuits)

  8. MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

    Science.gov (United States)

    Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

    2014-10-01

    Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

  9. MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

    International Nuclear Information System (INIS)

    Riggert, C; Ziegler, M; Kohlstedt, H; Schroeder, D; Krautschneider, W H

    2014-01-01

    Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit. (paper)

  10. Observing the amorphous-to-crystalline phase transition in Ge{sub 2}Sb{sub 2}Te{sub 5} non-volatile memory materials from ab initio molecular-dynamics simulations

    Energy Technology Data Exchange (ETDEWEB)

    Lee, T.H.; Elliott, S.R. [Department of Chemistry, University of Cambridge, Lensfield Road, CB2 1EW Cambridge (United Kingdom)

    2012-10-15

    Phase-change memory is a promising candidate for the next generation of non-volatile memory devices. This technology utilizes reversible phase transitions between amorphous and crystalline phases of a recording material, and has been successfully used in rewritable optical data storage, revealing its feasibility. In spite of the importance of understanding the nucleation and growth processes that play a critical role in the phase transition, this understanding is still incomplete. Here, we present observations of the early stages of crystallization in Ge{sub 2}Sb{sub 2}Te{sub 5} materials through ab initio molecular-dynamics simulations. Planar structures, including fourfold rings and planes, play an important role in the formation and growth of crystalline clusters in the amorphous matrix. At the same time, vacancies facilitate crystallization by providing space at the glass-crystalline interface for atomic diffusion, which results in fast crystal growth, as observed in simulations and experiments. The microscopic mechanism of crystallization presented here may deepen our understanding of the phase transition occurring in real devices, providing an opportunity to optimize the memory performance of phase-change materials. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  11. Human sensory-evoked responses differ coincident with either "fusion-memory" or "flash-memory", as shown by stimulus repetition-rate effects

    Directory of Open Access Journals (Sweden)

    Baird Bill

    2006-02-01

    Full Text Available Abstract Background: A new method has been used to obtain human sensory evoked-responses whose time-domain waveforms have been undetectable by previous methods. These newly discovered evoked-responses have durations that exceed the time between the stimuli in a continuous stream, thus causing an overlap which, up to now, has prevented their detection. We have named them "A-waves", and added a prefix to show the sensory system from which the responses were obtained (visA-waves, audA-waves, somA-waves. Results: When A-waves were studied as a function of stimulus repetition-rate, it was found that there were systematic differences in waveshape at repetition-rates above and below the psychophysical region in which the sensation of individual stimuli fuse into a continuity. The fusion phenomena is sometimes measured by a "Critical Fusion Frequency", but for this research we can only identify a frequency-region [which we call the STZ (Sensation-Transition Zone]. Thus, the A-waves above the STZ differed from those below the STZ, as did the sensations. Study of the psychophysical differences in auditory and visual stimuli, as shown in this paper, suggest that different stimulus features are detected, and remembered, at stimulation rates above and below STZ. Conclusion: The results motivate us to speculate that: 1 Stimulus repetition-rates above the STZ generate waveforms which underlie "fusion-memory" whereas rates below the STZ show neuronal processing in which "flash-memory" occurs. 2 These two memories differ in both duration and mechanism, though they may occur in the same cell groups. 3 The differences in neuronal processing may be related to "figure" and "ground" differentiation. We conclude that A-waves provide a novel measure of neural processes that can be detected on the human scalp, and speculate that they may extend clinical applications of evoked response recordings. If A-waves also occur in animals, it is likely that A-waves will provide

  12. Human sensory-evoked responses differ coincident with either "fusion-memory" or "flash-memory", as shown by stimulus repetition-rate effects

    Science.gov (United States)

    Jewett, Don L; Hart, Toryalai; Larson-Prior, Linda J; Baird, Bill; Olson, Marram; Trumpis, Michael; Makayed, Katherine; Bavafa, Payam

    2006-01-01

    Background: A new method has been used to obtain human sensory evoked-responses whose time-domain waveforms have been undetectable by previous methods. These newly discovered evoked-responses have durations that exceed the time between the stimuli in a continuous stream, thus causing an overlap which, up to now, has prevented their detection. We have named them "A-waves", and added a prefix to show the sensory system from which the responses were obtained (visA-waves, audA-waves, somA-waves). Results: When A-waves were studied as a function of stimulus repetition-rate, it was found that there were systematic differences in waveshape at repetition-rates above and below the psychophysical region in which the sensation of individual stimuli fuse into a continuity. The fusion phenomena is sometimes measured by a "Critical Fusion Frequency", but for this research we can only identify a frequency-region [which we call the STZ (Sensation-Transition Zone)]. Thus, the A-waves above the STZ differed from those below the STZ, as did the sensations. Study of the psychophysical differences in auditory and visual stimuli, as shown in this paper, suggest that different stimulus features are detected, and remembered, at stimulation rates above and below STZ. Conclusion: The results motivate us to speculate that: 1) Stimulus repetition-rates above the STZ generate waveforms which underlie "fusion-memory" whereas rates below the STZ show neuronal processing in which "flash-memory" occurs. 2) These two memories differ in both duration and mechanism, though they may occur in the same cell groups. 3) The differences in neuronal processing may be related to "figure" and "ground" differentiation. We conclude that A-waves provide a novel measure of neural processes that can be detected on the human scalp, and speculate that they may extend clinical applications of evoked response recordings. If A-waves also occur in animals, it is likely that A-waves will provide new methods for

  13. NAFFS: network attached flash file system for cloud storage on portable consumer electronics

    Science.gov (United States)

    Han, Lin; Huang, Hao; Xie, Changsheng

    Cloud storage technology has become a research hotspot in recent years, while the existing cloud storage services are mainly designed for data storage needs with stable high speed Internet connection. Mobile Internet connections are often unstable and the speed is relatively low. These native features of mobile Internet limit the use of cloud storage in portable consumer electronics. The Network Attached Flash File System (NAFFS) presented the idea of taking the portable device built-in NAND flash memory as the front-end cache of virtualized cloud storage device. Modern portable devices with Internet connection have built-in more than 1GB NAND Flash, which is quite enough for daily data storage. The data transfer rate of NAND flash device is much higher than mobile Internet connections[1], and its non-volatile feature makes it very suitable as the cache device of Internet cloud storage on portable device, which often have unstable power supply and intermittent Internet connection. In the present work, NAFFS is evaluated with several benchmarks, and its performance is compared with traditional network attached file systems, such as NFS. Our evaluation results indicate that the NAFFS achieves an average accessing speed of 3.38MB/s, which is about 3 times faster than directly accessing cloud storage by mobile Internet connection, and offers a more stable interface than that of directly using cloud storage API. Unstable Internet connection and sudden power off condition are tolerable, and no data in cache will be lost in such situation.

  14. Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO2/Al2O3 Stacks for Use in Charge Trapping Flash Memories

    Directory of Open Access Journals (Sweden)

    Nenad Novkovski

    2018-01-01

    Full Text Available Method for characterization of electrical and trapping properties of multilayered high permittivity stacks for use in charge trapping flash memories is proposed. Application of the method to the case of multilayered HfO2/Al2O3 stacks is presented. By applying our previously developed comprehensive model for MOS structures containing high-κ dielectrics on the J-V characteristics measured in the voltage range without marked degradation and charge trapping (from −3 V to +3 V, several parameters of the structure connected to the interfacial layer and the conduction mechanisms have been extracted. We found that the above analysis gives precise information on the main characteristics and the quality of the injection layer. C-V characteristics of stressed (with write and erase pulses structures recorded in a limited range of voltages between −1 V and +1 V (where neither significant charge trapping nor visible degradation of the structures is expected to occur were used in order to provide measures of the effect of stresses with no influence of the measurement process. Both trapped charge and the distribution of interface states have been determined using modified Terman method for fresh structures and for structures stressed with write and erase cycles. The proposed method allows determination of charge trapping and interface state with high resolution, promising a precise characterization of multilayered high permittivity stacks for use in charge trapping flash memories.

  15. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

    Science.gov (United States)

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-06-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

  16. Formation of the distributed NiSiGe nanocrystals nonvolatile memory formed by rapidly annealing in N2 and O2 ambient

    International Nuclear Information System (INIS)

    Hu, Chih-Wei; Chang, Ting-Chang; Tu, Chun-Hao; Chiang, Cheng-Neng; Lin, Chao-Cheng; Chen, Min-Chen; Chang, Chun-Yen; Sze, Simon M.; Tseng, Tseung-Yuen

    2010-01-01

    In this work, electrical characteristics of the Ge-incorporated Nickel silicide (NiSiGe) nanocrystals memory device formed by the rapidly thermal annealing in N 2 and O 2 ambient have been studied. The trapping layer was deposited by co-sputtering the NiSi 2 and Ge, simultaneously. Transmission electron microscope results indicate that the NiSiGe nanocrystals were formed obviously in both the samples. The memory devices show obvious charge-storage ability under capacitance-voltage measurement. However, it is found that the NiSiGe nanocrystals device formed by annealing in N 2 ambient has smaller memory window and better retention characteristics than in O 2 ambient. Then, related material analyses were used to confirm that the oxidized Ge elements affect the charge-storage sites and the electrical performance of the NCs memory.

  17. Flash grundkursus

    DEFF Research Database (Denmark)

    Jensen, Henrik

    2008-01-01

    Flash er et programmeringssprog  og kan som sådant ikke noget i sig selv. Kursets mål er, at give den studerende et grundlæggende kendskab til Flash, så det kan bruges til præsentationer på skærm og til produktion af hjemmesider. På kurset arbejdes der med billede, grafik, lyd, video og interakti...

  18. Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

    Science.gov (United States)

    MacLeod, Todd C.; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

    2011-01-01

    NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

  19. Nanoscale observations of the operational failure for phase-change-type nonvolatile memory devices using Ge2Sb2Te5 chalcogenide thin films

    International Nuclear Information System (INIS)

    Yoon, Sung-Min; Choi, Kyu-Jeong; Lee, Nam-Yeal; Lee, Seung-Yun; Park, Young-Sam; Yu, Byoung-Gon

    2007-01-01

    In this study, a phase-change memory device was fabricated and the origin of device failure mode was examined using transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDS). Ge 2 Sb 2 Te 5 (GST) was used as the active phase-change material in the memory device and the active pore size was designed to be 0.5 μm. After the programming signals of more than 2x10 6 cycles were repeatedly applied to the device, the high-resistance memory state (reset) could not be rewritten and the cell resistance was fixed at the low-resistance state (set). Based on TEM and EDS studies, Sb excess and Ge deficiency in the device operating region had a strong effect on device reliability, especially under endurance-demanding conditions. An abnormal segregation and oxidation of Ge also was observed in the region between the device operating and inactive peripheral regions. To guarantee an data endurability of more than 1x10 10 cycles of PRAM, it is very important to develop phase-change materials with more stable compositions and to reduce the current required for programming

  20. Pluto's Nonvolatile Chemical Compounds

    Science.gov (United States)

    Grundy, William M.; Binzel, Richard; Cook, Jason C.; Cruikshank, Dale P.; Dalle Ore, Cristina M.; Earle, Alissa M.; Ennico, Kimberly; Jennings, Donald; Howett, Carly; Kaiser, Ralf-Ingo; Linscott, Ivan; Lunsford, A. W.; Olkin, Catherine B.; Parker, Alex Harrison; Parker, Joel Wm.; Philippe, Sylvain; Protopapa, Silvia; Quirico, Eric; Reuter, D. C.; Schmitt, Bernard; Singer, Kelsi N.; Spencer, John R.; Stansberry, John A.; Stern, S. Alan; Tsang, Constantine; Verbiscer, Anne J.; Weaver, Harold A.; Weigle, G. E.; Young, Leslie

    2016-10-01

    Despite the migration of Pluto's volatile ices (N2, CO, and CH4) around the surface on seasonal timescales, the planet's non-volatile materials are not completely hidden from view. They occur in a variety of provinces formed over a wide range of timescales, including rugged mountains and chasms, the floors of mid-latitude craters, and an equatorial belt of especially dark and reddish material typified by the informally named Cthulhu Regio. NASA's New Horizons probe observed several of these regions at spatial resolutions as fine as 3 km/pixel with its LEISA imaging spectrometer, covering wavelengths from 1.25 to 2.5 microns. Various compounds that are much lighter than the tholin-like macromolecules responsible for the reddish coloration, but that are not volatile at Pluto surface temperatures such as methanol (CH3OH) and ethane (C2H6) have characteristic absorption bands within LEISA's wavelength range. This presentation will describe their geographic distributions and attempt to constrain their origins. Possibilities include an inheritance from Pluto's primordial composition (the likely source of H2O ice seen on Pluto's surface) or ongoing production from volatile precursors through photochemistry in Pluto's atmosphere or through radiolysis on Pluto's surface. New laboratory data inform the analysis.This work was supported by NASA's New Horizons project.

  1. Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory

    International Nuclear Information System (INIS)

    Biswas, Ayan K.; Bandyopadhyay, Supriyo; Atulasimha, Jayasimha

    2013-01-01

    We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle

  2. Pulsed ion-beam assisted deposition of Ge nanocrystals on SiO{sub 2} for non-volatile memory device

    Energy Technology Data Exchange (ETDEWEB)

    Stepina, N.P. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)], E-mail: nstepina@mail.ru; Dvurechenskii, A.V.; Armbrister, V.A.; Kirienko, V.V.; Novikov, P.L.; Kesler, V.G.; Gutakovskii, A.K.; Smagina, Z.V.; Spesivtzev, E.V. [Institute of Semiconductor Physics, Lavrenteva 13, 630090 Novosibirsk (Russian Federation)

    2008-11-03

    A floating gate memory structure, utilizing Ge nanocrystals (NCs) deposited on tunnel SiO{sub 2}, have been fabricated using pulsed low energy ion-beam induced molecular-beam deposition (MBD) in ultra-high vacuum. The ion-beam action is shown to stimulate the nucleation of Ge NCs when being applied after thin Ge layer deposition. Growth conditions for independent change of NCs size and array density were established allowing to optimize the structure parameters required for memory device. Activation energy E = 0.25 eV was determined from the temperature dependence of NCs array density. Monte Carlo simulation has shown that the process, determining NCs array density, is the surface diffusion. Embedding of the crystalline Ge dots into silicon oxide was carried out by selective oxidation of Si(100)/SiO{sub 2} /Ge(NCs)/poly-Si structure. MOS-capacitor obtained after oxidation showed a hysteresis in its C-V curves attributed to charge retention in the Ge dots.

  3. Improvement of multi-level resistive switching characteristics in solution-processed AlO x -based non-volatile resistive memory using microwave irradiation

    Science.gov (United States)

    Kim, Seung-Tae; Cho, Won-Ju

    2018-01-01

    We fabricated a resistive random access memory (ReRAM) device on a Ti/AlO x /Pt structure with solution-processed AlO x switching layer using microwave irradiation (MWI), and demonstrated multi-level cell (MLC) operation. To investigate the effect of MWI power on the MLC characteristics, post-deposition annealing was performed at 600-3000 W after AlO x switching layer deposition, and the MLC operation was compared with as-deposited (as-dep) and conventional thermally annealing (CTA) treated devices. All solution-processed AlO x -based ReRAM devices exhibited bipolar resistive switching (BRS) behavior. We found that these devices have four-resistance states (2 bits) of MLC operation according to the modulation of the high-resistance state (HRSs) through reset voltage control. Particularly, compared to the as-dep and CTA ReRAM devices, the MWI-treated ReRAM devices showed a significant increase in the memory window and stable endurance for multi-level operation. Moreover, as the MWI power increased, excellent MLC characteristics were exhibited because the resistance ratio between each resistance state was increased. In addition, it exhibited reliable retention characteristics without deterioration at 25 °C and 85 °C for 10 000 s. Finally, the relationship between the chemical characteristics of the solution-processed AlO x switching layer and BRS-based multi-level operation according to the annealing method and MWI power was investigated using x-ray photoelectron spectroscopy.

  4. Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

    Science.gov (United States)

    Briggs, Benjamin D.

    The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

  5. Phase change materials in non-volatile storage

    OpenAIRE

    Ielmini, Daniele; Lacaita, Andrea L.

    2011-01-01

    After revolutionizing the technology of optical data storage, phase change materials are being adopted in non-volatile semiconductor memories. Their success in electronic storage is mostly due to the unique properties of the amorphous state where carrier transport phenomena and thermally-induced phase change cooperate to enable high-speed, low-voltage operation and stable data retention possible within the same material. This paper reviews the key physical properties that make this phase so s...

  6. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

    Science.gov (United States)

    Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

    2018-09-01

    In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

  7. Nonvolatile flexible organic bistable devices fabricated utilizing CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole polymer layer

    International Nuclear Information System (INIS)

    Son, Dong-Ick; Kim, Ji-Hwan; Park, Dong-Hee; Choi, Won Kook; Li, Fushan; Ham, Jung Hun; Kim, Tae Whan

    2008-01-01

    The bistable effects of CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole (PVK) polymer layer by using flexible poly-vinylidene difluoride (PVDF) and polyethylene terephthalate (PET) substrates were investigated. Transmission electron microscopy (TEM) images revealed that CdSe/ZnS nanoparticles were formed inside the PVK polymer layer. Current-voltage (I-V) measurement on the Al/[CdSe/ZnS nanoparticles+ PVK]/ITO/PVDF and Al/[CdSe/ZnS nanoparticles+ PVK ]/ITO/PET structures at 300 K showed a nonvolatile electrical bistability behavior with a flat-band voltage shift due to the existence of the CdSe/ZnS nanoparticles, indicative of trapping, storing and emission of charges in the electronic states of the CdSe nanoparticles. A bistable behavior for the fabricated organic bistable device (OBD) structures is described on the basis of the I-V results. These results indicate that OBDs fabricated by embedding inorganic CdSe/ZnS nanoparticles in a conducting polymer matrix on flexible substrates are prospects for potential applications in flexible nonvolatile flash memory devices

  8. Embedded 3D Nonvolatile Memory, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Integrated circuits in NASA spacecraft and vehicle electronics must operate over large temperature extremes and mitigate radiation effects that can result in upset...

  9. Flash evaporator

    OpenAIRE

    1997-01-01

    A device and method for flash evaporating a reagent includes an evaporation chamber that houses a dome on which evaporation occurs. The dome is solid and of high thermal conductivity and mass, and may be heated to a temperature sufficient to vaporize a specific reagent. The reagent is supplied from an external source to the dome through a nozzle, and may be supplied as a continuous stream, as a shower, and as discrete drops. A carrier gas may be introduced into the evaporation chamber and cre...

  10. Model-assisted template extraction SRAF application to contact holes patterns in high-end flash memory device fabrication

    Science.gov (United States)

    Seoud, Ahmed; Kim, Juhwan; Ma, Yuansheng; Jayaram, Srividya; Hong, Le; Chae, Gyu-Yeol; Lee, Jeong-Woo; Park, Dae-Jin; Yune, Hyoung-Soon; Oh, Se-Young; Park, Chan-Ha

    2018-03-01

    Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.

  11. Multistate nonvolatile straintronics controlled by a lateral electric field

    International Nuclear Information System (INIS)

    Iurchuk, V; Doudin, B; Kundys, B

    2014-01-01

    We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications. (fast track communication)

  12. Multistate nonvolatile straintronics controlled by a lateral electric field.

    Science.gov (United States)

    Iurchuk, V; Doudin, B; Kundys, B

    2014-07-23

    We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications.

  13. Combined mask and illumination scheme optimization for robust contact patterning on 45nm technology node flash memory devices

    Science.gov (United States)

    Vaglio Pret, Alessandro; Capetti, Gianfranco; Bollin, Maddalena; Cotti, Gina; De Simone, Danilo; Cantù, Pietro; Vaccaro, Alessandro; Soma, Laura

    2008-03-01

    Immersion Lithography is the most important technique for extending optical lithography's capabilities and meeting the requirements of Semiconductor Roadmap. The introduction of immersion tools has recently allowed the development of 45nm technology node in single exposure. Nevertheless the usage of hyper-high NA scanners (NA > 1), some levels still remain very critical to be imaged with sufficient process performances. For memory devices, contact mask is for sure the most challenging layer. Aim of this paper is to present the lithographic assessment of 193nm contact holes process, with k I value of ~0.30 using NA 1.20 immersion lithography (minimum pitch is 100nm). Different issues will be reported, related to mask choices (Binary or Attenuated Phase Shift) and illuminator configurations. First phase of the work will be dedicated to a preliminary experimental screening on a simple test case in order to reduce the variables in the following optimization sections. Based on this analysis we will discard X-Y symmetrical illuminators (Annular, C-Quad) due to poor contrast. Second phase will be dedicated to a full simulation assessment. Different illuminators will be compared, with both mask type and several mask biases. From this study, we will identify some general trends of lithography performances that can be used for the fine tuning of the RET settings. The last phase of the work will be dedicated to find the sensitivity trends for one of the analyzed illuminators. In particular we study the effect of Numerical Aperture, mask bias in both X and Y direction and poles sigma ring-width and centre.

  14. Transparent Memory For Harsh Electronics

    KAUST Repository

    Ho, C. H.; Duran Retamal, Jose Ramon; Yang, P. K.; Lee, C. P.; Tsai, M. L.; Kang, C. F.; He, Jr-Hau

    2017-01-01

    As a new class of non-volatile memory, resistive random access memory (RRAM) offers not only superior electronic characteristics, but also advanced functionalities, such as transparency and radiation hardness. However, the environmental tolerance

  15. Electric-field-controlled interface dipole modulation for Si-based memory devices.

    Science.gov (United States)

    Miyata, Noriyuki

    2018-05-31

    Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

  16. DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

    Directory of Open Access Journals (Sweden)

    Sparsh Mittal

    2017-09-01

    Full Text Available To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM, spin transfer torque RAM (STT-RAM, phase change RAM (PCM and embedded DRAM (eDRAM and 2D memories designed using spin orbit torque RAM (SOT-RAM, domain wall memory (DWM and Flash memory. In addition to single-level cell (SLC designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparshmittal/destinyv2.

  17. Towards Terabit Memories

    Science.gov (United States)

    Hoefflinger, Bernd

    Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet

  18. Effect of AlN layer on the bipolar resistive switching behavior in TiN thin film based ReRAM device for non-volatile memory application

    Science.gov (United States)

    Prakash, Ravi; Kaur, Davinder

    2018-05-01

    The effect of an additional AlN layer in the Cu/TiN/AlN/Pt stack configuration deposited using sputtering has been investigated. The Cu/TiN/AlN/Pt device shows a tristate resistive switching. Multilevel switching is facilitated by ionic and metallic filament formation, and the nature of the filaments formed is confirmed by performing a resistance vs. temperature measurement. Ohmic behaviour and trap controlled space charge limited current (SCLC) conduction mechanisms are confirmed as dominant conduction mechanism at low resistance state (LRS) and high resistance state (HRS). High resistance ratio (102) corresponding to HRS and LRS, good write/erase endurance (105) and non-volatile long retention (105s) are also observed. Higher thermal conductivity of the AlN layer is the main reasons for the enhancement of resistive switching performance in Cu/TiN/AlN/Pt cell. The above result suggests the feasibility of Cu/TiN/AlN/Pt devices for multilevel nonvolatile ReRAM application.

  19. New memory devices based on the proton transfer process

    International Nuclear Information System (INIS)

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing  information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices. (paper)

  20. New memory devices based on the proton transfer process

    Science.gov (United States)

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices.

  1. Flash-Aware Page Replacement Algorithm

    Directory of Open Access Journals (Sweden)

    Guangxia Xu

    2014-01-01

    Full Text Available Due to the limited main memory resource of consumer electronics equipped with NAND flash memory as storage device, an efficient page replacement algorithm called FAPRA is proposed for NAND flash memory in the light of its inherent characteristics. FAPRA introduces an efficient victim page selection scheme taking into account the benefit-to-cost ratio for evicting each victim page candidate and the combined recency and frequency value, as well as the erase count of the block to which each page belongs. Since the dirty victim page often contains clean data that exist in both the main memory and the NAND flash memory based storage device, FAPRA only writes the dirty data within the victim page back to the NAND flash memory based storage device in order to reduce the redundant write operations. We conduct a series of trace-driven simulations and experimental results show that our proposed FAPRA algorithm outperforms the state-of-the-art algorithms in terms of page hit ratio, the number of write operations, runtime, and the degree of wear leveling.

  2. Performance enhancement in p-channel charge-trapping flash memory devices with Si/Ge super-lattice channel and band-to-band tunneling induced hot-electron injection

    International Nuclear Information System (INIS)

    Liu, Li-Jung; Chang-Liao, Kuei-Shu; Jian, Yi-Chuen; Wang, Tien-Ko; Tsai, Ming-Jinn

    2013-01-01

    P-channel charge-trapping flash memory devices with Si, SiGe, and Si/Ge super-lattice channel are investigated in this work. A Si/Ge super-lattice structure with extremely low roughness and good crystal structure is obtained by precisely controlling the epitaxy thickness of Ge layer. Both programming and erasing (P/E) speeds are significantly improved by employing this Si/Ge super-lattice channel. Moreover, satisfactory retention and excellent endurance characteristics up to 10 6 P/E cycles with 3.8 V memory window show that the degradation on reliability properties is negligible when super-lattice channel is introduced. - Highlights: ► A super-lattice structure is proposed to introduce more Ge content into channel. ► Super-lattice structure possesses low roughness and good crystal structure. ► P-channel flash devices with Si, SiGe, and super-lattice channel are investigated. ► Programming/erasing speeds are significantly improved. ► Reliability properties can be kept for device with super-lattice channel

  3. DIRCM FLASH Flight Tests

    National Research Council Canada - National Science Library

    Molocher, Bernhard; Kaltenecker, Anton; Thum-Jaeger, Andrea; Regensburger, Martin; Formery, Martin

    2005-01-01

    .... FLASH operation is as follows: After handover following an alarm from the missile warning system FLASH enters autonomous passive tracking mode for tracking a missiles and sending a laser beam onto the missile...

  4. Flash Platform Examination

    Science.gov (United States)

    2011-03-01

    than would be performed in software”[108]. Uro Tinic, one of the Flash player’s engineers, further clarifies exactly what Flash player 10 hardware...www.adobe.com/products/flashplayer/features/ (Access date: 28 Sep 2009). [109] Uro , T. What Does GPU Acceleration Mean? (online), http...133] Shorten, A. (2009), Design to Development: Flash Catalyst to Flash Builder, In Proceedings of Adobe Max 2009, Los Angeles, CA. 142 DRDC

  5. Simple flash evaporator for making thin films of compounds

    Energy Technology Data Exchange (ETDEWEB)

    Hemanadhan, M.; Bapanayya, Ch.; Agarwal, S. C. [Department of Physics, Indian Institute of Technology, Kanpur 208016 (India)

    2010-07-15

    A simple and compact arrangement for flash evaporation is described. It uses a cell phone vibrator for powder dispensing that can be incorporated into a vacuum deposition chamber without any major alterations. The performance of the flash evaporation system is checked by making thin films of the optical memory chalcogenide glass Ge{sub 2}Sb{sub 2}Te{sub 5} (GST). Energy dispersive x-ray analysis shows that the flash evaporation preserves the stoichiometry in thin films.

  6. Coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3/In memristive devices

    International Nuclear Information System (INIS)

    Yang, M; Bao, D H; Li, S W

    2013-01-01

    Memristive devices are triggering innovations in the fields of nonvolatile memory, digital logic, analogue circuits, neuromorphic engineering, and so on. Creating new memristive devices with unique characteristics would be significant for these emergent applications. Here we report the coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO 3 (NSTO)/In memristive devices. The Pt/NSTO interface contributes a nonvolatile resistive switching behaviour, whereas the NSTO/In interface displays a volatile hysteresis loop. Combining the two interfaces in the Pt/NSTO/In devices leads to the unique coexistence of nonvolatility and volatility. The results imply more opportunities to invent new memristive devices by engineering both interfaces in metal/insulator/metal structures. (paper)

  7. Resistive Memory Devices for Radiation Resistant Non-Volatile Memory

    Data.gov (United States)

    National Aeronautics and Space Administration — Ionizing radiation in space can damage electronic equipment, corrupting data and even disabling computers. Radiation resistant (rad hard) strategies must be employed...

  8. Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

    Science.gov (United States)

    Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

    2017-11-01

    A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

  9. Pro Android Flash

    CERN Document Server

    Chin, Stephen; Campesato, Oswald

    2011-01-01

    Did you know you can take your Flash skills beyond the browser, allowing you to make apps for Android, iOS and the BlackBerry Tablet OS? Build dynamic apps today starting with the easy-to-use Android smartphones and tablets. Then, take your app to other platforms without writing native code. Pro Android Flash is the definitive guide to building Flash and other rich Internet applications (RIAs) on the Android platform. It covers the most popular RIA frameworks for Android developers - Flash and Flex - and shows how to build rich, immersive user experiences on both Android smartphones and tablet

  10. Fabrication and characterization of metal-ferroelectric (PbZr0.6Ti0.4O3)-insulator (La2O3)-semiconductor capacitors for nonvolatile memory applications

    Science.gov (United States)

    Juan, Trevor Pi-Chun; Lin, Cheng-Li; Shih, Wen-Chieh; Yang, Chin-Chieh; Lee, Joseph Ya-Min; Shye, Der-Chi; Lu, Jong-Hong

    2009-03-01

    Metal-ferroelectric-insulator-semiconductor thin-film capacitors with Pb(Zr0.6,Ti0.4)O3 (PZT) ferroelectric layer and high-k lanthanum oxide (La2O3) insulator layer were fabricated. The outdiffusion of atoms between La2O3 and silicon was examined by the secondary-ion-mass spectroscopy. The size of memory window as a function of PZT annealing temperature was discussed. The maximum memory window saturated to 0.7 V, which is close to the theoretical memory window ΔW ≈2dfEc≈0.8 V with higher annealing temperatures above 700 °C. The memory window starts to decrease due to charge injection when the sweep voltage is higher than 5 V at 600 °C-annealed samples. The C-V flatband voltage shift (ΔVFB) as a function of charge injection was characterized in this work. An energy band diagram of the Al/PZT//La2O3/p-Si system was proposed to explain the memory window and the flatband voltage shift.

  11. Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

    Science.gov (United States)

    Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

    2013-07-01

    We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

  12. Environmental Effects on Data Retention in Flash Cells

    Science.gov (United States)

    Katz, Rich; Flowers, David; Bergevin, Keith

    2017-01-01

    Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

  13. Non-volatile MOS RAM cell with capacitor-isolated nodes that are radiation accessible for rendering a non-permanent programmed information in the cell of a non-volatile one

    NARCIS (Netherlands)

    Widdershoven, Franciscus P.; Annema, Anne J.; Storms, Maurits M.N.; Pelgrom, Marcellinus J.M.; Pelgrom, Marcel J M

    2001-01-01

    A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of

  14. Flash-Type Discrimination

    Science.gov (United States)

    Koshak, William J.

    2010-01-01

    This viewgraph presentation describes the significant progress made in the flash-type discrimination algorithm development. The contents include: 1) Highlights of Progress for GLM-R3 Flash-Type discrimination Algorithm Development; 2) Maximum Group Area (MGA) Data; 3) Retrieval Errors from Simulations; and 4) Preliminary Global-scale Retrieval.

  15. Investigation on amorphous InGaZnO based resistive switching memory with low-power, high-speed, high reliability

    Energy Technology Data Exchange (ETDEWEB)

    Fan, Yang-Shun [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China); Liu, Po-Tsun, E-mail: ptliu@mail.nctu.edu.tw [Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China); Hsu, Ching-Hui [Department of Photonics and Display Institute, National Chiao Tung University, Hsinchu 30010, Taiwan, ROC (China)

    2013-12-31

    Recently, non-volatile memory (NVM) has been widely used in electronic devices. Nowadays, the prevailing NVM is Flash memory. However, it is generally believed that the conventional Flash memory will approach its scaling limit within about a decade. The resistive random access memory (RRAM) is emerging as one of the potential candidates for future memory replacement because of its high storage density, low power consumption as well as simple structure. The purpose of this work is to develop a reliable a-InGaZnO based resistive switching memory. We investigate the resistive switching characteristics of TiN/Ti/IGZO/Pt structure and TiN/IGZO/Pt structure. The device with TiN/Ti/IGZO/Pt structure exhibits stable bipolar resistive switching. The impact of inserting a Ti interlayer is studied by material analyses. The device shows excellent resistive switching properties. For example, the DC sweep endurance can achieve over 1000 times; and the pulse induced switching cycles can reach at least 10,000 times. Furthermore, the impact of different sputtering ambience, the variable temperature measurement, and the conduction mechanisms are also investigated. According to our experiments, we propose a model to explain the resistive switching phenomenon observed in our devices.

  16. Nanoscale memory devices

    International Nuclear Information System (INIS)

    Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M

    2010-01-01

    This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO 2 . (topical review)

  17. Floods and Flash Flooding

    Science.gov (United States)

    Floods and flash flooding Now is the time to determine your area’s flood risk. If you are not sure whether you ... If you are in a floodplain, consider buying flood insurance. Do not drive around barricades. If your ...

  18. Strain-controlled nonvolatile magnetization switching

    Science.gov (United States)

    Geprägs, S.; Brandlmaier, A.; Brandt, M. S.; Gross, R.; Goennenwein, S. T. B.

    2014-11-01

    We investigate different approaches towards a nonvolatile switching of the remanent magnetization in single-crystalline ferromagnets at room temperature via elastic strain using ferromagnetic thin film/piezoelectric actuator hybrids. The piezoelectric actuator induces a voltage-controllable strain along different crystalline directions of the ferromagnetic thin film, resulting in modifications of its magnetization by converse magnetoelastic effects. We quantify the magnetization changes in the hybrids via ferromagnetic resonance spectroscopy and superconducting quantum interference device magnetometry. These measurements demonstrate a significant strain-induced change of the magnetization, limited by an inefficient strain transfer and domain formation in the particular system studied. To overcome these obstacles, we address practicable engineering concepts and use a model to demonstrate that a strain-controlled, nonvolatile magnetization switching should be possible in appropriately engineered ferromagnetic/piezoelectric actuator hybrids.

  19. Immersion and dry lithography monitoring for flash memories (after develop inspection and photo cell monitor) using a darkfield imaging inspector with advanced binning technology

    Science.gov (United States)

    Parisi, P.; Mani, A.; Perry-Sullivan, C.; Kopp, J.; Simpson, G.; Renis, M.; Padovani, M.; Severgnini, C.; Piacentini, P.; Piazza, P.; Beccalli, A.

    2009-12-01

    After-develop inspection (ADI) and photo-cell monitoring (PM) are part of a comprehensive lithography process monitoring strategy. Capturing defects of interest (DOI) in the lithography cell rather than at later process steps shortens the cycle time and allows for wafer re-work, reducing overall cost and improving yield. Low contrast DOI and multiple noise sources make litho inspection challenging. Broadband brightfield inspectors provide the highest sensitivity to litho DOI and are traditionally used for ADI and PM. However, a darkfield imaging inspector has shown sufficient sensitivity to litho DOI, providing a high-throughput option for litho defect monitoring. On the darkfield imaging inspector, a very high sensitivity inspection is used in conjunction with advanced defect binning to detect pattern issues and other DOI and minimize nuisance defects. For ADI, this darkfield inspection methodology enables the separation and tracking of 'color variation' defects that correlate directly to CD variations allowing a high-sampling monitor for focus excursions, thereby reducing scanner re-qualification time. For PM, the darkfield imaging inspector provides sensitivity to critical immersion litho defects at a lower cost-of-ownership. This paper describes litho monitoring methodologies developed and implemented for flash devices for 65nm production and 45nm development using the darkfield imaging inspector.

  20. Superior PSZ-SOD Gap-Fill Process Integration Using Ultra-Low Dispensation Amount in STI for 28 nm NAND Flash Memory and Beyond

    Directory of Open Access Journals (Sweden)

    Chun Chi Lai

    2015-01-01

    Full Text Available The gap-fill performance and process of perhydropolysilazane-based inorganic spin-on dielectric (PSZ-SOD film in shallow trench isolation (STI with the ultra-low dispensation amount of PSZ-SOD solution have been investigated in this study. A PSZ-SOD film process includes liner deposition, PSZ-SOD coating, and furnace curing. For liner deposition, hydrophilic property is required to improve the contact angle and gap-fill capability of PSZ-SOD coating. Prior to PSZ-SOD coating, the additional treatment on liner surface is beneficial for the fluidity of PSZ-SOD solution. The superior film thickness uniformity and gap-fill performance of PSZ-SOD film are achieved due to the improved fluidity of PSZ-SOD solution. Following that up, the low dispensation rate of PSZ-SOD solution leads to more PSZ-SOD filling in the trenches. After PSZ-SOD coating, high thermal curing process efficiently promotes PSZ-SOD film conversion into silicon oxide. Adequate conversion from PSZ-SOD into silicon oxide further increases the etching resistance inside the trenches. Integrating the above sequence of optimized factors, void-free gap-fill and well-controlled STI recess uniformity are achieved even when the PSZ-SOD solution dispensation volume is reduced 3 to 6 times compared with conventional condition for the 28 nm node NAND flash and beyond.

  1. Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

    Science.gov (United States)

    MacLeod, Todd; Ho, Fat D.

    2012-01-01

    The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere

  2. Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

    Science.gov (United States)

    Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

    2017-08-01

    In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

  3. Nonvolatile resistive switching in Pt/laALO3/srTiO3 heterostructures

    KAUST Repository

    Wu, S.

    2013-12-12

    Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO3/SrTiO3 heterostructures, where the conducting layer near the LaAlO3/SrTiO3 interface serves as the "unconventional"bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO3/SrTiO3 interface and the creation of defect-induced gap states within the ultrathin LaAlO3 layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

  4. Nonvolatile Resistive Switching in Pt/LaAlO_{3}/SrTiO_{3} Heterostructures

    Directory of Open Access Journals (Sweden)

    Shuxiang Wu

    2013-12-01

    Full Text Available Resistive switching heterojunctions, which are promising for nonvolatile memory applications, usually share a capacitorlike metal-oxide-metal configuration. Here, we report on the nonvolatile resistive switching in Pt/LaAlO_{3}/SrTiO_{3} heterostructures, where the conducting layer near the LaAlO_{3}/SrTiO_{3} interface serves as the “unconventional” bottom electrode although both oxides are band insulators. Interestingly, the switching between low-resistance and high-resistance states is accompanied by reversible transitions between tunneling and Ohmic characteristics in the current transport perpendicular to the planes of the heterojunctions. We propose that the observed resistive switching is likely caused by the electric-field-induced drift of charged oxygen vacancies across the LaAlO_{3}/SrTiO_{3} interface and the creation of defect-induced gap states within the ultrathin LaAlO_{3} layer. These metal-oxide-oxide heterojunctions with atomically smooth interfaces and defect-controlled transport provide a platform for the development of nonvolatile oxide nanoelectronics that integrate logic and memory devices.

  5. Influence of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon capacitors for flash memories

    International Nuclear Information System (INIS)

    Kim, Hee Dong; An, Ho-Myoung; Kim, Kyoung Chan; Seo, Yu Jeong; Kim, Tae Geun

    2008-01-01

    We report the effect of post-annealing on the electrical properties of metal/oxide/silicon nitride/oxide/silicon (MONOS) capacitors. Four samples, namely as-deposited and annealed at 750, 850 and 950 °C for 30 s in nitrogen ambient by a rapid thermal process, were prepared and characterized for comparison. The best performance with the largest memory window of 4.4 V and the fastest program speed of 10 ms was observed for the sample annealed at 850 °C. In addition, the highest traps density of 6.84 × 10 18 cm −3 was observed with ideal trap distributions for the same sample by capacitance–voltage (C–V) measurement. These results indicate that the memory traps in the ONO structure can be engineered by post-annealing to improve the electrical properties of the MONOS device

  6. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  7. Memory

    Science.gov (United States)

    ... it has to decide what is worth remembering. Memory is the process of storing and then remembering this information. There are different types of memory. Short-term memory stores information for a few ...

  8. 1T1R Nonvolatile Memory with Al/TiO2/Au and Sol-Gel-Processed Insulator for Barium Zirconate Nickelate Gate in Pentacene Thin Film Transistor

    Directory of Open Access Journals (Sweden)

    Ke-Jing Lee

    2017-12-01

    Full Text Available A one-transistor and one-resistor (1T1R architecture with a resistive random access memory (RRAM cell connected to an organic thin-film transistor (OTFT device is successfully demonstrated to avoid the cross-talk issues of only one RRAM cell. The OTFT device, which uses barium zirconate nickelate (BZN as a dielectric layer, exhibits favorable electrical properties, such as a high field-effect mobility of 2.5 cm2/Vs, low threshold voltage of −2.8 V, and low leakage current of 10−12 A, for a driver in the 1T1R operation scheme. The 1T1R architecture with a TiO2-based RRAM cell connected with a BZN OTFT device indicates a low operation current (10 μA and reliable data retention (over ten years. This favorable performance of the 1T1R device can be attributed to the additional barrier heights introduced by using Ni (II acetylacetone as a substitute for acetylacetone, and the relatively low leakage current of a BZN dielectric layer. The proposed 1T1R device with low leakage current OTFT and excellent uniform resistance distribution of RRAM exhibits a good potential for use in practical low-power electronic applications.

  9. Modélisation de Fautes et Test des Mémoires Flash

    OpenAIRE

    Ginez , Olivier

    2007-01-01

    Flash memories more and more occurs in complex integrated circuits designed for portable electronic devices and dominate the area of such circuits. The lack of defects within these memories is therefore one the key elements of the production yield for manufacturers of these types of applications. However, the high integration density and the complexity of the fabrication process make these Flash memories more and more prone to manufacturing defects. To exhibit the failures that affect the fun...

  10. Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

    Science.gov (United States)

    Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

    2017-12-01

    Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

  11. Digital Device Architecture and the Safe Use of Flash Devices in Munitions

    Science.gov (United States)

    Katz, Richard B.; Flowers, David; Bergevin, Keith

    2017-01-01

    Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

  12. Interactions of numerical and temporal stimulus characteristics on the control of response location by brief flashes of light.

    Science.gov (United States)

    Fetterman, J Gregor; Killeen, P Richard

    2011-09-01

    Pigeons pecked on three keys, responses to one of which could be reinforced after 3 flashes of the houselight, to a second key after 6, and to a third key after 12. The flashes were arranged according to variable-interval schedules. Response allocation among the keys was a function of the number of flashes. When flashes were omitted, transitions occurred very late. Increasing flash duration produced a leftward shift in the transitions along a number axis. Increasing reinforcement probability produced a leftward shift, and decreasing reinforcement probability produced a rightward shift. Intermixing different flash rates within sessions separated allocations: Faster flash rates shifted the functions sooner in real time, but later in terms of flash count, and conversely for slower flash rates. A model of control by fading memories of number and time was proposed.

  13. Professional Flash Lite Mobile Development

    CERN Document Server

    Anderson, J G

    2010-01-01

    Discover how to create Flash Lite mobile apps from the ground up. Adobe Flash is an ideal choice for developing rich interactive content for "Flash-enabled" mobile devices; and with this book, you'll learn how to create unique applications with Flash Lite. Through a series of code samples and extensive example applications, you'll explore the core concepts, key features, and best practices of the Flash Lite player. Coverage reveals various ways to develop Flash mobile content, create applications with a cross-platform programming framework based on the Model, View and Controller conc

  14. Timing in a FLASH

    Science.gov (United States)

    Hoek, M.; Cardinali, M.; Corell, O.; Dickescheid, M.; Ferretti B., M. I.; Lauth, W.; Schlimme, B. S.; Sfienti, C.; Thiel, M.

    2017-12-01

    A prototype detector, called FLASH (Fast Light Acquiring Start Hodoscope), was built to provide precise Time-of-Flight (TOF) measurements and reference timestamps for detector setups at external beam lines. Radiator bars, made of synthetic fused silica, were coupled to a fast MCP-PMT with 64 channels and read out with custom electronics using Time-over-Threshold (TOT) for signal characterization. The TRB3 system, a high-precision TDC implemented in an FPGA, was used as data acquisition system. The performance of a system consisting of two FLASH units was investigated at a dedicated test experiment at the Mainz Microtron (MAMI) accelerator using its 855 MeV electron beam. The TOT measurement enabled time walk corrections and an overall TOF resolution of ∼70 ps could be achieved which translates into a resolution of ∼50 ps per FLASH unit. The intrinsic resolution of the frontend electronics including the TDC was measured to be less than 25 ps.

  15. Foundation Flash Cartoon Animation

    CERN Document Server

    Jones, Tim; Rosson, Allan S

    2008-01-01

    One of Flash s most common uses is still animation for cartoons, games, advertising etc, and this book takes a fresh look at the topic, breaking it down pre-production, production, and post production, and looking at each section in detail, and covering topics such as storyboarding, character libraries and camera mechanics like no Flash book has before. The book is written by members of the Emmy award winning ANIMAX team, who have created work for clients such as Disney, AOL, Fox, WWE, ESPN, and Sesame workshop. This book is an opportunity for them to share their secrets, and is written to sui

  16. Flash x-ray

    International Nuclear Information System (INIS)

    Johnson, Q.; Pellinen, D.

    1976-01-01

    The complementary techniques of flash x-ray radiography (FXR) and flash x-ray diffraction (FXD) provide access to a unique domain in nondestructive materials testing. FXR is useful in studies of macroscopic properties during extremely short time intervals, and FXD, the newer technique, is used in studies of microscopic properties. Although these techniques are similar in many respects, there are some substantial differences. FXD generally requires low-voltage, line-radiation sources and extremely accurate timing; FXR is usually less demanding. Phenomena which can be profitably studied by FXR often can also be studied by FXD to permit a complete materials characterization

  17. Theory of optical flashes

    International Nuclear Information System (INIS)

    London, R.A.

    1983-01-01

    The theory of optical flashes created by x- and γ-ray burst heating of stars in binaries is reviewed. Calculations of spectra due to steady-state x-ray reprocessing and estimates of the fundamental time scales for the non-steady case are discussed. The results are applied to the extant optical data from x-ray and γ-ray bursters. Finally, I review predictions of flashes from γ-ray bursters detectable by a state of the art all-sky optical monitor

  18. Non-volatile resistive switching in the Mott insulator (V1-xCrx)2O3

    Science.gov (United States)

    Querré, M.; Tranchant, J.; Corraze, B.; Cordier, S.; Bouquet, V.; Députier, S.; Guilloux-Viry, M.; Besland, M.-P.; Janod, E.; Cario, L.

    2018-05-01

    The discovery of non-volatile resistive switching in Mott insulators related to an electric-field-induced insulator to metal transition (IMT) has paved the way for their use in a new type of non-volatile memories, the Mott memories. While most of the previous studies were dedicated to uncover the resistive switching mechanism and explore the memory potential of chalcogenide Mott insulators, we present here a comprehensive study of resistive switching in the canonical oxide Mott insulator (V1-xCrx)2O3. Our work demonstrates that this compound undergoes a non-volatile resistive switching under electric field. This resistive switching is induced by a Mott transition at the local scale which creates metallic domains closely related to existing phases of the temperature-pressure phase diagram of (V1-xCrx)2O3. Our work demonstrates also reversible resistive switching in (V1-xCrx)2O3 crystals and thin film devices. Preliminary performances obtained on 880 nm thick layers with 500 nm electrodes show the strong potential of Mott memories based on the Mott insulator (V1-xCrx)2O3.

  19. Learning Flash CS4 Professional

    CERN Document Server

    Shupe, Rich

    2009-01-01

    Learning Flash CS4 Professional offers beginners and intermediate Flash developers a unique introduction to the latest version of Adobe's powerful multimedia application. This easy-to-read book is loaded with full-color examples and hands-on tasks to help you master Flash CS4's new motion editor, integrated 3D system, and character control using the new inverse kinematics bones animation system. No previous Flash experience is necessary.

  20. Jaan Toomik Flash Artis

    Index Scriptorium Estoniae

    1999-01-01

    1999. a. mai-juuni 'Flash Artis' on ajakirja Eesti korrespondendi Ando Keskküla artikkel Jaan Toomikust. Jaan Toomik on kutsutud esinema Londoni The Photographers' Gallery grupinäitusele, tema videot 'Father and Son' näidatakse Londonis avataval näitusel 'Near and Elsewhere' 11.-24. juunini

  1. Inessa Josing Flash Artis

    Index Scriptorium Estoniae

    1999-01-01

    'Flash Art'i' 1998. a. nov.-dets. numbris Rosa Martínezi artiklis suvisest Manifesta II näitusest Luxembourg'is on positiivselt mainitud ka Inessa Josingut. Illustratsiooniks toodud seitsmest fotost ühel on I. Josingu aknakujundus 'What Must I Do to be Saved?'

  2. Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

    Science.gov (United States)

    Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

    Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

  3. Organic ferroelectric opto-electronic memories

    NARCIS (Netherlands)

    Asadi, K.; Li, M.; Blom, P.W.M.; Kemerink, M.; Leeuw, D.M. de

    2011-01-01

    Memory is a prerequisite for many electronic devices. Organic non-volatile memory devices based on ferroelectricity are a promising approach towards the development of a low-cost memory technology based on a simple cross-bar array. In this review article we discuss the latest developments in this

  4. Dual-functional Memory and Threshold Resistive Switching Based on the Push-Pull Mechanism of Oxygen Ions

    KAUST Repository

    Huang, Yi-Jen

    2016-04-07

    The combination of nonvolatile memory switching and volatile threshold switching functions of transition metal oxides in crossbar memory arrays is of great potential for replacing charge-based flash memory in very-large-scale integration. Here, we show that the resistive switching material structure, (amorphous TiOx)/(Ag nanoparticles)/(polycrystalline TiOx), fabricated on the textured-FTO substrate with ITO as the top electrode exhibits both the memory switching and threshold switching functions. When the device is used for resistive switching, it is forming-free for resistive memory applications with low operation voltage (<±1 V) and self-compliance to current up to 50 μA. When it is used for threshold switching, the low threshold current is beneficial for improving the device selectivity. The variation of oxygen distribution measured by energy dispersive X-ray spectroscopy and scanning transmission electron microscopy indicates the formation or rupture of conducting filaments in the device at different resistance states. It is therefore suggested that the push and pull actions of oxygen ions in the amorphous TiOx and polycrystalline TiOx films during the voltage sweep account for the memory switching and threshold switching properties in the device.

  5. Scaling Techniques for Massive Scale-Free Graphs in Distributed (External) Memory

    KAUST Repository

    Pearce, Roger

    2013-05-01

    We present techniques to process large scale-free graphs in distributed memory. Our aim is to scale to trillions of edges, and our research is targeted at leadership class supercomputers and clusters with local non-volatile memory, e.g., NAND Flash. We apply an edge list partitioning technique, designed to accommodate high-degree vertices (hubs) that create scaling challenges when processing scale-free graphs. In addition to partitioning hubs, we use ghost vertices to represent the hubs to reduce communication hotspots. We present a scaling study with three important graph algorithms: Breadth-First Search (BFS), K-Core decomposition, and Triangle Counting. We also demonstrate scalability on BG/P Intrepid by comparing to best known Graph500 results. We show results on two clusters with local NVRAM storage that are capable of traversing trillion-edge scale-free graphs. By leveraging node-local NAND Flash, our approach can process thirty-two times larger datasets with only a 39% performance degradation in Traversed Edges Per Second (TEPS). © 2013 IEEE.

  6. Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

    International Nuclear Information System (INIS)

    Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming

    2017-01-01

    The attractive usability of quantum phenomena in futuristic devices is possible by using zero-dimensional systems like nanocrystals (NCs). The performance of nonvolatile flash memory devices has greatly benefited from the use of NCs over recent decades. The quantum abilities of NCs have been used to improve the reliability of flash devices. Its appeal is extended to the design of emerging devices such as resistive random-access memory (RRAM), a technology where the use of silicon is optional. Here, we are going to review the recent progress in the design, characterization, and utilization of NCs in RRAM devices. We will first introduce the physical design of the RRAM devices using NCs and the improvement of electrical performance in NC-RRAM over conventional ones. In particular, special care has been taken to review the ways of development provided by the NCs in the RRAM devices. In a broad sense, the NCs can play a charge trapping role in the NC-RRAM structure or it can be responsible for the localization and improvement of the stability of the conductive filament or it can play a part in the formation of the conductive filament chain by the NC migration under applied bias. Finally, the scope of NCs in the RRAM devices has also been discussed. (topical review)

  7. Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

    Science.gov (United States)

    Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming

    2017-08-01

    The attractive usability of quantum phenomena in futuristic devices is possible by using zero-dimensional systems like nanocrystals (NCs). The performance of nonvolatile flash memory devices has greatly benefited from the use of NCs over recent decades. The quantum abilities of NCs have been used to improve the reliability of flash devices. Its appeal is extended to the design of emerging devices such as resistive random-access memory (RRAM), a technology where the use of silicon is optional. Here, we are going to review the recent progress in the design, characterization, and utilization of NCs in RRAM devices. We will first introduce the physical design of the RRAM devices using NCs and the improvement of electrical performance in NC-RRAM over conventional ones. In particular, special care has been taken to review the ways of development provided by the NCs in the RRAM devices. In a broad sense, the NCs can play a charge trapping role in the NC-RRAM structure or it can be responsible for the localization and improvement of the stability of the conductive filament or it can play a part in the formation of the conductive filament chain by the NC migration under applied bias. Finally, the scope of NCs in the RRAM devices has also been discussed.

  8. Investigations of Photovoltaic Ferroelectric-Semiconductor Nonvolatile Memory.

    Science.gov (United States)

    1981-03-01

    HEWLETT-PACKARD BOX 3310 100 MARKET ST APT 1 3404 EAST HARMONY RD2U ATTN J. M. KIRSCH, MTS ATTN R. SCHAEFER ATTN L. W. JAMES, MTS FULLERTON, CA 92633...RADIO SYS SPERRY UNICORN 1300 S ROGERS 367 ORCHARD STREET 52-21 65 PL AT’rN J. F. PRATHER, MGR CEN ATTN I. A. PAULL, ES ATTN W. BURSTEIN, ENGR

  9. 1 Gb Radiation Hardened Nonvolatile Memory Development, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of this effort is to identify, characterize and develop advanced semiconductor materials and fabrication process techniques, and design and produce a...

  10. Reconfigurable Electronics and Non-Volatile Memory Research

    Science.gov (United States)

    2011-10-14

    October 2009. The films were etched off wafer pieces using a blend of sulfuric, nitric and hydrofluoric acids and diluted for analysis. Table 5...interactions. A weak peak is also seen around g = 1.98 which intensifies under light illumination. This peak can be assigned to the charge defects of base...evidence of amorphous/crystalline GST. It is not clear why significantly oxidized devices were capable of switching. Dr. Miotti theorized that

  11. Reconfigurable Magnetic Logic Combined with Nonvolatile Memory Writing

    KAUST Repository

    Luo, Zhaochu

    2016-11-16

    In the magnetic logic, four basic Boolean logic operations can be programmed by a magnetic bit at room temperature with a high output ratio (>103%). In the same clock cycle, benefiting from the built-in spin Hall effect, logic results can be directly written into magnetic bits using an all-electric method.

  12. Reconfigurable Electronics and Non-Volatile Memory Research

    Science.gov (United States)

    2015-11-10

    spectrophotometer tool uses film reflectance to calculate film thickness via a set of proprietary algorithms and a developed recipe for material type. The...tool can also be used to collect transmission spectra. Recipes must be developed for each film type (and stack) that is measured. Once the recipe has...Regner, J.K.; Balasubramanian, M; Cook , B.; Li, Y.; Kassayebetre, H. Sharma, A.; Baker, R.J.; Campbell, K.A., “Integration of IC Industry Feature

  13. Reconfigurable Magnetic Logic Combined with Nonvolatile Memory Writing

    KAUST Repository

    Luo, Zhaochu; Lu, Ziyao; Xiong, Chengyue; Zhu, Tao; Wu, Wei; Zhang, Qiang; Wu, Huaqiang; Zhang, Xixiang; Zhang, Xiaozhong

    2016-01-01

    In the magnetic logic, four basic Boolean logic operations can be programmed by a magnetic bit at room temperature with a high output ratio (>103%). In the same clock cycle, benefiting from the built-in spin Hall effect, logic results can be directly written into magnetic bits using an all-electric method.

  14. Physics Flash August 2016

    Energy Technology Data Exchange (ETDEWEB)

    Kippen, Karen Elizabeth [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

    2016-08-25

    Physics Flash is the newsletter for the Physics Division at Los Alamos National Laboratory. This newsletter is for August 2016. The following topics are covered: "Accomplishments in the Trident Laser Facility", "David Meyerhofer elected as chair-elect APS Nominating Committee", "HAWC searches for gamma rays from dark matter", "Proton Radiography Facility commissions electromagnetic magnifier", and "Cosmic ray muon computed tomography of spent nuclear fuel in dry storage casks."

  15. The lightning flash

    CERN Document Server

    Cooray, Vernon

    2014-01-01

    With contributions from today's leading lightning engineers and researchers, this updated 2nd edition of Vernon Cooray's classic text, The Lightning Flash provides the reader with an essential introduction to lightning and its impact on electrical and electronic equipment. Providing the reader with a thorough background into almost every aspect of lightning and its impact on electrical and electronic equipment, this new edition is updated throughout and features eight new chapters that bring the science up to date.

  16. Deconstructing continuous flash suppression

    OpenAIRE

    Yang, Eunice; Blake, Randolph

    2012-01-01

    In this paper, we asked to what extent the depth of interocular suppression engendered by continuous flash suppression (CFS) varies depending on spatiotemporal properties of the suppressed stimulus and CFS suppressor. An answer to this question could have implications for interpreting the results in which CFS influences the processing of different categories of stimuli to different extents. In a series of experiments, we measured the selectivity and depth of suppression (i.e., elevation in co...

  17. Coherent imaging at FLASH

    International Nuclear Information System (INIS)

    Chapman, H N; Bajt, S; Duesterer, S; Treusch, R; Barty, A; Benner, W H; Bogan, M J; Frank, M; Hau-Riege, S P; Woods, B W; Boutet, S; Cavalleri, A; Hajdu, J; Iwan, B; Seibert, M M; Timneanu, N; Marchesini, S; Sakdinawat, A; Sokolowski-Tinten, K

    2009-01-01

    We have carried out high-resolution single-pulse coherent diffractive imaging at the FLASH free-electron laser. The intense focused FEL pulse gives a high-resolution low-noise coherent diffraction pattern of an object before that object turns into a plasma and explodes. In particular we are developing imaging of biological specimens beyond conventional radiation damage resolution limits, developing imaging of ultrafast processes, and testing methods to characterize and perform single-particle imaging.

  18. Physics Flash December 2016

    Energy Technology Data Exchange (ETDEWEB)

    Kippen, Karen Elizabeth [Los Alamos National Lab. (LANL), Los Alamos, NM (United States). ADEPS Communications

    2016-12-01

    This is the December 2016 issue of Physics Flash, the newsletter of the Physics Division of Los Alamos National Laboratory (LANL). In this issue, the following topics are covered: Novel liquid helium technique to aid highly sensitive search for a neutron electrical dipole moment; Silverleaf: Prototype Red Sage experiments performed at Q-site; John L. Kline named 2016 APS Fellow; Physics students in the news; First Entropy Engine quantum random number generator hits the market; and celebrating service.

  19. Enhanced memory performance by tailoring the microstructural evolution of (ZrO{sub 2}){sub 0.6}(SiO{sub 2}){sub 0.4} charge trapping layer in the nanocrystallites-based charge trap flash memory cells

    Energy Technology Data Exchange (ETDEWEB)

    Tang, Zhenjie; Xu, Hanni; Xia, Yidong; Yin, Jiang; Li, Aidong; Liu, Zhiguo [Nanjing University, Department of Materials Science and Engineering and National Laboratory of Solid State Microstructures, Nanjing (China); Zhu, Xinhua [Nanjing University, Department of Physics and National and Laboratory of Solid State Microstructures, Nanjing (China); Yan, Feng [Nanjing University, School of Electronics Science and Engineering, Nanjing (China)

    2012-07-15

    ZrO{sub 2} nanocrystallites based charge trap memory cells by incorporating a (ZrO{sub 2}){sub 0.6}(SiO{sub 2}){sub 0.4} film as a charge trapping layer and amorphous Al{sub 2}O{sub 3} as tunneling and blocking layer were prepared and investigated. The precipitation reaction in charge trapping layer forming ZrO{sub 2} nanocrystallites during rapid thermal annealing was investigated by transmission electron microscopy. The density and size of ZrO{sub 2} nanocrystallites are the critical factors for controlling the charge storage characteristics. The ZrO{sub 2} nanocrystallites based memory cells after postannealing at 800 C for 60 s exhibit the best electrical characteristics and a low charge loss {proportional_to}5 % after 10{sup 5} write/erase cycles operation. (orig.)

  20. Interfacial Redox Reactions Associated Ionic Transport in Oxide-Based Memories.

    Science.gov (United States)

    Younis, Adnan; Chu, Dewei; Shah, Abdul Hadi; Du, Haiwei; Li, Sean

    2017-01-18

    As an alternative to transistor-based flash memories, redox reactions mediated resistive switches are considered as the most promising next-generation nonvolatile memories that combine the advantages of a simple metal/solid electrolyte (insulator)/metal structure, high scalability, low power consumption, and fast processing. For cation-based memories, the unavailability of in-built mobile cations in many solid electrolytes/insulators (e.g., Ta 2 O 5 , SiO 2 , etc.) instigates the essential role of absorbed water in films to keep electroneutrality for redox reactions at counter electrodes. Herein, we demonstrate electrochemical characteristics (oxidation/reduction reactions) of active electrodes (Ag and Cu) at the electrode/electrolyte interface and their subsequent ions transportation in Fe 3 O 4 film by means of cyclic voltammetry measurements. By posing positive potentials on Ag/Cu active electrodes, Ag preferentially oxidized to Ag + , while Cu prefers to oxidize into Cu 2+ first, followed by Cu/Cu + oxidation. By sweeping the reverse potential, the oxidized ions can be subsequently reduced at the counter electrode. The results presented here provide a detailed understanding of the resistive switching phenomenon in Fe 3 O 4 -based memory cells. The results were further discussed on the basis of electrochemically assisted cations diffusions in the presence of absorbed surface water molecules in the film.

  1. Low Cost Writeable RFID Tag With MRAM Memory

    National Research Council Canada - National Science Library

    Beech, Russell

    1998-01-01

    This program's goal was to develop a writeable RFID tag using an integrated, permeable core coil as the inductor/antenna for communication and power transfer and MRAM as the low write energy, nonvolatile memory...

  2. Flashing inception in flowing liquids

    International Nuclear Information System (INIS)

    Jones, O.C. Jr.

    1979-01-01

    The inception of net vaporization in flashing flows is examined. It is suggested that the flashing inception can be expressed as two additive effects. One is due to the static decompression which is a function of the spinodal limit and also of the expansion rate. The other effect which is a function of Reynolds number and flashing index, is due to the turbulent fluctuations of the flowing liquid. It is shown that by taking a three standard deviation band on the turbulent velocity fluctuations, an adequate representation of the inverse mass flux effect on flashing inception for existing data is obtained

  3. Modular Electronics for Flash Memory Production

    Science.gov (United States)

    2011-12-28

    DEFENSE TECHNICAL INFORMATION CENTER ImuM ktkUmlimäj DTICfhas determined on oc öf^H AJI that this Technical Document has the Distribution...the second harmonic (8I2/8V2), and a normalization to remove the scale of the measured current. The red dashed lines represent notable vibrational...superimposed as red dashed lines. The agreement between the two spectroscopies is conclusive that we have successfully put our OPE derivative into the gap

  4. Performance improvement of charge-trap memory by using a stacked Zr_0_._4_6Si_0_._5_4O_2/Al_2O_3 charge-trapping layer

    International Nuclear Information System (INIS)

    Tang, Zhenjie; Hu, Dan; Zhang, Xiwei; Zhao, Yage; Li, Rong

    2016-01-01

    The postdeposition annealing (PDA)-treated charge-trap flash memory capacitor with stacked Zr_0_._4_6Si_0_._5_4O_2/Al_2O_3 charge-trapping layer flanked by a SiO_2 tunneling oxide and an Al_2O_3 blocking oxide was fabricated and investigated. It is observed that the memory capacitor exhibits prominent memory characteristics with large memory windows 12.8 V in a ±10 V gate sweeping voltage range, faster program/erase speed, and good data-retention characteristics even at 125 C compared to a single charge-trapping layer (Zr_0_._4_6Si_0_._5_4O_2, Zr_0_._7_9Si_0_._2_1O_2, and Zr_0_._4_6Al_1_._0_8O_2_._5_4). The quantum wells and introduced interfacial traps of the stacked trapping layer regulate the storage and loss behavior of charges, and jointly contribute to the improved memory characteristics. Hence, the memory capacitor with a stacked trapping layer is a promising candidate in future nonvolatile charge-trap memory device design and application. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  5. Performance improvement of charge-trap memory by using a stacked Zr{sub 0.46}Si{sub 0.54}O{sub 2}/Al{sub 2}O{sub 3} charge-trapping layer

    Energy Technology Data Exchange (ETDEWEB)

    Tang, Zhenjie; Hu, Dan; Zhang, Xiwei; Zhao, Yage [College of Physics and Electronic Engineering, Anyang Normal University, Anyang 455000 (China); Li, Rong [School of Mathematics and Statistics, Anyang Normal University, Anyang 455000 (China)

    2016-11-15

    The postdeposition annealing (PDA)-treated charge-trap flash memory capacitor with stacked Zr{sub 0.46}Si{sub 0.54}O{sub 2}/Al{sub 2}O{sub 3} charge-trapping layer flanked by a SiO{sub 2} tunneling oxide and an Al{sub 2}O{sub 3} blocking oxide was fabricated and investigated. It is observed that the memory capacitor exhibits prominent memory characteristics with large memory windows 12.8 V in a ±10 V gate sweeping voltage range, faster program/erase speed, and good data-retention characteristics even at 125 C compared to a single charge-trapping layer (Zr{sub 0.46}Si{sub 0.54}O{sub 2}, Zr{sub 0.79}Si{sub 0.21}O{sub 2}, and Zr{sub 0.46}Al{sub 1.08}O{sub 2.54}). The quantum wells and introduced interfacial traps of the stacked trapping layer regulate the storage and loss behavior of charges, and jointly contribute to the improved memory characteristics. Hence, the memory capacitor with a stacked trapping layer is a promising candidate in future nonvolatile charge-trap memory device design and application. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  6. Flash X-ray

    International Nuclear Information System (INIS)

    Sato, Eiichi

    2003-01-01

    Generation of quasi-monochromatic X-ray by production of weakly ionized line plasma (flash X-ray), high-speed imaging by the X-ray and high-contrast imaging by the characteristic X-ray absorption are described. The equipment for the X-ray is consisted from the high-voltage power supply and condenser, turbo molecular pump, and plasma X-ray tube. The tube has a long linear anticathode to produce the line plasma and flash X-ray at 20 kA current at maximum. X-ray spectrum is measured by the imaging plate equipped in the computed radiography system after diffracted by a LiF single crystal bender. Cu anticathode generates sharp peaks of K X-ray series. The tissue images are presented for vertebra, rabbit ear and heart, and dog heart by X-ray fluoroscopy with Ce anticathode. Generation of K-orbit characteristic X-ray with extremely low bremsstrahung is to be attempted for medical use. (N.I.)

  7. System of ispFlash configuration

    International Nuclear Information System (INIS)

    Bourrion, Olivier

    2003-01-01

    The aim of this module is to allow the use of FPGA components instead of EPLD components which for an equivalent or even inferior capacity are more expensive. For instance, the idea is to replace CPLD components having 512 macro-cells by one FPGA spartan II of Xilinx. However, due to the configuration's volatility, one configuration means is needed to put under voltage. A solution appears to be the using of a high capacity Flash memory coupled to a CPLD of small size to comply with the FPGA configuration protocol; also, one has to provide an in situ configuration means for this memory. Obviously, a product having an equivalent functionality already exists, since Xilinx and ALTERA supply PROMs of serial configuration. Unfortunately, they are expensive and a dealer is implied while the FLASH, the small CPLD and the FPGA spartan II are currently available. In conclusion, by using this assembly, which requires a small supplementary surface and a delay of upmost 240 ms (for the largest FPGA 1 Mbit), one obtains a solution cheaper and more performing than an EPLD of high capacity

  8. Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

    Science.gov (United States)

    Erlbacher, T.; Huerner, A.; Bauer, A. J.; Frey, L.

    2012-09-01

    Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

  9. Ferroelectric polymer gates for non-volatile field effect control of ferromagnetism in (Ga, Mn)As layers

    International Nuclear Information System (INIS)

    Stolichnov, I; Riester, S W E; Mikheev, E; Setter, N; Rushforth, A W; Edmonds, K W; Campion, R P; Foxon, C T; Gallagher, B L; Jungwirth, T; Trodahl, H J

    2011-01-01

    (Ga, Mn)As and other diluted magnetic semiconductors (DMS) attract a great deal of attention for potential spintronic applications because of the possibility of controlling the magnetic properties via electrical gating. Integration of a ferroelectric gate on the DMS channel adds to the system a non-volatile memory functionality and permits nanopatterning via the polarization domain engineering. This topical review is focused on the multiferroic system, where the ferromagnetism in the (Ga, Mn)As DMS channel is controlled by the non-volatile field effect of the spontaneous polarization. Use of ferroelectric polymer gates in such heterostructures offers a viable alternative to the traditional oxide ferroelectrics generally incompatible with DMS. Here we review the proof-of-concept experiments demonstrating the ferroelectric control of ferromagnetism, analyze the performance issues of the ferroelectric gates and discuss prospects for further development of the ferroelectric/DMS heterostructures toward the multiferroic field effect transistor. (topical review)

  10. Memory

    OpenAIRE

    Wager, Nadia

    2017-01-01

    This chapter will explore a response to traumatic victimisation which has divided the opinions of psychologists at an exponential rate. We will be examining amnesia for memories of childhood sexual abuse and the potential to recover these memories in adulthood. Whilst this phenomenon is generally accepted in clinical circles, it is seen as highly contentious amongst research psychologists, particularly experimental cognitive psychologists. The chapter will begin with a real case study of a wo...

  11. Laser-flash calorimetry

    International Nuclear Information System (INIS)

    Takahashi, Y.; Nakamura, J.-I.

    1982-01-01

    The heat capacity of vanadium has been measured by laser-flash calorimetry in the temperature region from 80 to 1000 K. The results are compared with available low- and high-temperature heat capacities, and revised thermodynamic values of vanadium are given. No heat-capacity anomaly has been found in the pure vanadium sample over the temperature range investigated, while a small heat-capacity discontinuity, less than 1.2 J.K -1 .mol -1 , has been observed at 220 to 230 K on the same sample but electropolished before measurement. This anomaly disappeared after annealing at 1000 K in vacuo for 1 h and is attributable to the introduction of a small amount of hydrogen during electropolishing. (author)

  12. Identification of nonvolatile compounds in clove (Syzygium aromaticum) from Manado

    Science.gov (United States)

    Fathoni, A.; Saepudin, E.; Cahyana, A. H.; Rahayu, D. U. C.; Haib, J.

    2017-07-01

    Syzygium aromaticum (clove) are native to Indonesia and have been widely used in food industry due to their flavor. Nonvolatile compounds contribute to flavor, mainly in their taste. Currently, there is very little information available about nonvolatile compounds in clove. Identification of nonvolatile compounds is important to improve clove's value. Compound extraction was conducted by maceration in ethanol. Fractionations of the extract were performed by using gravity column chromatography on silica gel and Sephadex LH-20 as stationary phase. Nonvolatile compounds were identified by Liquid Chromatography-Tandem Mass Spectrometry (LC-MS/MS). LC-MS/MS was operated in negative mode with 0.1 % formic acid in water and acetonitrile as mobile phase. Nonvolatile compounds were identified by fragment analysis and compared to references. Several compounds had been identified and characterized asquinic acid, monogalloylglucose, gallic acid, digalloylglucose, isobiflorin, biflorin, ellagic acid, hydroxygallic acid, luteolin, quercetin, naringenin, kaempferol, isorhamnetin, dimethoxyluteolin, and rhamnetin. These compounds had two main flavor perceptions, i.e. astringent, and bitter.

  13. Flashing oscillation in pool water

    International Nuclear Information System (INIS)

    Takamasa, Tomoji; Kondo, Koichi; Hazuku, Tatsuya

    1996-01-01

    This paper presents an experimental study of high-pressure saturated water discharging into the pool water. The purpose of the experiment is to clarify the phenomena that occur in blow-down of high-pressure saturated water from the pressure vessel into the water-filled containment in the case of a wall-crack accident or a LOCA in an advanced reactor. The results revealed that a flashing oscillation (FO) occurs when high-pressure saturated water discharges into the pool water, under specified experimental settings. The range of the flashing oscillates between a point very close to and some distance from the vent hole. The pressures in the vent tube and pool water vary according to the flashing oscillation. The pressure oscillation and frequency of flashing position might be caused by the balancing action between the supply of saturated water, flashing at the control volume and its condensation on the steam-water interface. A linear analysis was conducted using a spherical flashing bubble model. The period of the flashing oscillation in the experiments can be explained by theoretical analysis

  14. Flashing coupled density wave oscillation

    International Nuclear Information System (INIS)

    Jiang Shengyao; Wu Xinxin; Zhang Youjie

    1997-07-01

    The experiment was performed on the test loop (HRTL-5), which simulates the geometry and system design of the 5 MW reactor. The phenomenon and mechanism of different kinds of two-phase flow instabilities, namely geyser instability, flashing instability and flashing coupled density wave instability are described. The especially interpreted flashing coupled density wave instability has never been studied well, it is analyzed by using a one-dimensional non-thermo equilibrium two-phase flow drift model computer code. Calculations are in good agreement with the experiment results. (5 refs.,5 figs., 1 tab.)

  15. Memories.

    Science.gov (United States)

    Brand, Judith, Ed.

    1998-01-01

    This theme issue of the journal "Exploring" covers the topic of "memories" and describes an exhibition at San Francisco's Exploratorium that ran from May 22, 1998 through January 1999 and that contained over 40 hands-on exhibits, demonstrations, artworks, images, sounds, smells, and tastes that demonstrated and depicted the biological,…

  16. Two-dimensional non-volatile programmable p-n junctions

    Science.gov (United States)

    Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

    2017-09-01

    Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

  17. Observers can reliably identify illusory flashes in the illusory flash paradigm

    NARCIS (Netherlands)

    Erp, J.B.F. van; Philippi, T.G.; Werkhoven, P.

    2013-01-01

    In the illusory flash paradigm, a single flash may be experienced as two flashes when accompanied by two beeps or taps, and two flashes may be experienced as a single flash when accompanied by one beep or tap. The classic paradigm restricts responses to '1' and '2' (2-AFC), ignoring possible

  18. Flashing inception in flowing liquids

    International Nuclear Information System (INIS)

    Jones, O.C. Jr.

    1980-01-01

    The inception of net vaporization in flashing flows is examined. It is suggested that the flashing inception can be expressed as two additive effects. One is due to the static decompression which is a function of the initial temperature and also the expansion rate. The other effect which is a function of Reynolds number and flashing index, is due to the turbulent fluctuations of the flowing liquid. It is shown that by taking a three standard deviation band on the turbulent velocity fluctuations, an adequate representation of the inverse mass flux effect on flashing inception for existing data is obtained. The turbulence effects are combined with the correlation of Alamgir and Lienhard to provide predictive methods recommended for the case where both static and convective decompression effects exist

  19. Research of coal flash hydropyrolysis

    Energy Technology Data Exchange (ETDEWEB)

    Zhu, Z.; Zhu, H.; Wu, Y.; Tang, L.; Cheng, L.; Xu, Z. [East China University of Science and Technology, Shanghai (China)

    2001-02-01

    Using x-ray photoelectron spectroscopy (XPS) analyses the organic sufur of seven different Chinese coals and their semi-cokes from flash hydropyrolysis were studied. The results showed that the organic sulfur in coal was alkyal sulfur and thiophene with the peak of XPS located in 163.1-163.5 eV and 164.1-164.5 eV. The relative thiophene content in coal increased with the coal rank. The type of organic sulfur in semi-coke in flash hydropyrolysis was generally thiophene species; its XPS peak also located in 164.1-164.5 eV, and was in accord with its corresponding coal. Total alkyl sulfur and some thiophene sulfur were removed during the flash hydropyrolysis process. The alkyl sulfur had very high activity in hydrogenation reaction. Flash hydropyrolysis was an important new clean-coal technique and had notable desulfurization effect. 13 refs., 2 figs., 4 tabs.

  20. New flash mixing

    International Nuclear Information System (INIS)

    Sackmann, I.

    1980-01-01

    It was found that even for stars evolved away from the red giant branch, a new mixing of nucleo-synthesis products from the hydrogen-burning shells into surface layers was possible, from the penetration of the contaminated intershell region with the H- and He-ionization convection zones. This is due to the helium shell flash driving an immense expansion of an inner carbon pocket, namely, by a factor of 12,000 in radius, a drop in density of about 10 12 , and a cooling of inner pockets normally near 10 8 K to 23,000 K. The surface would be enriched in carbon ( 12 C), helium ( 4 He), and s-process elements, but not significantly in nitrogen ( 14 N), oxygen ( 16 O), or the isotope 13 C. This new type of mixing might provide the missing clue for FG Sagittae. Such a mixing had been suggested by the observations of FG Sagittae, but had been unexplainable by theory up to now

  1. Deconstructing continuous flash suppression.

    Science.gov (United States)

    Yang, Eunice; Blake, Randolph

    2012-03-08

    In this paper, we asked to what extent the depth of interocular suppression engendered by continuous flash suppression (CFS) varies depending on spatiotemporal properties of the suppressed stimulus and CFS suppressor. An answer to this question could have implications for interpreting the results in which CFS influences the processing of different categories of stimuli to different extents. In a series of experiments, we measured the selectivity and depth of suppression (i.e., elevation in contrast detection thresholds) as a function of the visual features of the stimulus being suppressed and the stimulus evoking suppression, namely, the popular "Mondrian" CFS stimulus (N. Tsuchiya & C. Koch, 2005). First, we found that CFS differentially suppresses the spatial components of the suppressed stimulus: Observers' sensitivity for stimuli of relatively low spatial frequency or cardinally oriented features was more strongly impaired in comparison to high spatial frequency or obliquely oriented stimuli. Second, we discovered that this feature-selective bias primarily arises from the spatiotemporal structure of the CFS stimulus, particularly within information residing in the low spatial frequency range and within the smooth rather than abrupt luminance changes over time. These results imply that this CFS stimulus operates by selectively attenuating certain classes of low-level signals while leaving others to be potentially encoded during suppression. These findings underscore the importance of considering the contribution of low-level features in stimulus-driven effects that are reported under CFS.

  2. Efficient Management for Hybrid Memory in Managed Language Runtime

    OpenAIRE

    Wang , Chenxi; Cao , Ting; Zigman , John; Lv , Fang; Zhang , Yunquan; Feng , Xiaobing

    2016-01-01

    Part 1: Memory: Non-Volatile, Solid State Drives, Hybrid Systems; International audience; Hybrid memory, which leverages the benefits of traditional DRAM and emerging memory technologies, is a promising alternative for future main memory design. However popular management policies through memory-access recording and page migration may invoke non-trivial overhead in execution time and hardware space. Nowadays, managed language applications are increasingly dominant in every kind of platform. M...

  3. Quick-low-density parity check and dynamic threshold voltage optimization in 1X nm triple-level cell NAND flash memory with comprehensive analysis of endurance, retention-time, and temperature variation

    Science.gov (United States)

    Doi, Masafumi; Tokutomi, Tsukasa; Hachiya, Shogo; Kobayashi, Atsuro; Tanakamaru, Shuhei; Ning, Sheyang; Ogura Iwasaki, Tomoko; Takeuchi, Ken

    2016-08-01

    NAND flash memory’s reliability degrades with increasing endurance, retention-time and/or temperature. After a comprehensive evaluation of 1X nm triple-level cell (TLC) NAND flash, two highly reliable techniques are proposed. The first proposal, quick low-density parity check (Quick-LDPC), requires only one cell read in order to accurately estimate a bit-error rate (BER) that includes the effects of temperature, write and erase (W/E) cycles and retention-time. As a result, 83% read latency reduction is achieved compared to conventional AEP-LDPC. Also, W/E cycling is extended by 100% compared with conventional Bose-Chaudhuri-Hocquenghem (BCH) error-correcting code (ECC). The second proposal, dynamic threshold voltage optimization (DVO) has two parts, adaptive V Ref shift (AVS) and V TH space control (VSC). AVS reduces read error and latency by adaptively optimizing the reference voltage (V Ref) based on temperature, W/E cycles and retention-time. AVS stores the optimal V Ref’s in a table in order to enable one cell read. VSC further improves AVS by optimizing the voltage margins between V TH states. DVO reduces BER by 80%.

  4. Flashing light in microalgae biotechnology.

    Science.gov (United States)

    Abu-Ghosh, Said; Fixler, Dror; Dubinsky, Zvy; Iluz, David

    2016-03-01

    Flashing light can enhance photosynthesis and improve the quality and quantity of microalgal biomass, as it can increase the products of interest by magnitudes. Therefore, the integration of flashing light effect into microalgal cultivation systems should be considered. However, microalgae require a balanced mix of the light/dark cycle for higher growth rates, and respond to light intensity differently according to the pigments acquired or lost during the growth. This review highlights recently published results on flashing light effect on microalgae and its applications in biotechnology, as well as the recently developed bioreactors designed to fulfill this effect. It also discusses how this knowledge can be applied in selecting the optimal light frequencies and intensities with specific technical properties for increasing biomass production and/or the yield of the chemicals of interest by microalgae belonging to different genera. Copyright © 2015 Elsevier Ltd. All rights reserved.

  5. Principles of arc flash protection

    Energy Technology Data Exchange (ETDEWEB)

    Hirschmann, R. B.

    2003-04-01

    Recent developments in NFPA 70E, the electrical safety standards in the United States and Canada, designed to provide for a safe industrial work environment, are discussed. The emphasis in this instance is on arc explosions. Development of an arc flash protective program is discussed under various major components of an electrical safety program. These are: appropriate qualifications and training for workers, safe work practices, appropriate hazard assessment practices for any task exceeding 50V where there is the potential of an arc flash accident, flash protection equipment commensurate with the hazard associated with the task to be performed, layering in protective clothing over all body surfaces, and strict adherence to rules regarding use of safety garments and equipment.

  6. Flash sintering of ceramic materials

    Science.gov (United States)

    Dancer, C. E. J.

    2016-10-01

    During flash sintering, ceramic materials can sinter to high density in a matter of seconds while subjected to electric field and elevated temperature. This process, which occurs at lower furnace temperatures and in shorter times than both conventional ceramic sintering and field-assisted methods such as spark plasma sintering, has the potential to radically reduce the power consumption required for the densification of ceramic materials. This paper reviews the experimental work on flash sintering methods carried out to date, and compares the properties of the materials obtained to those produced by conventional sintering. The flash sintering process is described for oxides of zirconium, yttrium, aluminium, tin, zinc, and titanium; silicon and boron carbide, zirconium diboride, materials for solid oxide fuel applications, ferroelectric materials, and composite materials. While experimental observations have been made on a wide range of materials, understanding of the underlying mechanisms responsible for the onset and latter stages of flash sintering is still elusive. Elements of the proposed theories to explain the observed behaviour include extensive Joule heating throughout the material causing thermal runaway, arrested by the current limitation in the power supply, and the formation of defect avalanches which rapidly and dramatically increase the sample conductivity. Undoubtedly, the flash sintering process is affected by the electric field strength, furnace temperature and current density limit, but also by microstructural features such as the presence of second phase particles or dopants and the particle size in the starting material. While further experimental work and modelling is still required to attain a full understanding capable of predicting the success of the flash sintering process in different materials, the technique non-etheless holds great potential for exceptional control of the ceramic sintering process.

  7. Quick Guide to Flash Catalyst

    CERN Document Server

    Elmansy, Rafiq

    2011-01-01

    How do you transform user interface designs created in Photoshop or Illustrator into interactive web pages? It's easier than you think. This guide shows you how to use Adobe Flash Catalyst to create interactive UIs and website wireframes for Rich Internet Applications-without writing a single line of code. Ideal for web designers, this book introduces Flash Catalyst basics with detailed step-by-step instructions and screenshots that illustrate every part of the process. You'll learn hands-on how to turn your static design or artwork into working user interfaces that can be implemented in Fla

  8. Electric Field Tuning Non-volatile Magnetism in Half-Metallic Alloys Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 Heterostructure

    Science.gov (United States)

    Dunzhu, Gesang; Wang, Fenglong; Zhou, Cai; Jiang, Changjun

    2018-03-01

    We reported the non-volatile electric field-mediated magnetic properties in the half-metallic Heusler alloy Co2FeAl/Pb(Mg1/3Nb2/3)O3-PbTiO3 heterostructure at room temperature. The remanent magnetization with different applied electric field along [100] and [01-1] directions was achieved, which showed the non-volatile remanent magnetization driven by an electric field. The two giant reversible and stable remanent magnetization states were obtained by applying pulsed electric field. This can be attributed to the piezostrain effect originating from the piezoelectric substrate, which can be used for magnetoelectric-based memory devices.

  9. Hot Flashes amd Night Sweats (PDQ)

    Science.gov (United States)

    ... Professionals Questions to Ask about Your Treatment Research Hot Flashes and Night Sweats (PDQ®)–Patient Version Overview ... quality of life in many patients with cancer. Hot flashes and night sweats may be side effects ...

  10. Detection of Malicious Flash Banner Advertisements

    Directory of Open Access Journals (Sweden)

    Kirill Alekseevich Samosadnyy

    2014-09-01

    Full Text Available The paper addresses the problem of detecting malicious flash advertisements. As a result, detection method based on dynamic analysis that modify flash application and execute it in Adobe Flash player is proposed and evaluated on synthetic and real world examples.

  11. Flash CS4: The Missing Manual

    CERN Document Server

    Grover, Chris

    2008-01-01

    Unlock the power of Flash and bring gorgeous animations to life onscreen. Flash CS4: The Missing Manual includes a complete primer on animation, a guided tour of the program's tools and capabilities, lots of new illustrations, and more details on working with video. Beginners will learn to use the software in no time, and experienced Flash designers will improve their skills.

  12. RELATIONSHIP BETWEEN FLASH POINTS OF SOME BINARY ...

    African Journals Online (AJOL)

    B. S. Chandravanshi

    Miscellaneous binary blends containing solvent neutral-150 (SN-150), ... viscosity, the flash point test has always been a standard part of a lubricant's specification. ... between structure and flash points of organic compounds [5-12] and fuels [13, 14]. ... in binary mixtures, the gaps between flash points would be high enough.

  13. Jaan Toomik ajakirjas Flash Art

    Index Scriptorium Estoniae

    1999-01-01

    Kunstiajakirja "Flash Art" maikuu numbris Ando Keskküla artikkel, mis annab ülevaate J. Toomiku loomingust ja peatub pikemalt tema olulisematel töödel. 10. juunist J. Toomiku isiknäitus Londoni fotograafide galeriis. Eksponeeritud video "Uisutaja"

  14. Ingmar Muusikuse foto Flash Artis

    Index Scriptorium Estoniae

    1999-01-01

    Flash Arti 1999. a. oktoobrinumbris virtuaalse näituse rubriigis Ando Keskküla artikkel radikaalsemast eesti kunstist ja kunstielust postsotsialistlikul ajastul. Illustratsiooniks Liina Siibi fotokompositsioonid, Ingmar Muusikuse foto Raoul Kurvitza, Ene-Liis Semperi ja Kiwa Eesti Panga performance'ist

  15. Undergraduate Separations Utilizing Flash Chromatography

    Science.gov (United States)

    Horowitz, G.

    2000-02-01

    This article describes the procedures used to carry out four flash chromatography experiments: the isolation of the carotenes, chlorophylls and xanthophylls from a spinach extract; the separation of ß-carotene from tetraphenyl cyclopentadienone; the isolation of (+) and (-) carvone from caraway and spearmint oil; and the purification of benzil from benzoin. Apparatus used is nonbreakable, easy to use, and inexpensive.

  16. Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

    Science.gov (United States)

    Suzuki, Daisuke; Hanyu, Takahiro

    2018-04-01

    A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

  17. Speeding up the flash calculations in two-phase compositional flow simulations - The application of sparse grids

    KAUST Repository

    Wu, Yuanqing

    2015-03-01

    Flash calculations have become a performance bottleneck in the simulation of compositional flow in subsurface reservoirs. We apply a sparse grid surrogate model to substitute the flash calculation and thus try to remove the bottleneck from the reservoir simulation. So instead of doing a flash calculation in each time step of the simulation, we just generate a sparse grid approximation of all possible results of the flash calculation before the reservoir simulation. Then we evaluate the constructed surrogate model to approximate the values of the flash calculation results from this surrogate during the simulations. The execution of the true flash calculation has been shifted from the online phase during the simulation to the offline phase before the simulation. Sparse grids are known to require only few unknowns in order to obtain good approximation qualities. In conjunction with local adaptivity, sparse grids ensure that the accuracy of the surrogate is acceptable while keeping the memory usage small by only storing a minimal amount of values for the surrogate. The accuracy of the sparse grid surrogate during the reservoir simulation is compared to the accuracy of using a surrogate based on regular Cartesian grids and the original flash calculation. The surrogate model improves the speed of the flash calculations and the simulation of the whole reservoir. In an experiment, it is shown that the speed of the online flash calculations is increased by about 2000 times and as a result the speed of the reservoir simulations has been enhanced by 21 times in the best conditions.

  18. Uncorrelated multiple conductive filament nucleation and rupture in ultra-thin high-κ dielectric based resistive random access memory

    KAUST Repository

    Wu, Xing; Li, Kun; Raghavan, Nagarajan; Bosman, Michel; Wang, Qing-Xiao; Cha, Dong Kyu; Zhang, Xixiang; Pey, Kin-Leong

    2011-01-01

    Resistive switching in transition metal oxides could form the basis for next-generation non-volatile memory (NVM). It has been reported that the current in the high-conductivity state of several technologically relevant oxide materials flows through

  19. Foundation Flash CS4 for Designers

    CERN Document Server

    Green, Tom

    2008-01-01

    In this book, you'll learn:* How to create effective animations using the new Motion Editor and animation tools * How to use the new 3D features to animate objects in 3D space * Best-practice tips and techniques from some of the top Flash practitioners on the planet * How to create captioned video and full-screen video, and deploy HD video using Flash * Techniques for using the Flash UI components as well as XML documents to create stunning,interactive presentations If you're a Flash designer looking for a solid overview of Flash CS4, this book is for you. Through the use of solid and practica

  20. Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells.

    Science.gov (United States)

    Paydavosi, Sarah; Aidala, Katherine E; Brown, Patrick R; Hashemi, Pouya; Supran, Geoffrey J; Osedach, Timothy P; Hoyt, Judy L; Bulović, Vladimir

    2012-03-14

    Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells. © 2012 American Chemical Society

  1. On multiphase negative flash for ideal solutions

    DEFF Research Database (Denmark)

    Yan, Wei; Stenby, Erling Halfdan

    2012-01-01

    simpler than the corresponding normal flash algorithm. Unlike normal flash, multiphase negative flash for ideal solutions can diverge if the feasible domain for phase amounts is not closed. This can be judged readily during the iteration process. The algorithm can also be extended to the partial negative......There is a recent interest to solve multiphase negative flash problems where the phase amounts can be negative for normal positive feed composition. Solving such a negative flash problem using successive substitution needs an inner loop for phase distribution calculation at constant fugacity...... coefficients. It is shown that this inner loop, named here as multiphase negative flash for ideal solutions, can be solved either by Michelsen's algorithm for multiphase normal flash, or by its variation which uses F−1 phase amounts as independent variables. In either case, the resulting algorithm is actually...

  2. Nonvolatile field effect transistors based on protons and Si/SiO2Si structures

    International Nuclear Information System (INIS)

    Warren, W.L.; Vanheusden, K.; Fleetwood, D.M.; Schwank, J.R.; Winokur, P.S.; Knoll, M.G.; Devine, R.A.B.

    1997-01-01

    Recently, the authors have demonstrated that annealing Si/SiO 2 /Si structures in a hydrogen containing ambient introduces mobile H + ions into the buried SiO 2 layer. Changes in the H + spatial distribution within the SiO 2 layer were electrically monitored by current-voltage (I-V) measurements. The ability to directly probe reversible protonic motion in Si/SiO 2 /Si structures makes this an exemplar system to explore the physics and chemistry of hydrogen in the technologically relevant Si/SiO 2 structure. In this work, they illustrate that this effect can be used as the basis for a programmable nonvolatile field effect transistor (NVFET) memory that may compete with other Si-based memory devices. The power of this novel device is its simplicity; it is based upon standard Si/SiO 2 /Si technology and forming gas annealing, a common treatment used in integrated circuit processing. They also briefly discuss the effects of radiation on its retention properties

  3. Atomic crystals resistive switching memory

    International Nuclear Information System (INIS)

    Liu Chunsen; Zhang David Wei; Zhou Peng

    2017-01-01

    Facing the growing data storage and computing demands, a high accessing speed memory with low power and non-volatile character is urgently needed. Resistive access random memory with 4F 2 cell size, switching in sub-nanosecond, cycling endurances of over 10 12 cycles, and information retention exceeding 10 years, is considered as promising next-generation non-volatile memory. However, the energy per bit is still too high to compete against static random access memory and dynamic random access memory. The sneak leakage path and metal film sheet resistance issues hinder the further scaling down. The variation of resistance between different devices and even various cycles in the same device, hold resistive access random memory back from commercialization. The emerging of atomic crystals, possessing fine interface without dangling bonds in low dimension, can provide atomic level solutions for the obsessional issues. Moreover, the unique properties of atomic crystals also enable new type resistive switching memories, which provide a brand-new direction for the resistive access random memory. (topical reviews)

  4. Spurious dispersion effects at FLASH

    International Nuclear Information System (INIS)

    Prat, Eduard

    2009-07-01

    The performance of the Free-Electron Laser (FEL) process imposes stringent demands on the transverse trajectory and size of the electron beam. Since transverse dispersion changes off-energy particle trajectories and increases the effective beam size, dispersion must be controlled. This thesis treats the concept of dispersion in linacs, and analyses the impact of dispersion on the electron beam and on the FEL process. It presents generation mechanisms for spurious dispersion, quantifying its importance for FLASH (Free-electron Laser in Hamburg) and the XFEL (European X-ray Free-Electron Laser). A method for measuring and correcting dispersion and its implementation in FLASH is described. Experiments of dispersion e ects on the transverse beam quality and on the FEL performance are presented. (orig.)

  5. Flash x-ray cinematography

    International Nuclear Information System (INIS)

    Stein, W.E.

    1976-01-01

    Experiments intended to provide an overview of the potential capabilities and limitations of flash x-ray cinematography as a diagnostic technique for a Fast Reactor Safety Test Facility are described. The results provide estimates of the x-ray pulse intensity required to obtain adequate radiographs of an array of fuel pins in a typical reactor configuration. An estimate of the upper limit on the pulse duration imposed by the reactor background radiation was also determined. X-ray cinematography has been demonstrated at a repetition rate limited only by the recording equipment on hand at the time of these measurements. These preliminary results indicate that flash x-ray cinematography of the motion of fuel in a Fast Reactor Test Facility is technically feasible

  6. Spurious dispersion effects at FLASH

    Energy Technology Data Exchange (ETDEWEB)

    Prat, Eduard

    2009-07-15

    The performance of the Free-Electron Laser (FEL) process imposes stringent demands on the transverse trajectory and size of the electron beam. Since transverse dispersion changes off-energy particle trajectories and increases the effective beam size, dispersion must be controlled. This thesis treats the concept of dispersion in linacs, and analyses the impact of dispersion on the electron beam and on the FEL process. It presents generation mechanisms for spurious dispersion, quantifying its importance for FLASH (Free-electron Laser in Hamburg) and the XFEL (European X-ray Free-Electron Laser). A method for measuring and correcting dispersion and its implementation in FLASH is described. Experiments of dispersion e ects on the transverse beam quality and on the FEL performance are presented. (orig.)

  7. Magnetic vortex racetrack memory

    Science.gov (United States)

    Geng, Liwei D.; Jin, Yongmei M.

    2017-02-01

    We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

  8. Hot flashes and sleep in women.

    Science.gov (United States)

    Moe, Karen E

    2004-12-01

    Sleep disturbances during menopause are often attributed to nocturnal hot flashes and 'sweats' associated with changing hormone patterns. This paper is a comprehensive critical review of the research on the relationship between sleep disturbance and hot flashes in women. Numerous studies have found a relationship between self-reported hot flashes and sleep complaints. However, hot flash studies using objective sleep assessment techniques such as polysomnography, actigraphy, or quantitative analysis of the sleep EEG are surprisingly scarce and have yielded somewhat mixed results. Much of this limited evidence suggests that hot flashes are associated with objectively identified sleep disruption in at least some women. At least some of the negative data may be due to methodological issues such as reliance upon problematic self-reports of nocturnal hot flashes and a lack of concurrent measures of hot flashes and sleep. The recent development of a reliable and non-intrusive method for objectively identifying hot flashes during the night should help address the need for substantial additional research in this area. Several areas of clinical relevance are described, including the effects of discontinuing combined hormone therapy (estrogen plus progesterone) or estrogen-only therapy, the possibility of hot flashes continuing for many years after menopause, and the link between hot flashes and depression.

  9. Fast Magnetoresistive Random-Access Memory

    Science.gov (United States)

    Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

    1991-01-01

    Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

  10. Doped SbTe phase change material in memory cells

    NARCIS (Netherlands)

    in ‘t Zandt, M.A.A.; Jedema, F.J.; Gravesteijn, Dirk J; Gravesteijn, D.J.; Attenborough, K.; Wolters, Robertus A.M.

    2009-01-01

    Phase Change Random Access Memory (PCRAM) is investigated as replacement for Flash. The memory concept is based on switching a chalcogenide from the crystalline (low ohmic) to the amorphous (high ohmic) state and vice versa. Basically two memory cell concepts exist: the Ovonic Unified Memory (OUM)

  11. Flexible NAND-Like Organic Ferroelectric Memory Array

    NARCIS (Netherlands)

    Kam, B.; Ke, T.H.; Chasin, A.; Tyagi, M.; Cristoferi, C.; Tempelaars, K.; Breemen, A.J.J.M. van; Myny, K.; Schols, S.; Genoe, J.; Gelinck, G.H.; Heremans, P.

    2014-01-01

    We present a memory array of organic ferroelectric field-effect transistors (OFeFETs) on flexible substrates. The OFeFETs are connected serially, similar to the NAND architecture of flash memory, which offers the highest memory density of transistor memories. We demonstrate a reliable addressing

  12. Evaluation of Flash Bainite in 4130 Steel

    Science.gov (United States)

    2011-07-01

    Technical Report ARWSB-TR-11011 Evaluation of Flash Bainite in 4130 Steel G. Vigilante M. Hespos S. Bartolucci...4. TITLE AND SUBTITLE Evaluation of Flash Bainite in 4130 Steel 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT...need to be addressed, the Flash Bainite processing of 4130 steel demonstrates promise for applications needing a combination of high strength with

  13. Construction and performance of large flash chambers

    International Nuclear Information System (INIS)

    Taylor, F.E.; Bogert, D.; Fisk, R.; Stutte, L.; Walker, J.K.; Wolfson, J.; Abolins, M.; Ernwein, J.; Owen, D.; Lyons, T.

    1979-01-01

    The construction and performance of 12' x 12' flash chambers used in a 340 ton neutrino detector under construction at Fermilab is described. The flash chambers supply digital information with a spatial resolution of 0.2'', and are used to finely sample the shower development of the reaction products of neutrino interactions. The flash chambers are easy and inexpensive to build and are electronically read out

  14. Menopausal Hot Flashes and White Matter Hyperintensities

    Science.gov (United States)

    Thurston, Rebecca C.; Aizenstein, Howard J.; Derby, Carol A.; Sejdić, Ervin; Maki, Pauline M.

    2015-01-01

    Objective Hot flashes are the classic menopausal symptom. Emerging data links hot flashes to cardiovascular disease (CVD) risk, yet how hot flashes are related to brain health is poorly understood. We examined the relationship between hot flashes - measured via physiologic monitor and self-report - and white matter hyperintensities (WMH) among midlife women. Methods Twenty midlife women ages 40-60 without clinical CVD, with their uterus and both ovaries, and not taking hormone therapy were recruited. Women underwent 24 hours of ambulatory physiologic and diary hot flash monitoring to quantify hot flashes; magnetic resonance imaging to assess WMH burden; 72 hours of actigraphy and questionnaires to quantify sleep; and a blood draw, questionnaires, and physical measures to quantify demographics and CVD risk factors. Test of a priori hypotheses regarding relations between physiologically-monitored and self-reported wake and sleep hot flashes and WMH were conducted in linear regression models. Results More physiologically-monitored hot flashes during sleep were associated with greater WMH, controlling for age, race, and body mass index [beta(standard error)=.0002 (.0001), p=.03]. Findings persisted controlling for sleep characteristics and additional CVD risk factors. No relations were observed for self-reported hot flashes. Conclusions More physiologically-monitored hot flashes during sleep were associated with greater WMH burden among midlife women free of clinical CVD. Results suggest that relations between hot flashes and CVD risk observed in the periphery may extend to the brain. Future work should consider the unique role of sleep hot flashes in brain health. PMID:26057822

  15. Modelling and mitigation of Flash Crashes

    OpenAIRE

    Fry, John; Serbera, Jean-Philippe

    2017-01-01

    The algorithmic trading revolution has had a dramatic effect upon markets. Trading has become faster, and in some ways more efficient, though potentially at the cost higher volatility and increased uncertainty. Stories of predatory trading and flash crashes constitute a new financial reality. Worryingly, highly capitalised stocks may be particularly vulnerable to flash crashes. Amid fears of high-risk technology failures in the global financial system we develop a model for flash crashes....

  16. A study on electromechanical carbon nanotube memory devices

    International Nuclear Information System (INIS)

    Kang, Jeong Won; Hwang, Ho Jung

    2005-01-01

    Electromechanical operations of carbon-nanotube (CNT) bridge memory device were investigated by using atomistic simulations based on empirical potentials. The nanotube-bridge memory device was operated by the electrostatic and the van der Waals forces acting on the nanotube-bridge. For the CNT bridge memory device, the van der Waals interactions between the CNT bridge and the oxide were very important. As the distance between the CNT bridge and the oxide decreased and the van der Waals interaction energy increased, the pull-in bias of the CNT-bridge decreased and the nonvolatility of the nanotube-bridge memory device increased, while the pull-out voltages increased. When the materials composed of the oxide film are different, since the van der Waals interactions must be also different, the oxide materials must be carefully selected for the CNT-bridge memory device to work as a nonvolatile memory.

  17. Flash CS5 The Missing Manual

    CERN Document Server

    Grover, Chris

    2010-01-01

    Once you know how to use Flash, you can create everything from simple animations to high-end desktop applications, but it's a complex tool that can be difficult to master on your own-unless you have this Missing Manual. This book will help you learn all you need to know about Flash CS5 to create animations that bring your ideas to life. Learn animation basics. Find everything you need to know to get started with FlashMaster the Flash tools. Learn the animation and effects toolset, with clear explanations and hands-on examplesUse 3D effects. Rotate and put objects in motion in three dimensions

  18. Search Engine Optimization for Flash Best Practices for Using Flash on the Web

    CERN Document Server

    Perkins, Todd

    2009-01-01

    Search Engine Optimization for Flash dispels the myth that Flash-based websites won't show up in a web search by demonstrating exactly what you can do to make your site fully searchable -- no matter how much Flash it contains. You'll learn best practices for using HTML, CSS and JavaScript, as well as SWFObject, for building sites with Flash that will stand tall in search rankings.

  19. The haptic and the visual flash-lag effect and the role of flash characteristics.

    Directory of Open Access Journals (Sweden)

    Knut Drewing

    Full Text Available When a short flash occurs in spatial alignment with a moving object, the moving object is seen ahead the stationary one. Similar to this visual "flash-lag effect" (FLE it has been recently observed for the haptic sense that participants judge a moving hand to be ahead a stationary hand when judged at the moment of a short vibration ("haptic flash" that is applied when the two hands are spatially aligned. We further investigated the haptic FLE. First, we compared participants' performance in two isosensory visual or haptic conditions, in which moving object and flash were presented only in a single modality (visual: sphere and short color change, haptic: hand and vibration, and two bisensory conditions, in which the moving object was presented in both modalities (hand aligned with visible sphere, but the flash was presented only visually or only haptically. The experiment aimed to disentangle contributions of the flash's and the objects' modalities to the FLEs in haptics versus vision. We observed a FLE when the flash was visually displayed, both when the moving object was visual and visuo-haptic. Because the position of a visual flash, but not of an analogue haptic flash, is misjudged relative to a same visuo-haptic moving object, the difference between visual and haptic conditions can be fully attributed to characteristics of the flash. The second experiment confirmed that a haptic FLE can be observed depending on flash characteristics: the FLE increases with decreasing intensity of the flash (slightly modulated by flash duration, which had been previously observed for vision. These findings underline the high relevance of flash characteristics in different senses, and thus fit well with the temporal-sampling framework, where the flash triggers a high-level, supra-modal process of position judgement, the time point of which further depends on the processing time of the flash.

  20. Spatial correlation of conductive filaments for multiple switching cycles in CBRAM

    KAUST Repository

    Pey, K. L.; Raghavan, N.; Wu, X.; Bosman, M.; Zhang, Xixiang; Li, Kun

    2014-01-01

    Conducting bridge random access memory (CBRAM) is one of the potential technologies being considered for replacement of Flash memory for non-volatile data storage. CBRAM devices operate on the principle of nucleation and rupture of metallic

  1. Rh-flash acquisition card

    International Nuclear Information System (INIS)

    Bourrion, O.

    2003-01-01

    The rh-flash card main purpose is to convert and store the image of the analog data present at input into an output buffer, namely in a given timing window besides a stop signal (like a digital oscilloscope). It is conceived in VME format 1U wide with an additional connector. Novelty of this card is its ability to sample at a high frequency, due to flash coders, and this at a high repetition rate. To do that the card allows the storage of the data considered 'useful' and that is done by storing only the data exceeding a certain threshold. This can be useful for instance for viewing peaks in a spectrum, and obtaining their relative location. The goal is to stock and process the data sampled before and after the arrival of a stop signal (what entails a storage depth). A threshold is defined and any peak exceeding its level will really be stored in the output buffer which is readable through the VME bus. The peak values will be stored as well as m preceding and n subsequent values (both programmable). Obviously, if the threshold is zero the system of data processing is off and all data will be stored. The document is structured on six sections titled: 1. Description; 2. Specifications; 3. Explaining the design of channels; 4. Explaining the shared part of the design; 5. Addressing (→ user guide); 6. Software precautions. (author)

  2. NO signatures from lightning flashes

    Science.gov (United States)

    Stith, J.; Dye, J.; Ridley, B.; Laroche, P.; Defer, E.; Baumann, K.; Hübler, G.; Zerr, R.; Venticinque, M.

    1999-07-01

    In situ measurements of cloud properties, NO, and other trace gases were made in active thunderstorms by two research aircraft. Concurrent measurements from a three-dimensional (3-D) VHF interferometer and the 2-D National Lightning Detection Network were used to determine lightning frequency and location. The CHILL Doppler radar and the NOAA-WP-3D Orion X band Doppler radar were also used to measure storm characteristics. Two case studies from the (STERAO) Stratosphere-Troposphere Experiments: Radiation, Aerosols, and Ozone project in northeastern Colorado during the summer of 1996 are presented. Narrow spikes (0.11-0.96 km across), containing up to 19 ppbv of NO, were observed in the storms. Most were located in or downwind of electrically active regions where the NO produced by lightning would be expected. However, it was difficult to correlate individual flashes with NO spikes. A simple model of the plume of NO from lightning is used to estimate NO production from the mean mixing ratio measured in these spikes. The estimates range from 2.0×1020 to 1.0×1022 molecules of NO per meter of flash length.

  3. Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

    Science.gov (United States)

    Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

    2015-09-01

    Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

  4. In Situ Transmission Electron Microscopy Observation of Nanostructural Changes in Phase-Change Memory

    KAUST Repository

    Meister, Stefan; Kim, SangBum; Cha, Judy J.; Wong, H.-S. Philip; Cui, Yi

    2011-01-01

    Phase-change memory (PCM) has been researched extensively as a promising alternative to flash memory. Important studies have focused on its scalability, switching speed, endurance, and new materials. Still, reliability issues and inconsistent

  5. uFlip: Understanding Flash IO Patterns

    DEFF Research Database (Denmark)

    Bouganim, Luc; Jonsson, Bjørn; Bonnet, Philippe

    2009-01-01

    want to establish what kind of IOs should be favored (or avoided) when designing algorithms and architectures for flash-based systems. In this paper, we focus on flash IO patterns, that capture relevant distribution of IOs in time and space, and our goal is to quantify their performance. We define uFLIP...

  6. Au Contraire: Gifted in a Flash (Mob)

    Science.gov (United States)

    Delisle, James R.

    2012-01-01

    A "flash mob" is defined by Wikipedia as "a large group of people who assemble suddenly in a public place, perform an unusual and pointless act for a brief time, then disperse." Fueled by social media and Smartphones, flash mobs have been used, primarily, as entertaining diversions by addicted techies with (apparently) tons of time on their hands.…

  7. FLASH Interface; a GUI for managing runtime parameters in FLASH simulations

    Science.gov (United States)

    Walker, Christopher; Tzeferacos, Petros; Weide, Klaus; Lamb, Donald; Flocke, Norbert; Feister, Scott

    2017-10-01

    We present FLASH Interface, a novel graphical user interface (GUI) for managing runtime parameters in simulations performed with the FLASH code. FLASH Interface supports full text search of available parameters; provides descriptions of each parameter's role and function; allows for the filtering of parameters based on categories; performs input validation; and maintains all comments and non-parameter information already present in existing parameter files. The GUI can be used to edit existing parameter files or generate new ones. FLASH Interface is open source and was implemented with the Electron framework, making it available on Mac OSX, Windows, and Linux operating systems. The new interface lowers the entry barrier for new FLASH users and provides an easy-to-use tool for experienced FLASH simulators. U.S. Department of Energy (DOE), NNSA ASC/Alliances Center for Astrophysical Thermonuclear Flashes, U.S. DOE NNSA ASC through the Argonne Institute for Computing in Science, U.S. National Science Foundation.

  8. Organic flash cycles for efficient power production

    Science.gov (United States)

    Ho, Tony; Mao, Samuel S.; Greif, Ralph

    2016-03-15

    This disclosure provides systems, methods, and apparatus related to an Organic Flash Cycle (OFC). In one aspect, a modified OFC system includes a pump, a heat exchanger, a flash evaporator, a high pressure turbine, a throttling valve, a mixer, a low pressure turbine, and a condenser. The heat exchanger is coupled to an outlet of the pump. The flash evaporator is coupled to an outlet of the heat exchanger. The high pressure turbine is coupled to a vapor outlet of the flash evaporator. The throttling valve is coupled to a liquid outlet of the flash evaporator. The mixer is coupled to an outlet of the throttling valve and to an outlet of the high pressure turbine. The low pressure turbine is coupled to an outlet of the mixer. The condenser is coupled to an outlet of the low pressure turbine and to an inlet of the pump.

  9. Intégration de matériaux à forte permittivité électrique (High-k) dans les mémoires non-volatiles pour les générations sub-45nm

    OpenAIRE

    Bocquet , Marc

    2009-01-01

    Flash memory is today a major element for the development of the portable electronics which require more and more memory capability at low cost (netbook, cell phones, PDA, USB sticks...). In order to maintain it for the years to come, it is necessary to continue improving this technology. Also, the integration of High-k materials and the use of trap charge memories are strongly envisaged. This PhD focuses on the integration and the electrical study (fixed charge, trapping, leakage currents......

  10. Carbon nanotube network-silicon oxide non-volatile switches.

    Science.gov (United States)

    Liao, Albert D; Araujo, Paulo T; Xu, Runjie; Dresselhaus, Mildred S

    2014-12-08

    The integration of carbon nanotubes with silicon is important for their incorporation into next-generation nano-electronics. Here we demonstrate a non-volatile switch that utilizes carbon nanotube networks to electrically contact a conductive nanocrystal silicon filament in silicon dioxide. We form this device by biasing a nanotube network until it physically breaks in vacuum, creating the conductive silicon filament connected across a small nano-gap. From Raman spectroscopy, we observe coalescence of nanotubes during breakdown, which stabilizes the system to form very small gaps in the network~15 nm. We report that carbon nanotubes themselves are involved in switching the device to a high resistive state. Calculations reveal that this switching event occurs at ~600 °C, the temperature associated with the oxidation of nanotubes. Therefore, we propose that, in switching to a resistive state, the nanotube oxidizes by extracting oxygen from the substrate.

  11. Apple juice composition: sugar, nonvolatile acid, and phenolic profiles.

    Science.gov (United States)

    Lee, H S; Wrolstad, R E

    1988-01-01

    Apples from Michigan, Washington, Argentina, Mexico, and New Zealand were processed into juice; the 8 samples included Golden Delicious, Jonathan, Granny Smith, and McIntosh varieties. Liquid chromatography was used for quantitation of sugars (glucose, fructose, sucrose, and sorbitol), nonvolatile acids (malic, quinic, citric, shikimic, and fumaric), and phenolics (chlorogenic acid and hydroxymethylfurfural [HMF]). Other determinations included pH, 0Brix, and L-malic acid. A number of compositional indices for these authentic juices, e.g., chlorogenic acid content, total malic - L-malic difference, and the HMF:chlorogenic ratio, were at variance with recommended standards. The phenolic profile was shown to be particularly influenced by gelatin fining, with peak areas decreasing by as much as 50%. The L-malic:total malic ratio serves as a better index for presence of synthetic malic acid than does the difference between the 2 determinations. No apparent differences in chemical composition could be attributed to geographic origin.

  12. Non-volatile polarization switch of magnetic domain wall velocity

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Z.; Stolichnov, I.; Setter, N. [Ceramics Laboratory, EPFL-Swiss Federal Institute of Technology, Lausanne 1015 (Switzerland); Bernand-Mantel, A.; Schott, Marine; Pizzini, S.; Ranno, L. [University of Grenoble Alpes, Institut Néel, F-38042 Grenoble (France); CNRS, Institut Néel, F-38042 Grenoble (France); Auffret, S.; Gaudin, G. [SPINTEC, UMR-8191, CEA/CNRS/UJF/GINP, INAC, F-38054 Grenoble (France)

    2015-12-21

    Controlled propagation speed of individual magnetic domains in metal channels at the room temperature is obtained via the non-volatile field effect associated with the switchable polarization of P(VDF-TrFE) (polyvinylidene fluoride-trifluoroethylene) ferroelectric polymer. Polarization domains directly written using conducting atomic force microscope probe locally accelerate/decelerate the magnetic domains in the 0.6 nm thick Co film. The change of the magnetic domain wall velocity is consistent with the magnetic anisotropy energy modulation through the polarization upward/downward orientation. Excellent retention is observed. The demonstrated local non-destructive and reversible change of magnetic properties via rewritable patterning of ferroelectric domains could be attractive for exploring the ultimate limit of miniaturization in devices based on ferromagnetic/ferroelectric bilayers.

  13. Terrestrial gamma-ray flashes

    Science.gov (United States)

    Marisaldi, Martino; Fuschino, Fabio; Labanti, Claudio; Tavani, Marco; Argan, Andrea; Del Monte, Ettore; Longo, Francesco; Barbiellini, Guido; Giuliani, Andrea; Trois, Alessio; Bulgarelli, Andrea; Gianotti, Fulvio; Trifoglio, Massimo

    2013-08-01

    Lightning and thunderstorm systems in general have been recently recognized as powerful particle accelerators, capable of producing electrons, positrons, gamma-rays and neutrons with energies as high as several tens of MeV. In fact, these natural systems turn out to be the highest energy and most efficient natural particle accelerators on Earth. Terrestrial Gamma-ray Flashes (TGFs) are millisecond long, very intense bursts of gamma-rays and are one of the most intriguing manifestation of these natural accelerators. Only three currently operative missions are capable of detecting TGFs from space: the RHESSI, Fermi and AGILE satellites. In this paper we review the characteristics of TGFs, including energy spectrum, timing structure, beam geometry and correlation with lightning, and the basic principles of the associated production models. Then we focus on the recent AGILE discoveries concerning the high energy extension of the TGF spectrum up to 100 MeV, which is difficult to reconcile with current theoretical models.

  14. Terrestrial gamma-ray flashes

    International Nuclear Information System (INIS)

    Marisaldi, Martino; Fuschino, Fabio; Labanti, Claudio; Tavani, Marco; Argan, Andrea; Del Monte, Ettore; Longo, Francesco; Barbiellini, Guido; Giuliani, Andrea; Trois, Alessio; Bulgarelli, Andrea; Gianotti, Fulvio; Trifoglio, Massimo

    2013-01-01

    Lightning and thunderstorm systems in general have been recently recognized as powerful particle accelerators, capable of producing electrons, positrons, gamma-rays and neutrons with energies as high as several tens of MeV. In fact, these natural systems turn out to be the highest energy and most efficient natural particle accelerators on Earth. Terrestrial Gamma-ray Flashes (TGFs) are millisecond long, very intense bursts of gamma-rays and are one of the most intriguing manifestation of these natural accelerators. Only three currently operative missions are capable of detecting TGFs from space: the RHESSI, Fermi and AGILE satellites. In this paper we review the characteristics of TGFs, including energy spectrum, timing structure, beam geometry and correlation with lightning, and the basic principles of the associated production models. Then we focus on the recent AGILE discoveries concerning the high energy extension of the TGF spectrum up to 100 MeV, which is difficult to reconcile with current theoretical models

  15. EEHG at FLASH and DELTA

    Energy Technology Data Exchange (ETDEWEB)

    Molo, Robert; Hoener, Markus; Huck, Holger; Hacker, Kirsten; Khan, Shaukat; Schick, Andreas; Ungelenk, Peter; Zeinalzadeh, Maryam [Center for Synchrotron Radiation (DELTA), TU Dortmund University (Germany); Meulen, Peter van der; Salen, Peter [Stockholm University (Sweden); Angelova Hamberg, Gergana; Ziemann, Volker [Uppsala University (Sweden)

    2013-07-01

    The echo-enabled harmonic generation (EEHG) scheme utilizes two modulators with two magnetic chicanes in order to generate an electron density modulation with high harmonic content. In contrast to free-electron lasers (FEL) based on self-amplified spontaneous emission (SASE), the radiation of an EEHG FEL has better longitudinal coherence and is naturally synchronized with an external laser, which is advantageous for pump-probe applications. At the free-electron laser in Hamburg (FLASH), an EEHG experiment is currently under preparation. The short-pulse facility at DELTA (a 1.5-GeV synchrotron light source operated by the TU Dortmund University) based on coherent harmonic generation (CHG) will be upgraded using the EEHG technique in order to reach shorter wavelengths.

  16. [Nikola Tesla: flashes of inspiration].

    Science.gov (United States)

    Villarejo-Galende, Albero; Herrero-San Martín, Alejandro

    2013-01-16

    Nikola Tesla (1856-1943) was one of the greatest inventors in history and a key player in the revolution that led to the large-scale use of electricity. He also made important contributions to such diverse fields as x-rays, remote control, radio, the theory of consciousness or electromagnetism. In his honour, the international unit of magnetic induction was named after him. Yet, his fame is scarce in comparison with that of other inventors of the time, such as Edison, with whom he had several heated arguments. He was a rather odd, reserved person who lived for his inventions, the ideas for which came to him in moments of inspiration. In his autobiography he relates these flashes with a number of neuropsychiatric manifestations, which can be seen to include migraine auras, synaesthesiae, obsessions and compulsions.

  17. Statistical Evolution of the Lightning Flash

    Science.gov (United States)

    Zoghzoghy, F. G.; Cohen, M.; Said, R.; Inan, U. S.

    2012-12-01

    Natural lightning is one of the most fascinating and powerful electrical processes on Earth. To date, the physics behind this natural phenomenon are not fully understood, due primarily to the difficulty of obtaining measurements inside thunderstorms and to the wide range of timescales involved (from nanoseconds to seconds). Our aim is to use accurate lightning geo-location data from the National Lightning Detection Network (NLDN) to study statistical patterns in lightning, taking advantage of the fact that millions of lightning flashes occur around the globe every day. We present two sets of results, one involving the patterns of flashes in a storm, and a second involving the patterns of strokes in a flash. These patterns can provide a surrogate measure of the timescales and the spatial extents of the underlying physical processes. First, we study the timescales of charge buildup inside thunderstorms. We find that, following a lightning flash, the probability of another neighboring flash decreases and takes tens of seconds to recover. We find that this suppression effect is a function of flash type, stroke peak current, cloud-to-ground (CG) stroke multiplicity, and other lightning and geographical parameters. We find that the probabilities of subsequent flashes are more suppressed following oceanic lightning, or following flashes with higher peak currents and/or higher multiplicities (for CG flashes). Second, we use NLDN data to study the evolution of the strokes within a CG flash. A CG flash typically includes multiple return strokes, which can occur in the same channel or in multiple channels within a few kilometers. We cluster NLDN stroke data into flashes and produce the probability density function of subsequent strokes as a function of distance and time-delays relative to the previous stroke. Using this technique, we investigate processes which occur during the CG lightning flash with nanosecond to millisecond timescales. For instance, our results suggest

  18. Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

    Science.gov (United States)

    Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

    2016-02-24

    Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Next generation spin torque memories

    CERN Document Server

    Kaushik, Brajesh Kumar; Kulkarni, Anant Aravind; Prajapati, Sanjay

    2017-01-01

    This book offers detailed insights into spin transfer torque (STT) based devices, circuits and memories. Starting with the basic concepts and device physics, it then addresses advanced STT applications and discusses the outlook for this cutting-edge technology. It also describes the architectures, performance parameters, fabrication, and the prospects of STT based devices. Further, moving from the device to the system perspective it presents a non-volatile computing architecture composed of STT based magneto-resistive and all-spin logic devices and demonstrates that efficient STT based magneto-resistive and all-spin logic devices can turn the dream of instant on/off non-volatile computing into reality.

  20. Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

    NARCIS (Netherlands)

    Cai, R.; Kassa, H.G.; Haouari, R.; Marrani, A.; Geerts, Y.H.; Ruzié, C.; Breemen, A.J.J.M. van; Gelinck, G.H.; Nysten, B.; Hu, Z.; Jonas, A.M.

    2016-01-01

    Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and

  1. MR colonography with fecal tagging: comparison between 2D turbo FLASH and 3D FLASH sequences

    International Nuclear Information System (INIS)

    Papanikolaou, Nickolas; Grammatikakis, John; Maris, Thomas; Prassopoulos, Panos; Gourtsoyiannis, Nicholas; Lauenstein, Thomas

    2003-01-01

    The objective of this study was to compare inversion recovery turbo 2D fast low-angle shot (FLASH) and 3D FLASH sequences for fecal-tagged MR colonography studies. Fifteen consecutive patients with indications for colonoscopy underwent MR colonography with fecal tagging. An inversion recovery turbo-FLASH sequence was applied and compared in terms of artifacts presence, efficiency for masking residual stool, and colonic wall conspicuity with a fat-saturated 3D FLASH sequence. Both sequences were acquired following administration of paramagnetic contrast agent. Contrast-to-noise ratio and relative contrast between colonic wall and lumen were calculated and compared for both sequences. Turbo 2D FLASH provided fewer artifacts, higher efficiency for masking the residual stool, and colonic wall conspicuity equivalent to 3D FLASH. An inversion time of 10 ms provided homogeneously low signal intensity of the colonic lumen. Contrast to noise between colonic wall and lumen was significantly higher in the 3D FLASH images, whereas differences in relative contrast were not statistically significant. An optimized inversion-recovery 2D turbo-FLASH sequence provides better fecal tagging results and should be added to the 3D FLASH sequence when designing dark-lumen MR colonography examination protocols. (orig.)

  2. A global flash flood forecasting system

    Science.gov (United States)

    Baugh, Calum; Pappenberger, Florian; Wetterhall, Fredrik; Hewson, Tim; Zsoter, Ervin

    2016-04-01

    The sudden and devastating nature of flash flood events means it is imperative to provide early warnings such as those derived from Numerical Weather Prediction (NWP) forecasts. Currently such systems exist on basin, national and continental scales in Europe, North America and Australia but rely on high resolution NWP forecasts or rainfall-radar nowcasting, neither of which have global coverage. To produce global flash flood forecasts this work investigates the possibility of using forecasts from a global NWP system. In particular we: (i) discuss how global NWP can be used for flash flood forecasting and discuss strengths and weaknesses; (ii) demonstrate how a robust evaluation can be performed given the rarity of the event; (iii) highlight the challenges and opportunities in communicating flash flood uncertainty to decision makers; and (iv) explore future developments which would significantly improve global flash flood forecasting. The proposed forecast system uses ensemble surface runoff forecasts from the ECMWF H-TESSEL land surface scheme. A flash flood index is generated using the ERIC (Enhanced Runoff Index based on Climatology) methodology [Raynaud et al., 2014]. This global methodology is applied to a series of flash floods across southern Europe. Results from the system are compared against warnings produced using the higher resolution COSMO-LEPS limited area model. The global system is evaluated by comparing forecasted warning locations against a flash flood database of media reports created in partnership with floodlist.com. To deal with the lack of objectivity in media reports we carefully assess the suitability of different skill scores and apply spatial uncertainty thresholds to the observations. To communicate the uncertainties of the flash flood system output we experiment with a dynamic region-growing algorithm. This automatically clusters regions of similar return period exceedence probabilities, thus presenting the at-risk areas at a spatial

  3. Mass transfer of nonvolatile organic compounds from porous media

    Science.gov (United States)

    Khachikian, Crist Simon

    This thesis presents data pertaining to the mass transfer of nonvolatile organic compounds from porous media. Physical properties of porous solids, including surface and pore areas, are studied. Information from these studies, along with dissolution data, are used to develop correlations relating the Sherwood Number to the Peclet Number. The contaminant used in this study is naphthalene; the solids used are Moffett Sand (MS), Borden Sand (BS), Lampblack (LB), and Silica Gel (SG). Surface area results indicate that contamination at 0.1% reduces the area of MS and SG by 48 and 37%, respectively, while contamination at 1.0% reduces the area of MS, BS, and SG by 59, 56, and 40%, respectively. Most of the reduction in area originates in the reduction of pore areas and volumes, where the contaminant precipitates. After long-term storage, surface areas did not recover to their original values due to an "irreversible" fraction of naphthalene. Treatment with heat or solvent or both was necessary to completely remove the contamination. For lampblack, treatment at 100°C decreased areas while treatment at 250°C increased them. Treatment at 250°°C probably opened pores while that at 100°C may have blocked more pores by redistributing the tar-like contaminant characteristic of lampblack. Contaminated MS and SG solids are packed in columns through which water is pumped. The effluent began at a relatively high concentration (˜70% of solubility) for both samples. However, SG column concentrations dropped quickly, never achieving steady state while the MS samples declined more gradually towards steady state. The high pore areas of the SG samples are believed to cause this behavior. The steady state portion of the MS dissolution history is used to develop mass transfer correlations. The correlation in this study differs from previous work in two major ways: (1) the exponent on the Pe is three times larger and (2) the limiting Sh is 106 times smaller. These results suggest that

  4. From silicon to organic nanoparticle memory devices.

    Science.gov (United States)

    Tsoukalas, D

    2009-10-28

    After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

  5. Flash spectroscopy of purple membrane.

    Science.gov (United States)

    Xie, A H; Nagle, J F; Lozier, R H

    1987-04-01

    Flash spectroscopy data were obtained for purple membrane fragments at pH 5, 7, and 9 for seven temperatures from 5 degrees to 35 degrees C, at the magic angle for actinic versus measuring beam polarizations, at fifteen wavelengths from 380 to 700 nm, and for about five decades of time from 1 microsecond to completion of the photocycle. Signal-to-noise ratios are as high as 500. Systematic errors involving beam geometries, light scattering, absorption flattening, photoselection, temperature fluctuations, partial dark adaptation of the sample, unwanted actinic effects, and cooperativity were eliminated, compensated for, or are shown to be irrelevant for the conclusions. Using nonlinear least squares techniques, all data at one temperature and one pH were fitted to sums of exponential decays, which is the form required if the system obeys conventional first-order kinetics. The rate constants obtained have well behaved Arrhenius plots. Analysis of the residual errors of the fitting shows that seven exponentials are required to fit the data to the accuracy of the noise level.

  6. Improving Flash Flood Prediction in Multiple Environments

    Science.gov (United States)

    Broxton, P. D.; Troch, P. A.; Schaffner, M.; Unkrich, C.; Goodrich, D.; Wagener, T.; Yatheendradas, S.

    2009-12-01

    Flash flooding is a major concern in many fast responding headwater catchments . There are many efforts to model and to predict these flood events, though it is not currently possible to adequately predict the nature of flash flood events with a single model, and furthermore, many of these efforts do not even consider snow, which can, by itself, or in combination with rainfall events, cause destructive floods. The current research is aimed at broadening the applicability of flash flood modeling. Specifically, we will take a state of the art flash flood model that is designed to work with warm season precipitation in arid environments, the KINematic runoff and EROSion model (KINEROS2), and combine it with a continuous subsurface flow model and an energy balance snow model. This should improve its predictive capacity in humid environments where lateral subsurface flow significantly contributes to streamflow, and it will make possible the prediction of flooding events that involve rain-on-snow or rapid snowmelt. By modeling changes in the hydrologic state of a catchment before a flood begins, we can also better understand the factors or combination of factors that are necessary to produce large floods. Broadening the applicability of an already state of the art flash flood model, such as KINEROS2, is logical because flash floods can occur in all types of environments, and it may lead to better predictions, which are necessary to preserve life and property.

  7. Magnetic vortex racetrack memory

    Energy Technology Data Exchange (ETDEWEB)

    Geng, Liwei D.; Jin, Yongmei M., E-mail: ymjin@mtu.edu

    2017-02-01

    We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications. - Highlights: • Advance fundamental knowledge of current-driven magnetic vortex phenomena. • Report appealing new magnetic racetrack memory based on current-controlled magnetic vortices in nanowires. • Provide a novel approach to adjust current magnitude for data propagation. • Overcome the limitations of domain wall racetrack memory.

  8. Improved charge trapping flash device with Al2O3/HfSiO stack as blocking layer

    International Nuclear Information System (INIS)

    Zheng Zhi-Wei; Huo Zong-Liang; Zhu Chen-Xin; Xu Zhong-Guang; Liu Jing; Liu Ming

    2011-01-01

    In this paper, we investigate an Al 2 O 3 /HfSiO stack as the blocking layer of a metal—oxide—nitride—oxide—silicon-type (MONOS) memory capacitor. Compared with a memory capacitor with a single HfSiO layer as the blocking layer or an Al 2 O 3 /HfO 2 stack as the blocking layer, the sample with the Al 2 O 3 /HfSiO stack as the blocking layer shows high program/erase (P/E) speed and good data retention characteristics. These improved performances can be explained by energy band engineering. The experimental results demonstrate that the memory device with an Al 2 O 3 /HfSiO stack as the blocking layer has great potential for further high-performance nonvolatile memory applications. (interdisciplinary physics and related areas of science and technology)

  9. Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

    Science.gov (United States)

    Sakaki, Yukiya; Yamada, Tomoaki; Matsui, Chihiro; Yamaga, Yusuke; Takeuchi, Ken

    2018-04-01

    In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with two-dimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

  10. Large non-volatile tuning of magnetism mediated by electric field in Fe–Al/Pb(Mg1/3Nb2/3)O3–PbTiO3 heterostructure

    International Nuclear Information System (INIS)

    Chen, Zhendong; Gao, Cunxu; Wei, Yanping; Zhang, Peng; Wang, Yutian; Zhang, Chao; Ma, Zhikun

    2017-01-01

    Electric-field control of magnetism is now an attractive trend to approach a new kind of fast, low-power-cost memory device. In this work, we report a strong non-volatile electric control of magnetism in an Fe–Al/Pb(Mg 1/3 Nb 2/3 )O 3 –PbTiO 3 heterostructure. In this system, a 90° rotation of the in-plane uniaxial magnetic anisotropy is exhibited during the increase of the external electric field, which means the easy axis turns into a hard axis and the hard axis turns into an easy one. Additionally, a non-volatile switch of the remanence is observed after a sweeping of the electric field from 0 kV cm −1 to  ±  10 kV cm −1 , then back to 0 kV cm −1 . More interestingly, a 20% non-volatile magnetic state tuning driven by individual pulse electric fields is shown in contrast to large tuning up to 120% caused by pulse electric fields with small assistant pulse magnetic fields, which means a 180° reverse of the magnetization. These remarkable behaviors demonstrated in this heterostructure reveal a promising potential application in magnetic memory devices mediated by electric fields. (paper)

  11. Quantitative reconstruction of the nonvolatile sensometabolome of a red wine.

    Science.gov (United States)

    Hufnagel, Jan Carlos; Hofmann, Thomas

    2008-10-08

    The first comprehensive quantitative determination of 82 putative taste-active metabolites and mineral salts, the ranking of these compounds in their sensory impact based on dose-over-threshold (DoT) factors, followed by the confirmation of their sensory relevance by taste reconstruction and omission experiments enabled the decoding of the nonvolatile sensometabolome of a red wine. For the first time, the bitterness of the red wine could be demonstrated to be induced by subthreshold concentrations of phenolic acid ethyl esters and flavan-3-ols. Whereas the velvety astringent onset was imparted by three flavon-3-ol glucosides and dihydroflavon-3-ol rhamnosides, the puckering astringent offset was caused by a polymeric fraction exhibiting molecular masses above >5 kDa and was found to be amplified by the organic acids. The perceived sourness was imparted by l-tartaric acid, d-galacturonic acid, acetic acid, succinic acid, l-malic acid, and l-lactic acid and was slightly suppressed by the chlorides of potassium, magnesium, and ammonium, respectively. In addition, d-fructose and glycerol as well as subthreshold concentrations of glucose, 1,2-propandiol, and myo-inositol were found to be responsible for the sweetness, whereas the mouthfulness and body of the red wine were induced only by glycerol, 1,2-propandiol, and myo-inositol.

  12. Measuring hot flash phenomenonology using ambulatory prospective digital diaries

    Science.gov (United States)

    Fisher, William I.; Thurston, Rebecca C.

    2016-01-01

    Objective This study provides the description, protocol, and results from a novel prospective ambulatory digital hot flash phenomenon diary. Methods This study included 152 midlife women with daily hot flashes who completed an ambulatory electronic hot flash diary continuously for the waking hours of 3 consecutive days. In this diary, women recorded their hot flashes and accompanying characteristics and associations as the hot flashes occurred. Results Self-reported hot flash severity on the digital diaries indicated that the majority of hot flashes were rated as mild (41.3%) or moderate (43.7%). Severe (13.1%) and very severe (1.8%) hot flashes were less common. Hot flash bother ratings were rated as mild (43%), or moderate (33.5%), with fewer hot flashes reported bothersome (17.5%) or very bothersome (6%). The majority of hot flashes were reported as occurring on the on the face (78.9%), neck (74.7%), and chest (61.3%). Prickly skin was reported concurrently with 32% of hot flashes, 7% with anxiety and 5% with nausea. A novel finding, 38% of hot flashes were accompanied by a premonitory aura. Conclusion A prospective electronic digital hot flash diary allows for a more precise quantitation of hot flashes while overcoming many of the limitations of commonly employed retrospective questionnaires and paper diaries. Unique insights into the phenomenology, loci and associated characteristics of hot flashes were obtained using this device. The digital hot flash phenomenology diary is recommended for future ambulatory studies of hot flashes as a prospective measure of the hot flash experience. PMID:27404030

  13. Ferroelectric-gate field effect transistor memories device physics and applications

    CERN Document Server

    Ishiwara, Hiroshi; Okuyama, Masanori; Sakai, Shigeki; Yoon, Sung-Min

    2016-01-01

    This book provides comprehensive coverage of the materials characteristics, process technologies, and device operations for memory field-effect transistors employing inorganic or organic ferroelectric thin films. This transistor-type ferroelectric memory has interesting fundamental device physics and potentially large industrial impact. Among the various applications of ferroelectric thin films, the development of nonvolatile ferroelectric random access memory (FeRAM) has progressed most actively since the late 1980s and has achieved modest mass production levels for specific applications since 1995. There are two types of memory cells in ferroelectric nonvolatile memories. One is the capacitor-type FeRAM and the other is the field-effect transistor (FET)-type FeRAM. Although the FET-type FeRAM claims ultimate scalability and nondestructive readout characteristics, the capacitor-type FeRAMs have been the main interest for the major semiconductor memory companies, because the ferroelectric FET has fatal handic...

  14. Nonvolatile, semivolatile, or volatile: redefining volatile for volatile organic compounds.

    Science.gov (United States)

    Võ, Uyên-Uyén T; Morris, Michael P

    2014-06-01

    Although widely used in air quality regulatory frameworks, the term "volatile organic compound" (VOC) is poorly defined. Numerous standardized tests are currently used in regulations to determine VOC content (and thus volatility), but in many cases the tests do not agree with each other, nor do they always accurately represent actual evaporation rates under ambient conditions. The parameters (time, temperature, reference material, column polarity, etc.) used in the definitions and the associated test methods were created without a significant evaluation of volatilization characteristics in real world settings. Not only do these differences lead to varying VOC content results, but occasionally they conflict with one another. An ambient evaporation study of selected compounds and a few formulated products was conducted and the results were compared to several current VOC test methodologies: SCAQMD Method 313 (M313), ASTM Standard Test Method E 1868-10 (E1868), and US. EPA Reference Method 24 (M24). The ambient evaporation study showed a definite distinction between nonvolatile, semivolatile, and volatile compounds. Some low vapor pressure (LVP) solvents, currently considered exempt as VOCs by some methods, volatilize at ambient conditions nearly as rapidly as the traditional high-volatility solvents they are meant to replace. Conversely, bio-based and heavy hydrocarbons did not readily volatilize, though they often are calculated as VOCs in some traditional test methods. The study suggests that regulatory standards should be reevaluated to more accurately reflect real-world emission from the use of VOC containing products. The definition of VOC in current test methods may lead to regulations that exclude otherwise viable alternatives or allow substitutions of chemicals that may limit the environmental benefits sought in the regulation. A study was conducted to examine volatility of several compounds and a few formulated products under several current VOC test

  15. MAP Detector for Flash Memory Without Accessing the Interfering Cells

    DEFF Research Database (Denmark)

    Yassine, Hachem; Badiu, Mihai Alin; Coon, Justin P.

    2018-01-01

    the latency cost of accessing the interfering cells. Specifically, we exploit the fact that adjacent cells have common interferers by modeling the system as an appropriate hidden Markov model. Then we use the sum-product (message-passing) algorithm to compute the marginal posterior probabilities of the stored...

  16. A void distribution model-flashing flow

    International Nuclear Information System (INIS)

    Riznic, J.; Ishii, M.; Afgan, N.

    1987-01-01

    A new model for flashing flow based on wall nucleations is proposed here and the model predictions are compared with some experimental data. In order to calculate the bubble number density, the bubble number transport equation with a distributed source from the wall nucleation sites was used. Thus it was possible to avoid the usual assumption of a constant bubble number density. Comparisons of the model with the data shows that the model based on the nucleation site density correlation appears to be acceptable to describe the vapor generation in the flashing flow. For the limited data examined, the comparisons show rather satisfactory agreement without using a floating parameter to adjust the model. This result indicated that, at least for the experimental conditions considered here, the mechanistic predictions of the flashing phenomenon is possible on the present wall nucleation based model

  17. Mechanisms of nucleation in flashing flows

    International Nuclear Information System (INIS)

    Yan, F.; Giot, M.

    1989-01-01

    The mechanisms of nucleation have been analysed. Starting from the assumption that the activation of micro-cavities in the wall surfaces is the most probable nucleation mechanism in practical flashing system, the authors study in detail the nucleation in a micro-cavity. A three step nucleation criterion is proposed, namely: trapping cavity, activable cavity and active cavity. Then, a new nucleation model is presented. The output of the model is the prediction of the bubble departure frequency versus the thermodynamic state of the liquid and the geometry of the cavity. The model can also predict the nucleation site density if the nature of the wall and the surface roughness are know. The prediction have been successfully compared with some preliminary experimental results. By combining the present model with Jones'theory, the flashing inception is correctly predicted. The use of this nucleation model for the complete modelling of a flashing non-equilibrium flow is in progress

  18. An Analysis of Total Lightning Flash Rates Over Florida

    Science.gov (United States)

    Mazzetti, Thomas O.; Fuelberg, Henry E.

    2017-12-01

    Although Florida is known as the "Sunshine State", it also contains the greatest lightning flash densities in the United States. Flash density has received considerable attention in the literature, but lightning flash rate has received much less attention. We use data from the Earth Networks Total Lightning Network (ENTLN) to produce a 5 year (2010-2014) set of statistics regarding total flash rates over Florida and adjacent regions. Instead of tracking individual storms, we superimpose a 0.2° × 0.2° grid over the study region and count both cloud-to-ground (CG) and in-cloud (IC) flashes over 5 min intervals. Results show that the distribution of total flash rates is highly skewed toward small values, whereas the greatest rate is 185 flashes min-1. Greatest average annual flash rates ( 3 flashes min-1) are located near Orlando. The southernmost peninsula, North Florida, and the Florida Panhandle exhibit smaller average annual flash rates ( 1.5 flashes min-1). Large flash rates > 100 flashes min-1 can occur during any season, at any time during the 24 h period, and at any location within the domain. However, they are most likely during the afternoon and early evening in East Central Florida during the spring and summer months.

  19. Flash Builder 4 and Flex 4 Bible

    CERN Document Server

    Gassner, David

    2010-01-01

    A complete and thorough reference for developers on the new Flex 4 platform. Create desktop applications that behave identically on Windows, Mac OS X, and Linux with Adobe's new Flash Builder 4 platform and this in-depth guide. The book's tutorials and explanations walk you step-by-step through Flash Builder's new, faster tools; the new framework for generating code; how to connect to popular application servers; upgrading from Flex 3; and much more.: Shows you how to create rich applications for the Web and desktop with the very latest version of Flex, with detailed coverage for both new and

  20. Foundation Flash CS5 for Designers

    CERN Document Server

    Green, T

    2010-01-01

    Flash is one of the most engaging, innovative, and versatile technologies available - allowing the creation of anything from animated banners and simple cartoons to Rich Internet Applications, interactive videos, and dynamic user interfaces for web sites, kiosks, devices, or DVDs. The possibilities are endless, and now it just got better. Flash CS5 boasts a host of new features, including better support for mobile devices, a whole new animation engine enabling full manipulation of tweens and paths, custom easing, improved inverse kinematics, a revamped timeline, built-in 3D, and much more. Thi