WorldWideScience

Sample records for network vlsi chip

  1. Cascaded VLSI Chips Help Neural Network To Learn

    Science.gov (United States)

    Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

    1993-01-01

    Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

  2. Learning and optimization with cascaded VLSI neural network building-block chips

    Science.gov (United States)

    Duong, T.; Eberhardt, S. P.; Tran, M.; Daud, T.; Thakoor, A. P.

    1992-01-01

    To demonstrate the versatility of the building-block approach, two neural network applications were implemented on cascaded analog VLSI chips. Weights were implemented using 7-b multiplying digital-to-analog converter (MDAC) synapse circuits, with 31 x 32 and 32 x 32 synapses per chip. A novel learning algorithm compatible with analog VLSI was applied to the two-input parity problem. The algorithm combines dynamically evolving architecture with limited gradient-descent backpropagation for efficient and versatile supervised learning. To implement the learning algorithm in hardware, synapse circuits were paralleled for additional quantization levels. The hardware-in-the-loop learning system allocated 2-5 hidden neurons for parity problems. Also, a 7 x 7 assignment problem was mapped onto a cascaded 64-neuron fully connected feedback network. In 100 randomly selected problems, the network found optimal or good solutions in most cases, with settling times in the range of 7-100 microseconds.

  3. UW VLSI chip tester

    Science.gov (United States)

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  4. Handbook of VLSI chip design and expert systems

    CERN Document Server

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  5. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  6. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  7. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  8. Constant fan-in digital neural networks are VLSI-optimal

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1995-12-31

    The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

  9. Synthesis of on-chip control circuits for mVLSI biochips

    DEFF Research Database (Denmark)

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  10. INTERNAL MEASUREMENTS FOR FAILURE ANALYSIS AND CHIP VERIFICATION OF VLSI CIRCUITS

    OpenAIRE

    KÖlzer, J.; Otto, J.

    1989-01-01

    Chip verification and failure analysis during the design evaluation of very large scale integrated (VLSI) devices call for highly accurate internal analysis methods. After having characterized the first silicon by automated functional testing, classification and statistical analysis can be carried out : In this way a rough electrical evaluation of the material under investigation can be made. Further clues to a faulty device behavior can only be obtained by internal measurements. Serious malf...

  11. How to build VLSI-efficient neural chips

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-02-01

    This paper presents several upper and lower bounds for the number-of-bits required for solving a classification problem, as well as ways in which these bounds can be used to efficiently build neural network chips. The focus will be on complexity aspects pertaining to neural networks: (1) size complexity and depth (size) tradeoffs, and (2) precision of weights and thresholds as well as limited interconnectivity. They show difficult problems-exponential growth in either space (precision and size) and/or time (learning and depth)-when using neural networks for solving general classes of problems (particular cases may enjoy better performances). The bounds for the number-of-bits required for solving a classification problem represent the first step of a general class of constructive algorithms, by showing how the quantization of the input space could be done in O (m{sup 2}n) steps. Here m is the number of examples, while n is the number of dimensions. The second step of the algorithm finds its roots in the implementation of a class of Boolean functions using threshold gates. It is substantiated by mathematical proofs for the size O (mn/{Delta}), and the depth O [log(mn)/log{Delta}] of the resulting network (here {Delta} is the maximum fan in). Using the fan in as a parameter, a full class of solutions can be designed. The third step of the algorithm represents a reduction of the size and an increase of its generalization capabilities. Extensions by using analogue COMPARISONs, allows for real inputs, and increase the generalization capabilities at the expense of longer training times. Finally, several solutions which can lower the size of the resulting neural network are detailed. The interesting aspect is that they are obtained for limited, or even constant, fan-ins. In support of these claims many simulations have been performed and are called upon.

  12. Learning in Neural Networks: VLSI Implementation Strategies

    Science.gov (United States)

    Duong, Tuan Anh

    1995-01-01

    Fully-parallel hardware neural network implementations may be applied to high-speed recognition, classification, and mapping tasks in areas such as vision, or can be used as low-cost self-contained units for tasks such as error detection in mechanical systems (e.g. autos). Learning is required not only to satisfy application requirements, but also to overcome hardware-imposed limitations such as reduced dynamic range of connections.

  13. A VLSI System-on-Chip for Particle Detectors

    CERN Document Server

    AUTHOR|(CDS)2078019

    In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

  14. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Directory of Open Access Journals (Sweden)

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  15. An Integrated Unix-based CAD System for the Design and Testing of Custom VLSI Chips

    Science.gov (United States)

    Deutsch, L. J.

    1985-01-01

    A computer aided design (CAD) system that is being used at the Jet Propulsion Laboratory for the design of custom and semicustom very large scale integrated (VLSI) chips is described. The system consists of a Digital Equipment Corporation VAX computer with the UNIX operating system and a collection of software tools for the layout, simulation, and verification of microcircuits. Most of these tools were written by the academic community and are, therefore, available to JPL at little or no cost. Some small pieces of software have been written in-house in order to make all the tools interact with each other with a minimal amount of effort on the part of the designer.

  16. Autonomous navigation of a mobile robot using custom-designed qualitative reasoning VLSI chips and boards

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, H.; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of a mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation is a-priori unknown environments is discussed. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse inaccurate sensor data. 17 refs., 6 figs.

  17. Using custom-designed VLSI fuzzy inferencing chips for the autonomous navigation of a mobile robot

    Energy Technology Data Exchange (ETDEWEB)

    Pin, F.G.; Pattay, R.S. (Oak Ridge National Lab., TN (United States)); Watanabe, Hiroyuki; Symon, J. (North Carolina Univ., Chapel Hill, NC (United States). Dept. of Computer Science)

    1991-01-01

    Two types of computer boards including custom-designed VLSI fuzzy inferencing chips have been developed to add a qualitative reasoning capability to the real-time control of autonomous mobile robots. The design and operation of these boards are first described and an example of their use for the autonomous navigation of mobile robot is presented. The development of qualitative reasoning schemes emulating human-like navigation in apriori unknown environments is discussed. An approach using superposition of elemental sensor-based behaviors is shown to alloy easy development and testing of the inferencing rule base, while providing for progressive addition of behaviors to resolve situations of increasing complexity. The efficiency of such schemes, which can consist of as little as a dozen qualitative rules, is illustrated in experiments involving an autonomous mobile robot navigating on the basis of very sparse and inaccurate sensor data. 17 refs., 6 figs.

  18. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Science.gov (United States)

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  19. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Science.gov (United States)

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  20. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Science.gov (United States)

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  1. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    CERN Document Server

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  2. VLSI-distributed architectures for smart cameras

    Science.gov (United States)

    Wolf, Wayne H.

    2001-03-01

    Smart cameras use video/image processing algorithms to capture images as objects, not as pixels. This paper describes architectures for smart cameras that take advantage of VLSI to improve the capabilities and performance of smart camera systems. Advances in VLSI technology aid in the development of smart cameras in two ways. First, VLSI allows us to integrate large amounts of processing power and memory along with image sensors. CMOS sensors are rapidly improving in performance, allowing us to integrate sensors, logic, and memory on the same chip. As we become able to build chips with hundreds of millions of transistors, we will be able to include powerful multiprocessors on the same chip as the image sensors. We call these image sensor/multiprocessor systems image processors. Second, VLSI allows us to put a large number of these powerful sensor/processor systems on a single scene. VLSI factories will produce large quantities of these image processors, making it cost-effective to use a large number of them in a single location. Image processors will be networked into distributed cameras that use many sensors as well as the full computational resources of all the available multiprocessors. Multiple cameras make a number of image recognition tasks easier: we can select the best view of an object, eliminate occlusions, and use 3D information to improve the accuracy of object recognition. This paper outlines approaches to distributed camera design: architectures for image processors and distributed cameras; algorithms to run on distributed smart cameras, and applications of which VLSI distributed camera systems.

  3. VLSI design

    CERN Document Server

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  4. VLSI design

    CERN Document Server

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  5. Non-linear feedback neural networks VLSI implementations and applications

    CERN Document Server

    Ansari, Mohd Samar

    2014-01-01

    This book aims to present a viable alternative to the Hopfield Neural Network (HNN) model for analog computation. It is well known that the standard HNN suffers from problems of convergence to local minima, and requirement of a large number of neurons and synaptic weights. Therefore, improved solutions are needed. The non-linear synapse neural network (NoSyNN) is one such possibility and is discussed in detail in this book. This book also discusses the applications in computationally intensive tasks like graph coloring, ranking, and linear as well as quadratic programming. The material in the book is useful to students, researchers and academician working in the area of analog computation.

  6. Microarchitecture and Implementation of Networks-on-Chip with a Flexible Concept for Communication Media Sharing

    OpenAIRE

    Samman, Faizal Arya

    2010-01-01

    This thesis proposes a concept, VLSI microarchitecture and implementation of a network on-chip (NoC) supporting a flexible communication media share methodology. The concept and methodology are based on a variable dynamic local identity tag (ID-tag) management technique, where different messages can be interleaved at flit-level on the same communication channel. Each message is multiplexed and allocated to a local ID slot on the shared channel. In order to implement the concept and methodolog...

  7. Harnessing VLSI System Design with EDA Tools

    CERN Document Server

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  8. VLSI design

    CERN Document Server

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  9. VLSI metallization

    CERN Document Server

    Einspruch, Norman G; Gildenblat, Gennady Sh

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 15: VLSI Metallization discusses the various issues and problems related to VLSI metallization. It details the available solutions and presents emerging trends.This volume is comprised of 10 chapters. The two introductory chapters, Chapter 1 and 2 serve as general references for the electrical and metallurgical properties of thin conducting films. Subsequent chapters review the various aspects of VLSI metallization. The order of presentation has been chosen to follow the common processing sequence. In Chapter 3, some relevant metal deposition tec

  10. Towards Dependable Network-on-Chip Architectures

    NARCIS (Netherlands)

    Chen, C.

    2015-01-01

    The aggressive semiconductor technology scaling provides the means for doubling the amount of transistors on a single chip each and every 18 months. To efficiently utilize these vast chip resources, Multi-Processor Systems on Chip (MPSoCs) integrated with a Network-on-Chip (NoC) communication

  11. Reconfigurable Networks-on-Chip

    CERN Document Server

    Chen, Sao-Jie; Tsai, Wen-Chung; Hu, Yu-Hen

    2012-01-01

    This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.   Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.     From the Foreword: Overall this book shows important advances over the...

  12. Photonic network-on-chip design

    CERN Document Server

    Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

    2013-01-01

    This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

  13. Radiation Behavior of Analog Neural Network Chip

    Science.gov (United States)

    Langenbacher, H.; Zee, F.; Daud, T.; Thakoor, A.

    1996-01-01

    A neural network experiment conducted for the Space Technology Research Vehicle (STRV-1) 1-b launched in June 1994. Identical sets of analog feed-forward neural network chips was used to study and compare the effects of space and ground radiation on the chips. Three failure mechanisms are noted.

  14. Programmable synaptic chip for electronic neural networks

    Science.gov (United States)

    Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

    1988-01-01

    A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

  15. Associative Pattern Recognition In Analog VLSI Circuits

    Science.gov (United States)

    Tawel, Raoul

    1995-01-01

    Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.

  16. Modeling and simulation of network-on-chip systems with DEVS and DEUS.

    Science.gov (United States)

    Amoretti, Michele

    2014-01-01

    Networks on-chip (NoCs) provide enhanced performance, scalability, modularity, and design productivity as compared with previous communication architectures for VLSI systems on-chip (SoCs), such as buses and dedicated signal wires. Since the NoC design space is very large and high dimensional, evaluation methodologies rely heavily on analytical modeling and simulation. Unfortunately, there is no standard modeling framework. In this paper we illustrate how to design and evaluate NoCs by integrating the Discrete Event System Specification (DEVS) modeling framework and the simulation environment called DEUS. The advantage of such an approach is that both DEVS and DEUS support modularity-the former being a sound and complete modeling framework and the latter being an open, general-purpose platform, characterized by a steep learning curve and the possibility to simulate any system at any level of detail.

  17. Asynchronous design of Networks-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2007-01-01

    The Network-on-chip concept has evolved as a solution to a broad range of problems related to the design of complex systems-on-chip (SoC) with tenths or hundreds of (heterogeneous) IP-cores. The paper introduces the NoC concept, identifies a range of possible timing organizations (globally...

  18. VLSI signal processing technology

    CERN Document Server

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  19. VLSI electronics microstructure science

    CERN Document Server

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  20. Quantitative design space exploration of routing-switches for Network-on-Chip

    Directory of Open Access Journals (Sweden)

    M. C. Neuenhahn

    2008-05-01

    Full Text Available Future Systems-on-Chip (SoC will consist of many embedded functional units like e.g. embedded processor cores, memories or FPGA like structures. These SoCs will have huge communication demands, which can not be fulfilled by bus-based communication systems. Possible solutions to this problem are so called Networks-on-Chip (NoC.

    These NoCs basically consist of network-interfaces which integrate functional units into the NoC and routing-switches which connect the network-interfaces. Here, VLSI-based routing-switch implementations are presented. The characteristics of these NoCs like performance and costs (e.g. silicon area respectively logic elements, power dissipation depend on a variety of parameters. As a routing-switch is a key component of a NoC, the costs and performance of routing-switches are compared for different parameter combinations. Evaluated parameters are for example data word length, architecture of the routing-switch (parallel vs. centralized implementation and routing-algorithm.

    The performance and costs of routing-switches were evaluated using an FPGA-based NoC-emulator. In addition different routing-switches were implemented using a 90 nm standard-cell library to determine the maximum clock frequency, power-dissipation and area of a VLSI-implementation. The power consumption was determined by simulating the extracted layout of the routing-switches. Finally, these results are benchmarked to other routing-switch implementations like Aetheral and xpipes.

  1. VLSI in medicine

    CERN Document Server

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  2. VLSI electronics microstructure science

    CERN Document Server

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  3. Use of polyimides in VLSI fabrication

    Science.gov (United States)

    Wilson, A. M.

    The functional requirements of overcoats and multilevel insulators for very large scale integrated circuits (VLSI) are outlined. The moisture barrier properties of polyimide films are reviewed. Polyimide performance vs plasma enhanced chemically vapor deposited (CVD) silicon nitride overcoats are compared. The topological and via forming advantages of polyimides vs plasma enhanced CVD silicon oxide as a multilevel insulator are cited. The temperature and voltage field induced electronic charge transport and trapping at oxide interfaces is cited as the most serious limitation to the use of polyimides as multilevel insulators on VLSI chips.

  4. The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture

    OpenAIRE

    Biagioni, Andrea; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Perra, Mersia; Rossetti, Davide; Sidore, Carlo; Simula, Francesco; Tosoratto, Laura; Vicini, Piero

    2012-01-01

    One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communications between processors, recent multi-tile (i.e. multi-core) architectures face the challenge for an efficient on-chip interconnection network between processor's tiles. In this paper, we present a configurable and scalable architecture, based on...

  5. Drift chamber tracking with neural networks

    Energy Technology Data Exchange (ETDEWEB)

    Lindsey, C.S.; Denby, B.; Haggerty, H.

    1992-10-01

    We discuss drift chamber tracking with a commercial log VLSI neural network chip. Voltages proportional to the drift times in a 4-layer drift chamber were presented to the Intel ETANN chip. The network was trained to provide the intercept and slope of straight tracks traversing the chamber. The outputs were recorded and later compared off line to conventional track fits. Two types of network architectures were studied. Applications of neural network tracking to high energy physics detector triggers is discussed.

  6. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  7. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jurgen

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon- Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  8. Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs

    CERN Document Server

    Shen, Ruijing; Yu, Hao

    2012-01-01

    Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have  become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits.  Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and ...

  9. A Methodology for Producing and Testing a Genesil Silicon Compiler Designed VLSI Chip Which Incorporates Design for Testability

    Science.gov (United States)

    1990-09-01

    position of the Depart- ment of Defense or the US Government. ś COSA I CODL> 18 S,,BjECT TERMS (Continue on reverse if necessar dno idenritj b blck...submissions. All interaction with MOSIS is normally done using elec- tronic mail via the INTERNET computer network. Electronic mail correspondence to

  10. Routing algorithms in networks-on-chip

    CERN Document Server

    Daneshtalab, Masoud

    2014-01-01

    This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.   ·         Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems; ·         Describe...

  11. VLSI Microsystem for Rapid Bioinformatic Pattern Recognition

    Science.gov (United States)

    Fang, Wai-Chi; Lue, Jaw-Chyng

    2009-01-01

    A system comprising very-large-scale integrated (VLSI) circuits is being developed as a means of bioinformatics-oriented analysis and recognition of patterns of fluorescence generated in a microarray in an advanced, highly miniaturized, portable genetic-expression-assay instrument. Such an instrument implements an on-chip combination of polymerase chain reactions and electrochemical transduction for amplification and detection of deoxyribonucleic acid (DNA).

  12. Learning to Classify Map Data with Cascaded VLSI Neural Network Building Block Chips

    Science.gov (United States)

    Brown, T. X.; Duong, T.; Eberhardt, S. P.; Tran, M. D.; Daud, T.; Thakoor, A. P.

    1993-01-01

    Paper maps are an important but unwieldy data format. To increase its utility, copious amounts of map data have been scanned into a digital map knowledge base. The next task in this knowledge base is to reduce this data to its underlying feature form suitable for analysis.

  13. Plasma processing for VLSI

    CERN Document Server

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  14. Custom Topology Generation for Network-on-Chip

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo; Sparsø, Jens

    2007-01-01

    This paper compares simulated annealing and tabu search for generating custom topologies for applications with periodic behaviour executing on a network-on-chip. The approach differs from previous work by starting from a fixed mapping of IP-cores to routers and performing design space exploration....... An analytical model is used to determine communication latencies in the network-on-chip....

  15. Modelling, Synthesis, and Configuration of Networks-on-Chips

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo

    This thesis presents three contributions in two different areas of network-on-chip and system-on-chip research: Application modelling and identifying and solving different optimization problems related to two specific network-on-chip architectures. The contribution related to application modelling...... is an analytical method for deriving the worst-case traffic pattern caused by an application and the cache-coherence protocol in a cache-coherent shared-memory system. The contributions related to network-on-chip optimization problems consist of two parts: The development and evaluation of six heuristics...... for solving the network synthesis problem in the MANGO network-on-chip, and the identification and formalization of the ReNoC configuration problem together with three heuristics for solving it....

  16. Transient and permanent error control for networks-on-chip

    CERN Document Server

    Yu, Qiaoyan

    2012-01-01

    This book addresses reliability and energy efficiency of on-chip networks using a configurable error control coding (ECC) scheme for datalink-layer transient error management. The method can adjust both error detection and correction strengths at runtime by varying the number of redundant wires for parity-check bits. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance. Includes a complete survey of error control methods for reliable networks-on-chip, evaluated for reliability, energy and performance metrics; Provides analysis of error control in various network-on-chip layers, as well as presentation of an innovative multi-layer error control coding technique; Presents state-of-the-art solutions to address simultaneously reliability, energy and performan...

  17. Low-Cost Allocator Implementations for Networks-on-Chip Routers

    Directory of Open Access Journals (Sweden)

    Min Zhang

    2009-01-01

    Full Text Available Cost-effective Networks-on-Chip (NoCs routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA and the generic switch allocator (SA of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

  18. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Science.gov (United States)

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  19. The ReNoC Reconfigurable Network-on-Chip

    DEFF Research Database (Denmark)

    Stuart, Matthias Bo; Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2011-01-01

    This article presents a reconfigurable network-on-chip architecture called ReNoC, which is intended for use in general-purpose multiprocessor system-on-chip platforms, and which enables application-specific logical NoC topologies to be configured, thus providing both efficiency and flexibility...

  20. A Time-predictable Memory Network-on-Chip

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Chong, David VH; Puffitsch, Wolfgang

    2014-01-01

    arbitration and access for chip-multiprocessors. The memory network-on-chip is organized as a tree with time-division multiplexing (TDM) of accesses to the shared memory. The TDM based arbitration completely decouples processor cores and allows WCET analysis of the memory accesses on individual cores without...

  1. Brain-on-a-chip integrated neuronal networks

    NARCIS (Netherlands)

    Xie, Sijia

    2016-01-01

    The brain-on-a-chip technology aims to provide an efficient and economic in vitro platform for brain disease study. In the well-known literature on brain-on-a-chip systems, nonstructured surfaces were conventionally used for the cell attachment in a culture chamber, therefore the neuronal networks

  2. Summary of workshop on the application of VLSI for robotic sensing

    Science.gov (United States)

    Brooks, T.; Wilcox, B.

    1984-01-01

    It was one of the objectives of the considered workshop to identify near, mid, and far-term applications of VLSI for robotic sensing and sensor data preprocessing. The workshop was also to indicate areas in which VLSI technology can provide immediate and future payoffs. A third objective is related to the promotion of dialog and collaborative efforts between research communities, industry, and government. The workshop was held on March 24-25, 1983. Conclusions and recommendations are discussed. Attention is given to the need for a pixel correction chip, an image sensor with 10,000 dynamic range, VLSI enhanced architectures, the need for a high-density serpentine memory, an LSI-tactile sensing program, an analog-signal preprocessor chip, a smart strain gage, a protective proximity envelope, a VLSI-proximity sensor program, a robot-net chip, and aspects of silicon micromechanics.

  3. A Neuron- and a Synapse Chip for Artificial Neural Networks

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1992-01-01

    A cascadable, analog, CMOS chip set has been developed for hardware implementations of artificial neural networks (ANN's):I) a neuron chip containing an array of neurons with hyperbolic tangent activation functions and adjustable gains, and II) a synapse chip (or a matrix-vector multiplier) where...... the matrix is stored on-chip as differential voltages on capacitors. In principal any ANN configuration can be made using these chips. A neuron array of 4 neurons and a 4 × 4 matrix-vector multiplier has been fabricated in a standard 2.4 ¿m CMOS process for test purposes. The propagation time through...... the synapse and neuron chips is less than 4 ¿s and the weight matrix has a 10 bit resolution....

  4. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  5. Lithography for VLSI

    CERN Document Server

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  6. Spike-driven synaptic plasticity: theory, simulation, VLSI implementation.

    Science.gov (United States)

    Fusi, S; Annunziato, M; Badoni, D; Salamon, A; Amit, D J

    2000-10-01

    We present a model for spike-driven dynamics of a plastic synapse, suited for aVLSI implementation. The synaptic device behaves as a capacitor on short timescales and preserves the memory of two stable states (efficacies) on long timescales. The transitions (LTP/LTD) are stochastic because both the number and the distribution of neural spikes in any finite (stimulation) interval fluctuate, even at fixed pre- and postsynaptic spike rates. The dynamics of the single synapse is studied analytically by extending the solution to a classic problem in queuing theory (Takacs process). The model of the synapse is implemented in aVLSI and consists of only 18 transistors. It is also directly simulated. The simulations indicate that LTP/LTD probabilities versus rates are robust to fluctuations of the electronic parameters in a wide range of rates. The solutions for these probabilities are in very good agreement with both the simulations and measurements. Moreover, the probabilities are readily manipulable by variations of the chip's parameters, even in ranges where they are very small. The tests of the electronic device cover the range from spontaneous activity (3-4 Hz) to stimulus-driven rates (50 Hz). Low transition probabilities can be maintained in all ranges, even though the intrinsic time constants of the device are short (approximately 100 ms). Synaptic transitions are triggered by elevated presynaptic rates: for low presynaptic rates, there are essentially no transitions. The synaptic device can preserve its memory for years in the absence of stimulation. Stochasticity of learning is a result of the variability of interspike intervals; noise is a feature of the distributed dynamics of the network. The fact that the synapse is binary on long timescales solves the stability problem of synaptic efficacies in the absence of stimulation. Yet stochastic learning theory ensures that it does not affect the collective behavior of the network, if the transition probabilities are

  7. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...... transactions are packetized and transmitted across the shared network, and illustrate how this affects the end-to-end performance. A high predictability of the latency of communication on shared links is shown in a MANGO-based demonstrator system...

  8. VLSI micro- and nanophotonics science, technology, and applications

    CERN Document Server

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  9. Transformational VLSI Design

    DEFF Research Database (Denmark)

    Rasmussen, Ole Steen

    This thesis introduces a formal approach to deriving VLSI circuits by the use of correctness-preserving transformations. Both the specification and the implementation are descibed by the relation based language Ruby. In order to prove the transformation rules a proof tool called RubyZF has been...

  10. Noise-margin limitations on gallium-arsenide VLSI

    Science.gov (United States)

    Long, Stephen I.; Sundaram, Mani

    1988-01-01

    Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

  11. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  12. Reliability, Availability and Serviceability of Networks-on-Chip

    CERN Document Server

    Cota, Érika; Soares Lubaszewski, Marcelo

    2012-01-01

    This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

  13. An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable System-on-Chip

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria

    This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial

  14. An energy-efficient Network-on-Chip for a heterogeneous tiled reconfigurable Systems-on-Chip

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria

    This paper proposes a Network-on-Chip architecture that offers high flexibility and performance. It is used in a System-on-Chip platform for future multimedia mobile devices. The network is packet switching wormhole network with virtual-channel flow control and source routing. The initial

  15. Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

    Science.gov (United States)

    Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

    2013-03-11

    The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

  16. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    OpenAIRE

    Xin Wang; Jari Nurmi

    2007-01-01

    Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, ...

  17. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...

  18. A coherent VLSI design environment

    Science.gov (United States)

    Penfield, Paul, Jr.

    1988-05-01

    The CAD effort is centered on timing analysis and circuit simulation. Advances have been made in tightening the bounds of timing analysis. The superiority of the Gauss-Jacobi technique for matrix solution, over the Gauss-Seidel method, has been proven when the algorithms are implemented on massively parallel machines. In the circuits area, one result of importance is a new technique for calculating the highest frequency of operation of transistors with parasitic elements present. Work on a synthesis technique is under way. In the architecture area, many new results have been derived for parallel algorithms and complexity. One of the most astonishing is that a hypercube with a large number of faulty nodes can be used, with high probability, as another perfectly functioning hypercube of half the size, by using reconfiguration algorithms that are simple, fast, and require only local information. Also, the design of the message-driven processor is continuing, with several advances in architecture, software, communications, and ALU design. Many of these are being implemented in VLSI circuits. The theory work has as a central theme that the cost of communication should be included in complexity analyses. This has led to advances in models for computation, including volume-universal networks, routing, network flow, fault avoidance, queue management, and network simulation.

  19. Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

    Directory of Open Access Journals (Sweden)

    Xin Wang

    2007-01-01

    Full Text Available Two network-on-chip (NoC designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

  20. A Light-Weight Statically Scheduled Network-on-Chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Schoeberl, Martin; Sparsø, Jens

    2012-01-01

    This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources...

  1. The VLSI handbook

    CERN Document Server

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  2. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2008-01-01

    This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long...

  3. AN ACCURATE MODELING OF DELAY AND SLEW METRICS FOR ON-CHIP VLSI RC INTERCONNECTS FOR RAMP INPUTS USING BURR’S DISTRIBUTION FUNCTION

    Directory of Open Access Journals (Sweden)

    Rajib Kar

    2010-09-01

    Full Text Available This work presents an accurate and efficient model to compute the delay and slew metric of on-chip interconnect of high speed CMOS circuits foe ramp input. Our metric assumption is based on the Burr’s Distribution function. The Burr’s distribution is used to characterize the normalized homogeneous portion of the step response. We used the PERI (Probability distribution function Extension for Ramp Inputs technique that extends delay metrics and slew metric for step inputs to the more general and realistic non-step inputs. The accuracy of our models is justified with the results compared with that of SPICE simulations.

  4. A simple clockless Network-on-Chip for a commercial audio DSP chip

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    We design a very small, packet-switched, clockless Network-on-Chip (NoC) as a replacement for the existing crossbar-based communication infrastructure in a commercial audio DSP chip. Both solutions are laid out in a 0.18 um process, and compared in terms of area, power consumption and routing...... complexity. Even though the NoC turns out to be larger and more power consuming than the existing crossbar implementation, it still accounts for less than 1% of the total chip area and power consumption, and is justified by a long list of advantages: The NoC is modular, scalable, and in contrast......-Synchronous (GALS) system where independent clocking of the individual blocks is enabled. This study shows that NoCs are feasible even for small systems....

  5. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

    Science.gov (United States)

    Lee, Dasheng

    2008-12-02

    In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

  6. Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    Dasheng Lee

    2008-12-01

    Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

  7. VLSI implementation of a fairness ATM buffer system

    DEFF Research Database (Denmark)

    Nielsen, J.V.; Dittmann, Lars; Madsen, Jens Kargaard

    1996-01-01

    This paper presents a VLSI implementation of a resource allocation scheme, based on the concept of weighted fair queueing. The design can be used in asynchronous transfer mode (ATM) networks to ensure fairness and robustness. Weighted fair queueing is a scheduling and buffer management scheme...

  8. An analog CMOS chip set for neural networks with arbitrary topologies

    DEFF Research Database (Denmark)

    Lansner, John; Lehmann, Torsten

    1993-01-01

    An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus...... implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with well defined hyperbolic tangent activation functions which is implemented by using parasitic lateral bipolar transistors. The synapse test chip is a cascadable 4×4 matrix-vector multiplier with variable, 10-b...... resolution matrix elements. The propagation delay of the test chips was measured to 2.6 μs per layer...

  9. Spacecraft Neural Network Control System Design using FPGA

    OpenAIRE

    Hanaa T. El-Madany; Faten H. Fahmy; Ninet M. A. El-Rahman; Hassen T. Dorrah

    2011-01-01

    Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffer...

  10. A Formal Approach to the Verification of Networks on Chip

    Directory of Open Access Journals (Sweden)

    Schmaltz Julien

    2009-01-01

    Full Text Available Abstract The current technology allows the integration on a single die of complex systems-on-chip (SoCs that are composed of manufactured blocks (IPs, interconnected through specialized networks on chip (NoCs. IPs have usually been validated by diverse techniques (simulation, test, formal verification and the key problem remains the validation of the communication infrastructure. This paper addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A metamodel for NoCs has been developed and implemented in ACL2. This metamodel satisfies a generic correctness statement. Its verification for a particular NoC instance is reduced to discharging a set of proof obligations for each one of the NoC constituents. The methodology is demonstrated on a realistic and state-of-the-art design, the Spidergon network from STMicroelectronics.

  11. Artificial immune system algorithm in VLSI circuit configuration

    Science.gov (United States)

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  12. Integrated Circuit Chip Improves Network Efficiency

    Science.gov (United States)

    2008-01-01

    Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating

  13. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

  14. The role of simulation in the design of a neural network chip

    Science.gov (United States)

    Desai, Utpal; Roppel, Thaddeus A.; Padgett, Mary L.

    1993-01-01

    An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

  15. VLSI implementations for image communications

    CERN Document Server

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  16. Application of butterfly Clos-network in network-on-chip.

    Science.gov (United States)

    Liu, Hui; Xie, Linquan; Liu, Jiansheng; Ding, Lei

    2014-01-01

    This paper studied the topology of NoC (Network-on-Chip). By combining the characteristics of the Clos network and butterfly network, a new topology named BFC (Butterfly Clos-network) network was proposed. This topology integrates several modules, which belongs to the same layer but different dimensions, into a new module. In the BFC network, a bidirectional link is used to complete information exchange, instead of information exchange between different layers in the original network. During the routing period, other nondestination nodes can be used as middle stages to transfer data packets to complete the routing mission. Therefore, this topology has the characteristic of multistage. Simulation analyses show that BFC inherits the rich path diversity of Clos network, and it has a better performance than butterfly network in throughput and delay in a quite congested traffic pattern.

  17. A Novel Architecture for Adaptive Traffic Control in Network on Chip using Code Division Multiple Access Technique

    OpenAIRE

    Fatemeh. Dehghani; Shahram. Darooei

    2016-01-01

    Network on chip has emerged as a long-term and effective method in Multiprocessor System-on-Chip communications in order to overcome the bottleneck in bus based communication architectures. Efficiency and performance of network on chip is so dependent on the architecture and structure of the network. In this paper a new structure and architecture for adaptive traffic control in network on chip using Code Division Multiple Access technique is presented. To solve the problem of synchronous acce...

  18. A Virtual Channel Network-on-Chip for GT and BE traffic

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria; Jansen, P.G.; Wolkotte, P.T.

    2005-01-01

    This paper presents an on-chip network for a run-time reconfigurable System-on-Chip. The network uses packet-switching with virtual channels. It can provide guaranteed services as well as best effort services. The guaranteed services are based on virtual channel allocation, in contrast to other

  19. Neural network predicts sequence of TP53 gene based on DNA chip

    DEFF Research Database (Denmark)

    Spicker, J.S.; Wikman, F.; Lu, M.L.

    2002-01-01

    We have trained an artificial neural network to predict the sequence of the human TP53 tumor suppressor gene based on a p53 GeneChip. The trained neural network uses as input the fluorescence intensities of DNA hybridized to oligonucleotides on the surface of the chip and makes between zero...

  20. Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

    NARCIS (Netherlands)

    Hansson, A.; Goossens, K.; Rãdulescu, A.

    2007-01-01

    Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions

  1. On limited fan-in optimal neural networks

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.; Makaruk, H.E. [Los Alamos National Lab., NM (United States); Draghici, S. [Wayne State Univ., Detroit, MI (United States). Vision and Neural Networks Lab.

    1998-03-01

    Because VLSI implementations do not cope well with highly interconnected nets the area of a chip growing as the cube of the fan-in--this paper analyses the influence of limited fan in on the size and VLSI optimality of such nets. Two different approaches will show that VLSI- and size-optimal discrete neural networks can be obtained for small (i.e. lower than linear) fan-in values. They have applications to hardware implementations of neural networks. The first approach is based on implementing a certain sub class of Boolean functions, IF{sub n,m} functions. The authors will show that this class of functions can be implemented in VLSI optimal (i.e., minimizing AT{sup 2}) neural networks of small constant fan ins. The second approach is based on implementing Boolean functions for which the classical Shannon`s decomposition can be used. Such a solution has already been used to prove bounds on neural networks with fan-ins limited to 2. They generalize the result presented there to arbitrary fan-in, and prove that the size is minimized by small fan in values, while relative minimum size solutions can be obtained for fan-ins strictly lower than linear. Finally, a size-optimal neural network having small constant fan-ins will be suggested for IF{sub n,m} functions.

  2. Routing Aware Switch Hardware Customization for Networks on Chips

    OpenAIRE

    Meloni, Paolo; Murali, Srinivasan; Carta, Salvatore; Camplani, Massimo; Raffo, Luigi; Micheli, Giovanni,

    2006-01-01

    Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the app...

  3. Microarchitecture of network-on-chip routers a designer's perspective

    CERN Document Server

    Dimitrakopoulos, Giorgos; Seitanidis, Ioannis

    2014-01-01

    This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a

  4. Declarative Descriptions for VLSI Generators

    Science.gov (United States)

    1986-06-01

    will review languages in each category. Sheeran [ Sheeran 83] proposes a structured hierarchical design language, IL, FP (a variation of the...IEEE, 1982. [ Sheeran 83] Mary Sheeran . p& FP -An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing Laboratory, November, 1983

  5. VLSI mixed signal processing system

    Science.gov (United States)

    Alvarez, A.; Premkumar, A. B.

    1993-01-01

    An economical and efficient VLSI implementation of a mixed signal processing system (MSP) is presented in this paper. The MSP concept is investigated and the functional blocks of the proposed MSP are described. The requirements of each of the blocks are discussed in detail. A sample application using active acoustic cancellation technique is described to demonstrate the power of the MSP approach.

  6. Fundamentals of Microelectronics Processing (VLSI).

    Science.gov (United States)

    Takoudis, Christos G.

    1987-01-01

    Describes a 15-week course in the fundamentals of microelectronics processing in chemical engineering, which emphasizes the use of very large scale integration (VLSI). Provides a listing of the topics covered in the course outline, along with a sample of some of the final projects done by students. (TW)

  7. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Directory of Open Access Journals (Sweden)

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  8. Microscale Adaptive Optics: Wave-Front Control with a mu-Mirror Array and a VLSI Stochastic Gradient Descent Controller.

    Science.gov (United States)

    Weyrauch, T; Vorontsov, M A; Bifano, T G; Hammer, J A; Cohen, M; Cauwenberghs, G

    2001-08-20

    The performance of adaptive systems that consist of microscale on-chip elements [microelectromechanical mirror (mu-mirror) arrays and a VLSI stochastic gradient descent microelectronic control system] is analyzed. The mu-mirror arrays with 5 x 5 and 6 x 6 actuators were driven with a control system composed of two mixed-mode VLSI chips implementing model-free beam-quality metric optimization by the stochastic parallel perturbative gradient descent technique. The adaptation rate achieved was near 6000 iterations/s. A secondary (learning) feedback loop was used to control system parameters during the adaptation process, further increasing the adaptation rate.

  9. A Network Traffic Generator Model for Fast Network-on-Chip Simulation

    DEFF Research Database (Denmark)

    Mahadevan, Shankar; Angiolini, Frederico; Storgaard, Michael

    2005-01-01

    and effective Network-on-Chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an IP core in a reference environment, the TG can subsequently emulate the core's communication behavior in different environments. Access patterns......For Systems-on-Chip (SoCs) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast...

  10. Network Traffic Generator Model for Fast Network-on-Chip Simulation

    DEFF Research Database (Denmark)

    Mahadevan, Shankar; Ang, Frederico; Olsen, Rasmus G.

    2008-01-01

    and effective Network-on-Chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an IP core in a reference environment, the TG can subsequently emulate the core's communication behavior in different environments. Access patterns......For Systems-on-Chip (SoCs) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast...

  11. On-chip bioassay using immobilized sensing bacteria in three-dimensional microfluidic network.

    Science.gov (United States)

    Tani, Hirofumi; Maehana, Koji; Kamidate, Tamio

    2007-01-01

    An on-chip whole-cell bioassay has been carried out using Escherichia coli tester strains for genotoxicity. In this assay format, the mutagen-responsive bioluminescence (BL) strains are immobilized in a chip assembly in which a silicon chip is placed between two poly(dimethylsiloxane) (PDMS) chips. In the chip assembly, microchannels fabricated on the two separate PDMS layers are connected via perforated microwells on the Si chip, and thus a three-dimensional microfluidic network is constructed. The strains mixed with agarose are loaded from the channels on one of the two PDMS layers into the wells on Si chip, followed by gelation. Induction of the expression of firefly luciferase in the tester strains and BL reaction are successively carried out by filling the channels on another PDMS layer with samples containing inducer (genotoxic substance) and then adenosine triphosphate/luciferin mixture, respectively. BL emission from each of the wells can be monitored by using a charge-coupled device camera to obtain an overall picture of the chip. The on-chip format based on a three-dimensional microfluidic network provides a combinatorial bioassay for multiple samples with multiple tester strains in a simple chip assembly. Thus, the presented method could be applied not only to various microbial sensing applications but also to other (bio)chemical analyses.

  12. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard...

  13. Simulation-based Modeling Frameworks for Networked Multi-processor System-on-Chip

    DEFF Research Database (Denmark)

    Mahadevan, Shankar

    2006-01-01

    This thesis deals with modeling aspects of multi-processor system-on-chip (MpSoC) design affected by the on-chip interconnect, also called the Network-on-Chip (NoC), at various levels of abstraction. To begin with, we undertook a comprehensive survey of research and design practices of networked Mp......: namely ARTS and RIPE, that allows to model hardware (computation time, power consumption, network latency, caching effect, etc.) and software (application partition and mapping, operating system scheduling, interrupt handling, etc.) aspects from system-level to cycle-true abstraction. Thereby, we can...

  14. A Coherent VLSI Design Environment.

    Science.gov (United States)

    1985-03-31

    We would like to acknowledge the contributions by Flavio Rose of MIT when we first studied this problem. The three of us originally produced a O(1V13...Rinehart and Winston, New York, 1976. 18] Charles E. Leiserson, Flavio M. Rose, and James B. Saxe, "Optimizing synchronous circuitry by retiming... Flavio M. Rose, Models for VLSI CircuiLs, Masters Thesis, Department of Electrical En- gineering and Computer Science, Massachusetts Institute of

  15. Aelite: A Flit-Synchronous Network on Chip with Composable and Predictable Services.

    NARCIS (Netherlands)

    Hansson, A.; Subburaman, Mahesh; Goossens, Kees

    To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput

  16. A new 2D mesh routing approach for networks on chip Une nouvelle ...

    African Journals Online (AJOL)

    Keywords: Networks on chip, Dynamic routing algorithm, Clustering, Mesh topology, Systems on chip. Résumé. Dans le passé, les ... Mots Clés: Réseaux sur puce, Algorithme de routage dynamique, Clustering, Topologie Mesh, Systèmes sur puce. * Corresponding ..... [1] Semiconductor Industry Association. International.

  17. Routing of guaranteed throughput traffic in a network-on-chip

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Smit, Gerardus Johannes Maria; Wolkotte, P.T.; Jansen, P.G.

    This paper examines the possibilities of providing throughput guarantees in a network-on-chip by appropriate traffic routing. A source routing function is used to find routes with specified throughput for the data streams in a streaming multiprocessor system-on-chip. The influence of the routing

  18. Robust Bioinformatics Recognition with VLSI Biochip Microsystem

    Science.gov (United States)

    Lue, Jaw-Chyng L.; Fang, Wai-Chi

    2006-01-01

    A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

  19. Multi-Cluster Network on a Chip Reconfigurable Radiation Hardened Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of the Phase-I research is to architect, model and simulate a multi-cluster Network on a Chip (NoC) reconfigurable Radio in SystemC RTL, with...

  20. Structuring a multi-nodal neural network in vitro within a novel design microfluidic chip.

    Science.gov (United States)

    van de Wijdeven, Rosanne; Ramstad, Ola Huse; Bauer, Ulrich Stefan; Halaas, Øyvind; Sandvig, Axel; Sandvig, Ioanna

    2018-01-02

    Neural network formation is a complex process involving axon outgrowth and guidance. Axon guidance is facilitated by structural and molecular cues from the surrounding microenvironment. Micro-fabrication techniques can be employed to produce microfluidic chips with a highly controlled microenvironment for neural cells enabling longitudinal studies of complex processes associated with network formation. In this work, we demonstrate a novel open microfluidic chip design that encompasses a freely variable number of nodes interconnected by axon-permissible tunnels, enabling structuring of multi-nodal neural networks in vitro. The chip employs a partially open design to allow high level of control and reproducibility of cell seeding, while reducing shear stress on the cells. We show that by culturing dorsal root ganglion cells (DRGs) in our microfluidic chip, we were able to structure a neural network in vitro. These neurons were compartmentalized within six nodes interconnected through axon growth tunnels. Furthermore, we demonstrate the additional benefit of open top design by establishing a 3D neural culture in matrigel and a neuronal aggregate 3D culture within the chips. In conclusion, our results demonstrate a novel microfluidic chip design applicable to structuring complex neural networks in vitro, thus providing a versatile, highly relevant platform for the study of neural network dynamics applicable to developmental and regenerative neuroscience.

  1. Autonomic networking-on-chip bio-inspired specification, development, and verification

    CERN Document Server

    Cong-Vinh, Phan

    2011-01-01

    Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system. The FIRST Book to Assess Research Results, Opportunities, & Trends in ""BioChipNets"" The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent re

  2. System-Level Design Methodologies for Networked Multiprocessor Systems-on-Chip

    DEFF Research Database (Denmark)

    Virk, Kashif Munir

    2008-01-01

    is the first such attempt in the published literature. The second part of the thesis deals with the issues related to the development of system-level design methodologies for networked multiprocessor systems-on-chip at various levels of design abstraction with special focus on the modeling and design...... of wireless integrated sensor networks which are an emerging class of networked embedded computer systems. The work described here demonstrates how to model multiprocessor systems-on-chip at the system level by abstracting away most of the lower-level details albeit retaining the parameters most relevant...... at the system-level. The multiprocessor modeling framework is then extended to include models of networked multiprocessor systems-on-chip which is then employed to model wireless sensor networks both at the sensor node level as well as the wireless network level. In the third and the final part, the thesis...

  3. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Energy Technology Data Exchange (ETDEWEB)

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  4. A survey of research and practices of network-on-chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar

    2006-01-01

    The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures....... This survey presents a perspective on existing NoC research. We define the following abstractions: system, network adapter, network, and link to explain and structure the fundamental concepts. First, research relating to the actual network design is reviewed. Then system level design and modeling...

  5. Surface and interface effects in VLSI

    CERN Document Server

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  6. Exploration within the Network-on-Chip Paradigm

    NARCIS (Netherlands)

    Wolkotte, P.T.

    2009-01-01

    A general purpose processor used to consist of a single processing core, which performed and controlled all tasks on the chip. Its functionality and maximum clock frequency grew steadily over the years. Due to the continuous increase of the number of transistors available on-chip and the operational

  7. Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

    NARCIS (Netherlands)

    Hansson, A.; Hansson, Andreas; Wiggers, M.H.; Moonen, Arno; Goossens, Kees; Bekooij, Marco Jan Gerrit; Bekooij, Marco

    A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are

  8. III-V/silicon-on-Insulator nanophotonic cavities for optical network-on-chip.

    Science.gov (United States)

    Liu, Liu; Roelkens, Günther; Van Campenhout, Joris; Brouckaert, Joost; Van Thourhout, Dries; Baets, Roel

    2010-03-01

    We review some opto-electronic devices based on the III-V/SOI heterogeneous integration platform, including lasers, modulators, wavelength converters, and photo-detectors. All of them are critical components for future on-chip interconnect and optical network-on-chip. The footprints of such devices are kept small by employing micro-cavity based structures. We give an overview of the device performances. The advantages over the all-silicon based devices are also discussed.

  9. Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Yin Zhen Tei

    2014-01-01

    Full Text Available This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC. As the number of intellectual property (IP cores in multiprocessor system-on-chip (MPSoC increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA. The initial population of GA is initialized with network partitioning (NP while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

  10. An area-efficient network interface for a TDM-based Network-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens; Kasapaki, Evangelia; Schoeberl, Martin

    2013-01-01

    Network interfaces (NIs) are used in multi-core systems where they connect processors, memories, and other IP-cores to a packet switched Network-on-Chip (NOC). The functionality of a NI is to bridge between the read/write transaction interfaces used by the cores and the packet-streaming interface...... used by the routers and links in the NOC. The paper addresses the design of a NI for a NOC that uses time division multiplexing (TDM). By keeping the essence of TDM in mind, we have developed a new area-efficient NI micro-architecture. The new design completely eliminates the need for FIFO buffers...... and credit based flow control - resources which are reported to account for 50–85% of the area in existing NI designs. The paper discusses the design considerations, presents the new NI micro-architecture, and reports area figures for a range of implementations....

  11. VLSI architectures for modern error-correcting codes

    CERN Document Server

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  12. VLSI Technology for Cognitive Radio

    Science.gov (United States)

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  13. Error Control for Network-on-Chip Links

    CERN Document Server

    Fu, Bo

    2012-01-01

    As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

  14. Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors...... in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel...

  15. Full custom VLSI - A technology for high performance computing

    Science.gov (United States)

    Maki, Gary K.; Whitaker, Sterling R.

    1990-01-01

    Full custom VLSI is presented as a viable technology for addressing the need for the computing capabilities required for the real-time health monitoring of spacecraft systems. This technology presents solutions that cannot be realized with stored program computers or semicustom VLSI; also, it is not dependent on current IC processes. It is argued that, while design time is longer, full custom VLSI produces the fastest and densest VLSI solution and that high density normally also yields low manufacturing costs.

  16. Variable-Width Datapath for On-Chip Network Static Power Reduction

    Energy Technology Data Exchange (ETDEWEB)

    Michelogiannakis, George; Shalf, John

    2013-11-13

    With the tight power budgets in modern large-scale chips and the unpredictability of application traffic, on-chip network designers are faced with the dilemma of designing for worst- case bandwidth demands and incurring high static power overheads, or designing for an average traffic pattern and risk degrading performance. This paper proposes adaptive bandwidth networks (ABNs) which divide channels and switches into lanes such that the network provides just the bandwidth necessary in each hop. ABNs also activate input virtual channels (VCs) individually and take advantage of drowsy SRAM cells to eliminate false VC activations. In addition, ABNs readily apply to silicon defect tolerance with just the extra cost for detecting faults. For application traffic, ABNs reduce total power consumption by an average of 45percent with comparable performance compared to single-lane power-gated networks, and 33percent compared to multi-network designs.

  17. A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips

    Directory of Open Access Journals (Sweden)

    Onur Derin

    2011-01-01

    propose a task-aware middleware concept that allows adaptivity in KPN implemented over a Network on Chip (NoC. We also list our ideas on the development of a simulation platform as an initial step towards creating fault tolerance strategies for KPNs applications running on NoCs. In doing that, we extend our SACRE (Self-Adaptive Component Run Time Environment framework by integrating it with an open source NoC simulator, Noxim. We evaluate the overhead that the middleware brings to the the total execution time and to the total amount of data transferred in the NoC. With this work, we also provide a methodology that can help in identifying the requirements and implementing fault tolerance and adaptivity support on real platforms.

  18. Power gating of VLSI circuits using MEMS switches in low power applications

    KAUST Repository

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  19. An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar; Olsen, Rasmus Grøndahl

    2005-01-01

    The demand for IP reuse and system level scalability in System-on-Chip (SoC) designs is growing. Network-onchip (NoC) constitutes a viable solution space to emerging SoC design challenges. In this paper we describe an OCP compliant network adapter (NA) architecture for the MANGO NoC. The NA...... decouples communication and computation, providing memory-mapped OCP transactions based on primitive message-passing services of the network. Also, it facilitates GALS-type systems, by adapting to the clockless network. This helps leverage a modular SoC design flow. We evaluate performance and cost of 0...

  20. Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Sparsø, Jens; Sørensen, Rasmus Bo

    2013-01-01

    In this paper we explore the design of an asynchronous router for a time-division-multiplexed (TDM) network-on-chip (NOC) that is being developed for a multi-processor platform for hard real-time systems. TDM inherently requires a common time reference, and existing TDM-based NOC designs are either...

  1. A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of GS in asynchronous Network-on-Chip. We present a novel scheduling discipline called Asynchronous Latency Guarantee (ALG...

  2. Synthesis and Layout of an Asynchronous Network-on-Chip using Standard EDA Tools

    DEFF Research Database (Denmark)

    Müller, Christoph; Kasapaki, Evangelia; Sørensen, Rasmus Bo

    2014-01-01

    is the key role that clock signals play in specifying time-constraints for the synthesis. In this paper explain how we handled the synthesis and layout of an asynchronous network-on-chip for a multi-core platform. Focus is on the design process while the actual NOC-design and its performance are presented...

  3. A Metaheuristic Scheduler for Time Division Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Sparsø, Jens; Pedersen, Mark Ruvald

    2014-01-01

    This paper presents a metaheuristic scheduler for inter-processor communication in multi-processor platforms using time division multiplexed (TDM) networks on chip (NOC). Compared to previous works, the scheduler handles a broader and more general class of platforms. Another contribution, which has...

  4. Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

    Science.gov (United States)

    2009-05-01

    adversarial way. Each of the synthetic benchmark traces are generated from their descriptions in the literature using Python scripts. Application-Based...networks for chip multiprocessors. In 16th IEEE Symposium on High Perfor- mance Interconnects, Aug 2008. [16] V. Puente , R. Beivide, J. A. Gregorio, J. M

  5. Analysis and design of an on-chip retargeting engine for IEEE 1687 networks

    NARCIS (Netherlands)

    Ibrahim, Ahmed Mohammed Youssef; Kerkhoff, Hans G.

    IEEE 1687 (iJTAG) standard introduces a methodology for accessing the increasing number of embedded instruments found in modern System-on-Chips. Retargeting is defined by iJTAG as the procedure of translating instrument-level patterns to system-level scan vectors for a certain network organization.

  6. Networking and computing: From the Chip to the Web

    OpenAIRE

    Kropf, Peter; Plaice, John

    2010-01-01

    There are two fundamental trends in the development of computers: the miniaturization of components and the increase in communication capacities. The combination of these two trends is leading to a qualitatively new situation, in which the same techniques will be applicable at all scales of computing, be they at the chip level or at the level of the World Wide Web (WWW).

  7. Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

    Science.gov (United States)

    Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

    2009-04-13

    The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

  8. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  9. An all-glass microfluidic network with integrated amorphous silicon photosensors for on-chip monitoring of enzymatic biochemical assay

    NARCIS (Netherlands)

    Costantini, Francesca; Tiggelaar, Roald M.; Salvio, Riccardo; Nardecchia, Marco; Schlautmann, Stefan; Manetti, Cesare; Gardeniers, Han J.G.E.; de Cesare, Giampiero; Caputo, Domenico; Nascetti, Augusto

    2017-01-01

    A lab-on-chip system, integrating an all-glass microfluidics and on-chip optical detection, was developed and tested. The microfluidic network is etched in a glass substrate, which is then sealed with a glass cover by direct bonding. Thin film amorphous silicon photosensors have been fabricated on

  10. Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis

    NARCIS (Netherlands)

    Hansson, A.; Hansson, A.; Wiggers, M.H.; Moonen, A.; Goossens, K.; Bekooij, Marco Jan Gerrit; Bekooij, M.

    2009-01-01

    A growing number of applications, often with real-time requirements, are integrated on the same system on chip (SoC), in the form of hardware and software intellectual property (IP). To facilitate real-time applications, networks on chip (NoC) guarantee bounds on latency and throughput. These

  11. Static Routing in Symmetric Real-Time Network-on-Chips

    DEFF Research Database (Denmark)

    Brandner, Florian; Schoeberl, Martin

    2012-01-01

    With the rising number of cores on a single chip the question on how to organize the communication among those cores becomes more and more relevant. A common solution is to use a network-on-chip (NoC) that provides communication bandwidth, routing, and arbitration among the cores. The use of No......Cs in real-time systems is problematic, since the shared network and all cores connected to it have to be analyzed to derive time bounds of real-time tasks. We propose to use a statically scheduled, time-division-multiplexed NoC design that allows a decoupled analysis of individual real-time tasks. Our...... network provides virtual circuits between all cores. These virtual circuits are implemented by delivering messages periodically on a static, fixed routing schedule. Since the routing does not change, it can be pre-computed offline. This work focuses on the computation of routing schedules for symmetric No...

  12. Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Feng Wang

    2015-01-01

    Full Text Available Network-on-Chip (NoC is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

  13. Modeling, analysis and optimization of network-on-chip communication architectures

    CERN Document Server

    Ogras, Umit Y

    2013-01-01

    Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

  14. Network-on-chip the next generation of system-on-chip integration

    CERN Document Server

    Kundu, Santanu

    2014-01-01

    ""What makes this book special as compared to the current literature in the field is that it provides a complete picture of NoC architectures. In fact, current books in the context of NoCs are usually specific and presuppose a basic knowledge of NoC architectures. Conversely, this book provides a complete guide for both unskilled readers and researchers working in the area, to acquire not only the basic concepts but also the advanced techniques for improving power, cost and performance metrics of the on-chip communication system.""-Maurizio Palesi, Kore University, Italy.

  15. Recent developments in neurodynamics and their impact on the design of neuro-chips.

    Science.gov (United States)

    Ramacher, U; Schildberg, P

    1993-12-01

    Neurons can be modeled either by equations or differential equations. For the latter, a low-pass filter must be added to the analog function blocks associated with the McCullogh and Pitts type of static neuron in order to provide the time-dependent neuron solution. The low-pass filter enhances stability and enables a time-continuous analog implementation much more compact than that attained with time-discrete analog or pure digital design. A few examples of equations as well as differential equations are known for that part of learning. However, much less than for the recall mode, it is clear how to design learning neuro-chips for temporal pattern processing. It is shown here that a partial differential equation can be used to provide a unified description of both the recall and learning dynamics of a neural network as well as to investigate systematically the VLSI potential for analog time-continuous neuro-chips. It turns out that the recall and learning dynamics can be divided into causal as well as noncausal solutions. The first type of solution includes oscillating or spiking neurons. The second type of solution allows for a much simpler signal representation but leads to the problem of storing the temporal signal of each neuron for as long a time as a single pattern lasts. As this is prohibitive for larger networks and time-varying patterns, the analog VLSI implementation of causal neuron models is suggested.

  16. Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

    Directory of Open Access Journals (Sweden)

    Diana Göhringer

    2012-01-01

    Full Text Available This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC. The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.

  17. An on-chip cardiomyocyte cell network assay for stable drug screening regarding community effect of cell network size.

    Science.gov (United States)

    Kaneko, Tomoyuki; Kojima, Kensuke; Yasuda, Kenji

    2007-09-01

    We investigate the effect of haloperidol on a four-cell and nine-cell cardiomyocyte network on an agarose microchamber array chip to evaluate a cell-based model for drug screening. Using a network of cardiomyocytes whose beating intervals were stable and relatively uniform (they only fluctuated 10% from the mean beating interval), we easily observed the effect of haloperidol on the cell network beating interval 5 min after administering it. We also observed the beating interval returned to its original state 10 min after the haloperidol was washed out of the chip. Although the four-cell network showed the unstable recovery of its beating rhythm after washout of haloperidol, the nine-cell network recovered completely to the stable original beating rhythm even after a second administration of haloperidol. The results indicate the importance of the community size in cell networks used in the stable cell-based screening model. Moreover, they indicate the advantage of using direct cell-based measurements in which the amount of drug administered and the time course over which it is administered are strictly controlled for evaluating the quantitative chemical effects of drugs on cells.

  18. The prediction of maximum temperature for single chips' cooling using artificial neural networks

    Science.gov (United States)

    Ozsunar, Abuzer; Arcaklıoglu, Erol; Nusret Dur, F.

    2009-02-01

    A CFD simulation usually requires extensive computer storage and lengthy computational time. The application of artificial neural network models to thermal management of chips is still limited. In this study, the main objective is to find a neural network solution for obtaining suitable thickness levels and material for a chip subjected to a constant heat power. To achieve this aim a neural network is trained and tested using the results of the CFD program package Fluent. The back-propagation learning algorithm with three different variants, single layer and logistic sigmoid transfer function is employed in the network. By using the weights of the network, various formulations are designed for the output. The network has resulted in R 2 values of 0.999, and the mean% errors smaller than 0.8 and 0.7 for the training and test data, respectively. The analysis is extended for different thickness and input power values. Comparison of some randomly selected results obtained by the neural network model and the CFD program has yielded a maximum error of 1.8%, mean absolute percentage error of 0.55% and R 2 of 0.99994.

  19. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    OpenAIRE

    Lucas Antón Pastur-Romay; Francisco Cedrón; Alejandro Pazos; Ana Belén Porto-Pazos

    2016-01-01

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by D...

  20. Edge chipping resistance and flexural strength of polymer infiltrated ceramic network and resin nanoceramic restorative materials.

    Science.gov (United States)

    Argyrou, Renos; Thompson, Geoffrey A; Cho, Seok-Hwan; Berzins, David W

    2016-09-01

    Two novel restorative materials, a polymer infiltrated ceramic network (PICN) and a resin nanoceramic (RNC), for computer-assisted design and computer-assisted manufacturing (CAD-CAM) applications have recently become commercially available. Little independent evidence regarding their mechanical properties exists to facilitate material selection. The purpose of this in vitro study was to measure the edge chipping resistance and flexural strength of the PICN and RNC materials and compare them with 2 commonly used feldspathic ceramic (FC) and leucite reinforced glass-ceramic (LRGC) CAD-CAM materials that share the same clinical indications. PICN, RNC, FC, and LRGC material specimens were obtained by sectioning commercially available CAD-CAM blocks. Edge chipping test specimens (n=20/material) were adhesively attached to a resin substrate before testing. Edge chips were produced using a 120-degree, sharp, conical diamond indenter mounted on a universal testing machine and positioned 0.1 to 0.7 mm horizontally from the specimen's edge. The chipping force was plotted against distance to the edge, and the data were fitted to linear and quadratic equations. One-way ANOVA determined intergroup differences (α=.05) in edge chipping toughness. Beam specimens (n=22/material) were tested for determining flexural strength using a 3-point bend test. Weibull statistics determined intergroup differences (α=.05). Flexural modulus and work of fracture were also calculated, and 1-way ANOVA determined intergroup differences (α=.05) RESULTS: Significant (Pmaterials for the 4 mechanical properties. Specifically, the material rankings were edge chipping toughness: RNC>LRGC=FC>PICN; flexural strength: RNC=LRGC>PICN>FC; flexural modulus: RNCLRGC=PICN>FC. The RNC material demonstrated superior performance for the mechanical properties tested compared with the other 3 materials. Copyright © 2016 Editorial Council for the Journal of Prosthetic Dentistry. Published by Elsevier Inc. All

  1. Analog very large-scale integrated (VLSI) implementation of a model of amplitude-modulation sensitivity in the auditory brainstem.

    Science.gov (United States)

    van Schaik, A; Meddis, R

    1999-02-01

    An analog very large-scale integrated (VLSI) implementation of a model of signal processing in the auditory brainstem is presented and evaluated. The implementation is based on a model of amplitude-modulation sensitivity in the central nucleus of the inferior colliculus (CNIC) previously described by Hewitt and Meddis [J. Acoust. Soc. Am. 95, 2145-2159 (1994)]. A single chip is used to implement the three processing stages of the model; the inner-hair cell (IHC), cochlear nucleus sustained-chopper, and CNIC coincidence-detection stages. The chip incorporates two new circuits: an IHC circuit and a neuron circuit. The input to the chip is taken from a "silicon cochlea" consisting of a cascade of filters that simulate basilar membrane mechanical frequency selectivity. The chip which contains 142 neurons was evaluated using amplitude-modulated pure tones. Individual cells in the CNIC stage demonstrate bandpass rate-modulation responses using these stimuli. The frequency of modulation is represented spatially in an array of these cells as the location of the cell generating the highest rate of action potentials. The chip processes acoustic signals in real time and demonstrates the feasibility of using analog VLSI to build and test auditory models that use large numbers of component neurons.

  2. NUMERICAL SIMULATION OF DIGITAL VLSI TOTAL DOSE FUNCTIONAL FAILURES

    Directory of Open Access Journals (Sweden)

    O. A. Kalashnikov

    2016-10-01

    Full Text Available The technique for numerical simulation of digital VLSI total dose failures is presented, based on fuzzy logic sets theory. It assumes transfer from boolean logic model of a VLSI with values {0,1} to fuzzy model with continuous interval [0,1], and from boolean logic functions to continuous minimax functions. The technique is realized as a calculation system and allows effective estimating of digital VLSI radiation behavior without experimental investigation.

  3. Analog VLSI implementation of resonate-and-fire neuron.

    Science.gov (United States)

    Nakada, Kazuki; Asai, Tetsuya; Hayashi, Hatsuo

    2006-12-01

    We propose an analog integrated circuit that implements a resonate-and-fire neuron (RFN) model based on the Lotka-Volterra (LV) system. The RFN model is a spiking neuron model that has second-order membrane dynamics, and thus exhibits fast damped subthreshold oscillation, resulting in the coincidence detection, frequency preference, and post-inhibitory rebound. The RFN circuit has been derived from the LV system to mimic such dynamical behavior of the RFN model. Through circuit simulations, we demonstrate that the RFN circuit can act as a coincidence detector and a band-pass filter at circuit level even in the presence of additive white noise and background random activity. These results show that our circuit is expected to be useful for very large-scale integration (VLSI) implementation of functional spiking neural networks.

  4. Silicon-based all-optical multi microring network-on-chip.

    Science.gov (United States)

    Pintus, Paolo; Contu, Pietro; Raponi, Pier Giorgio; Cerutti, Isabella; Andriolli, Nicola

    2014-02-15

    An optical multi microring network-on-chip (MMR NoC) is proposed and evaluated through numerical simulations. The network architecture consists of a central resonating microring with local microrings connected to the input/output ports. A mathematical model based on the transfer matrix method is used to assess the MMR NoC performance and to analyze the fabrication tolerances. Results show that the proposed architecture exhibits a limited coherent crosstalk with a bandwidth suitable for 10  Gb/s signals, and it is robust to coupling ratio variations and ring radii fabrication inaccuracies.

  5. Support for Programming Models in Network-on-Chip-based Many-core Systems

    DEFF Research Database (Denmark)

    Rasmussen, Morten Sleth

    This thesis addresses aspects of support for programming models in Network-on- Chip-based many-core architectures. The main focus is to consider architectural support for a plethora of programming models in a single system. The thesis has three main parts. The first part considers parallelization...... models to be supported by a single architecture. The architecture features a specialized network interface processor which allows extensive configurability of the memory system. Based on this architecture, a detailed implementation of the cache coherent shared memory programming model is presented...

  6. Time-Predictable Communication on a Time-Division Multiplexing Network-on-Chip Multicore

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo

    This thesis presents time-predictable inter-core communication on a multicore platform with a time-division multiplexing (TDM) network-on-chip (NoC) for hard real-time systems. The thesis is structured as a collection of papers that contribute within the areas of: reconfigurable TDM NoCs, static...... of the Argo NoC network interface (NI) that supports instantaneous reconfiguration, a TDM traffic scheduler that generates virtual circuit (VC) configurations for the Argo NoC, and software functions for two types of intercore communication. The new generation of the Argo NoC adds the capability...

  7. Networking challenges and prospective impact of broadcast-oriented wireless networkson- chip

    OpenAIRE

    Abadal Cavallé, Sergi; Nemirovsky, Mario; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto

    2015-01-01

    The cost of broadcast has been constraining the design of manycore processors and of the algorithms that run upon them. However, as on-chip RF technologies allow the design of small-footprint and high-bandwidth antennas and transceivers, native low-latency (a few clock cycles) and low-power (a few pJ/bit) broadcast support through wireless communication can be envisaged. In this paper, we analyze the main networking design aspects and challenges of Broadcast-oriented Wireless Network-on-Ch...

  8. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Schoeberl, Martin; Sørensen, Rasmus Bo

    2016-01-01

    In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing...... (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result...

  9. VLSI 'smart' I/O module development

    Science.gov (United States)

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  10. TECHNOLOGY MAPPING TOOL FOR VLSI CAD

    Directory of Open Access Journals (Sweden)

    D. I. Cheremisinov

    2017-01-01

    Full Text Available Technology mapping program implements a sequential circuit using the gates of a particular technology library. It is an integral component of any automated VLSI circuit design flow. The structure of the program for solving the technology mapping problem and formats of the source and result data are presented. Models of intermediate representations of the sequential circuit and their conversions are described. Technology mapping is a stage of logic synthesis and it is viewed as the transformation of a functional (i.e., algebraic circuit specification into a gate (i.e., netlist specification. The program is included as project operations in the VLSI CAD system for energy-saving logical synthesis developed in the United Institute of Informatics Problems of NAS of Belarus.

  11. VLSI Architectures For Syntactic Image Analysis

    Science.gov (United States)

    Chiang, Y. P.; Fu, K. S.

    1984-01-01

    Earley's algorithm has been commonly used for the parsing of general context-free languages and error-correcting parsing in syntactic pattern recognition. The time complexity for parsing is 0(n3). In this paper we present a parallel Earley's recognition algorithm in terms of "x*" operation. By restricting the input context-free grammar to be X-free, we are able to implement this parallel algorithm on a triangular shape VLSI array. This system has an efficient way of moving data to the right place at the right time. Simulation results show that this system can recognize a string with length n in 2n+1 system time. We also present an error-correcting recognition algorithm. The parallel error-correcting recognition algorithm has also been im-plemented on a triangular VLSI array. This array recognizes an erroneous string length n in time 2n+1 and gives the correct error count. Applications of the proposed VLSI architectures to image analysis are illus-trated by examples.

  12. An Asynchronous Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia

    Multi-processor architectures using networks-on-chip (NOCs) for communication are becoming the standard approach in the development of embedded systems and general purpose platforms. Typically, multi-processor platforms follow a globally asynchronous locally synchronous (GALS) timing organization...... more flexible timing within its structure, to address signal distribution issues, using a network of synchronous routers. NOCs consist of a switching structure of routers connected by links, with network interfaces (NIs) that connect the processors to the switching structure. Argo uses a novel NI...... design that supports time-predictability, and asynchronous routers that form a time-elastic network. The NI design integrates the DMA functionality and the TDM schedule, and uses dual-ported local memories. The routers combine the router functionality and asynchronous elastic behavior. They also use...

  13. Analysis of Photonic Networks for a Chip Multiprocessor Using Scientific Applications

    Energy Technology Data Exchange (ETDEWEB)

    Kamil, Shoaib A; Hendry, Gilbert; Biberman, Aleksandr; Chan, Johnnie; Lee, Benjamin G.; Mohiyuddin, Marghoob; Jain, Ankit; Bergman, Keren; Carloni, Luca; Kubiatowicz, John; Oliker, Leonid; Shalf, John

    2009-01-31

    As multiprocessors scale to unprecedented numbers of cores in order to sustain performance growth, it is vital that these gains are not nullified by high energy consumption from inter-core communication. With recent advances in 3D Integration CMOS technology, the possibility for realizing hybrid photonic-electronic networks-on-chip warrants investigating real application traces on functionally comparable photonic and electronic network designs. We present a comparative analysis using both synthetic benchmarks as well as real applications, run through detailed cycle accurate models implemented under the OMNeT++ discrete event simulation environment. Results show that when utilizing standard process-to-processor mapping methods, this hybrid network can achieve 75X improvement in energy efficiency for synthetic benchmarks and up to 37X improvement for real scientific applications, defined as network performance per energy spent, over an electronic mesh for large messages across a variety of communication patterns.

  14. Fish and chips: implementation of a neural network model into computer chips to maximize swimming efficiency in autonomous underwater vehicles.

    Science.gov (United States)

    Blake, R W; Ng, H; Chan, K H S; Li, J

    2008-09-01

    Recent developments in the design and propulsion of biomimetic autonomous underwater vehicles (AUVs) have focused on boxfish as models (e.g. Deng and Avadhanula 2005 Biomimetic micro underwater vehicle with oscillating fin propulsion: system design and force measurement Proc. 2005 IEEE Int. Conf. Robot. Auto. (Barcelona, Spain) pp 3312-7). Whilst such vehicles have many potential advantages in operating in complex environments (e.g. high manoeuvrability and stability), limited battery life and payload capacity are likely functional disadvantages. Boxfish employ undulatory median and paired fins during routine swimming which are characterized by high hydromechanical Froude efficiencies (approximately 0.9) at low forward speeds. Current boxfish-inspired vehicles are propelled by a low aspect ratio, 'plate-like' caudal fin (ostraciiform tail) which can be shown to operate at a relatively low maximum Froude efficiency (approximately 0.5) and is mainly employed as a rudder for steering and in rapid swimming bouts (e.g. escape responses). Given this and the fact that bioinspired engineering designs are not obligated to wholly duplicate a biological model, computer chips were developed using a multilayer perception neural network model of undulatory fin propulsion in the knifefish Xenomystus nigri that would potentially allow an AUV to achieve high optimum values of propulsive efficiency at any given forward velocity, giving a minimum energy drain on the battery. We envisage that externally monitored information on flow velocity (sensory system) would be conveyed to the chips residing in the vehicle's control unit, which in turn would signal the locomotor unit to adopt kinematics (e.g. fin frequency, amplitude) associated with optimal propulsion efficiency. Power savings could protract vehicle operational life and/or provide more power to other functions (e.g. communications).

  15. Analisis Unjuk Kerja Flow Control pada Network on Chip dalam Beberapa Kondisi Jaringan

    Directory of Open Access Journals (Sweden)

    Muhammad Hizrian Hizburrahman

    2015-12-01

    Full Text Available Network on Chip ialah teknik yang digunakan di System on Chip sebagai pengganti shared bus dan direct point – to – point. Pada Network on Chip terdapat parameter desain dan parameter performansi jaringan. Penentuan parameter desain dan perkembangan dari jaringan dapat menimbulkan permasalahan pada jaringan seperti congestion dan saturasi yang menyebabkan paket hilang. Congestion dapat diatasi dengan menggunakan flow control yang tepat. Pada penelitian ini dilakukan analisis terhadap tiga teknik flow control yaitu Stall / Go , Ack / Nack serta Dynamic Multi Level yang diterapkan pada dua model jaringan. Model jaringan yang pertama untuk mengamati pengaruh flow control terhadap saturasi jaringan dan model kedua untuk mengamati pengaruh flow control terhadap perubahan parameter desain dan mendapatkan teknik flow control yang paling optimal dan pengaruh perubahan parameter desain terhadap parameter performansi jaringan. Dari hasil penelitian, jaringan yang menggunakan flow control tidak mengalami saturasi. Dimana flow control Stall / Go merupakan flow control terbaik dalam meningkatkan throughput sebesar 21.08% , 65.33%, 151% dan 13.37% , menurunkan delay sebesar 407.85, 606.03, 1631.95, 322.59 cycles, menurunkan penggunaan daya sebesar 68.67%, 61.33%, 49.93%, 68.22% untuk masing – masing perubahan ukuran jaringan, perubahan packet injection rate, perubahan ukuran paket dan perubahan ukuran buffer.

  16. Stereolithographic hydrogel printing of 3D culture chips with biofunctionalized complex 3D perfusion networks.

    Science.gov (United States)

    Zhang, Rujing; Larsen, Niels B

    2017-12-05

    Three-dimensional (3D) in vitro models capturing both the structural and dynamic complexity of the in vivo situation are in great demand as an alternative to animal models. Despite tremendous progress in engineering complex tissue/organ models in the past decade, approaches that support the required freedom in design, detail and chemistry for fabricating truly 3D constructs have remained limited. Here, we report a stereolithographic high-resolution 3D printing technique utilizing poly(ethylene glycol) diacrylate (PEGDA, MW 700) to manufacture diffusion-open and mechanically stable hydrogel constructs as self-contained chips, where confined culture volumes are traversed and surrounded by perfusable vascular-like networks. An optimized resin formulation enables printing of hydrogel chips holding perfusable microchannels with a cross-section as small as 100 μm × 100 μm, and the printed microchannels can be steadily perfused for at least one week. In addition, the integration of multiple independently perfusable and structurally stable channel systems further allows for easy combination of different bulk material volumes at exact relative spatial positions. We demonstrate this structural and material flexibility by embedding a highly compliant cell-laden gelatin hydrogel within the confines of a 3D printed resilient PEGDA hydrogel chip of intermediate compliance. Overall, our proposed strategy represents an automated, cost-effective and high resolution technique to manufacture complex 3D constructs containing microfluidic perfusion networks for advanced in vitro models.

  17. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    Science.gov (United States)

    Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

    2016-01-01

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure–Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods. PMID:27529225

  18. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  19. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

    Directory of Open Access Journals (Sweden)

    Lucas Antón Pastur-Romay

    2016-08-01

    Full Text Available Over the past decade, Deep Artificial Neural Networks (DNNs have become the state-of-the-art algorithms in Machine Learning (ML, speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs. All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS, Quantitative Structure–Activity Relationship (QSAR research, protein structure prediction and genomics (and other omics data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  20. Mode-Division Multiplexing for Silicon Photonic Network-on-Chip

    Science.gov (United States)

    Wu, Xinru; Huang, Chaoran; Xu, Ke; Shu, Chester; Tsang, Hon Ki

    2017-08-01

    Optical interconnect is a potential solution to attain the large bandwidth on-chip communications needed in high performance computers in a low power and low cost manner. Mode-division multiplexing (MDM) is an emerging technology that scales the capacity of a single wavelength carrier by the number of modes in a multimode waveguide, and is attractive as a cost-effective means for high bandwidth density on-chip communications. Advanced modulation formats with high spectral efficiency in MDM networks can further improve the data rates of the optical link. Here, we demonstrate an intra-chip MDM communications link employing advanced modulation formats with two waveguide modes. We demonstrate a compact single wavelength carrier link that is expected to support 2x100 Gb/s mode multiplexed capacity. The network comprised integrated microring modulators at the transmitter, mode multiplexers, multimode waveguide interconnect, mode demultiplexers and integrated germanium on silicon photodetectors. Each of the mode channels achieves 100 Gb/s line rate with 84 Gb/s net payload data rate at 7% overhead for hard-decision forward error correction (HD-FEC) in the OFDM/16-QAM signal transmission.

  1. Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications.

    Science.gov (United States)

    Pastur-Romay, Lucas Antón; Cedrón, Francisco; Pazos, Alejandro; Porto-Pazos, Ana Belén

    2016-08-11

    Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure-Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron-Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

  2. A Bio-Inspired Hybrid Thermal Management Approach for 3-D Network-on-Chip Systems.

    Science.gov (United States)

    Dash, Ranjita; Risco-Martin, Jose L; Turuk, Ashok Kumar; Ayala, Jose L; Pangracious, Vinod; Majumdar, Amartya

    2017-12-01

    3-D network-on-chip (NoC) systems are getting popular among the integrated circuit (IC) manufacturer because of reduced latency, heterogeneous integration of technologies on a single chip, high yield, and consumption of less interconnecting power. However, the addition of functional units in the -direction has resulted in higher on-chip temperature and appearance of local hotspots on the die. The increase in temperature degrades the performance, lifetime, and reliability, and increases the maintenance cost of 3-D ICs. To keep the heat within an acceptable limit, floorplanning is the widely accepted solution. Proper arrangement of functional units across different layers can lead to uniform thermal distribution in the chip. For systems with high density of elements, few hotspots cannot be eliminated in the floorplanning approach. To overcome, liquid microchannel cooling technology has emerged as an efficient and scalable solution for 3-D NoC. In this paper, we propose a novel hybrid algorithm combining both floorplanning, and liquid microchannel placement to alleviate the hotspots in high-density systems. A mathematical model is proposed to deal with heat transfer due to diffusion and convention. The proposed approach is independent of topology. Three different topologies: 3-D stacked homogeneous mesh architecture, 3-D stacked heterogeneous mesh architecture, and 3-D stacked ciliated mesh architecture are considered to check the effectiveness of the proposed algorithm in hotspot reduction. A thermal comparison is made with and without the proposed thermal management approach for the above architectures considered. It is observed that there is a significant reduction in on-chip temperature when the proposed thermal management approach is applied.

  3. A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks

    Directory of Open Access Journals (Sweden)

    Jim Harkin

    2009-01-01

    Full Text Available FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE, incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

  4. On-Chip SDM Switching for Unicast, Multicast and Traffic Grooming in Data Center Networks

    DEFF Research Database (Denmark)

    Kamchevska, Valerija; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    This paper reports on the use of a novel photonic integrated circuit that facilitates multicast and grooming in an optical data center architecture. The circuit allows for on-chip spatial multiplexing and demultiplexing as well as fiber core switching. Using this device, we experimentally verify...... that multicast and/or grooming can be successfully performed along the full range of output ports, for different group size and different power ratio. Moreover, we experimentally demonstrate SDM transmission and 5 Tbit/s switching using the on-chip fiber switch with integrated fan-in/fan-out devices and achieve...... errorfree performance (BER≤10-9) for a network scenario including simultaneous unicast/multicast switching and traffic grooming....

  5. DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

    Science.gov (United States)

    Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

    2017-07-18

    Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

  6. A Notation for Describing Multiple Views of VLSI Circuits

    Science.gov (United States)

    1988-06-01

    leaf In the functional programming language pFP cells or abstract objects) and a set of relations among [ Sheeran 83] the behavior specification implies a...A raduate VLSI design class has employed the notation in the design of modules com- [ Sheeran 83] M. Sheeran , "jvFP - An Algebraic VLSI prising a

  7. Trends and challenges in VLSI technology scaling towards 100 nm

    NARCIS (Netherlands)

    Rusu, S.; Sachdev, M.; Svensson, C.; Nauta, Bram

    Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm

  8. Parallel optimization algorithms and their implementation in VLSI design

    Science.gov (United States)

    Lee, G.; Feeley, J. J.

    1991-01-01

    Two new parallel optimization algorithms based on the simplex method are described. They may be executed by a SIMD parallel processor architecture and be implemented in VLSI design. Several VLSI design implementations are introduced. An application example is reported to demonstrate that the algorithms are effective.

  9. Reducing weight precision of convolutional neural networks towards large-scale on-chip image recognition

    Science.gov (United States)

    Ji, Zhengping; Ovsiannikov, Ilia; Wang, Yibing; Shi, Lilong; Zhang, Qiang

    2015-05-01

    In this paper, we develop a server-client quantization scheme to reduce bit resolution of deep learning architecture, i.e., Convolutional Neural Networks, for image recognition tasks. Low bit resolution is an important factor in bringing the deep learning neural network into hardware implementation, which directly determines the cost and power consumption. We aim to reduce the bit resolution of the network without sacrificing its performance. To this end, we design a new quantization algorithm called supervised iterative quantization to reduce the bit resolution of learned network weights. In the training stage, the supervised iterative quantization is conducted via two steps on server - apply k-means based adaptive quantization on learned network weights and retrain the network based on quantized weights. These two steps are alternated until the convergence criterion is met. In this testing stage, the network configuration and low-bit weights are loaded to the client hardware device to recognize coming input in real time, where optimized but expensive quantization becomes infeasible. Considering this, we adopt a uniform quantization for the inputs and internal network responses (called feature maps) to maintain low on-chip expenses. The Convolutional Neural Network with reduced weight and input/response precision is demonstrated in recognizing two types of images: one is hand-written digit images and the other is real-life images in office scenarios. Both results show that the new network is able to achieve the performance of the neural network with full bit resolution, even though in the new network the bit resolution of both weight and input are significantly reduced, e.g., from 64 bits to 4-5 bits.

  10. Routing in Wireless Sensor Networks Using an Ant Colony Optimization (ACO) Router Chip.

    Science.gov (United States)

    Okdem, Selcuk; Karaboga, Dervis

    2009-01-01

    Wireless Sensor Networks consisting of nodes with limited power are deployed to gather useful information from the field. In WSNs it is critical to collect the information in an energy efficient manner. Ant Colony Optimization, a swarm intelligence based optimization technique, is widely used in network routing. A novel routing approach using an Ant Colony Optimization algorithm is proposed for Wireless Sensor Networks consisting of stable nodes. Illustrative examples, detailed descriptions and comparative performance test results of the proposed approach are included. The approach is also implemented to a small sized hardware component as a router chip. Simulation results show that proposed algorithm provides promising solutions allowing node designers to efficiently operate routing tasks.

  11. Learning transcriptional networks from the integration of ChIP-chip and expression data in a non-parametric model.

    Science.gov (United States)

    Youn, Ahrim; Reiss, David J; Stuetzle, Werner

    2010-08-01

    We have developed LeTICE (Learning Transcriptional networks from the Integration of ChIP-chip and Expression data), an algorithm for learning a transcriptional network from ChIP-chip and expression data. The network is specified by a binary matrix of transcription factor (TF)-gene interactions partitioning genes into modules and a background of genes that are not involved in the transcriptional regulation. We define a likelihood of a network, and then search for the network optimizing the likelihood. We applied LeTICE to the location and expression data from yeast cells grown in rich media to learn the transcriptional network specific to the yeast cell cycle. It found 12 condition-specific TFs and 15 modules each of which is highly represented with functions related to particular phases of cell-cycle regulation. Our algorithm is available at http://linus.nci.nih.gov/Data/YounA/LeTICE.zip

  12. Intelligent On/Off Dynamic Link Management for On-Chip Networks

    Directory of Open Access Journals (Sweden)

    Andreas G. Savva

    2012-01-01

    Full Text Available Networks-on-chips (NoCs provide scalable on-chip communication and are expected to be the dominant interconnection architectures in multicore and manycore systems. Power consumption, however, is a major limitation in NoCs today, and researchers have been constantly working on reducing both dynamic and static power. Among the NoC components, links that connect the NoC routers are the most power-hungry components. Several attempts have been made to reduce the link power consumption at both the circuit level and the system level. Most past research efforts have proposed selective on/off link state switching based on system-level information based on link utilization levels. Most of these proposed algorithms focus on a pessimistic and simple static threshold mechanism which determines whether or not a link should be turned on/off. This paper presents an intelligent dynamic power management policy for NoCs with improved predictive abilities based on supervised online learning of the system status (i.e., expected future utilization link levels, where links are turned off and on via the use of a small and scalable neural network. Simulation results with various synthetic traffic models over various network topologies show that the proposed work can reach up to 13% power savings when compared to a trivial threshold computation, at very low (<4% hardware overheads.

  13. Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

    Directory of Open Access Journals (Sweden)

    Alireza Monemi

    2015-01-01

    Full Text Available Network-on-Chip (NoC is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs. However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS. We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA. The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

  14. Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

    Directory of Open Access Journals (Sweden)

    Fernando Gutierrez

    2017-03-01

    Full Text Available To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC. With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

  15. BER evaluation of a low-crosstalk silicon integrated multi-microring network-on-chip.

    Science.gov (United States)

    Gambini, Fabrizio; Faralli, Stefano; Pintus, Paolo; Andriolli, Nicola; Cerutti, Isabella

    2015-06-29

    The operation of an integrated silicon-photonics multi-microring network-on-chip (NoC) is experimentally demonstrated in terms of transmission spectra and bit error rates at 10 Gb/s. The integrated NoC consists of 8 thermally tuned microrings coupled to a central ring. The switching functionalities are tested with concurrent transmissions at both the same and different wavelengths. Experimental results validate the analytical model based on the transfer matrix method. BER measurements show performance up to 10(-9) at 10 Gb/s with limited crosstalk and penalty (below 0.5 dB) induced by an interfering transmission.

  16. A Metaheuristic Scheduler for Time Division Multiplexed Network-on-Chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Sparsø, Jens; Pedersen, Mark Ruvald

    This report presents a metaheuristic scheduler for inter-processor communication in multi-core platforms using time division multiplexed (TDM) networks on chip (NOC). Input to the scheduler is a specification of the target multi-core platform and a specification of the application. Compared...... that this is possible with only negligible impact on the schedule period. We evaluate the scheduler with seven different applications from the MCSL NOC benchmark suite. We observe that the metaheuristics perform better than the greedy solution. In the special case of all-to-all communication with equal bandwidths...

  17. Composable Flexible Real-time Packet Scheduling for Networks on-Chip

    Science.gov (United States)

    2012-05-16

    the packets at the flow’s source. 2) Preemptive EDF Scheduling: As wormhole flow control allows sending packets sent flit-by-flit, we could employ a...analysis of wormhole based heterogeneous noc. In Proceedings of the 2011 Fifth ACM/IEEE International Symposium on Networks-on-Chip, NOCS ’11, pages 161–168...Computer Architecture, ISCA ’08, pages 89–100, Washington, DC, USA, 2008. IEEE Computer Society. [14] Sunggu Lee. Real-time wormhole channels. Journal of

  18. A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Brandner, Florian; Sparsø, Jens

    2012-01-01

    This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We...... consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits - all with the same bandwidth - between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper...

  19. An Efficient Radio Access Control Mechanism for Wireless Network-On-Chip Architectures

    Directory of Open Access Journals (Sweden)

    Maurizio Palesi

    2015-03-01

    Full Text Available Modern systems-on-chip (SoCs today contain hundreds of cores, and this number is predicted to reach the thousands by the year 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The network-on-chip (NoC design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues, such as the performance limitations of long interconnects and integration of large number of cores on a chip. Recently, new communication technologies based on the NoC concept have emerged with the aim of improving the scalability limitations of conventional NoC-based architectures. Among them, wireless NoCs (WiNoCs use the radio medium for reducing the performance and energy penalties of long-range and multi-hop communications. As the radio medium can be accessed by a single transmitter at a time, a radio access control mechanism (RACM is needed. In this paper, we present a novel RACM, which allows one to improve both the performance and energy figures of the WiNoC. Experiments, carried out on both synthetic and real traffic scenarios, have shown the effectiveness of the proposed RACM. On average, a 30% reduction in communication delay and a 25% energy savings have been observed when the proposed RACM is applied to a known WiNoC architecture.

  20. Defense Against Chip Cloning Attacks Based on Fractional Hopfield Neural Networks.

    Science.gov (United States)

    Pu, Yi-Fei; Yi, Zhang; Zhou, Ji-Liu

    2017-06-01

    This paper presents a state-of-the-art application of fractional hopfield neural networks (FHNNs) to defend against chip cloning attacks, and provides insight into the reason that the proposed method is superior to physically unclonable functions (PUFs). In the past decade, PUFs have been evolving as one of the best types of hardware security. However, the development of the PUFs has been somewhat limited by its implementation cost, its temperature variation effect, its electromagnetic interference effect, the amount of entropy in it, etc. Therefore, it is imperative to discover, through promising mathematical methods and physical modules, some novel mechanisms to overcome the aforementioned weaknesses of the PUFs. Motivated by this need, in this paper, we propose applying the FHNNs to defend against chip cloning attacks. At first, we implement the arbitrary-order fractor of a FHNN. Secondly, we describe the implementation cost of the FHNNs. Thirdly, we propose the achievement of the constant-order performance of a FHNN when ambient temperature varies. Fourthly, we analyze the electrical performance stability of the FHNNs under electromagnetic disturbance conditions. Fifthly, we study the amount of entropy of the FHNNs. Lastly, we perform experiments to analyze the pass-band width of the fractor of an arbitrary-order FHNN and the defense against chip cloning attacks capability of the FHNNs. In particular, the capabilities of defense against chip cloning attacks, anti-electromagnetic interference, and anti-temperature variation of a FHNN are illustrated experimentally in detail. Some significant advantages of the FHNNs are that their implementation cost is considerably lower than that of the PUFs, their electrical performance is much more stable than that of the PUFs under different temperature conditions, their electrical performance stability of the FHNNs under electromagnetic disturbance conditions is much more robust than that of the PUFs, and their amount of

  1. Artwork Analysis Tools for VLSI Circuits.

    Science.gov (United States)

    1980-06-01

    derived frcm the art- work.i~nFo :.- Is zr Code DI t pecal Sculnfv CLA a uPICAT OP T0416 PA*6WM Dine Bftee AMA& -’M Artwork Analysis Tools for VLSI Circuits... code of the program and in pre-generated bit tables. The design rules thcmselves are not input directly into the checker. The rules were interpreted...circuit simulation is swich -level sintulation. In this type, transistors are modeled as switches that are either on or off. Fixed delays are a%.ociated

  2. InP on SOI devices for optical communication and optical network on chip

    Science.gov (United States)

    Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

    2011-01-01

    For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

  3. Analysis and design of networks-on-chip under high process variation

    CERN Document Server

    Ezz-Eldin, Rabab; Hamed, Hesham F A

    2015-01-01

    This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. Demonstrates the impact of process variation on Networks-on-Chip of different topologies;  Includes an overview of the sy...

  4. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  5. Designing 2D and 3D network-on-chip architectures

    CERN Document Server

    Tatas, Konstantinos; Soudris, Dimitrios; Jantsch, Axel

    2014-01-01

    This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

  6. A low overhead load balancing router for network-on-chip

    Science.gov (United States)

    Xiaofeng, Zhou; Lu, Liu; Zhangming, Zhu; Duan, Zhou

    2016-11-01

    The design of a router in a network-on-chip (NoC) system has an important impact on some performance criteria. In this paper, we propose a low overhead load balancing router (LOLBR) for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance toggle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively. Project supported by the National Natural Science Foundation of China (Nos. 61474087, 61322405, 61376039).

  7. Pre-Allocation Based Flow Control Scheme for Networks-On-Chip

    Science.gov (United States)

    Lin, Shijun; Su, Li; Su, Haibo; Jin, Depeng; Zeng, Lieguang

    Based on the traffic predictability characteristic of Networks-on-Chip (NoC), we propose a pre-allocation based flow control scheme to improve the performance of NoC. In this scheme, routes are pre-allocated and the injection rates of all routes are regulated at the traffic sources according to the average available bandwidths in the links. Then, the number of packets in the network is decreased and thus, the congestion probability is reduced and the communication performance is improved. Simulation results show that this scheme greatly increases the throughput and cuts down the average latency with little area and energy overhead, compared with the switch-to-switch flow control scheme.

  8. Book Titled Autonomic Networking-on-Chip: Bio-Inspired Specification, Development, and Verification: An Introduction

    Directory of Open Access Journals (Sweden)

    Phan Cong Vinh

    2015-03-01

    Full Text Available Despite the growing mainstream importance and unique advantages of autonomic networking-onchip (ANoC technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system. The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent researchers in industry and academia around the world. A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are now ready to learn how to specify, develop, and verify ANoC using rigorous approaches.

  9. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  10. The Implications of VLSI ROM Chips on Numerical Analysis.

    Science.gov (United States)

    1982-01-08

    pattern transferred onto the silicon wafer. That is, they are manufactured directly. The advatage of this approach is extremely low cost when produced...the writing of an operating system, and thuis, is impractical for the numerical j analyst. As software design aide become available, this technique may...rare for anyone to write machine code. Obviously, some type of translation j is made from another language. At the elementary level, an assembly

  11. Seeing chips : analog VLSI circuits for computer vision

    OpenAIRE

    Koch, Christof

    1989-01-01

    Vision is simple. We open our eyes and, instantly, the world surrounding us is perceived in all its splendor. Yet Artificial Intelligence has been trying with very limited success for over 20 years to endow machines with similar abilities. A large van, filled with computers and driving unguided at a mile per hour across gently sloping hills in Colorado and using a laser-range system to “see” is the most we have accomplished so far. On the other hand, computers can play a decent game of chess ...

  12. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  13. Single-chip ring resonator-based 1 x 8 optical beam forming network in CMOS-compatible waveguide technology

    NARCIS (Netherlands)

    Zhuang, L.; Roeloffzen, C.G.H.; Heideman, Rene; Borreman, A.; Meijerink, Arjan; van Etten, Wim

    2007-01-01

    Optical ring resonators (ORRs) are good candidates to provide continuously tunable delay in optical beam forming networks (OBFNs) for phased array antenna systems. Delay and splitting/combining elements can be integrated on a single optical chip to form an OBFN. A state-of-the-art ring resonator-

  14. A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Pezzarossa, Luca; Schoeberl, Martin

    2017-01-01

    to all slave nodes for a 16-core plat- form in between 500 and 3500 clock cycles. The results also show that the hardware cost for an FPGA implementation of our architecture is considerably smaller than other network-on-chips with similar re- configuration functionalities, and that the worst-case time...

  15. Bottom-Up Abstract Modelling of Optical Networks-on-Chip: From Physical to Architectural Layer

    Directory of Open Access Journals (Sweden)

    Alberto Parini

    2012-01-01

    Full Text Available This work presents a bottom-up abstraction procedure based on the design-flow FDTD + SystemC suitable for the modelling of optical Networks-on-Chip. In this procedure, a complex network is decomposed into elementary switching elements whose input-output behavior is described by means of scattering parameters models. The parameters of each elementary block are then determined through 2D-FDTD simulation, and the resulting analytical models are exported within functional blocks in SystemC environment. The inherent modularity and scalability of the S-matrix formalism are preserved inside SystemC, thus allowing the incremental composition and successive characterization of complex topologies typically out of reach for full-vectorial electromagnetic simulators. The consistency of the outlined approach is verified, in the first instance, by performing a SystemC analysis of a four-input, four-output ports switch and making a comparison with the results of 2D-FDTD simulations of the same device. Finally, a further complex network encompassing 160 microrings is investigated, the losses over each routing path are calculated, and the minimum amount of power needed to guarantee an assigned BER is determined. This work is a basic step in the direction of an automatic technology-aware network-level simulation framework capable of assembling complex optical switching fabrics, while at the same time assessing the practical feasibility and effectiveness at the physical/technological level.

  16. Decoding Network Structure in On-Chip Integrated Flow Cells with Synchronization of Electrochemical Oscillators.

    Science.gov (United States)

    Jia, Yanxin; Kiss, István Z

    2017-04-07

    The analysis of network interactions among dynamical units and the impact of the coupling on self-organized structures is a challenging task with implications in many biological and engineered systems. We explore the coupling topology that arises through the potential drops in a flow channel in a lab-on-chip device that accommodates chemical reactions on electrode arrays. The networks are revealed by analysis of the synchronization patterns with the use of an oscillatory chemical reaction (nickel electrodissolution) and are further confirmed by direct decoding using phase model analysis. In dual electrode configuration, a variety coupling schemes, (uni- or bidirectional positive or negative) were identified depending on the relative placement of the reference and counter electrodes (e.g., placed at the same or the opposite ends of the flow channel). With three electrodes, the network consists of a superposition of a localized (upstream) and global (all-to-all) coupling. With six electrodes, the unique, position dependent coupling topology resulted spatially organized partial synchronization such that there was a synchrony gradient along the quasi-one-dimensional spatial coordinate. The networked, electrode potential (current) spike generating electrochemical reactions hold potential for construction of an in-situ information processing unit to be used in electrochemical devices in sensors and batteries.

  17. Decoding Network Structure in On-Chip Integrated Flow Cells with Synchronization of Electrochemical Oscillators

    Science.gov (United States)

    Jia, Yanxin; Kiss, István Z.

    2017-04-01

    The analysis of network interactions among dynamical units and the impact of the coupling on self-organized structures is a challenging task with implications in many biological and engineered systems. We explore the coupling topology that arises through the potential drops in a flow channel in a lab-on-chip device that accommodates chemical reactions on electrode arrays. The networks are revealed by analysis of the synchronization patterns with the use of an oscillatory chemical reaction (nickel electrodissolution) and are further confirmed by direct decoding using phase model analysis. In dual electrode configuration, a variety coupling schemes, (uni- or bidirectional positive or negative) were identified depending on the relative placement of the reference and counter electrodes (e.g., placed at the same or the opposite ends of the flow channel). With three electrodes, the network consists of a superposition of a localized (upstream) and global (all-to-all) coupling. With six electrodes, the unique, position dependent coupling topology resulted spatially organized partial synchronization such that there was a synchrony gradient along the quasi-one-dimensional spatial coordinate. The networked, electrode potential (current) spike generating electrochemical reactions hold potential for construction of an in-situ information processing unit to be used in electrochemical devices in sensors and batteries.

  18. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    Directory of Open Access Journals (Sweden)

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  19. Advanced plasma etching processes for dielectric materials in VLSI technology

    Science.gov (United States)

    Wang, Juan Juan

    Manufacturable plasma etching processes for dielectric materials have played an important role in the Integrated Circuits (IC) industry in recent decades. Dielectric materials such as SiO2 and SiN are widely used to electrically isolate the active device regions (like the gate, source and drain from the first level of metallic interconnects) and to isolate different metallic interconnect levels from each other. However, development of new state-of-the-art etching processes is urgently needed for higher aspect ratio (oxide depth/hole diameter---6:1) in Very Large Scale Integrated (VLSI) circuits technology. The smaller features can provide greater packing density of devices on a single chip and greater number of chips on a single wafer. This dissertation focuses on understanding and optimizing of several key aspects of etching processes for dielectric materials. The challenges are how to get higher selectivity of oxide/Si for contact and oxide/TiN for vias; tight Critical Dimension (CD) control; wide process margin (enough over-etch); uniformity and repeatability. By exploring all of the parameters for the plasma etch process, the key variables are found and studied extensively. The parameters investigated here are Power, Pressure, Gas ratio, and Temperature. In particular, the novel gases such as C4F8, C5F8, and C4F6 were studied in order to meet the requirements of the design rules. We also studied CF4 that is used frequently for dielectric material etching in the industry. Advanced etch equipment was used for the above applications: the medium-density plasma tools (like Magnet-Enhanced Reactive Ion Etching (MERIE) tool) and the high-density plasma tools. By applying the Design of Experiments (DOE) method, we found the key factors needed to predict the trend of the etch process (such as how to increase the etch rates, selectivity, etc.; and how to control the stability of the etch process). We used JMP software to analyze the DOE data. The characterization of the

  20. Neural networks for data compression and invariant image recognition

    Science.gov (United States)

    Gardner, Sheldon

    1989-01-01

    An approach to invariant image recognition (I2R), based upon a model of biological vision in the mammalian visual system (MVS), is described. The complete I2R model incorporates several biologically inspired features: exponential mapping of retinal images, Gabor spatial filtering, and a neural network associative memory. In the I2R model, exponentially mapped retinal images are filtered by a hierarchical set of Gabor spatial filters (GSF) which provide compression of the information contained within a pixel-based image. A neural network associative memory (AM) is used to process the GSF coded images. We describe a 1-D shape function method for coding of scale and rotationally invariant shape information. This method reduces image shape information to a periodic waveform suitable for coding as an input vector to a neural network AM. The shape function method is suitable for near term applications on conventional computing architectures equipped with VLSI FFT chips to provide a rapid image search capability.

  1. Multi-net optimization of VLSI interconnect

    CERN Document Server

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  2. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    Directory of Open Access Journals (Sweden)

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  3. An All-Glass Microfluidic Network with Integrated Amorphous Silicon Photosensors for on-Chip Monitoring of Enzymatic Biochemical Assay.

    Science.gov (United States)

    Costantini, Francesca; Tiggelaar, Roald M; Salvio, Riccardo; Nardecchia, Marco; Schlautmann, Stefan; Manetti, Cesare; Gardeniers, Han J G E; de Cesare, Giampiero; Caputo, Domenico; Nascetti, Augusto

    2017-12-05

    A lab-on-chip system, integrating an all-glass microfluidics and on-chip optical detection, was developed and tested. The microfluidic network is etched in a glass substrate, which is then sealed with a glass cover by direct bonding. Thin film amorphous silicon photosensors have been fabricated on the sealed microfluidic substrate preventing the contamination of the micro-channels. The microfluidic network is then made accessible by opening inlets and outlets just prior to the use, ensuring the sterility of the device. The entire fabrication process relies on conventional photolithographic microfabrication techniques and is suitable for low-cost mass production of the device. The lab-on-chip system has been tested by implementing a chemiluminescent biochemical reaction. The inner channel walls of the microfluidic network are chemically functionalized with a layer of polymer brushes and horseradish peroxidase is immobilized into the coated channel. The results demonstrate the successful on-chip detection of hydrogen peroxide down to 18 μM by using luminol and 4-iodophenol as enhancer agent.

  4. VLSI Design of Trusted Virtual Sensors

    Directory of Open Access Journals (Sweden)

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  5. On-chip switch for reconfigurable mode-multiplexing optical network.

    Science.gov (United States)

    Sun, Chunlei; Yu, Yu; Chen, Guanyu; Zhang, Xinliang

    2016-09-19

    The switching and routing is essential for an advanced and reconfigurable optical network, and great efforts have been done for traditional single-mode system. We propose and demonstrate an on-chip switch compatible with mode-division multiplexing system. By controlling the induced phase difference, the functionalities of dynamically routing data channels can be achieved. The proposed switch is experimentally demonstrated with low insertion loss of ~1 dB and high extinction ratio of ~20 dB over the C-band for OFF-ON switchover. For further demonstration, the non-return-to-zero on-off keying signals at 10 Gb/s carried on the two spatial modes are successfully processed. Open and clear eye diagrams can be observed and the bit error rate measurements indicate a good data routing performance.

  6. Design of Smart Power-Saving Architecture for Network on Chip

    Directory of Open Access Journals (Sweden)

    Trong-Yen Lee

    2014-01-01

    Full Text Available In network-on-chip (NoC, the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS, for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively.

  7. A system-level bandwidth design method for wormhole network-on-chip

    Science.gov (United States)

    Wang, Jian; Li, Yubai; Liao, Changjun

    2016-11-01

    To improve the Network-on-Chip (NoC) performance, we propose a system-level bandwidth design method customising the bandwidths of the NoC links. In details, we first built a mathematical model to catch the relationship between the NoC commutation latency and the NoC link bandwidth, and then develop a bandwidth allocation algorithm to automatically optimise the bandwidth for each NoC link. The experimental results show that our bandwidth-customising method improves the NoC performance compared to the traditional uniform bandwidth allocation method. Besides, it can also make our NoC to achieve the same communication performance level as the uniform bandwidth NoC but using fewer bandwidth resources, which is beneficial to save the NoC area and power.

  8. Multifunctional optical system-on-a-chip for heterogeneous fiber optic sensor networks

    Science.gov (United States)

    Yu, Miao; Pang, Cheng; Gupta, Ashwani

    2015-08-01

    In this article, we review our recent progress on the development of a multifunctional optical system-on-a-chip platform, which can be used for achieving heterogeneous wireless fiber optical sensor networks. A multifunctional optical sensor platform based on the micro-electromechanical systems (MEMS) technology is developed. The key component of the multifunctional optical sensor platform is a MEMS based tunable Fabry-Pérot (FP) filter, which can be used as a phase modulator or a wavelength tuning device in a multifunctional optical sensing system. Mechanics model of the FP filter and optics model of the multifunctional optical sensing system are developed to facilitate the design of the filter. The MEMS FP filter is implemented in a multifunctional optical sensing system including both Fabry-Perot interferometer based sensors and Fiber Bragg grating sensors. The experimental results indicate that this large dynamic range tunable filter can enable high performance heterogeneous optical sensing for many applications.

  9. The CHIPS project: a health information network to serve the consumer.

    Science.gov (United States)

    Goodchild, E Y; Furman, J A; Addison, B L; Umbarger, H N

    1978-10-01

    CHIPS (Consumer Health Information Program and Services/Salud y Bienestar) is a Library Services and Construction Act Title I-funded project that has as its major goal the formation of a health information network to serve the consumer, the public library client, and the hospital patient. Funded for two years, 1976-1978, this bilingual project coordinates efforts of the Los Angeles County Harbor General Hospital Regional Medical Library and the Los Angeles County Carson Regional Public Library to provide health information resources and services to the public. The target population is over two million people of diverse ethnic backgrounds. This paper discusses the project's objectives and encourages an active role for all libraries in the consumer health education movement.

  10. On Asymptotic Analysis of Packet and Wormhole Switched Routing Algorithm for Application-Specific Networks-on-Chip

    Directory of Open Access Journals (Sweden)

    Nitin

    2012-01-01

    Full Text Available The application of the multistage interconnection networks (MINs in systems-on-chip (SoC and networks-on-chip (NoC is hottest since year 2002. Nevertheless, nobody used them practically for parallel communication. However, to overcome all the previous problems, a new method is proposed that uses MIN to provide intra-(global communication among application-specific NoCs in networks-in-package (NiP. For this, four fault-tolerant parallel algorithms are proposed. It allows different NoCs to communicate in parallel using either fault-tolerant irregular Penta multistage interconnection network (PNN or fault-tolerant regular Hexa multistage interconnection network (HXN. These two are acting as an interconnects-on-chip (IoC in NiP. Both IoC use packet switching and wormhole switching to route packets from source NoC to destination NoC. The results are compared in terms of packet losses and wormhole switching which comes out to be better than packet switching. The comparison of IoC on cost and MTTR concluded that the HXN has the higher cost than the PNN, but MTTR values of the HXN are low in comparison to the PNN. This signifies that the ability to tolerate faults and online repairing of the HXN is higher and faster than the PNN.

  11. The Torus Routing Chip

    National Research Council Canada - National Science Library

    Dally, William J; Seitz, Charles L

    1986-01-01

    The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels...

  12. Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating

    Science.gov (United States)

    Wang, Feng; Tang, Xiantuo; Xing, Zuocheng; Liu, Hengzhu

    2016-08-01

    Network-on-chip (NoC) is one of critical communication architectures for the scaling of future many-core processors. The challenge for on-chip network is reducing design complexity to save both area and power while providing high performance such as low latency and high throughput. Especially, with increase of network size, both design complexity and power consumption have become the bottlenecks preventing proper network scaling. Moreover, as technology continuously scales down, leakage power takes up a larger fraction of total NoC power. It is increasingly important for a power-efficient NoC design to reduce the increasing leakage power. Power-gating, as a representative low-power technique, can be applied to an on-chip network for mitigating leakage power. In this paper, we propose a low-cost and low-power router architecture for the unidirectional torus network, and adopt an improved corner buffer structure for the inoffensive power-gating, which has minimal impact on network performance. Besides, an explicit starvation avoidance mechanism is introduced to guarantee injection fairness while decreasing its negative impact on network throughput. Simulation results with synthetic traffic show that our design can improve network throughput by 11.3% on average and achieve significant power-saving in low- and medium-load regions. In the SPLASH-2 workload simulation, our design can save on average 27.2% of total power compared to the baseline, and decrease 42.8% average latency compared to the baseline with power-gating.

  13. Intelligent microchip networks: an agent-on-chip synthesis framework for the design of smart and robust sensor networks

    Science.gov (United States)

    Bosse, Stefan

    2013-05-01

    Sensorial materials consisting of high-density, miniaturized, and embedded sensor networks require new robust and reliable data processing and communication approaches. Structural health monitoring is one major field of application for sensorial materials. Each sensor node provides some kind of sensor, electronics, data processing, and communication with a strong focus on microchip-level implementation to meet the goals of miniaturization and low-power energy environments, a prerequisite for autonomous behaviour and operation. Reliability requires robustness of the entire system in the presence of node, link, data processing, and communication failures. Interaction between nodes is required to manage and distribute information. One common interaction model is the mobile agent. An agent approach provides stronger autonomy than a traditional object or remote-procedure-call based approach. Agents can decide for themselves, which actions are performed, and they are capable of flexible behaviour, reacting on the environment and other agents, providing some degree of robustness. Traditionally multi-agent systems are abstract programming models which are implemented in software and executed on program controlled computer architectures. This approach does not well scale to micro-chip level and requires full equipped computers and communication structures, and the hardware architecture does not consider and reflect the requirements for agent processing and interaction. We propose and demonstrate a novel design paradigm for reliable distributed data processing systems and a synthesis methodology and framework for multi-agent systems implementable entirely on microchip-level with resource and power constrained digital logic supporting Agent-On-Chip architectures (AoC). The agent behaviour and mobility is fully integrated on the micro-chip using pipelined communicating processes implemented with finite-state machines and register-transfer logic. The agent behaviour

  14. Engineering a Blood Vessel Network Module for Body-on-a-Chip Applications.

    Science.gov (United States)

    Ryu, Hyunryul; Oh, Soojung; Lee, Hyun Jae; Lee, Jin Young; Lee, Hae Kwang; Jeon, Noo Li

    2015-06-01

    The blood circulatory system links all organs from one to another to support and maintain each organ's functions consistently. Therefore, blood vessels have been considered as a vital unit. Engineering perfusable functional blood vessels in vitro has been challenging due to difficulties in designing the connection between rigid macroscale tubes and fragile microscale ones. Here, we propose a generalizable method to engineer a "long" perfusable blood vessel network. To form millimeter-scale vessels, fibroblasts were co-cultured with human umbilical vein endothelial cells (HUVECs) in close proximity. In contrast to previous works, in which all cells were permanently placed within the device, we developed a novel method to culture paracrine factor secreting fibroblasts on an O-ring-shaped guide that can be transferred in and out. This approach affords flexibility in co-culture, where the effects of secreted factors can be decoupled. Using this, blood vessels with length up to 2 mm were successfully produced in a reproducible manner (>90%). Because the vessels form a perfusable network within the channel, simple links to inlets and outlets of the device allowed connections to the outside world. The robust and reproducible formation of in vitro engineered vessels can be used as a module to link various organ components as parts of future body-on-a-chip applications. © 2014 Society for Laboratory Automation and Screening.

  15. Smart Memory and Network-On-Chip Design for High-Performance Shared-Memory Chip Multiprocessors

    OpenAIRE

    Lodde, Mario

    2014-01-01

    La jerarquía de caches y la red en el chip (NoC) son dos componentes clave de los chip multiprocesadores (CMPs). La mayoría del trafico en la NoC se debe a mensajes que las caches envían según lo que establece el protocolo de coherencia. La cantidad de trafico, el porcentaje de mensajes cortos y largos y el patrón de trafico en general varían dependiendo de la geometría de las caches y del protocolo de coherencia. La arquitectura de la NoC y la jerarquía de caches están de hecho firmemente ac...

  16. On-chip in vitro cell-network pre-clinical cardiac toxicity using spatiotemporal human cardiomyocyte measurement on a chip.

    Science.gov (United States)

    Kaneko, Tomoyuki; Nomura, Fumimasa; Hamada, Tomoyo; Abe, Yasuyuki; Takamori, Hideo; Sakakura, Tomoko; Takasuna, Kiyoshi; Sanbuissho, Atsushi; Hyllner, Johan; Sartipy, Peter; Yasuda, Kenji

    2014-04-22

    To overcome the limitations and misjudgments of conventional prediction of arrhythmic cardiotoxicity, we have developed an on-chip in vitro predictive cardiotoxicity assay using cardiomyocytes derived from human stem cells employing a constructive spatiotemporal two step measurement of fluctuation (short-term variability; STV) of cell's repolarization and cell-to-cell conduction time, representing two origins of lethal arrhythmia. Temporal STV of field potential duration (FPD) showed a potential to predict the risks of lethal arrhythmia originated from repolarization dispersion for false negative compounds, which was not correctly predicted by conventional measurements using animal cells, even for non-QT prolonging clinical positive compounds. Spatial STV of conduction time delay also unveiled the proarrhythmic risk of asynchronous propagation in cell networks, whose risk cannot be correctly predicted by single-cell-based measurements, indicating the importance of the spatiotemporal fluctuation viewpoint of in vitro cell networks for precise prediction of lethal arrhythmia reaching clinical assessment such as thorough QT assay.

  17. Squeeze-chip: a finger-controlled microfluidic flow network device and its application to biochemical assays.

    Science.gov (United States)

    Li, Wentao; Chen, Tao; Chen, Zitian; Fei, Peng; Yu, Zhilong; Pang, Yuhong; Huang, Yanyi

    2012-05-07

    We designed and fabricated a novel microfluidic device that can be operated through simple finger squeezing. On-chip microfluidic flow control is enabled through an optimized network of check-valves and squeeze-pumps. The sophisticated flow system can be easily constructed by combining a few key elements. We implemented this device to perform quantitative biochemical assays with no requirement for precision instruments.

  18. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  19. Multilevel VLSI interconnection—an optimum approach?

    Science.gov (United States)

    Srikrishnan, K. V.; Totta, P. A.

    1986-04-01

    The wirability of circuit elements is a key ingredient in the success of the very large scale integration technology. Multilevel wiring eliminates the need to use extensive areas of the silicon surface simply for wiring channels. Increasing the number of wiring planes significantly improves the possibility of achieving the goals of the VLSI, i.e. the interconnection of the maximum number of devices in the smallest possible area. Extensive modeling has shown the need to optimize the wiring pitch, number of wiring planes and electrical properties of the materials used (e.g-low resistivity for conductors and low dielectric constant for insulators). The choice of the interconnection technology is also influenced by other factors. Some of these areas: cost and reliability objectives; in house expertise and practice; new process/equipment availability and a desire to maintain process commonality. The selected strategy is sometimes an optimum approach for an individual situation which is not universally optimum. In IBM, for example, two different but successful multilevel wiring technologies are being used extensively. The first is used for bipolar circuits; it is a three-level metallization design, with sputtered SiO2 as the insulator. The second, for FET devices, has two-levels of metal and polyimide as the insulator. Both technologies use area array input/output terminal connections and lift off line definition. The process/material set of each is reviewed to emphasize the mechanics of reaching an ``optimum'' solution for the individual applications.

  20. Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.

    Science.gov (United States)

    Carrillo, Snaider; Harkin, Jim; McDaid, Liam; Pande, Sandeep; Cawley, Seamus; McGinley, Brian; Morgan, Fearghal

    2012-09-01

    The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware. Copyright © 2012 Elsevier Ltd. All rights reserved.

  1. AN ALGORITHM FOR ASSEMBLING A COMMON IMAGE OF VLSI LAYOUT

    Directory of Open Access Journals (Sweden)

    Y. Y. Lankevich

    2015-01-01

    Full Text Available We consider problem of assembling a common image of VLSI layout. Common image is composedof frames obtained by electron microscope photographing. Many frames require a lot of computation for positioning each frame inside the common image. Employing graphics processing units enables acceleration of computations. We realize algorithms and programs for assembling a common image of VLSI layout. Specificity of this work is to use abilities of CUDA to reduce computation time. Experimental results show efficiency of the proposed programs.

  2. Remote System Update for System on Programmable Chip Based on Controller Area Network

    Directory of Open Access Journals (Sweden)

    Lei Zhou

    2017-06-01

    Full Text Available In some application domains, using a download cable to update the system on a programmable chip (SoPC is infeasible, which reduces the maintainability and flexibility of the system. Hence the remote system update (RSU scheme is being studied. In this scheme, the serial configuration (EPCS device involves a factory mode configuration image, which acts as the baseline, and an application mode configuration image, which is used for some specific functions. Specifically, a new application mode image is delivered through the controller area network (CAN with the improved application layer protocol. Besides, the data flow and data check for transmitting a new image are constructed to combine the transmission reliability with efficiency. The boot sequence copying hardware configuration code and software configuration code is analyzed, and the advanced boot loader is carried out to specify boot address of the application mode image manually. Experiments have demonstrated the feasibility of updating and running a new application mode image, as well as rolling back into the factory mode image when no application mode image is available. This scheme applies a single CAN bus, which makes the system easy to construct and suitable for the field distributed control system.

  3. On-chip constructive cell-network study (II): on-chip quasi-in vivo cardiac toxicity assay for ventricular tachycardia/fibrillation measurement using ring-shaped closed circuit microelectrode with lined-up cardiomyocyte cell network.

    Science.gov (United States)

    Nomura, Fumimasa; Kaneko, Tomoyuki; Hattori, Akihiro; Yasuda, Kenji

    2011-09-19

    Conventional in vitro approach using human ether-a-go-go related gene (hERG) assay has been considered worldwide as the first screening assay for cardiac repolarization safety. However, it does not always oredict the potential QT prolongation risk or pro-arrhythmic risk correctly. For adaptable preclinical strategiesto evaluate global cardiac safety, an on-chip quasi-in vivo cardiac toxicity assay for lethal arrhythmia (ventricular tachyarrhythmia) measurement using ring-shaped closed circuit microelectrode chip has been developed. The ventricular electrocardiogram (ECG)-like field potential data, which includes both the repolarization and the conductance abnormality, was acquired from the self-convolutied extracellular field potentials (FPs) of a lined-up cardiomyocyte network on a circle-shaped microelectrode in an agarose microchamber. When Astemisol applied to the closed-loop cardiomyocyte network, self-convoluted FP profile of normal beating changed into an early afterdepolarization (EAD) like waveform, and then showed ventricular tachyarrhythmias and ventricular fibrilations (VT/Vf). QT-prolongation-like self-convoluted FP duration prolongation and its fluctuation increase was also observed according to the increase of Astemizole concentration. The results indicate that the convoluted FPs of the quasi-in vivo cell network assay includes both of the repolarization data and the conductance abnormality of cardiomyocyte networks has the strong potential to prediction lethal arrhythmia.

  4. On-chip constructive cell-network study (II: on-chip quasi-in vivo cardiac toxicity assay for ventricular tachycardia/fibrillation measurement using ring-shaped closed circuit microelectrode with lined-up cardiomyocyte cell network

    Directory of Open Access Journals (Sweden)

    Yasuda Kenji

    2011-09-01

    Full Text Available Abstract Backgrounds Conventional in vitro approach using human ether-a-go-go related gene (hERG assay has been considered worldwide as the first screening assay for cardiac repolarization safety. However, it does not always oredict the potential QT prolongation risk or pro-arrhythmic risk correctly. For adaptable preclinical strategiesto evaluate global cardiac safety, an on-chip quasi-in vivo cardiac toxicity assay for lethal arrhythmia (ventricular tachyarrhythmia measurement using ring-shaped closed circuit microelectrode chip has been developed. Results The ventricular electrocardiogram (ECG-like field potential data, which includes both the repolarization and the conductance abnormality, was acquired from the self-convolutied extracellular field potentials (FPs of a lined-up cardiomyocyte network on a circle-shaped microelectrode in an agarose microchamber. When Astemisol applied to the closed-loop cardiomyocyte network, self-convoluted FP profile of normal beating changed into an early afterdepolarization (EAD like waveform, and then showed ventricular tachyarrhythmias and ventricular fibrilations (VT/Vf. QT-prolongation-like self-convoluted FP duration prolongation and its fluctuation increase was also observed according to the increase of Astemizole concentration. Conclusions The results indicate that the convoluted FPs of the quasi-in vivo cell network assay includes both of the repolarization data and the conductance abnormality of cardiomyocyte networks has the strong potential to prediction lethal arrhythmia.

  5. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    Directory of Open Access Journals (Sweden)

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  6. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    Directory of Open Access Journals (Sweden)

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  7. Single-chip multimedia network access using installed in-home cable and that can be remotely managed

    Science.gov (United States)

    Gandar, Marc; Mlynek, Daniel; Osseiran, Adam

    1998-02-01

    This paper describes a solution to multimedia networking using presently installed home cable. To reach this goal a concept based on a high performance single chip has been achieved. This concept has been validated in several applications and is now available in an open VHDL or silicon format. The flexibility of this network allows high-speed data and power multiplexing on the same wire. The MediaFlow solution, described in this paper, proposed a remote management tool for distributed device interconnection such as phone, hi-fi, video control and computers in the home. This management could either be locally or remotely controlled through ATM or ISDN networks. The concept allows a service provider to take over the installation, management and maintenance of the whole network.

  8. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  9. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Science.gov (United States)

    Khawaja, Sajid Gul; Mushtaq, Mian Hamza; Khan, Shoab A; Akram, M Usman; Jamal, Habib Ullah

    2015-01-01

    With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS) guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC) topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  10. Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees.

    Directory of Open Access Journals (Sweden)

    Sajid Gul Khawaja

    Full Text Available With the increase of transistors' density, popularity of System on Chip (SoC has increased exponentially. As a communication module for SoC, Network on Chip (NoC framework has been adapted as its backbone. In this paper, we propose a methodology for designing area-optimized application specific NoC while providing hard Quality of Service (QoS guarantees for real time flows. The novelty of the proposed system lies in derivation of a Mixed Integer Linear Programming model which is then used to generate a resource optimal Network on Chip (NoC topology and architecture while considering traffic and QoS requirements. We also present the micro-architectural design features used for enabling traffic and latency guarantees and discuss how the solution adapts for dynamic variations in the application traffic. The paper highlights the effectiveness of proposed method by generating resource efficient NoC solutions for both industrial and benchmark applications. The area-optimized results are generated in few seconds by proposed technique, without resorting to heuristics, even for an application with 48 traffic flows.

  11. Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture

    Directory of Open Access Journals (Sweden)

    Hayat Daoud

    2017-02-01

    Full Text Available Approaches for the design of fault tolerant Network-on-Chip (NoC for use in System-on-Chip (SoC reconfigurable technology using Field-Programmable Gate Array (FPGA technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC design. To achieve this, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in the validation process. The Event-B method is a promising formal approach that can be used to develop, model and prove accurately SoC and MPSoC architectures. This paper proposes a formal verification approach for NoC architecture including the dependability constraints relating to the choice of the path routing of data packets and the strategy imposed for diversion when faulty routers are detected. The formalization process is incremental and validated by correct-by-construction development of the NoC architecture. Using the concepts of graph colouring and B-event formalism, the results obtained have demonstrated its efficiency for determining the bugs, and a solution to ensure a fast and reliable operation of the network when compared to existing similar methods.

  12. A run-time reconfigurable Network-on-Chip for streaming DSP applications

    NARCIS (Netherlands)

    Kavaldjiev, N.K.; Kavaldjiev, Nikolay Krasimirov

    2007-01-01

    With the advance of semiconductor technology, global on-chip wiring is becoming a limiting factor for the overall performance of large System-on-Chip (SoC) designs. In this thesis we propose a global communication architecture that avoids this limitation by structuring and shortening of the global

  13. Application and Integration of Quantum-Effect Devices for Cellular VLSI

    Science.gov (United States)

    Levy, Harold Joseph

    1995-01-01

    Cellular VLSI is that subclass of electronic systems for which small perturbations in a repeated cell design can dramatically influence the cost and performance of the entire system. This thesis presents examples of how the room-temperature quantum effects of tunneling and resonance may be used to condense the functionality of many conventional VLSI devices into a smaller and more efficient subunit, thus yielding tremendous benefits for the system as a whole. In particular, two and three-terminal applications of a complimentary pair of quantum-effect devices, the resonant-tunneling diode and the tunneling-switch diode, are presented. The first example is an image-segmentation network for machine vision, implemented by using resonant-tunneling diodes in one and two-dimensional networks to extract boundaries between regions of constant spatial texture. In this case a single quantum-effect device may replace up to thirty -three CMOS transistors per pixel. The second example is an artificial neural-network processor based on multistate resistors for synaptic conductances. These programmable resistors were produced by combining a vertically -integrated stack of resonant-tunneling diodes with a resistive load and a single MOSFET driven in its ohmic region. This macrostructure has the potential to provide synaptic changes on the picosecond time scale at length scales well below one micron. The third example is a current-mode transistorless memory array based on a two-dimensional network of cells containing only a single tunneling-switch diode and a resistive load. The resulting system has the potential for reaching more than an order-of-magnitude more cell density than state-of-the-art DRAM arrays, while operating at state -of-the-art SRAM speeds and reasonable power consumption.

  14. Formal Hierarchical Multilevel Verification of Synchronous MOS VLSI Designs,

    Science.gov (United States)

    1987-11-01

    description of digital systems appear in Johnson [Johnson] (though in a much less accessible form). Other researchers, [ Sheeran , Johnson], use the same...Snepscheut, "Hot-Clock nMOS," Proc of the 1985 Chapel Hil Conference on VLSI. Henry Fuchs, Editor. Computer Science Press 1985 [ Sheeran ] Mary Sheeran

  15. A 0.5-GHz CMOS digital RF memory chip

    Science.gov (United States)

    Schnaitter, W. M.; Lewis, E. T.; Gordon, B. E.

    1986-10-01

    Digital RF memories (DRFM's) are key elements for modern radar jamming. An RF signal is sampled, stored in random access memory (RAM), and later recreated from the stored data. Here the first CMOS DRFM chip, integrating static RAM, control circuitry, and two channels of shift registers, on a single chip is described. The sample rate achieved was 0.5 GHz, VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.

  16. Extended QoS modelling based on multi-application environment in network on chip

    Science.gov (United States)

    Saadaoui, Abdelkader; Nasri, Salem

    2015-01-01

    Until now, there is no standard method of the quality of service (QoS) measurement and fewer techniques have been used to provide its definition. Therefore, researchers are looking for a projection of QoS on quantifiable space, since it is qualitative, subjective and not measurable. However, a few tentatives have studied QoS parameter estimation. Many applications in network on chip (NoC) present variable QoS parameters such as packet loss rate (PLR), end-to-end delay (EED) and throughput (Thp). However, there are a few papers that have developed different methods to modelise QoS in NoC. Their QoS presentation does not provide a multi-application parameter arbiter. Independently of the approach used, an important challenge associated with QoS provision is the development of an efficient and flexible way to monitor QoS. The originality of our approach is based on a proposition of a QoS-intellectual property module in NoC architecture to improve network performances. We implement an extended approach of QoS metrics modelling for NoC on multi-parameter and multi-application environment. The QoS metrics model is based on QoS parameters such as PLR, EED and Thp for different applications. To validate this work, a dynamic routing simulation for 4 × 4 mesh NoC behaviour under three different applications, namely transmission control protocol, variable bit rate and constant bit rate, is considered. To achieve an ideal network behaviour, load balancing on NoC with multiple concurrent applications is improved using QoS metrics measurement based on dynamic routing. The results have shown that extended QoS modelling approach is easy and cheap to implement in hardware-software quantifiable representation. Thus, implementing a quantifiable representation of QoS can be used to provide a NoC services arbiter. QoS arbiter interacts with other routers to ensure flit flow and QoS modelling to provide a QoS value.

  17. Supporting Symmetric 128-bit AES in Networked Embedded Systems: An Elliptic Curve Key Establishment Protocol-on-Chip

    Directory of Open Access Journals (Sweden)

    Roshan Duraisamy

    2007-02-01

    Full Text Available The secure establishment of cryptographic keys for symmetric encryption via key agreement protocols enables nodes in a network of embedded systems and remote agents to communicate securely in an insecure environment. In this paper, we propose a pure hardware implementation of a key agreement protocol, which uses the elliptic curve Diffie-Hellmann and digital signature algorithms and enables two parties, a remote agent and a networked embedded system, to establish a 128-bit symmetric key for encryption of all transmitted data via the advanced encryption scheme (AES. The resulting implementation is a protocol-on-chip that supports full 128-bit equivalent security (PoC-128. The PoC-128 has been implemented in an FPGA, but it can also be used as an IP within different embedded applications. As 128-bit security is conjectured valid for the foreseeable future, the PoC-128 goes well beyond the state of art in securing networked embedded devices.

  18. β-catenin promoter ChIP-chip reveals potential schizophrenia and bipolar disorder gene network.

    Science.gov (United States)

    Pedrosa, Erika; Shah, Abhishek; Tenore, Christopher; Capogna, Michael; Villa, Catalina; Guo, Xingyi; Zheng, Deyou; Lachman, Herbert M

    2010-12-01

    Therapeutic concentrations of lithium salts inhibit glycogen synthase kinase 3 beta (GSK3β) and phosphoinositide (PI) signaling suggesting that abnormal activation of these pathways could be a factor in the pathophysiology of bipolar disorder (BD). Involvement of these pathways is also supported by recent genome-wide association studies (GWASs). One way investigators have investigated the molecular basis of BD and the therapeutic action of lithium is by microarray expression studies, since both GSK3β- and PI-mediated signal transduction pathways are coupled to transcriptional activation and inhibition. However, expression profiling has some limitations and investigators cannot use the approach to analyze fetal brain tissue, arguably the most relevant biological structure related to the development of genetically based psychiatric disorders. To address these shortcomings, the authors have taken a novel approach using chromatin immunoprecipitation-enriched material annealed to microarrays (ChIP-chip) targeting genes in fetal brain tissue bound by β-catenin, a transcription factor that is directly regulated by GSK3β. The promoters for 640 genes were found to be bound by β-catenin, many of which are known schizophrenia (SZ), autism spectrum disorder (ASD), and BD candidates, including CACNA1B, NRNG, SNAP29, FGFR1, PCDH9, and nine others identified in recently published GWASs and genome-wide searches for copy number variants (CNVs). The findings suggest that seemingly disparate candidate genes for SZ and BD can be incorporated into a common molecular network revolving around GSK3β/β-catenin signaling. In addition, the finding that a putative lithium-responsive pathway may influence a subgroup of SZ and ASD candidate genes could have therapeutic implications.

  19. Novel Self-Heated Gas Sensors Using on-Chip Networked Nanowires with Ultralow Power Consumption.

    Science.gov (United States)

    Tan, Ha Minh; Manh Hung, Chu; Ngoc, Trinh Minh; Nguyen, Hugo; Duc Hoa, Nguyen; Van Duy, Nguyen; Hieu, Nguyen Van

    2017-02-22

    The length of single crystalline nanowires (NWs) offers a perfect pathway for electron transfer, while the small diameter of the NWs hampers thermal losses to tje environment, substrate, and metal electrodes. Therefore, Joule self-heating effect is nearly ideal for operating NW gas sensors at ultralow power consumption, without additional heaters. The realization of the self-heated NW sensors using the "pick and place" approach is complex, hardly reproducible, low yield, and not applicable for mass production. Here, we present the sensing capability of the self-heated networked SnO2 NWs effectively prepared by on-chip growth. Our developed self-heated sensors exhibit a good response of 25.6 to 2.5 ppm NO2 gas, while the response to 500 ppm H2, 100 ppm NH3, 100 ppm H2S, and 500 ppm C2H5OH is very low, indicating the good selectivity of the sensors to NO2 gas. Furthermore, the detection limit is very low, down to 82 parts-per-trillion. As-obtained sensing performance under self-heating mode is nearly identical to that under external heating mode. While the power consumption under self-heating mode is extremely low, around hundreds of microwatts, as scaled-down the size of the electrode is below 10 μm. The selectivity of the sensors can be controlled simply by tuning the loading power that enables simple detection of NO2 in mixed gases. Remarkable performance together with a significantly facile fabrication process of the present sensors enhances the potential application of NW sensors in next generation technologies such as electronic noses, the Internet of Things, and smartphone sensing.

  20. Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Bufferless Data Flow

    Directory of Open Access Journals (Sweden)

    S. Ortega-Cisneros

    2014-02-01

    Full Text Available The use of on chip networks as interconnection media for systems implemented in FPGAs is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the performance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aimed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4-device. We also provide a performance profile, obtained by subjecting a network formed by these switches to different synthetic workloads within a simulator. This simulator was developed as part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.

  1. Reconstituting Corticostriatal Network on-a-Chip Reveals the Contribution of the Presynaptic Compartment to Huntington's Disease.

    Science.gov (United States)

    Virlogeux, Amandine; Moutaux, Eve; Christaller, Wilhelm; Genoux, Aurélie; Bruyère, Julie; Fino, Elodie; Charlot, Benoit; Cazorla, Maxime; Saudou, Frédéric

    2018-01-02

    Huntington's disease (HD), a devastating neurodegenerative disorder, strongly affects the corticostriatal network, but the contribution of pre- and postsynaptic neurons in the first phases of disease is unclear due to difficulties performing early subcellular investigations in vivo. Here, we have developed an on-a-chip approach to reconstitute an HD corticostriatal network in vitro, using microfluidic devices compatible with subcellular resolution. We observed major defects in the different compartments of the corticostriatal circuit, from presynaptic dynamics to synaptic structure and transmission and to postsynaptic traffic and signaling, that correlate with altered global synchrony of the network. Importantly, the genetic status of the presynaptic compartment was necessary and sufficient to alter or restore the circuit. This highlights an important weight for the presynaptic compartment in HD that has to be considered for future therapies. This disease-on-a-chip microfluidic platform is thus a physiologically relevant in vitro system for investigating pathogenic mechanisms and for identifying drugs. Copyright © 2017 The Author(s). Published by Elsevier Inc. All rights reserved.

  2. Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

    Science.gov (United States)

    Liu, Yangfan; Liu, Peng; Jiang, Yingtao; Yang, Mei; Wu, Kejun; Wang, Weidong; Yao, Qingdong

    2010-10-01

    In this article, we present a highly scalable, flexible hardware-based network-on-chip (NoC) emulation framework, through which NoCs built upon various types of network topologies, routing algorithms, switching protocols and flow control schemes can be explored, compared, and validated with injected or self-generated traffic from both real-life and synthetic applications. This high degree of scalability and flexibility is achieved due to the field programmable gate array (FPGA) design choices made at both functional and physical levels. At the functional level, a NoC system to be emulated can be partitioned into two parts: (i) the processing cores and (ii) the network. Each part is mapped onto a different FPGA so that when there is any change to be made to any one of these parts, only the corresponding FPGA needs to be reconfigured and the rest of the FPGAs will be left untouched. At the physical level, two levels of interconnects are adopted to mimic NoC on-chip communications: high bandwidth and low latency parallel on-board wires, and high-speed serial multigigabit transceivers available in FPGAs. The latter is particularly important as it helps the proposed NoC emulation platform scale well with the size increase of the NoCs.

  3. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    OpenAIRE

    U. Saravanakumar; R. Rangarajan; K. Rajasekar

    2012-01-01

    As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. ...

  4. A low latency and high efficient three-dimension Network-on-Chip based on hierarchical structure

    Science.gov (United States)

    Zhu, Chen; Zhao, Huatao; Chen, Tinghuan; Zhu, Tianbo

    2017-07-01

    Currently, the majority of the Network-on-Chip (NoC) researches are based on 2D algorithm or simple 3D structure. However, the congestion and faulty links in the topology can increase the latency and power consumption. In this paper, the authors try to build a novel 3D topology based on hierarchical structure and TSV links which can reduce the latency and power consumption by decreasing the hops during the process of passing the packets. We employ the C++ tool to test our method, and the results show that the performance can be improved about 21%-36% in throughput, also 3%-11% in latency.

  5. Chip, Chip, Hooray!

    Science.gov (United States)

    Kelly, Susan

    2001-01-01

    Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

  6. VLSI Implementation of Digital Fourier Transforms.

    Science.gov (United States)

    1982-11-01

    aItkewng 37 5Ŗ.2. M -ulie of the Real and Imagnary POt 3S 5.3. Root S Circuit 39 5.4. Barrel 39ftr 41 55. -rotator 4216 5.5.1. Theary of operatio. 42 5...s is done so that the strings - - - -. ________-----:- -.- r 7 - r -rrr ------------- -7- of operators will match the structures exactly when they...results of the CORDIC cal- culation on a fabricated chip. However, it would be possible to add a register at the output of each adder module and string

  7. Flow control using audio tones in resonant microfluidic networks: towards cell-phone controlled lab-on-a-chip devices.

    Science.gov (United States)

    Phillips, Reid H; Jain, Rahil; Browning, Yoni; Shah, Rachana; Kauffman, Peter; Dinh, Doan; Lutz, Barry R

    2016-08-16

    Fluid control remains a challenge in development of portable lab-on-a-chip devices. Here, we show that microfluidic networks driven by single-frequency audio tones create resonant oscillating flow that is predicted by equivalent electrical circuit models. We fabricated microfluidic devices with fluidic resistors (R), inductors (L), and capacitors (C) to create RLC networks with band-pass resonance in the audible frequency range available on portable audio devices. Microfluidic devices were fabricated from laser-cut adhesive plastic, and a "buzzer" was glued to a diaphragm (capacitor) to integrate the actuator on the device. The AC flowrate magnitude was measured by imaging oscillation of bead tracers to allow direct comparison to the RLC circuit model across the frequency range. We present a systematic build-up from single-channel systems to multi-channel (3-channel) networks, and show that RLC circuit models predict complex frequency-dependent interactions within multi-channel networks. Finally, we show that adding flow rectifying valves to the network creates pumps that can be driven by amplified and non-amplified audio tones from common audio devices (iPod and iPhone). This work shows that RLC circuit models predict resonant flow responses in multi-channel fluidic networks as a step towards microfluidic devices controlled by audio tones.

  8. Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks

    Directory of Open Access Journals (Sweden)

    Angelo Kuti Lusala

    2012-01-01

    Full Text Available A Hybrid router architecture for Networks-on-Chip “NoC” is presented, it combines Spatial Division Multiplexing “SDM” based circuit switching and packet switching in order to efficiently and separately handle both streaming and best-effort traffic generated in real-time applications. Furthermore the SDM technique is combined with Time Division Multiplexing “TDM” technique in the circuit switching part in order to increase path diversity, thus improving throughput while sharing communication resources among multiple connections. Combining these two techniques allows mitigating the poor resource usage inherent to circuit switching. In this way Quality of Service “QoS” is easily provided for the streaming traffic through the circuit-switched sub-router while the packet-switched sub-router handles best-effort traffic. The proposed hybrid router architectures were synthesized, placed and routed on an FPGA. Results show that a practicable Network-on-Chip “NoC” can be built using the proposed router architectures. 7 × 7 mesh NoCs were simulated in SystemC. Simulation results show that the probability of establishing paths through the NoC increases with the number of sub-channels and has its highest value when combining SDM with TDM, thereby significantly reducing contention in the NoC.

  9. VLSI architectures for the new (T,L) algorithm

    Science.gov (United States)

    Bengough, P. A.; Simmons, S. J.

    Trellis coding techniques have seen much use in error correction codes for space and satellite applications. When long sequences of data are encoded, the number of possible paths through the trellis becomes great and a trellis search algorithm must be used to determine the path that best matches the received data sequence. The (T,L) algorithm is a new reduced complexity trellis search algorithm, applicable to data sequence estimation in digital communications, that adapts to changing channel conditions. Its simplicity and inherent parallelism suits it well for very large scale integration (VLSI) implementation. A number of alternative VLSI architectures are presented which can be used to realize this algorithm. While one uses a simple nonsorting structure, two other sorting designs based on parallel insertion and weavesorting algorithms are proposed. The area-time performance of the various architectures is compared.

  10. Trace-based post-silicon validation for VLSI circuits

    CERN Document Server

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  11. Advanced symbolic analysis for VLSI systems methods and applications

    CERN Document Server

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  12. UW/NW (University of Washington/Northwest) VLSI Consortium

    Science.gov (United States)

    1986-12-10

    structure of the described circuits. One such language is ^ FP (a variation of the Functional Programming language FP) [ Sheeran 83] that describes...86] [Lipton 82] [ Sheeran 83] [Suzuki 85] [UW/NW 84] Bamji, C, Hauck, C. and Allen, J. A Design by Example Regular Structure Generator. In 22nd...Automation Conference, pages 467-474. IEEE, 1982. Mary Sheeran . \\i.FP - An Algebraic VLSI Design Language. PhD thesis, Oxford University Computing La

  13. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    Science.gov (United States)

    1985-01-01

    and Smoliar [Fran7g], Rowson [Rows80, Gordon [Gord8lJ, Cardelli and Plotkin [Card8l1, Hafer and Parker (Hafe83I, and Sheeran [Shee84] have all suggested...Software 1, 4 (October 1984), pp. 10-26. •.’ Y .. , ;,, ..- , .. r ,- ’..-.... -. -.. ,.:.%.. -. 149 ISbeeS4I. Sheeran , M., "mFP, a Language for VLSI

  14. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Directory of Open Access Journals (Sweden)

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  15. Model for EOS caused EF screening in CMOS VLSI

    Energy Technology Data Exchange (ETDEWEB)

    Lisenker, B. [Tower Semiconductor Ltd., Migdal Haemek (Israel); Nevo, Y. [National Semiconductor Ltd., Herzlia B` (Israel)

    1995-12-31

    This paper introduced a Fault Model, capable to elucidate the sensitivity to Electrical Overstress (EOS) and Early Fault (EF) rising nature in CMOS VLSI circuit. The Model based on the general Percolation Theory applied to the CMOS technology. Early Failures screening technique employing this Model, shows strong correlation between rejected devices, EOS faults and EF rate. This technique is recommenced both as an EF screening test and a process reliability monitor.

  16. VLSI realization of learning vector quantization with hardware/software co-design for different applications

    Science.gov (United States)

    An, Fengwei; Akazawa, Toshinobu; Yamasaki, Shogo; Chen, Lei; Jürgen Mattausch, Hans

    2015-04-01

    This paper reports a VLSI realization of learning vector quantization (LVQ) with high flexibility for different applications. It is based on a hardware/software (HW/SW) co-design concept for on-chip learning and recognition and designed as a SoC in 180 nm CMOS. The time consuming nearest Euclidean distance search in the LVQ algorithm’s competition layer is efficiently implemented as a pipeline with parallel p-word input. Since neuron number in the competition layer, weight values, input and output number are scalable, the requirements of many different applications can be satisfied without hardware changes. Classification of a d-dimensional input vector is completed in n × \\lceil d/p \\rceil + R clock cycles, where R is the pipeline depth, and n is the number of reference feature vectors (FVs). Adjustment of stored reference FVs during learning is done by the embedded 32-bit RISC CPU, because this operation is not time critical. The high flexibility is verified by the application of human detection with different numbers for the dimensionality of the FVs.

  17. A configurable realtime DWT-based neural data compression and communication VLSI system for wireless implants.

    Science.gov (United States)

    Yang, Yuning; Kamboh, Awais M; Mason, Andrew J

    2014-04-30

    This paper presents the design of a complete multi-channel neural recording compression and communication system for wireless implants that addresses the challenging simultaneous requirements for low power, high bandwidth and error-free communication. The compression engine implements discrete wavelet transform (DWT) and run length encoding schemes and offers a practical data compression solution that faithfully preserves neural information. The communication engine encodes data and commands separately into custom-designed packet structures utilizing a protocol capable of error handling. VLSI hardware implementation of these functions, within the design constraints of a 32-channel neural compression implant, is presented. Designed in 0.13μm CMOS, the core of the neural compression and communication chip occupies only 1.21mm(2) and consumes 800μW of power (25μW per channel at 26KS/s) demonstrating an effective solution for intra-cortical neural interfaces. Copyright © 2014 Elsevier B.V. All rights reserved.

  18. A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

    NARCIS (Netherlands)

    Hansson, A.; Goossens, K.; R?dulescu, A.

    2007-01-01

    One of the key steps in Network-on-Chip-based design is spatial mapping of cores and routing of the communication between those cores. Known solutions to the mapping and routing problems first map cores onto a topology and then route communication, using separate and possibly conflicting objective

  19. A new 2D mesh routing approach for networks on chip ...

    African Journals Online (AJOL)

    Traditionally, embedded systems and digital electronics technology were confined to computer systems. Today, embedded systems and systems on chip are applied in a wide range of areas such as television, communication systems, radar, military systems, medical instrumentation, and consumer electronics use digital ...

  20. A new 2D mesh routing approach for networks on chip Une nouvelle ...

    African Journals Online (AJOL)

    Traditionally, embedded systems and digital electronics technology were confined to computer systems. Today, embedded systems and systems on chip are applied in a wide range of areas such as television, communication systems, radar, military systems, ..... Channel,” Research Journal of Applied Sciences, Engineering.

  1. Power and Thermal Management of System-on-Chip

    DEFF Research Database (Denmark)

    Liu, Wei

    , are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution......With greater integration of VLSI circuits, power consumption and power density have increased dramatically resulting in high chip temperatures and presenting a heat removal challenge. To effectively limit the high temperature inside a chip, thermal specific approaches, besides low power techniques...... of power efficient dividers on the energy consumption and thermal distribution within the FPU and the on-chip cache. We also characterize the temperature dependent static dissipation to evaluate the reduction in leakage obtained from the decrease in temperature....

  2. Las Vegas is better than determinism in VLSI and distributed computing

    DEFF Research Database (Denmark)

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  3. On-chip constructive cell-network study (I): contribution of cardiac fibroblasts to cardiomyocyte beating synchronization and community effect.

    Science.gov (United States)

    Kaneko, Tomoyuki; Nomura, Fumimasa; Yasuda, Kenji

    2011-05-23

    To clarify the role of cardiac fibroblasts in beating synchronization, we have made simple lined-up cardiomyocyte-fibroblast network model in an on-chip single-cell-based cultivation system. The synchronization phenomenon of two cardiomyocyte networks connected by fibroblasts showed (1) propagation velocity of electrophysiological signals decreased a magnitude depending on the increasing number of fibroblasts, not the lengths of fibroblasts; (2) fluctuation of interbeat intervals of the synchronized two cardiomyocyte network connected by fibroblasts did not always decreased, and was opposite from homogeneous cardiomyocyte networks; and (3) the synchronized cardiomyocytes connected by fibroblasts sometimes loses their synchronized condition and recovered to synchronized condition, in which the length of asynchronized period was shorter less than 30 beats and was independent to their cultivation time, whereas the length of synchronized period increased according to cultivation time. The results indicated that fibroblasts can connect cardiomyocytes electrically but do not significantly enhance and contribute to beating interval stability and synchronization. This might also mean that an increase in the number of fibroblasts in heart tissue reduces the cardiomyocyte 'community effect', which enhances synchronization and stability of their beating rhythms.

  4. Implementation of a Universal Micro-Sensor Interface Chip

    National Research Council Canada - National Science Library

    Zhang, Kun

    2002-01-01

    .... Significant features of this chip are low-power design including chip-level power management, single chip solution containing all necessary interface electronics and capable of network implementation...

  5. Crystal growth and evaluation of silicon for VLSI and ULSI

    CERN Document Server

    Eranna, Golla

    2014-01-01

    PrefaceAbout the AuthorIntroductionSilicon: The SemiconductorWhy Single CrystalsRevolution in Integrated Circuit Fabrication Technology and the Art of Device MiniaturizationUse of Silicon as a SemiconductorSilicon Devices for Boolean ApplicationsIntegration of Silicon Devices and the Art of Circuit MiniaturizationMOS and CMOS Devices for Digital ApplicationsLSI, VLSI, and ULSI Circuits and ApplicationsSilicon for MEMS ApplicationsSummaryReferencesSilicon: The Key Material for Integrated Circuit Fabrication TechnologyIntroductionPreparation of Raw Silicon MaterialMetallurgical-Grade SiliconPuri

  6. Formal verification an essential toolkit for modern VLSI design

    CERN Document Server

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  7. Phase-Based Binocular Perception of Motion in Depth: Cortical-Like Operators and Analog VLSI Architectures

    Directory of Open Access Journals (Sweden)

    Silvio P. Sabatini

    2003-06-01

    Full Text Available We present a cortical-like strategy to obtain reliable estimates of the motions of objects in a scene toward/away from the observer (motion in depth, from local measurements of binocular parameters derived from direct comparison of the results of monocular spatiotemporal filtering operations performed on stereo image pairs. This approach is suitable for a hardware implementation, in which such parameters can be gained via a feedforward computation (i.e., collection, comparison, and punctual operations on the outputs of the nodes of recurrent VLSI lattice networks, performing local computations. These networks act as efficient computational structures for embedded analog filtering operations in smart vision sensors. Extensive simulations on both synthetic and real-world image sequences prove the validity of the approach that allows to gain high-level information about the 3D structure of the scene, directly from sensorial data, without resorting to explicit scene reconstruction.

  8. Locality-Driven Parallel Static Analysis for Power Delivery Networks

    KAUST Repository

    Zeng, Zhiyu

    2011-06-01

    Large VLSI on-chip Power Delivery Networks (PDNs) are challenging to analyze due to the sheer network complexity. In this article, a novel parallel partitioning-based PDN analysis approach is presented. We use the boundary circuit responses of each partition to divide the full grid simulation problem into a set of independent subgrid simulation problems. Instead of solving exact boundary circuit responses, a more efficient scheme is proposed to provide near-exact approximation to the boundary circuit responses by exploiting the spatial locality of the flip-chip-type power grids. This scheme is also used in a block-based iterative error reduction process to achieve fast convergence. Detailed computational cost analysis and performance modeling is carried out to determine the optimal (or near-optimal) number of partitions for parallel implementation. Through the analysis of several large power grids, the proposed approach is shown to have excellent parallel efficiency, fast convergence, and favorable scalability. Our approach can solve a 16-million-node power grid in 18 seconds on an IBM p5-575 processing node with 16 Power5+ processors, which is 18.8X faster than a state-of-the-art direct solver. © 2011 ACM.

  9. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  10. A VLSI design concept for parallel iterative algorithms

    Directory of Open Access Journals (Sweden)

    C. C. Sun

    2009-05-01

    Full Text Available Modern VLSI manufacturing technology has kept shrinking down to the nanoscale level with a very fast trend. Integration with the advanced nano-technology now makes it possible to realize advanced parallel iterative algorithms directly which was almost impossible 10 years ago. In this paper, we want to discuss the influences of evolving VLSI technologies for iterative algorithms and present design strategies from an algorithmic and architectural point of view. Implementing an iterative algorithm on a multiprocessor array, there is a trade-off between the performance/complexity of processors and the load/throughput of interconnects. This is due to the behavior of iterative algorithms. For example, we could simplify the parallel implementation of the iterative algorithm (i.e., processor elements of the multiprocessor array in any way as long as the convergence is guaranteed. However, the modification of the algorithm (processors usually increases the number of required iterations which also means that the switch activity of interconnects is increasing. As an example we show that a 25×25 full Jacobi EVD array could be realized into one single FPGA device with the simplified μ-rotation CORDIC architecture.

  11. VLSI design for reliability. Final report, September-November 1989

    Energy Technology Data Exchange (ETDEWEB)

    Hajj, I.N.; Najm, F.N.; Yang, P.

    1990-05-01

    This report contains the results of supplementary work done related to the reliability analysis of Application Specific Very Large Scale Integrated (ASIC VLSI) CMOS circuits. The major work is currently being carried out under Task N-9-5716. The main goal of both tasks is to determine the electromigration susceptibility of VLSI circuits. Electromigration is a major reliability problem caused by the transport of atoms in a metal line due to the electron flow. Under persistent current stress, electromigration can cause deformations of the metal lines which may result in shorts or open circuits. The failure rate due to electromigration depends on the current density in the metal lines and is usually expressed as a median-time-to-failure (MTF). This work focuses on the electromigration problem in the power and ground busses. To estimate the bust MTF, an estimate of the current waveform in each branch of the bus is required. In general, the MTF is dependent on the shape of the current waveform, and not simply on its time-average. However, a very large number of such waveform shapes are possible, depending on what inputs are applied to the circuit. This is especially true for complementary metal oxide semiconductors circuits, which draw current only during switching.

  12. Temporal ChIP-on-chip reveals Biniou as a universal regulator of the visceral muscle transcriptional network.

    Science.gov (United States)

    Jakobsen, Janus S; Braun, Martina; Astorga, Jeanette; Gustafson, E Hilary; Sandmann, Thomas; Karzynski, Michal; Carlsson, Peter; Furlong, Eileen E M

    2007-10-01

    Smooth muscle plays a prominent role in many fundamental processes and diseases, yet our understanding of the transcriptional network regulating its development is very limited. The FoxF transcription factors are essential for visceral smooth muscle development in diverse species, although their direct regulatory role remains elusive. We present a transcriptional map of Biniou (a FoxF transcription factor) and Bagpipe (an Nkx factor) activity, as a first step to deciphering the developmental program regulating Drosophila visceral muscle development. A time course of chromatin immunoprecipitatation followed by microarray analysis (ChIP-on-chip) experiments and expression profiling of mutant embryos reveal a dynamic map of in vivo bound enhancers and direct target genes. While Biniou is broadly expressed, it regulates enhancers driving temporally and spatially restricted expression. In vivo reporter assays indicate that the timing of Biniou binding is a key trigger for the time span of enhancer activity. Although bagpipe and biniou mutants phenocopy each other, their regulatory potential is quite different. This network architecture was not apparent from genetic studies, and highlights Biniou as a universal regulator in all visceral muscle, regardless of its developmental origin or subsequent function. The regulatory connection of a number of Biniou target genes is conserved in mice, suggesting an ancient wiring of this developmental program.

  13. On-chip superconducting LC matching networks and coplanar waveguides for radio-frequency single electron transistors

    Science.gov (United States)

    Xue, Weiwei

    The radio-frequency single-electron transistor (RF-SET) [1--3] has attracted significant interest as one of the fastest charge detectors known today. In this thesis, we show that by designing an on-chip superconducting LC matching network for the RF-SET, we can minimize unwanted dissipation and optimize impedance matching. Using such a network, we fabricated one of world's fastest RF-SETs and measured the quantum noise of an S-SET near the quantum limit [4]. In the later part, we develop a design consisting of an SET embedded in a circuit quantum electrodynamics (QED) architecture, where the SET is coupled to a coplanar waveguide (CPW) resonator. The resonator is carefully designed to allow introduction of a DC voltage or current bias to the microwave cavity without significantly disturbing the cavity modes or degrading the quality factor [5]. Our proposed experiments will be focused on the zero bias region of the SET where it is strongly nonlinear.

  14. Five-port silicon optical router based on Mach—Zehnder optical switches for photonic networks-on-chip

    Science.gov (United States)

    Yunchou, Zhao; Hao, Jia; Jianfeng, Ding; Lei, Zhang; Xin, Fu; Lin, Yang

    2016-11-01

    With the continuous development of integrated circuits, the performance of the processor has been improved steadily. To integrate more cores in one processor is an effective way to improve the performance of the processor, while it is impossible to further improve the property of the processor by only increasing the clock frequency. For a processor with integrated multiple cores, its performance is determined not only by the number of cores, but also by communication efficiency between them. With more processor cores integrated on a chip, larger bandwidths are required to establish the communication among them. The traditional electrical interconnect has gradually become a bottleneck for improving the performance of multiple-core processors due to its limited bandwidth, high power consumption, and long latency. The optical interconnect is considered as a potential way to solve this issue. The optical router is the key device for realizing the optical interconnect. Its basic function is to achieve the data routing and switching between the local node and the multi-node. In this paper we present a five-port optical router for Mesh photonics network-on-chip. A five-port optical router composed of eight thermally tuned silicon Mach—Zehnder optical switches is demonstrated. The experimental spectral responses indicate that the optical signal-to-noise ratios of the optical router are over 13 dB in the wavelength range of 1525-1565 nm for all of its 20 optical links. Each optical link can manipulate 50 wavelength channels with the channel spacing of 100 GHz and the data rate of 32 Gbps for each wavelength channel in the same wavelength range. The lowest energy efficiency of the optical router is 43.4 fJ/bit. Project supported by the National High Technology Research and Development Program of China (Nos. 2015AA010103, 2015AA010901) and the National Natural Science Foundation of China (Nos. 61575187, 61235001, 61505198, 61377067).

  15. Stereolithographic hydrogel printing of 3D culture chips with biofunctionalized complex 3D perfusion networks

    DEFF Research Database (Denmark)

    Zhang, Rujing; Larsen, Niels Bent

    2017-01-01

    the required freedom in design, detail and chemistry for fabricating truly 3D constructs have remained limited. Here, we report a stereolithographic high-resolution 3D printing technique utilizing poly(ethylene glycol) diacrylate (PEGDA, MW 700) to manufacture diffusion-open and mechanically stable hydrogel...... and material flexibility by embedding a highly compliant cell-laden gelatin hydrogel within the confines of a 3D printed resilient PEGDA hydrogel chip of intermediate compliance. Overall, our proposed strategy represents an automated, cost-effective and high resolution technique to manufacture complex 3D......Three-dimensional (3D) in vitro models capturing both the structural and dynamic complexity of the in vivo situation are in great demand as an alternative to animal models. Despite tremendous progress in engineering complex tissue/organ models in the past decade, approaches that support...

  16. Demonstration of efficient on-chip photon transfer in self-assembled optoplasmonic networks.

    Science.gov (United States)

    Ahn, Wonmi; Hong, Yan; Boriskina, Svetlana V; Reinhard, Björn M

    2013-05-28

    Plasmonic nanoantennas facilitate the manipulation of light fields on deeply sub-diffraction-limited length scales, but high dissipative losses in metals make new approaches for an efficient energy transfer in extended on-chip integrated plasmonic circuits mandatory. We demonstrate in this article efficient photon transfer in discrete optoplasmonic molecules comprising gold nanoparticle (NP) dimer antennas located in the evanescent field of a 2 μm diameter polystyrene bead, which served as an optical microcavity (OM). The optoplasmonic molecules were generated through a guided self-assembly strategy in which the OMs were immobilized in binding sites generated by quartz (SiO2) or silicon posts that contained plasmonic nanoantennas on their tips. Control of the post height facilitated an accurate positioning of the plasmonic antennas into the evanescent field of the whispering gallery modes located in the equatorial plane of the OM. Cy3 and Cy5.5 dyes were tethered to the plasmonic antennas through oligonucleotide spacers to act as on-chip light sources. The intensity of Cy3 was found to be increased relative to that of Cy5.5 in the vicinity of the plasmonic antennas where strongly enhanced electric field intensity and optical density of states selectively increase the excitation and emission rates of Cy3 due to spectral overlap with the plasmon. The fluorescent dyes preferentially emitted into the OM, which efficiently trapped and recirculated the photons. We experimentally determined a relative photon transfer efficiency of 44% in non-optimized self-assembled optoplasmonic molecules in this proof-of-principle study.

  17. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    CERN Document Server

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  18. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    CERN Document Server

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  19. A CMOS vision chip for a contrast-enhanced image using a logarithmic APS and a switch-selective resistive network

    Science.gov (United States)

    Kong, Jae-Sung; Kim, Sang-Heon; Sung, Dong-Kyu; Seo, Sang-Ho; Shin, Jang-Kyoo

    2007-02-01

    In this paper, a vision chip for a contrast-enhanced image based on a structure of a biological retina is introduced. The key advantage of this structure is high speed of signal processing. In a conventional active pixel sensor (APS), the charge accumulation time limits its operation speed. In order to enhance the speed, a logarithmic APS was applied to the vision chip. By applying a MOS-type photodetector to the logarithmic APS, we could achieve sufficient output swing for the vision chip in natural illumination condition. In addition, a CMOS buffer circuit, a common drain amplifier, is commonly used for both raw and smoothed images by using additional switches. By using the switch-selective resistive network, the total number of MOSFETs for a unit pixel and the fixed-pattern noise were reduced. A vision chip with a 160×120 pixel array was fabricated using a 0.35 μm double-poly four-metal CMOS technology, and its operation was experimentally investigated.

  20. Piecewise Linear Approach for Timing Simulation of VLSI (Very-Large-Scale-Integrated) Circuits on Serial and Parallel Computers.

    Science.gov (United States)

    1987-12-01

    328 S % 33880E ° PIECEWISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS Ongky Tejayadi UNIVE,’RSITY OF ILL...APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS 12. PERSONAL AUTHOR(S) Tejayadi, Ongky 13a. TYPE OF REPO~Z J,..-13b...PIECE’WISE LINEAR APPROACH FOR TIMING SIMULATION OF VLSI CIRCUITS ON SERIAL AND PARALLEL COMPUTERS BY ONGKY TEJAYADI B.S., University of Illinois

  1. Carbon nanotube based VLSI interconnects analysis and design

    CERN Document Server

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  2. Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems

    Science.gov (United States)

    Giulioni, Massimiliano; Corradi, Federico; Dante, Vittorio; Del Giudice, Paolo

    2015-10-01

    Neuromorphic chips embody computational principles operating in the nervous system, into microelectronic devices. In this domain it is important to identify computational primitives that theory and experiments suggest as generic and reusable cognitive elements. One such element is provided by attractor dynamics in recurrent networks. Point attractors are equilibrium states of the dynamics (up to fluctuations), determined by the synaptic structure of the network; a ‘basin’ of attraction comprises all initial states leading to a given attractor upon relaxation, hence making attractor dynamics suitable to implement robust associative memory. The initial network state is dictated by the stimulus, and relaxation to the attractor state implements the retrieval of the corresponding memorized prototypical pattern. In a previous work we demonstrated that a neuromorphic recurrent network of spiking neurons and suitably chosen, fixed synapses supports attractor dynamics. Here we focus on learning: activating on-chip synaptic plasticity and using a theory-driven strategy for choosing network parameters, we show that autonomous learning, following repeated presentation of simple visual stimuli, shapes a synaptic connectivity supporting stimulus-selective attractors. Associative memory develops on chip as the result of the coupled stimulus-driven neural activity and ensuing synaptic dynamics, with no artificial separation between learning and retrieval phases.

  3. Experimental demonstration of a 24-port packaged multi-microring network-on-chip in silicon photonic platform.

    Science.gov (United States)

    Gambini, Fabrizio; Pintus, Paolo; Faralli, Stefano; Chiesa, Marco; Preve, Giovan Battista; Cerutti, Isabella; Andriolli, Nicola

    2017-09-04

    A 24-port packaged multi-microring optical network-on-chip has been tested for simultaneous co- and counter-propagating transmissions at the same wavelength at 10 Gbps. In the co-propagating scenario communications up to five hops with one interfering signal have been tested, together with transmissions impaired by up to three interfering signals. In the counter-propagating scenario the device performance has been investigated exploiting the ring resonators in both shared-source and shared-destination configurations. The spectral characterization is in good agreement with the theoretical results. Bit-error-rate measurements indicate power penalties at BER=10 -9 limited to (i) 0.5 dB in the co-propagating scenarios independently from the number of interfering transmissions, (ii) 0.8 dB in the counter-propagating scenario with shared-source configuration, and (iii) 2 dB in the counter-propagating scenario with shared-destination configuration.

  4. A programming environment to control switching networks based on STC104 packet routing chip

    Science.gov (United States)

    Legrand, I. C.; Schwendicke, U.; Leich, H.; Medinnis, M.; Koehler, A.; Wegner, P.; Sulanke, K.; Dippel, R.; Gellrich, A.

    1997-02-01

    The software environment used to control a large switching architecture based on SGS-Thomson STC104 (an asynchronous 32-way dynamic packet routing chip) is presented. We are evaluating this switching technology for large scale, real-time parallel systems. A Graphical User Interface (GUI) written as a multi-thread application in Java allows to set the switch configuration and to continuously monitor the state of each link. This GUI connects to a multi-thread server via TCP/IP sockets. The server is running on a PC-Linux system and implements the virtual channel protocol in communicating with the STC104 switching units using the Data Strobe link or the VME bus. Linux I/O drivers to control the Data Strobe link parallel adaptor (STC101) were developed. For each client the server creates a new thread and allocates a new socket for communications. The Java code of the GUI may be transferred to any client using the http protocol providing a user friendly interface to the system with real-time monitoring which is also platform independent.

  5. Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2012-01-01

    Full Text Available Two multiprocessor system-on-chip (MPSoC architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

  6. The Aethereal Network on Chip after Ten Years: Goals, Evolution, Lessons, and Future

    NARCIS (Netherlands)

    Goossens, Kees; Hansson, A.

    2010-01-01

    The goals for the Æthereal network on silicon, as it was then called, were set in 2000 and its concepts were defined early 2001. Ten years on, what has been achieved? Did we meet the goals, and what is left of the concepts? In this paper we answer those questions, and evaluate different

  7. Fixed latency on-chip interconnect for hardware spiking neural network architectures

    NARCIS (Netherlands)

    Pande, Sandeep; Morgan, Fearghal; Smit, Gerardus Johannes Maria; Bruintjes, Tom; Rutgers, J.H.; Cawley, Seamus; Harkin, Jim; McDaid, Liam

    Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable

  8. Biologically-inspired On-chip Learning in Pulsed Neural Networks

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Woodburn, Robin

    1999-01-01

    , explaining what we mean by this term and providing an example of a robust, self-learning design that can solve simple classical-conditioning tasks, We give details of the design of individual circuits to perform component functions, which can then be combined into a network to solve the task. We argue...

  9. A 3 W High-Voltage Single-Chip Green Light-Emitting Diode with Multiple-Cells Network

    Directory of Open Access Journals (Sweden)

    W. Wang

    2015-01-01

    Full Text Available A parallel and series network structure was introduced into the design of the high-voltage single-chip (HV-SC light-emitting diode to inhibit the effect of current crowding and to improve the yield. Using such a design, a 6.6×5 mm2 large area LED chip of 24 parallel stages was demonstrated with 3 W light output power (LOP at the current of 500 mA. The forward voltage was measured to be 83 V with the same current injection, corresponding to 3.5 V for a single stage. The LED chip’s average thermal resistance was identified to be 0.28 K/W by using infrared thermography analysis.

  10. On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices

    National Research Council Canada - National Science Library

    Carlos García-meca; Sergio Lechago; Antoine Brimont; Amadeu Griol; Sara Mas; Luis Sánchez; Laurent Bellieres; Nuria S Losilla; Javier Martí

    2017-01-01

    Photonic integrated circuits are developing as key enabling components for high-performance computing and advanced network-on-chip, as well as other emerging technologies such as lab-on-chip sensors...

  11. Simultaneous detection of duplex DNA oligonucleotides using a SERS-based micro-network gradient chip.

    Science.gov (United States)

    Choi, Namhyun; Lee, Kangsun; Lim, Dong Woo; Lee, Eun Kyu; Chang, Soo-Ik; Oh, Kwang W; Choo, Jaebum

    2012-12-21

    We report the development of a programmable surface-enhanced Raman scattering (SERS)-based micro-network gradient platform to simultaneously detect two different types of DNA oligomer mixtures. The utility of this platform was demonstrated by quantitative analysis of two breast cancer-related (BRCA1) DNA oligomer mixtures. To generate on-demand concentration gradients, the microfluidic circuit was designed using an electric-hydraulic analogy. Then a multi-gradient microfluidic channel was fabricated based on the theoretical design of the concentration control module. These micro-network structures automatically produce a series of different concentration gradients by continuously mixing Cy3-labeled DNA oligomers (BRAC1-Mutation) with TAMRA-labeled DNA oligomer (BRAC1-Wild). The SERS signals for different ratios of duplex DNA oligomer mixtures, adsorbed on the surface of silver nanoparticles, were measured under flowing conditions. Total analysis time from serial mixing to SERS detection takes less than 10 min because all experimental conditions are automatically controlled inside the exquisitely designed microfluidic channel. This novel SERS-based DNA sensing technology in a micro-network gradient channel is expected to be a powerful analytical tool to simultaneously detect multiple DNA oligomer mixtures.

  12. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

    Science.gov (United States)

    Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

    2016-12-01

    Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

  13. Thermosetting polyimide resin matrix composites with interpenetrating polymer networks for precision foil resistor chips based on special mechanical performance requirements

    Energy Technology Data Exchange (ETDEWEB)

    Wang, X.Y., E-mail: wxy@tju.edu.cn [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China); Ma, J.X.; Li, C.G. [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China); Wang, H.X. [ZHENGHE electronics Co., Ltd, Jining 272023 (China)

    2014-04-01

    Highlights: • Macromolecular materials were chosen to modify thermosetting polyimide (TSPI). • The formation of IPN structure in TSPI composite polymers was discussed. • The special mechanical properties required were the main study object. • The desired candidate materials should have proper hardness and toughness. • The specific mechanical data are quantitatively determined by experiments. - Abstract: Based on interpenetrating networks (IPNs) different macromolecular materials such as epoxy, phenolic, and silicone resin were chosen to modify thermosetting polyimide (TSPI) resin to solve the lack of performance when used for protecting precision foil resistor chips. Copolymerization modification, controlled at curing stage, was used to prepare TSPI composites considering both performance and process requirements. The mechanical properties related to trimming process were mainly studied due to the special requirements of the regularity of scratch edges caused by a tungsten needle. The analysis on scratch edges reveals that the generation and propagation of microcracks caused by scratching together with crack closure effect may lead to regular scratch traces. Experiments show that the elongation at break of TSPI composites is the main reason that determines the special mechanical properties. The desired candidate materials should have proper hardness and toughness, and the specific mechanical data are that the mean elongation at break and tensile strength of polymer materials are in the range of 9.2–10.4% and 100–107 MPa, respectively. Possible reasons for the effect of the modifiers chosen on TSPI polymers, the reaction mechanisms on modified TSPI resin and the IPN structure in TSPI composite polymers were discussed based on IR and TG analysis.

  14. Liquid state machine with dendritically enhanced readout for low-power, neuromorphic VLSI implementations.

    Science.gov (United States)

    Roy, Subhrajit; Banerjee, Amitava; Basu, Arindam

    2014-10-01

    In this paper, we describe a new neuro-inspired, hardware-friendly readout stage for the liquid state machine (LSM), a popular model for reservoir computing. Compared to the parallel perceptron architecture trained by the p-delta algorithm, which is the state of the art in terms of performance of readout stages, our readout architecture and learning algorithm can attain better performance with significantly less synaptic resources making it attractive for VLSI implementation. Inspired by the nonlinear properties of dendrites in biological neurons, our readout stage incorporates neurons having multiple dendrites with a lumped nonlinearity (two compartment model). The number of synaptic connections on each branch is significantly lower than the total number of connections from the liquid neurons and the learning algorithm tries to find the best 'combination' of input connections on each branch to reduce the error. Hence, the learning involves network rewiring (NRW) of the readout network similar to structural plasticity observed in its biological counterparts. We show that compared to a single perceptron using analog weights, this architecture for the readout can attain, even by using the same number of binary valued synapses, up to 3.3 times less error for a two-class spike train classification problem and 2.4 times less error for an input rate approximation task. Even with 60 times larger synapses, a group of 60 parallel perceptrons cannot attain the performance of the proposed dendritically enhanced readout. An additional advantage of this method for hardware implementations is that the 'choice' of connectivity can be easily implemented exploiting address event representation (AER) protocols commonly used in current neuromorphic systems where the connection matrix is stored in memory. Also, due to the use of binary synapses, our proposed method is more robust against statistical variations.

  15. Integration of gene chip and topological network techniques to screen a candidate biomarker gene (CBG) for predication of the source water carcinogenesis risks on mouse Mus musculus.

    Science.gov (United States)

    Sun, Jie; Cheng, Shupei; Li, Aimin; Zhang, Rui; Wu, Bing; Zhang, Yan; Zhang, Xuxiang

    2011-07-01

    Screening of a candidate biomarker gene (CBG) to predicate the carcinogenesis risks in the Yangtze River source of drinking water in Nanjing area (YZR-SDW-NJ) on mouse (Mus musculus) was conducted in this research. The effects of YZR-SDW-NJ on the genomic transcriptional expression levels were measured by the GeneChip(®) Mouse Genome and data treated by the GO database analysis. The 298 genes discovered as the differently expressed genes (DEGs) were down-regulated and their values were ≤-1.5-fold. Of the 298 DEGs, 25 were cancer-related genes selected as the seed genes to build a topological network map with Genes2Networks software, only 7 of them occurred at the constructed map. Smad2 gene was at the constructed map center and could be identified as a candidate biomarker gene (CBG) primarily which involves the genesis and development of colorectal, leukemia, lung and prostate cancers directly. Analysis of the gene signal pathway further approved that smad2 gene had the relationships closely to other 16 cancer-related genes and could be used as a CBG to indicate the carcinogenic risks in YZR-SDW-NJ. The data suggest that integration of gene chip and network techniques may be a way effectively to screen a CBG. And the parameter values for further judgment of the CBG through signal pathway relationship analysis also will be discussed.

  16. Nonlinear Circuits and Neural Networks: Chip Implementation and Applications of the TeraOPS CNN Dynamic Array Supercomputer

    National Research Council Canada - National Science Library

    Chua, L

    1998-01-01

    .... Advances in research have been made in the following areas: (1) The design and implementation of the first-ever ARAM in the CNN Chip Set Architecture was successfully competed, and the samples were successfully tested; (2...

  17. Sucrose-based fabrication of 3D-networked, cylindrical microfluidic channels for rapid prototyping of lab-on-a-chip and vaso-mimetic devices.

    Science.gov (United States)

    Lee, Jiwon; Paek, Jungwook; Kim, Jaeyoun

    2012-08-07

    We present a new fabrication scheme for 3D-networked, cylindrical microfluidic (MF) channels based on shaping, bonding, and assembly of sucrose fibers. It is a simple, cleanroom-free, and environment-friendly method, ideal for rapid prototyping of lab-on-a-chip devices. Despite its simplicity, it can realize complex 3D MF channel architectures such as cylindrical tapers, internal loops, end-to-side junctions, tapered junctions, and stenosis. The last two will be of special use for realizing vaso-mimetic MF structures. It also enables molding with polymers incompatible with high-temperature processing.

  18. System-level network simulation for robust centrifugal-microfluidic lab-on-a-chip systems.

    Science.gov (United States)

    Schwarz, I; Zehnle, S; Hutzenlaub, T; Zengerle, R; Paust, N

    2016-05-10

    Centrifugal microfluidics shows a clear trend towards a higher degree of integration and parallelization. This trend leads to an increase in the number and density of integrated microfluidic unit operations. The fact that all unit operations are processed by the same common spin protocol turns higher integration into higher complexity. To allow for efficient development anyhow, we introduce advanced lumped models for network simulations in centrifugal microfluidics. These models consider the interplay of centrifugal and Euler pressures, viscous dissipation, capillary pressures and pneumatic pressures. The simulations are fast and simple to set up and allow for the precise prediction of flow rates as well as switching and valving events. During development, channel and chamber geometry variations due to manufacturing tolerances can be taken into account as well as pipetting errors, variations of contact angles, compliant chamber walls and temperature variations in the processing device. As an example of considering these parameters during development, we demonstrate simulation based robustness analysis for pneumatic siphon valving in centrifugal microfluidics. Subsequently, the influence of liquid properties on pumping and valving is studied for four liquids relevant for biochemical analysis, namely, water (large surface tension), blood plasma (large contact angle hysteresis), ethanol/water (highly wetting) and glycerine/water (highly viscous). In a second example, we derive a spin protocol to attain a constant flow rate under varying pressure conditions. Both examples show excellent agreement with experimental validations.

  19. A parallel VLSI architecture for a digital filter using a number theoretic transform

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1983-01-01

    The advantages of a very large scalee integration (VLSI) architecture for implementing a digital filter using fermat number transforms (FNT) are the following: It requires no multiplication. Only additions and bit rotations are needed. It alleviates the usual dynamic range limitation for long sequence FNT's. It utilizes the FNT and inverse FNT circuits 100% of the time. The lengths of the input data and filter sequences can be arbitraty and different. It is regular, simple, and expandable, and as a consequence suitable for VLSI implementation.

  20. Circuit design of VLSI for microelectronic coordinate-sensitive detector for material element analysis

    Directory of Open Access Journals (Sweden)

    Sidorenko V. P.

    2012-08-01

    Full Text Available There has been designed, manufactured and tested a VLSI providing as a part of the microelectronic coordinate-sensitive detector the simultaneous elemental analysis of all the principles of the substance. VLSI ensures the amplifier-converter response on receiving of 1,6.10–13 С negative charge to its input. Response speed of the microcircuit is at least 3 MHz in the counting mode and more than 4 MHz in the counter information read-out mode. The power consumption of the microcircuit is no more than 7 mA.

  1. SU-8 cantilever chip interconnection

    DEFF Research Database (Denmark)

    Johansson, Alicia Charlotte; Janting, Jakob; Schultz, Peter

    2006-01-01

    The polymer SU-8 is becoming widely used for all kinds of micromechanical and microfluidic devices, not only as a photoresist but also as the constitutional material of the devices. Many of these polymeric devices need to include a microfluidic system as well as electrical connection from...... the electrodes on the SU-8 chip to a printed circuit board. Here, we present two different methods of electrically connecting an SU-8 chip, which contains a microfluidic network and free-hanging mechanical parts. The tested electrical interconnection techniques are flip chip bonding using underfill or flip chip...... bonding using an anisotropic conductive film (ACF). These are both widely used in the Si industry and might also be used for the large scale interconnection of SU-8 chips. The SU-8 chip, to which the interconnections are made, has a microfluidic channel with integrated micrometer-sized cantilevers...

  2. DIALOG and SYNC a VLSI chip set for timing of the LHCb Muon detector

    CERN Document Server

    Cadeddu, S; Deplano, C; Lai, A

    2004-01-01

    The Muon detector of the LHCb experiment at CERN plays a fundamental role in the first trigger level. It is mainly realized by means of a MWPC technology and consists of about 126,000 front-end channels. High efficiency is necessary both at detector and front-end level to satisfy the trigger requirement of 5 hits per 5 Muon stations with an overall efficiency of 95%. This corresponds to having a single front- end channel detection efficiency of 99% within a time window of 20 ns and also poses the problem of an accurate time alignment of the whole detector. The problem is addressed by designing two custom integrated circuits, named DIALOG and SYNC, realized in the IBM 0.25 mu m radiation hard technology. (3 refs).

  3. Dimensionality reduction in conic section function neural network

    Indian Academy of Sciences (India)

    R. Narasimhan (Krishtel eMaging) 1461 1996 Oct 15 13:05:22

    layer, for input pattern p and θj is the threshold value. The output of the hidden ... The weights, centres and angle values are updated using error back propagation so that the network would converge ..... Delgado-Frias J G, Moore W R 1994 VLSI for neural networks and artificial intelligence (New York: Plenum). Dorffner G ...

  4. The E3 ubiquitin ligase CHIP/miR-92b/PTEN regulatory network contributes to tumorigenesis of glioblastoma.

    Science.gov (United States)

    Xu, Tao; Wang, Hongxiang; Jiang, Mei; Yan, Yong; Li, Weiqing; Xu, Hanchong; Huang, Qilin; Lu, Yicheng; Chen, Juxiang

    2017-01-01

    Glioblastoma (GBM) is the most frequent, aggressive and fatal tumor in the central nervous system, while PTEN signaling is frequently deregulated in human GBM. We previously reported the up-regulation of the carboxyl terminal of Hsp70-interacting protein (CHIP) in GBM, however, the causal link between its dysregulation and tumorigenesis has not been established. Using miRNA microarrays and quantitative RT-PCR (qRT-PCR), we found activation of CHIP leads to increased transcription of miR-92b. Further studies in T98G and LN229 cells showed overexpression of miR-92b elicited reduction of PTEN and efficiently rescued glioma development in CHIP knock-down cells. The core pathway, PI3K/Akt pathway, was then upregulated, which promoted GBM cell proliferation. Meanwhile, genetic ablation of miR-92b could restore PTEN expression and inhibit glioma growth. These data demonstrate that the CHIP/miR-92b/PTEN axis serves as a new mechanism underlying GBM tumorigenesis, providing potential new therapeutic targets.

  5. Distributed Processing Using Single-chip Microcomputers

    National Research Council Canada - National Science Library

    Pritchett, William

    1996-01-01

    This project investigates the use of single-chip microprocessors as nodes in a token ring control network and explores the implementation of a protocol to manage communication across such a network...

  6. VLSI top-down design based on the separation of hierarchies

    NARCIS (Netherlands)

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  7. Diseño e Implementación de un Multiprocessor Systems-on-Chip (MPSoC Interconectado por una Networks-on-Chip (NoC

    Directory of Open Access Journals (Sweden)

    Wilson Mauricio Chicaiza

    2013-11-01

    Full Text Available En el presente documento se presenta una breve caracterización de los medios de comunicación empleados en arquitecturas multiprocesadas. Esta caracterización tiene como objetivo principal el mostrar un nuevo modelo de comunicación basado en conmutación de paquetes a los cuales se les denomina como Networks-On-Chip (NoC. Esta publicación muestra una arquitectura de red llamada NoC Hermes, la cual fue interconectada a un Multiprocessor-Systems-on-Chip (MPSoC compuesto de cuatro procesadores MicroBlaze. Está conexión se la realizó gracias al diseño y desarrollo de una Interfaz de Red generada en código VHDL. Por medio de la Interfaz de Red se consiguió que los procesadores MicroBlaze interactúen con los Switches de Hermes a fin de crear una arquitectura multiprocesada interconectada por una NoC. Con el motivo de realizar comparaciones también se creó otra arquitectura de multiprocesadores interconectados por buses. Para ambas arquitecturas se desarrolló una aplicación de Esteganografía enla que existe multiprocesamiento de dos procesadores trabajando simultáneamente. Lamentablemente sobre dicha aplicación no fue posible medir directamente la latencia y el consumo de energía, razón por la cual se utilizó simuladores que permitieron estimar dichas mediciones.

  8. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Directory of Open Access Journals (Sweden)

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  9. Using a single chip FEC for satellite systems

    Science.gov (United States)

    Onotera, L.; Nicholson, R.

    Information transmission over digital satellite communication channels is primarily power-limited, where forward error correction (FEC) codes can significantly improve performance. The use of FEC can reduce the required signal to noise ratio to sustain a given bit error rate. The use of forward error correction has become a standard part of present day digital satellite communication systems. Means of applying a new very large scale integration (VLSI) integrated circuit FEC chip into various kinds of systems is discussed. Specifically, some of the considerations and tradeoffs in continuous single channel per carrier (SCPC), multiple channels per carrier (MCPC), and burst systems are related to the new design. This new chip will provide an effective space and cost advantage by inserting a powerful forward error correction capability into most types of satellite digital communication links.

  10. A Multi-Verse Optimizer with Levy Flights for Numerical Optimization and Its Application in Test Scheduling for Network-on-Chip.

    Science.gov (United States)

    Hu, Cong; Li, Zhi; Zhou, Tian; Zhu, Aijun; Xu, Chuanpei

    2016-01-01

    We propose a new meta-heuristic algorithm named Levy flights multi-verse optimizer (LFMVO), which incorporates Levy flights into multi-verse optimizer (MVO) algorithm to solve numerical and engineering optimization problems. The Original MVO easily falls into stagnation when wormholes stochastically re-span a number of universes (solutions) around the best universe achieved over the course of iterations. Since Levy flights are superior in exploring unknown, large-scale search space, they are integrated into the previous best universe to force MVO out of stagnation. We test this method on three sets of 23 well-known benchmark test functions and an NP complete problem of test scheduling for Network-on-Chip (NoC). Experimental results prove that the proposed LFMVO is more competitive than its peers in both the quality of the resulting solutions and convergence speed.

  11. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    OpenAIRE

    T. Kalavathi Devi; Sakthivel Palaniappan

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the powe...

  12. Handbook of VLSI microlithography principles, technology and applications

    CERN Document Server

    Glendinning, William B

    1991-01-01

    This handbook gives readers a close look at the entire technology of printing very high resolution and high density integrated circuit (IC) patterns into thin resist process transfer coatings-- including optical lithography, electron beam, ion beam, and x-ray lithography. The book's main theme is the special printing process needed to achieve volume high density IC chip production, especially in the Dynamic Random Access Memory (DRAM) industry. The book leads off with a comparison of various lithography methods, covering the three major patterning parameters of line/space, resolution, line e

  13. An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1991-01-01

    A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required......- mu m CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V/sub DD/=4.75 V and T/sub A/=70 degrees C). The core of the chip (excluding pad cells) is 7.8*5.1 mm/sup 2/ and contains approximately 50000 transistors...

  14. Analysis and compensation of the effects of analog VLSI arithmetic on the LMS algorithm.

    Science.gov (United States)

    Carvajal, Gonzalo; Figueroa, Miguel; Sbarbaro, Daniel; Valenzuela, Waldo

    2011-07-01

    Analog very large scale integration implementations of neural networks can compute using a fraction of the size and power required by their digital counterparts. However, intrinsic limitations of analog hardware, such as device mismatch, charge leakage, and noise, reduce the accuracy of analog arithmetic circuits, degrading the performance of large-scale adaptive systems. In this paper, we present a detailed mathematical analysis that relates different parameters of the hardware limitations to specific effects on the convergence properties of linear perceptrons trained with the least-mean-square (LMS) algorithm. Using this analysis, we derive design guidelines and introduce simple on-chip calibration techniques to improve the accuracy of analog neural networks with a small cost in die area and power dissipation. We validate our analysis by evaluating the performance of a mixed-signal complementary metal-oxide-semiconductor implementation of a 32-input perceptron trained with LMS.

  15. DNA Chip

    Indian Academy of Sciences (India)

    involved in the pathology of schizophrenia. In the human ge- nome, the ratio between coding and non-coding DNA is very low (less than 3% of the human .... construction of a Tm-specific chip, i.e. all the oligos/cDNA on the chip will hybridize at the same temperature. The techniques available are still not able to create a chip ...

  16. Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

    Directory of Open Access Journals (Sweden)

    S. Jayanthy

    2012-01-01

    Full Text Available As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG method based on a modified Fanout Oriented (FAN to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

  17. A subthreshold aVLSI implementation of the Izhikevich simple neuron model.

    Science.gov (United States)

    Rangan, Venkat; Ghosh, Abhishek; Aparin, Vladimir; Cauwenberghs, Gert

    2010-01-01

    We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

  18. On-chip cellomics assay enabling algebraic and geometric understanding of epigenetic information in cellular networks of living systems. 1. Temporal aspects of epigenetic information in bacteria.

    Science.gov (United States)

    Yasuda, Kenji

    2012-01-01

    A series of studies aimed at developing methods and systems of analyzing epigenetic information in cells and in cell networks, as well as that of genetic information, was examined to expand our understanding of how living systems are determined. Because cells are minimum units reflecting epigenetic information, which is considered to map the history of a parallel-processing recurrent network of biochemical reactions, their behaviors cannot be explained by considering only conventional DNA information-processing events. The role of epigenetic information on cells, which complements their genetic information, was inferred by comparing predictions from genetic information with cell behaviour observed under conditions chosen to reveal adaptation processes, population effects and community effects. A system of analyzing epigenetic information was developed starting from the twin complementary viewpoints of cell regulation as an "algebraic" system (emphasis on temporal aspects) and as a "geometric" system (emphasis on spatial aspects). Exploiting the combination of latest microfabrication technology and measurement technologies, which we call on-chip cellomics assay, we can control and re-construct the environments and interaction of cells from "algebraic" and "geometric" viewpoints. In this review, temporal viewpoint of epigenetic information, a part of the series of single-cell-based "algebraic" and "geometric" studies of celluler systems in our research groups, are summerized and reported. The knowlege acquired from this study may lead to the use of cells that fully control practical applications like cell-based drug screening and the regeneration of organs.

  19. A VLSI design for universal noiseless coding. [for spacecraft imaging equipment

    Science.gov (United States)

    Lee, Jun-Ji; Fang, Wai-Chi; Rice, Robert F.

    1988-01-01

    The practical, noiseless and efficient data-compression technique presented involves a conceptual VLSI design which is capable of meeting real-time processing rates and meets low-power, low-weight, and small-volume requirements. This form of data compression is applicable to image data compression aboard future low-budget spaceflight missions, for such instruments as visual-IR mapping spectrometers and high-resolution imaging spectrometers.

  20. Simulation-based analysis for NBTI degradation in combinational CMOS VLSI circuits

    OpenAIRE

    Georgiev, Zdravko

    2013-01-01

    The negative-bias temperature instability (NBTI) is one of the dominant aging degradation mechanisms in today Very Large Scale Integration (VLSI) Integrated Circuits (IC). With the further decreasing of the transistor dimensions and reduction of supply voltage, the NBTI degradation may become a critical reliability threat. Nevertheless, most of the EDA tools lack in the ability to predict and analyse the impact of the NBTI. Other tools able to analyse the NBTI, are often on very low design le...

  1. Importance of Thickness in Human Cardiomyocyte Network for Effective Electrophysiological Stimulation Using On-Chip Extracellular Microelectrodes

    Science.gov (United States)

    Hamada, Tomoyo; Nomura, Fumimasa; Kaneko, Tomoyuki; Yasuda, Kenji

    2012-06-01

    We have developed a three-dimensionally controlled in vitro human cardiomyocyte network assay for the measurements of drug-induced conductivity changes and the appearance of fatal arrhythmia such as ventricular tachycardia/fibrillation for more precise in vitro predictive cardiotoxicity. To construct an artificial conductance propagation model of a human cardiomyocyte network, first, we examined the cell concentration dependence of the cell network heights and found the existence of a height limit of cell networks, which was double-layer height, whereas the cardiomyocytes were effectively and homogeneously cultivated within the microchamber maintaining their spatial distribution constant and their electrophysiological conductance and propagation were successfully recorded using a microelectrode array set on the bottom of the microchamber. The pacing ability of a cardiomyocyte's electrophysiological response has been evaluated using microelectrode extracellular stimulation, and the stimulation for pacing also successfully regulated the beating frequencies of two-layered cardiomyocyte networks, whereas monolayered cardiomyocyte networks were hardly stimulated by the external electrodes using the two-layered cardiomyocyte stimulation condition. The stability of the lined-up shape of human cardiomyocytes within the rectangularly arranged agarose microchambers was limited for a two-layered cardiomyocyte network because their stronger force generation shrunk those cells after peeling off the substrate. The results indicate the importance of fabrication technology of thickness control of cellular networks for effective extracellular stimulation and the potential concerning thick cardiomyocyte networks for long-term cultivation.

  2. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Directory of Open Access Journals (Sweden)

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  3. Adaptive Capacity Management in Bluetooth Networks

    OpenAIRE

    Son, L.T.

    2004-01-01

    With the Internet and mobile wireless development, accelerated by high-speed and low cost VLSI device evolution, short range wireless communications have become more and more popular, especially Bluetooth. Bluetooth is a new short range radio technology that promises to be very convenient, low power, and low cost mobile ad hoc solution for the global interconnection of all mobile devices. To implement Bluetooth network as a true mobile ad hoc wireless network operating in short radio range, h...

  4. Assembly, chip and method of operating

    NARCIS (Netherlands)

    Reefman, D.; Roozeboom, F.; Klootwijk, J.H.

    2012-01-01

    The chip comprises a network of trench capacitors and an inductor, wherein the trench capacitors are coupled in parallel with a pattern of interconnects that is designed so as to limit generation of eddy current induced by the inductor in the interconnects. This allows the use of the chip as a

  5. On sparsely connected optimal neural networks

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V. [Los Alamos National Lab., NM (United States); Draghici, S. [Wayne State Univ., Detroit, MI (United States)

    1997-10-01

    This paper uses two different approaches to show that VLSI- and size-optimal discrete neural networks are obtained for small fan-in values. These have applications to hardware implementations of neural networks, but also reveal an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures. The first approach is based on implementing F{sub n,m} functions. The authors show that this class of functions can be implemented in VLSI-optimal (i.e., minimizing AT{sup 2}) neural networks of small constant fan-ins. In order to estimate the area (A) and the delay (T) of such networks, the following cost functions will be used: (i) the connectivity and the number-of-bits for representing the weights and thresholds--for good estimates of the area; and (ii) the fan-ins and the length of the wires--for good approximates of the delay. The second approach is based on implementing Boolean functions for which the classical Shannon`s decomposition can be used. Such a solution has already been used to prove bounds on the size of fan-in 2 neural networks. They will generalize the result presented there to arbitrary fan-in, and prove that the size is minimized by small fan-in values. Finally, a size-optimal neural network of small constant fan-ins will be suggested for F{sub n,m} functions.

  6. Inferring gene regulatory networks by integrating ChIP-seq/chip and transcriptome data via LASSO-type regularization methods.

    Science.gov (United States)

    Qin, Jing; Hu, Yaohua; Xu, Feng; Yalamanchili, Hari Krishna; Wang, Junwen

    2014-06-01

    Inferring gene regulatory networks from gene expression data at whole genome level is still an arduous challenge, especially in higher organisms where the number of genes is large but the number of experimental samples is small. It is reported that the accuracy of current methods at genome scale significantly drops from Escherichia coli to Saccharomyces cerevisiae due to the increase in number of genes. This limits the applicability of current methods to more complex genomes, like human and mouse. Least absolute shrinkage and selection operator (LASSO) is widely used for gene regulatory network inference from gene expression profiles. However, the accuracy of LASSO on large genomes is not satisfactory. In this study, we apply two extended models of LASSO, L0 and L1/2 regularization models to infer gene regulatory network from both high-throughput gene expression data and transcription factor binding data in mouse embryonic stem cells (mESCs). We find that both the L0 and L1/2 regularization models significantly outperform LASSO in network inference. Incorporating interactions between transcription factors and their targets remarkably improved the prediction accuracy. Current study demonstrates the efficiency and applicability of these two models for gene regulatory network inference from integrative omics data in large genomes. The applications of the two models will facilitate biologists to study the gene regulation of higher model organisms in a genome-wide scale. Copyright © 2014 Elsevier Inc. All rights reserved.

  7. On-Chip Cellomics Assay Enabling Algebraic and Geometric Understanding of Epigenetic Information in Cellular Networks of Living Systems. 1. Temporal Aspects of Epigenetic Information in Bacteria

    Directory of Open Access Journals (Sweden)

    Kenji Yasuda

    2012-05-01

    Full Text Available A series of studies aimed at developing methods and systems of analyzing epigenetic information in cells and in cell networks, as well as that of genetic information, was examined to expand our understanding of how living systems are determined. Because cells are minimum units reflecting epigenetic information, which is considered to map the history of a parallel-processing recurrent network of biochemical reactions, their behaviors cannot be explained by considering only conventional DNA information-processing events. The role of epigenetic information on cells, which complements their genetic information, was inferred by comparing predictions from genetic information with cell behaviour observed under conditions chosen to reveal adaptation processes, population effects and community effects. A system of analyzing epigenetic information was developed starting from the twin complementary viewpoints of cell regulation as an “algebraic” system (emphasis on temporal aspects and as a “geometric” system (emphasis on spatial aspects. Exploiting the combination of latest microfabrication technology and measurement technologies, which we call on-chip cellomics assay, we can control and re-construct the environments and interaction of cells from “algebraic” and “geometric” viewpoints. In this review, temporal viewpoint of epigenetic information, a part of the series of single-cell-based “algebraic” and “geometric” studies of celluler systems in our research groups, are summerized and reported. The knowlege acquired from this study may lead to the use of cells that fully control practical applications like cell-based drug screening and the regeneration of organs.

  8. Construction of pancreatic cancer double-factor regulatory network based on chip data on the transcriptional level.

    Science.gov (United States)

    Zhao, Li-Li; Zhang, Tong; Liu, Bing-Rong; Liu, Tie-Fu; Tao, Na; Zhuang, Li-Wei

    2014-05-01

    Transcription factor (TF) and microRNA (miRNA) have been discovered playing crucial roles in cancer development. However, the effect of TFs and miRNAs in pancreatic cancer pathogenesis remains vague. We attempted to reveal the possible mechanism of pancreatic cancer based on transcription level. Using GSE16515 datasets downloaded from gene expression omnibus database, we first identified the differentially expressed genes (DEGs) in pancreatic cancer by the limma package in R. Then the DEGs were mapped into DAVID to conduct the kyoto encyclopedia of genes and genomes (KEGG) pathway enrichment analysis. TFs and miRNAs that DEGs significantly enriched were identified by Fisher's test, and then the pancreatic cancer double-factor regulatory network was constructed. In our study, total 1117 DEGs were identified and they significantly enriched in 4 KEGG pathways. A double-factor regulatory network was established, including 29 DEGs, 24 TFs, 25 miRNAs. In the network, LAMC2, BRIP1 and miR155 were identified which may be involved in pancreatic cancer development. In conclusion, the double-factor regulatory network was found to play an important role in pancreatic cancer progression and our results shed new light on the molecular mechanism of pancreatic cancer.

  9. Specification and Design Methodologies for High-Speed Fault-Tolerant Array Algorithms and Structures for VLSI.

    Science.gov (United States)

    1987-06-01

    Verlag Lecture Notes 201, 1985. [She84] M. Sheeran , "muFP, a language for VLSI design", Proc. 1984 ACM Conference on LISP and Functional Programming...fMeshkinpour8S5 and Sheeran (Sheeran84] extended Backus’ Fl? language with operators to handle sequential circuits. 2 Brief Introduction to vFP vFP...Spring 1913, pp. 274-277. (201 Sheeran , M., "muFP, a Language for VLSI Design." Proc 1984 ACM Conference on LU and Functional Programming. August [4

  10. An effective timing characterization method for an accuracy-proved VLSI standard cell library

    Science.gov (United States)

    Jianhua, Jiang; Man, Liang; Lei, Wang; Yumei, Zhou

    2014-02-01

    This paper presents a method of tailoring the characterization and modeling timing of a VLSI standard cell library. The paper also presents a method to validate the reasonability of the value through accuracy analysis. In the process of designing a standard cell library, this method is applied to characterize the cell library. In addition, the error calculations of some simple circuit path delays are compared between using the characterization file and an Hspice simulation. The comparison results demonstrate the accuracy of the generated timing library file.

  11. Towards an automated system for the verification and diagnosis of intelligent VLSI circuits

    Science.gov (United States)

    Velazco, Raoul; Ziade, Haissam

    The main features of a system designed to cope with both the verification and diagnosis of Very Large Scale Integration (VLSI) intelligent circuits are detailed. The system is composed of a validation program generator, the GAPT (French Acronym for automatic generation of test programs) software and a microprocessor dedicated verification system, the TEMAC functional tester. GAPT/TEMAC tools allow an easy implementation of a top down diagnosis procedure. Each diagnosis action is composed of symptom analysis, malfunction hypothesis statement, sequence generation, execution, and result evaluation. It was successfully used in various microprocessor qualification/validation experiments. The system capabilities and the diagnosis procedure are illustrated by an actual 68000 microprocessor diagnosis experiment.

  12. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Directory of Open Access Journals (Sweden)

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  13. High-performance fault-tolerant VLSI systems using micro rollback

    Science.gov (United States)

    Tamir, Yuval; Tremblay, Marc

    1990-01-01

    A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.

  14. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Science.gov (United States)

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  15. Space division multiplexing chip-to-chip quantum key distribution

    DEFF Research Database (Denmark)

    Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld

    2017-01-01

    nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum...... keys are obtained, which are useful in crypto-systems and future quantum network....

  16. Low-Power and Optimized VLSI Implementation of Compact Recursive Discrete Fourier Transform (RDFT Processor for the Computations of DFT and Inverse Modified Cosine Transform (IMDCT in a Digital Radio Mondiale (DRM and DRM+ Receiver

    Directory of Open Access Journals (Sweden)

    Sheau-Fang Lei

    2013-05-01

    Full Text Available This paper presents a compact structure of recursive discrete Fourier transform (RDFT with prime factor (PF and common factor (CF algorithms to calculate variable-length DFT coefficients. Low-power optimizations in VLSI implementation are applied to the proposed RDFT design. In the algorithm, for 256-point DFT computation, the results show that the proposed method greatly reduces the number of multiplications/additions/computational cycles by 97.40/94.31/46.50% compared to a recent approach. In chip realization, the core size and chip size are, respectively, 0.84 × 0.84 and 1.38 × 1.38 mm2. The power consumption for the 288- and 256-point DFT computations are, respectively, 10.2 (or 0.1051 and 11.5 (or 0.1176 mW at 25 (or 0.273 MHz simulated by NanoSim. It would be more efficient and more suitable than previous works for DRM and DRM+ applications.

  17. Tissue culture on a chip: Developmental biology applications of self-organized capillary networks in microfluidic devices.

    Science.gov (United States)

    Miura, Takashi; Yokokawa, Ryuji

    2016-08-01

    Organ culture systems are used to elucidate the mechanisms of pattern formation in developmental biology. Various organ culture techniques have been used, but the lack of microcirculation in such cultures impedes the long-term maintenance of larger tissues. Recent advances in microfluidic devices now enable us to utilize self-organized perfusable capillary networks in organ cultures. In this review, we will overview past approaches to organ culture and current technical advances in microfluidic devices, and discuss possible applications of microfluidics towards the study of developmental biology. © 2016 Japanese Society of Developmental Biologists.

  18. Integrated Circuit For Simulation Of Neural Network

    Science.gov (United States)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  19. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  20. On-chip anticancer drug test of regular tumor spheroids formed in microwells by a distributive microchannel network.

    Science.gov (United States)

    Kim, Choong; Bang, Jae Hoon; Kim, Young Eun; Lee, Soo Hyun; Kang, Ji Yoon

    2012-10-21

    This paper proposes a new cytotoxicity assay in a microfluidic device with microwells and a distributive microfluidic channel network for the formation of cancer cell spheroids. The assay can generate rapid and uniform cell clusters in microwells and test in situ cytotoxicity of anticancer drugs including sequential drug treatments, long term culture of spheroids and cell viability assays. Inlet ports are connected to the microwells by a hydraulic resistance network. This uniform distribution of cell suspensions results in regular spheroid dimensions. Injected cancer cells were trapped in microwells, and aggregated into tumor spheroids within 3 days. A cytotoxicity test of the spheroids in microwells was subsequently processed in the same device without the extraction of cells. The in situ cytotoxicity assay of tumor spheroids in microwells was comparable with the MTT assay on hanging drop spheroids using a conventional 96-well plate. It was observed that the inhibition rate of the spheroids was less than that in the 2D culture dish and the effect on tumor spheroids was different depending on the anticancer drug. This device could provide a convenient in situ assay tool to assess the cytotoxicity of anticancer drugs on tumor spheroids, offering more information than the conventional 2D culture plate.

  1. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Energy Technology Data Exchange (ETDEWEB)

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  2. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Science.gov (United States)

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  3. Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

    Science.gov (United States)

    Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

    1989-01-01

    Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

  4. Hydra: an Energy-efficient and Reconfigurable Network Interface

    NARCIS (Netherlands)

    van de Burgwal, M.D.; Smit, Gerardus Johannes Maria; Rauwerda, G.K.; Heysters, P.M.

    In heterogeneous tiled System-on-Chip architectures a Network-on-Chip is used to transport messages between processing elements. A reconfigurable network interface is used to connect the processing elements to the Network-on-Chip, converting the messages between both domains. This paper introduces

  5. An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing

    Directory of Open Access Journals (Sweden)

    Ginhac Dominique

    2008-01-01

    Full Text Available Abstract A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A pixel proof-of-concept chip was fabricated in a 0.35  m standard CMOS process, with a pixel size of 35  m 35  m. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second.

  6. Space division multiplexing chip-to-chip quantum key distribution.

    Science.gov (United States)

    Bacco, Davide; Ding, Yunhong; Dalgaard, Kjeld; Rottwitt, Karsten; Oxenløwe, Leif Katsuo

    2017-09-29

    Quantum cryptography is set to become a key technology for future secure communications. However, to get maximum benefit in communication networks, transmission links will need to be shared among several quantum keys for several independent users. Such links will enable switching in quantum network nodes of the quantum keys to their respective destinations. In this paper we present an experimental demonstration of a photonic integrated silicon chip quantum key distribution protocols based on space division multiplexing (SDM), through multicore fiber technology. Parallel and independent quantum keys are obtained, which are useful in crypto-systems and future quantum network.

  7. On-chip power delivery and management

    CERN Document Server

    Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

    2016-01-01

    This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

  8. Electronic device aspects of neural network memories

    Science.gov (United States)

    Lambe, J.; Moopenn, A.; Thakoor, A. P.

    1985-01-01

    The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

  9. KPIX a pixel detector imaging chip

    CERN Document Server

    Cadeddu, S; Caria, M

    2002-01-01

    We present a VLSI custom device, named KPIX, developed in a 0.6 mu m CMOS technology. The circuit is dedicated to readout solid-state detectors covering large areas (on the order of square centimetre) and featuring very small currents. KPIX integrates 1024 channels (current amplifiers) and 8 ADCs on a 15.5x4 mm sup 2 area. Both an analogue and digital readout are allowed, with a 10 bit amplitude resolution. Amplifiers are organized in 8 columns of 128 rows. When choosing the digital or the analogue readout, the complete set of channels can be read out in about 30 ms. The specific design of the amplification cells allows to measure very small input current levels, on the order of fractions of pico-ampere. Power consumption has also been kept at the level of 80 mu W per cell and 150 mW (peak value) in total. The specific chip architecture and geometry allow use of many KPIX circuits together in order to serve a large detector sensitive area. The KPIX structure is presented along with some measurements character...

  10. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Science.gov (United States)

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  11. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Science.gov (United States)

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  12. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Directory of Open Access Journals (Sweden)

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  13. Bufferless transmission in complex networks

    OpenAIRE

    Pu, Cunlai; Cui, Wei; Wu, Jiexin; Yang, Jian

    2017-01-01

    Complex bufferless networks such as on-chip networks and optical burst switching networks haven't been paid enough attention in network science. In complex bufferless networks, the store and forward mechanism is not applicable, since the network nodes are not allowed to buffer data packets. In this paper, we study the data transmission process in complex bufferless networks from the perspective of network science. Specifically, we use the Price model to generate the underlying network topolog...

  14. VLSI Research

    Science.gov (United States)

    1983-10-31

    Caesar and Mextra and other old programs, as well as several previously-unreleased pro- grams, such as Lyra. Crystal. Peg, and Tpack . The 1983...release was sent to eight beta test sites in January, and began general distribution on April 1. EL1. Tpack : A System for Combining Graphics and Procedures

  15. VLSI Research

    Science.gov (United States)

    1984-04-01

    23,1984 / CONTINENTAL BALLROOMS 6-9 / 9:00 A.M. *T-ś! J SESSION XII: MICROPROCESSORS ANO MICROCONTROLLERS THAM 12.1: A 32b NMOS Microprocessor...roisideration, AlC is insensitive to the interface-wrapt..2 charge. The difference between AVr and Al£, therefore, will be the con- tribution from the...reduction of AVr . Since the degree of impact ionization increases with the substrate bias, the end result is the observed decrease in AVj- with

  16. Design and performance analysis for a single-chip optoelectronic database filter

    Science.gov (United States)

    Tang, Jianjing; Rittgers, A.; Lorenz, J.; Miles, K.; Beyette, Fred R.

    2001-11-01

    The commercialization of CD-ROM drives has clearly demonstrated the ability of optical storage devices to meet the growing demand for archival data storage. However, with the continued expansion of electronic information resources, storage capacity requirements are expected to approach the terabyte level for personal users and exceed the petabyte level for databases and data warehouse systems. Further, many data-intensive applications require real-time data access rates. Thus, designers for the next generation of archival storage systems have the challenging task of providing storage capacities several orders of magnitude larger than existing systems while maintaining current data access times. To meet this challenge, we have developed a single-chip database filter suitable for large-capacity database systems that use page- oriented optical storage devices. Based on a photonic VLSI device technology, our data filter monolithically integrates optical detectors, photoreceiver circuits, data manipulation logic, and filter control circuitry onto a single CMOS chip that can be readily fabricated using a standard VLSI fabrication facility. Thus, our device is compatible with existing electronic device manufacturing technology and shares all of the reliability, uniformity, and manufacturability benefits associated with current electronic hardware. In addition to describing the database filter concept, this paper presents design and circuit evaluation data suggesting that a 32 X 32-bit filter fabricated in a 1.5-micrometers CMOS process could have an optical page read rate of 87 Mpage/s and support 123-Mrecord/s transfer rate to a host computer. Finally, queuing theory is used to show that even with the limitation of finite queue capacity, a database filter chip could be controlled to work at near-optimal performance, where database search time is limited by the data transfer rate into the host computer. Since only valid search data are passed through to the host computer

  17. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits

    Science.gov (United States)

    Xu, Peng; Pan, Zhongliang

    2017-09-01

    With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits. To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed. First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes. The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model. Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique and ABCD parameter matrix approach at local level, intermediate level and global level, respectively. Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits. It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system. Project supported by the Guangdong Provincial Natural Science Foundation of China (No. 2014A030313441), the Guangzhou Science and Technology Project (No. 201510010169), the Guangdong Province Science and Technology Project (No. 2016B090918071), and the National Natural Science Foundation of China (No. 61072028).

  18. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Directory of Open Access Journals (Sweden)

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  19. Design, Characterization and Test of the Associative Memory Chip AM06 for the Fast TracKer System

    CERN Document Server

    Liberali, Valentino; The ATLAS collaboration

    2016-01-01

    We present the performance of the new Associative Memory (AM) chip, designed and manufactured in 65 nm CMOS technology. The AM06 is the 6th version of a highly parallel ASIC processor for pattern recognition in high energy physics experiments. The AM06 is based on the XORAM cell architecture, which has been specifically designed to reduce power consumption and control complexity. The AM06 is a large chip, which contains memory banks that store all data of interest. The basic unit is a word of 18 bit. A group of 8 words (each of them related to a detector layer) is called a “pattern”. Each AM06 chip stores 2^17 patterns. The AM06 integrates serializer and deserializer IP blocks (working up to 2.4 GHz), to avoid routing congestion at the board level. AM06 is a complex VLSI chip, designed combining full-custom memory arrays, standard logic cells and IP blocks. It occupies a silicon area of 168 mm^2 and it contains about 421 millions transistors. The AM06 chip is able to perform a synchronous bitwise comparis...

  20. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Science.gov (United States)

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  1. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Directory of Open Access Journals (Sweden)

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  2. A novel VLSI processor for high-rate, high resolution spectroscopy

    CERN Document Server

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  3. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    Directory of Open Access Journals (Sweden)

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  4. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    CERN Document Server

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  5. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Science.gov (United States)

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  6. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  7. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  8. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    CERN Document Server

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  9. An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

    DEFF Research Database (Denmark)

    Paaske, Erik; Pedersen, Steen; Sparsø, Jens

    1991-01-01

    area savings compared to the REA and the TBA are achieved. Furthermore, the relative area savings increase for larger decoding depths, which might be desirable for punctured codes.Based on the new algorithm a test chip has been designed and fabricated in a 2 micron CMOS process using MOSIS like...

  10. BM/C3 Force Model VLSI/VHSIC Digital Processing: A Cost Methodology

    Science.gov (United States)

    1988-10-01

    industrial , commercial, aerospace, and military applications. The $907 part is assumed to be for ground and airborne applications, while the $3165 part...number of produccions lots is increased. This is similar to a learning curve effect. Quantity demanded largely explains the reason why memory chips are

  11. Design and Evaluation of Fault-Tolerant VLSI/WSI Processor Arrays.

    Science.gov (United States)

    1987-12-31

    subgraphs which are 4 % isomorphic to the Indirect Binary N-Cube network in the LADM network. This knowledge can be used to characterize properties of...34 40 I. N r -r -6- sufficient conditions to perform rerouting in the LADM network are derived in Section 3 . In Section 4 two routing and rerouting...network that are isomorphic to the lCube - network are identified in Section 6, and it is shown how to reconfigure the LADM network under certain link

  12. Spiking Neural Classifier with Lumped Dendritic Nonlinearity and Binary Synapses: A Current Mode VLSI Implementation and Analysis.

    Science.gov (United States)

    Bhaduri, Aritra; Banerjee, Amitava; Roy, Subhrajit; Kar, Sougata; Basu, Arindam

    2017-12-08

    We present a neuromorphic current mode implementation of a spiking neural classifier with lumped square law dendritic nonlinearity. It has been shown previously in software simulations that such a system with binary synapses can be trained with structural plasticity algorithms to achieve comparable classification accuracy with fewer synaptic resources than conventional algorithms. We show that even in real analog systems with manufacturing imperfections (CV of 23.5% and 14.4% for dendritic branch gains and leaks respectively), this network is able to produce comparable results with fewer synaptic resources. The chip fabricated in [Formula: see text]m complementary metal oxide semiconductor has eight dendrites per cell and uses two opposing cells per class to cancel common-mode inputs. The chip can operate down to a [Formula: see text] V and dissipates 19 nW of static power per neuronal cell and [Formula: see text] 125 pJ/spike. For two-class classification problems of high-dimensional rate encoded binary patterns, the hardware achieves comparable performance as software implementation of the same with only about a 0.5% reduction in accuracy. On two UCI data sets, the IC integrated circuit has classification accuracy comparable to standard machine learners like support vector machines and extreme learning machines while using two to five times binary synapses. We also show that the system can operate on mean rate encoded spike patterns, as well as short bursts of spikes. To the best of our knowledge, this is the first attempt in hardware to perform classification exploiting dendritic properties and binary synapses.

  13. Adaptive Capacity Management in Bluetooth Networks

    DEFF Research Database (Denmark)

    Son, L.T.

    With the Internet and mobile wireless development, accelerated by high-speed and low cost VLSI device evolution, short range wireless communications have become more and more popular, especially Bluetooth. Bluetooth is a new short range radio technology that promises to be very convenient, low...... of Bluetooth devices is increasing, a larger-scale ad hoc network, scatternet, is formed, as well as the booming of Internet has demanded for large bandwidth and low delay mobile access. This dissertation is to address the capacity management issues in Bluetooth networks. The main goals of the network capacity...... resource constraints in Bluetooth networks and adapt to mobility and frequent changes of the network topology, as well as to bursty traffic of Internet data applications, which are supposedly very common in Bluetooth. Some performance characteristics of these approaches are illustrated by analysis as well...

  14. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates.

    Science.gov (United States)

    Devi, T Kalavathi; Palaniappan, Sakthivel

    2015-01-01

    Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  15. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    Directory of Open Access Journals (Sweden)

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  16. CHIP Reporting in the CPS

    Data.gov (United States)

    U.S. Department of Health & Human Services — CHIP reporting in the CPS is unreliable. Only 10 to 30 percent of those with CHIP (but not Medicaid) report this type of coverage in the CPS. Many with CHIP report...

  17. Chip-based quantum key distribution.

    Science.gov (United States)

    Sibson, P; Erven, C; Godfrey, M; Miki, S; Yamashita, T; Fujiwara, M; Sasaki, M; Terai, H; Tanner, M G; Natarajan, C M; Hadfield, R H; O'Brien, J L; Thompson, M G

    2017-02-09

    Improvement in secure transmission of information is an urgent need for governments, corporations and individuals. Quantum key distribution (QKD) promises security based on the laws of physics and has rapidly grown from proof-of-concept to robust demonstrations and deployment of commercial systems. Despite these advances, QKD has not been widely adopted, and large-scale deployment will likely require chip-based devices for improved performance, miniaturization and enhanced functionality. Here we report low error rate, GHz clocked QKD operation of an indium phosphide transmitter chip and a silicon oxynitride receiver chip-monolithically integrated devices using components and manufacturing processes from the telecommunications industry. We use the reconfigurability of these devices to demonstrate three prominent QKD protocols-BB84, Coherent One Way and Differential Phase Shift-with performance comparable to state-of-the-art. These devices, when combined with integrated single photon detectors, pave the way for successfully integrating QKD into future telecommunications networks.

  18. TEST ON ABCD CHIPS

    CERN Document Server

    Ferrère, D; Zsenei, A; Kaplon, J; Lacasta, C; Dabrowski, W; Kudlaty, J; Wolter, M; Azman, S

    1998-01-01

    The ABCD chip is one of the two technological options for the binary readout architecture under development for the Silicon Tracker (SCT) in ATLAS. The chip is realised in the DMILL technology (a 0.8 mum BICMOS trench isolation process). This note reports on the first results obtained at CERN on the p-type ABCD chips of the first batch delivered by TEMIC in February 1998.

  19. Introduction to computer networking

    CERN Document Server

    Robertazzi, Thomas G

    2017-01-01

    This book gives a broad look at both fundamental networking technology and new areas that support it and use it. It is a concise introduction to the most prominent, recent technological topics in computer networking. Topics include network technology such as wired and wireless networks, enabling technologies such as data centers, software defined networking, cloud and grid computing and applications such as networks on chips, space networking and network security. The accessible writing style and non-mathematical treatment makes this a useful book for the student, network and communications engineer, computer scientist and IT professional. • Features a concise, accessible treatment of computer networking, focusing on new technological topics; • Provides non-mathematical introduction to networks in their most common forms today;< • Includes new developments in switching, optical networks, WiFi, Bluetooth, LTE, 5G, and quantum cryptography.

  20. Diverse roles of C-terminal Hsp70-interacting protein (CHIP) in tumorigenesis.

    Science.gov (United States)

    Sun, Chao; Li, Hai-Long; Shi, Mei-Lin; Liu, Qing-Hua; Bai, Jin; Zheng, Jun-Nian

    2014-02-01

    The carboxyl terminus of Hsp70-interacting protein (CHIP) is a member of E3 ubiquitin ligase, functioning as a link between the chaperone (heat shock protein 70/90) and proteasome systems, playing a vital role in maintaining the protein homeostasis in the cytoplasm. CHIP has been demonstrated to be involved in tumorigenesis, proliferation and invasion in several malignancies, regulating a number of oncogenic proteins. However, CHIP has also been implicated in the modulation of tumor suppressor proteins. The pathogenic mechanism of CHIP expression in human malignancy is not yet clear, and a number of studies have suggested that CHIP may have opposing roles in different cancers. Therefore, many studies have focused on the relationship between CHIP and carcinoma. A literature search focusing on regulation network, biological function and clinical significance of CHIP in connection with its role in cancer development was performed on the MEDLINE databases. CHIP may be a potential diagnostic biomarker and therapeutic target for human cancer, and may play different roles in different human cancers. This inconsistence might be induced by the diversity of CHIP downstream targeting proteins. Therefore, the phenotypes determined by CHIP should be dependent on the function of its specific targets in a specific type of cancer cells. Whether CHIP contributes to tumor progression or suppression in various human cancers remains unclear, suggesting the necessity of further extensive investigation of its role in tumorigenesis.

  1. High-density, fail-in-place switches for computer and data networks

    Energy Technology Data Exchange (ETDEWEB)

    Coteus, Paul W.; Doany, Fuad E.; Hall, Shawn A.; Schultz, Mark D.; Takken, Todd E.; Tian, Shurong

    2017-04-25

    A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.

  2. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Directory of Open Access Journals (Sweden)

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  3. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  4. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  5. Application of a computational neural network to optimize the fluorescence signal from a receptor-ligand interaction on a microfluidic chip.

    Science.gov (United States)

    Ortega, Maria; Hanrahan, Grady; Arceo, Marilyn; Gomez, Frank A

    2015-02-01

    We describe the use of a computational neural network platform to optimize the fluorescence upon binding 5-carboxyfluorescein-d-Ala-d-Ala-d-Ala (5-FAM(DA)3 ) (1) to the antibiotic teicoplanin covalently attached to a glass slide. A three-level response surface experimental design was used as the first stage of investigation. Subsequently, three defined experimental parameters were examined by the neural network approach: (i) the concentration of teicoplanin used to derivatize a glass platform on the microfluidic device, (ii) the time required for the immobilization of teicoplanin on the platform, and (iii) the length of time 1 is allowed to equilibrate with teicoplanin in the microfluidic channel. Optimal neural structure provided a best fit model, both for the training set (r(2) = 0.961) and test set (r(2) = 0.934) data. Model simulated results were experimentally validated with excellent agreement (% difference) between experimental and predicted fluorescence shown, thus demonstrating efficiency of the neural network approach. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Emulated Muscle Spindle and Spiking Afferents Validates VLSI Neuromorphic Hardware as a Testbed for Sensorimotor Function and Disease

    Directory of Open Access Journals (Sweden)

    Chuanxin M. Niu

    2014-12-01

    Full Text Available The lack of multi-scale empirical measurements (e.g. recording simultaneously from neurons, muscles, whole body, etc. complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI technology to provide considerable scalability and high-speed, as much as 365x faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006 and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Matthews, 1964; 1972; Crowe and Matthews, 1964b. Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365x real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  7. Emulated muscle spindle and spiking afferents validates VLSI neuromorphic hardware as a testbed for sensorimotor function and disease.

    Science.gov (United States)

    Niu, Chuanxin M; Nandyala, Sirish K; Sanger, Terence D

    2014-01-01

    The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin-Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

  8. Reservoir-on-a-Chip (ROC): A new paradigm in reservoir engineering

    NARCIS (Netherlands)

    Kumar Gunda, N.S.; Bera, B.; Karadimitriou, N.K.; Mitra, S.K.; Hassanizadeh, S.M.

    2011-01-01

    In this study, we design a microfluidic chip, which represents the pore structure of a naturally occurring oil-bearing reservoir rock. The pore-network has been etched in a silicon substrate and bonded with a glass covering layer to make a complete microfluidic chip, which is termed as

  9. Omphale: Streamlining the Communication for Jobs in a Multi Processor System on Chip

    NARCIS (Netherlands)

    Bijlsma, T.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria; Jansen, P.G.

    2007-01-01

    Our Multi Processor System on Chip (MPSoC) template provides processing tiles that are connected via a network on chip. A processing tile contains a processing unit and a Scratch Pad Memory (SPM). This paper presents the Omphale tool that performs the first step in mapping a job, represented by a

  10. Sensor Network Motes:

    DEFF Research Database (Denmark)

    Leopold, Martin

    . In addition, we present our results from porting the highly popular sensor network operating system TinyOS to a new and emerging system on a chip based platform. Moving the sensor network field towards the use of system-on- a-chip devices has large potential in terms of price and performance. We claim to have......This dissertation describes our efforts to improve sensor network performance evaluation and portability, within the context of the sensor network project Hogthrob. In Hogthrob, we faced the challenge of building an sensor network architecture for sow monitoring. This application has hard...... requirements on price and performance, and shows great potential for using sensor networks. Throughout the project we let the application requirements guide our design choices, leading us to push the technologies further to meet the specific goal of the application. In this dissertation, we attack two key...

  11. CHIP, CHIP, ARRAY! THREE CHIPS FOR POST-GENOMIC RESEARCH

    Science.gov (United States)

    Cambridge Healthtech Institute recently held the 4th installment of their popular "Lab-on-a-Chip" series in Zurich, Switzerland. As usual, it was enthusiastically received and over 225 people attended the 2-1/2 day meeting to see and hear about some of the latest developments an...

  12. Neural networks: Application to medical imaging

    Science.gov (United States)

    Clarke, Laurence P.

    1994-01-01

    The research mission is the development of computer assisted diagnostic (CAD) methods for improved diagnosis of medical images including digital x-ray sensors and tomographic imaging modalities. The CAD algorithms include advanced methods for adaptive nonlinear filters for image noise suppression, hybrid wavelet methods for feature segmentation and enhancement, and high convergence neural networks for feature detection and VLSI implementation of neural networks for real time analysis. Other missions include (1) implementation of CAD methods on hospital based picture archiving computer systems (PACS) and information networks for central and remote diagnosis and (2) collaboration with defense and medical industry, NASA, and federal laboratories in the area of dual use technology conversion from defense or aerospace to medicine.

  13. Aceleración de un algoritmo de enfriamiento simulado mediante particionamiento de redes. Aplicación a "placement" de circuitos VLSI

    OpenAIRE

    Aguirre Echanove, Miguel Ángel; Torralba Silgado, Antonio Jesús; García Franquelo, Leopoldo

    1995-01-01

    Se propone un nuevo método de mejora de los resultados del "placement" de un circuito VLSI. El método propuesto utiliza un particionamiento recursivo para obtener una solución de partida para el posterior proceso de enfriamiento simulado. Para preservar los beneficios de esta solución de partida, la temperatura inicial del algoritmo de enfriamiento es seleccionada del espacio intermedio de las temperaturas. Se presentan resultados experimentales sobre diversos circuitos de prueba, demostrando...

  14. Grain-size considerations for optoelectronic multistage interconnection networks.

    Science.gov (United States)

    Krishnamoorthy, A V; Marchand, P J; Kiamilev, F E; Esener, S C

    1992-09-10

    This paper investigates, at the system level, the performance-cost trade-off between optical and electronic interconnects in an optoelectronic interconnection network. The specific system considered is a packet-switched, free-space optoelectronic shuffle-exchange multistage interconnection network (MIN). System bandwidth is used as the performance measure, while system area, system power, and system volume constitute the cost measures. A detailed design and analysis of a two-dimensional (2-D) optoelectronic shuffle-exchange routing network with variable grain size K is presented. The architecture permits the conventional 2 x 2 switches or grains to be generalized to larger K x K grain sizes by replacing optical interconnects with electronic wires without affecting the functionality of the system. Thus the system consists of log(k) N optoelectronic stages interconnected with free-space K-shuffles. When K = N, the MIN consists of a single electronic stage with optical input-output. The system design use an effi ient 2-D VLSI layout and a single diffractive optical element between stages to provide the 2-D K-shuffle interconnection. Results indicate that there is an optimum range of grain sizes that provides the best performance per cost. For the specific VLSI/GaAs multiple quantum well technology and system architecture considered, grain sizes larger than 256 x 256 result in a reduced performance, while grain sizes smaller than 16 x 16 have a high cost. For a network with 4096 channels, the useful range of grain sizes corresponds to approximately 250-400 electronic transistors per optical input-output channel. The effect of varying certain technology parameters such as the number of hologram phase levels, the modulator driving voltage, the minimum detectable power, and VLSI minimum feature size on the optimum grain-size system is studied. For instance, results show that using four phase levels for the interconnection hologram is a good compromise for the cost

  15. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip...... communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  16. A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

    DEFF Research Database (Denmark)

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1989-01-01

    or different values of K. The Shuffle-Exchange type interconnection network is implemented by organizing the 64 processing elements to form a ring. The ring is laid out in two columns, and the interconnections between non-neighbours are routed in the channel between the columns. The interconnection network...

  17. On-chip cellomics: Single-cell-based constructive cell-network assay for quasi-in vivo screening of cardiotoxicity.

    Science.gov (United States)

    Yasuda, Kenji

    2013-01-01

    We have developed methods and systems of analyzing epigenetic information in cells, as well as that of genetic information, to expand our understanding of how living systems are determined. A system of analyzing epigenetic information was developed starting from the twin complementary viewpoints of cell regulation as an 'algebraic' system (emphasis on temporal aspects) and as a 'geometric' system (emphasis on spatial aspects). As an example of the 'geometric' system, we have developed an quasi-in vivo hiPS cardiomyocyte network assay and confirmed that it can predict the risk of lethal arrythmia correctly in 22 compounds. The knowlege acquired from this study may lead to the use of cells that fully control practical applications like cell-based drug screening and the regeneration of organs.

  18. A hardware-oriented histogram of oriented gradients algorithm and its VLSI implementation

    Science.gov (United States)

    Zhang, Xiangyu; An, Fengwei; Nakashima, Ikki; Luo, Aiwen; Chen, Lei; Ishii, Idaku; Jürgen Mattausch, Hans

    2017-04-01

    A challenging and important issue for object recognition is feature extraction on embedded systems. We report a hardware implementation of the histogram of oriented gradients (HOG) algorithm for real-time object recognition, which is known to provide high efficiency and accuracy. The developed hardware-oriented algorithm exploits the cell-based scan strategy which enables image-sensor synchronization and extraction-speed acceleration. Furthermore, buffers for image frames or integral images are avoided. An image-size scalable hardware architecture with an effective bin-decoder and a parallelized voting element (PVE) is developed and used to verify the hardware-oriented HOG implementation with the application of human detection. The fabricated test chip in 180 nm CMOS technology achieves fast processing speed and large flexibility for different image resolutions with substantially reduced hardware cost and energy consumption.

  19. Chips of Hope: Neuro-Electronic Hybrids for Brain Repair

    Science.gov (United States)

    Ben-Jacob, Eshel

    2010-03-01

    The field of Neuro-Electronic Hybrids kicked off 30 years ago when researchers in the US first tweaked the technology of recording and stimulation of networks of live neurons grown in a Petri dish and interfaced with a computer via an array of electrodes. Since then, many researchers have searched for ways to imprint in neural networks new ``memories" without erasing old ones. I will describe our new generation of Neuro-Electronic Hybrids and how we succeeded to turn them into the first learning Neurochips - memory and information processing chips made of live neurons. To imprint multiple memories in our new chip we used chemical stimulation at specific locations that were selected by analyzing the networks activity in real time according to our new information encoding principle. Currently we develop new-generation of neuro chips using special carbon nano tubes (CNT). These electrodes enable to engineer the networks topology and efficient electrical interfacing with the neurons. This advance bears the promise to pave the way for building a new experimental platform for testing new drugs and developing new methods for neural networks repair and regeneration. Looking into the future, the development brings us a step closer towards the dream of Brain Repair by implementable Neuro-Electronic hybrid chips.

  20. Three levels of neuroelectronic interfacing: silicon chips with ion channels, nerve cells, and brain tissue.

    Science.gov (United States)

    Fromherz, Peter

    2006-12-01

    We consider the direct electrical interfacing of semiconductor chips with individual nerve cells and brain tissue. At first, the structure of the cell-chip contact is studied. Then we characterize the electrical coupling of ion channels--the electrical elements of nerve cells--with transistors and capacitors in silicon chips. On that basis it is possible to implement signal transmission between microelectronics and the microionics of nerve cells in both directions. Simple hybrid neuroelectronic systems are assembled with neuron pairs and with small neuronal networks. Finally, the interfacing with capacitors and transistors is extended to brain tissue cultured on silicon chips. The application of highly integrated silicon chips allows an imaging of neuronal activity with high spatiotemporal resolution. The goal of the work is an integration of neuronal network dynamics with digital electronics on a microscopic level with respect to experiments in brain research, medical prosthetics, and information technology.

  1. Chip to System Testability

    National Research Council Canada - National Science Library

    McNamer, Michael

    1997-01-01

    The ultimate objective of the Chip-to-System Testability program was the development of a structured testability implementation methodology which will be used as a basis for a PC-based tool called TESPAD...

  2. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states and...

  3. Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning.

    Science.gov (United States)

    Srinivasan, Gopalakrishnan; Sengupta, Abhronil; Roy, Kaushik

    2016-07-13

    Spiking Neural Networks (SNNs) have emerged as a powerful neuromorphic computing paradigm to carry out classification and recognition tasks. Nevertheless, the general purpose computing platforms and the custom hardware architectures implemented using standard CMOS technology, have been unable to rival the power efficiency of the human brain. Hence, there is a need for novel nanoelectronic devices that can efficiently model the neurons and synapses constituting an SNN. In this work, we propose a heterostructure composed of a Magnetic Tunnel Junction (MTJ) and a heavy metal as a stochastic binary synapse. Synaptic plasticity is achieved by the stochastic switching of the MTJ conductance states, based on the temporal correlation between the spiking activities of the interconnecting neurons. Additionally, we present a significance driven long-term short-term stochastic synapse comprising two unique binary synaptic elements, in order to improve the synaptic learning efficiency. We demonstrate the efficacy of the proposed synaptic configurations and the stochastic learning algorithm on an SNN trained to classify handwritten digits from the MNIST dataset, using a device to system-level simulation framework. The power efficiency of the proposed neuromorphic system stems from the ultra-low programming energy of the spintronic synapses.

  4. Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning

    Science.gov (United States)

    Srinivasan, Gopalakrishnan; Sengupta, Abhronil; Roy, Kaushik

    2016-07-01

    Spiking Neural Networks (SNNs) have emerged as a powerful neuromorphic computing paradigm to carry out classification and recognition tasks. Nevertheless, the general purpose computing platforms and the custom hardware architectures implemented using standard CMOS technology, have been unable to rival the power efficiency of the human brain. Hence, there is a need for novel nanoelectronic devices that can efficiently model the neurons and synapses constituting an SNN. In this work, we propose a heterostructure composed of a Magnetic Tunnel Junction (MTJ) and a heavy metal as a stochastic binary synapse. Synaptic plasticity is achieved by the stochastic switching of the MTJ conductance states, based on the temporal correlation between the spiking activities of the interconnecting neurons. Additionally, we present a significance driven long-term short-term stochastic synapse comprising two unique binary synaptic elements, in order to improve the synaptic learning efficiency. We demonstrate the efficacy of the proposed synaptic configurations and the stochastic learning algorithm on an SNN trained to classify handwritten digits from the MNIST dataset, using a device to system-level simulation framework. The power efficiency of the proposed neuromorphic system stems from the ultra-low programming energy of the spintronic synapses.

  5. A system-level multiprocessor system-on-chip modeling framework

    DEFF Research Database (Denmark)

    Virk, Kashif Munir; Madsen, Jan

    2004-01-01

    We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip...... and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient...

  6. An Electrochromatography Chip with Integrated Waveguides for UV Absorbance Detection

    DEFF Research Database (Denmark)

    Gustafsson, Omar; Mogensen, Klaus Bo; Ohlsson, Pelle Daniel

    2008-01-01

    A silicon-based microchip for electrochromatographic separations is presented. Apart from a microfluidic network, the microchip has integrated UV-transparent waveguides for detection and integrated couplers for optical fibers on the chip, yielding the most complete chromatography microchip to date...... in terms of the integration of optical components. The microfluidic network and the optical components are fabricated in a single etching step in silicon and subsequently thermally oxidized. The separation column consists of a regular array of microfabricated solid support structures with a monolayer...... of an octylsilane covalently bonded to the surfaces to provide chromatographic interaction. The chip features a 1 mm long U-shaped detection cell and planar silicon dioxide waveguides that couple light to and from the detection cell. Microfabricated on-chip fiber couplers assure perfect alignment of optical fibers...

  7. Chip-based quantum key distribution

    Science.gov (United States)

    Sibson, P.; Erven, C.; Godfrey, M.; Miki, S.; Yamashita, T.; Fujiwara, M.; Sasaki, M.; Terai, H.; Tanner, M. G.; Natarajan, C. M.; Hadfield, R. H.; O'Brien, J. L.; Thompson, M. G.

    2017-01-01

    Improvement in secure transmission of information is an urgent need for governments, corporations and individuals. Quantum key distribution (QKD) promises security based on the laws of physics and has rapidly grown from proof-of-concept to robust demonstrations and deployment of commercial systems. Despite these advances, QKD has not been widely adopted, and large-scale deployment will likely require chip-based devices for improved performance, miniaturization and enhanced functionality. Here we report low error rate, GHz clocked QKD operation of an indium phosphide transmitter chip and a silicon oxynitride receiver chip—monolithically integrated devices using components and manufacturing processes from the telecommunications industry. We use the reconfigurability of these devices to demonstrate three prominent QKD protocols—BB84, Coherent One Way and Differential Phase Shift—with performance comparable to state-of-the-art. These devices, when combined with integrated single photon detectors, pave the way for successfully integrating QKD into future telecommunications networks. PMID:28181489

  8. Multi-layer microfluidic glass chips for microanalytical applications

    NARCIS (Netherlands)

    Daridon, Antoine; Fascio, Valia; Lichtenberg, Jan; Wütrich, Rolf; Langen, Hans; Verpoorte, Elisabeth; De Rooij, Nico F.

    2001-01-01

    A new, versatile architecture is presented for microfluidic devices made entirely from glass, for use with reagents which would prove highly corrosive for silicon. Chips consist of three layers of glass wafers bonded together by fusion bonding. On the inside wafer faces a network of microfluidic

  9. Disposable polydimethylsiloxane/silicon hybrid chips for protein detection.

    Science.gov (United States)

    Li, Shifeng; Floriano, Pierre N; Christodoulides, Nicolaos; Fozdar, David Y; Shao, Dongbing; Ali, Mehnaaz F; Dharshan, Priya; Mohanty, Sanghamitra; Neikirk, Dean; McDevitt, John T; Chen, Shaochen

    2005-10-15

    This paper presents disposable protein analysis chips with single- or four-chamber-constructed from poly(dimethylsiloxane) (PDMS) and silicon. The chips are composed of a multilayer stack of PDMS layers that sandwich a silicon microchip. This inner silicon chip features an etched array of micro-cavities hosting polymeric beads. The sample is introduced into the fluid network through the top PDMS layer, where it is directed to the bead chamber. After reaction of the analyte with the probe beads, the signal generated on the beads is captured with a CCD camera, digitally processed, and analyzed. An established bead-based fluorescent assay for C-reactive protein (CRP) was used here to characterize these hybrid chips. The detection limit of the single-chamber protein chip was found to be 1 ng/ml. Additionally, using a back pressure compensation method, the signals from each chamber of the four-chamber chip were found to fall within 10% of each other.

  10. Organ-on-a-chip for assessing environmental toxicants.

    Science.gov (United States)

    Cho, Soohee; Yoon, Jeong-Yeol

    2017-06-01

    Man-made xenobiotics, whose potential toxicological effects are not fully understood, are oversaturating the already-contaminated environment. Due to the rate of toxicant accumulation, unmanaged disposal, and unknown adverse effects to the environment and the human population, there is a crucial need to screen for environmental toxicants. Animal models and in vitro models are ineffective models in predicting in vivo responses due to inter-species difference and/or lack of physiologically-relevant 3D tissue environment. Such conventional screening assays possess limitations that prevent dynamic understanding of toxicants and their metabolites produced in the human body. Organ-on-a-chip systems can recapitulate in vivo like environment and subsequently in vivo like responses generating a realistic mock-up of human organs of interest, which can potentially provide human physiology-relevant models for studying environmental toxicology. Feasibility, tunability, and low-maintenance features of organ-on-chips can also make possible to construct an interconnected network of multiple-organs-on-chip toward a realistic human-on-a-chip system. Such interconnected organ-on-a-chip network can be efficiently utilized for toxicological studies by enabling the study of metabolism, collective response, and fate of toxicants through its journey in the human body. Further advancements can address the challenges of this technology, which potentiates high predictive power for environmental toxicology studies. Copyright © 2017 Elsevier Ltd. All rights reserved.

  11. Single-chip microprocessor that communicates directly using light.

    Science.gov (United States)

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  12. Single-chip microprocessor that communicates directly using light

    Science.gov (United States)

    Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

    2015-12-01

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  13. Nondestructive diagnosis of flip chips based on vibration analysis using PCA-RBF

    Science.gov (United States)

    Su, Lei; Shi, Tielin; Liu, Zhiping; Zhou, Hongdi; Du, Li; Liao, Guanglan

    2017-02-01

    Flip chip technology combined with solder bump interconnection has been widely applied in IC package. The solder bumps are sandwiched between dies and substrates, leading to conventional techniques being difficult to diagnose the flip chips. Meanwhile, these conventional diagnosis methods are usually performed by human visual judgment. The human eye-fatigue can easily cause fault detection. Thus, it is difficult and crucial to detect the defects of flip chips automatically. In this paper, a nondestructive diagnosis system based on vibration analysis is proposed. The flip chip is excited by air-coupled ultrasounds and raw vibration signals are measured by a laser scanning vibrometer. Forty-two features are extracted for analysis, including ten time domain features, sixteen frequency domain features and sixteen wavelet packet energy features. Principal component analysis is used for feature reduction. Radial basis function neural network is adopted for classification and recognition. Flip chips in three states (good flip chips, flip chips with missing solder bumps and flip chips with open solder bumps) are utilized to validate the proposed method. The results demonstrate that this method is effective for defect inspection in flip chip package.

  14. Nanoslits in silicon chips.

    Science.gov (United States)

    Aref, Thomas; Brenner, Matthew; Bezryadin, Alexey

    2009-01-28

    Potassium hydroxide (KOH) etching of a patterned [100] oriented silicon wafer produces V-shaped etch pits. We demonstrate that the remaining thickness of silicon at the tip of the etch pit can be reduced to approximately 5 microm using an appropriately sized etch mask and optical feedback. Starting from such an etched chip, we have developed two different routes for fabricating 100 nm scale slits that penetrate through the macroscopic silicon chip (the slits are approximately 850 microm wide at one face of the chip and gradually narrow to approximately 100-200 nm wide at the opposite face of the chip). In the first process, the etched chips are sonicated to break the thin silicon at the tip of the etch pit and then further KOH etched to form a narrow slit. In the second process, focused ion beam milling is used to etch through the thin silicon at the tip of the etch pit. The first method has the advantage that it uses only low-resolution technology while the second method offers more control over the length and width of the slit. Our slits can be used for preparing mechanically stable, transmission electron microscopy samples compatible with electrical transport measurements or as nanostencils for depositing nanowires seamlessly connected to their contact pads.

  15. On-chip positionable photonic waveguides for chip-to-chip optical interconnects

    NARCIS (Netherlands)

    Peters, T.J.; Tichem, M.; Vivien, Laurent; Pavesi, Lorenzo; Pelli, Stefano

    2016-01-01

    This paper reports on the progress related to a multichannel photonic alignment concept, aiming for sub-micrometer precision in the alignment of the waveguides of two photonic integrated circuits (PICs). The concept consists of two steps: chip-to-chip positioning and chip bonding provide a coarse

  16. Synchronization of Integrated Systems on a Chip

    Directory of Open Access Journals (Sweden)

    González-Díaz O.

    2012-04-01

    Full Text Available In the present paper, the non-conventional interconnected and coupled ring oscillators approach working as clock distribution networks to synchronize electronic systems on a chip (SoC is proposed. Typical CMOS (Complementary Metal-Oxide Semiconductor N-well 0.35 µm Austria Micro Systems process parameters were used for conventional and non-conventional clock distribution nets design and simulation. Experimental results from local and global clock distribution networks fabricated using a CMOS 0.35 µm process show that the use of interconnected rings arrays, as globally asynchronous locally synchronous (GALS clock distribution networks, represent an appropriate approach due to good performance regarding scalability, low clock-skew, high-speed, faults tolerant and robust under process variations, regularity, and modularity.

  17. Compression Debarking of Stored Wood Chips

    Science.gov (United States)

    James A. Mattson

    1974-01-01

    Two 750 ft. piles of unbarked chips were stored for 1 year to evaluate the effect of chip storage on the effectiveness of bark-chip separations-segregation methods under study. in processing stored chips suffered more wood loss than fresh chips.

  18. Application specific Tester-On-a-Resident-Chip (TORCH{trademark}) - innovation in the area of semiconductor testing

    Energy Technology Data Exchange (ETDEWEB)

    Bowles, M. [L& M Technologies, Albuquerque, NM (United States); Peterson, T. [New Mexico Highlands Univ., Las Vegas, NM (United States); Savignon, D.; Campbell, D. [Sandia National Labs., Albuquerque, NM (United States)

    1997-12-01

    Manufacturers widely recognize testing as a major factor in the cost, producability, and delivery of product in the $100 billion integrated circuit business: {open_quotes}The rapid development of VLSI using sub-micron CMOS technology has suddenly exposed traditional test techniques as a major cost factor that could restrict the development of VLSI devices exceeding 512 pins an operating frequencies above 200 MHz.{close_quotes} -- 1994 Semiconductor Industry Association Roadmap, Design and Test, Summary, pg. 43. This problem increases dramatically for stockpile electronics, where small production quantities make it difficult to amortize the cost of increasingly expensive testers. Application of multiple ICs in Multi-Chip Modules (MCM) greatly multiplies testing problems for commercial and defense users alike. By traditional test methods, each new design requires custom test hardware and software and often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems often dedicated testing equipment costing millions of dollars. Also, physical properties of traditional test systems limit capabilities in testing at-speed (>200 MHz), high-impedance, and high-accuracy analog signals. This project proposed a revolutionary approach to these problems: replace the multi-million dollar external test system with an inexpensive test system integrated onto the product wafer. Such a methodology enables testing functions otherwise unachievable by conventional means, particularly in the areas of high-frequency, at-speed testing, high impedance analog circuits, and known good die assessment. The techniques apply specifically to low volume applications, typical of Defense Programs, where testing costs represent an unusually high proportional of product costs, not easily amortized.

  19. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  20. Highly integrated lab-on-a-chip for fluorescence detection

    Science.gov (United States)

    Guduru, Surya S. K.; Scotognella, Francesco; Chiasera, Alessandro; Sreeramulu, Valligatla; Criante, Luigino; Vishnubhatla, Krishna Chaitanya; Ferrari, Maurizio; Ramponi, Roberta; Lanzani, Guglielmo; Vázquez, Rebeca Martínez

    2016-09-01

    We report the fabrication and validation of a microfluidic chip for fluorescence detection, which incorporates in the same glass substrate the microfluidic network, the excitation, the filtering, and the collection elements. The device is fabricated in a hybrid approach combining different technologies, such as femtosecond laser micromachining and RF sputtering, to increase their individual capabilities. The validation of the chip demonstrates a good wavelength selective light filtering and a limit of detection of a 600-nM concentration of Oxazine 720 perchlorate dye.

  1. Time-division multiplexing vs network calculus: A comparison

    DEFF Research Database (Denmark)

    Puffitsch, Wolfgang; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    Networks-on-chip are increasingly common in modern multicore architectures. However, general-purpose networks-on-chip are not always well suited for real-time applications that require bandwidth and latency guarantees. Two approaches to provide real-time guarantees have emerged: time...... that time-division multiplexing leads to better worst-case latencies, while network calculus supports higher bandwidths. Furthermore, time-division multiplexing leads to a simpler hardware implementation, while dynamically scheduled networks-on-chip allow the integration of best-effort traffic in the on-chip......-division multiplexing, where traffic is scheduled according to a precalculated static schedule, and network calculus, a mathematical framework to reason about dynamically scheduled networks. This paper compares the two approaches to provide insight into their relative advantages and disadvantages. The results show...

  2. Experiment list: SRX122496 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

  3. Cytometer on a Chip

    Science.gov (United States)

    Fernandez, Salvador M.

    2011-01-01

    A cytometer now under development exploits spatial sorting of sampled cells on a microarray chip followed by use of grating-coupled surface-plasmon-resonance imaging (GCSPRI) to detect the sorted cells. This cytometer on a chip is a prototype of contemplated future miniature cytometers that would be suitable for rapidly identifying pathogens and other cells of interest in both field and laboratory applications and that would be attractive as alternatives to conventional flow cytometers. The basic principle of operation of a conventional flow cytometer requires fluorescent labeling of sampled cells, stringent optical alignment of a laser beam with a narrow orifice, and flow of the cells through the orifice, which is subject to clogging. In contrast, the principle of operation of the present cytometer on a chip does not require fluorescent labeling of cells, stringent optical alignment, or flow through a narrow orifice. The basic principle of operation of the cytometer on a chip also reduces the complexity, mass, and power of the associated laser and detection systems, relative to those needed in conventional flow cytometry. Instead of making cells flow in single file through a narrow flow orifice for sequential interrogation as in conventional flow cytometry, a liquid containing suspended sampled cells is made to flow over the front surface of a microarray chip on which there are many capture spots. Each capture spot is coated with a thin (approximately 50-nm) layer of gold that is, in turn, coated with antibodies that bind to cell-surface molecules characteristic of one the cell species of interest. The multiplicity of capture spots makes it possible to perform rapid, massively parallel analysis of a large cell population. The binding of cells to each capture spot gives rise to a minute change in the index of refraction at the surface of the chip. This change in the index of refraction is what is sensed in GCSPRI, as described briefly below. The identities of the

  4. Radiometer on a Chip

    Science.gov (United States)

    Chattopadhyay, Goutam; Gill, John J.; Mehdi, Imran; Lee, Choonsup; Schlecht, Erich T.; Skalare, Anders; Ward, John S.; Siegel, Peter H.; Thomas, Bertrand C.

    2009-01-01

    The radiometer on a chip (ROC) integrates whole wafers together to p rovide a robust, extremely powerful way of making submillimeter rece ivers that provide vertically integrated functionality. By integratin g at the wafer level, customizing the interconnects, and planarizing the transmission media, it is possible to create a lightweight asse mbly performing the function of several pieces in a more conventiona l radiometer.

  5. Mikrofluidik-Chips

    NARCIS (Netherlands)

    Verpoorte, E.; Lichtenberg, J.

    2000-01-01

    Microfluidic chips are becoming the new paradigm for chemical processing and analysis in the laboratory. Hair-fine channels made in planar substrates using silicon processing technologies replace beakers and tubing for automated liquid transport and handling on a sub-μ L scale. Reduced conduit

  6. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  7. [Wood chip alveolitis].

    Science.gov (United States)

    Müller-Wening, D; Renck, T; Neuhauss, M

    1999-07-01

    A 52 year old farmer was referred to us for investigation of suspected farmer's lung. For many years the farmer had been exposed to hay, straw, pigeons, and fuel chip dust. Under exertion he suffered from shortness of breath. In the farmer's own fuel chips we could identify Aspergillus fumigatus, Paecilomyces species and Mucor species. In the farmer's blood we found IgG-antibodies against his own fuel chips, thermophilic actinomycetes, Penicillium species, Mucor species and Aspergillus fumigatus. We did not detect any IgG-antibodies against pigeon serum or pigeon faeces. In order to determine the responsible allergen we performed two challenge tests. In the first test the farmer had to inhale his own hay and straw dust for one hour. This provocation was negative. A second one-hour inhalative challenge was carried out 16 days later using his own fuel chips. This time he experienced significant pulmonary and systemic reactions: body temperature rose by 3.3 degrees C, leucocytes by 12,200/mm3; PO2 fell by 39.4 mmHg, vital capacity by 52%, DLCO by 36%. After the challenge the farmer complained of coughing and dyspnoea. Rales could be heard on auscultation, and an interstitial infiltrate was seen to develop on chest x-rays. After the challenge the patient had to be treated with oxygen and systemic corticosteroids. We diagnosed a fuel chip-induced exogenous allergic alveolitis (EAA). Eight days later the parameters were back to normal and the farmer was discharged from our hospital with further corticosteroid medication. This method of inhalative provocation is very important in diagnosing an EAA. Problems arise when the mode and duration of exposure to substances has to be chosen. Because of the risk of severe reactions, inhalative provocations relating to EAAs should only be performed in special centres with an intensive care unit. In this paper we present a diagnosis of fuel chip lung, which is rarely seen in Germany. However, with the rising use of fuel chips as

  8. On-Chip Power-Combining for High-Power Schottky Diode Based Frequency Multipliers

    Science.gov (United States)

    Siles Perez, Jose Vicente (Inventor); Chattopadhyay, Goutam (Inventor); Lee, Choonsup (Inventor); Schlecht, Erich T. (Inventor); Jung-Kubiak, Cecile D. (Inventor); Mehdi, Imran (Inventor)

    2015-01-01

    A novel MMIC on-chip power-combined frequency multiplier device and a method of fabricating the same, comprising two or more multiplying structures integrated on a single chip, wherein each of the integrated multiplying structures are electrically identical and each of the multiplying structures include one input antenna (E-probe) for receiving an input signal in the millimeter-wave, submillimeter-wave or terahertz frequency range inputted on the chip, a stripline based input matching network electrically connecting the input antennas to two or more Schottky diodes in a balanced configuration, two or more Schottky diodes that are used as nonlinear semiconductor devices to generate harmonics out of the input signal and produce the multiplied output signal, stripline based output matching networks for transmitting the output signal from the Schottky diodes to an output antenna, and an output antenna (E-probe) for transmitting the output signal off the chip into the output waveguide transmission line.

  9. FY1995 trial production of brain functional chip; 1995 nendo no kino shuseki chip no shisaku

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The present computer system will run on a program which is prepared in advance. On the other hand, the human brain can acquire some processes from learning with experiments. It would be very useful us human nature, if these learning process should be build up artificially. Our aim is to reveal basic self-acquiring mechanism of information and its processes of the brain, and preliminary research, including theoretical problems, for building up specialized processor chip. Many research on the brain have been held at the views of scientifically and medically. However; we focused on the principle brain learning process itself. The results of the research was directly realized on a specialized processor chip tuned for high-speed simulation of neural network. We could pointed out some problems on the present brain type processor, and discussed about basic technique for implementation of the next age brain type processor and theories. (NEDO)

  10. On-chip biomedical imaging.

    Science.gov (United States)

    Göröcs, Zoltán; Ozcan, Aydogan

    2013-01-01

    Lab-on-a-chip systems have been rapidly emerging to pave the way toward ultra-compact, efficient, mass producible and cost-effective biomedical research and diagnostic tools. Although such microfluidic and microelectromechanical systems have achieved high levels of integration, and are capable of performing various important tasks on the same chip, such as cell culturing, sorting and staining, they still rely on conventional microscopes for their imaging needs. Recently, several alternative on-chip optical imaging techniques have been introduced, which have the potential to substitute conventional microscopes for various lab-on-a-chip applications. Here we present a critical review of these recently emerging on-chip biomedical imaging modalities, including contact shadow imaging, lens-free holographic microscopy, fluorescent on-chip microscopy and lens-free optical tomography.

  11. A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

    Science.gov (United States)

    Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

    2013-01-01

    This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

  12. A 260-340 GHz Dual Chip Frequency Tripler for THz Frequency Multiplier Chains

    Science.gov (United States)

    Maestrini, Alain; Tripon-Canseliet, Charlotte; Ward, John S.; Gill, John J.; Mehdi, Imran

    2006-01-01

    We designed and fabricated a fix-tuned balanced frequency tripler working in the 260-340 GHz band to be the first stage of a x3x3x3 multiplier chain to 2.7 THz. The design of a dual-chip version of this multiplier featuring an input splitter / output combiner as part of the input / output matching networks of both chips - with no degradation of the expected bandwidth and efficiency- will be presented.

  13. Implementation and Performance of GaAs Digital Signal Processing ASICs

    Science.gov (United States)

    Whitaker, William D.; Buchanan, Jeffrey R.; Burke, Gary R.; Chow, Terrance W.; Graham, J. Scott; Kowalski, James E.; Lam, Barbara; Siavoshi, Fardad; Thompson, Matthew S.; Johnson, Robert A.

    1993-01-01

    The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

  14. Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

    Science.gov (United States)

    Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

    2015-06-10

    When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

  15. Readout Architecture for Hybrid Pixel Readout Chips

    CERN Document Server

    AUTHOR|(SzGeCERN)694170; Westerlund, Tomi; Wyllie, Ken

    The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time...

  16. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a ...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  17. Nanoparticle Reactions on Chip

    Science.gov (United States)

    Köhler, J. M.; Kirner, Th.; Wagner, J.; Csáki, A.; Möller, R.; Fritzsche, W.

    The handling of heterogenous systems in micro reactors is difficult due to their adhesion and transport behaviour. Therefore, the formation of precipitates and gas bubbles has to be avoided in micro reaction technology, in most cases. But, micro channels and other micro reactors offer interesting possibilities for the control of reaction conditions and transport by diffusion and convection due to the laminar flow caused by small Reynolds numbers. This can be used for the preparation and modification of objects, which are much smaller than the cross section of microchannels. The formation of colloidal solutions and the change of surface states of nano particles are two important tasks for the application of chip reactors in nanoparticle technology. Some concepts for the preparation and reaction of nanoparticles in modular chip reactor arrangements will be discussed.

  18. Amdahl 470 Chip Package

    CERN Multimedia

    1975-01-01

    In the late 70s the larger IBM computers were water cooled. Amdahl, an IBM competitor, invented an air cooling technology for it's computers. His company worked hard, developing a computer that was faster and less expensive than the IBM System/360 mainframe computer systems. This object contains an actual Amdahl series 470 computer logic chip with an air cooling device mounted on top. The package leads and cooling tower are gold-plated.

  19. Focal-plane sensor-processor chips

    CERN Document Server

    Zarándy, Ákos

    2011-01-01

    Focal-Plane Sensor-Processor Chips explores both the implementation and application of state-of-the-art vision chips. Presenting an overview of focal plane chip technology, the text discusses smart imagers and cellular wave computers, along with numerous examples of current vision chips.

  20. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  1. On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

    NARCIS (Netherlands)

    Zhang, X.; Kerkhoff, Hans G.; Vermeulen, Bart

    2010-01-01

    Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated into the SoC to function as an ATE. This paper introduces the reuse of a Network-on-Chip as a test access mechanism. Since

  2. Embedded Network Protocols for Mobile Devices

    Science.gov (United States)

    Galataki, Despo; Radulescu, Andrei; Verstoep, Kees; Fokkink, Wan

    Embedded networks for chip-to-chip networks are emerging as communication infrastructure in mobile devices. We present three novel embedded network protocols: a sliding window protocol, a protocol for opening and closing connections, and a bandwidth reservation protocol. The design of these protocols is tailored to the low power and low cost requirements of mobile devices. The model checker SPIN played an important role in the design and analysis of these protocols. Large instances of the protocols could be analyzed successfully using the distributed model checker DiVinE.

  3. Reservoir-on-a-chip (ROC): a new paradigm in reservoir engineering.

    Science.gov (United States)

    Gunda, Naga Siva Kumar; Bera, Bijoyendra; Karadimitriou, Nikolaos K; Mitra, Sushanta K; Hassanizadeh, S Majid

    2011-11-21

    In this study, we design a microfluidic chip, which represents the pore structure of a naturally occurring oil-bearing reservoir rock. The pore-network has been etched in a silicon substrate and bonded with a glass covering layer to make a complete microfluidic chip, which is termed as 'Reservoir-on-a-chip' (ROC). Here we report, for the first time, the ability to perform traditional waterflooding experiments in a ROC. Oil is kept as the resident phase in the ROC, and waterflooding is performed to displace the oil phase from the network. The flow visualization provides specific information about the presence of the trapped oil phase and the movement of the oil/water interface/meniscus in the network. The recovery curve is extracted based on the measured volume of oil at the outlet of the ROC. We also provide the first indication that this oil-recovery trend realized at chip-level can be correlated to the flooding experiments related to actual reservoir cores. Hence, we have successfully demonstrated that the conceptualized 'Reservoir-on-a-Chip' has the features of a realistic pore-network and in principle is able to perform the necessary flooding experiments that are routinely done in reservoir engineering.

  4. Cellular Neural Network-Based Methods for Distributed Network Intrusion Detection

    Directory of Open Access Journals (Sweden)

    Kang Xie

    2015-01-01

    Full Text Available According to the problems of current distributed architecture intrusion detection systems (DIDS, a new online distributed intrusion detection model based on cellular neural network (CNN was proposed, in which discrete-time CNN (DTCNN was used as weak classifier in each local node and state-controlled CNN (SCCNN was used as global detection method, respectively. We further proposed a new method for design template parameters of SCCNN via solving Linear Matrix Inequality. Experimental results based on KDD CUP 99 dataset show its feasibility and effectiveness. Emerging evidence has indicated that this new approach is affordable to parallelism and analog very large scale integration (VLSI implementation which allows the distributed intrusion detection to be performed better.

  5. THE CHIPS SHAPES AT THE BEECH WOODTURNING

    Directory of Open Access Journals (Sweden)

    Iulian POPESCU

    2015-05-01

    Full Text Available we did research on the process of beech woodturning with low cutting speed. We studied the different chip shapes resulted for different feeds. Based on chip shapes, the phenomena that occur in the cutting area were interpreted by the theory of woodturning. It was found that broken chips occur and the variable hardness of some areas on the workingpiece determined forming of smaller flowing chips. We give the resulting images of the chips which are then analysed and commented.

  6. Andy Jenkins Builds Applications Development For Lab-on-a-Chip

    Science.gov (United States)

    2004-01-01

    Andy Jenkins, an engineer for the Lab on a Chip Applications Development program, helped build the Applications Development Unit (ADU-25), a one-of-a-kind facility for controlling and analyzing processes on chips with extreme accuracy. Pressure is used to cause fluids to travel through network of fluid pathways, or micro-channels, embossed on the chips through a process similar to the one used to print circuits on computer chips. To make customized chips for various applications, NASA has an agreement with the U.S. Army's Micro devices and Micro fabrication Laboratory at Redstone Arsenal in Huntsville, Alabama, where NASA's Marshall Space Flight Center (MSFC) is located. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for many applications, such as studying how fluidic systems work in spacecraft and identifying microbes in self-contained life support systems. Chips could even be designed for use on Earth, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

  7. Direct reading of charge multipliers with a self-triggering CMOS analog chip with 105k pixels at 50 micron pitch

    CERN Document Server

    Bellazzini, R; Minuti, M; Baldini, L; Brez, A; Cavalca, F; Latronico, L; Omodei, N; Massai, M M; Sgro, C; Costa, E; Krummenacher, P S F; De Oliveira, R

    2006-01-01

    We report on a large active area (15x15mm2), high channel density (470 pixels/mm2), self-triggering CMOS analog chip that we have developed as pixelized charge collecting electrode of a Micropattern Gas Detector. This device, which represents a big step forward both in terms of size and performance, is the last version of three generations of custom ASICs of increasing complexity. The CMOS pixel array has the top metal layer patterned in a matrix of 105600 hexagonal pixels at 50 micron pitch. Each pixel is directly connected to the underneath full electronics chain which has been realized in the remaining five metal and two poly-silicon layers of a 0.18 micron VLSI technology. The chip has customizable self-triggering capability and includes a signal pre-processing function for the automatic localization of the event coordinates. In this way it is possible to reduce significantly the readout time and the data volume by limiting the signal output only to those pixels belonging to the region of interest. The ve...

  8. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    CERN Document Server

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  9. Application of a Silicon Compiler to VLSI (Very Large Scale Integrated Circuits) Design of Digital Pipelined Multipliers.

    Science.gov (United States)

    1984-06-01

    cif (Rename cif file to Iroclaim that it is a 5 micron design.) ctrl-D (Sto; the recording session.) Frint typescript (Get bardcopy of compiler...C for details.) S script 0 % esim eultir8c5.sim sultip8c.sacrol (Perform event simulation of chip.) S ctrl-D 0., p rint typescript % vi multipecS.cif...ctrl-D p rint typescript I.. 70 | - cif2ca aultip8c4.cif (Convert citf to caesar format. Benign warnings are issued when user extension 0 lines

  10. Experiment list: SRX214086 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

  11. Experiment list: SRX122520 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  12. Experiment list: SRX122485 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100

  13. Experiment list: SRX122413 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  14. Experiment list: SRX122412 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

  15. Experiment list: SRX214073 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  16. Experiment list: SRX214067 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available fferentiated || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacture...r 1=Santa Cruz || chip antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.bioscien

  17. Experiment list: SRX214075 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  18. Experiment list: SRX214071 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2=

  19. Experiment list: SRX122523 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  20. Experiment list: SRX214085 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

  1. Experiment list: SRX122414 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  2. Experiment list: SRX122522 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  3. Experiment list: SRX122416 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  4. Experiment list: SRX122417 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  5. Experiment list: SRX122406 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Irf1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http:/

  6. Experiment list: SRX122521 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

  7. Experiment list: SRX122566 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

  8. Experiment list: SRX122415 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

  9. Experiment list: SRX214074 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available ge=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  10. Experiment list: SRX214072 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available e=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

  11. Experiment list: SRX122565 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

  12. Experiment list: SRX214070 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available =Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2

  13. Pulmonary responses after wood chip mulch exposure.

    Science.gov (United States)

    Wintermeyer, S F; Kuschner, W G; Wong, H; D'Alessandro, A; Blanc, P D

    1997-04-01

    Organic Dust Toxic Syndrome (ODTS) is a flu-like syndrome that can occur after inhalation of cotton, grain, wood chip dusts, or other organic dusts or aerosols. We investigated whether inflammatory pulmonary responses occur, even after relatively brief, low-level wood chip mulch exposure. Six volunteers were exposed to wood chip mulch dust. Total dust and/or endotoxin levels were measured in five subjects. Pulmonary function and peripheral blood counts were measured before and after exposure in each subject. Bronchoalveolar lavage (BAL) was performed in each subject after exposure, and cell, cytokine, and protein concentrations were measured. Control BAL without previous exposure was also performed on three of the subjects. Three of six subjects had symptoms consistent with ODTS. No clinically relevant or statistically significant changes in pulmonary function tests after exposure were found. Three subjects manifested a marked elevation in neutrophil percentage in their BAL (range, 10 to 57%). When these three subjects underwent control BAL, the postexposure comparison demonstrated an increase in neutrophil levels of 154 +/- 89 x 10(3)/mL (mean +/- standard error; P = 0.22). The mean increase in BAL interleukin-8 levels after exposure, compared with paired control values, was 11.2 +/- SE 2.5 pg/mL (P = 0.047). There was also an increase in BAL interleukin-6 levels that reached borderline significance (6.4 +/- SE 2.0 pg/mL; P = 0.08). Tumor necrosis factor levels were increased in all three subjects' BAL as well (0.4 +/- SE 0.2 pg/mL), but this change was not statistically significant (P = 0.2). Our findings of increased BAL proinflammatory cytokine and neutrophil levels are consistent with the theory that cytokine networking in the lung may mediate ODTS.

  14. Chip-scale optical vortex lattice generator on a silicon platform.

    Science.gov (United States)

    Du, Jing; Wang, Jian

    2017-12-01

    An optical vortex (OV) with an isolated field singularity has been extensively studied in a variety of fields. An OV lattice with a network of optical vortices may find more advanced applications in widespread areas such as optical metrology, optical manipulation, and quantum processing. An OV lattice generated by traditional approaches relies on a number of bulky diffractive optical elements with large volumes and long working distances. Here we present a simple and compact on-chip OV lattice emitter on silicon photonics platforms. The principle relies on three-plane-wave interference. We design, fabricate, and demonstrate an on-chip OV lattice emitter consisting of three parallel waveguides with etched tilt gratings. The tilt gratings facilitate flexible light emission in a wide range of directions, enabling the generation of an OV lattice above the silicon chip. The demonstrated on-chip OV lattice emitter may open a door to generate, manipulate, and detect an OV lattice using photonic integrated circuits.

  15. Noninvasive neuroelectronic interfacing with synaptically connected snail neurons immobilized on a semiconductor chip

    Science.gov (United States)

    Zeck, Günther; Fromherz, Peter

    2001-08-01

    A hybrid circuit of a semiconductor chip and synaptically connected neurons was implemented and characterized. Individual nerve cells from the snail Lymnaea stagnalis were immobilized on a silicon chip by microscopic picket fences of polyimide. The cells formed a network with electrical synapses after outgrowth in brain conditioned medium. Pairs of neurons were electronically interfaced for noninvasive stimulation and recording. Voltage pulses were applied to a capacitive stimulator on the chip to excite the attached neuron. Signals were transmitted in the neuronal net and elicited an action potential in a second neuron. The postsynaptic excitation modulated the current of a transistor on the chip. The implementation of the silicon-neuron-neuron-silicon circuit constitutes a proof-of-principle experiment for the development of neuroelectronic systems to be used in studies on neuronal signal processing, neurocomputation, and neuroprosthetics.

  16. Chips with everything

    CERN Multimedia

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  17. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  18. Integrative analysis of ChIP-chip and ChIP-seq dataset.

    Science.gov (United States)

    Zhu, Lihua Julie

    2013-01-01

    Epigenetic regulation and interactions between transcription factors and regulatory genomic regions play crucial roles in controlling transcriptional regulatory networks that drive development, environmental responses, and disease. Chromatin immunoprecipitation (ChIP) followed by high-throughput sequencing (ChIP-seq) and ChIP followed by genomic tiling microarray hybridization (ChIP-chip) are the two of the most widely used technologies for genome-wide identification of DNA protein interactions and histone modification in vivo. Many algorithms and tools have been developed and evaluated that allow identification of transcription factor binding sites from ChIP-seq or ChIP-chip datasets. However, binding site identification is only the first step; the ultimate goal is to discover the regulatory network of the transcription factor (TF). Here, we present a common workflow for downstream analysis of ChIP-chip and ChIP-seq with an emphasis on annotating binding sites and integration with gene expression data to identify direct and indirect targets of the TF. These tools will help with the overall goal of unraveling transcriptional regulatory networks using datasets publicly available in GEO.

  19. Princeton VLSI Project.

    Science.gov (United States)

    1982-01-01

    and having no physical reality in the fabricated circuit. For example, in the program of fig. 2, the declaration vertical :metal specifies that the...can be given a name, provided that the name given has been declared as a rectangle of the standard simple type vitual . The relationship of the

  20. Silicides for VLSI applications

    CERN Document Server

    Murarka, Shyam P

    1983-01-01

    Most of the subject matter of this book has previously been available only in the form of research papers and review articles. I have not attempted to refer to all the published papers. The reader may find it advantageous to refer to the references listed.