WorldWideScience

Sample records for network processor architectures

  1. The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture

    OpenAIRE

    Biagioni, Andrea; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Perra, Mersia; Rossetti, Davide; Sidore, Carlo; Simula, Francesco; Tosoratto, Laura; Vicini, Piero

    2012-01-01

    One of the most demanding challenges for the designers of parallel computing architectures is to deliver an efficient network infrastructure providing low latency, high bandwidth communications while preserving scalability. Besides off-chip communications between processors, recent multi-tile (i.e. multi-core) architectures face the challenge for an efficient on-chip interconnection network between processor's tiles. In this paper, we present a configurable and scalable architecture, based on...

  2. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  3. Intrusion Detection Architecture Utilizing Graphics Processors

    Directory of Open Access Journals (Sweden)

    Branislav Madoš

    2012-12-01

    Full Text Available With the thriving technology and the great increase in the usage of computer networks, the risk of having these network to be under attacks have been increased. Number of techniques have been created and designed to help in detecting and/or preventing such attacks. One common technique is the use of Intrusion Detection Systems (IDS. Today, number of open sources and commercial IDS are available to match enterprises requirements. However, the performance of these systems is still the main concern. This paper examines perceptions of intrusion detection architecture implementation, resulting from the use of graphics processor. It discusses recent research activities, developments and problems of operating systems security. Some exploratory evidence is presented that shows capabilities of using graphical processors and intrusion detection systems. The focus is on how knowledge experienced throughout the graphics processor inclusion has played out in the design of intrusion detection architecture that is seen as an opportunity to strengthen research expertise.

  4. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  5. An orthogonal wavelet division multiple-access processor architecture for LTE-advanced wireless/radio-over-fiber systems over heterogeneous networks

    Science.gov (United States)

    Mahapatra, Chinmaya; Leung, Victor CM; Stouraitis, Thanos

    2014-12-01

    The increase in internet traffic, number of users, and availability of mobile devices poses a challenge to wireless technologies. In long-term evolution (LTE) advanced system, heterogeneous networks (HetNet) using centralized coordinated multipoint (CoMP) transmitting radio over optical fibers (LTE A-ROF) have provided a feasible way of satisfying user demands. In this paper, an orthogonal wavelet division multiple-access (OWDMA) processor architecture is proposed, which is shown to be better suited to LTE advanced systems as compared to orthogonal frequency division multiple access (OFDMA) as in LTE systems 3GPP rel.8 (3GPP, http://www.3gpp.org/DynaReport/36300.htm). ROF systems are a viable alternative to satisfy large data demands; hence, the performance in ROF systems is also evaluated. To validate the architecture, the circuit is designed and synthesized on a Xilinx vertex-6 field-programmable gate array (FPGA). The synthesis results show that the circuit performs with a clock period as short as 7.036 ns (i.e., a maximum clock frequency of 142.13 MHz) for transform size of 512. A pipelined version of the architecture reduces the power consumption by approximately 89%. We compare our architecture with similar available architectures for resource utilization and timing and provide performance comparison with OFDMA systems for various quality metrics of communication systems. The OWDMA architecture is found to perform better than OFDMA for bit error rate (BER) performance versus signal-to-noise ratio (SNR) in wireless channel as well as ROF media. It also gives higher throughput and mitigates the bad effect of peak-to-average-power ratio (PAPR).

  6. In-Network Adaptation of Video Streams Using Network Processors

    Directory of Open Access Journals (Sweden)

    Mohammad Shorfuzzaman

    2009-01-01

    problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

  7. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  8. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  9. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups...... of tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  10. On the Distribution of Control in Asynchronous Processor Architectures

    OpenAIRE

    Rebello, Vinod

    1997-01-01

    The effective performance of computer systems is to a large measure determined by the synergy between the processor architecture, the instruction set and the compiler. In the past, the sequencing of information within processor architectures has normally been synchronous: controlled centrally by a clock. However, this global signal could possibly limit the future gains in performance that can potentially be achieved through improvements in implementation technology. T...

  11. Image processing system architecture using parallel arrays of digital signal processors

    Science.gov (United States)

    Kshirsagar, Shirish P.; Hobson, Clifford A.; Hartley, David A.; Harvey, David M.

    1993-10-01

    The paper describes the requirements of a high definition, high speed image processing system. Different types of parallel architectures were considered for the system. Advantages and limitations of SIMD and MIMD architectures are briefly discussed for image processing applications. A parallel image processing system based on MIMD architecture has been developed using multiple digital signal processors which can communicate with each other through an interconnection network. Texas Instruments TMS320C40 digital signal processors have been selected because they have a powerful floating point CPU supported by fast parallel communication ports, a DMA coprocessor and two memory interfaces. A five processor system is described in the paper. The EISA bus is used as the host interface and VISION bus is used to transfer images between the processors. The system is being used for automated non-contact inspection in which electro-optic signals are processed to identify manufacturing problems.

  12. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  13. An architecture of the real-time parallel processor CODA

    Energy Technology Data Exchange (ETDEWEB)

    Nishida, Kenji; Toda, Kenji; Takahashi, Eiichi; Yamaguchi, Yoshinori [Electrotechnical Lab., Tsukuba, Ibaraki (Japan)

    1995-08-01

    The architecture described in this paper supports a wide I/O bandwidth, a high performance computation ability, and a real-time property required for sensor fusion processing. The entire system consists of 64 processing elements connected by multi-stage communication network. The processing element has a hardware task queue to help manage tasks for two execution pipelines (one for executing tasks, and the other for communication). Two pipelines are connected with multi-port register file preventing access contension between pipelines. Therefore, a task can be executed without being interfered by inter-processor communication processing. A register file contains eight context to improve the context switch response. Utilizing hardware features employed for CODA, execution predictability will be improved. (author).

  14. Soft-core processor study for node-based architectures.

    Energy Technology Data Exchange (ETDEWEB)

    Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James; Gallegos, Daniel E.; Learn, Mark Walter

    2008-09-01

    Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor built out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.

  15. Reversible machine code and its abstract processor architecture

    DEFF Research Database (Denmark)

    Axelsen, Holger Bock; Glück, Robert; Yokoyama, Tetsuo

    2007-01-01

    A reversible abstract machine architecture and its reversible machine code are presented and formalized. For machine code to be reversible, both the underlying control logic and each instruction must be reversible. A general class of machine instruction sets was proven to be reversible, building ...... on our concept of reversible updates. The presentation is abstract and can serve as a guideline for a family of reversible processor designs. By example, we illustrate programming principles for the abstract machine architecture formalized in this paper....

  16. Processor-in-memory-and-storage architecture

    Energy Technology Data Exchange (ETDEWEB)

    DeBenedictis, Erik

    2018-01-02

    A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

  17. Architecture of a complex arithmetic processor for communication signal processing

    Science.gov (United States)

    Gilfeather, Susan L.; Gehman, John B., Jr.; Harrison, Calvin

    1994-10-01

    The Complex Arithmetic Processor (CAP) is a high performance, single chip Digital Signal Processor optimized for communication signal processing operations. The CAP VLSI provides the communication system building block necessary to meet the increased signal processing requirements of complex modulation types, voice and image compression while maintaining the requirement for small, low power implementations. The chip is intended for high speed, low power digital communication system applications such as hand held spread spectrum communications systems. The CAP architecture has been developed specifically for the complex arithmetic functions required in communication signal processing. The CAP is a software programmable, highly integrated parallel array of processors containing the arithmetic resources, memories, address generation, bit manipulation and logic functions necessary to support the sophisticated processing required in advanced communication equipment. The CAP executes a 1024 point complex Fast Fourier Transform in 131 microseconds.

  18. Design and implementation of a high performance network security processor

    Science.gov (United States)

    Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

    2010-03-01

    The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

  19. Optical chirp z-transform processor with a simplified architecture.

    Science.gov (United States)

    Ngo, Nam Quoc

    2014-12-29

    Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

  20. Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

    Directory of Open Access Journals (Sweden)

    Ausif Mahmood

    1996-01-01

    Full Text Available The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the processes into their equivalent subprograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechanism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transparent to the user.

  1. FPGA Based Intelligent Co-operative Processor in Memory Architecture

    DEFF Research Database (Denmark)

    Ahmed, Zaki; Sotudeh, Reza; Hussain, Dil Muhammad Akbar

    2011-01-01

    benefits of PIM, a concept of Co-operative Intelligent Memory (CIM) was developed by the intelligent system group of University of Hertfordshire, based on the previously developed Co-operative Pseudo Intelligent Memory (CPIM). This paper provides an overview on previous works (CPIM, CIM) and realization......In a continuing effort to improve computer system performance, Processor-In-Memory (PIM) architecture has emerged as an alternative solution. PIM architecture incorporates computational units and control logic directly on the memory to provide immediate access to the data. To exploit the potential...

  2. Clock generators for SOC processors circuits and architectures

    CERN Document Server

    Fahim, Amr

    2004-01-01

    This book explores the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. The text takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The comprehensive coverage includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The book provides numerous real world applications, as well as practical rules-of-thumb for modern designers to use at the system, architectural, as well as the circuit level.

  3. A soft-core processor architecture optimised for radar signal processing applications

    CSIR Research Space (South Africa)

    Broich, R

    2013-12-01

    Full Text Available Current radar signal processor architectures lack either performance or flexibility in terms of ease of modification and large design time overheads. Combinations of processors and FPGAs are typically hard-wired together into a precisely timed...

  4. Information network architectures

    Science.gov (United States)

    Murray, N. D.

    1985-01-01

    Graphs, charts, diagrams and outlines of information relative to information network architectures for advanced aerospace missions, such as the Space Station, are presented. Local area information networks are considered a likely technology solution. The principle needs for the network are listed.

  5. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  6. Soft-core dataflow processor architecture optimised for radar signal processing: Article

    CSIR Research Space (South Africa)

    Broich, R

    2014-10-01

    Full Text Available an iterative design methodology to propose a novel softcore streaming processor architecture. The datapaths of this architecture are arranged in a circular pattern, with multiple operands simultaneously flowing between switching multiplexers and functional...

  7. Directions in parallel processor architecture, and GPUs too

    CERN Multimedia

    CERN. Geneva

    2014-01-01

    Modern computing is power-limited in every domain of computing. Performance increments extracted from instruction-level parallelism (ILP) are no longer power-efficient; they haven't been for some time. Thread-level parallelism (TLP) is a more easily exploited form of parallelism, at the expense of programmer effort to expose it in the program. In this talk, I will introduce you to disparate topics in parallel processor architecture that will impact programming models (and you) in both the near and far future. About the speaker Olivier is a senior GPU (SM) architect at NVIDIA and an active participant in the concurrency working group of the ISO C++ committee. He has also worked on very large diesel engines as a mechanical engineer, and taught at McGill University (Canada) as a faculty instructor.

  8. Mobile networks architecture

    CERN Document Server

    Perez, Andre

    2013-01-01

    This book explains the evolutions of architecture for mobiles and summarizes the different technologies:- 2G: the GSM (Global System for Mobile) network, the GPRS (General Packet Radio Service) network and the EDGE (Enhanced Data for Global Evolution) evolution;- 3G: the UMTS (Universal Mobile Telecommunications System) network and the HSPA (High Speed Packet Access) evolutions:- HSDPA (High Speed Downlink Packet Access),- HSUPA (High Speed Uplink Packet Access),- HSPA+;- 4G: the EPS (Evolved Packet System) network.The telephone service and data transmission are the

  9. Future Network Architectures

    DEFF Research Database (Denmark)

    Wessing, Henrik; Bozorgebrahimi, Kurosh; Belter, Bartosz

    2015-01-01

    This study identifies key requirements for NRENs towards future network architectures that become apparent as users become more mobile and have increased expectations in terms of availability of data. In addition, cost saving requirements call for federated use of, in particular, the optical...

  10. Quantifying loopy network architectures.

    Directory of Open Access Journals (Sweden)

    Eleni Katifori

    Full Text Available Biology presents many examples of planar distribution and structural networks having dense sets of closed loops. An archetype of this form of network organization is the vasculature of dicotyledonous leaves, which showcases a hierarchically-nested architecture containing closed loops at many different levels. Although a number of approaches have been proposed to measure aspects of the structure of such networks, a robust metric to quantify their hierarchical organization is still lacking. We present an algorithmic framework, the hierarchical loop decomposition, that allows mapping loopy networks to binary trees, preserving in the connectivity of the trees the architecture of the original graph. We apply this framework to investigate computer generated graphs, such as artificial models and optimal distribution networks, as well as natural graphs extracted from digitized images of dicotyledonous leaves and vasculature of rat cerebral neocortex. We calculate various metrics based on the asymmetry, the cumulative size distribution and the Strahler bifurcation ratios of the corresponding trees and discuss the relationship of these quantities to the architectural organization of the original graphs. This algorithmic framework decouples the geometric information (exact location of edges and nodes from the metric topology (connectivity and edge weight and it ultimately allows us to perform a quantitative statistical comparison between predictions of theoretical models and naturally occurring loopy graphs.

  11. A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs).

    Science.gov (United States)

    Moradi, Saber; Qiao, Ning; Stefanini, Fabio; Indiveri, Giacomo

    2018-02-01

    Neuromorphic computing systems comprise networks of neurons that use asynchronous events for both computation and communication. This type of representation offers several advantages in terms of bandwidth and power consumption in neuromorphic electronic systems. However, managing the traffic of asynchronous events in large scale systems is a daunting task, both in terms of circuit complexity and memory requirements. Here, we present a novel routing methodology that employs both hierarchical and mesh routing strategies and combines heterogeneous memory structures for minimizing both memory requirements and latency, while maximizing programming flexibility to support a wide range of event-based neural network architectures, through parameter configuration. We validated the proposed scheme in a prototype multicore neuromorphic processor chip that employs hybrid analog/digital circuits for emulating synapse and neuron dynamics together with asynchronous digital circuits for managing the address-event traffic. We present a theoretical analysis of the proposed connectivity scheme, describe the methods and circuits used to implement such scheme, and characterize the prototype chip. Finally, we demonstrate the use of the neuromorphic processor with a convolutional neural network for the real-time classification of visual symbols being flashed to a dynamic vision sensor (DVS) at high speed.

  12. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  13. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

    Directory of Open Access Journals (Sweden)

    Kit eCheung

    2016-01-01

    Full Text Available NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs. Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimised performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP rule for learning. A 6-FPGA system can simulate a network of up to approximately 600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

  14. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

    Science.gov (United States)

    Cheung, Kit; Schultz, Simon R; Luk, Wayne

    2015-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

  15. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

    Science.gov (United States)

    Cheung, Kit; Schultz, Simon R.; Luk, Wayne

    2016-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. PMID:26834542

  16. Towards a networkArchitecture

    DEFF Research Database (Denmark)

    Rüdiger, Bjarne; Tournay, Bruno

    2001-01-01

    Planche, bidrag til DAL-konkurrencen. Hvor industrien har været inspirationen for udviklingen af den moderne arkitektur, er IT det tekniske og æstetiske grundlag for den spirende NetworkArchitecture. Computeren og netværker af computerne er således mere end en metafor for NetworkArchitecture....... NetworkArchitecture består af intelligente byggekomponenter forbundet med hinanden i et netværk og i interaktion med omgivelser....

  17. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

  18. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

    Science.gov (United States)

    Manolakos, Elias S.

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

  19. Assimilation Dynamic Network (ADN) Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The Assimilation Dynamic Network (ADN) is a dynamic inter-processor communication network that spans heterogeneous processor architectures, unifying components,...

  20. A reversible processor architecture and its reversible logic design

    DEFF Research Database (Denmark)

    Thomsen, Michael Kirkedal; Axelsen, Holger Bock; Glück, Robert

    2012-01-01

    an architecture with an ISA that is expressive enough to serve as the target for a compiler from a high-level structured reversible programming language. All-in-all, this paper demonstrates that the design of a complete reversible computing architecture is possible and can serve as the core of a programmable......We describe the design of a purely reversible computing architecture, Bob, and its instruction set, BobISA. The special features of the design include a simple, yet expressive, locally-invertible instruction set, and fully reversible control logic and address calculation. We have designed...

  1. Adaptive Optoelectronic Eyes: Hybrid Sensor/Processor Architectures

    National Research Council Canada - National Science Library

    Tanguay, Jr., Armand R; Jenkins, B. K; von der Malsburg, Christoph; Mel, Bartlett; Biederman, Irving; O'Brien, John; Madhukar, Anupam

    2006-01-01

    The goal of this research program was to develop novel algorithms, architectures, and hardware for a truly smart camera, with inherent capability for semi-autonomous object recognition as well as optimal image capture...

  2. Architectures for Wireless Sensor Networks

    NARCIS (Netherlands)

    Dulman, S.O.; Havinga, Paul J.M.

    2005-01-01

    Various architectures have been developed for wireless sensor networks. Many of them leave to the programmer important concepts as the way in which the inter-task communication and dynamic reconfigurations are addressed. In this paper we describe the characteristics of a new architecture we proposed

  3. Network architecture as internet governance

    Directory of Open Access Journals (Sweden)

    Francesca Musiani

    2013-10-01

    Full Text Available The architecture of a networked system is its underlying technical and logical structure, including transmission equipment, communication protocols, infrastructure, and connectivity between its components or nodes. This article introduces the idea of network architecture as internet governance, and more specifically, it outlines the dialectic between centralised and distributed architectures, institutions and practices, and how they mutually affect each other. The article argues that network architecture is internet governance in the sense that, by changing the design of the networks subtending internet-based services and the global internet itself, its politics are affected – the balance of rights between users and providers, the capacity of online communities to engage in open and direct interaction, the fair competition between actors of the internet market.

  4. A programmable analog VLSI neural network processor for communication receivers.

    Science.gov (United States)

    Choi, J; Bang, S H; Sheu, B J

    1993-01-01

    An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.

  5. Scalable architecture for a room temperature solid-state quantum information processor.

    Science.gov (United States)

    Yao, N Y; Jiang, L; Gorshkov, A V; Maurer, P C; Giedke, G; Cirac, J I; Lukin, M D

    2012-04-24

    The realization of a scalable quantum information processor has emerged over the past decade as one of the central challenges at the interface of fundamental science and engineering. Here we propose and analyse an architecture for a scalable, solid-state quantum information processor capable of operating at room temperature. Our approach is based on recent experimental advances involving nitrogen-vacancy colour centres in diamond. In particular, we demonstrate that the multiple challenges associated with operation at ambient temperature, individual addressing at the nanoscale, strong qubit coupling, robustness against disorder and low decoherence rates can be simultaneously achieved under realistic, experimentally relevant conditions. The architecture uses a novel approach to quantum information transfer and includes a hierarchy of control at successive length scales. Moreover, it alleviates the stringent constraints currently limiting the realization of scalable quantum processors and will provide fundamental insights into the physics of non-equilibrium many-body quantum systems.

  6. Optogenetics in Silicon: A Neural Processor for Predicting Optically Active Neural Networks.

    Science.gov (United States)

    Junwen Luo; Nikolic, Konstantin; Evans, Benjamin D; Na Dong; Xiaohan Sun; Andras, Peter; Yakovlev, Alex; Degenaar, Patrick

    2017-02-01

    We present a reconfigurable neural processor for real-time simulation and prediction of opto-neural behaviour. We combined a detailed Hodgkin-Huxley CA3 neuron integrated with a four-state Channelrhodopsin-2 (ChR2) model into reconfigurable silicon hardware. Our architecture consists of a Field Programmable Gated Array (FPGA) with a custom-built computing data-path, a separate data management system and a memory approach based router. Advancements over previous work include the incorporation of short and long-term calcium and light-dependent ion channels in reconfigurable hardware. Also, the developed processor is computationally efficient, requiring only 0.03 ms processing time per sub-frame for a single neuron and 9.7 ms for a fully connected network of 500 neurons with a given FPGA frequency of 56.7 MHz. It can therefore be utilized for exploration of closed loop processing and tuning of biologically realistic optogenetic circuitry.

  7. Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

    2010-01-01

    The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

  8. Speeding up the MATLAB complex networks package using graphic processors

    Science.gov (United States)

    Zhang, Bai-Da; Tang, Yu-Hua; Wu, Jun-Jie; Li, Xin

    2011-09-01

    The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units (GPU). This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3×. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

  9. Re-engineering Nascom's network management architecture

    Science.gov (United States)

    Drake, Brian C.; Messent, David

    1994-01-01

    The development of Nascom systems for ground communications began in 1958 with Project Vanguard. The low-speed systems (rates less than 9.6 Kbs) were developed following existing standards; but, there were no comparable standards for high-speed systems. As a result, these systems were developed using custom protocols and custom hardware. Technology has made enormous strides since the ground support systems were implemented. Standards for computer equipment, software, and high-speed communications exist and the performance of current workstations exceeds that of the mainframes used in the development of the ground systems. Nascom is in the process of upgrading its ground support systems and providing additional services. The Message Switching System (MSS), Communications Address Processor (CAP), and Multiplexer/Demultiplexer (MDM) Automated Control System (MACS) are all examples of Nascom systems developed using standards such as, X-windows, Motif, and Simple Network Management Protocol (SNMP). Also, the Earth Observing System (EOS) Communications (Ecom) project is stressing standards as an integral part of its network. The move towards standards has produced a reduction in development, maintenance, and interoperability costs, while providing operational quality improvement. The Facility and Resource Manager (FARM) project has been established to integrate the Nascom networks and systems into a common network management architecture. The maximization of standards and implementation of computer automation in the architecture will lead to continued cost reductions and increased operational efficiency. The first step has been to derive overall Nascom requirements and identify the functionality common to all the current management systems. The identification of these common functions will enable the reuse of processes in the management architecture and promote increased use of automation throughout the Nascom network. The MSS, CAP, MACS, and Ecom projects have indicated

  10. Heterogeneous network architectures

    DEFF Research Database (Denmark)

    Christiansen, Henrik Lehrmann

    2006-01-01

    Future networks will be heterogeneous! Due to the sheer size of networks (e.g., the Internet) upgrades cannot be instantaneous and thus heterogeneity appears. This means that instead of trying to find the olution, networks hould be designed as being heterogeneous. One of the key equirements here...

  11. Network Analysis, Architecture, and Design

    CERN Document Server

    McCabe, James D

    2007-01-01

    Traditionally, networking has had little or no basis in analysis or architectural development, with designers relying on technologies they are most familiar with or being influenced by vendors or consultants. However, the landscape of networking has changed so that network services have now become one of the most important factors to the success of many third generation networks. It has become an important feature of the designer's job to define the problems that exist in his network, choose and analyze several optimization parameters during the analysis process, and then prioritize and evalua

  12. Emerging Mobile Networking Architectures

    Science.gov (United States)

    2006-12-01

    years to address this problem area. Basic concepts began as early a the 1970s with DARPA sponsored "packet radio" research, yet a new flurry of design...routing, MAC , middleware). The appropriate mechanisms are also not orthogonal to the intended application or deployment scenario of the mobile ad hoc...technology that can improve the capability of future mobile architectures Original work dates back to DARPA packet radio work 1970s More recent flurry of

  13. Deep Space Network information system architecture study

    Science.gov (United States)

    Beswick, C. A.; Markley, R. W. (Editor); Atkinson, D. J.; Cooper, L. P.; Tausworthe, R. C.; Masline, R. C.; Jenkins, J. S.; Crowe, R. A.; Thomas, J. L.; Stoloff, M. J.

    1992-01-01

    The purpose of this article is to describe an architecture for the DSN information system in the years 2000-2010 and to provide guidelines for its evolution during the 1990's. The study scope is defined to be from the front-end areas at the antennas to the end users (spacecraft teams, principal investigators, archival storage systems, and non-NASA partners). The architectural vision provides guidance for major DSN implementation efforts during the next decade. A strong motivation for the study is an expected dramatic improvement in information-systems technologies--i.e., computer processing, automation technology (including knowledge-based systems), networking and data transport, software and hardware engineering, and human-interface technology. The proposed Ground Information System has the following major features: unified architecture from the front-end area to the end user; open-systems standards to achieve interoperability; DSN production of level 0 data; delivery of level 0 data from the Deep Space Communications Complex, if desired; dedicated telemetry processors for each receiver; security against unauthorized access and errors; and highly automated monitor and control.

  14. Wireless Computational Networking Architectures

    Science.gov (United States)

    2013-12-01

    2] T. Ho, M. Medard, R. Kotter , D. Karger, M. Effros, J. Shi, and B. Leong, “A Random Linear Network Coding Approach to Multicast,” IEEE...218, January 2008. [10] R. Kotter and F. R. Kschischang, “Coding for Errors and Erasures in Random Network Coding,” IEEE Transactions on...Systems, Johns Hopkins University, Baltimore, Maryland, 2011. 6. B. W. Suter and Z. Yan U.S. Patent Pending 13/949,319 Rank Deficient Decoding

  15. Network coding on heterogeneous multi-core processors for wireless sensor networks.

    Science.gov (United States)

    Kim, Deokho; Park, Karam; Ro, Won W

    2011-01-01

    While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine.

  16. Network Coding on Heterogeneous Multi-Core Processors for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Won W. Ro

    2011-08-01

    Full Text Available While network coding is well known for its efficiency and usefulness in wireless sensor networks, the excessive costs associated with decoding computation and complexity still hinder its adoption into practical use. On the other hand, high-performance microprocessors with heterogeneous multi-cores would be used as processing nodes of the wireless sensor networks in the near future. To this end, this paper introduces an efficient network coding algorithm developed for the heterogenous multi-core processors. The proposed idea is fully tested on one of the currently available heterogeneous multi-core processors referred to as the Cell Broadband Engine.

  17. Architecture in the network society

    DEFF Research Database (Denmark)

    2004-01-01

    Under the theme Architecture in the Network Society, participants were invited to focus on the dialog and sharing of knowledge between architects and other disciplines and to reflect on, and propose, new methods in the design process, to enhance and improve the impact of information technology...

  18. Small Universal Accepting Networks of Evolutionary Processors with Filtered Connections

    Directory of Open Access Journals (Sweden)

    Remco Loos

    2009-07-01

    Full Text Available In this paper, we present some results regarding the size complexity of Accepting Networks of Evolutionary Processors with Filtered Connections (ANEPFCs. We show that there are universal ANEPFCs of size 10, by devising a method for simulating 2-Tag Systems. This result significantly improves the known upper bound for the size of universal ANEPFCs which is 18. We also propose a new, computationally and descriptionally efficient simulation of nondeterministic Turing machines by ANEPFCs. More precisely, we describe (informally, due to space limitations how ANEPFCs with 16 nodes can simulate in O(f(n time any nondeterministic Turing machine of time complexity f(n. Thus the known upper bound for the number of nodes in a network simulating an arbitrary Turing machine is decreased from 26 to 16.

  19. Entanglement in a Quantum Annealing Processor

    Science.gov (United States)

    2016-09-07

    Entanglement in a Quantum Annealing Processor T. Lanting,1,* A. J. Przybysz,1 A. Yu. Smirnov,1 F. M. Spedalieri,2,3 M. H. Amin,1,4 A. J. Berkley,1 R...promising path to a practical quantum processor . We have built a series of architecturally scalable QA processors consisting of networks of manufactured...such processor , demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits

  20. Service entity network virtualization architecture and model

    Science.gov (United States)

    Jin, Xue-Guang; Shou, Guo-Chu; Hu, Yi-Hong; Guo, Zhi-Gang

    2017-07-01

    Communication network can be treated as a complex network carrying a variety of services and service can be treated as a network composed of functional entities. There are growing interests in multiplex service entities where individual entity and link can be used for different services simultaneously. Entities and their relationships constitute a service entity network. In this paper, we introduced a service entity network virtualization architecture including service entity network hierarchical model, service entity network model, service implementation and deployment of service entity networks. Service entity network oriented multiplex planning model were also studied and many of these multiplex models were characterized by a significant multiplex of the links or entities in different service entity network. Service entity networks were mapped onto shared physical resources by dynamic resource allocation controller. The efficiency of the proposed architecture was illustrated in a simulation environment that allows for comparative performance evaluation. The results show that, compared to traditional networking architecture, this architecture has a better performance.

  1. Sensor Network Architectures for Monitoring Underwater Pipelines

    Science.gov (United States)

    Mohamed, Nader; Jawhar, Imad; Al-Jaroodi, Jameela; Zhang, Liren

    2011-01-01

    This paper develops and compares different sensor network architecture designs that can be used for monitoring underwater pipeline infrastructures. These architectures are underwater wired sensor networks, underwater acoustic wireless sensor networks, RF (Radio Frequency) wireless sensor networks, integrated wired/acoustic wireless sensor networks, and integrated wired/RF wireless sensor networks. The paper also discusses the reliability challenges and enhancement approaches for these network architectures. The reliability evaluation, characteristics, advantages, and disadvantages among these architectures are discussed and compared. Three reliability factors are used for the discussion and comparison: the network connectivity, the continuity of power supply for the network, and the physical network security. In addition, the paper also develops and evaluates a hierarchical sensor network framework for underwater pipeline monitoring. PMID:22346669

  2. Data Architecture for Sensor Network

    Directory of Open Access Journals (Sweden)

    Jan Ježek

    2012-03-01

    Full Text Available Fast development of hardware in recent years leads to the high availability of simple sensing devices at minimal cost. As a consequence, there is many of sensor networks nowadays. These networks can continuously produce a large amount of observed data including the location of measurement. Optimal data architecture for such propose is a challenging issue due to its large scale and spatio-temporal nature.  The aim of this paper is to describe data architecture that was used in a particular solution for storage of sensor data. This solution is based on relation data model – concretely PostgreSQL and PostGIS. We will mention out experience from real world projects focused on car monitoring and project targeted on agriculture sensor networks. We will also shortly demonstrate the possibilities of client side API and the potential of other open source libraries that can be used for cartographic visualization (e.g. GeoServer. The main objective is to describe the strength and weakness of usage of relation database system for such propose and to introduce also alternative approaches based on NoSQL concept.

  3. DMS processor evolution study

    Science.gov (United States)

    Liu, Yuan-Kwei

    1990-01-01

    Increasing the processor performance and capability has not only become a wish list item for the Space Station Freedom (SSF) Data Management System (DMS), but also a necessity. There are many commercially available processors which have superior performance compared to the 386, but we cannot only consider performance when selecting a processor for the DMS. The processor is the 'foundation' of the DMS. It will affect the local bus, system bus, interface unit, global network, etc., that have been selected for the DMS. Besides, once the processor instruction set architecture (ISA) is selected, all of the important system software will be implemented based on this ISA. Selecting an ISA that has a strong commercial support and can be upgraded in the 30-year life cycle of the Space Station Freedom is one of the most important items for the DMS.

  4. Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

    Directory of Open Access Journals (Sweden)

    Feilong Tang

    2010-01-01

    Full Text Available Mobile and wireless networks are the integrant infrastructure of mobile and pervasive computing that aims at providing transparent and preferred information and services for people anytime anywhere. In such environments, end-to-end network bandwidth is crucial to improve user's transparent experience when providing on-demand services such as mobile video playing. As a result, powerful computing power is required for networked nodes, especially for routers. General-purpose processors cannot meet such requirements due to their limited processing ability, and poor programmability and scalability. Intel's network processor IXP is specially designed for fast packet processing to achieve a broad bandwidth. IXP provides a large number of registers to reduce the number of memory accesses. Registers in an IXP are physically partitioned as two banks so that two source operands in an instruction have to come from the two banks respectively, which makes the IXP register allocation tricky and different from conventional ones. In this paper, we investigate an approach for efficiently generating balanced bipartite graph and register allocation algorithms for the dual-bank register allocation in IXPs. The paper presents a graph uniform 2-way partition algorithm (FPT, which provides an optimal solution to the graph partition, and a heuristic algorithm for generating balanced bipartite graph. Finally, we design a framework for IXP register allocation. Experimental results demonstrate the framework and the algorithms are efficient in register allocation for IXP network processors.

  5. Security Shift in Future Network Architectures

    NARCIS (Netherlands)

    Hartog, T.; Schotanus, H.A.; Verkoelen, C.A.A.

    2010-01-01

    In current practice military communication infrastructures are deployed as stand-alone networked information systems. Network-Enabled Capabilities (NEC) and combined military operations lead to new requirements which current communication architectures cannot deliver. This paper informs IT

  6. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

    National Research Council Canada - National Science Library

    Cheung, Kit; Schultz, Simon R; Luk, Wayne

    2015-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs...

  7. A node architecture for disaster relief networking

    NARCIS (Netherlands)

    Hoeksema, F.W.; Heskamp, M.; Schiphorst, Roelof; Slump, Cornelis H.

    2005-01-01

    In this paper we present node architecture for a personal node in a cognitive ad-hoc disaster relief network. This architecture is motivated from the network system requirements, especially single-hop distance and jamming-resilience requirements. It is shown that the power consumption of current-day

  8. Towards Dependable Network-on-Chip Architectures

    NARCIS (Netherlands)

    Chen, C.

    2015-01-01

    The aggressive semiconductor technology scaling provides the means for doubling the amount of transistors on a single chip each and every 18 months. To efficiently utilize these vast chip resources, Multi-Processor Systems on Chip (MPSoCs) integrated with a Network-on-Chip (NoC) communication

  9. CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Arun Ravindran

    2012-02-01

    Full Text Available Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs. While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9

  10. Heterogeneous reconfigurable processors for real-time baseband processing from algorithm to architecture

    CERN Document Server

    Zhang, Chenxin; Öwall, Viktor

    2016-01-01

    This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfigur...

  11. Evaluation of Dual-Launch Lunar Architectures Using the Mission Assessment Post Processor

    Science.gov (United States)

    Stewart, Shaun M.; Senent, Juan; Williams, Jacob; Condon, Gerald L.; Lee, David E.

    2010-01-01

    The National Aeronautics and Space Administrations (NASA) Constellation Program is currently designing a new transportation system to replace the Space Shuttle, support human missions to both the International Space Station (ISS) and the Moon, and enable the eventual establishment of an outpost on the lunar surface. The present Constellation architecture is designed to meet nominal capability requirements and provide flexibility sufficient for handling a host of contingency scenarios including (but not limited to) launch delays at the Earth. This report summarizes a body of work performed in support of the Review of U.S. Human Space Flight Committee. It analyzes three lunar orbit rendezvous dual-launch architecture options which incorporate differing methodologies for mitigating the effects of launch delays at the Earth. NASA employed the recently-developed Mission Assessment Post Processor (MAPP) tool to quickly evaluate vehicle performance requirements for several candidate approaches for conducting human missions to the Moon. The MAPP tool enabled analysis of Earth perturbation effects and Earth-Moon geometry effects on the integrated vehicle performance as it varies over the 18.6-year lunar nodal cycle. Results are provided summarizing best-case and worst-case vehicle propellant requirements for each architecture option. Additionally, the associated vehicle payload mass requirements at launch are compared between each architecture and against those of the Constellation Program. The current Constellation Program architecture assumes that the Altair lunar lander and Earth Departure Stage (EDS) vehicles are launched on a heavy lift launch vehicle. The Orion Crew Exploration Vehicle (CEV) is separately launched on a smaller man-rated vehicle. This strategy relaxes man-rating requirements for the heavy lift launch vehicle and has the potential to significantly reduce the cost of the overall architecture over the operational lifetime of the program. The crew launch

  12. A Security Architecture for Health Information Networks

    OpenAIRE

    Kailar, Rajashekar

    2007-01-01

    Health information network security needs to balance exacting security controls with practicality, and ease of implementation in today’s healthcare enterprise. Recent work on ‘nationwide health information network’ architectures has sought to share highly confidential data over insecure networks such as the Internet. Using basic patterns of health network data flow and trust models to support secure communication between network nodes, we abstract network security requirements to a core set t...

  13. An architecture for human-network interfaces

    DEFF Research Database (Denmark)

    Sonnenwald, Diane H.

    1990-01-01

    Some of the issues (and their consequences) that arise when human-network interfaces (HNIs) are viewed from the perspective of people who use and develop them are examined. Target attributes of HNI architecture are presented. A high-level architecture model that supports the attributes is discussed...

  14. Microsoft Windows 2000 Network Architecture Guide

    National Research Council Canada - National Science Library

    Bartock, Paul

    2000-01-01

    The purpose of this guide is to inform the reader about the services that are available in the Microsoft Windows 2000 environment and how to integrate these services into their network architecture...

  15. The functional consequences of mutualistic network architecture.

    Directory of Open Access Journals (Sweden)

    José M Gómez

    Full Text Available The architecture and properties of many complex networks play a significant role in the functioning of the systems they describe. Recently, complex network theory has been applied to ecological entities, like food webs or mutualistic plant-animal interactions. Unfortunately, we still lack an accurate view of the relationship between the architecture and functioning of ecological networks. In this study we explore this link by building individual-based pollination networks from eight Erysimum mediohispanicum (Brassicaceae populations. In these individual-based networks, each individual plant in a population was considered a node, and was connected by means of undirected links to conspecifics sharing pollinators. The architecture of these unipartite networks was described by means of nestedness, connectivity and transitivity. Network functioning was estimated by quantifying the performance of the population described by each network as the number of per-capita juvenile plants produced per population. We found a consistent relationship between the topology of the networks and their functioning, since variation across populations in the average per-capita production of juvenile plants was positively and significantly related with network nestedness, connectivity and clustering. Subtle changes in the composition of diverse pollinator assemblages can drive major consequences for plant population performance and local persistence through modifications in the structure of the inter-plant pollination networks.

  16. implementation of internet protocol network architecture

    African Journals Online (AJOL)

    User

    ABSTRACT. Advances in multimedia technologies and development of overlay networks foster the opportu- nity for creating new value-added services over the current Internet. In this paper, a new service network architecture that supports multiparty multimedia conferencing applications, character- istics of which include ...

  17. Network interconnections: an architectural reference model

    NARCIS (Netherlands)

    Butscher, B.; Lenzini, L.; Morling, R.; Vissers, C.A.; Popescu-Zeletin, R.; van Sinderen, Marten J.; Heger, D.; Krueger, G.; Spaniol, O.; Zorn, W.

    1985-01-01

    One of the major problems in understanding the different approaches in interconnecting networks of different technologies is the lack of reference to a general model. The paper develops the rationales for a reference model of network interconnection and focuses on the architectural implications for

  18. Network architecture functional description and design

    Energy Technology Data Exchange (ETDEWEB)

    Stans, L.; Bencoe, M.; Brown, D.; Kelly, S.; Pierson, L.; Schaldach, C.

    1989-05-25

    This report provides a top level functional description and design for the development and implementation of the central network to support the next generation of SNL, Albuquerque supercomputer in a UNIX{reg sign} environment. It describes the network functions and provides an architecture and topology.

  19. Virtualized cognitive network architecture for 5G cellular networks

    KAUST Repository

    Elsawy, Hesham

    2015-07-17

    Cellular networks have preserved an application agnostic and base station (BS) centric architecture1 for decades. Network functionalities (e.g. user association) are decided and performed regardless of the underlying application (e.g. automation, tactile Internet, online gaming, multimedia). Such an ossified architecture imposes several hurdles against achieving the ambitious metrics of next generation cellular systems. This article first highlights the features and drawbacks of such architectural ossification. Then the article proposes a virtualized and cognitive network architecture, wherein network functionalities are implemented via software instances in the cloud, and the underlying architecture can adapt to the application of interest as well as to changes in channels and traffic conditions. The adaptation is done in terms of the network topology by manipulating connectivities and steering traffic via different paths, so as to attain the applications\\' requirements and network design objectives. The article presents cognitive strategies to implement some of the classical network functionalities, along with their related implementation challenges. The article further presents a case study illustrating the performance improvement of the proposed architecture as compared to conventional cellular networks, both in terms of outage probability and handover rate.

  20. Mobile opportunistic networks architectures, protocols and applications

    CERN Document Server

    Denko, Mieso K

    2011-01-01

    Widespread availability of pervasive and mobile devices coupled with recent advances in networking technologies make opportunistic networks one of the most promising communication technologies for a growing number of future mobile applications. Covering the basics as well as advanced concepts, this book introduces state-of-the-art research findings, technologies, tools, and innovations. Prominent researchers from academia and industry report on communication architectures, network algorithms and protocols, emerging applications, experimental studies, simulation tools, implementation test beds,

  1. A security architecture for health information networks.

    Science.gov (United States)

    Kailar, Rajashekar; Muralidhar, Vinod

    2007-10-11

    Health information network security needs to balance exacting security controls with practicality, and ease of implementation in today's healthcare enterprise. Recent work on 'nationwide health information network' architectures has sought to share highly confidential data over insecure networks such as the Internet. Using basic patterns of health network data flow and trust models to support secure communication between network nodes, we abstract network security requirements to a core set to enable secure inter-network data sharing. We propose a minimum set of security controls that can be implemented without needing major new technologies, but yet realize network security and privacy goals of confidentiality, integrity and availability. This framework combines a set of technology mechanisms with environmental controls, and is shown to be sufficient to counter commonly encountered network security threats adequately.

  2. HONEI: A collection of libraries for numerical computations targeting multiple processor architectures

    Science.gov (United States)

    van Dyk, Danny; Geveler, Markus; Mallach, Sven; Ribbrock, Dirk; Göddeke, Dominik; Gutwenger, Carsten

    2009-12-01

    We present HONEI, an open-source collection of libraries offering a hardware oriented approach to numerical calculations. HONEI abstracts the hardware, and applications written on top of HONEI can be executed on a wide range of computer architectures such as CPUs, GPUs and the Cell processor. We demonstrate the flexibility and performance of our approach with two test applications, a Finite Element multigrid solver for the Poisson problem and a robust and fast simulation of shallow water waves. By linking against HONEI's libraries, we achieve a two-fold speedup over straight forward C++ code using HONEI's SSE backend, and additional 3-4 and 4-16 times faster execution on the Cell and a GPU. A second important aspect of our approach is that the full performance capabilities of the hardware under consideration can be exploited by adding optimised application-specific operations to the HONEI libraries. HONEI provides all necessary infrastructure for development and evaluation of such kernels, significantly simplifying their development. Program summaryProgram title: HONEI Catalogue identifier: AEDW_v1_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/AEDW_v1_0.html Program obtainable from: CPC Program Library, Queen's University, Belfast, N. Ireland Licensing provisions: GPLv2 No. of lines in distributed program, including test data, etc.: 216 180 No. of bytes in distributed program, including test data, etc.: 1 270 140 Distribution format: tar.gz Programming language: C++ Computer: x86, x86_64, NVIDIA CUDA GPUs, Cell blades and PlayStation 3 Operating system: Linux RAM: at least 500 MB free Classification: 4.8, 4.3, 6.1 External routines: SSE: none; [1] for GPU, [2] for Cell backend Nature of problem: Computational science in general and numerical simulation in particular have reached a turning point. The revolution developers are facing is not primarily driven by a change in (problem-specific) methodology, but rather by the fundamental paradigm shift of the

  3. Accepting Hybrid Networks of Evolutionary Processors with Special Topologies and Small Communication

    Directory of Open Access Journals (Sweden)

    Jürgen Dassow

    2010-08-01

    Full Text Available Starting from the fact that complete Accepting Hybrid Networks of Evolutionary Processors allow much communication between the nodes and are far from network structures used in practice, we propose in this paper three network topologies that restrict the communication: star networks, ring networks, and grid networks. We show that ring-AHNEPs can simulate 2-tag systems, thus we deduce the existence of a universal ring-AHNEP. For star networks or grid networks, we show a more general result; that is, each recursively enumerable language can be accepted efficiently by a star- or grid-AHNEP. We also present bounds for the size of these star and grid networks. As a consequence we get that each recursively enumerable can be accepted by networks with at most 13 communication channels and by networks where each node communicates with at most three other nodes.

  4. Architecture for Mobile Heterogeneous Multi Domain Networks

    Directory of Open Access Journals (Sweden)

    Arjan Durresi

    2010-01-01

    Full Text Available Multi domain networks can be used in several scenarios including military, enterprize networks, emergency networks and many other cases. In such networks, each domain might be under its own administration. Therefore, the cooperation among domains is conditioned by individual domain policies regarding sharing information, such as network topology, connectivity, mobility, security, various service availability and so on. We propose a new architecture for Heterogeneous Multi Domain (HMD networks, in which one the operations are subject to specific domain policies. We propose a hierarchical architecture, with an infrastructure of gateways at highest-control level that enables policy based interconnection, mobility and other services among domains. Gateways are responsible for translation among different communication protocols, including routing, signalling, and security. Besides the architecture, we discuss in more details the mobility and adaptive capacity of services in HMD. We discuss the HMD scalability and other advantages compared to existing architectural and mobility solutions. Furthermore, we analyze the dynamic availability at the control level of the hierarchy.

  5. Cognitive optical networks: architectures and techniques

    Science.gov (United States)

    Grebeshkov, Alexander Y.

    2017-04-01

    This article analyzes architectures and techniques of the optical networks with taking into account the cognitive methodology based on continuous cycle "Observe-Orient-Plan-Decide-Act-Learn" and the ability of the cognitive systems adjust itself through an adaptive process by responding to new changes in the environment. Cognitive optical network architecture includes cognitive control layer with knowledge base for control of software-configurable devices as reconfigurable optical add-drop multiplexers, flexible optical transceivers, software-defined receivers. Some techniques for cognitive optical networks as flexible-grid technology, broker-oriented technique, machine learning are examined. Software defined optical network and integration of wireless and optical networks with radio over fiber technique and fiber-wireless technique in the context of cognitive technologies are discussed.

  6. Stable architectures for deep neural networks

    Science.gov (United States)

    Haber, Eldad; Ruthotto, Lars

    2018-01-01

    Deep neural networks have become invaluable tools for supervised machine learning, e.g. classification of text or images. While often offering superior results over traditional techniques and successfully expressing complicated patterns in data, deep architectures are known to be challenging to design and train such that they generalize well to new data. Critical issues with deep architectures are numerical instabilities in derivative-based learning algorithms commonly called exploding or vanishing gradients. In this paper, we propose new forward propagation techniques inspired by systems of ordinary differential equations (ODE) that overcome this challenge and lead to well-posed learning problems for arbitrarily deep networks. The backbone of our approach is our interpretation of deep learning as a parameter estimation problem of nonlinear dynamical systems. Given this formulation, we analyze stability and well-posedness of deep learning and use this new understanding to develop new network architectures. We relate the exploding and vanishing gradient phenomenon to the stability of the discrete ODE and present several strategies for stabilizing deep learning for very deep networks. While our new architectures restrict the solution space, several numerical experiments show their competitiveness with state-of-the-art networks.

  7. Integrated Network Architecture for NASA's Orion Missions

    Science.gov (United States)

    Bhasin, Kul B.; Hayden, Jeffrey L.; Sartwell, Thomas; Miller, Ronald A.; Hudiburg, John J.

    2008-01-01

    NASA is planning a series of short and long duration human and robotic missions to explore the Moon and then Mars. The series of missions will begin with a new crew exploration vehicle (called Orion) that will initially provide crew exchange and cargo supply support to the International Space Station (ISS) and then become a human conveyance for travel to the Moon. The Orion vehicle will be mounted atop the Ares I launch vehicle for a series of pre-launch tests and then launched and inserted into low Earth orbit (LEO) for crew exchange missions to the ISS. The Orion and Ares I comprise the initial vehicles in the Constellation system of systems that later includes Ares V, Earth departure stage, lunar lander, and other lunar surface systems for the lunar exploration missions. These key systems will enable the lunar surface exploration missions to be initiated in 2018. The complexity of the Constellation system of systems and missions will require a communication and navigation infrastructure to provide low and high rate forward and return communication services, tracking services, and ground network services. The infrastructure must provide robust, reliable, safe, sustainable, and autonomous operations at minimum cost while maximizing the exploration capabilities and science return. The infrastructure will be based on a network of networks architecture that will integrate NASA legacy communication, modified elements, and navigation systems. New networks will be added to extend communication, navigation, and timing services for the Moon missions. Internet protocol (IP) and network management systems within the networks will enable interoperability throughout the Constellation system of systems. An integrated network architecture has developed based on the emerging Constellation requirements for Orion missions. The architecture, as presented in this paper, addresses the early Orion missions to the ISS with communication, navigation, and network services over five

  8. MIRAI Architecture for Heterogeneous Network

    NARCIS (Netherlands)

    Wu, Gang; Mizuno, Mitsuhiko; Havinga, Paul J.M.

    One of the keywords that describe next-generation wireless communications is "seamless." As part of the e-Japan Plan promoted by the Japanese Government, the Multimedia Integrated Network by Radio Access Innovation project has as its goal the development of new technologies to enable seamless

  9. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  10. Architecture for networked electronic patient record systems.

    Science.gov (United States)

    Takeda, H; Matsumura, Y; Kuwata, S; Nakano, H; Sakamoto, N; Yamamoto, R

    2000-11-01

    There have been two major approaches to the development of networked electronic patient record (EPR) architecture. One uses object-oriented methodologies for constructing the model, which include the GEHR project, Synapses, HL7 RIM and so on. The second approach uses document-oriented methodologies, as applied in examples of HL7 PRA. It is practically beneficial to take the advantages of both approaches and to add solution technologies for network security such as PKI. In recognition of the similarity with electronic commerce, a certificate authority as a trusted third party will be organised for establishing networked EPR system. This paper describes a Japanese functional model that has been developed, and proposes a document-object-oriented architecture, which is-compared with other existing models.

  11. Simulation-based Modeling Frameworks for Networked Multi-processor System-on-Chip

    DEFF Research Database (Denmark)

    Mahadevan, Shankar

    2006-01-01

    This thesis deals with modeling aspects of multi-processor system-on-chip (MpSoC) design affected by the on-chip interconnect, also called the Network-on-Chip (NoC), at various levels of abstraction. To begin with, we undertook a comprehensive survey of research and design practices of networked Mp......: namely ARTS and RIPE, that allows to model hardware (computation time, power consumption, network latency, caching effect, etc.) and software (application partition and mapping, operating system scheduling, interrupt handling, etc.) aspects from system-level to cycle-true abstraction. Thereby, we can...

  12. Distributed Prognostics and Health Management with a Wireless Network Architecture

    Science.gov (United States)

    Goebel, Kai; Saha, Sankalita; Sha, Bhaskar

    2013-01-01

    A heterogeneous set of system components monitored by a varied suite of sensors and a particle-filtering (PF) framework, with the power and the flexibility to adapt to the different diagnostic and prognostic needs, has been developed. Both the diagnostic and prognostic tasks are formulated as a particle-filtering problem in order to explicitly represent and manage uncertainties in state estimation and remaining life estimation. Current state-of-the-art prognostic health management (PHM) systems are mostly centralized in nature, where all the processing is reliant on a single processor. This can lead to a loss in functionality in case of a crash of the central processor or monitor. Furthermore, with increases in the volume of sensor data as well as the complexity of algorithms, traditional centralized systems become for a number of reasons somewhat ungainly for successful deployment, and efficient distributed architectures can be more beneficial. The distributed health management architecture is comprised of a network of smart sensor devices. These devices monitor the health of various subsystems or modules. They perform diagnostics operations and trigger prognostics operations based on user-defined thresholds and rules. The sensor devices, called computing elements (CEs), consist of a sensor, or set of sensors, and a communication device (i.e., a wireless transceiver beside an embedded processing element). The CE runs in either a diagnostic or prognostic operating mode. The diagnostic mode is the default mode where a CE monitors a given subsystem or component through a low-weight diagnostic algorithm. If a CE detects a critical condition during monitoring, it raises a flag. Depending on availability of resources, a networked local cluster of CEs is formed that then carries out prognostics and fault mitigation by efficient distribution of the tasks. It should be noted that the CEs are expected not to suspend their previous tasks in the prognostic mode. When the

  13. An Evolutionary Optimization Framework for Neural Networks and Neuromorphic Architectures

    Energy Technology Data Exchange (ETDEWEB)

    Schuman, Catherine D [ORNL; Plank, James [University of Tennessee (UT); Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

    2016-01-01

    As new neural network and neuromorphic architectures are being developed, new training methods that operate within the constraints of the new architectures are required. Evolutionary optimization (EO) is a convenient training method for new architectures. In this work, we review a spiking neural network architecture and a neuromorphic architecture, and we describe an EO training framework for these architectures. We present the results of this training framework on four classification data sets and compare those results to other neural network and neuromorphic implementations. We also discuss how this EO framework may be extended to other architectures.

  14. Multiple core computer processor with globally-accessible local memories

    Energy Technology Data Exchange (ETDEWEB)

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  15. Architecture dependence of actin filament network disassembly.

    Science.gov (United States)

    Gressin, Laurène; Guillotin, Audrey; Guérin, Christophe; Blanchoin, Laurent; Michelot, Alphée

    2015-06-01

    Turnover of actin networks in cells requires the fast disassembly of aging actin structures. While ADF/cofilin and Aip1 have been identified as central players, how their activities are modulated by the architecture of the networks remains unknown. Using our ability to reconstitute a diverse array of cellular actin organizations, we found that ADF/cofilin binding and ADF/cofilin-mediated disassembly both depend on actin geometrical organization. ADF/cofilin decorates strongly and stabilizes actin cables, whereas its weaker interaction to Arp2/3 complex networks is correlated with their dismantling and their reorganization into stable architectures. Cooperation of ADF/cofilin with Aip1 is necessary to trigger the full disassembly of all actin filament networks. Additional experiments performed at the single-molecule level indicate that this cooperation is optimal above a threshold of 23 molecules of ADF/cofilin bound as clusters along an actin filament. Our results indicate that although ADF/cofilin is able to dismantle selectively branched networks through severing and debranching, stochastic disassembly of actin filaments by ADF/cofilin and Aip1 represents an efficient alternative pathway for the full disassembly of all actin networks. Our data support a model in which the binding of ADF/cofilin is required to trigger a structural change of the actin filaments, as a prerequisite for their disassembly by Aip1. Copyright © 2015 Elsevier Ltd. All rights reserved.

  16. Multisite phosphorylation networks as signal processors for Cdk1.

    Science.gov (United States)

    Kõivomägi, Mardo; Ord, Mihkel; Iofik, Anna; Valk, Ervin; Venta, Rainis; Faustova, Ilona; Kivi, Rait; Balog, Eva Rose M; Rubin, Seth M; Loog, Mart

    2013-12-01

    The order and timing of cell-cycle events is controlled by changing substrate specificity and different activity thresholds of cyclin-dependent kinases (CDKs). However, it is not understood how a single protein kinase can trigger hundreds of switches in a sufficiently time-resolved fashion. We show that cyclin-Cdk1-Cks1-dependent phosphorylation of multisite targets in Saccharomyces cerevisiae is controlled by key substrate parameters including distances between phosphorylation sites, distribution of serines and threonines as phosphoacceptors and positioning of cyclin-docking motifs. The component mediating the key interactions in this process is Cks1, the phosphoadaptor subunit of the cyclin-Cdk1-Cks1 complex. We propose that variation of these parameters within networks of phosphorylation sites in different targets provides a wide range of possibilities for differential amplification of Cdk1 signals, thus providing a mechanism to generate a wide range of thresholds in the cell cycle.

  17. Cloud Radio Access Network architecture. Towards 5G mobile networks

    DEFF Research Database (Denmark)

    Checko, Aleksandra

    Cloud Radio Access Network (C-RAN) is a novel mobile network architecture which can address a number of challenges that mobile operators face while trying to support ever-growing end-users’ needs towards 5th generation of mobile networks (5G). The main idea behind C-RAN is to split the base......, and for the analyzed scenario it can assure synchronization on the nanosecond level, fulfilling mobile network requirements. Furthermore, mechanisms to lower delay and jitter have been identified, namely: source scheduling and preemption. An innovative source scheduling scheme which can minimize jitter has been...

  18. Acceleration of spiking neural network based pattern recognition on NVIDIA graphics processors.

    Science.gov (United States)

    Han, Bing; Taha, Tarek M

    2010-04-01

    There is currently a strong push in the research community to develop biological scale implementations of neuron based vision models. Systems at this scale are computationally demanding and generally utilize more accurate neuron models, such as the Izhikevich and the Hodgkin-Huxley models, in favor of the more popular integrate and fire model. We examine the feasibility of using graphics processing units (GPUs) to accelerate a spiking neural network based character recognition network to enable such large scale systems. Two versions of the network utilizing the Izhikevich and Hodgkin-Huxley models are implemented. Three NVIDIA general-purpose (GP) GPU platforms are examined, including the GeForce 9800 GX2, the Tesla C1060, and the Tesla S1070. Our results show that the GPGPUs can provide significant speedup over conventional processors. In particular, the fastest GPGPU utilized, the Tesla S1070, provided a speedup of 5.6 and 84.4 over highly optimized implementations on the fastest central processing unit (CPU) tested, a quadcore 2.67 GHz Xeon processor, for the Izhikevich and the Hodgkin-Huxley models, respectively. The CPU implementation utilized all four cores and the vector data parallelism offered by the processor. The results indicate that GPUs are well suited for this application domain.

  19. An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications.

    Science.gov (United States)

    Park, Seong-Wook; Park, Junyoung; Bong, Kyeongryeol; Shin, Dongjoo; Lee, Jinmook; Choi, Sungpill; Yoo, Hoi-Jun

    2015-12-01

    Deep Learning algorithm is widely used for various pattern recognition applications such as text recognition, object recognition and action recognition because of its best-in-class recognition accuracy compared to hand-crafted algorithm and shallow learning based algorithms. Long learning time caused by its complex structure, however, limits its usage only in high-cost servers or many-core GPU platforms so far. On the other hand, the demand on customized pattern recognition within personal devices will grow gradually as more deep learning applications will be developed. This paper presents a SoC implementation to enable deep learning applications to run with low cost platforms such as mobile or portable devices. Different from conventional works which have adopted massively-parallel architecture, this work adopts task-flexible architecture and exploits multiple parallelism to cover complex functions of convolutional deep belief network which is one of popular deep learning/inference algorithms. In this paper, we implement the most energy-efficient deep learning and inference processor for wearable system. The implemented 2.5 mm × 4.0 mm deep learning/inference processor is fabricated using 65 nm 8-metal CMOS technology for a battery-powered platform with real-time deep inference and deep learning operation. It consumes 185 mW average power, and 213.1 mW peak power at 200 MHz operating frequency and 1.2 V supply voltage. It achieves 411.3 GOPS peak performance and 1.93 TOPS/W energy efficiency, which is 2.07× higher than the state-of-the-art.

  20. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

    DEFF Research Database (Denmark)

    Kasapaki, Evangelia; Schoeberl, Martin; Sørensen, Rasmus Bo

    2016-01-01

    In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing...... (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result...

  1. The TurboLAN project. Phase 1: Protocol choices for high speed local area networks. Phase 2: TurboLAN Intelligent Network Adapter Card, (TINAC) architecture

    Science.gov (United States)

    Alkhatib, Hasan S.

    1991-01-01

    The hardware and the software architecture of the TurboLAN Intelligent Network Adapter Card (TINAC) are described. A high level as well as detailed treatment of the workings of various components of the TINAC are presented. The TINAC is divided into the following four major functional units: (1) the network access unit (NAU); (2) the buffer management unit; (3) the host interface unit; and (4) the node processor unit.

  2. Preliminary design of an advanced programmable digital filter network for large passive acoustic ASW systems. [Parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    McWilliams, T.; Widdoes, Jr., L. C.; Wood, L.

    1976-09-30

    The design of an extremely high performance programmable digital filter of novel architecture, the LLL Programmable Digital Filter, is described. The digital filter is a high-performance multiprocessor having general purpose applicability and high programmability; it is extremely cost effective either in a uniprocessor or a multiprocessor configuration. The architecture and instruction set of the individual processor was optimized with regard to the multiple processor configuration. The optimal structure of a parallel processing system was determined for addressing the specific Navy application centering on the advanced digital filtering of passive acoustic ASW data of the type obtained from the SOSUS net. 148 figures. (RWR)

  3. Navigation Architecture for a Space Mobile Network

    Science.gov (United States)

    Valdez, Jennifer E.; Ashman, Benjamin; Gramling, Cheryl; Heckler, Gregory W.; Carpenter, Russell

    2016-01-01

    The Tracking and Data Relay Satellite System (TDRSS) Augmentation Service for Satellites (TASS) is a proposed beacon service to provide a global, space based GPS augmentation service based on the NASA Global Differential GPS (GDGPS) System. The TASS signal will be tied to the GPS time system and usable as an additional ranging and Doppler radiometric source. Additionally, it will provide data vital to autonomous navigation in the near Earth regime, including space weather information, TDRS ephemerides, Earth Orientation Parameters (EOP), and forward commanding capability. TASS benefits include enhancing situational awareness, enabling increased autonomy, and providing near real-time command access for user platforms. As NASA Headquarters' Space Communication and Navigation Office (SCaN) begins to move away from a centralized network architecture and towards a Space Mobile Network (SMN) that allows for user initiated services, autonomous navigation will be a key part of such a system. This paper explores how a TASS beacon service enables the Space Mobile Networking paradigm, what a typical user platform would require, and provides an in-depth analysis of several navigation scenarios and operations concepts. This paper provides an overview of the TASS beacon and its role within the SMN and user community. Supporting navigation analysis is presented for two user mission scenarios: an Earth observing spacecraft in low earth orbit (LEO), and a highly elliptical spacecraft in a lunar resonance orbit. These diverse flight scenarios indicate the breadth of applicability of the TASS beacon for upcoming users within the current network architecture and in the SMN.

  4. NATO Human View Architecture and Human Networks

    Science.gov (United States)

    Handley, Holly A. H.; Houston, Nancy P.

    2010-01-01

    The NATO Human View is a system architectural viewpoint that focuses on the human as part of a system. Its purpose is to capture the human requirements and to inform on how the human impacts the system design. The viewpoint contains seven static models that include different aspects of the human element, such as roles, tasks, constraints, training and metrics. It also includes a Human Dynamics component to perform simulations of the human system under design. One of the static models, termed Human Networks, focuses on the human-to-human communication patterns that occur as a result of ad hoc or deliberate team formation, especially teams distributed across space and time. Parameters of human teams that effect system performance can be captured in this model. Human centered aspects of networks, such as differences in operational tempo (sense of urgency), priorities (common goal), and team history (knowledge of the other team members), can be incorporated. The information captured in the Human Network static model can then be included in the Human Dynamics component so that the impact of distributed teams is represented in the simulation. As the NATO militaries transform to a more networked force, the Human View architecture is an important tool that can be used to make recommendations on the proper mix of technological innovations and human interactions.

  5. Probabilistic logic modeling of network reliability for hybrid network architectures

    Energy Technology Data Exchange (ETDEWEB)

    Wyss, G.D.; Schriner, H.K.; Gaylor, T.R.

    1996-10-01

    Sandia National Laboratories has found that the reliability and failure modes of current-generation network technologies can be effectively modeled using fault tree-based probabilistic logic modeling (PLM) techniques. We have developed fault tree models that include various hierarchical networking technologies and classes of components interconnected in a wide variety of typical and atypical configurations. In this paper we discuss the types of results that can be obtained from PLMs and why these results are of great practical value to network designers and analysts. After providing some mathematical background, we describe the `plug-and-play` fault tree analysis methodology that we have developed for modeling connectivity and the provision of network services in several current- generation network architectures. Finally, we demonstrate the flexibility of the method by modeling the reliability of a hybrid example network that contains several interconnected ethernet, FDDI, and token ring segments. 11 refs., 3 figs., 1 tab.

  6. A Survey of 5G Network: Architecture and Emerging Technologies

    National Research Council Canada - National Science Library

    Gupta, A; Jha, R. K

    2015-01-01

    .... This paper presents the results of a detailed survey on the fifth generation (5G) cellular network architecture and some of the key emerging technologies that are helpful in improving the architecture and meeting the demands of users...

  7. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  8. A fast band-Krylov eigensolver for macromolecular functional motion simulation on multicore architectures and graphics processors

    Science.gov (United States)

    Aliaga, José I.; Alonso, Pedro; Badía, José M.; Chacón, Pablo; Davidović, Davor; López-Blanco, José R.; Quintana-Ortí, Enrique S.

    2016-03-01

    We introduce a new iterative Krylov subspace-based eigensolver for the simulation of macromolecular motions on desktop multithreaded platforms equipped with multicore processors and, possibly, a graphics accelerator (GPU). The method consists of two stages, with the original problem first reduced into a simpler band-structured form by means of a high-performance compute-intensive procedure. This is followed by a memory-intensive but low-cost Krylov iteration, which is off-loaded to be computed on the GPU by means of an efficient data-parallel kernel. The experimental results reveal the performance of the new eigensolver. Concretely, when applied to the simulation of macromolecules with a few thousands degrees of freedom and the number of eigenpairs to be computed is small to moderate, the new solver outperforms other methods implemented as part of high-performance numerical linear algebra packages for multithreaded architectures.

  9. A fast band–Krylov eigensolver for macromolecular functional motion simulation on multicore architectures and graphics processors

    Energy Technology Data Exchange (ETDEWEB)

    Aliaga, José I., E-mail: aliaga@uji.es [Depto. Ingeniería y Ciencia de Computadores, Universitat Jaume I, Castellón (Spain); Alonso, Pedro [Departamento de Sistemas Informáticos y Computación, Universitat Politècnica de València (Spain); Badía, José M. [Depto. Ingeniería y Ciencia de Computadores, Universitat Jaume I, Castellón (Spain); Chacón, Pablo [Dept. Biological Chemical Physics, Rocasolano Physics and Chemistry Institute, CSIC, Madrid (Spain); Davidović, Davor [Rudjer Bošković Institute, Centar za Informatiku i Računarstvo – CIR, Zagreb (Croatia); López-Blanco, José R. [Dept. Biological Chemical Physics, Rocasolano Physics and Chemistry Institute, CSIC, Madrid (Spain); Quintana-Ortí, Enrique S. [Depto. Ingeniería y Ciencia de Computadores, Universitat Jaume I, Castellón (Spain)

    2016-03-15

    We introduce a new iterative Krylov subspace-based eigensolver for the simulation of macromolecular motions on desktop multithreaded platforms equipped with multicore processors and, possibly, a graphics accelerator (GPU). The method consists of two stages, with the original problem first reduced into a simpler band-structured form by means of a high-performance compute-intensive procedure. This is followed by a memory-intensive but low-cost Krylov iteration, which is off-loaded to be computed on the GPU by means of an efficient data-parallel kernel. The experimental results reveal the performance of the new eigensolver. Concretely, when applied to the simulation of macromolecules with a few thousands degrees of freedom and the number of eigenpairs to be computed is small to moderate, the new solver outperforms other methods implemented as part of high-performance numerical linear algebra packages for multithreaded architectures.

  10. An interaction switch predicts the nested architecture of mutualistic networks.

    Science.gov (United States)

    Zhang, Feng; Hui, Cang; Terblanche, John S

    2011-08-01

    Nested architecture is distinctive in plant-animal mutualistic networks. However, to date an integrative and quantitative explanation has been lacking. It is evident that species often switch their interactive partners in real-world mutualistic networks such as pollination and seed-dispersal networks. By incorporating an interaction switch into a novel multi-population model, we show that the nested architecture rapidly emerges from an initially random network. The model allowing interaction switches between partner species produced predictions which fit remarkably well with observations from 81 empirical networks. Thus, the nested architecture in mutualistic networks could be an intrinsic physical structure of dynamic networks and the interaction switch is likely a key ecological process that results in nestedness of real-world networks. Identifying the biological processes responsible for network structures is thus crucial for understanding the architecture of ecological networks. © 2011 Blackwell Publishing Ltd/CNRS.

  11. Self-powered information measuring wireless networks using the distribution of tasks within multicore processors

    Science.gov (United States)

    Zhuravska, Iryna M.; Koretska, Oleksandra O.; Musiyenko, Maksym P.; Surtel, Wojciech; Assembay, Azat; Kovalev, Vladimir; Tleshova, Akmaral

    2017-08-01

    The article contains basic approaches to develop the self-powered information measuring wireless networks (SPIM-WN) using the distribution of tasks within multicore processors critical applying based on the interaction of movable components - as in the direction of data transmission as wireless transfer of energy coming from polymetric sensors. Base mathematic model of scheduling tasks within multiprocessor systems was modernized to schedule and allocate tasks between cores of one-crystal computer (SoC) to increase energy efficiency SPIM-WN objects.

  12. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  13. System, methods and apparatus for program optimization for multi-threaded processor architectures

    Science.gov (United States)

    Bastoul, Cedric; Lethin, Richard A; Leung, Allen K; Meister, Benoit J; Szilagyi, Peter; Vasilache, Nicolas T; Wohlford, David E

    2015-01-06

    Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

  14. Media processors using a new microsystem architecture designed for the Internet era

    Science.gov (United States)

    Wyland, David C.

    1999-12-01

    The demands of digital image processing, communications and multimedia applications are growing more rapidly than traditional design methods can fulfill them. Previously, only custom hardware designs could provide the performance required to meet the demands of these applications. However, hardware design has reached a crisis point. Hardware design can no longer deliver a product with the required performance and cost in a reasonable time for a reasonable risk. Software based designs running on conventional processors can deliver working designs in a reasonable time and with low risk but cannot meet the performance requirements. What is needed is a media processing approach that combines very high performance, a simple programming model, complete programmability, short time to market and scalability. The Universal Micro System (UMS) is a solution to these problems. The UMS is a completely programmable (including I/O) system on a chip that combines hardware performance with the fast time to market, low cost and low risk of software designs.

  15. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...

  16. HyperForest: A high performance multi-processor architecture for real-time intelligent systems

    Energy Technology Data Exchange (ETDEWEB)

    Garcia, P. Jr.; Rebeil, J.P. [Sandia National Labs., Albuquerque, NM (United States); Pollard, H. [Univ. of New Mexico, Albuquerque, NM (United States). Electrical Engineering and Computer Engineering Dept.

    1997-04-01

    Intelligent Systems are characterized by the intensive use of computer power. The computer revolution of the last few years is what has made possible the development of the first generation of Intelligent Systems. Software for second generation Intelligent Systems will be more complex and will require more powerful computing engines in order to meet real-time constraints imposed by new robots, sensors, and applications. A multiprocessor architecture was developed that merges the advantages of message-passing and shared-memory structures: expendability and real-time compliance. The HyperForest architecture will provide an expandable real-time computing platform for computationally intensive Intelligent Systems and open the doors for the application of these systems to more complex tasks in environmental restoration and cleanup projects, flexible manufacturing systems, and DOE`s own production and disassembly activities.

  17. A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors

    Science.gov (United States)

    Nguyen, Kayla; Zheng, Jason; He, Yutao; Shah, Biren

    2010-01-01

    Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.

  18. Transportable GPU (General Processor Units) chip set technology for standard computer architectures

    Science.gov (United States)

    Fosdick, R. E.; Denison, H. C.

    1982-11-01

    The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

  19. Establishment of a Spaceport Network Architecture

    Science.gov (United States)

    Larson, Wiley J.; Gill, Tracy R.; Mueller, Robert P.; Brink, Jeffrey S.

    2012-01-01

    Since the beginning of the space age, the main actors in space exploration have been governmental agencies, enabling a privileged access to space, but with very restricted and rare missions. The last decade has seen the rise of space tourism, and the founding of ambitious private space mining companies, showing the beginnings of a new exploration era, that is based on a more generalized and regular access to space and which is not limited to the Earth's vicinity. However, the cost of launching sufficient mass into orbit to sustain these inspiring challenges is prohibitive, and the necessary infrastructures to support these missions is still lacking. To provide easy and affordable access into orbital and deep space destinations, there is the need to create a network of spaceports via specific waypoint locations coupled with the use of natural resources, or In Situ Resource Utilization (ISRU), to provide a more economical solution. As part of the International Space University Space Studies Program 2012, the international and intercultural team of Operations and Service Infrastructure for Space (OASIS) proposes an interdisciplinary answer to the problem of economical space access and transportation. This paper presents a summary of a detailed report [1] of the different phases of a project for developing a network of spaceports throughout the Solar System in a timeframe of 50 years. The requirements, functions, critical technologies and mission architecture of this network of spaceports are outlined in a roadmap of the important steps and phases. The economic and financial aspects are emphasized in order to allow a sustainable development of the network in a public-private partnership via the formation of an International Spaceport Authority (ISPA). The approach includes engineering, scientific, financial, legal, policy, and societal aspects. Team OASIS intends to provide guidelines to make the development of space transportation via a spaceports logistics network

  20. MSAT signalling and network management architectures

    Science.gov (United States)

    Garland, Peter; Keelty, J. Malcolm

    1989-01-01

    Spar Aerospace has been active in the design and definition of Mobile Satellite Systems since the mid 1970's. In work sponsored by the Canadian Department of Communications, various payload configurations have evolved. In addressing the payload configuration, the requirements of the mobile user, the service provider and the satellite operator have always been the most important consideration. The current Spar 11 beam satellite design is reviewed, and its capabilities to provide flexibility and potential for network growth within the WARC87 allocations are explored. To enable the full capabilities of the payload to be realized, a large amount of ground based Switching and Network Management infrastructure will be required, when space segment becomes available. Early indications were that a single custom designed Demand Assignment Multiple Access (DAMA) switch should be implemented to provide efficient use of the space segment. As MSAT has evolved into a multiple service concept, supporting many service providers, this architecture should be reviewed. Some possible signalling and Network Management solutions are explored.

  1. NEBULAS a high performance data-driven event-building architecture based on an asynchronous self-routing packet-switching network

    CERN Document Server

    Christiansen, J; Letheren, M F; Marchioro, A; Tenhunen, H; Nummela, A; Nurmi, J; Gomes, P; Mandjavidze, I D; CERN. Geneva. Detector Research and Development Committee

    1992-01-01

    We propose a new approach to event building in future high rate experiments such as those at the LHC. We use a real-time, hierarchical event filtering paradigm based on pipelined triggering and data buffering at level 1, followed by farms of several hundreds of independent processors operating at level 2 and level 3. In view of the uncertainty in the rates and event sizes expected after the first level trigger in LHC experiments, it is important that data acquisition architectures can be open- endedly scaled to handle higher global bandwidths and accommodate more processors. We propose to apply the principle of self-routing packet-switching networks (currently under industrial development for telecommunications and multi-processor applications) to event building. We plan to implement a conceptually simple, distributed, asynchronous, data-driven, scalable, bottleneck-free architecture. An important feature of the architecture is that it can satisfy the data acquisition system's performance requirements using o...

  2. WDM-PON Architecture for FTTx Networks

    Science.gov (United States)

    Iannone, E.; Franco, P.; Santoni, S.

    Broadband services for residential users in European countries have until now largely relied on xDSL technologies, while FTTx technologies have been mainly exploited in Asia and North America. The increasing bandwidth demand and the growing penetration of new services are pushing the deployment of optical access networks, and major European operators are now announcing FTTx projects. While FTTH is recognized as the target solution to bring broadband services to residential users, the identification of an FTTx evolutionary path able to seamlessly migrate to FTTH is key to enabling a massive deployment, easing the huge investments needed. WDM-PON architecture is an interesting solution that is able to accommodate the strategic need of building a new fiber-based access infrastructure with the possibility of adapting investments to actual demands and evolving to FTTH without requiring further interventions on fiber infrastructures.

  3. A research on the application of software defined networking in satellite network architecture

    Science.gov (United States)

    Song, Huan; Chen, Jinqiang; Cao, Suzhi; Cui, Dandan; Li, Tong; Su, Yuxing

    2017-10-01

    Software defined network is a new type of network architecture, which decouples control plane and data plane of traditional network, has the feature of flexible configurations and is a direction of the next generation terrestrial Internet development. Satellite network is an important part of the space-ground integrated information network, while the traditional satellite network has the disadvantages of difficult network topology maintenance and slow configuration. The application of SDN technology in satellite network can solve these problems that traditional satellite network faces. At present, the research on the application of SDN technology in satellite network is still in the stage of preliminary study. In this paper, we start with introducing the SDN technology and satellite network architecture. Then we mainly introduce software defined satellite network architecture, as well as the comparison of different software defined satellite network architecture and satellite network virtualization. Finally, the present research status and development trend of SDN technology in satellite network are analyzed.

  4. TUTORIAL: Neural blackboard architectures: the realization of compositionality and systematicity in neural networks

    Science.gov (United States)

    de Kamps, Marc; van der Velde, Frank

    2006-03-01

    In this paper, we will first introduce the notions of systematicity and combinatorial productivity and we will argue that these notions are essential for human cognition and probably for every agent that needs to be able to deal with novel, unexpected situations in a complex environment. Agents that use compositional representations are faced with the so-called binding problem and the question of how to create neural network architectures that can deal with it is essential for understanding higher level cognition. Moreover, an architecture that can solve this problem is likely to scale better with problem size than other neural network architectures. Then, we will discuss object-based attention. The influence of spatial attention is well known, but there is solid evidence for object-based attention as well. We will discuss experiments that demonstrate object-based attention and will discuss a model that can explain the data of these experiments very well. The model strongly suggests that this mode of attention provides a neural basis for parallel search. Next, we will show a model for binding in visual cortex. This model is based on a so-called neural blackboard architecture, where higher cortical areas act as processors, specialized for specific features of a visual stimulus, and lower visual areas act as a blackboard for communication between these processors. This implies that lower visual areas are involved in more than bottom-up visual processing, something which already was apparent from the large number of recurrent connections from higher to lower visual areas. This model identifies a specific role for these feedback connections. Finally, we will discuss the experimental evidence that exists for this architecture. .

  5. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  6. High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors

    Science.gov (United States)

    NguyenKobayashi, Kayla; Zheng, Jason X.; He, Yutao; Shah, Biren N.

    2011-01-01

    Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the

  7. Transformation of legacy network management system to service oriented architecture

    Science.gov (United States)

    Sathyan, Jithesh; Shenoy, Krishnananda

    2007-09-01

    Service providers today are facing the challenge of operating and maintaining multiple networks, based on multiple technologies. Network Management System (NMS) solutions are being used to manage these networks. However the NMS is tightly coupled with Element or the Core network components. Hence there are multiple NMS solutions for heterogeneous networks. Current network management solutions are targeted at a variety of independent networks. The wide spread popularity of IP Multimedia Subsystem (IMS) is a clear indication that all of these independent networks will be integrated into a single IP-based infrastructure referred to as Next Generation Networks (NGN) in the near future. The services, network architectures and traffic pattern in NGN will dramatically differ from the current networks. The heterogeneity and complexity in NGN including concepts like Fixed Mobile Convergence will bring a number of challenges to network management. The high degree of complexity accompanying the network element technology necessitates network management systems (NMS) which can utilize this technology to provide more service interfaces while hiding the inherent complexity. As operators begin to add new networks and expand existing networks to support new technologies and products, the necessity of scalable, flexible and functionally rich NMS systems arises. Another important factor influencing NMS architecture is mergers and acquisitions among the key vendors. Ease of integration is a key impediment in the traditional hierarchical NMS architecture. These requirements trigger the need for an architectural framework that will address the NGNM (Next Generation Network Management) issues seamlessly. This paper presents a unique perspective of bringing service orientated architecture (SOA) to legacy network management systems (NMS). It advocates a staged approach in transforming a legacy NMS to SOA. The architecture at each stage is detailed along with the technical advantages and

  8. Neuron splitting in compute-bound parallel network simulations enables runtime scaling with twice as many processors.

    Science.gov (United States)

    Hines, Michael L; Eichner, Hubert; Schürmann, Felix

    2008-08-01

    Neuron tree topology equations can be split into two subtrees and solved on different processors with no change in accuracy, stability, or computational effort; communication costs involve only sending and receiving two double precision values by each subtree at each time step. Splitting cells is useful in attaining load balance in neural network simulations, especially when there is a wide range of cell sizes and the number of cells is about the same as the number of processors. For compute-bound simulations load balance results in almost ideal runtime scaling. Application of the cell splitting method to two published network models exhibits good runtime scaling on twice as many processors as could be effectively used with whole-cell balancing.

  9. Greening radio access networks using distributed base station architectures

    DEFF Research Database (Denmark)

    Kardaras, Georgios; Soler, José; Dittmann, Lars

    2010-01-01

    . However besides this, increasing energy efficiency represents a key factor for reducing operating expenses and deploying cost effective mobile networks. This paper presents how distributed base station architectures can contribute in greening radio access networks. More specifically, the advantages...... energy saving. Different subsystems have to be coordinated real-time and intelligent network nodes supporting complicated functionalities are necessary. Distributed base station architectures are ideal for this purpose mainly because of their high degree of configurability and self...

  10. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  11. Advances in network systems architectures, security, and applications

    CERN Document Server

    Awad, Ali; Furtak, Janusz; Legierski, Jarosław

    2017-01-01

    This book provides the reader with a comprehensive selection of cutting–edge algorithms, technologies, and applications. The volume offers new insights into a range of fundamentally important topics in network architectures, network security, and network applications. It serves as a reference for researchers and practitioners by featuring research contributions exemplifying research done in the field of network systems. In addition, the book highlights several key topics in both theoretical and practical aspects of networking. These include wireless sensor networks, performance of TCP connections in mobile networks, photonic data transport networks, security policies, credentials management, data encryption for network transmission, risk management, live TV services, and multicore energy harvesting in distributed systems. .

  12. Space Mobile Network: A Near Earth Communication and Navigation Architecture

    Science.gov (United States)

    Israel, Dave J.; Heckler, Greg; Menrad, Robert J.

    2016-01-01

    This paper describes a Space Mobile Network architecture, the result of a recently completed NASA study exploring architectural concepts to produce a vision for the future Near Earth communications and navigation systems. The Space Mobile Network (SMN) incorporates technologies, such as Disruption Tolerant Networking (DTN) and optical communications, and new operations concepts, such as User Initiated Services, to provide user services analogous to a terrestrial smartphone user. The paper will describe the SMN Architecture, envisioned future operations concepts, opportunities for industry and international collaboration and interoperability, and technology development areas and goals.

  13. Security Aspects of an Enterprise-Wide Network Architecture.

    Science.gov (United States)

    Loew, Robert; Stengel, Ingo; Bleimann, Udo; McDonald, Aidan

    1999-01-01

    Presents an overview of two projects that concern local area networks and the common point between networks as they relate to network security. Discusses security architectures based on firewall components, packet filters, application gateways, security-management components, an intranet solution, user registration by Web form, and requests for…

  14. A concrete example of a Personal Network architecture

    NARCIS (Netherlands)

    Hartog, F.T.H. den; Peeters, M.E.

    2006-01-01

    A Personal Network (PN) is created when the various private networks of a single user are always seamlessly interconnected, despite the mobility of the user. To realize this vision we have designed an architecture of a simple, concrete example of such a PN. It consists of just a home network and a

  15. An Architecture for Cooperative Localization in Underwater Acoustic Networks

    Science.gov (United States)

    2015-10-24

    An Architecture for Cooperative Localization in Underwater Acoustic Networks ∗ Jeffrey M. Walls University of Michigan Ann Arbor, Michigan jmwalls...umich.edu Ryan M. Eustice University of Michigan Ann Arbor, Michigan eustice@umich.edu ABSTRACT This paper outlines an architecture for underwater...underwater navigation framework. In this paper, we outline the design, implemen- tation, and deployment of a system architecture for multiple vehicle

  16. Wireless sensor networks architectures and protocols

    CERN Document Server

    Callaway, Jr, Edgar H

    2003-01-01

    Introduction to Wireless Sensor NetworksApplications and MotivationNetwork Performance ObjectivesContributions of this BookOrganization of this BookThe Development of Wireless Sensor NetworksEarly Wireless NetworksWireless Data NetworksWireless Sensor and Related NetworksConclusionThe Physical LayerSome Physical Layer ExamplesA Practical Physical Layer for Wireless Sensor NetworksSimulations and ResultsConclusionThe Data Link LayerMedium Access Control TechniquesThe Mediation DeviceSystem Analysis and SimulationConclusionThe Network LayerSome Network Design ExamplesA Wireless Sensor Network De

  17. The Hi-Ring architecture for datacentre networks

    DEFF Research Database (Denmark)

    Galili, Michael; Kamchevska, Valerija; Ding, Yunhong

    2016-01-01

    This paper summarizes recent work on a hierarchical ring-based network architecture (Hi-Ring) for datacentre and short-range applications. The architecture allows leveraging benefits of optical switching technologies while maintaining a high level of connection granularity. We discuss results...

  18. A Reference Architecture for Network-Centric Information Systems

    National Research Council Canada - National Science Library

    Renner, Scott; Schaefer, Ronald

    2003-01-01

    This paper presents the "C2 Enterprise Reference Architecture" (C2ERA), which is a new technical concept of operations for building information systems better suited to the Network-Centric Warfare (NCW) environment...

  19. A universal quantum information processor for scalable quantum communication and networks.

    Science.gov (United States)

    Yang, Xihua; Xue, Bolin; Zhang, Junxiang; Zhu, Shiyao

    2014-10-15

    Entanglement provides an essential resource for quantum computation, quantum communication, and quantum networks. How to conveniently and efficiently realize the generation, distribution, storage, retrieval, and control of multipartite entanglement is the basic requirement for realistic quantum information processing. Here, we present a theoretical proposal to efficiently and conveniently achieve a universal quantum information processor (QIP) via atomic coherence in an atomic ensemble. The atomic coherence, produced through electromagnetically induced transparency (EIT) in the Λ-type configuration, acts as the QIP and has full functions of quantum beam splitter, quantum frequency converter, quantum entangler, and quantum repeater. By employing EIT-based nondegenerate four-wave mixing processes, the generation, exchange, distribution, and manipulation of light-light, atom-light, and atom-atom multipartite entanglement can be efficiently and flexibly achieved in a deterministic way with only coherent light fields. This method greatly facilitates the operations in quantum information processing, and holds promising applications in realistic scalable quantum communication and quantum networks.

  20. A NOVEL ARCHITECTURE FOR SDN-BASED CELLULAR NETWORK

    OpenAIRE

    Md. Humayun Kabir

    2014-01-01

    In this paper, we propose a novel SDN-based cellular network architecture that will be able to utilize the opportunities of centralized administration of today’s emerging mobile network. Our proposed architecture would not depend on a single controller, rather it divides the whole cellular area into clusters, and each cluster is controlled by a separate controller. A number of controller services are provided on top of each controller to manage all the major functionalities of the...

  1. Fast Decision Algorithms in Low-Power Embedded Processors for Quality-of-Service Based Connectivity of Mobile Sensors in Heterogeneous Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Juan M. Sánchez-Pérez

    2012-02-01

    Full Text Available When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration.

  2. Fast decision algorithms in low-power embedded processors for quality-of-service based connectivity of mobile sensors in heterogeneous wireless sensor networks.

    Science.gov (United States)

    Jaraíz-Simón, María D; Gómez-Pulido, Juan A; Vega-Rodríguez, Miguel A; Sánchez-Pérez, Juan M

    2012-01-01

    When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration.

  3. Designing Networked Energy Infrastructures with Architectural Flexibility

    NARCIS (Netherlands)

    Melese, Y.G.; Heijnen, P.W.; Stikkelman, R.M.

    2014-01-01

    Development of networked energy infrastructures (like gas pipe networks), generally requires a significant amount of capital investment under resources, market and institutional uncertainties. Several independent suppliers and consumers are to be connected into these networks. However, the actual

  4. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  5. Using overlay network architectures for scalable video distribution

    Science.gov (United States)

    Patrikakis, Charalampos Z.; Despotopoulos, Yannis; Fafali, Paraskevi; Cha, Jihun; Kim, Kyuheon

    2004-11-01

    Within the last years, the enormous growth of Internet based communication as well as the rapid increase of available processing power has lead to the widespread use of multimedia streaming as a means to convey information. This work aims at providing an open architecture designed to support scalable streaming to a large number of clients using application layer multicast. The architecture is based on media relay nodes that can be deployed transparently to any existing media distribution scheme, which can support media streamed using the RTP and RTSP protocols. The architecture is based on overlay networks at application level, featuring rate adaptation mechanisms for responding to network congestion.

  6. Public Safety Broadband Network Architecture Description

    Science.gov (United States)

    2013-08-01

    through roaming agreements o Clearinghouse IP eXchange o Satellite hub station o VSAT terminals o Transport network (backhaul) o Lawful intercept...Mobile Network VPN Virtual Private Network VQiPS Video Quality in Public Safety VSAT Very Small Aperture Terminal WAN Wide Area Network Wi-Fi

  7. Investigating the effectiveness of many-core network processors for high performance cyber protection systems. Part I, FY2011.

    Energy Technology Data Exchange (ETDEWEB)

    Wheeler, Kyle Bruce; Naegle, John Hunt; Wright, Brian J.; Benner, Robert E., Jr.; Shelburg, Jeffrey Scott; Pearson, David Benjamin; Johnson, Joshua Alan; Onunkwo, Uzoma A.; Zage, David John; Patel, Jay S.

    2011-09-01

    This report documents our first year efforts to address the use of many-core processors for high performance cyber protection. As the demands grow for higher bandwidth (beyond 1 Gbits/sec) on network connections, the need to provide faster and more efficient solution to cyber security grows. Fortunately, in recent years, the development of many-core network processors have seen increased interest. Prior working experiences with many-core processors have led us to investigate its effectiveness for cyber protection tools, with particular emphasis on high performance firewalls. Although advanced algorithms for smarter cyber protection of high-speed network traffic are being developed, these advanced analysis techniques require significantly more computational capabilities than static techniques. Moreover, many locations where cyber protections are deployed have limited power, space and cooling resources. This makes the use of traditionally large computing systems impractical for the front-end systems that process large network streams; hence, the drive for this study which could potentially yield a highly reconfigurable and rapidly scalable solution.

  8. Software architecture for hybrid electrical/optical data center network

    DEFF Research Database (Denmark)

    Mehmeri, Victor; Vegas Olmos, Juan José; Tafur Monroy, Idelfonso

    2016-01-01

    This paper presents hardware and software architecture based on Software-Defined Networking (SDN) paradigm and OpenFlow/NETCONF protocols for enabling topology management of hybrid electrical/optical switching data center networks. In particular, a development on top of SDN open-source controller...

  9. Architecture for Cognitive Networking within NASAs Future Space Communications Infrastructure

    Science.gov (United States)

    Clark, Gilbert J., III; Eddy, Wesley M.; Johnson, Sandra K.; Barnes, James; Brooks, David

    2016-01-01

    Future space mission concepts and designs pose many networking challenges for command, telemetry, and science data applications with diverse end-to-end data delivery needs. For future end-to-end architecture designs, a key challenge is meeting expected application quality of service requirements for multiple simultaneous mission data flows with options to use diverse onboard local data buses, commercial ground networks, and multiple satellite relay constellations in LEO, MEO, GEO, or even deep space relay links. Effectively utilizing a complex network topology requires orchestration and direction that spans the many discrete, individually addressable computer systems, which cause them to act in concert to achieve the overall network goals. The system must be intelligent enough to not only function under nominal conditions, but also adapt to unexpected situations, and reorganize or adapt to perform roles not originally intended for the system or explicitly programmed. This paper describes architecture features of cognitive networking within the future NASA space communications infrastructure, and interacting with the legacy systems and infrastructure in the meantime. The paper begins by discussing the need for increased automation, including inter-system collaboration. This discussion motivates the features of an architecture including cognitive networking for future missions and relays, interoperating with both existing endpoint-based networking models and emerging information-centric models. From this basis, we discuss progress on a proof-of-concept implementation of this architecture as a cognitive networking on-orbit application on the SCaN Testbed attached to the International Space Station.

  10. Architecture for Cognitive Networking within NASA's Future Space Communications Infrastructure

    Science.gov (United States)

    Clark, Gilbert; Eddy, Wesley M.; Johnson, Sandra K.; Barnes, James; Brooks, David

    2016-01-01

    Future space mission concepts and designs pose many networking challenges for command, telemetry, and science data applications with diverse end-to-end data delivery needs. For future end-to-end architecture designs, a key challenge is meeting expected application quality of service requirements for multiple simultaneous mission data flows with options to use diverse onboard local data buses, commercial ground networks, and multiple satellite relay constellations in LEO, GEO, MEO, or even deep space relay links. Effectively utilizing a complex network topology requires orchestration and direction that spans the many discrete, individually addressable computer systems, which cause them to act in concert to achieve the overall network goals. The system must be intelligent enough to not only function under nominal conditions, but also adapt to unexpected situations, and reorganize or adapt to perform roles not originally intended for the system or explicitly programmed. This paper describes an architecture enabling the development and deployment of cognitive networking capabilities into the envisioned future NASA space communications infrastructure. We begin by discussing the need for increased automation, including inter-system discovery and collaboration. This discussion frames the requirements for an architecture supporting cognitive networking for future missions and relays, including both existing endpoint-based networking models and emerging information-centric models. From this basis, we discuss progress on a proof-of-concept implementation of this architecture, and results of implementation and initial testing of a cognitive networking on-orbit application on the SCaN Testbed attached to the International Space Station.

  11. Designing network on-chip architectures in the nanoscale era

    CERN Document Server

    Flich, Jose

    2010-01-01

    Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent p

  12. The architecture of a network level intrusion detection system

    Energy Technology Data Exchange (ETDEWEB)

    Heady, R.; Luger, G.; Maccabe, A.; Servilla, M. [New Mexico Univ., Albuquerque, NM (United States). Dept. of Computer Science

    1990-08-15

    This paper presents the preliminary architecture of a network level intrusion detection system. The proposed system will monitor base level information in network packets (source, destination, packet size, and time), learning the normal patterns and announcing anomalies as they occur. The goal of this research is to determine the applicability of current intrusion detection technology to the detection of network level intrusions. In particular, the authors are investigating the possibility of using this technology to detect and react to worm programs.

  13. Efficient VLSI Architecture for Training Radial Basis Function Networks

    Science.gov (United States)

    Fan, Zhe-Cheng; Hwang, Wen-Jyi

    2013-01-01

    This paper presents a novel VLSI architecture for the training of radial basis function (RBF) networks. The architecture contains the circuits for fuzzy C-means (FCM) and the recursive Least Mean Square (LMS) operations. The FCM circuit is designed for the training of centers in the hidden layer of the RBF network. The recursive LMS circuit is adopted for the training of connecting weights in the output layer. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for real-time training and classification. Experimental results reveal that the proposed RBF architecture is an effective alternative for applications where fast and efficient RBF training is desired. PMID:23519346

  14. Security Policy for a Generic Space Exploration Communication Network Architecture

    Science.gov (United States)

    Ivancic, William D.; Sheehe, Charles J.; Vaden, Karl R.

    2016-01-01

    This document is one of three. It describes various security mechanisms and a security policy profile for a generic space-based communication architecture. Two other documents accompany this document- an Operations Concept (OpsCon) and a communication architecture document. The OpsCon should be read first followed by the security policy profile described by this document and then the architecture document. The overall goal is to design a generic space exploration communication network architecture that is affordable, deployable, maintainable, securable, evolvable, reliable, and adaptable. The architecture should also require limited reconfiguration throughout system development and deployment. System deployment includes subsystem development in a factory setting, system integration in a laboratory setting, launch preparation, launch, and deployment and operation in space.

  15. Towards a Security Architecture for Vehicular Ad Hoc Networks

    OpenAIRE

    Plößl, Klaus; Nowey, Thomas; Mletzko, Christian

    2006-01-01

    Vehicular ad hoc networks (VANETs) have the potential to increase road safety and comfort. Especially because of the road safety functions, there is a strong demand for security in VANETs. After defining three application categories the paper outlines main security and privacy requirements in VANETs. Next, a security architecture for VANETs (SAV) is proposed that strives to satisfy the requirements. To find mechanisms applicable in the architecture a survey of existing mechanisms is given.

  16. Architectural transformations in network services and distributed systems

    CERN Document Server

    Luntovskyy, Andriy

    2017-01-01

    With the given work we decided to help not only the readers but ourselves, as the professionals who actively involved in the networking branch, with understanding the trends that have developed in recent two decades in distributed systems and networks. Important architecture transformations of distributed systems have been examined. The examples of new architectural solutions are discussed. Content Periodization of service development Energy efficiency Architectural transformations in Distributed Systems Clustering and Parallel Computing, performance models Cloud Computing, RAICs, Virtualization, SDN Smart Grid, Internet of Things, Fog Computing Mobile Communication from LTE to 5G, DIDO, SAT-based systems Data Security Guaranteeing Distributed Systems Target Groups Students in EE and IT of universities and (dual) technical high schools Graduated engineers as well as teaching staff About the Authors Andriy Luntovskyy provides classes on networks, mobile communication, software technology, distributed systems, ...

  17. Network architectural conditions for prominent and robust stochastic oscillations

    Science.gov (United States)

    Joo, Jaewook; Choi, Jinmyung

    2012-02-01

    Understanding relationship between noisy dynamics and biological network architecture is a fundamentally important question, particularly in order to elucidate how cells encode and process information. We analytically and numerically investigate general network architectural conditions that are necessary to generate stochastic amplified and coherent oscillations. We enumerate all possible topologies of coupled negative feedbacks in the underlying biochemical networks with three components, negative feedback loops, and mass action kinetics. Using the linear noise approximation to analytically obtain the time-dependent solution of the master equation and derive the algebraic expression of power spectra, we find that (a) all networks with coupled negative feedbacks are capable of generating stochastic amplified and coherent oscillations; (b) networks with a single negative feedback are better stochastic amplified and coherent oscillators than those with multiple coupled negative feedbacks; (c) multiple timescale difference among the kinetic rate constants is required for stochastic amplified and coherent oscillations.

  18. Design concepts for a virtualizable embedded MPSoC architecture enabling virtualization in embedded multi-processor systems

    CERN Document Server

    Biedermann, Alexander

    2014-01-01

    Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concepts for the design of energy aware systems, self-healing systems as well as parallelized systems. For the latter, the novel so-called Agile Processing scheme is introduced by the author, which enables a seamless transition between sequential and parallel execution schemes. The design of such virtualizable systems is further aided by introduction

  19. Convolutional neural network architectures for predicting DNA–protein binding

    Science.gov (United States)

    Zeng, Haoyang; Edwards, Matthew D.; Liu, Ge; Gifford, David K.

    2016-01-01

    Motivation: Convolutional neural networks (CNN) have outperformed conventional methods in modeling the sequence specificity of DNA–protein binding. Yet inappropriate CNN architectures can yield poorer performance than simpler models. Thus an in-depth understanding of how to match CNN architecture to a given task is needed to fully harness the power of CNNs for computational biology applications. Results: We present a systematic exploration of CNN architectures for predicting DNA sequence binding using a large compendium of transcription factor datasets. We identify the best-performing architectures by varying CNN width, depth and pooling designs. We find that adding convolutional kernels to a network is important for motif-based tasks. We show the benefits of CNNs in learning rich higher-order sequence features, such as secondary motifs and local sequence context, by comparing network performance on multiple modeling tasks ranging in difficulty. We also demonstrate how careful construction of sequence benchmark datasets, using approaches that control potentially confounding effects like positional or motif strength bias, is critical in making fair comparisons between competing methods. We explore how to establish the sufficiency of training data for these learning tasks, and we have created a flexible cloud-based framework that permits the rapid exploration of alternative neural network architectures for problems in computational biology. Availability and Implementation: All the models analyzed are available at http://cnn.csail.mit.edu. Contact: gifford@mit.edu Supplementary information: Supplementary data are available at Bioinformatics online. PMID:27307608

  20. Convolutional neural network architectures for predicting DNA-protein binding.

    Science.gov (United States)

    Zeng, Haoyang; Edwards, Matthew D; Liu, Ge; Gifford, David K

    2016-06-15

    Convolutional neural networks (CNN) have outperformed conventional methods in modeling the sequence specificity of DNA-protein binding. Yet inappropriate CNN architectures can yield poorer performance than simpler models. Thus an in-depth understanding of how to match CNN architecture to a given task is needed to fully harness the power of CNNs for computational biology applications. We present a systematic exploration of CNN architectures for predicting DNA sequence binding using a large compendium of transcription factor datasets. We identify the best-performing architectures by varying CNN width, depth and pooling designs. We find that adding convolutional kernels to a network is important for motif-based tasks. We show the benefits of CNNs in learning rich higher-order sequence features, such as secondary motifs and local sequence context, by comparing network performance on multiple modeling tasks ranging in difficulty. We also demonstrate how careful construction of sequence benchmark datasets, using approaches that control potentially confounding effects like positional or motif strength bias, is critical in making fair comparisons between competing methods. We explore how to establish the sufficiency of training data for these learning tasks, and we have created a flexible cloud-based framework that permits the rapid exploration of alternative neural network architectures for problems in computational biology. All the models analyzed are available at http://cnn.csail.mit.edu gifford@mit.edu Supplementary data are available at Bioinformatics online. © The Author 2016. Published by Oxford University Press.

  1. Embedded Data Processor and Portable Computer Technology testbeds

    Science.gov (United States)

    Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

    1993-01-01

    Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

  2. Robust quantum network architectures and topologies for entanglement distribution

    Science.gov (United States)

    Das, Siddhartha; Khatri, Sumeet; Dowling, Jonathan P.

    2018-01-01

    Entanglement distribution is a prerequisite for several important quantum information processing and computing tasks, such as quantum teleportation, quantum key distribution, and distributed quantum computing. In this work, we focus on two-dimensional quantum networks based on optical quantum technologies using dual-rail photonic qubits for the building of a fail-safe quantum internet. We lay out a quantum network architecture for entanglement distribution between distant parties using a Bravais lattice topology, with the technological constraint that quantum repeaters equipped with quantum memories are not easily accessible. We provide a robust protocol for simultaneous entanglement distribution between two distant groups of parties on this network. We also discuss a memory-based quantum network architecture that can be implemented on networks with an arbitrary topology. We examine networks with bow-tie lattice and Archimedean lattice topologies and use percolation theory to quantify the robustness of the networks. In particular, we provide figures of merit on the loss parameter of the optical medium that depend only on the topology of the network and quantify the robustness of the network against intermittent photon loss and intermittent failure of nodes. These figures of merit can be used to compare the robustness of different network topologies in order to determine the best topology in a given real-world scenario, which is critical in the realization of the quantum internet.

  3. Towards blueprints for network architecture, biophysical dynamics and signal transduction.

    Science.gov (United States)

    Coombes, Stephen; Doiron, Brent; Josić, Kresimir; Shea-Brown, Eric

    2006-12-15

    We review mathematical aspects of biophysical dynamics, signal transduction and network architecture that have been used to uncover functionally significant relations between the dynamics of single neurons and the networks they compose. We focus on examples that combine insights from these three areas to expand our understanding of systems neuroscience. These range from single neuron coding to models of decision making and electrosensory discrimination by networks and populations and also coincidence detection in pairs of dendrites and dynamics of large networks of excitable dendritic spines. We conclude by describing some of the challenges that lie ahead as the applied mathematics community seeks to provide the tools which will ultimately underpin systems neuroscience.

  4. Designing 2D and 3D network-on-chip architectures

    CERN Document Server

    Tatas, Konstantinos; Soudris, Dimitrios; Jantsch, Axel

    2014-01-01

    This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect.  It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools.  Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliabilty.  Case studies are used to illuminate new design methodologies.  ·         Describes essential theory, practice and state-of-the-art applications of 2D and 3D Network-on-Chip interconnect; ·         Enables readers to exploit parallelism in processor architecture, with interconnect design that is efficient in terms of energy and performance; ·         Covers topics not available in other books, such as NoC and distributed memory organization, dynamic memory management and abstract data type support in many-core platforms, and distributed hierarchical power management.

  5. A cache architecture for counting Bloom filters : Theory and application

    NARCIS (Netherlands)

    Ahmadi, M.; Wong, S.

    2011-01-01

    Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, for example, utilizing multilevel memory hierarchies, special hardware architectures, and hardware threading. In this paper, we

  6. Architecture Analysis of an FPGA-Based Hopfield Neural Network

    Directory of Open Access Journals (Sweden)

    Miguel Angelo de Abreu de Sousa

    2014-01-01

    Full Text Available Interconnections between electronic circuits and neural computation have been a strongly researched topic in the machine learning field in order to approach several practical requirements, including decreasing training and operation times in high performance applications and reducing cost, size, and energy consumption for autonomous or embedded developments. Field programmable gate array (FPGA hardware shows some inherent features typically associated with neural networks, such as, parallel processing, modular executions, and dynamic adaptation, and works on different types of FPGA-based neural networks were presented in recent years. This paper aims to address different aspects of architectural characteristics analysis on a Hopfield Neural Network implemented in FPGA, such as maximum operating frequency and chip-area occupancy according to the network capacity. Also, the FPGA implementation methodology, which does not employ multipliers in the architecture developed for the Hopfield neural model, is presented, in detail.

  7. Entanglement in a Quantum Annealing Processor

    Science.gov (United States)

    Lanting, T.; Przybysz, A. J.; Smirnov, A. Yu.; Spedalieri, F. M.; Amin, M. H.; Berkley, A. J.; Harris, R.; Altomare, F.; Boixo, S.; Bunyk, P.; Dickson, N.; Enderud, C.; Hilton, J. P.; Hoskinson, E.; Johnson, M. W.; Ladizinsky, E.; Ladizinsky, N.; Neufeld, R.; Oh, T.; Perminov, I.; Rich, C.; Thom, M. C.; Tolkacheva, E.; Uchaikin, S.; Wilson, A. B.; Rose, G.

    2014-04-01

    Entanglement lies at the core of quantum algorithms designed to solve problems that are intractable by classical approaches. One such algorithm, quantum annealing (QA), provides a promising path to a practical quantum processor. We have built a series of architecturally scalable QA processors consisting of networks of manufactured interacting spins (qubits). Here, we use qubit tunneling spectroscopy to measure the energy eigenspectrum of two- and eight-qubit systems within one such processor, demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits become entangled and entanglement persists even as these systems reach equilibrium with a thermal environment. Our results provide an encouraging sign that QA is a viable technology for large-scale quantum computing.

  8. Management issues in multilayered network architectures

    Science.gov (United States)

    Piergigli, Mauro; Vercelli, Roberto; Zucchinali, A.

    1996-12-01

    The importance of managing networks and services is finally being accepted by both operators/service providers and HW/SW manufacturers. Standards are thus coming for managing solutions based on any new emerging technology. However standards and commercial solutions have different level of completeness and performance depending on the related managed technology. Thus, being real systems often composed of a mix of different technologies, the quality of their overall management is limited by the less mature and effective single technology management system. Today broadband networks can be seen as a layered structure including ATM, SDH and WDM optical layers. While the management of SDH is quite mature and significant results are reached for ATM management, the management of the WDM optical layer is still in its infancy. Therefore the WDM layer management is a critical factor in the development of the overall broadband network management. The paper, after few considerations on general public network management issues, presents some solutions currently under study for the WDM optical layer management. Although the improvement of the weaker single technology management system surely improves the quality of the overall layered network management, this is just one step along the path for optimizing it. The objective is in fact the integration of the single layer management systems into a global one, avoiding duplications and improving efficiency and effectiveness. The paper presents at the end some considerations about this topic that is rapidly getting hot because of the potential economical benefits such as integration can offer.

  9. Internet of Things Heterogeneous Interoperable Network Architecture Design

    DEFF Research Database (Denmark)

    Bhalerao, Dipashree M.

    2014-01-01

    Internet of Thing‘s (IoT) state of the art deduce that there is no mature Internet of Things architecture available. Thesis contributes an abstract generic IoT system reference architecture development with specifications. Novelties of thesis are proposed solutions and implementations....... It is proved that reduction of data at a source will result in huge vertical scalability and indirectly horizontal also. Second non functional feature contributes in heterogeneous interoperable network architecture for constrained Things. To eliminate increasing number of gateways, Wi-Fi access point...... with Bluetooth, Zigbee (new access point is called as BZ-Fi) is proposed. Co-existence of Wi-Fi, Bluetooth, and Zigbee network technologies results in interference. To reduce the interference, orthogonal frequency division multiplexing (OFDM) is proposed tobe implemented in Bluetooth and Zigbee. The proposed...

  10. Optimizing Neural Network Architectures Using Generalization Error Estimators

    DEFF Research Database (Denmark)

    Larsen, Jan

    1994-01-01

    This paper addresses the optimization of neural network architectures. It is suggested to optimize the architecture by selecting the model with minimal estimated averaged generalization error. We consider a least-squares (LS) criterion for estimating neural network models, i.e., the associated...... model weights are estimated by minimizing the LS criterion. The quality of a particular estimated model is measured by the average generalization error. This is defined as the expected squared prediction error on a novel input-output sample averaged over all possible training sets. An essential part...... of the suggested architecture optimization scheme is to calculate an estimate of the average generalization error. We suggest using the GEN-estimator which allows for dealing with nonlinear, incomplete models, i.e., models which are not capable of modeling the underlying nonlinear relationship perfectly. In most...

  11. MANET: tracing evolution of protein architecture in metabolic networks

    Directory of Open Access Journals (Sweden)

    Caetano-Anollés Gustavo

    2006-07-01

    Full Text Available Abstract Background Cellular metabolism can be characterized by networks of enzymatic reactions and transport processes capable of supporting cellular life. Our aim is to find evolutionary patterns and processes embedded in the architecture and function of modern metabolism, using information derived from structural genomics. Description The Molecular Ancestry Network (MANET project traces evolution of protein architecture in biomolecular networks. We describe metabolic MANET, a database that links information in the Structural Classification of Proteins (SCOP, the Kyoto Encyclopedia of Genes and Genomes (KEGG, and phylogenetic reconstructions depicting the evolution of protein fold architecture. Metabolic MANET literally 'paints' the ancestries of enzymes derived from rooted phylogenomic trees directly onto over one hundred metabolic subnetworks, enabling the study of evolutionary patterns at global and local levels. An initial analysis of painted subnetworks reveals widespread enzymatic recruitment and an early origin of amino acid metabolism. Conclusion MANET maps evolutionary relationships directly and globally onto biological networks, and can generate and test hypotheses related to evolution of metabolism. We anticipate its use in the study of other networks, such as signaling and other protein-protein interaction networks.

  12. Hybrid RRM Architecture for Future Wireless Networks

    DEFF Research Database (Denmark)

    Tragos, Elias; Mihovska, Albena D.; Mino, Emilio

    2007-01-01

    The concept of ubiquitous and scalable system is applied in the IST WINNER II [1] project to deliver optimum performance for different deployment scenarios from local area to wide area wireless networks. The integration of cellular and local area networks in a unique radio system will provide...... a great advantage to final users and operators, compared with the nowadays situation with many disconnected systems and users equipped with different subscriptions, radio interfaces and terminals. To this issue, the IST project WINNER II has defined three system modes suited to local, metropolitan...

  13. Reconfigurable radio systems network architectures and standards

    CERN Document Server

    Iacobucci, Maria Stella

    2013-01-01

    This timely book provides a standards-based view of the development, evolution, techniques and potential future scenarios for the deployment of reconfigurable radio systems.  After an introduction to radiomobile and radio systems deployed in the access network, the book describes cognitive radio concepts and capabilities, which are the basis for reconfigurable radio systems.  The self-organizing network features introduced in 3GPP standards are discussed and IEEE 802.22, the first standard based on cognitive radio, is described. Then the ETSI reconfigurable radio systems functional ar

  14. Implementation of Internet Protocol Network Architecture for Effective ...

    African Journals Online (AJOL)

    Implementation of Internet Protocol Network Architecture for Effective bandwidth Allocation in a Multiparty, Multimedia Conferencing. ... as M/G/∞ input processes and divided into several classes, with the constraint that the aggregate effective bandwidth is within the link capacity times a prescribed utilization threshold.

  15. Robust Networking Architecture and Secure Communication Scheme for Heterogeneous Wireless Sensor Networks

    Science.gov (United States)

    McNeal, McKenzie, III.

    2012-01-01

    Current networking architectures and communication protocols used for Wireless Sensor Networks (WSNs) have been designed to be energy efficient, low latency, and long network lifetime. One major issue that must be addressed is the security in data communication. Due to the limited capabilities of low cost and small sized sensor nodes, designing…

  16. A Security Architecture for Personal Networks

    NARCIS (Netherlands)

    Jehangir, A.; Heemstra de Groot, S.M.

    2006-01-01

    Abstract Personal Network (PN) is a new concept utilizing pervasive computing to meet the needs of the user. As PNs edge closer towards reality, security becomes an important concern since any vulnerability in the system will limit its practical use. In this paper we introduce a security

  17. The development of brain network architecture

    NARCIS (Netherlands)

    Wierenga, Lara M.; van den Heuvel, Martijn P.; van Dijk, Sarai; Rijks, Yvonne; de Reus, Marcel A.; Durston, Sarah

    2016-01-01

    Brain connectivity shows protracted development throughout childhood and adolescence, and, as such, the topology of brain networks changes during this period. The complexity of these changes with development is reflected by regional differences in maturation. This study explored age-related changes

  18. Communication Network Architectures Based on Ethernet Passive Optical Network for Offshore Wind Power Farms

    Directory of Open Access Journals (Sweden)

    Mohamed A. Ahmed

    2016-03-01

    Full Text Available Nowadays, with large-scale offshore wind power farms (WPFs becoming a reality, more efforts are needed to maintain a reliable communication network for WPF monitoring. Deployment topologies, redundancy, and network availability are the main items to enhance the communication reliability between wind turbines (WTs and control centers. Traditional communication networks for monitoring and control (i.e., supervisory control and data acquisition (SCADA systems using switched gigabit Ethernet will not be sufficient for the huge amount of data passing through the network. In this paper, the optical power budget, optical path loss, reliability, and network cost of the proposed Ethernet Passive Optical Network (EPON-based communication network for small-size offshore WPFs have been evaluated for five different network architectures. The proposed network model consists of an optical network unit device (ONU deployed on the WT side for collecting data from different internal networks. All ONUs from different WTs are connected to a central optical line terminal (OLT, placed in the control center. There are no active electronic elements used between the ONUs and the OLT, which reduces the costs and complexity of maintenance and deployment. As fiber access networks without any protection are characterized by poor reliability, three different protection schemes have been configured, explained, and discussed. Considering the cost of network components, the total implementation expense of different architectures with, or without, protection have been calculated and compared. The proposed network model can significantly contribute to the communication network architecture for next generation WPFs.

  19. Mesoscale Architecture Shapes Initiation and Richness of Spontaneous Network Activity.

    Science.gov (United States)

    Okujeni, Samora; Kandler, Steffen; Egert, Ulrich

    2017-04-05

    Spontaneous activity in the absence of external input, including propagating waves of activity, is a robust feature of neuronal networks in vivo and in vitro The neurophysiological and anatomical requirements for initiation and persistence of such activity, however, are poorly understood, as is their role in the function of neuronal networks. Computational network studies indicate that clustered connectivity may foster the generation, maintenance, and richness of spontaneous activity. Since this mesoscale architecture cannot be systematically modified in intact tissue, testing these predictions is impracticable in vivo Here, we investigate how the mesoscale structure shapes spontaneous activity in generic networks of rat cortical neurons in vitro In these networks, neurons spontaneously arrange into local clusters with high neurite density and form fasciculating long-range axons. We modified this structure by modulation of protein kinase C, an enzyme regulating neurite growth and cell migration. Inhibition of protein kinase C reduced neuronal aggregation and fasciculation of axons, i.e., promoted uniform architecture. Conversely, activation of protein kinase C promoted aggregation of neurons into clusters, local connectivity, and bundling of long-range axons. Supporting predictions from theory, clustered networks were more spontaneously active and generated diverse activity patterns. Neurons within clusters received stronger synaptic inputs and displayed increased membrane potential fluctuations. Intensified clustering promoted the initiation of synchronous bursting events but entailed incomplete network recruitment. Moderately clustered networks appear optimal for initiation and propagation of diverse patterns of activity. Our findings support a crucial role of the mesoscale architectures in the regulation of spontaneous activity dynamics. SIGNIFICANCE STATEMENT Computational studies predict richer and persisting spatiotemporal patterns of spontaneous activity in

  20. Building and measuring a high performance network architecture

    Energy Technology Data Exchange (ETDEWEB)

    Kramer, William T.C.; Toole, Timothy; Fisher, Chuck; Dugan, Jon; Wheeler, David; Wing, William R; Nickless, William; Goddard, Gregory; Corbato, Steven; Love, E. Paul; Daspit, Paul; Edwards, Hal; Mercer, Linden; Koester, David; Decina, Basil; Dart, Eli; Paul Reisinger, Paul; Kurihara, Riki; Zekauskas, Matthew J; Plesset, Eric; Wulf, Julie; Luce, Douglas; Rogers, James; Duncan, Rex; Mauth, Jeffery

    2001-04-20

    Once a year, the SC conferences present a unique opportunity to create and build one of the most complex and highest performance networks in the world. At SC2000, large-scale and complex local and wide area networking connections were demonstrated, including large-scale distributed applications running on different architectures. This project was designed to use the unique opportunity presented at SC2000 to create a testbed network environment and then use that network to demonstrate and evaluate high performance computational and communication applications. This testbed was designed to incorporate many interoperable systems and services and was designed for measurement from the very beginning. The end results were key insights into how to use novel, high performance networking technologies and to accumulate measurements that will give insights into the networks of the future.

  1. Network Architecture: lessons from the past, vision for the future

    CERN Document Server

    CERN. Geneva

    2004-01-01

    The Architectural Principles of the Internet have dominated the past decade. Orthogonal to the telecommunications industry principles, they dramatically changed the networking landscape because they relied on iconoclastic ideas. First, the Internet end-to-end principle, which stipulates that the network should intervene minimally on the end-to-end traffic, pushing the complexity to the end-systems. Second, the ban of centralized functions: all the Internet techniques (routing, DNS, management) are based on distributed, decentralized mechanisms. Third, the absolute domination of connectionless (stateless) protocols (as with IP, HTTTP). However, when facing new requirements: multimedia traffic, security, Grid applications, these principles appear sometimes as architectural barriers. Multimedia requires QoS guarantees, but stateless systems are not good at QoS. Security requires active, intelligent networks, but dumb routers or plain end-to-end mail systems are insufficient. Grid applications require...

  2. Network architecture in a converged optical + IP network

    Science.gov (United States)

    Wakim, Walid; Zottmann, Harald

    2012-01-01

    As demands on Provider Networks continue to grow at exponential rates, providers are forced to evaluate how to continue to grow the network while increasing service velocity, enhancing resiliency while decreasing the total cost of ownership (TCO). The bandwidth growth that networks are experiencing is in the form packet based multimedia services such as video, video conferencing, gaming, etc... mixed with Over the Top (OTT) content providers such as Netflix, and the customer's expectations that best effort is not enough you end up with a situation that forces the provider to analyze how to gain more out of the network with less cost. In this paper we will discuss changes in the network that are driving us to a tighter integration between packet and optical layers and how to improve on today's multi - layer inefficiencies to drive down network TCO and provide for a fully integrated and dynamic network that will decrease time to revenue.

  3. Nexus network journal patterns in architecture

    CERN Document Server

    2007-01-01

    This issue is dedicated to various kinds of patterns in architecture. Buthayna Eilouti and Amer Al-Jokhadar address patterns in shape grammars in the ground plans of Mamluk madrasas, religious schools. Giulio Magli goes back further in history, to the age of Greek colonies in Italy before they were conquered by the Romans, to examine patterns in urban design. In Traditional Patterns in Pyrgi of Chios: Mathematics and Community Charoula Stathopoulou examines the geometric patterns that decorate the buildings of the town of Pyrgi, on the Greek island of Chios. Curve Fitting is a study of ways to construct a function so that its graph most closely approximates the pattern given by a set of points. Dirk Huylebrouck’s paper examines how a pattern of points extracted from an arch might be associated to a precise mathematical curve. James Harris looks at the designs of Frank Lloyd Wright and Piet Mondrian to extract the rules of their pattern generation and propose possible applications.

  4. Resting state networks' corticotopy: the dual intertwined rings architecture.

    Directory of Open Access Journals (Sweden)

    Salma Mesmoudi

    Full Text Available How does the brain integrate multiple sources of information to support normal sensorimotor and cognitive functions? To investigate this question we present an overall brain architecture (called "the dual intertwined rings architecture" that relates the functional specialization of cortical networks to their spatial distribution over the cerebral cortex (or "corticotopy". Recent results suggest that the resting state networks (RSNs are organized into two large families: 1 a sensorimotor family that includes visual, somatic, and auditory areas and 2 a large association family that comprises parietal, temporal, and frontal regions and also includes the default mode network. We used two large databases of resting state fMRI data, from which we extracted 32 robust RSNs. We estimated: (1 the RSN functional roles by using a projection of the results on task based networks (TBNs as referenced in large databases of fMRI activation studies; and (2 relationship of the RSNs with the Brodmann Areas. In both classifications, the 32 RSNs are organized into a remarkable architecture of two intertwined rings per hemisphere and so four rings linked by homotopic connections. The first ring forms a continuous ensemble and includes visual, somatic, and auditory cortices, with interspersed bimodal cortices (auditory-visual, visual-somatic and auditory-somatic, abbreviated as VSA ring. The second ring integrates distant parietal, temporal and frontal regions (PTF ring through a network of association fiber tracts which closes the ring anatomically and ensures a functional continuity within the ring. The PTF ring relates association cortices specialized in attention, language and working memory, to the networks involved in motivation and biological regulation and rhythms. This "dual intertwined architecture" suggests a dual integrative process: the VSA ring performs fast real-time multimodal integration of sensorimotor information whereas the PTF ring performs multi

  5. Network Architecture, Security Issues, and Hardware Implementation of a Home Area Network for Smart Grid

    OpenAIRE

    Saponara, Sergio; Bacchillone, Tony

    2012-01-01

    This paper discusses aims, architecture, and security issues of Smart Grid, taking care of the lesson learned at University of Pisa in research projects on smart energy and grid. A key element of Smart Grid is the energy home area network (HAN), for which an implementation is proposed, dealing with its security aspects and showing some solutions for realizing a wireless network based on ZigBee. Possible hardware-software architectures and implementations using COTS (Commercial Off The Shelf) ...

  6. NEBULAS A High Performance Data-Driven Event-Building Architecture based on an Asynchronous Self-Routing Packet-Switching Network

    CERN Multimedia

    Costa, M; Letheren, M; Djidi, K; Gustafsson, L; Lazraq, T; Minerskjold, M; Tenhunen, H; Manabe, A; Nomachi, M; Watase, Y

    2002-01-01

    RD31 : The project is evaluating a new approach to event building for level-two and level-three processor farms at high rate experiments. It is based on the use of commercial switching fabrics to replace the traditional bus-based architectures used in most previous data acquisition sytems. Switching fabrics permit the construction of parallel, expandable, hardware-driven event builders that can deliver higher aggregate throughput than the bus-based architectures. A standard industrial switching fabric technology is being evaluated. It is based on Asynchronous Transfer Mode (ATM) packet-switching network technology. Commercial, expandable ATM switching fabrics and processor interfaces, now being developed for the future Broadband ISDN infrastructure, could form the basis of an implementation. The goals of the project are to demonstrate the viability of this approach, to evaluate the trade-offs involved in make versus buy options, to study the interfacing of the physics frontend data buffers to such a fabric, a...

  7. Research on two-port network of wavelet transform processor using surface acoustic wavelet devices and its application.

    Science.gov (United States)

    Liu, Shoubing; Lu, Wenke; Zhu, Changchun

    2017-11-01

    The goal of this research is to study two-port network of wavelet transform processor (WTP) using surface acoustic wave (SAW) devices and its application. The motive was prompted by the inconvenience of the long research and design cycle and the huge research funding involved with traditional method in this field, which were caused by the lack of the simulation and emulation method of WTP using SAW devices. For this reason, we introduce the two-port network analysis tool, which has been widely used in the design and analysis of SAW devices with uniform interdigital transducers (IDTs). Because the admittance parameters calculation formula of the two-port network can only be used for the SAW devices with uniform IDTs, this analysis tool cannot be directly applied into the design and analysis of the processor using SAW devices, whose input interdigital transducer (IDT) is apodized weighting. Therefore, in this paper, we propose the channel segmentation method, which can convert the WTP using SAW devices into parallel channels, and also provide with the calculation formula of the number of channels, the number of finger pairs and the static capacitance of an interdigital period in each parallel channel firstly. From the parameters given above, we can calculate the admittance parameters of the two port network for each channel, so that we can obtain the admittance parameter of the two-port network of the WTP using SAW devices on the basis of the simplification rule of parallel two-port network. Through this analysis tool, not only can we get the impulse response function of the WTP using SAW devices but we can also get the matching circuit of it. Large numbers of studies show that the parameters of the two-port network obtained by this paper are consistent with those measured by network analyzer E5061A, and the impulse response function obtained by the two-port network analysis tool is also consistent with that measured by network analyzer E5061A, which can meet the

  8. Hierarchical Communication Network Architectures for Offshore Wind Power Farms

    Directory of Open Access Journals (Sweden)

    Mohamed A. Ahmed

    2014-05-01

    Full Text Available Nowadays, large-scale wind power farms (WPFs bring new challenges for both electric systems and communication networks. Communication networks are an essential part of WPFs because they provide real-time control and monitoring of wind turbines from a remote location (local control center. However, different wind turbine applications have different requirements in terms of data volume, latency, bandwidth, QoS, etc. This paper proposes a hierarchical communication network architecture that consist of a turbine area network (TAN, farm area network (FAN, and control area network (CAN for offshore WPFs. The two types of offshore WPFs studied are small-scale WPFs close to the grid and medium-scale WPFs far from the grid. The wind turbines are modelled based on the logical nodes (LN concepts of the IEC 61400-25 standard. To keep pace with current developments in wind turbine technology, the network design takes into account the extension of the LNs for both the wind turbine foundation and meteorological measurements. The proposed hierarchical communication network is based on Switched Ethernet. Servers at the control center are used to store and process the data received from the WPF. The network architecture is modelled and evaluated via OPNET. We investigated the end-to-end (ETE delay for different WPF applications. The results are validated by comparing the amount of generated sensing data with that of received traffic at servers. The network performance is evaluated, analyzed and discussed in view of end-to-end (ETE delay for different link bandwidths.

  9. Evolution of network architecture in a granular material under compression.

    Science.gov (United States)

    Papadopoulos, Lia; Puckett, James G; Daniels, Karen E; Bassett, Danielle S

    2016-09-01

    As a granular material is compressed, the particles and forces within the system arrange to form complex and heterogeneous collective structures. Force chains are a prime example of such structures, and are thought to constrain bulk properties such as mechanical stability and acoustic transmission. However, capturing and characterizing the evolving nature of the intrinsic inhomogeneity and mesoscale architecture of granular systems can be challenging. A growing body of work has shown that graph theoretic approaches may provide a useful foundation for tackling these problems. Here, we extend the current approaches by utilizing multilayer networks as a framework for directly quantifying the progression of mesoscale architecture in a compressed granular system. We examine a quasi-two-dimensional aggregate of photoelastic disks, subject to biaxial compressions through a series of small, quasistatic steps. Treating particles as network nodes and interparticle forces as network edges, we construct a multilayer network for the system by linking together the series of static force networks that exist at each strain step. We then extract the inherent mesoscale structure from the system by using a generalization of community detection methods to multilayer networks, and we define quantitative measures to characterize the changes in this structure throughout the compression process. We separately consider the network of normal and tangential forces, and find that they display a different progression throughout compression. To test the sensitivity of the network model to particle properties, we examine whether the method can distinguish a subsystem of low-friction particles within a bath of higher-friction particles. We find that this can be achieved by considering the network of tangential forces, and that the community structure is better able to separate the subsystem than a purely local measure of interparticle forces alone. The results discussed throughout this study

  10. Architecture and dynamics of overlapped RNA regulatory networks.

    Science.gov (United States)

    Lapointe, Christopher P; Preston, Melanie A; Wilinski, Daniel; Saunders, Harriet A J; Campbell, Zachary T; Wickens, Marvin

    2017-11-01

    A single protein can bind and regulate many mRNAs. Multiple proteins with similar specificities often bind and control overlapping sets of mRNAs. Yet little is known about the architecture or dynamics of overlapped networks. We focused on three proteins with similar structures and related RNA-binding specificities-Puf3p, Puf4p, and Puf5p of S. cerevisiae Using RNA Tagging, we identified a "super-network" comprised of four subnetworks: Puf3p, Puf4p, and Puf5p subnetworks, and one controlled by both Puf4p and Puf5p. The architecture of individual subnetworks, and thus the super-network, is determined by competition among particular PUF proteins to bind mRNAs, their affinities for binding elements, and the abundances of the proteins. The super-network responds dramatically: The remaining network can either expand or contract. These strikingly opposite outcomes are determined by an interplay between the relative abundance of the RNAs and proteins, and their affinities for one another. The diverse interplay between overlapping RNA-protein networks provides versatile opportunities for regulation and evolution. © 2017 Lapointe et al.; Published by Cold Spring Harbor Laboratory Press for the RNA Society.

  11. Thread assignment of multithreaded network applications in multicore/multithreaded processors

    OpenAIRE

    Radojkovic P.; Cakarevic V.; Verdu J.; Pajuelo A.; Cazorla F.J.; Nemirovsky M.; Valero M.

    2013-01-01

    © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The introduction of multithreaded processors comprised of a large number of cores with many shared resources m...

  12. Stability of ecological communities and the architecture of mutualistic and trophic networks.

    Science.gov (United States)

    Thébault, Elisa; Fontaine, Colin

    2010-08-13

    Research on the relationship between the architecture of ecological networks and community stability has mainly focused on one type of interaction at a time, making difficult any comparison between different network types. We used a theoretical approach to show that the network architecture favoring stability fundamentally differs between trophic and mutualistic networks. A highly connected and nested architecture promotes community stability in mutualistic networks, whereas the stability of trophic networks is enhanced in compartmented and weakly connected architectures. These theoretical predictions are supported by a meta-analysis on the architecture of a large series of real pollination (mutualistic) and herbivory (trophic) networks. We conclude that strong variations in the stability of architectural patterns constrain ecological networks toward different architectures, depending on the type of interaction.

  13. Adaptive pattern recognition by mini-max neural networks as a part of an intelligent processor

    Science.gov (United States)

    Szu, Harold H.

    1990-01-01

    In this decade and progressing into 21st Century, NASA will have missions including Space Station and the Earth related Planet Sciences. To support these missions, a high degree of sophistication in machine automation and an increasing amount of data processing throughput rate are necessary. Meeting these challenges requires intelligent machines, designed to support the necessary automations in a remote space and hazardous environment. There are two approaches to designing these intelligent machines. One of these is the knowledge-based expert system approach, namely AI. The other is a non-rule approach based on parallel and distributed computing for adaptive fault-tolerances, namely Neural or Natural Intelligence (NI). The union of AI and NI is the solution to the problem stated above. The NI segment of this unit extracts features automatically by applying Cauchy simulated annealing to a mini-max cost energy function. The feature discovered by NI can then be passed to the AI system for future processing, and vice versa. This passing increases reliability, for AI can follow the NI formulated algorithm exactly, and can provide the context knowledge base as the constraints of neurocomputing. The mini-max cost function that solves the unknown feature can furthermore give us a top-down architectural design of neural networks by means of Taylor series expansion of the cost function. A typical mini-max cost function consists of the sample variance of each class in the numerator, and separation of the center of each class in the denominator. Thus, when the total cost energy is minimized, the conflicting goals of intraclass clustering and interclass segregation are achieved simultaneously.

  14. Evolution of network architecture in a granular material under compression

    Science.gov (United States)

    Bassett, Danielle

    As a granular material is compressed, the particles and forces within the system arrange to form complex and heterogeneous collective structures. However, capturing and characterizing the dynamic nature of the intrinsic inhomogeneity and mesoscale architecture of granular systems can be challenging. Here, we utilize multilayer networks as a framework for directly quantifying the evolution of mesoscale architecture in a compressed granular system. We examine a quasi-two-dimensional aggregate of photoelastic disks, subject to biaxial compressions through a series of small, quasistatic steps. Treating particles as network nodes and inter-particle forces as network edges, we construct a multilayer network for the system by linking together the series of static force networks that exist at each strain step. We then extract the inherent mesoscale structure from the system by using a generalization of community detection methods to multilayer networks, and we define quantitative measures to characterize the reconfiguration and evolution of this structure throughout the compression process. To test the sensitivity of the network model to particle properties, we examine whether the method can distinguish a subsystem of low-friction particles within a bath of higher-friction particles. We find that this can be done by considering the network of tangential forces, and that the community structure is better able to separate the subsystem than consideration of the local inter-particle forces alone. The results discussed throughout this study suggest that these novel network science techniques may provide a direct way to compare and classify data from systems under different external conditions or with different physical makeup. National Science Foundation (BCS-1441502, PHY-1554488, and BCS-1631550).

  15. Mesh Network Architecture for Enabling Inter-Spacecraft Communication

    Science.gov (United States)

    Becker, Christopher; Merrill, Garrick

    2017-01-01

    To enable communication between spacecraft operating in a formation or small constellation, a mesh network architecture was developed and tested using a time division multiple access (TDMA) communication scheme. The network is designed to allow for the exchange of telemetry and other data between spacecraft to enable collaboration between small spacecraft. The system uses a peer-to-peer topology with no central router, so that it does not have a single point of failure. The mesh network is dynamically configurable to allow for addition and subtraction of new spacecraft into the communication network. Flight testing was performed using an unmanned aerial system (UAS) formation acting as a spacecraft analogue and providing a stressing environment to prove mesh network performance. The mesh network was primarily devised to provide low latency, high frequency communication but is flexible and can also be configured to provide higher bandwidth for applications desiring high data throughput. The network includes a relay functionality that extends the maximum range between spacecraft in the network by relaying data from node to node. The mesh network control is implemented completely in software making it hardware agnostic, thereby allowing it to function with a wide variety of existing radios and computing platforms..

  16. Shifts in the architecture of the Nationwide Health Information Network.

    Science.gov (United States)

    Lenert, Leslie; Sundwall, David; Lenert, Michael Edward

    2012-01-01

    In the midst of a US $30 billion USD investment in the Nationwide Health Information Network (NwHIN) and electronic health records systems, a significant change in the architecture of the NwHIN is taking place. Prior to 2010, the focus of information exchange in the NwHIN was the Regional Health Information Organization (RHIO). Since 2010, the Office of the National Coordinator (ONC) has been sponsoring policies that promote an internet-like architecture that encourages point to-point information exchange and private health information exchange networks. The net effect of these activities is to undercut the limited business model for RHIOs, decreasing the likelihood of their success, while making the NwHIN dependent on nascent technologies for community level functions such as record locator services. These changes may impact the health of patients and communities. Independent, scientifically focused debate is needed on the wisdom of ONC's proposed changes in its strategy for the NwHIN.

  17. A Unified Network Security Architecture for Large, Distributed Networks Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In typical, multi-organizational networking environments, it is difficult to define and maintain a uniform authentication scheme that provides users with easy access...

  18. Fast packet switch architectures for broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.

    1990-01-01

    Background information on networking and switching is provided, and the various architectures that have been considered for fast packet switches are described. The focus is solely on switches designed to be implemented electronically. A set of definitions and a brief description of the functionality required of fast packet switches are given. Three basic types of packet switches are identified: the shared-memory, shared-medium, and space-division types. Each of these is described, and examples are given.

  19. Agent-based Personal Network (PN) service architecture

    DEFF Research Database (Denmark)

    Jiang, Bo; Olesen, Henning

    2004-01-01

    In this paper we proposte a new concept for a centralized agent system as the solution for the PN service architecture, which aims to efficiently control and manage the PN resources and enable the PN based services to run seamlessly over different networks and devices. The working principle......, control procedure and enabling techniques behind the agent based solution are the main focuses of this paper....

  20. Multitask neurovision processor with extensive feedback and feedforward connections

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1991-11-01

    A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

  1. Evaluation of Flex-Grid architecture for NREN optical networks

    DEFF Research Database (Denmark)

    Turus, Ioan; Kleist, Josva; Fagertun, Anna Manolova

    2014-01-01

    The paper presents an in-depth and structured evaluation of the impact that Flex-Grid technology reveals within current NRENs’ core optical networks. The evaluation is based on simulations performed with OPNET Modeler tool and considers NORDUnet as well as a normalized GEANT core optical network...... all benefits given by the flexible spectrum allocation. GMPLS is considered in our implementation and the simulated scenarios follow the goal of answering the question: Do NRENs benefit from the introduction of Flex-Grid architecture?...

  2. Data center networks topologies, architectures and fault-tolerance characteristics

    CERN Document Server

    Liu, Yang; Veeraraghavan, Malathi; Lin, Dong; Hamdi, Mounir

    2013-01-01

    This SpringerBrief presents a survey of data center network designs and topologies and compares several properties in order to highlight their advantages and disadvantages. The brief also explores several routing protocols designed for these topologies and compares the basic algorithms to establish connections, the techniques used to gain better performance, and the mechanisms for fault-tolerance. Readers will be equipped to understand how current research on data center networks enables the design of future architectures that can improve performance and dependability of data centers. This con

  3. Integrated Network Architecture for Sustained Human and Robotic Exploration

    Science.gov (United States)

    Noreen, Gary; Cesarone, Robert; Deutsch, Leslie; Edwards, Charles; Soloff, Jason; Ely, Todd; Cook, Brian; Morabito, David; Hemmati, Hamid; Piazolla, Sabino; hide

    2005-01-01

    The National Aeronautics and Space Administration (NASA) Exploration Systems Enterprise is planning a series of human and robotic missions to the Earth's moon and to Mars. These missions will require communication and navigation services. This paper1 sets forth presumed requirements for such services and concepts for lunar and Mars telecommunications network architectures to satisfy the presumed requirements. The paper suggests that an inexpensive ground network would suffice for missions to the near-side of the moon. A constellation of three Lunar Telecommunications Orbiters connected to an inexpensive ground network could provide continuous redundant links to a polar lunar base and its vicinity. For human and robotic missions to Mars, a pair of areostationary satellites could provide continuous redundant links between Earth and a mid-latitude Mars base in conjunction with the Deep Space Network augmented by large arrays of 12-m antennas on Earth.

  4. A modular architecture for transparent computation in recurrent neural networks.

    Science.gov (United States)

    Carmantini, Giovanni S; Beim Graben, Peter; Desroches, Mathieu; Rodrigues, Serafim

    2017-01-01

    Computation is classically studied in terms of automata, formal languages and algorithms; yet, the relation between neural dynamics and symbolic representations and operations is still unclear in traditional eliminative connectionism. Therefore, we suggest a unique perspective on this central issue, to which we would like to refer as transparent connectionism, by proposing accounts of how symbolic computation can be implemented in neural substrates. In this study we first introduce a new model of dynamics on a symbolic space, the versatile shift, showing that it supports the real-time simulation of a range of automata. We then show that the Gödelization of versatile shifts defines nonlinear dynamical automata, dynamical systems evolving on a vectorial space. Finally, we present a mapping between nonlinear dynamical automata and recurrent artificial neural networks. The mapping defines an architecture characterized by its granular modularity, where data, symbolic operations and their control are not only distinguishable in activation space, but also spatially localizable in the network itself, while maintaining a distributed encoding of symbolic representations. The resulting networks simulate automata in real-time and are programmed directly, in the absence of network training. To discuss the unique characteristics of the architecture and their consequences, we present two examples: (i) the design of a Central Pattern Generator from a finite-state locomotive controller, and (ii) the creation of a network simulating a system of interactive automata that supports the parsing of garden-path sentences as investigated in psycholinguistics experiments. Copyright © 2016 Elsevier Ltd. All rights reserved.

  5. Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

    Directory of Open Access Journals (Sweden)

    Ludovic Devaux

    2010-01-01

    Full Text Available The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

  6. Bluetooth telemedicine processor for multichannel biomedical signal transmission via mobile cellular networks.

    Science.gov (United States)

    Rasid, Mohd Fadlee A; Woodward, Bryan

    2005-03-01

    One of the emerging issues in m-Health is how best to exploit the mobile communications technologies that are now almost globally available. The challenge is to produce a system to transmit a patient's biomedical signals directly to a hospital for monitoring or diagnosis, using an unmodified mobile telephone. The paper focuses on the design of a processor, which samples signals from sensors on the patient. It then transmits digital data over a Bluetooth link to a mobile telephone that uses the General Packet Radio Service. The modular design adopted is intended to provide a "future-proofed" system, whose functionality may be upgraded by modifying the software.

  7. Software Defined Networking (SDN) controlled all optical switching networks with multi-dimensional switching architecture

    Science.gov (United States)

    Zhao, Yongli; Ji, Yuefeng; Zhang, Jie; Li, Hui; Xiong, Qianjin; Qiu, Shaofeng

    2014-08-01

    Ultrahigh throughout capacity requirement is challenging the current optical switching nodes with the fast development of data center networks. Pbit/s level all optical switching networks need to be deployed soon, which will cause the high complexity of node architecture. How to control the future network and node equipment together will become a new problem. An enhanced Software Defined Networking (eSDN) control architecture is proposed in the paper, which consists of Provider NOX (P-NOX) and Node NOX (N-NOX). With the cooperation of P-NOX and N-NOX, the flexible control of the entire network can be achieved. All optical switching network testbed has been experimentally demonstrated with efficient control of enhanced Software Defined Networking (eSDN). Pbit/s level all optical switching nodes in the testbed are implemented based on multi-dimensional switching architecture, i.e. multi-level and multi-planar. Due to the space and cost limitation, each optical switching node is only equipped with four input line boxes and four output line boxes respectively. Experimental results are given to verify the performance of our proposed control and switching architecture.

  8. The architecture of mutualistic networks minimizes competition and increases biodiversity.

    Science.gov (United States)

    Bastolla, Ugo; Fortuna, Miguel A; Pascual-García, Alberto; Ferrera, Antonio; Luque, Bartolo; Bascompte, Jordi

    2009-04-23

    The main theories of biodiversity either neglect species interactions or assume that species interact randomly with each other. However, recent empirical work has revealed that ecological networks are highly structured, and the lack of a theory that takes into account the structure of interactions precludes further assessment of the implications of such network patterns for biodiversity. Here we use a combination of analytical and empirical approaches to quantify the influence of network architecture on the number of coexisting species. As a case study we consider mutualistic networks between plants and their animal pollinators or seed dispersers. These networks have been found to be highly nested, with the more specialist species interacting only with proper subsets of the species that interact with the more generalist. We show that nestedness reduces effective interspecific competition and enhances the number of coexisting species. Furthermore, we show that a nested network will naturally emerge if new species are more likely to enter the community where they have minimal competitive load. Nested networks seem to occur in many biological and social contexts, suggesting that our results are relevant in a wide range of fields.

  9. Cortical network architecture for context processing in primate brain.

    Science.gov (United States)

    Chao, Zenas C; Nagasaka, Yasuo; Fujii, Naotaka

    2015-09-29

    Context is information linked to a situation that can guide behavior. In the brain, context is encoded by sensory processing and can later be retrieved from memory. How context is communicated within the cortical network in sensory and mnemonic forms is unknown due to the lack of methods for high-resolution, brain-wide neuronal recording and analysis. Here, we report the comprehensive architecture of a cortical network for context processing. Using hemisphere-wide, high-density electrocorticography, we measured large-scale neuronal activity from monkeys observing videos of agents interacting in situations with different contexts. We extracted five context-related network structures including a bottom-up network during encoding and, seconds later, cue-dependent retrieval of the same network with the opposite top-down connectivity. These findings show that context is represented in the cortical network as distributed communication structures with dynamic information flows. This study provides a general methodology for recording and analyzing cortical network neuronal communication during cognition.

  10. An open, interoperable, and scalable prehospital information technology network architecture.

    Science.gov (United States)

    Landman, Adam B; Rokos, Ivan C; Burns, Kevin; Van Gelder, Carin M; Fisher, Roger M; Dunford, James V; Cone, David C; Bogucki, Sandy

    2011-01-01

    Some of the most intractable challenges in prehospital medicine include response time optimization, inefficiencies at the emergency medical services (EMS)-emergency department (ED) interface, and the ability to correlate field interventions with patient outcomes. Information technology (IT) can address these and other concerns by ensuring that system and patient information is received when and where it is needed, is fully integrated with prior and subsequent patient information, and is securely archived. Some EMS agencies have begun adopting information technologies, such as wireless transmission of 12-lead electrocardiograms, but few agencies have developed a comprehensive plan for management of their prehospital information and integration with other electronic medical records. This perspective article highlights the challenges and limitations of integrating IT elements without a strategic plan, and proposes an open, interoperable, and scalable prehospital information technology (PHIT) architecture. The two core components of this PHIT architecture are 1) routers with broadband network connectivity to share data between ambulance devices and EMS system information services and 2) an electronic patient care report to organize and archive all electronic prehospital data. To successfully implement this comprehensive PHIT architecture, data and technology requirements must be based on best available evidence, and the system must adhere to health data standards as well as privacy and security regulations. Recent federal legislation prioritizing health information technology may position federal agencies to help design and fund PHIT architectures.

  11. SELECTING NEURAL NETWORK ARCHITECTURE FOR INVESTMENT PROFITABILITY PREDICTIONS

    Directory of Open Access Journals (Sweden)

    Marijana Zekić-Sušac

    2012-07-01

    Full Text Available After production and operations, finance and investments are one of the mostfrequent areas of neural network applications in business. The lack of standardizedparadigms that can determine the efficiency of certain NN architectures in a particularproblem domain is still present. The selection of NN architecture needs to take intoconsideration the type of the problem, the nature of the data in the model, as well as somestrategies based on result comparison. The paper describes previous research in that areaand suggests a forward strategy for selecting best NN algorithm and structure. Since thestrategy includes both parameter-based and variable-based testings, it can be used forselecting NN architectures as well as for extracting models. The backpropagation, radialbasis,modular, LVQ and probabilistic neural network algorithms were used on twoindependent sets: stock market and credit scoring data. The results show that neuralnetworks give better accuracy comparing to multiple regression and logistic regressionmodels. Since it is model-independant, the strategy can be used by researchers andprofessionals in other areas of application.

  12. Communication Network Architectures for Smart-Wind Power Farms

    Directory of Open Access Journals (Sweden)

    Mohamed A. Ahmed

    2014-06-01

    Full Text Available Developments in the wind power industry have enabled a new generation of wind turbines with longer blades, taller towers, higher efficiency, and lower maintenance costs due to the maturity of related technologies. Nevertheless, wind turbines are still blind machines because the control center is responsible for managing and controlling individual wind turbines that are turned on or off according to demand for electricity. In this paper, we propose a communication network architecture for smart-wind power farms (Smart-WPFs. The proposed architecture is designed for wind turbines to communicate directly and share sensing data in order to maximize power generation, WPF availability, and turbine efficiency. We also designed a sensor data frame structure to carry sensing data from different wind turbine parts such as the rotor, transformer, nacelle, etc. The data frame includes a logical node ID (LNID, sensor node ID (SNID, sensor type (ST, and sensor data based on the International Electrotechnical Commission (IEC 61400-25 standard. We present an analytical model that describes upstream traffic between the wind turbines and the control center. Using a queueing theory approach, the upstream traffic is evaluated in view of bandwidth utilization and average queuing delay. The performance of the proposed network architectures are evaluated by using analytical and simulation models.

  13. SDN architecture for optical packet and circuit integrated networks

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  14. The architecture of functional interaction networks in the retina.

    Science.gov (United States)

    Ganmor, Elad; Segev, Ronen; Schneidman, Elad

    2011-02-23

    Sensory information is represented in the brain by the joint activity of large groups of neurons. Recent studies have shown that, although the number of possible activity patterns and underlying interactions is exponentially large, pairwise-based models give a surprisingly accurate description of neural population activity patterns. We explored the architecture of maximum entropy models of the functional interaction networks underlying the response of large populations of retinal ganglion cells, in adult tiger salamander retina, responding to natural and artificial stimuli. We found that we can further simplify these pairwise models by neglecting weak interaction terms or by relying on a small set of interaction strengths. Comparing network interactions under different visual stimuli, we show the existence of local network motifs in the interaction map of the retina. Our results demonstrate that the underlying interaction map of the retina is sparse and dominated by local overlapping interaction modules.

  15. Disrupted Brain Functional Network Architecture in Chronic Tinnitus Patients.

    Science.gov (United States)

    Chen, Yu-Chen; Feng, Yuan; Xu, Jin-Jing; Mao, Cun-Nan; Xia, Wenqing; Ren, Jun; Yin, Xindao

    2016-01-01

    Resting-state functional magnetic resonance imaging (fMRI) studies have demonstrated the disruptions of multiple brain networks in tinnitus patients. Nonetheless, several studies found no differences in network processing between tinnitus patients and healthy controls (HCs). Its neural bases are poorly understood. To identify aberrant brain network architecture involved in chronic tinnitus, we compared the resting-state fMRI (rs-fMRI) patterns of tinnitus patients and HCs. Chronic tinnitus patients (n = 24) with normal hearing thresholds and age-, sex-, education- and hearing threshold-matched HCs (n = 22) participated in the current study and underwent the rs-fMRI scanning. We used degree centrality (DC) to investigate functional connectivity (FC) strength of the whole-brain network and Granger causality to analyze effective connectivity in order to explore directional aspects involved in tinnitus. Compared to HCs, we found significantly increased network centrality in bilateral superior frontal gyrus (SFG). Unidirectionally, the left SFG revealed increased effective connectivity to the left middle orbitofrontal cortex (OFC), left posterior lobe of cerebellum (PLC), left postcentral gyrus, and right middle occipital gyrus (MOG) while the right SFG exhibited enhanced effective connectivity to the right supplementary motor area (SMA). In addition, the effective connectivity from the bilateral SFG to the OFC and SMA showed positive correlations with tinnitus distress. Rs-fMRI provides a new and novel method for identifying aberrant brain network architecture. Chronic tinnitus patients have disrupted FC strength and causal connectivity mostly in non-auditory regions, especially the prefrontal cortex (PFC). The current findings will provide a new perspective for understanding the neuropathophysiological mechanisms in chronic tinnitus.

  16. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  17. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....

  18. A solution for parallel network architectures applied to network defense appliances and sensors

    Science.gov (United States)

    Naber, Eric C.; Velez, Paul G.; Johal, Amanpreet S.

    2012-06-01

    Network defense has more technologies available for purchase today than ever before. As the number of threats increase, organizations are deploying multiple defense technologies to defend their networks. For instance, an enterprise network boundary often implements multiple network defense appliances, some with overlapping capabilities (e.g., firewalls, IDS/IPS, DNS Defense). These appliances are applied in a serial fashion to create a chain of network processing specifically designed to drop bad traffic from the network. In these architectures, once a packet is dropped by an appliance subsequent appliances do not process it. This introduces significant limitations; (1) Stateful appliances will maintain an internal state which differs from network reality; (2) The network manager cannot determine, or unit test, how each appliance would have treated each packet; (3) The appliance "votes" cannot be combined to achieve higherlevel functionality. To address these limitations, we have developed a novel, backwards-compatible Parallel Architecture for Network Defense Appliances (PANDA). Our approach allows every appliance to process all network traffic and cast a vote to drop or allow each packet. This "crowd-sourcing" approach allows the network designer to take full advantage of each appliance, understand how each appliance is behaving, and achieve new collaborative appliance behavior.

  19. The brain's functional network architecture reveals human motives.

    Science.gov (United States)

    Hein, Grit; Morishima, Yosuke; Leiberg, Susanne; Sul, Sunhae; Fehr, Ernst

    2016-03-04

    Goal-directed human behaviors are driven by motives. Motives are, however, purely mental constructs that are not directly observable. Here, we show that the brain's functional network architecture captures information that predicts different motives behind the same altruistic act with high accuracy. In contrast, mere activity in these regions contains no information about motives. Empathy-based altruism is primarily characterized by a positive connectivity from the anterior cingulate cortex (ACC) to the anterior insula (AI), whereas reciprocity-based altruism additionally invokes strong positive connectivity from the AI to the ACC and even stronger positive connectivity from the AI to the ventral striatum. Moreover, predominantly selfish individuals show distinct functional architectures compared to altruists, and they only increase altruistic behavior in response to empathy inductions, but not reciprocity inductions. Copyright © 2016, American Association for the Advancement of Science.

  20. Correlation Between Channel Profile and Plan View Drainage Network Architecture

    Science.gov (United States)

    Shelef, E.; Hilley, G. E.

    2011-12-01

    This research explores the relationship between the plan-view network and profile geometry of channels using high-resolution digital topography and numerical models. In particular, we study the relations between plan-view morphometrics of the channel network and the mechanics of land-shaping processes as reflected by channel profile concavity. This analysis addresses one of the long-standing questions in geomorphology relating to the mechanistic significance of various plan-view channel network geometry measures. Statistically based studies suggest that Hortonian measures of channel network architecture (e.g. bifurcation ratio, area ratio, and length ratio) describe virtually all possible network geometries, and hence are not diagnostic when evaluating the origins of the geometry of a particular network. Our analyses of high resolution DEMs that capture different channel profile concavities (i.e debris flow vs. fluvial flows), as well as the topography of landscapes produced by process-based numerical models affirms this conclusion and indicates that Hortonian measures, as well as Hack exponent, are insensitive to channel concavity. In contrast, channel frequency (number of channel segments per area) appears to provide a measure that is sensitive to channel concavity. As such, channel frequency appears to discern between landscapes dominated by different land-shaping processes that produce different channel profile concavities. In the context of headword growing networks, the observed relations between concavity and channel frequency can be modeled through the coupled effect of concavity and surface roughness on the competition between headword growing channels. Our results suggest that the plan-view geometry of channel networks does not simply arise from random deflection of channels that once joined, cannot separate, but rather reflects the underlying processes that incise through rock and transport mass through the channel network

  1. Thinking in networks: artistic–architectural responses to ubiquitous information

    Directory of Open Access Journals (Sweden)

    Yvonne Spielmann

    2011-12-01

    Full Text Available The article discusses creative practices that in aesthetical-technical ways intervene into the computer networked communication systems.I am interested in artist practices that use networks in different ways to make us aware about the possibilities to rethink media-cultural environments. I use the example of the Japanese art-architectural group Double Negative Architecture to give an example of creatively thinking in networks.Yvonne Spielmann (Ph.D., Dr. habil. is presently Research Professor and Chair of New Media at The University of the West of Scotland. Her work focuses on inter-relationships between media and culture, technology, art, science and communication, and in particular on Western/European and non-Western/South-East Asian interaction. Milestones of publish research output are four authored monographs and about 90 single authored articles. Her book, “Video, the Reflexive Medium” (published by MIT Press 2008, Japanese edition by Sangen-sha Press 2011 was rewarded the 2009 Lewis Mumford Award for Outstanding Scholarship in the Ecology of Technics. Her most recent book “Hybrid Cultures” was published in German by Suhrkamp Press in 2010, English edition from MIT Press in 2012. Spielmann's work has been published in German and English and has been translated into French, Polish, Croatian, Swedish, Japanese, and Korean. She holds the 2011 Swedish Prize for Swedish–German scientific co-operation.

  2. A Novel Architectural Concept for Enhanced 5G Network Facilities

    Directory of Open Access Journals (Sweden)

    Chochliouros Ioannis P.

    2017-01-01

    Full Text Available The 5G ESSENCE project’s context is based on the concept of Edge Cloud Computing and Small Cell-as-a-Service (SCaaS -as both have been previously identified in the SESAME 5G-PPP project of phase 1- and further “promotes” their role and/or influences within the related 5G vertical markets. 5G ESSENCE’s core innovation is focused upon the development/provision of a highly flexible and scalable platform, offering benefits to the involved market actors. The present work identifies a variety of challenges to be fulfilled by the 5G ESSENCE, in the scope of an enhanced architectural framework. The proposed technical approach exploits the profits of the centralization of Small Cell functions as scale grows through an edge cloud environment, based on a two-tier architecture with the first distributed tier being for offering low latency services and the second centralized tier being for the provision of high processing power for computing-intensive network applications. This permits decoupling the control and user planes of the Radio Access Network (RAN and achieving the advantages of Cloud-RAN without the enormous fronthaul latency restrictions. The use of end-to-end network slicing mechanisms allows for sharing the related infrastructure among multiple operators/vertical industries and customizing its capabilities on a per-tenant basis, creating a neutral host market and reducing operational costs.

  3. Network architecture underlying maximal separation of neuronal representations

    Directory of Open Access Journals (Sweden)

    Ron A Jortner

    2013-01-01

    Full Text Available One of the most basic and general tasks faced by all nervous systems is extracting relevant information from the organism’s surrounding world. While physical signals available to sensory systems are often continuous, variable, overlapping and noisy, high-level neuronal representations used for decision-making tend to be discrete, specific, invariant, and highly separable. This study addresses the question of how neuronal specificity is generated. Inspired by experimental findings on network architecture in the olfactory system of the locust, I construct a highly simplified theoretical framework which allows for analytic solution of its key properties. For generalized feed-forward systems, I show that an intermediate range of connectivity values between source- and target-populations leads to a combinatorial explosion of wiring possibilities, resulting in input spaces which are, by their very nature, exquisitely sparsely populated. In particular, connection probability ½, as found in the locust antennal-lobe–mushroom-body circuit, serves to maximize separation of neuronal representations across the target Kenyon-cells, and explains their specific and reliable responses. This analysis yields a function expressing response specificity in terms of lower network-parameters; together with appropriate gain control this leads to a simple neuronal algorithm for generating arbitrarily sparse and selective codes and linking network architecture and neural coding. I suggest a way to easily construct ecologically meaningful representations from this code.

  4. Signalling design and architecture for a proposed mobile satellite network

    Science.gov (United States)

    Yan, T.-Y.; Cheng, U.; Wang, C.

    1990-01-01

    In a frequency-division/demand-assigned multiple-access (FD/DAMA) architecture, each mobile subscriber must make a connection request to the Network Management Center before transmission for either open-end or closed-end services. Open-end services are for voice calls and long file transfer and are processed on a blocked-call-cleared basis. Closed-end services are for transmitting burst data and are processed on a first-come first-served basis. This paper presents the signalling design and architecture for non-voice services of an FD/DAMA mobile satellite network. The connection requests are made through the recently proposed multiple channel collision resolution scheme which provides a significantly higher throughput than the traditional slotted ALOHA scheme. For non-voice services, it is well known that retransmissions are necessary to ensure the delivery of a message in its entirety from the source to destination. Retransmission protocols for open-end and closed-end data transfer are investigated. The signal structure for the proposed network is derived from X-25 standards with appropriate modifications. The packet types and their usages are described in this paper.

  5. Green Building between Tradition and Modernity Study Comparative Analysis between Conventional Methods and Updated Styles of Design and Architecture Processors

    Directory of Open Access Journals (Sweden)

    H Elshimy

    2017-03-01

    Full Text Available Green house   concept appeared from the ancient to the modern age ages and there is a tendency to use a traditional architecture with a pristine ecological environment areas and through sophisticated systems arrived to modern systems of the upgraded systems by Treatment architectural achieve environmental   sustainability   in   recent   years,   sustainability concept has become the common interest of numerous disciplines. The reason for this popularity is to perform the sustainable development. The Concept of Green Architecture, also known as "sustainable architecture” or “green house,” is the theory, science and style of buildings designed and constructed in accordance   with environmentally   friendly   principles.   Green house strives to minimize the number of resources consumed in the   building's  construction,   use   and   operation,   as  well  as curtailing  the  harm  done  to  the  environment  through  the emission, pollution and waste of its components.To design, construct, operate and maintain buildings energy, water and new materials are utilized as well as amounts of waste causing negative effects to health and environment is generated. In order to limit these effects and design environmentally sound and resource efficient buildings; "green building systems" must be introduced, clarified, understood and practiced.This paper aims at highlighting these difficult and complex issues of sustainability which encompass the scope of almost every aspect of human life.

  6. Timing organization of a real-time multicore processor

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sparsø, Jens

    2017-01-01

    Real-time systems need a time-predictable computing platform. Computation, communication, and access to shared resources needs to be time-predictable. We use time division multiplexing to statically schedule all computation and communication resources, such as access to main memory or message...... passing over a network-on-chip. We use time-driven communication over an asynchronous network-on-chip to enable time division multiplexing even in a globally asynchronous, locally synchronous multicore architecture. Using time division multiplexing at all levels of the architecture yields in a time......-predictable multicore processor where we can statically analyze the worst-case execution time of tasks....

  7. Performance Analysis of Digital Signal Processors Using SMV Benchmark

    OpenAIRE

    Erh-Wen Hu; Cyril S. Ku; Andrew T. Russo; Bogong Su; Jian Wang

    2009-01-01

    Unlike general-purpose processors, digital signal processors (DSP processors) are strongly application-dependent. To meet the needs for diverse applications, a wide variety of DSP processors based on different architectures ranging from the traditional to VLIW have been introduced to the market over the years. The functionality, performance, and cost of these processors vary over a wide range. In order to select a processor that meets the design criteria for an applicatio...

  8. SANDS: an architecture for clinical decision support in a National Health Information Network.

    Science.gov (United States)

    Wright, Adam; Sittig, Dean F

    2007-10-11

    A new architecture for clinical decision support called SANDS (Service-oriented Architecture for NHIN Decision Support) is introduced and its performance evaluated. The architecture provides a method for performing clinical decision support across a network, as in a health information exchange. Using the prototype we demonstrated that, first, a number of useful types of decision support can be carried out using our architecture; and, second, that the architecture exhibits desirable reliability and performance characteristics.

  9. Stability of Ecological Communities and the Architecture of Mutualistic and Trophic Networks

    NARCIS (Netherlands)

    Thebault, E.M.C.; Fontaine, C.

    2010-01-01

    Research on the relationship between the architecture of ecological networks and community stability has mainly focused on one type of interaction at a time, making difficult any comparison between different network types. We used a theoretical approach to show that the network architecture favoring

  10. Intelligent Approaches in Improving In-vehicle Network Architecture and Minimizing Power Consumption in Combat Vehicles

    Science.gov (United States)

    2011-01-01

    1345– 1361, November 2002. [30] L.F. P. Pollo , J. -Porto, ―A Network-oriented Power Management Architecture,‖ Proc. Integrated Network Management...208, Feb. 2007, doi: 10.1109/TCE.2007.339526. [47] L.F. Pollo and J-Porto, ―A Network-oriented Power Management Architecture,‖ Proc. Integrated

  11. Towards A New Opportunistic IoT Network Architecture for Wildlife Monitoring System

    NARCIS (Netherlands)

    Ayele, Eyuel Debebe; Meratnia, Nirvana; Havinga, Paul J.M.

    In this paper we introduce an opportunistic dual radio IoT network architecture for wildlife monitoring systems (WMS). Since data processing consumes less energy than transmitting the raw data, the proposed architecture leverages opportunistic mobile networks in a fixed LPWAN IoT network

  12. Use of genetic algorithms for encoding efficient neural network architectures: neurocomputer implementation

    Science.gov (United States)

    James, Jason; Dagli, Cihan H.

    1995-04-01

    In this study an attempt is being made to encode the architecture of a neural network in a chromosome string for evolving robust, fast-learning, minimal neural network architectures through genetic algorithms. Various attributes affecting the learning of the network are represented as genes. The performance of the networks is used as the fitness value. Neural network architecture design concepts are initially demonstrated using a backpropagation architecture with the standard data set of Rosenberg and Sejnowski for text to speech conversion on Adaptive Solutions Inc.'s CNAPS Neuro-Computer. The architectures obtained are compared with the one reported in the literature for the standard data set used. The study concludes by providing some insights regarding the architecture encoding for other artificial neural network paradigms.

  13. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

    2005-01-01

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  14. Energy Model of Networks-on-Chip and a Bus

    NARCIS (Netherlands)

    Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jurgen

    A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon- Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

  15. Architectural approach for quality and safety aware healthcare social networks.

    Science.gov (United States)

    López, Diego M; Blobel, Bernd; González, Carolina

    2012-01-01

    Quality of information and privacy and safety issues are frequently identified as main limitations to make most benefit from social media in healthcare. The objective of the paper is to contribute to the analysis of healthcare social networks (SN), and online healthcare social network services (SNS) by proposing a formal architectural analysis of healthcare SN and SNS, considering the complexity of both systems, but stressing on quality, safety and usability aspects. Quality policies are necessary to control the quality of content published by experts and consumers. Privacy and safety policies protect against inappropriate use of information and users responsibility for sharing information. After the policies are established and documented, a proof of concept online SNS supporting primary healthcare promotion is presented in the paper.

  16. Interoperability Architecture for a Paediatric Oncology European Reference Network.

    Science.gov (United States)

    Nitzlnader, Michael; Canete Nieto, Adela; Ribelles, Antonio Juan; Brunmair, Barbara; Ladenstein, Ruth; Schreier, Günter

    2016-01-01

    With the Directive 2011/24/EU on patients' rights in cross-border healthcare and the related delegated decisions, the European Commission defined a legal framework on how healthcare shall be organised by European Union (EU) member states (MS) where patients can move beyond the borders of their home country. Among other aspects, Article 12 of the directive is concerned with supporting MS with the development of so called European Reference Networks (ERN), dedicated to the treatment of "patients with a medical condition requiring a particular concentration of expertise in medical domains where expertise is rare". In the "European Expert Paediatric Oncology Reference Network for Diagnostics and Treatment" (ExPO-r-Net) project, the establishment of such an ERN in the domain of Paediatric Oncology is currently piloted. The present paper describes the high level use cases, the main requirements and a corresponding interoperability architecture capable to serve as the necessary IT platform to facilitate cross-border health data exchange.

  17. An architecture for design and planning of mobile television networks

    Directory of Open Access Journals (Sweden)

    R. Tamayo-Fernández

    2011-12-01

    Full Text Available Mobile television (TV, made possible by the convergence of media, telecommunications and consumer electronicsindustries, is one of the most hyped new mobile services in several countries [1]. The advertised key features ofmobile TV are personalization, interactivity, and most importantly, the ability to watch TV programming while on thego. The deployment of a mobile TV network consists of several stages that require careful planning. There are available simulation packages for designing wireless technologies, however, for mobile TV there are still planning and simulations concerns that have to be addressed in order to identify its design challenges. This article reviews the main parameters that should be taken into account to support the design and planning of a mobile TV network andproposes an architecture for its implementation.

  18. An architecture for designing fuzzy logic controllers using neural networks

    Science.gov (United States)

    Berenji, Hamid R.

    1991-01-01

    Described here is an architecture for designing fuzzy controllers through a hierarchical process of control rule acquisition and by using special classes of neural network learning techniques. A new method for learning to refine a fuzzy logic controller is introduced. A reinforcement learning technique is used in conjunction with a multi-layer neural network model of a fuzzy controller. The model learns by updating its prediction of the plant's behavior and is related to the Sutton's Temporal Difference (TD) method. The method proposed here has the advantage of using the control knowledge of an experienced operator and fine-tuning it through the process of learning. The approach is applied to a cart-pole balancing system.

  19. CPU architecture for a fast and energy-saving calculation of convolution neural networks

    Science.gov (United States)

    Knoll, Florian J.; Grelcke, Michael; Czymmek, Vitali; Holtorf, Tim; Hussmann, Stephan

    2017-06-01

    One of the most difficult problem in the use of artificial neural networks is the computational capacity. Although large search engine companies own specially developed hardware to provide the necessary computing power, for the conventional user only remains the state of the art method, which is the use of a graphic processing unit (GPU) as a computational basis. Although these processors are well suited for large matrix computations, they need massive energy. Therefore a new processor on the basis of a field programmable gate array (FPGA) has been developed and is optimized for the application of deep learning. This processor is presented in this paper. The processor can be adapted for a particular application (in this paper to an organic farming application). The power consumption is only a fraction of a GPU application and should therefore be well suited for energy-saving applications.

  20. Intrinsic and Task-Evoked Network Architectures of the Human Brain

    OpenAIRE

    Cole, Michael W.; Bassett, Danielle S.; Power, Jonathan D.; Braver, Todd S.; Petersen, Steven E.

    2014-01-01

    Many functional network properties of the human brain have been identified during rest and task states, yet it remains unclear how the two relate. We identified a whole-brain network architecture present across dozens of task states that was highly similar to the resting-state network architecture. The most frequent functional connectivity strengths across tasks closely matched the strengths observed at rest, suggesting this is an “intrinsic”, standard architecture of functional brain organiz...

  1. Time-memory-processor tradeoffs

    Energy Technology Data Exchange (ETDEWEB)

    Amirazizi, H.R.; Hellman, M.E.

    This paper demonstrates that usual time-memory tradeoffs offer no asymptotic advantage over exhaustive search. Instead, it proposes tradoffs between time, memory, and parallel processing. Using this approach it is shown that most searching problems allow a tradeoff between c/sub s/, the cost per solution, and c/sub m/, the cost of the machine; doubling c/sub m/ increases the solution rate by a factor of four, halving c/sub s/. The machine which achieves this has an unusual architecture, with a number of processors sharing a large memory through a sorting/switching network. The implications for cryptanalysis, the knapsack problem, multiple encryption and VLSI are discussed.

  2. Pathway Processor: A Tool for Integrating Whole-Genome Expression Results into Metabolic Networks

    Science.gov (United States)

    Grosu, Paul; Townsend, Jeffrey P.; Hartl, Daniel L.; Cavalieri, Duccio

    2002-01-01

    We have developed a new tool to visualize expression data on metabolic pathways and to evaluate which metabolic pathways are most affected by transcriptional changes in whole-genome expression experiments. Using the Fisher Exact Test, the method scores biochemical pathways according to the probability that as many or more genes in a pathway would be significantly altered in a given experiment by chance alone. This method has been validated on diauxic shift experiments and reproduces well known effects of carbon source on yeast metabolism. The analysis is implemented with Pathway Analyzer, one of the tools of Pathway Processor, a new statistical package for the analysis of whole-genome expression data. Results from multiple experiments can be compared, reducing the analysis from the full set of individual genes to a limited number of pathways of interest. The pathways are visualized with OpenDX, an open-source visualization software package, and the relationship between genes in the pathways can be examined in detail using Expression Mapper, the second program of the package. This program features a graphical output displaying differences in expression on metabolic charts of the biochemical pathways to which the open reading frames are assigned. [Supplementary materials are available at http://www.cgr.harvard.edu/cavalieri/pp.html and http://www.genome.org.] PMID:12097350

  3. Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2012-01-01

    Full Text Available Two multiprocessor system-on-chip (MPSoC architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

  4. Sensor network architecture for monitoring turtles on seashore

    Science.gov (United States)

    Carvajal-Gámez, Blanca E.; Cruz, Victor; Díaz-Casco, Manuel A.; Franco, Andrea; Escobar, Carolina; Colin, Abilene; Carreto-Arellano, Chadwick

    2017-04-01

    In the last decade, advances in information and communication technologies have made it possible to diversify the use of sensor networks in different areas of knowledge (medicine, education, militia, urbanization, protection of the environment, etc.). At present, this type of tools is used to develop applications that allow the identification and monitoring of endangered animals in their natural habitat; however, there are still limitations because some of the devices used alter the behavior of the animals, as in the case of sea turtles. Research and monitoring of sea turtles is of vital importance in identifying possible threats and ensuring their preservation, the behavior of this species (migration, reproduction, and nesting) is highly related to environmental conditions. Because of this, behavioral changes information of this species can be used to monitor global climatic conditions. This work presents the design, development and implementation of an architecture for the monitoring and identification of the sea turtle using sensor networks. This will allow to obtain information for the different investigations with a greater accuracy than the conventional techniques, through non-invasive means for the species and its habitat. The proposed architecture contemplates the use of new technology devices, selfconfigurable, with low energy consumption, interconnection with various communication protocols and sustainable energy supply (solar, wind, etc.).

  5. 3-D Scene Generation On A Shared Memory Parallel Processor

    Science.gov (United States)

    Kelly, R. F.

    1987-06-01

    Realistic 3-D scene generation is now a possibility for many applications. One barrier to increased use of this technique is the large amount of computer processing time needed to render a scene. With the advent of parallel processors that barrier may be overcome if efficient parallel scene generation algorithms can be developed. In general, this has not been true because of restrictions imposed by non-shared memory and limited processor interconnect architectures. In addition, vector processors do not efficiently support the adaptive nature of many of the algorithms. A new parallel computer, the NYU Ultracomputer, has been developed which features a shared memory with a combining network. The com-bining network permits simultaneous reads and writes to the same memory location using a new instruction the Fetch and_Op. These memory references are resolved in the memory access network and result in particularly efficient shared data structures. Basic elements of this architecture are also being used in the design of the gigaflop range RP3 at IBM. Some algorithms typical of image synthesis are explored in the paper and a class of equivalent queue based algorithms are developed. These algorithms are particularly well suited to the Ultra-computer class processor and hold the promise for many new applications of realistic scene generation.

  6. Analysis of Terminal Server Architectures for Thin Clients in a High Assurance Network

    National Research Council Canada - National Science Library

    Balmer, Steven R; Irvine, Cynthia E

    2000-01-01

    This paper examines the architectural and security impact of using commercially available, popular terminal servers to support thin clients within the context of a high assurance multilevel network...

  7. Fiber-wireless convergence in next-generation communication networks systems, architectures, and management

    CERN Document Server

    Chang, Gee-Kung; Ellinas, Georgios

    2017-01-01

    This book investigates new enabling technologies for Fi-Wi convergence. The editors discuss Fi-Wi technologies at the three major network levels involved in the path towards convergence: system level, network architecture level, and network management level. The main topics will be: a. At system level: Radio over Fiber (digitalized vs. analogic, standardization, E-band and beyond) and 5G wireless technologies; b. Network architecture level: NGPON, WDM-PON, BBU Hotelling, Cloud Radio Access Networks (C-RANs), HetNets. c. Network management level: SDN for convergence, Next-generation Point-of-Presence, Wi-Fi LTE Handover, Cooperative MultiPoint. • Addresses the Fi-Wi convergence issues at three different levels, namely at the system level, network architecture level, and network management level • Provides approaches in communication systems, network architecture, and management that are expected to steer the evolution towards fiber-wireless convergence • Contributions from leading experts in the field of...

  8. Firewall Architectures for High-Speed Networks: Final Report

    Energy Technology Data Exchange (ETDEWEB)

    Errin W. Fulp

    2007-08-20

    Firewalls are a key component for securing networks that are vital to government agencies and private industry. They enforce a security policy by inspecting and filtering traffic arriving or departing from a secure network. While performing these critical security operations, firewalls must act transparent to legitimate users, with little or no effect on the perceived network performance (QoS). Packets must be inspected and compared against increasingly complex rule sets and tables, which is a time-consuming process. As a result, current firewall systems can introduce significant delays and are unable to maintain QoS guarantees. Furthermore, firewalls are susceptible to Denial of Service (DoS) attacks that merely overload/saturate the firewall with illegitimate traffic. Current firewall technology only offers a short-term solution that is not scalable; therefore, the \\textbf{objective of this DOE project was to develop new firewall optimization techniques and architectures} that meet these important challenges. Firewall optimization concerns decreasing the number of comparisons required per packet, which reduces processing time and delay. This is done by reorganizing policy rules via special sorting techniques that maintain the original policy integrity. This research is important since it applies to current and future firewall systems. Another method for increasing firewall performance is with new firewall designs. The architectures under investigation consist of multiple firewalls that collectively enforce a security policy. Our innovative distributed systems quickly divide traffic across different levels based on perceived threat, allowing traffic to be processed in parallel (beyond current firewall sandwich technology). Traffic deemed safe is transmitted to the secure network, while remaining traffic is forwarded to lower levels for further examination. The result of this divide-and-conquer strategy is lower delays for legitimate traffic, higher throughput

  9. Ultra Dependable Processor

    Science.gov (United States)

    Sakai, Shuichi; Goshima, Masahiro; Irie, Hidetsugu

    This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.

  10. High-efficiency space-based software radio architectures & algorithms (a minimum size, weight, and power TeraOps processor)

    Energy Technology Data Exchange (ETDEWEB)

    Dunham, Mark Edward [Los Alamos National Laboratory; Baker, Zachary K [Los Alamos National Laboratory; Stettler, Matthew W [Los Alamos National Laboratory; Pigue, Michael J [Los Alamos National Laboratory; Schmierer, Eric N [Los Alamos National Laboratory; Power, John F [Los Alamos National Laboratory; Graham, Paul S [Los Alamos National Laboratory

    2009-01-01

    Los Alamos has recently completed the latest in a series of Reconfigurable Software Radios, which incorporates several key innovations in both hardware design and algorithms. Due to our focus on satellite applications, each design must extract the best size, weight, and power performance possible from the ensemble of Commodity Off-the-Shelf (COTS) parts available at the time of design. In this case we have achieved 1 TeraOps/second signal processing on a 1920 Megabit/second datastream, while using only 53 Watts mains power, 5.5 kg, and 3 liters. This processing capability enables very advanced algorithms such as our wideband RF compression scheme to operate remotely, allowing network bandwidth constrained applications to deliver previously unattainable performance.

  11. Mobile network architecture of the long-range WindScanner system

    DEFF Research Database (Denmark)

    Vasiljevic, Nikola; Lea, Guillaume; Hansen, Per

    In this report we have presented the network architecture of the long-range WindScanner system that allows utilization of mobile network connections without the use of static public IP addresses. The architecture mitigates the issues of additional fees and contractual obligations that are linked...... to the acquisition of the mobile network connections with static public IP addresses. The architecture consists of a hardware VPN solution based on the network appliances Z1 and MX60 from Cisco Meraki with additional 3G or 4G dongles. With the presented network architecture and appropriate configuration, we fulfill...... the requirements of running the long-range WindScanner system using a mobile network such as 3G. This architecture allows us to have the WindScanners and the master computer in different geographical locations, and in general facilitates deployments of the long-range WindScanner system....

  12. FIGARO ( Future Internet Gateway-based Architecture of Residential Networks ) D5.2: Architecture for service federation in residential networks

    NARCIS (Netherlands)

    Hartog, F.T.H. den; Hillen, B.A.G.; Tijmes, M.R.

    2011-01-01

    This document defines the preliminary version of the FIGARO architectural solution for federation within residential networks. The architecture is derived from use cases from the domains of e-health, energy management, domotics and social community services and thus supports requirements from each

  13. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  14. Architecture of the Florida Power Grid as a Complex Network

    Science.gov (United States)

    Xu, Yan; Gurfinkel, Aleks Jacob; Rikvold, Per Arne

    2014-03-01

    Power grids are the largest engineered systems ever built. Our work presents a simple and self-consistent graph-theoretic analysis of the Florida high-voltage power grid as a technological network embedded in two-dimensional space. We take a new perspective on the mixing patterns of generators and loads in power grids, pointing out that the real grid is usually intermediate between the random mixing and semi-bipartite case (in which generator-generator power transmission lines are disallowed). We propose spatial network models for power grids, which are obtained via a Monte Carlo cooling optimization process. Our results suggest some possible design principles behind the complex architecture of the Florida grid, viz. balancing low construction cost (measured by the total length of transmission lines) and an indispensable redundancy (measured by the clustering coefficient and edge multiplicity) responsible for the robustness of the grid. We also study community structures (modularity) of the real and modeled power-grid networks. Such communities can be electrically separated from each other to limit cascading power failures, a technique known as intentional islanding. Supported by NSF Grant No. DMR-1104829.

  15. Service Oriented Architecture for Wireless Sensor Networks in Agriculture

    Science.gov (United States)

    Sawant, S. A.; Adinarayana, J.; Durbha, S. S.; Tripathy, A. K.; Sudharsan, D.

    2012-08-01

    Rapid advances in Wireless Sensor Network (WSN) for agricultural applications has provided a platform for better decision making for crop planning and management, particularly in precision agriculture aspects. Due to the ever-increasing spread of WSNs there is a need for standards, i.e. a set of specifications and encodings to bring multiple sensor networks on common platform. Distributed sensor systems when brought together can facilitate better decision making in agricultural domain. The Open Geospatial Consortium (OGC) through Sensor Web Enablement (SWE) provides guidelines for semantic and syntactic standardization of sensor networks. In this work two distributed sensing systems (Agrisens and FieldServer) were selected to implement OGC SWE standards through a Service Oriented Architecture (SOA) approach. Online interoperable data processing was developed through SWE components such as Sensor Model Language (SensorML) and Sensor Observation Service (SOS). An integrated web client was developed to visualize the sensor observations and measurements that enables the retrieval of crop water resources availability and requirements in a systematic manner for both the sensing devices. Further, the client has also the ability to operate in an interoperable manner with any other OGC standardized WSN systems. The study of WSN systems has shown that there is need to augment the operations / processing capabilities of SOS in order to understand about collected sensor data and implement the modelling services. Also, the very low cost availability of WSN systems in future, it is possible to implement the OGC standardized SWE framework for agricultural applications with open source software tools.

  16. A Novel, Privacy Preserving, Architecture for Online Social Networks

    Directory of Open Access Journals (Sweden)

    Zhe Wang

    2015-12-01

    Full Text Available The centralized nature of conventional OSNs poses serious risks to the privacy and security of information exchanged between their members. These risks prompted several attempts to create decentralized OSNs, or DOSNs. The basic idea underlying these attempts, is that each member of a social network keeps its data under its own control, instead of surrendering it to a central host, providing access to it to other members according to its own access-control policy. Unfortunately all existing versions of DOSNs have a very serious limitation. Namely, they are unable to subject the membership of a DOSN, and the interaction between its members, to any global policy—which is essential for many social communities. Moreover, the DOSN architecture is unable to support useful capabilities such as narrowcasting and profile based search. This paper describes a novel architecture of decentralized OSNs—called DOSC, for “online social community”. DOSC adopts the decentralization idea underlying DOSNs, but it is able to subject the membership of a DOSC-community, and the interaction between its members, to a wide range of policies, including privacy-preserving narrowcasting and profile-sensitive search.

  17. SPANNER: A Self-Repairing Spiking Neural Network Hardware Architecture.

    Science.gov (United States)

    Liu, Junxiu; Harkin, Jim; Maguire, Liam P; McDaid, Liam J; Wade, John J

    2017-03-06

    Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel hardware architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing architecture is significantly damaged at a fault density of 80%.

  18. ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology

    DEFF Research Database (Denmark)

    Stensgaard, Mikkel Bystrup; Sparsø, Jens

    2008-01-01

    This paper presents a Network-on-Chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long...

  19. Scale-space measures for graph topology link protein network architecture to function

    NARCIS (Netherlands)

    Hulsman, M.; Dimitrakopoulos, C.; De Ridder, J.

    2014-01-01

    MOTIVATION: The network architecture of physical protein interactions is an important determinant for the molecular functions that are carried out within each cell. To study this relation, the network architecture can be characterized by graph topological characteristics such as shortest paths and

  20. Low-Cost Hybrid ROADM Architectures for Scalable C/DWDM Metro Networks

    DEFF Research Database (Denmark)

    Nooruzzaman, Md; Halima, Elbiaze

    2016-01-01

    CWDM networks have proven to be a promising first-step metro and access network architecture, offering a significant cost advantage over DWDM due to the lower cost of lasers and the filters used in CWDM modules. If demand grows beyond the capacity covered by CWDM channels, DWDM network elements can...... be introduced to merge CWDM and DWDM traffic at the optical layer. This ensures two advantages: reduced initial investment and scalability for deploying DWDM channels in the future. This article presents various ROADM architectures, and explores the novel optical node architecture of hybrid C/DWDM networks......, consisting of CWDM, hybrid C/DWDM, and junction nodes connecting two rings. Evaluation has shown that the hybrid ROADM architecture is superior to other conventional ROADM architectures in terms of scalability and the initial cost of optical nodes and networks....

  1. Network Architecture, Security Issues, and Hardware Implementation of a Home Area Network for Smart Grid

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2012-01-01

    Full Text Available This paper discusses aims, architecture, and security issues of Smart Grid, taking care of the lesson learned at University of Pisa in research projects on smart energy and grid. A key element of Smart Grid is the energy home area network (HAN, for which an implementation is proposed, dealing with its security aspects and showing some solutions for realizing a wireless network based on ZigBee. Possible hardware-software architectures and implementations using COTS (Commercial Off The Shelf components are presented for key building blocks of the energy HAN such as smart power meters and plugs and a home smart information box providing energy management policy and supporting user's energy awareness.

  2. An Open Distributed Architecture for Sensor Networks for Risk Management

    Directory of Open Access Journals (Sweden)

    Ralf Denzer

    2008-03-01

    Full Text Available Sensors provide some of the basic input data for risk management of natural andman-made hazards. Here the word ‘sensors’ covers everything from remote sensingsatellites, providing invaluable images of large regions, through instruments installed on theEarth’s surface to instruments situated in deep boreholes and on the sea floor, providinghighly-detailed point-based information from single sites. Data from such sensors is used inall stages of risk management, from hazard, vulnerability and risk assessment in the preeventphase, information to provide on-site help during the crisis phase through to data toaid in recovery following an event. Because data from sensors play such an important part inimproving understanding of the causes of risk and consequently in its mitigation,considerable investment has been made in the construction and maintenance of highlysophisticatedsensor networks. In spite of the ubiquitous need for information from sensornetworks, the use of such data is hampered in many ways. Firstly, information about thepresence and capabilities of sensor networks operating in a region is difficult to obtain dueto a lack of easily available and usable meta-information. Secondly, once sensor networkshave been identified their data it is often difficult to access due to a lack of interoperability between dissemination and acquisition systems. Thirdly, the transfer and processing ofinformation from sensors is limited, again by incompatibilities between systems. Therefore,the current situation leads to a lack of efficiency and limited use of the available data thathas an important role to play in risk mitigation. In view of this situation, the EuropeanCommission (EC is funding a number of Integrated Projects within the Sixth FrameworkProgramme concerned with improving the accessibility of data and services for riskmanagement. Two of these projects: ‘Open Architecture and Spatial Data

  3. Efficient reconstruction of biological networks via transitive reduction on general purpose graphics processors.

    Science.gov (United States)

    Bošnački, Dragan; Odenbrett, Maximilian R; Wijs, Anton; Ligtenberg, Willem; Hilbers, Peter

    2012-10-30

    Techniques for reconstruction of biological networks which are based on perturbation experiments often predict direct interactions between nodes that do not exist. Transitive reduction removes such relations if they can be explained by an indirect path of influences. The existing algorithms for transitive reduction are sequential and might suffer from too long run times for large networks. They also exhibit the anomaly that some existing direct interactions are also removed. We develop efficient scalable parallel algorithms for transitive reduction on general purpose graphics processing units for both standard (unweighted) and weighted graphs. Edge weights are regarded as uncertainties of interactions. A direct interaction is removed only if there exists an indirect interaction path between the same nodes which is strictly more certain than the direct one. This is a refinement of the removal condition for the unweighted graphs and avoids to a great extent the erroneous elimination of direct edges. Parallel implementations of these algorithms can achieve speed-ups of two orders of magnitude compared to their sequential counterparts. Our experiments show that: i) taking into account the edge weights improves the reconstruction quality compared to the unweighted case; ii) it is advantageous not to distinguish between positive and negative interactions since this lowers the complexity of the algorithms from NP-complete to polynomial without loss of quality.

  4. Implementing wireless sensor networks for architectural heritage conservation

    Science.gov (United States)

    Martínez-Garrido, M. I.; Aparicio, S.; Fort, R.; Izquierdo, M. A. G.; Anaya, J. J.

    2012-04-01

    Preventive conservation in architectural heritage is one of the most important aims for the development and implementation of new techniques to assess decay, lending to reduce damage before it has occurred and reducing costs in the long term. For that purpose, it is necessary to know all aspects influencing in decay evolution depending on the material under study and its internal and external conditions. Wireless sensor networks are an emerging technology and a minimally invasive technique. The use of these networks facilitates data acquisition and monitoring of a large number of variables that could provoke material damages, such as presence of harmful compounds like salts, dampness, etc. The current project presents different wireless sensors networks (WSN) and sensors used to fulfill the requirements for a complete analysis of main decay agents in a Renaissance church of the 16th century in Madrid (Spain). Current typologies and wireless technologies are studied establishing the most suitable system and the convenience of each one. Firstly, it is very important to consider that microclimate is in close correlation with material deterioration. Therefore a temperature(T) and relative humidity (RH)/moisture network has been developed, using ZigBee wireless communications protocols, and monitoring different points along the church surface. These points are recording RH/T differences depending on the height and the sensor location (inside the material or on the surface). On the other hand, T/RH button sensors have been used, minimizing aesthetical interferences, and concluding which is the most advisable way for monitoring these specific parameters. Due to the fact that microclimate is a complex phenomenon, it is necessary to examine spatial distribution and time evolution at the same time. This work shows both studies since the development expects a long term monitoring. A different wireless network has been deployed to study the effects of pollution caused by other

  5. Overview of the Smart Network Element Architecture and Recent Innovations

    Science.gov (United States)

    Perotti, Jose M.; Mata, Carlos T.; Oostdyk, Rebecca L.

    2008-01-01

    In industrial environments, system operators rely on the availability and accuracy of sensors to monitor processes and detect failures of components and/or processes. The sensors must be networked in such a way that their data is reported to a central human interface, where operators are tasked with making real-time decisions based on the state of the sensors and the components that are being monitored. Incorporating health management functions at this central location aids the operator by automating the decision-making process to suggest, and sometimes perform, the action required by current operating conditions. Integrated Systems Health Management (ISHM) aims to incorporate data from many sources, including real-time and historical data and user input, and extract information and knowledge from that data to diagnose failures and predict future failures of the system. By distributing health management processing to lower levels of the architecture, there is less bandwidth required for ISHM, enhanced data fusion, make systems and processes more robust, and improved resolution for the detection and isolation of failures in a system, subsystem, component, or process. The Smart Network Element (SNE) has been developed at NASA Kennedy Space Center to perform intelligent functions at sensors and actuators' level in support of ISHM.

  6. Wireless Sensor Networks for Space Applications: Network Architecture and Protocol Enhancements

    Directory of Open Access Journals (Sweden)

    Driss BENHADDOU

    2009-10-01

    Full Text Available The application of Wireless Sensor Networks (WSNs in time-sensitive space applications, such as astronaut health monitoring and environment-risk monitoring, demands exclusive investigation of network design and protocols for optimized operation in geo-station environments. The continuous monitoring of physiological condition of crew members, spaceflight equipments and habitat during long space missions is of paramount importance to NASA for mitigating performance risks. Continual performance tracking and local response advisory capabilities, within space environments, are crucial to ensure overall mission success. This paper will present challenges and opportunities of wireless sensor networks in space applications, and the investigation of system and protocol design for efficient performance monitoring. We describe a flexible WSN architecture and the required system components for reliable communications. We also investigate crucial network algorithms including link quality adaptation, energy efficiency and quality-of-service that are essential for efficient performance monitoring in geo-station environments.

  7. A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processors.

    Science.gov (United States)

    Nageswaran, Jayram Moorkanikara; Dutt, Nikil; Krichmar, Jeffrey L; Nicolau, Alex; Veidenbaum, Alexander V

    2009-01-01

    Neural network simulators that take into account the spiking behavior of neurons are useful for studying brain mechanisms and for various neural engineering applications. Spiking Neural Network (SNN) simulators have been traditionally simulated on large-scale clusters, super-computers, or on dedicated hardware architectures. Alternatively, Compute Unified Device Architecture (CUDA) Graphics Processing Units (GPUs) can provide a low-cost, programmable, and high-performance computing platform for simulation of SNNs. In this paper we demonstrate an efficient, biologically realistic, large-scale SNN simulator that runs on a single GPU. The SNN model includes Izhikevich spiking neurons, detailed models of synaptic plasticity and variable axonal delay. We allow user-defined configuration of the GPU-SNN model by means of a high-level programming interface written in C++ but similar to the PyNN programming interface specification. PyNN is a common programming interface developed by the neuronal simulation community to allow a single script to run on various simulators. The GPU implementation (on NVIDIA GTX-280 with 1 GB of memory) is up to 26 times faster than a CPU version for the simulation of 100K neurons with 50 Million synaptic connections, firing at an average rate of 7 Hz. For simulation of 10 Million synaptic connections and 100K neurons, the GPU SNN model is only 1.5 times slower than real-time. Further, we present a collection of new techniques related to parallelism extraction, mapping of irregular communication, and network representation for effective simulation of SNNs on GPUs. The fidelity of the simulation results was validated on CPU simulations using firing rate, synaptic weight distribution, and inter-spike interval analysis. Our simulator is publicly available to the modeling community so that researchers will have easy access to large-scale SNN simulations.

  8. Security Policy Scheme for an Efficient Security Architecture in Software-Defined Networking

    Directory of Open Access Journals (Sweden)

    Woosik Lee

    2017-06-01

    Full Text Available In order to build an efficient security architecture, previous studies have attempted to understand complex system architectures and message flows to detect various attack packets. However, the existing hardware-based single security architecture cannot efficiently handle a complex system structure. To solve this problem, we propose a software-defined networking (SDN policy-based scheme for an efficient security architecture. The proposed scheme considers four policy functions: separating, chaining, merging, and reordering. If SDN network functions virtualization (NFV system managers use these policy functions to deploy a security architecture, they only submit some of the requirement documents to the SDN policy-based architecture. After that, the entire security network can be easily built. This paper presents information about the design of a new policy functions model, and it discusses the performance of this model using theoretical analysis.

  9. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performan...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  10. Analog Processor To Solve Optimization Problems

    Science.gov (United States)

    Duong, Tuan A.; Eberhardt, Silvio P.; Thakoor, Anil P.

    1993-01-01

    Proposed analog processor solves "traveling-salesman" problem, considered paradigm of global-optimization problems involving routing or allocation of resources. Includes electronic neural network and auxiliary circuitry based partly on concepts described in "Neural-Network Processor Would Allocate Resources" (NPO-17781) and "Neural Network Solves 'Traveling-Salesman' Problem" (NPO-17807). Processor based on highly parallel computing solves problem in significantly less time.

  11. Neural network architecture for cognitive navigation in dynamic environments.

    Science.gov (United States)

    Villacorta-Atienza, José Antonio; Makarov, Valeri A

    2013-12-01

    Navigation in time-evolving environments with moving targets and obstacles requires cognitive abilities widely demonstrated by even simplest animals. However, it is a long-standing challenging problem for artificial agents. Cognitive autonomous robots coping with this problem must solve two essential tasks: 1) understand the environment in terms of what may happen and how I can deal with this and 2) learn successful experiences for their further use in an automatic subconscious way. The recently introduced concept of compact internal representation (CIR) provides the ground for both the tasks. CIR is a specific cognitive map that compacts time-evolving situations into static structures containing information necessary for navigation. It belongs to the class of global approaches, i.e., it finds trajectories to a target when they exist but also detects situations when no solution can be found. Here we extend the concept of situations with mobile targets. Then using CIR as a core, we propose a closed-loop neural network architecture consisting of conscious and subconscious pathways for efficient decision-making. The conscious pathway provides solutions to novel situations if the default subconscious pathway fails to guide the agent to a target. Employing experiments with roving robots and numerical simulations, we show that the proposed architecture provides the robot with cognitive abilities and enables reliable and flexible navigation in realistic time-evolving environments. We prove that the subconscious pathway is robust against uncertainty in the sensory information. Thus if a novel situation is similar but not identical to the previous experience (because of, e.g., noisy perception) then the subconscious pathway is able to provide an effective solution.

  12. Quantum perceptron over a field and neural network architecture selection in a quantum computer.

    Science.gov (United States)

    da Silva, Adenilton José; Ludermir, Teresa Bernarda; de Oliveira, Wilson Rosa

    2016-04-01

    In this work, we propose a quantum neural network named quantum perceptron over a field (QPF). Quantum computers are not yet a reality and the models and algorithms proposed in this work cannot be simulated in actual (or classical) computers. QPF is a direct generalization of a classical perceptron and solves some drawbacks found in previous models of quantum perceptrons. We also present a learning algorithm named Superposition based Architecture Learning algorithm (SAL) that optimizes the neural network weights and architectures. SAL searches for the best architecture in a finite set of neural network architectures with linear time over the number of patterns in the training set. SAL is the first learning algorithm to determine neural network architectures in polynomial time. This speedup is obtained by the use of quantum parallelism and a non-linear quantum operator. Copyright © 2016 Elsevier Ltd. All rights reserved.

  13. Multithreaded Processors

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 20; Issue 9. Multithreaded Processors. Venkat Arun. General Article Volume 20 Issue 9 September 2015 pp 844-855. Fulltext. Click here to view fulltext PDF. Permanent link: http://www.ias.ac.in/article/fulltext/reso/020/09/0844-0855. Keywords.

  14. T-SDN architecture for space and ground integrated optical transport network

    Science.gov (United States)

    Nie, Kunkun; Hu, Wenjing; Gao, Shenghua; Chang, Chengwu

    2015-11-01

    Integrated optical transport network is the development trend of the future space information backbone network. The space and ground integrated optical transport network(SGIOTN) may contain a variety of equipment and systems. Changing the network or meeting some innovation missions in the network will be an expensive implement. Software Defined Network(SDN) provides a good solution to flexibly adding process logic, timely control states and resources of the whole network, as well as shielding the differences of heterogeneous equipment and so on. According to the characteristics of SGIOTN, we propose an transport SDN architecture for it, with hierarchical control plane and data plane composed of packet networks and optical transport networks.

  15. Multi-layer architecture for realization of network virtualization using MPLS technology

    Directory of Open Access Journals (Sweden)

    Ghasem Ahmadeyan Mazhin

    2017-03-01

    Full Text Available Network virtualization (NV increases Internet flexibility by separating policies from mechanisms. This makes developing new applications, managing the Internet, and supporting different applications much easier. In this study, we introduce a multi-layer architecture which combines multi-level multiprotocol label switching (MPLS technology with NV. The proposed architecture combines the high speed advantage of MPLS with the high flexibility of NV. We use MPLS in MPLS technique and encapsulate each MPLS packet within another when it encounters a new virtual network. Our architecture has the potential to improve Internet flexibility and pave the way for deployment and commercialization of NV in next generation networks.

  16. Metabolic network architecture and carbon source determine metabolite production costs.

    Science.gov (United States)

    Waschina, Silvio; D'Souza, Glen; Kost, Christian; Kaleta, Christoph

    2016-06-01

    Metabolism is essential to organismal life, because it provides energy and building block metabolites. Even though it is known that the biosynthesis of metabolites consumes a significant proportion of the resources available to a cell, the factors that determine their production costs remain less well understood. In this context, it is especially unclear how the nutritional environment affects the costs of metabolite production. Here, we use the amino acid metabolism of Escherichia coli as a model to show that the point at which a carbon source enters central metabolic pathways is a major determinant of individual metabolite production costs. Growth rates of auxotrophic genotypes, which in the presence of the required amino acid save biosynthetic costs, were compared to the growth rates that prototrophic cells achieved under the same conditions. The experimental results showed a strong concordance with computationally estimated biosynthetic costs, which allowed us, for the first time, to systematically quantify carbon source-dependent metabolite production costs. Thus, we demonstrate that the nutritional environment in combination with network architecture is an important but hitherto underestimated factor influencing biosynthetic costs and thus microbial growth. Our observations are highly relevant for the optimization of biotechnological processes as well as for understanding the ecology of microorganisms in their natural environments. © 2016 Federation of European Biochemical Societies.

  17. Predicting Electrocardiogram and Arterial Blood Pressure Waveforms with Different Echo State Network Architectures

    Science.gov (United States)

    2014-11-01

    Predicting Electrocardiogram and Arterial Blood Pressure Waveforms with Different Echo State Network Architectures Allan Fong, MS1,3, Ranjeev...the medical staff in Intensive Care Units. The ability to predict electrocardiogram and arterial blood pressure waveforms can potentially help the...type of neural network for mining, understanding, and predicting electrocardiogram and arterial blood pressure waveforms. Several network

  18. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural

  19. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  20. The middleware architecture supports heterogeneous network systems for module-based personal robot system

    Science.gov (United States)

    Choo, Seongho; Li, Vitaly; Choi, Dong Hee; Jung, Gi Deck; Park, Hong Seong; Ryuh, Youngsun

    2005-12-01

    On developing the personal robot system presently, the internal architecture is every module those occupy separated functions are connected through heterogeneous network system. This module-based architecture supports specialization and division of labor at not only designing but also implementation, as an effect of this architecture, it can reduce developing times and costs for modules. Furthermore, because every module is connected among other modules through network systems, we can get easy integrations and synergy effect to apply advanced mutual functions by co-working some modules. In this architecture, one of the most important technologies is the network middleware that takes charge communications among each modules connected through heterogeneous networks systems. The network middleware acts as the human nerve system inside of personal robot system; it relays, transmits, and translates information appropriately between modules that are similar to human organizations. The network middleware supports various hardware platform, heterogeneous network systems (Ethernet, Wireless LAN, USB, IEEE 1394, CAN, CDMA-SMS, RS-232C). This paper discussed some mechanisms about our network middleware to intercommunication and routing among modules, methods for real-time data communication and fault-tolerant network service. There have designed and implemented a layered network middleware scheme, distributed routing management, network monitoring/notification technology on heterogeneous networks for these goals. The main theme is how to make routing information in our network middleware. Additionally, with this routing information table, we appended some features. Now we are designing, making a new version network middleware (we call 'OO M/W') that can support object-oriented operation, also are updating program sources itself for object-oriented architecture. It is lighter, faster, and can support more operation systems and heterogeneous network systems, but other general

  1. Sentient networks

    Energy Technology Data Exchange (ETDEWEB)

    Chapline, G.

    1998-03-01

    The engineering problems of constructing autonomous networks of sensors and data processors that can provide alerts for dangerous situations provide a new context for debating the question whether man-made systems can emulate the cognitive capabilities of the mammalian brain. In this paper we consider the question whether a distributed network of sensors and data processors can form ``perceptions`` based on sensory data. Because sensory data can have exponentially many explanations, the use of a central data processor to analyze the outputs from a large ensemble of sensors will in general introduce unacceptable latencies for responding to dangerous situations. A better idea is to use a distributed ``Helmholtz machine`` architecture in which the sensors are connected to a network of simple processors, and the collective state of the network as a whole provides an explanation for the sensory data. In general communication within such a network will require time division multiplexing, which opens the door to the possibility that with certain refinements to the Helmholtz machine architecture it may be possible to build sensor networks that exhibit a form of artificial consciousness.

  2. Multithreading architecture

    CERN Document Server

    Nemirovsky, Mario

    2013-01-01

    Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computational resources, as a stall in one thread need not cause execution resources to be idle. This enables the computer architect to maximize performance within area constraints, power constraints, or energy constraints. However, the architectural options for the processor designer or architect looking to implement multithreading are quite extensive and

  3. Communications systems and methods for subsea processors

    Science.gov (United States)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  4. A Deep Generative Adversarial Architecture for Network-Wide Spatial-Temporal Traffic State Estimation

    OpenAIRE

    Liang, Yunyi; Cui, Zhiyong; Tian, Yu; Chen, Huimiao; Wang, Yinhai

    2018-01-01

    This study proposes a deep generative adversarial architecture (GAA) for network-wide spatial-temporal traffic state estimation. The GAA is able to combine traffic flow theory with neural networks and thus improve the accuracy of traffic state estimation. It consists of two Long Short-Term Memory Neural Networks (LSTM NNs) which capture correlation in time and space among traffic flow and traffic density. One of the LSTM NNs, called a discriminative network, aims to maximize the probability o...

  5. Enabling Wireless Power Transfer in Cellular Networks: Architecture, Modeling and Deployment

    OpenAIRE

    Huang, Kaibin; Lau, Vincent K. N.

    2012-01-01

    Microwave power transfer (MPT) delivers energy wirelessly from stations called power beacons (PBs) to mobile devices by microwave radiation. This provides mobiles practically infinite battery lives and eliminates the need of power cords and chargers. To enable MPT for mobile charging, this paper proposes a new network architecture that overlays an uplink cellular network with randomly deployed PBs for powering mobiles, called a hybrid network. The deployment of the hybrid network under an out...

  6. Modelling intracellular signalling networks using behaviour-based systems and the blackboard architecture

    OpenAIRE

    Perez, Pedro Pablo Gonzalez; Gershenson, Carlos; Garcia, Maura Cardenas; Otero, Jaime Lagunez

    2002-01-01

    This paper proposes to model the intracellular signalling networks using a fusion of behaviour-based systems and the blackboard architecture. In virtue of this fusion, the model developed by us, which has been named Cellulat, allows to take account two essential aspects of the intracellular signalling networks: (1) the cognitive capabilities of certain types of networks' components and (2) the high level of spatial organization of these networks. A simple example of modelling of Ca2+ signalli...

  7. Space Network IP Services (SNIS): An Architecture for Supporting Low Earth Orbiting IP Satellite Missions

    Science.gov (United States)

    Israel, David J.

    2005-01-01

    The NASA Space Network (SN) supports a variety of missions using the Tracking and Data Relay Satellite System (TDRSS), which includes ground stations in White Sands, New Mexico and Guam. A Space Network IP Services (SNIS) architecture is being developed to support future users with requirements for end-to-end Internet Protocol (IP) communications. This architecture will support all IP protocols, including Mobile IP, over TDRSS Single Access, Multiple Access, and Demand Access Radio Frequency (RF) links. This paper will describe this architecture and how it can enable Low Earth Orbiting IP satellite missions.

  8. A Novel Architecture for Adaptive Traffic Control in Network on Chip using Code Division Multiple Access Technique

    OpenAIRE

    Fatemeh. Dehghani; Shahram. Darooei

    2016-01-01

    Network on chip has emerged as a long-term and effective method in Multiprocessor System-on-Chip communications in order to overcome the bottleneck in bus based communication architectures. Efficiency and performance of network on chip is so dependent on the architecture and structure of the network. In this paper a new structure and architecture for adaptive traffic control in network on chip using Code Division Multiple Access technique is presented. To solve the problem of synchronous acce...

  9. A neural network architecture for implementation of expert systems for real time monitoring

    Science.gov (United States)

    Ramamoorthy, P. A.

    1991-01-01

    Since neural networks have the advantages of massive parallelism and simple architecture, they are good tools for implementing real time expert systems. In a rule based expert system, the antecedents of rules are in the conjunctive or disjunctive form. We constructed a multilayer feedforward type network in which neurons represent AND or OR operations of rules. Further, we developed a translator which can automatically map a given rule base into the network. Also, we proposed a new and powerful yet flexible architecture that combines the advantages of both fuzzy expert systems and neural networks. This architecture uses the fuzzy logic concepts to separate input data domains into several smaller and overlapped regions. Rule-based expert systems for time critical applications using neural networks, the automated implementation of rule-based expert systems with neural nets, and fuzzy expert systems vs. neural nets are covered.

  10. The TMS34010 graphic processor - an architecture for image visualization in NMR tomography; O processador grafico TMS34010 - uma arquitetura para visualizacao de imagem em tomografia por RMN

    Energy Technology Data Exchange (ETDEWEB)

    Slaets, Jan Frans Willem; Paiva, Maria Stela Veludo de; Almeida, Lirio O.B

    1989-12-31

    This abstract presents a description of the minimum system implemented with the graphic processor TMS34010, which will be used in the reconstruction, treatment and interpretation f images obtained by NMR tomography. The project is being developed in the LIE (Electronic Instrumentation Laboratory), of the Sao Carlos Chemistry and Physical Institute, S P, Brazil and is already in operation 4 refs., 7 figs.

  11. Hardware Trigger Processor for the MDT System

    CERN Document Server

    Costa De Paiva, Thiago; The ATLAS collaboration

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  12. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  13. Architecture and System Engineering Development Study of Space-Based Satellite Networks for NASA Missions

    Science.gov (United States)

    Ivancic, William D.

    2003-01-01

    Traditional NASA missions, both near Earth and deep space, have been stovepipe in nature and point-to-point in architecture. Recently, NASA and others have conceptualized missions that required space-based networking. The notion of networks in space is a drastic shift in thinking and requires entirely new architectures, radio systems (antennas, modems, and media access), and possibly even new protocols. A full system engineering approach for some key mission architectures will occur that considers issues such as the science being performed, stationkeeping, antenna size, contact time, data rates, radio-link power requirements, media access techniques, and appropriate networking and transport protocols. This report highlights preliminary architecture concepts and key technologies that will be investigated.

  14. Evolving Interoperable Network Architectures for NATO Coalition Forces

    National Research Council Canada - National Science Library

    Sowerbutts, Barry; Sharman, Richard; West, Mark

    2005-01-01

    .... Various factors, such as security, subnetworking, information management and mobility management for NATO requirements are examined in this light and a proposal made for a generic Defence Intranet Architecture (DIA...

  15. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  16. RoboSmith: Wireless Networked Architecture for Multiagent Robotic System

    OpenAIRE

    Florin Moldoveanu; Doru Ursutiu; Dan Floroian; Laura Floroian

    2010-01-01

    In this paper is presented an architecture for a flexible mini robot for a multiagent robotic system. In a multiagent system the value of an individual agent is negligible since the goal of the system is essential. Thus, the agents (robots) need to be small, low cost and cooperative. RoboSmith are designed based on these conditions. The proposed architecture divide a robot into functional modules such as locomotion, control, sensors, communication, and actuation. Any mobile robot can be const...

  17. 78 FR 40434 - Proposed Information Collection; Comment Request; Survey of Fish Processors and Disruptions...

    Science.gov (United States)

    2013-07-05

    ... Fish Processors and Disruptions Caused by Hurricane Sandy AGENCY: National Oceanic and Atmospheric... seeks to collect data on distribution networks and business practices from fish processors that process...

  18. ATLANTIDES: An Architecture for Alert Verification in Network Intrusion Detection Systems

    NARCIS (Netherlands)

    Bolzoni, D.; Crispo, Bruno; Etalle, Sandro

    We present an architecture designed for alert verification (i.e., to reduce false positives) in network intrusion-detection systems. Our technique is based on a systematic (and automatic) anomaly-based analysis of the system output, which provides useful context information regarding the network

  19. mCRAN: A radio access network architecture for 5G indoor ccommunications

    NARCIS (Netherlands)

    Chandra, Kishor; Cao, Zizheng; Bruintjes, Tom; Prasad, R.V.; Karagiannis, Georgios; Tangdiongga, E.; van den Boom, H.P.A.; Kokkeler, Andre B.J.

    2015-01-01

    Millimeter wave (mmWave) communication is being seen as a disruptive technology for 5G era. In particular, 60GHz frequency band has emerged as a promising candidate for multi-Gbps connectivity in indoor and hotspot areas. In terms of network architecture, cloud radio access network (CRAN) has

  20. Software for embedded processors: Problems and solutions

    Science.gov (United States)

    Bogaerts, J. A. C.

    1990-08-01

    Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I

  1. Requirements and System Architecture for a Healthcare Wireless Body Area Network

    DEFF Research Database (Denmark)

    Hansen, Finn Overgaard; Toftegaard, Thomas Skjødeberg

    Wireless body area networks enable new opportunities for personal healthcare monitoring and personal healthcare applications. This paper presents a comprehensive set of requirements and challenges for building a wireless body area network to support diverse user groups and a corresponding set...... of healthcare applications. Based on the identified requirements, the paper presents an architecture for a wireless body area network and describes how this architecture is connected to an existing it-infrastructure supporting healthcare at home. Finally the paper presents our on-going research with development...

  2. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    André B. J. Kokkeler

    2007-02-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  3. The Chameleon Architecture for Streaming DSP Applications

    Directory of Open Access Journals (Sweden)

    Heysters PaulM

    2007-01-01

    Full Text Available We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2 in a 130 nm process, is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC via a network interface (NI. Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT and best effort (BE. For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool.

  4. Design mobile satellite system architecture as an integral part of the cellular access digital network

    Science.gov (United States)

    Chien, E. S. K.; Marinho, J. A.; Russell, J. E., Sr.

    1988-01-01

    The Cellular Access Digital Network (CADN) is the access vehicle through which cellular technology is brought into the mainstream of the evolving integrated telecommunications network. Beyond the integrated end-to-end digital access and per call network services provisioning of the Integrated Services Digital Network (ISDN), the CADN engenders the added capability of mobility freedom via wireless access. One key element of the CADN network architecture is the standard user to network interface that is independent of RF transmission technology. Since the Mobile Satellite System (MSS) is envisioned to not only complement but also enhance the capabilities of the terrestrial cellular telecommunications network, compatibility and interoperability between terrestrial cellular and mobile satellite systems are vitally important to provide an integrated moving telecommunications network of the future. From a network standpoint, there exist very strong commonalities between the terrestrial cellular system and the mobile satellite system. Therefore, the MSS architecture should be designed as an integral part of the CADN. This paper describes the concept of the CADN, the functional architecture of the MSS, and the user-network interface signaling protocols.

  5. SANDS: a service-oriented architecture for clinical decision support in a National Health Information Network.

    Science.gov (United States)

    Wright, Adam; Sittig, Dean F

    2008-12-01

    In this paper, we describe and evaluate a new distributed architecture for clinical decision support called SANDS (Service-oriented Architecture for NHIN Decision Support), which leverages current health information exchange efforts and is based on the principles of a service-oriented architecture. The architecture allows disparate clinical information systems and clinical decision support systems to be seamlessly integrated over a network according to a set of interfaces and protocols described in this paper. The architecture described is fully defined and developed, and six use cases have been developed and tested using a prototype electronic health record which links to one of the existing prototype National Health Information Networks (NHIN): drug interaction checking, syndromic surveillance, diagnostic decision support, inappropriate prescribing in older adults, information at the point of care and a simple personal health record. Some of these use cases utilize existing decision support systems, which are either commercially or freely available at present, and developed outside of the SANDS project, while other use cases are based on decision support systems developed specifically for the project. Open source code for many of these components is available, and an open source reference parser is also available for comparison and testing of other clinical information systems and clinical decision support systems that wish to implement the SANDS architecture. The SANDS architecture for decision support has several significant advantages over other architectures for clinical decision support. The most salient of these are:

  6. Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Luis Parrilla

    2018-01-01

    Full Text Available Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

  7. Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.

    Science.gov (United States)

    Parrilla, Luis; Castillo, Encarnación; López-Ramos, Juan A; Álvarez-Bermejo, José A; García, Antonio; Morales, Diego P

    2018-01-16

    Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

  8. Hybrid SDN Architecture for Resource Consolidation in MPLS Networks

    DEFF Research Database (Denmark)

    Katov, Anton Nikolaev; Mihovska, Albena D.; Prasad, Neeli R.

    2015-01-01

    This paper proposes a methodology for resource consolidation towards minimizing the power consumption in a large network, with a substantial resource overprovisioning. The focus is on the operation of the core MPLS networks. The proposed approach is based on a software defined networking (SDN...

  9. Processor Cache

    NARCIS (Netherlands)

    P.A. Boncz (Peter); L. Liu (Lei); M. Tamer Özsu

    2008-01-01

    htmlabstractTo hide the high latencies of DRAM access, modern computer architecture now features a memory hierarchy that besides DRAM also includes SRAM cache memories, typically located on the CPU chip. Memory access first check these caches, which takes only a few cycles. Only if the needed data

  10. Comparison of different artificial neural network architectures in modeling of Chlorella sp. flocculation.

    Science.gov (United States)

    Zenooz, Alireza Moosavi; Ashtiani, Farzin Zokaee; Ranjbar, Reza; Nikbakht, Fatemeh; Bolouri, Oberon

    2017-07-03

    Biodiesel production from microalgae feedstock should be performed after growth and harvesting of the cells, and the most feasible method for harvesting and dewatering of microalgae is flocculation. Flocculation modeling can be used for evaluation and prediction of its performance under different affective parameters. However, the modeling of flocculation in microalgae is not simple and has not performed yet, under all experimental conditions, mostly due to different behaviors of microalgae cells during the process under different flocculation conditions. In the current study, the modeling of microalgae flocculation is studied with different neural network architectures. Microalgae species, Chlorella sp., was flocculated with ferric chloride under different conditions and then the experimental data modeled using artificial neural network. Neural network architectures of multilayer perceptron (MLP) and radial basis function architectures, failed to predict the targets successfully, though, modeling was effective with ensemble architecture of MLP networks. Comparison between the performances of the ensemble and each individual network explains the ability of the ensemble architecture in microalgae flocculation modeling.

  11. A cluster-based architecture to structure the topology of parallel wireless sensor networks.

    Science.gov (United States)

    Lloret, Jaime; Garcia, Miguel; Bri, Diana; Diaz, Juan R

    2009-01-01

    A wireless sensor network is a self-configuring network of mobile nodes connected by wireless links where the nodes have limited capacity and energy. In many cases, the application environment requires the design of an exclusive network topology for a particular case. Cluster-based network developments and proposals in existence have been designed to build a network for just one type of node, where all nodes can communicate with any other nodes in their coverage area. Let us suppose a set of clusters of sensor nodes where each cluster is formed by different types of nodes (e.g., they could be classified by the sensed parameter using different transmitting interfaces, by the node profile or by the type of device: laptops, PDAs, sensor etc.) and exclusive networks, as virtual networks, are needed with the same type of sensed data, or the same type of devices, or even the same type of profiles. In this paper, we propose an algorithm that is able to structure the topology of different wireless sensor networks to coexist in the same environment. It allows control and management of the topology of each network. The architecture operation and the protocol messages will be described. Measurements from a real test-bench will show that the designed protocol has low bandwidth consumption and also demonstrates the viability and the scalability of the proposed architecture. Our ccluster-based algorithm is compared with other algorithms reported in the literature in terms of architecture and protocol measurements.

  12. Analog parallel processor hardware for high speed pattern recognition

    Science.gov (United States)

    Daud, T.; Tawel, R.; Langenbacher, H.; Eberhardt, S. P.; Thakoor, A. P.

    1990-01-01

    A VLSI-based analog processor for fully parallel, associative, high-speed pattern matching is reported. The processor consists of two main components: an analog memory matrix for storage of a library of patterns, and a winner-take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied to a WTA network for determination of the closest match. Patterns with up to 22 percent overlap are successfully classified with a WTA settling time of less than 10 microsec. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 10 exp 9 bits per second for a large memory.

  13. Reference Architecture for Multi-Layer Software Defined Optical Data Center Networks

    Directory of Open Access Journals (Sweden)

    Casimer DeCusatis

    2015-09-01

    Full Text Available As cloud computing data centers grow larger and networking devices proliferate; many complex issues arise in the network management architecture. We propose a framework for multi-layer; multi-vendor optical network management using open standards-based software defined networking (SDN. Experimental results are demonstrated in a test bed consisting of three data centers interconnected by a 125 km metropolitan area network; running OpenStack with KVM and VMW are components. Use cases include inter-data center connectivity via a packet-optical metropolitan area network; intra-data center connectivity using an optical mesh network; and SDN coordination of networking equipment within and between multiple data centers. We create and demonstrate original software to implement virtual network slicing and affinity policy-as-a-service offerings. Enhancements to synchronous storage backup; cloud exchanges; and Fibre Channel over Ethernet topologies are also discussed.

  14. Network Coding Parallelization Based on Matrix Operations for Multicore Architectures

    DEFF Research Database (Denmark)

    Wunderlich, Simon; Cabrera, Juan; Fitzek, Frank

    2015-01-01

    such as the Raspberry Pi2 with four cores in the order of up to one full magnitude. The speed increase gain is even higher than the number of cores of the Raspberry Pi2 since the newly introduced approach exploits the cache architecture way better than by-the-book matrix operations. Copyright © 2015 by the Institute...

  15. Towards Horizontal Architecture for Autonomic M2M Service Networks

    Directory of Open Access Journals (Sweden)

    Juhani Latvakoski

    2014-05-01

    Full Text Available Today, increasing number of industrial application cases rely on the Machine to Machine (M2M services exposed from physical devices. Such M2M services enable interaction of physical world with the core processes of company information systems. However, there are grand challenges related to complexity and “vertical silos” limiting the M2M market scale and interoperability. It is here expected that horizontal approach for the system architecture is required for solving these challenges. Therefore, a set of architectural principles and key enablers for the horizontal architecture have been specified in this work. A selected set of key enablers called as autonomic M2M manager, M2M service capabilities, M2M messaging system, M2M gateways towards energy constrained M2M asset devices and creation of trust to enable end-to-end security for M2M applications have been developed. The developed key enablers have been evaluated separately in different scenarios dealing with smart metering, car sharing and electric bike experiments. The evaluation results shows that the provided architectural principles, and developed key enablers establish a solid ground for future research and seem to enable communication between objects and applications, which are not initially been designed to communicate together. The aim as the next step in this research is to create a combined experimental system to evaluate the system interoperability and performance in a more detailed manner.

  16. Multi-layered Security Approaches for a Modular Open Network Architecture-based Satellite

    OpenAIRE

    Shirley, Brandon; Young, Quinn; Wegner, Peter; Christensen, Jacob; Janicik, Jeffrey

    2014-01-01

    A growing trend in satellite development includes shortening the development lifecycle for hardware and software, cost reduction, and promoting reuse for future missions. Department of Defense (DoD) acquisition policies mandate system providers use Open Systems Architecture (OSA) where feasible. Modular Open Network Architecture (MONA) is a subset of OSA and paves the way to achieve cost reduction and reuse during a reduced development lifecycle. MONA approaches provide opportunities to enhan...

  17. ARCHITECTURES AND ALGORITHMS FOR COGNITIVE NETWORKS ENABLED BY QUALITATIVE MODELS

    DEFF Research Database (Denmark)

    Balamuralidhar, P.

    2013-01-01

    Complexity of communication networks is ever increasing and getting complicated by their heterogeneity and dynamism. Traditional techniques are facing challenges in network performance management. Cognitive networking is an emerging paradigm to make networks more intelligent, thereby overcoming...... traditional limitations and potentially achieving better performance. The vision is that, networks should be able to monitor themselves, reason upon changes in self and environment, act towards the achievement of specific goals and learn from experience. The concept of a Cognitive Engine (CE) supporting...... cognitive functions, as part of network elements, enabling above said autonomic capabilities is gathering attention. Awareness of the self and the world is an important aspect of the cognitive engine to be autonomic. This is achieved through embedding their models in the engine, but the complexity...

  18. Softwarization of Mobile Network Functions towards Agile and Energy Efficient 5G Architectures: A Survey

    Directory of Open Access Journals (Sweden)

    Dlamini Thembelihle

    2017-01-01

    Full Text Available Future mobile networks (MNs are required to be flexible with minimal infrastructure complexity, unlike current ones that rely on proprietary network elements to offer their services. Moreover, they are expected to make use of renewable energy to decrease their carbon footprint and of virtualization technologies for improved adaptability and flexibility, thus resulting in green and self-organized systems. In this article, we discuss the application of software defined networking (SDN and network function virtualization (NFV technologies towards softwarization of the mobile network functions, taking into account different architectural proposals. In addition, we elaborate on whether mobile edge computing (MEC, a new architectural concept that uses NFV techniques, can enhance communication in 5G cellular networks, reducing latency due to its proximity deployment. Besides discussing existing techniques, expounding their pros and cons and comparing state-of-the-art architectural proposals, we examine the role of machine learning and data mining tools, analyzing their use within fully SDN- and NFV-enabled mobile systems. Finally, we outline the challenges and the open issues related to evolved packet core (EPC and MEC architectures.

  19. Marginally Stable Triangular Recurrent Neural Network Architecture for Time Series Prediction.

    Science.gov (United States)

    Sivakumar, Seshadri; Sivakumar, Shyamala

    2017-09-25

    This paper introduces a discrete-time recurrent neural network architecture using triangular feedback weight matrices that allows a simplified approach to ensuring network and training stability. The triangular structure of the weight matrices is exploited to readily ensure that the eigenvalues of the feedback weight matrix represented by the block diagonal elements lie on the unit circle in the complex z-plane by updating these weights based on the differential of the angular error variable. Such placement of the eigenvalues together with the extended close interaction between state variables facilitated by the nondiagonal triangular elements, enhances the learning ability of the proposed architecture. Simulation results show that the proposed architecture is highly effective in time-series prediction tasks associated with nonlinear and chaotic dynamic systems with underlying oscillatory modes. This modular architecture with dual upper and lower triangular feedback weight matrices mimics fully recurrent network architectures, while maintaining learning stability with a simplified training process. While training, the block-diagonal weights (hence the eigenvalues) of the dual triangular matrices are constrained to the same values during weight updates aimed at minimizing the possibility of overfitting. The dual triangular architecture also exploits the benefit of parsing the input and selectively applying the parsed inputs to the two subnetworks to facilitate enhanced learning performance.

  20. A Study of Artificial Neural Network Architectures for Othello Evaluation Functions

    Science.gov (United States)

    Binkley, Kevin J.; Seehart, Ken; Hagiwara, Masafumi

    In this study, we use temporal difference learning (TDL) to investigate the ability of 20 different artificial neural network (ANN) architectures to learn othello game board evaluation functions. The ANN evaluation functions are applied to create a strong othello player using only 1-ply search. In addition to comparing many of the ANN architectures seen in the literature, we introduce several new architectures that consider the game board symmetry. Both embedding the game board symmetry into the network architecture through weight sharing and the outright removal of symmetry through symmetry removal are explored. Experiments varying the number of inputs per game board square from one to three, the number of hidden nodes, and number of hidden layers are also performed. We found it advantageous to consider game board symmetry in the form of symmetry by weight sharing; and that an input encoding of three inputs per square outperformed the one input per square encoding that is commonly seen in the literature. Furthermore, architectures with only one hidden layer were strongly outperformed by architectures with multiple hidden layers. A standard weighted-square board heuristic evaluation function from the literature was used to evaluate the quality of the trained ANN othello players. One of the ANN architectures introduced in this study, an ANN implementing weight sharing and consisting of three hidden layers, using only a 1-ply search, outperformed a weighted-square test heuristic player using a 6-ply minimax search.

  1. A Novel Buffer Management Architecture for Epidemic Routing in Delay Tolerant Networks (DTNs)

    KAUST Repository

    Elwhishi, Ahmed

    2010-11-17

    Delay tolerant networks (DTNs) are wireless networks in which an end-to-end path for a given node pair can never exist for an extended period. It has been reported as a viable approach in launching multiple message replicas in order to increase message delivery ratio and reduce message delivery delay. This advantage, nonetheless, is at the expense of taking more buffer space at each node. The combination of custody and replication entails high buffer and bandwidth overhead. This paper investigates a new buffer management architecture for epidemic routing in DTNs, which helps each node to make a decision on which message should be forwarded or dropped. The proposed buffer management architecture is characterized by a suite of novel functional modules, including Summary Vector Exchange Module (SVEM), Networks State Estimation Module (NSEM), and Utility Calculation Module (UCM). Extensive simulation results show that the proposed buffer management architecture can achieve superb performance against its counterparts in terms of delivery ratio and delivery delay.

  2. Time Shared Optical Network (TSON): a novel metro architecture for flexible multi-granular services.

    Science.gov (United States)

    Zervas, Georgios S; Triay, Joan; Amaya, Norberto; Qin, Yixuan; Cervelló-Pastor, Cristina; Simeonidou, Dimitra

    2011-12-12

    This paper presents the Time Shared Optical Network (TSON) as metro mesh network architecture for guaranteed, statistically-multiplexed services. TSON proposes a flexible and tunable time-wavelength assignment along with one-way tree-based reservation and node architecture. It delivers guaranteed sub-wavelength and multi-granular network services without wavelength conversion, time-slice interchange and optical buffering. Simulation results demonstrate high network utilization, fast service delivery, and low end-to-end delay on a contention-free sub-wavelength optical transport network. In addition, implementation complexity in terms of Layer 2 aggregation, grooming and optical switching has been evaluated. © 2011 Optical Society of America

  3. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Wiatr Kazimierz

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  4. An architecture including network QoS in scientific workflows

    NARCIS (Netherlands)

    Zhao, Z.; Grosso, P.; Koning, R.; van der Ham, J.; de Laat, C.

    2010-01-01

    The quality of the network services has so far rarely been considered in composing and executing scientific workflows. Currently, scientific applications tune the execution quality of workflows neglecting network resources, and by selecting only optimal software services and computing resources. One

  5. Experimental species removals impact the architecture of pollination networks.

    Science.gov (United States)

    Brosi, Berry J; Niezgoda, Kyle; Briggs, Heather M

    2017-06-01

    Mutualistic networks are key for the creation and maintenance of biodiversity, yet are threatened by global environmental change. Most simulation models assume that network structure remains static after species losses, despite theoretical and empirical reasons to expect dynamic responses. We assessed the effects of experimental single bumblebee species removals on the structure of entire flower visitation networks. We hypothesized that network structure would change following processes linking interspecific competition with dietary niche breadth. We found that single pollinator species losses impact pollination network structure: resource complementarity decreased, while resource overlap increased. Despite marginally increased connectance, fewer plant species were visited after species removals. These changes may have negative functional impacts, as complementarity is important for maintaining biodiversity-ecological functioning relationships and visitation of rare plant species is critical for maintaining diverse plant communities. © 2017 The Author(s).

  6. Experiments on neural network architectures for fuzzy logic

    Science.gov (United States)

    Keller, James M.

    1991-01-01

    The use of fuzzy logic to model and manage uncertainty in a rule-based system places high computational demands on an inference engine. In an earlier paper, the authors introduced a trainable neural network structure for fuzzy logic. These networks can learn and extrapolate complex relationships between possibility distributions for the antecedents and consequents in the rules. Here, the power of these networks is further explored. The insensitivity of the output to noisy input distributions (which are likely if the clauses are generated from real data) is demonstrated as well as the ability of the networks to internalize multiple conjunctive clause and disjunctive clause rules. Since different rules with the same variables can be encoded in a single network, this approach to fuzzy logic inference provides a natural mechanism for rule conflict resolution.

  7. A Combined Network Architecture Using Art2 and Back Propagation for Adaptive Estimation of Dynamic Processes

    Directory of Open Access Journals (Sweden)

    Einar Sørheim

    1990-10-01

    Full Text Available A neural network architecture called ART2/BP is proposed. Thc goal has been to construct an artificial neural network that learns incrementally an unknown mapping, and is motivated by the instability found in back propagation (BP networks: after first learning pattern A and then pattern B, a BP network often has completely 'forgotten' pattern A. A network using both supervised and unsupervised training is proposed, consisting of a combination of ART2 and BP. ART2 is used to build and focus a supervised backpropagation network consisting of many small subnetworks each specialized on a particular domain of the input space. The ART2/BP network has the advantage of being able to dynamically expand itself in response to input patterns containing new information. Simulation results show that the ART2/BP network outperforms a classical maximum likelihood method for the estimation of a discrete dynamic and nonlinear transfer function.

  8. An Architectural Concept for Intrusion Tolerance in Air Traffic Networks

    Science.gov (United States)

    Maddalon, Jeffrey M.; Miner, Paul S.

    2003-01-01

    The goal of an intrusion tolerant network is to continue to provide predictable and reliable communication in the presence of a limited num ber of compromised network components. The behavior of a compromised network component ranges from a node that no longer responds to a nod e that is under the control of a malicious entity that is actively tr ying to cause other nodes to fail. Most current data communication ne tworks do not include support for tolerating unconstrained misbehavio r of components in the network. However, the fault tolerance communit y has developed protocols that provide both predictable and reliable communication in the presence of the worst possible behavior of a limited number of nodes in the system. One may view a malicious entity in a communication network as a node that has failed and is behaving in an arbitrary manner. NASA/Langley Research Center has developed one such fault-tolerant computing platform called SPIDER (Scalable Proces sor-Independent Design for Electromagnetic Resilience). The protocols and interconnection mechanisms of SPIDER may be adapted to large-sca le, distributed communication networks such as would be required for future Air Traffic Management systems. The predictability and reliabi lity guarantees provided by the SPIDER protocols have been formally v erified. This analysis can be readily adapted to similar network stru ctures.

  9. The Hi-Ring Architecture for Data Center Networks

    DEFF Research Database (Denmark)

    Kamchevska, Valerija; Ding, Yunhong; Berger, Michael Stübert

    2018-01-01

    Optical technologies have long been used for standard telecom applications ranging from long haul to metro and access networks. With the rapid expansion of traffic in data center networks, the deployment of optical technologies for computationally intensive short reach networking has attracted...... greatly be reduced as there is no need to perform operations like electrical demultiplexing of high-speed data streams. Moreover, simultaneous switching of wavelength channels using an optical circuit switch yields energy-efficient operation, which is crucial to data centers....

  10. Context Aware Routing Management Architecture for Airborne Networks

    Science.gov (United States)

    2012-03-22

    Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IPSec Internet Protocol Security . . . . . . . . . . . . . . . . . . . . . . . . . 14...encryption standards such as Internet Protocol Security ( IPSec ). Using this technique, red-network traffic is going to be optimized and prioritized

  11. Research on the Architecture of a Basic Reconfigurable Information Communication Network

    Directory of Open Access Journals (Sweden)

    Ruimin Wang

    2013-01-01

    Full Text Available The current information network cannot fundamentally meet some urgent requirements, such as providing ubiquitous information services and various types of heterogeneous network, supporting diverse and comprehensive network services, possessing high quality communication effects, ensuring the security and credibility of information interaction, and implementing effective supervisory control. This paper provides the theory system for the basic reconfigurable information communication network based on the analysis of present problems on the Internet and summarizes the root of these problems. It also provides an in-depth discussion about the related technologies and the prime components of the architecture.

  12. Heterogeneous Multicore Processor Technologies for Embedded Systems

    CERN Document Server

    Uchiyama, Kunio; Kasahara, Hironori; Nojiri, Tohru; Noda, Hideyuki; Tawara, Yasuhiro; Idehara, Akio; Iwata, Kenichi; Shikano, Hiroaki

    2012-01-01

    To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-p...

  13. SCAN secure processor and its biometric capabilities

    Science.gov (United States)

    Kannavara, Raghudeep; Mertoguno, Sukarno; Bourbakis, Nikolaos

    2011-04-01

    This paper presents the design of the SCAN secure processor and its extended instruction set to enable secure biometric authentication. The SCAN secure processor is a modified SparcV8 processor architecture with a new instruction set to handle voice, iris, and fingerprint-based biometric authentication. The algorithms for processing biometric data are based on the local global graph methodology. The biometric modules are synthesized in reconfigurable logic and the results of the field-programmable gate array (FPGA) synthesis are presented. We propose to implement the above-mentioned modules in an off-chip FPGA co-processor. Further, the SCAN-secure processor will offer a SCAN-based encryption and decryption of 32 bit instructions and data.

  14. Architecture and Applications of Functional Three-Dimensional Graphene Networks

    DEFF Research Database (Denmark)

    Dey, Ramendra Sundar; Chi, Qijin

    2015-01-01

    building blocksfor the bottom-up architecture of various graphene based nanomaterials. Th eassembly of functionalized GNS into three-dimensional (3D) porous graphenenetworks represents a novel approach. Resulting 3D porous graphene materialsposses unique physicochemical properties such as large surface...... based on the accomplishmentsrecently reported. Th e chapter will include: (1) a brief introduction to grapheneand its nanocomposites, (2) the major methods to assemble 3D porous graphenenetworks, (3) structural characteristics of 3D porous graphene, (4) some typicalexamples of their applications...

  15. TopoGen: A Network Topology Generation Architecture with application to automating simulations of Software Defined Networks

    CERN Document Server

    Laurito, Andres; The ATLAS collaboration

    2017-01-01

    Simulation is an important tool to validate the performance impact of control decisions in Software Defined Networks (SDN). Yet, the manual modeling of complex topologies that may change often during a design process can be a tedious error-prone task. We present TopoGen, a general purpose architecture and tool for systematic translation and generation of network topologies. TopoGen can be used to generate network simulation models automatically by querying information available at diverse sources, notably SDN controllers. The DEVS modeling and simulation framework facilitates a systematic translation of structured knowledge about a network topology into a formal modular and hierarchical coupling of preexisting or new models of network entities (physical or logical). TopoGen can be flexibly extended with new parsers and generators to grow its scope of applicability. This permits to design arbitrary workflows of topology transformations. We tested TopoGen in a network engineering project for the ATLAS detector ...

  16. TopoGen: A Network Topology Generation Architecture with application to automating simulations of Software Defined Networks

    CERN Document Server

    Laurito, Andres; The ATLAS collaboration

    2018-01-01

    Simulation is an important tool to validate the performance impact of control decisions in Software Defined Networks (SDN). Yet, the manual modeling of complex topologies that may change often during a design process can be a tedious error-prone task. We present TopoGen, a general purpose architecture and tool for systematic translation and generation of network topologies. TopoGen can be used to generate network simulation models automatically by querying information available at diverse sources, notably SDN controllers. The DEVS modeling and simulation framework facilitates a systematic translation of structured knowledge about a network topology into a formal modular and hierarchical coupling of preexisting or new models of network entities (physical or logical). TopoGen can be flexibly extended with new parsers and generators to grow its scope of applicability. This permits to design arbitrary workflows of topology transformations. We tested TopoGen in a network engineering project for the ATLAS detector ...

  17. The architecture of antagonistic networks: Node degree distribution, compartmentalization and nestedness

    Directory of Open Access Journals (Sweden)

    Savannah Nuwagaba

    2015-12-01

    Full Text Available Describing complex ecosystems as networks of interacting components has proved fruitful - revealing many distinctive patterns and dynamics of ecological systems. Of these patterns, three have often been brought up in literature, including species degree distribution, compartmentalization and nestedness, due largely to their implications for the functionality and stability of communities. Here, using 61 empirical antagonistic networks, we aim to settle the inconsistency in literature by (i fitting their node degree distributions to five different parametric models and identifying the one fits the best, (ii measuring the levels of nestedness and compartmentalization of these 61 networks and testing their significance using different null models, and (iii exploring how network connectance affects these three network architecture metrics. This research showed that most antagonistic networks do not display power law degree distributions and that resource species are generally uniformly distributed. We also clearly showed that the conclusion of whether a network is significantly compartmentalized or nested depends largely on the null model used.

  18. Genes and networks regulating root anatomy and architecture.

    Science.gov (United States)

    Wachsman, Guy; Sparks, Erin E; Benfey, Philip N

    2015-10-01

    The root is an excellent model for studying developmental processes that underlie plant anatomy and architecture. Its modular structure, the lack of cell movement and relative accessibility to microscopic visualization facilitate research in a number of areas of plant biology. In this review, we describe several examples that demonstrate how cell type-specific developmental mechanisms determine cell fate and the formation of defined tissues with unique characteristics. In the last 10 yr, advances in genome-wide technologies have led to the sequencing of thousands of plant genomes, transcriptomes and proteomes. In parallel with the development of these high-throughput technologies, biologists have had to establish computational, statistical and bioinformatic tools that can deal with the wealth of data generated by them. These resources provide a foundation for posing more complex questions about molecular interactions, and have led to the discovery of new mechanisms that control phenotypic differences. Here we review several recent studies that shed new light on developmental processes, which are involved in establishing root anatomy and architecture. We highlight the power of combining large-scale experiments with classical techniques to uncover new pathways in root development. © 2015 The Authors. New Phytologist © 2015 New Phytologist Trust.

  19. Self-growing neural network architecture using crisp and fuzzy entropy

    Science.gov (United States)

    Cios, Krzysztof J.

    1992-01-01

    The paper briefly describes the self-growing neural network algorithm, CID2, which makes decision trees equivalent to hidden layers of a neural network. The algorithm generates a feedforward architecture using crisp and fuzzy entropy measures. The results of a real-life recognition problem of distinguishing defects in a glass ribbon and of a benchmark problem of differentiating two spirals are shown and discussed.

  20. An Architecture for Coexistence with Multiple Users in Frequency Hopping Cognitive Radio Networks

    Science.gov (United States)

    2013-03-01

    delivered in hardware. The implementation studied in [27] uses sensing bits to quantize a likelihood ratio ( LR ) for determining which nodes have enough...worthwhile information to disseminate through the network. Using LRs is thereby a means for reducing meaningless observation traffic within the network...itself. The architecture itself consists of eight sub-components: database interface, spectrum map parser , map distributor, clustering, map merger

  1. A Novel Airborne Self-organising Architecture for 5G+ Networks

    OpenAIRE

    Ahmadi, Hamed; Katzis, Konstantinos; Shakir, Muhammad Zeeshan

    2017-01-01

    Network Flying Platforms (NFPs) such as unmanned aerial vehicles, unmanned balloons or drones flying at low/medium/high altitude can be employed to enhance network coverage and capacity by deploying a swarm of flying platforms that implement novel radio resource management techniques. In this paper, we propose a novel layered architecture where NFPs, of various types and flying at low/medium/high layers in a swarm of flying platforms, are considered as an integrated part of the future cellula...

  2. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  3. A self-organized artificial neural network architecture for sensory integration with applications to letter-phoneme integration

    OpenAIRE

    Jantvik, Tamas; Gustafsson, Lennart; Paplinski, Andrew

    2011-01-01

    The multimodal self-organizing network (MMSON), an artificial neural network architecture carrying out sensory integration, is presented here. The architecture is designed using neurophysiological findings and imaging studies that pertain to sensory integration and consists of interconnected lattices of artificial neurons. In this artificial neural architecture, the degree of recognition of stimuli, that is, the perceived reliability of stimuli in the various subnetworks, is included in the c...

  4. Modeling, analysis and optimization of network-on-chip communication architectures

    CERN Document Server

    Ogras, Umit Y

    2013-01-01

    Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures. This book explores outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

  5. FemtoNode: Reconfigurable and Customizable Architecture for Wireless Sensor Networks

    Science.gov (United States)

    Allgayer, Rodrigo Schmidt; Götz, Marcelo; Pereira, Carlos Eduardo

    With the growth and the development of new applications for Wireless Sensor Networks (WSN), sensor nodes are able to handle more complex events that require higher processing performance and hardware flexibility. These new features intend to meet the requirements of various applications, as well as to provide customized platforms that have only the needed resources. WSNs often need a flexible architecture able to adapt to design and environment changes. The use of reconfigurable architectures is an alternative to bring more flexibility and more processing capability for the sensor node. This paper proposes a reconfigurable and customizable sensor node called FemtoNode which has a reconfigurable platform and a wireless module to support applications for WSNs, using an object-oriented language Java as specification language of its architecture. The proposed concepts were validated with a case study of an heterogeneous wireless sensor network composed of sensors nodes based on different platforms, whose results are described in this work.

  6. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  7. Habitat loss alters the architecture of plant--pollinator interaction networks.

    Science.gov (United States)

    Spiesman, Brian J; Inouye, Brian D

    2013-12-01

    Habitat loss can have a negative effect on the number, abundance, and composition of species in plant-pollinator communities. Although we have a general understanding of the negative consequences of habitat loss for biodiversity, much less is known about the resulting effects on the pattern of interactions in mutualistic networks. Ecological networks formed by mutualistic interactions often exhibit a highly nested architecture with low modularity, especially in comparison with antagonistic networks. These patterns of interaction are thought to confer stability on mutualistic communities. With the growing threat of environmental change, it is important to expand our understanding of the factors that affect biodiversity and the stability of the communities that provide critical ecosystem functions and services. We studied the effects of habitat loss on plant--pollinator network architecture and found that regional habitat loss contributes directly to species loss and indirectly to the reorganization of interspecific interactions in a local community. Networks became more highly connected and more modular with habitat loss. Species richness and abundance were the primary drivers of variation in network architecture, though species compositi n affected modularity. Theory suggests that an increase in modularity with habitat loss will threaten community stability, which may contribute to an extinction debt in communities already affected by habitat loss.

  8. Cluster based architecture and network maintenance protocol for medical priority aware cognitive radio based hospital.

    Science.gov (United States)

    Al Mamoon, Ishtiak; Muzahidul Islam, A K M; Baharun, Sabariah; Ahmed, Ashir; Komaki, Shozo

    2016-08-01

    Due to the rapid growth of wireless medical devices in near future, wireless healthcare services may face some inescapable issue such as medical spectrum scarcity, electromagnetic interference (EMI), bandwidth constraint, security and finally medical data communication model. To mitigate these issues, cognitive radio (CR) or opportunistic radio network enabled wireless technology is suitable for the upcoming wireless healthcare system. The up-to-date research on CR based healthcare has exposed some developments on EMI and spectrum problems. However, the investigation recommendation on system design and network model for CR enabled hospital is rare. Thus, this research designs a hierarchy based hybrid network architecture and network maintenance protocols for previously proposed CR hospital system, known as CogMed. In the previous study, the detail architecture of CogMed and its maintenance protocols were not present. The proposed architecture includes clustering concepts for cognitive base stations and non-medical devices. Two cluster head (CH selector equations are formulated based on priority of location, device, mobility rate of devices and number of accessible channels. In order to maintain the integrity of the proposed network model, node joining and node leaving protocols are also proposed. Finally, the simulation results show that the proposed network maintenance time is very low for emergency medical devices (average maintenance period 9.5 ms) and the re-clustering effects for different mobility enabled non-medical devices are also balanced.

  9. A multi-tiered architecture for content retrieval in mobile peer-to-peer networks.

    Science.gov (United States)

    2012-01-01

    In this paper, we address content retrieval in Mobile Peer-to-Peer (P2P) Networks. We design a multi-tiered architecture for content : retrieval, where at Tier 1, we design a protocol for content similarity governed by a parameter that trades accu...

  10. A high level architecture for personalized learning in collaborative networks

    NARCIS (Netherlands)

    Afsarmanesh, H.; Tanha, J.

    2010-01-01

    In Collaborative Network (CN) environments, creation of collective understanding about both the aimed outcome and the procedure for achieving it by its members is the antecedent to any successful co-working and co-development. While a part of the common CN knowledge is pre-existing to its

  11. Signatures of arithmetic simplicity in metabolic network architecture.

    Directory of Open Access Journals (Sweden)

    William J Riehl

    2010-04-01

    Full Text Available Metabolic networks perform some of the most fundamental functions in living cells, including energy transduction and building block biosynthesis. While these are the best characterized networks in living systems, understanding their evolutionary history and complex wiring constitutes one of the most fascinating open questions in biology, intimately related to the enigma of life's origin itself. Is the evolution of metabolism subject to general principles, beyond the unpredictable accumulation of multiple historical accidents? Here we search for such principles by applying to an artificial chemical universe some of the methodologies developed for the study of genome scale models of cellular metabolism. In particular, we use metabolic flux constraint-based models to exhaustively search for artificial chemistry pathways that can optimally perform an array of elementary metabolic functions. Despite the simplicity of the model employed, we find that the ensuing pathways display a surprisingly rich set of properties, including the existence of autocatalytic cycles and hierarchical modules, the appearance of universally preferable metabolites and reactions, and a logarithmic trend of pathway length as a function of input/output molecule size. Some of these properties can be derived analytically, borrowing methods previously used in cryptography. In addition, by mapping biochemical networks onto a simplified carbon atom reaction backbone, we find that properties similar to those predicted for the artificial chemistry hold also for real metabolic networks. These findings suggest that optimality principles and arithmetic simplicity might lie beneath some aspects of biochemical complexity.

  12. Dynamic Adaptive Neural Network Arrays: A Neuromorphic Architecture

    Energy Technology Data Exchange (ETDEWEB)

    Disney, Adam [University of Tennessee (UT); Reynolds, John [University of Tennessee (UT)

    2015-01-01

    Dynamic Adaptive Neural Network Array (DANNA) is a neuromorphic hardware implementation. It differs from most other neuromorphic projects in that it allows for programmability of structure, and it is trained or designed using evolutionary optimization. This paper describes the DANNA structure, how DANNA is trained using evolutionary optimization, and an application of DANNA to a very simple classification task.

  13. Architecture of the rat nephron-arterial network

    DEFF Research Database (Denmark)

    Marsh, Donald J; Postnov, Dmitry D; Rowland, Douglas

    2017-01-01

    Among solid organs the kidney's vascular network stands out because each nephron has 2 distinct capillary structures in series, and because tubuloglomerular feedback (TGF), one of the mechanisms responsible for blood flow autoregulation, is specific to renal tubules. TGF and the myogenic mechanism...

  14. Validation of Bosch' Mobile Communication NetworkArchitecture with SPIN

    NARCIS (Netherlands)

    Ruys, T.C.; Langerak, Romanus

    This paper discusses validation projects carried out for the Mobile Communication Division of Robert Bosch GmbH. We verified parts of their Mobile Communication Network (MCNet), a communication system which is to be used in infotainment systems of future cars. The protocols of the MCNet have been

  15. Network Architecture of a Packet-switched WDM

    NARCIS (Netherlands)

    Dey, D.; Koonen, A.M.J.; Salvador, M.R.

    2000-01-01

    We propose a packet-switched WDM slotted ring network with destination release. The total bandwidth of each channel is divided into a fixed number of equal-sized slots. The nodes are equipped with fixed transmitters and tunable receivers. Control information, which is transmitted on a specific

  16. An Architecture for Anonymous Mobile Coupons in a Large Network

    Directory of Open Access Journals (Sweden)

    Alberto Bartoli

    2016-01-01

    Full Text Available A mobile coupon (m-coupon can be presented with a smartphone for obtaining a financial discount when purchasing a product or a service. M-coupons are a powerful marketing tool that has enjoyed a huge growth and diffusion, involving tens of millions of people each year. We propose an architecture which may enable significant improvements over current m-coupon technology, in terms of acceptance of potential customers and of marketing actions that become feasible: the customer does not need to install any dedicated app; an m-coupon is not bound to any specific device or customer; an m-coupon may be redeemed at any store in a set of potentially many thousands of stores, without any prior arrangement between customer and store. We are not aware of any proposal with these properties.

  17. Feedback Control Architecture and the Bacterial Chemotaxis Network

    Science.gov (United States)

    Hamadeh, Abdullah; Roberts, Mark A. J.; August, Elias; McSharry, Patrick E.; Maini, Philip K.; Armitage, Judith P.; Papachristodoulou, Antonis

    2011-01-01

    Bacteria move towards favourable and away from toxic environments by changing their swimming pattern. This response is regulated by the chemotaxis signalling pathway, which has an important feature: it uses feedback to ‘reset’ (adapt) the bacterial sensing ability, which allows the bacteria to sense a range of background environmental changes. The role of this feedback has been studied extensively in the simple chemotaxis pathway of Escherichia coli. However it has been recently found that the majority of bacteria have multiple chemotaxis homologues of the E. coli proteins, resulting in more complex pathways. In this paper we investigate the configuration and role of feedback in Rhodobacter sphaeroides, a bacterium containing multiple homologues of the chemotaxis proteins found in E. coli. Multiple proteins could produce different possible feedback configurations, each having different chemotactic performance qualities and levels of robustness to variations and uncertainties in biological parameters and to intracellular noise. We develop four models corresponding to different feedback configurations. Using a series of carefully designed experiments we discriminate between these models and invalidate three of them. When these models are examined in terms of robustness to noise and parametric uncertainties, we find that the non-invalidated model is superior to the others. Moreover, it has a ‘cascade control’ feedback architecture which is used extensively in engineering to improve system performance, including robustness. Given that the majority of bacteria are known to have multiple chemotaxis pathways, in this paper we show that some feedback architectures allow them to have better performance than others. In particular, cascade control may be an important feature in achieving robust functionality in more complex signalling pathways and in improving their performance. PMID:21573199

  18. Feedback control architecture and the bacterial chemotaxis network.

    Science.gov (United States)

    Hamadeh, Abdullah; Roberts, Mark A J; August, Elias; McSharry, Patrick E; Maini, Philip K; Armitage, Judith P; Papachristodoulou, Antonis

    2011-05-01

    Bacteria move towards favourable and away from toxic environments by changing their swimming pattern. This response is regulated by the chemotaxis signalling pathway, which has an important feature: it uses feedback to 'reset' (adapt) the bacterial sensing ability, which allows the bacteria to sense a range of background environmental changes. The role of this feedback has been studied extensively in the simple chemotaxis pathway of Escherichia coli. However it has been recently found that the majority of bacteria have multiple chemotaxis homologues of the E. coli proteins, resulting in more complex pathways. In this paper we investigate the configuration and role of feedback in Rhodobacter sphaeroides, a bacterium containing multiple homologues of the chemotaxis proteins found in E. coli. Multiple proteins could produce different possible feedback configurations, each having different chemotactic performance qualities and levels of robustness to variations and uncertainties in biological parameters and to intracellular noise. We develop four models corresponding to different feedback configurations. Using a series of carefully designed experiments we discriminate between these models and invalidate three of them. When these models are examined in terms of robustness to noise and parametric uncertainties, we find that the non-invalidated model is superior to the others. Moreover, it has a 'cascade control' feedback architecture which is used extensively in engineering to improve system performance, including robustness. Given that the majority of bacteria are known to have multiple chemotaxis pathways, in this paper we show that some feedback architectures allow them to have better performance than others. In particular, cascade control may be an important feature in achieving robust functionality in more complex signalling pathways and in improving their performance.

  19. Feedback control architecture and the bacterial chemotaxis network.

    Directory of Open Access Journals (Sweden)

    Abdullah Hamadeh

    2011-05-01

    Full Text Available Bacteria move towards favourable and away from toxic environments by changing their swimming pattern. This response is regulated by the chemotaxis signalling pathway, which has an important feature: it uses feedback to 'reset' (adapt the bacterial sensing ability, which allows the bacteria to sense a range of background environmental changes. The role of this feedback has been studied extensively in the simple chemotaxis pathway of Escherichia coli. However it has been recently found that the majority of bacteria have multiple chemotaxis homologues of the E. coli proteins, resulting in more complex pathways. In this paper we investigate the configuration and role of feedback in Rhodobacter sphaeroides, a bacterium containing multiple homologues of the chemotaxis proteins found in E. coli. Multiple proteins could produce different possible feedback configurations, each having different chemotactic performance qualities and levels of robustness to variations and uncertainties in biological parameters and to intracellular noise. We develop four models corresponding to different feedback configurations. Using a series of carefully designed experiments we discriminate between these models and invalidate three of them. When these models are examined in terms of robustness to noise and parametric uncertainties, we find that the non-invalidated model is superior to the others. Moreover, it has a 'cascade control' feedback architecture which is used extensively in engineering to improve system performance, including robustness. Given that the majority of bacteria are known to have multiple chemotaxis pathways, in this paper we show that some feedback architectures allow them to have better performance than others. In particular, cascade control may be an important feature in achieving robust functionality in more complex signalling pathways and in improving their performance.

  20. Toward a Mobility-Driven Architecture for Multimodal Underwater Networking

    Science.gov (United States)

    2017-02-01

    interest in the undersea domain, sparked by applications including environmental monitoring, deep-sea exploration and exploitation, and undersea...allow them to gather large volumes of data, ranging from acoustic and environmental measurements to high-resolution imagery and video. Although they...of Partially Observed Dynamical Processes over Networks via Dictionary Learning,” IEEE Transactions on Signal Processing. vol. 62, no. 13 (July), pp

  1. Algorithm-structured computer arrays and networks architectures and processes for images, percepts, models, information

    CERN Document Server

    Uhr, Leonard

    1984-01-01

    Computer Science and Applied Mathematics: Algorithm-Structured Computer Arrays and Networks: Architectures and Processes for Images, Percepts, Models, Information examines the parallel-array, pipeline, and other network multi-computers.This book describes and explores arrays and networks, those built, being designed, or proposed. The problems of developing higher-level languages for systems and designing algorithm, program, data flow, and computer structure are also discussed. This text likewise describes several sequences of successively more general attempts to combine the power of arrays wi

  2. Design and architecture of the Mars relay network planning and analysis framework

    Science.gov (United States)

    Cheung, K. M.; Lee, C. H.

    2002-01-01

    In this paper we describe the design and architecture of the Mars Network planning and analysis framework that supports generation and validation of efficient planning and scheduling strategy. The goals are to minimize the transmitting time, minimize the delaying time, and/or maximize the network throughputs. The proposed framework would require (1) a client-server architecture to support interactive, batch, WEB, and distributed analysis and planning applications for the relay network analysis scheme, (2) a high-fidelity modeling and simulation environment that expresses link capabilities between spacecraft to spacecraft and spacecraft to Earth stations as time-varying resources, and spacecraft activities, link priority, Solar System dynamic events, the laws of orbital mechanics, and other limiting factors as spacecraft power and thermal constraints, (3) an optimization methodology that casts the resource and constraint models into a standard linear and nonlinear constrained optimization problem that lends itself to commercial off-the-shelf (COTS)planning and scheduling algorithms.

  3. Process reveals structure: How a network is traversed mediates expectations about its architecture.

    Science.gov (United States)

    Karuza, Elisabeth A; Kahn, Ari E; Thompson-Schill, Sharon L; Bassett, Danielle S

    2017-10-06

    Network science has emerged as a powerful tool through which we can study the higher-order architectural properties of the world around us. How human learners exploit this information remains an essential question. Here, we focus on the temporal constraints that govern such a process. Participants viewed a continuous sequence of images generated by three distinct walks on a modular network. Walks varied along two critical dimensions: their predictability and the density with which they sampled from communities of images. Learners exposed to walks that richly sampled from each community exhibited a sharp increase in processing time upon entry into a new community. This effect was eliminated in a highly regular walk that sampled exhaustively from images in short, successive cycles (i.e., that increasingly minimized uncertainty about the nature of upcoming stimuli). These results demonstrate that temporal organization plays an essential role in learners' sensitivity to the network architecture underlying sensory input.

  4. Hierarchical network architectures of carbon fiber paper supported cobalt oxide nanonet for high-capacity pseudocapacitors.

    Science.gov (United States)

    Yang, Lei; Cheng, Shuang; Ding, Yong; Zhu, Xingbao; Wang, Zhong Lin; Liu, Meilin

    2012-01-11

    We present a high-capacity pseudocapacitor based on a hierarchical network architecture consisting of Co(3)O(4) nanowire network (nanonet) coated on a carbon fiber paper. With this tailored architecture, the electrode shows ideal capacitive behavior (rectangular shape of cyclic voltammograms) and large specific capacitance (1124 F/g) at high charge/discharge rate (25.34 A/g), still retaining ~94% of the capacitance at a much lower rate of 0.25 A/g. The much-improved capacity, rate capability, and cycling stability may be attributed to the unique hierarchical network structures, which improves electron/ion transport, enhances the kinetics of redox reactions, and facilitates facile stress relaxation during cycling. © 2011 American Chemical Society

  5. An Object-Oriented Network-Centric Software Architecture for Physical Computing

    Science.gov (United States)

    Palmer, Richard

    1997-08-01

    Recent developments in object-oriented computer languages and infrastructure such as the Internet, Web browsers, and the like provide an opportunity to define a more productive computational environment for scientific programming that is based more closely on the underlying mathematics describing physics than traditional programming languages such as FORTRAN or C++. In this talk I describe an object-oriented software architecture for representing physical problems that includes classes for such common mathematical objects as geometry, boundary conditions, partial differential and integral equations, discretization and numerical solution methods, etc. In practice, a scientific program written using this architecture looks remarkably like the mathematics used to understand the problem, is typically an order of magnitude smaller than traditional FORTRAN or C++ codes, and hence easier to understand, debug, describe, etc. All objects in this architecture are ``network-enabled,'' which means that components of a software solution to a physical problem can be transparently loaded from anywhere on the Internet or other global network. The architecture is expressed as an ``API,'' or application programmers interface specification, with reference embeddings in Java, Python, and C++. A C++ class library for an early version of this API has been implemented for machines ranging from PC's to the IBM SP2, meaning that phidentical codes run on all architectures.

  6. Performance and Challenges of Service-Oriented Architecture for Wireless Sensor Networks.

    Science.gov (United States)

    Alshinina, Remah; Elleithy, Khaled

    2017-03-08

    Wireless Sensor Networks (WSNs) have become essential components for a variety of environmental, surveillance, military, traffic control, and healthcare applications. These applications face critical challenges such as communication, security, power consumption, data aggregation, heterogeneities of sensor hardware, and Quality of Service (QoS) issues. Service-Oriented Architecture (SOA) is a software architecture that can be integrated with WSN applications to address those challenges. The SOA middleware bridges the gap between the high-level requirements of different applications and the hardware constraints of WSNs. This survey explores state-of-the-art approaches based on SOA and Service-Oriented Middleware (SOM) architecture that provide solutions for WSN challenges. The categories of this paper are based on approaches of SOA with and without middleware for WSNs. Additionally, features of SOA and middleware architectures for WSNs are compared to achieve more robust and efficient network performance. Design issues of SOA middleware for WSNs and its characteristics are also highlighted. The paper concludes with future research directions in SOM architecture to meet all requirements of emerging application of WSNs.

  7. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performan...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  8. A CNN-Specific Integrated Processor

    Science.gov (United States)

    Malki, Suleyman; Spaanenburg, Lambert

    2009-12-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  9. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  10. Architecture of the parallel hierarchical network for fast image recognition

    Science.gov (United States)

    Timchenko, Leonid; Wójcik, Waldemar; Kokriatskaia, Natalia; Kutaev, Yuriy; Ivasyuk, Igor; Kotyra, Andrzej; Smailova, Saule

    2016-09-01

    Multistage integration of visual information in the brain allows humans to respond quickly to most significant stimuli while maintaining their ability to recognize small details in the image. Implementation of this principle in technical systems can lead to more efficient processing procedures. The multistage approach to image processing includes main types of cortical multistage convergence. The input images are mapped into a flexible hierarchy that reflects complexity of image data. Procedures of the temporal image decomposition and hierarchy formation are described in mathematical expressions. The multistage system highlights spatial regularities, which are passed through a number of transformational levels to generate a coded representation of the image that encapsulates a structure on different hierarchical levels in the image. At each processing stage a single output result is computed to allow a quick response of the system. The result is presented as an activity pattern, which can be compared with previously computed patterns on the basis of the closest match. With regard to the forecasting method, its idea lies in the following. In the results synchronization block, network-processed data arrive to the database where a sample of most correlated data is drawn using service parameters of the parallel-hierarchical network.

  11. A new constructive algorithm for architectural and functional adaptation of artificial neural networks.

    Science.gov (United States)

    Islam, Md Monirul; Sattar, Md Abdus; Amin, Md Faijul; Yao, Xin; Murase, Kazuyuki

    2009-12-01

    The generalization ability of artificial neural networks (ANNs) is greatly dependent on their architectures. Constructive algorithms provide an attractive automatic way of determining a near-optimal ANN architecture for a given problem. Several such algorithms have been proposed in the literature and shown their effectiveness. This paper presents a new constructive algorithm (NCA) in automatically determining ANN architectures. Unlike most previous studies on determining ANN architectures, NCA puts emphasis on architectural adaptation and functional adaptation in its architecture determination process. It uses a constructive approach to determine the number of hidden layers in an ANN and of neurons in each hidden layer. To achieve functional adaptation, NCA trains hidden neurons in the ANN by using different training sets that were created by employing a similar concept used in the boosting algorithm. The purpose of using different training sets is to encourage hidden neurons to learn different parts or aspects of the training data so that the ANN can learn the whole training data in a better way. In this paper, the convergence and computational issues of NCA are analytically studied. The computational complexity of NCA is found to be O(W xP(t) xtau), where W is the number of weights in the ANN, P(t) is the number of training examples, and tau is the number of training epochs. This complexity has the same order as what the backpropagation learning algorithm requires for training a fixed ANN architecture. A set of eight classification and two approximation benchmark problems was used to evaluate the performance of NCA. The experimental results show that NCA can produce ANN architectures with fewer hidden neurons and better generalization ability compared to existing constructive and nonconstructive algorithms.

  12. Parallelization of applications for networks with homogeneous and heterogeneous processors; Parallelisation d`applications pour des reseaux de processeurs homogenes ou heterogenes

    Energy Technology Data Exchange (ETDEWEB)

    Colombet, L.

    1994-10-07

    The aim of this thesis is to study and develop efficient methods for parallelization of scientific applications on parallel computers with distributed memory. The first part presents two libraries of PVM (Parallel Virtual Machine) and MPI (Message Passing Interface) communication tools. They allow implementation of programs on most parallel machines, but also on heterogeneous computer networks. This chapter illustrates the problems faced when trying to evaluate performances of networks with heterogeneous processors. To evaluate such performances, the concepts of speed-up and efficiency have been modified and adapted to account for heterogeneity. The second part deals with a study of parallel application libraries such as ScaLAPACK and with the development of communication masking techniques. The general concept is based on communication anticipation, in particular by pipelining message sending operations. Experimental results on Cray T3D and IBM SP1 machines validates the theoretical studies performed on basic algorithms of the libraries discussed above. Two examples of scientific applications are given: the first is a model of young stars for astrophysics and the other is a model of photon trajectories in the Compton effect. (J.S.). 83 refs., 65 figs., 24 tabs.

  13. Adaptive Security Architecture based on EC-MQV Algorithm in Personal Network (PN)

    DEFF Research Database (Denmark)

    Mihovska, Albena D.; Prasad, Neeli R.

    2007-01-01

    Abstract — Personal Networks (PNs) have been focused on in order to support the user’s business and private activities without jeopardizing privacy and security of the users and their data. In such a network, it is necessary to produce a proper key agreement method according to the feature...... of the network. One of the features of the network is that the personal devices have deferent capabilities such as computational ability, memory size, transmission power, processing speed and implementation cost. Therefore an adaptive security mechanism should be contrived for such a network of various device...... combinations based on user’s location and device’s capability. The paper proposes new adaptive security architecture with three levels of asymmetric key agreement scheme by using context-aware security manager (CASM) based on elliptic curve cryptosystem (EC-MQV)....

  14. Teledesic Global Wireless Broadband Network: Space Infrastructure Architecture, Design Features and Technologies

    Science.gov (United States)

    Stuart, James R.

    1995-01-01

    The Teledesic satellites are a new class of small satellites which demonstrate the important commercial benefits of using technologies developed for other purposes by U.S. National Laboratories. The Teledesic satellite architecture, subsystem design features, and new technologies are described. The new Teledesic satellite manufacturing, integration, and test approaches which use modern high volume production techniques and result in surprisingly low space segment costs are discussed. The constellation control and management features and attendant software architecture features are addressed. After briefly discussing the economic and technological impact on the USA commercial space industries of the space communications revolution and such large constellation projects, the paper concludes with observations on the trend toward future system architectures using networked groups of much smaller satellites.

  15. 64k networked multi-threaded processors and their real-time application in high energy physics

    CERN Document Server

    Schneider, R; Gutfleisch, M; Gareus, R; Lesser, F; Lindenstruth, V; Reichling, C; Torralba, G

    2002-01-01

    Particle physics experiments create large data streams at high rates ranging from kHz to MHz. In a single event the number of created particles can easily exceed 20.000. The architecture of high resolution tracking detectors does not allow to handle the event data stream exceeding 10 TByte/s. Since only some rare scenarios are interesting a selection process increases the efficiency by identifying relevant events which are processed afterwards. This trigger has to be fast enough to avoid loss of data. In case of the ALICE experiment at CERN the trigger is created by analyzing data of the transition radiation detector where about 16.000 charged particles cross six independent layers. Nearly 1.2 million analog data channels are digitized at 10 MHz by 10 bit ADCs within 2 mu s. On this data stream of 13 TByte/s a trigger decision has to be made within 6 mu s. (5 refs).

  16. High-Resolution Laser Scanning Reveals Plant Architectures that Reflect Universal Network Design Principles.

    Science.gov (United States)

    Conn, Adam; Pedmale, Ullas V; Chory, Joanne; Navlakha, Saket

    2017-07-26

    Transport networks serve critical functions in biological and engineered systems, and yet their design requires trade-offs between competing objectives. Due to their sessile lifestyle, plants need to optimize their architecture to efficiently acquire and distribute resources while also minimizing costs in building infrastructure. To understand how plants resolve this design trade-off, we used high-precision three-dimensional laser scanning to map the architectures of tomato, tobacco, or sorghum plants grown in several environmental conditions and through multiple developmental time points, scanning in total 505 architectures from 37 plants. Using a graph-theoretic algorithm that we developed to evaluate design strategies, we find that plant architectures lie along the Pareto front between two simple length-based objectives-minimizing total branch length and minimizing nutrient transport distance-thereby conferring a selective fitness advantage for plant transport processes. The location along the Pareto front can distinguish among species and conditions, suggesting that during evolution, natural selection may employ common network design principles despite different optimization trade-offs. Copyright © 2017 Elsevier Inc. All rights reserved.

  17. A Smart Gateway Architecture for Improving Efficiency of Home Network Applications

    Directory of Open Access Journals (Sweden)

    Fei Ding

    2016-01-01

    Full Text Available A smart home gateway plays an important role in the Internet of Things (IoT system that takes responsibility for the connection between the network layer and the ubiquitous sensor network (USN layer. Even though the home network application is developing rapidly, researches on the home gateway based open development architecture are less. This makes it difficult to extend the home network to support new applications, share service, and interoperate with other home network systems. An integrated access gateway (IAGW is proposed in this paper which upward connects with the operator machine-to-machine platform (M2M P/F. In this home network scheme, the gateway provides standard interfaces for supporting various applications in home environments, ranging from on-site configuration to node and service access. In addition, communication management ability is also provided by M2M P/F. A testbed of a simple home network application system that includes the IAGW prototype is created to test its user interaction capabilities. Experimental results show that the proposed gateway provides significant flexibility for users to configure and deploy a home automation network; it can be applied to other monitoring areas and simultaneously supports a multi-ubiquitous sensor network.

  18. Role of graph architecture in controlling dynamical networks with applications to neural systems

    Science.gov (United States)

    Kim, Jason Z.; Soffer, Jonathan M.; Kahn, Ari E.; Vettel, Jean M.; Pasqualetti, Fabio; Bassett, Danielle S.

    2018-01-01

    Networked systems display complex patterns of interactions between components. In physical networks, these interactions often occur along structural connections that link components in a hard-wired connection topology, supporting a variety of system-wide dynamical behaviours such as synchronization. Although descriptions of these behaviours are important, they are only a first step towards understanding and harnessing the relationship between network topology and system behaviour. Here, we use linear network control theory to derive accurate closed-form expressions that relate the connectivity of a subset of structural connections (those linking driver nodes to non-driver nodes) to the minimum energy required to control networked systems. To illustrate the utility of the mathematics, we apply this approach to high-resolution connectomes recently reconstructed from Drosophila, mouse, and human brains. We use these principles to suggest an advantage of the human brain in supporting diverse network dynamics with small energetic costs while remaining robust to perturbations, and to perform clinically accessible targeted manipulation of the brain's control performance by removing single edges in the network. Generally, our results ground the expectation of a control system's behaviour in its network architecture, and directly inspire new directions in network analysis and design via distributed control.

  19. The development of hub architecture in the human functional brain network.

    Science.gov (United States)

    Hwang, Kai; Hallquist, Michael N; Luna, Beatriz

    2013-10-01

    Functional hubs are brain regions that play a crucial role in facilitating communication among parallel, distributed brain networks. The developmental emergence and stability of hubs, however, is not well understood. The current study used measures of network topology drawn from graph theory to investigate the development of functional hubs in 99 participants, 10-20 years of age. We found that hub architecture was evident in late childhood and was stable from adolescence to early adulthood. Connectivity between hub and non-hub ("spoke") regions, however, changed with development. From childhood to adolescence, the strength of connections between frontal hubs and cortical and subcortical spoke regions increased. From adolescence to adulthood, hub-spoke connections with frontal hubs were stable, whereas connectivity between cerebellar hubs and cortical spoke regions increased. Our findings suggest that a developmentally stable functional hub architecture provides the foundation of information flow in the brain, whereas connections between hubs and spokes continue to develop, possibly supporting mature cognitive function.

  20. GEYSERS: a novel architecture for virtualization and co-provisioning of dynamic optical networks and IT services

    NARCIS (Netherlands)

    Escalona, E.; Peng, S.; Nejabati, R.; Simeonidou, D.; García-Espín, J.A.; Ferrer, J.; Figuerola, S.; Landi, G.; Ciulli, N.; Jiménez, J.; Belter, B.; Demchenko, Y.; de Laat, C.; Chen, X.; Yukan, A.; Soudan, S.; Vicat-Blanc, P.; Buysse, J.; de Leenheer, M.; Develder, C.; Tzanakaki, A.; Robinson, P.; Brogle, M.; Bohnert, T.M.

    2011-01-01

    GEYSERS aims at defining an end-to-end network architecture that offers a novel planning, provisioning and operational framework for optical network and IT infrastructure providers and operators. In this framework, physical infrastructure resources (network and IT) are dynamically partitioned to

  1. An integrated architecture for deploying a virtual private medical network over the web.

    Science.gov (United States)

    Gritzalis, S; Gritzalis, D; Moulinos, C; Iliadis, J

    2001-01-01

    In this paper we describe a pilot architecture aiming at protecting Web-based medical applications through the development of a virtual private medical network. The basic technology, which is utilized by this integrated architecture, is the Trusted Third Party (TTP). In specific, a TTP is used to generate, distribute, and revoke digital certificates to/from medical practitioners and healthcare organizations wishing to communicate in a secure way. Digital certificates and digital signatures are, in particular, used to provide peer and data origin authentication and access control functionalities. We also propose a logical Public Key Infrastructure (PKI) architecture, which is robust, scalable, and based on standards. This architecture aims at supporting large-scale healthcare applications. It supports openness, scalability, flexibility and extensibility, and can be integrated with existing TTP schemes and infrastructures offering transparency and adequate security. Finally, it is demonstrated that the proposed architecture enjoys all desirable usability characteristics, and meets the set of criteria, which constitutes an applicable framework for the development of trusted medical services over the Web.

  2. Brain Network Architecture and Global Intelligence in Children with Focal Epilepsy.

    Science.gov (United States)

    Paldino, M J; Golriz, F; Chapieski, M L; Zhang, W; Chu, Z D

    2017-02-01

    The biologic basis for intelligence rests to a large degree on the capacity for efficient integration of information across the cerebral network. We aimed to measure the relationship between network architecture and intelligence in the pediatric, epileptic brain. Patients were retrospectively identified with the following: 1) focal epilepsy; 2) brain MR imaging at 3T, including resting-state functional MR imaging; and 3) full-scale intelligence quotient measured by a pediatric neuropsychologist. The cerebral cortex was parcellated into approximately 700 gray matter network "nodes." The strength of a connection between 2 nodes was defined by the correlation between their blood oxygen level-dependent time-series. We calculated the following topologic properties: clustering coefficient, transitivity, modularity, path length, and global efficiency. A machine learning algorithm was used to measure the independent contribution of each metric to the intelligence quotient after adjusting for all other metrics. Thirty patients met the criteria (4-18 years of age); 20 patients required anesthesia during MR imaging. After we accounted for age and sex, clustering coefficient and path length were independently associated with full-scale intelligence quotient. Neither motion parameters nor general anesthesia was an important variable with regard to accurate intelligence quotient prediction by the machine learning algorithm. A longer history of epilepsy was associated with shorter path lengths (P = .008), consistent with reorganization of the network on the basis of seizures. Considering only patients receiving anesthesia during machine learning did not alter the patterns of network architecture contributing to global intelligence. These findings support the physiologic relevance of imaging-based metrics of network architecture in the pathologic, developing brain. © 2017 by American Journal of Neuroradiology.

  3. A Robust Dynamic Edge Network Architecture for the Internet-of-Things

    OpenAIRE

    Lorenzo, Beatriz; Garcia-Rois, Juan; Li, Xuanheng; Gonzalez-Castano, Javier; Fang, Yuguang

    2017-01-01

    A massive number of devices are expected to fulfill the missions of sensing, processing and control in cyber-physical Internet-of-Things (IoT) systems with new applications and connectivity requirements. In this context, scarce spectrum resources must accommodate a high traffic volume with stringent requirements of low latency, high reliability and energy efficiency. Conventional centralized network architectures may not be able to fulfill these requirements due to congestion in backhaul link...

  4. Seafloor classification using echo- waveforms: A method employing hybrid neural network architecture

    Digital Repository Service at National Institute of Oceanography (India)

    Chakraborty, B.; Mahale, V.; DeSouza, C.; Das, P.

    , neural network architecture, seafloor classification, self-organizing feature map (SOFM). I. INTRODUCTION S EAFLOOR classification and characterization using re- mote high-frequency acoustic system has been recognized as a useful tool (see [1...] and references therein). The seafloor’s characteristics are extremely complicated due to variations of the many parameters at different scales. The parameters include sediment grain size, relief height at the water–sediment inter- face, and variations within...

  5. STOMP: A Software Architecture for the Design and Simulation UAV-Based Sensor Networks

    Energy Technology Data Exchange (ETDEWEB)

    Jones, E D; Roberts, R S; Hsia, T C S

    2002-10-28

    This paper presents the Simulation, Tactical Operations and Mission Planning (STOMP) software architecture and framework for simulating, controlling and communicating with unmanned air vehicles (UAVs) servicing large distributed sensor networks. STOMP provides hardware-in-the-loop capability enabling real UAVs and sensors to feedback state information, route data and receive command and control requests while interacting with other real or virtual objects thereby enhancing support for simulation of dynamic and complex events.

  6. CRAC: Confidentiality Risk Analysis and IT-Architecture Comparison of Business Networks (extended version)

    OpenAIRE

    Morali, A.; Zambon, Emmanuele; Etalle, Sandro; Wieringa, Roelf J.

    2009-01-01

    The leakage of confidential information (e.g.\\ industrial secrets, patient records and user credentials) is one of the risks that have to be accounted for and mitigated by organizations dealing with confidential data. Unfortunately, assessing confidentiality risk is challenging, particularly in the presence of cross- organization cooperation, like in the case of outsourcing. This is due to the complexity of business networks. This paper presents an IT-architecture based method for assessing a...

  7. Software-Defined Networking Using OpenFlow: Protocols, Applications and Architectural Design Choices

    Directory of Open Access Journals (Sweden)

    Wolfgang Braun

    2014-05-01

    Full Text Available We explain the notion of software-defined networking (SDN, whose southbound interface may be implemented by the OpenFlow protocol. We describe the operation of OpenFlow and summarize the features of specification versions 1.0–1.4. We give an overview of existing SDN-based applications grouped by topic areas. Finally, we point out architectural design choices for SDN using OpenFlow and discuss their performance implications.

  8. Lightweight Filter Architecture for Energy Efficient Mobile Vehicle Localization Based on a Distributed Acoustic Sensor Network

    OpenAIRE

    Kim, Keonwook

    2013-01-01

    The generic properties of an acoustic signal provide numerous benefits for localization by applying energy-based methods over a deployed wireless sensor network (WSN). However, the signal generated by a stationary target utilizes a significant amount of bandwidth and power in the system without providing further position information. For vehicle localization, this paper proposes a novel proximity velocity vector estimator (PVVE) node architecture in order to capture the energy from a moving v...

  9. Enhanced Stochastic Methodology for Combined Architecture of E-Commerce and Security Networks

    OpenAIRE

    Song-Kyoo Kim

    2009-01-01

    This paper deals with network architecture which is a combination of electronic commerce and security systems in the typical Internet ecosystems. The e-commerce model that is typically known as online shopping can be considered as a multichannel queueing system. In the other hand, stochastic security system is designed for improving the reliability and availability of the e-commerce system. The security system in this paper deals with a complex system that consists of main unreliable servers,...

  10. Open|SpeedShop Ease of Use Performance Analysis for Heterogenious Processor Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose building upon the modular extensible architecture and existing capabilities of Open|SpeedShop to provide seamless, integrated, heterogeneous processor...

  11. OTN Transport of Baseband Radio Serial Protocols in C-RAN Architecture for Mobile Network Applications

    DEFF Research Database (Denmark)

    Checko, Aleksandra; Kardaras, Georgios; Lanzani, Christian Fabio Alessandro

    This white paper presents a proof of concept implementation of digital baseband radio data transport over Optical Transport Network (OTN) compliant to 3GPP Long Term Evolution – Advanced (LTE-A) standard enabling Cloud Radio Access Network (C-RAN) architecture. The transport between the baseband...... module and a remote radio module is compliant to Common Public Radio Interface (CPRI) and to the OBSAI reference point 3 - 01 (RP3-01) interface protocols, respectively. The purpose is to demonstrate that data integrity and clocking performance at the radio node still meets the strict standard...

  12. Architectural style classification of Mexican historical buildings using deep convolutional neural networks and sparse features

    Science.gov (United States)

    Obeso, Abraham Montoya; Benois-Pineau, Jenny; Acosta, Alejandro Álvaro Ramirez; Vázquez, Mireya Saraí García

    2017-01-01

    We propose a convolutional neural network to classify images of buildings using sparse features at the network's input in conjunction with primary color pixel values. As a result, a trained neuronal model is obtained to classify Mexican buildings in three classes according to the architectural styles: prehispanic, colonial, and modern with an accuracy of 88.01%. The problem of poor information in a training dataset is faced due to the unequal availability of cultural material. We propose a data augmentation and oversampling method to solve this problem. The results are encouraging and allow for prefiltering of the content in the search tasks.

  13. Fiber-optic subscriber system based on passive optical network architecture

    Energy Technology Data Exchange (ETDEWEB)

    Kitazawa, M.; Yamazaki, M.; Himi, S. (Hitachi, Ltd., Tokyo (Japan))

    1994-04-01

    The subscriber line terminal and optical network unit were developed for the fiber-optic subscriber system based on a passive double star (PDS) optical network architecture which allows narrowband ISDN (integrated services digital network) services and video image transmission. Various LSIs were developed to implement the major system functions such as fast bit-synchronization, time division multiple access control, subscriber multiplexing/demultiplexing and 16-channel multiprocessing. For the optical interface module, the wavelength division multiplexing chip was hermetically sealed together with laser diode and photodiode chips by adopting high-silica based optical-waveguide technology to reduce a system dimension. The PDS fiber-optic subscriber system is useful for construction of economic optical subscriber networks because it allows multiple subscribers to share a single optical transmission line and a central equipment unit through a star coupler. 4 refs., 10 figs., 1 tab.

  14. Modeling suggests that gene circuit architecture controls phenotypic variability in a bacterial persistence network.

    Science.gov (United States)

    Koh, Rachel S; Dunlop, Mary J

    2012-05-20

    Bacterial persistence is a non-inherited bet-hedging mechanism where a subpopulation of cells enters a dormant state, allowing those cells to survive environmental stress such as treatment with antibiotics. Persister cells are not mutants; they are formed by natural stochastic variation in gene expression. Understanding how regulatory architecture influences the level of phenotypic variability can help us explain how the frequency of persistence events can be tuned. We present a model of the regulatory network controlling the HipBA toxin-antitoxin system from Escherichia coli. Using a biologically realistic model we first determine that the persistence phenotype is not the result of bistability within the network. Next, we develop a stochastic model and show that cells can enter persistence due to random fluctuations in transcription, translation, degradation, and complex formation. We then examine alternative gene circuit architectures for controlling hipBA expression and show that networks with more noise (more persisters) and less noise (fewer persisters) are straightforward to achieve. Thus, we propose that the gene circuit architecture can be used to tune the frequency of persistence, a trait that can be selected for by evolution. We develop deterministic and stochastic models describing how the regulation of toxin and antitoxin expression influences phenotypic variation within a population. Persistence events are the result of stochastic fluctuations in toxin levels that cross a threshold, and their frequency is controlled by the regulatory topology governing gene expression.

  15. Modeling suggests that gene circuit architecture controls phenotypic variability in a bacterial persistence network

    Directory of Open Access Journals (Sweden)

    Koh Rachel S

    2012-05-01

    Full Text Available Abstract Background Bacterial persistence is a non-inherited bet-hedging mechanism where a subpopulation of cells enters a dormant state, allowing those cells to survive environmental stress such as treatment with antibiotics. Persister cells are not mutants; they are formed by natural stochastic variation in gene expression. Understanding how regulatory architecture influences the level of phenotypic variability can help us explain how the frequency of persistence events can be tuned. Results We present a model of the regulatory network controlling the HipBA toxin-antitoxin system from Escherichia coli. Using a biologically realistic model we first determine that the persistence phenotype is not the result of bistability within the network. Next, we develop a stochastic model and show that cells can enter persistence due to random fluctuations in transcription, translation, degradation, and complex formation. We then examine alternative gene circuit architectures for controlling hipBA expression and show that networks with more noise (more persisters and less noise (fewer persisters are straightforward to achieve. Thus, we propose that the gene circuit architecture can be used to tune the frequency of persistence, a trait that can be selected for by evolution. Conclusions We develop deterministic and stochastic models describing how the regulation of toxin and antitoxin expression influences phenotypic variation within a population. Persistence events are the result of stochastic fluctuations in toxin levels that cross a threshold, and their frequency is controlled by the regulatory topology governing gene expression.

  16. Modeling workplace contact networks: The effects of organizational structure, architecture, and reporting errors on epidemic predictions.

    Science.gov (United States)

    Potter, Gail E; Smieszek, Timo; Sailer, Kerstin

    2015-09-01

    Face-to-face social contacts are potentially important transmission routes for acute respiratory infections, and understanding the contact network can improve our ability to predict, contain, and control epidemics. Although workplaces are important settings for infectious disease transmission, few studies have collected workplace contact data and estimated workplace contact networks. We use contact diaries, architectural distance measures, and institutional structures to estimate social contact networks within a Swiss research institute. Some contact reports were inconsistent, indicating reporting errors. We adjust for this with a latent variable model, jointly estimating the true (unobserved) network of contacts and duration-specific reporting probabilities. We find that contact probability decreases with distance, and that research group membership, role, and shared projects are strongly predictive of contact patterns. Estimated reporting probabilities were low only for 0-5 min contacts. Adjusting for reporting error changed the estimate of the duration distribution, but did not change the estimates of covariate effects and had little effect on epidemic predictions. Our epidemic simulation study indicates that inclusion of network structure based on architectural and organizational structure data can improve the accuracy of epidemic forecasting models.

  17. Micro mirrors based coupling of light to multi-core fiber realizing in-fiber photonic neural network processor

    Science.gov (United States)

    Cohen, Eyal; Malka, Dror; Shemer, Amir; Shahmoon, Asaf; London, Michael; Zalevsky, Zeev

    2017-02-01

    Hardware implementation of artificial neural networks facilitates real-time parallel processing of massive data sets. Optical neural networks offer low-volume 3D connectivity together with large bandwidth and minimal heat production in contrast to electronic implementation. Here, we present a DMD based approaches to realize energetically efficient light coupling into a multi-core fiber realizing a unique design for in-fiber optical neural networks. Neurons and synapses are realized as individual cores in a multi-core fiber. Optical signals are transferred transversely between cores by means of optical coupling. Pump driven amplification in Erbium-doped cores mimics synaptic interactions. In order to dynamically and efficiently couple light into the multi-core fiber a DMD based micro mirror device is used to perform proper beam shaping operation. The beam shaping reshapes the light into a large set of points in space matching the positions of the required cores in the entrance plane to the multi-core fiber.

  18. Impaired brain network architecture in newly diagnosed Parkinson's disease based on graph theoretical analysis.

    Science.gov (United States)

    Fang, Jinping; Chen, Huimin; Cao, Zhentang; Jiang, Ying; Ma, Lingyan; Ma, Huizi; Feng, Tao

    2017-09-14

    Resting state functional magnetic resonance imaging (rs-fMRI) has been applied to investigate topographic structure in Parkinson's disease (PD). Alteration of topographic architecture has been inconsistent in PD AIM: To investigate the network profile of PD using graph theoretical analysis. Twenty six newly diagnosed PD and 19 age- and gender- matched healthy controls (HC) were included in our analysis. Small-world profile and topographic profiles (nodal degree, global efficiency, local efficiency, cluster coefficient, shortest path length, betweenness centrality) were measured and compared between groups, with age and gender as covariates. We also performed correlation analysis between topographic features with motor severity measured by UPDRS III. Small-world property was present in PD. Nodal degree, global efficiency, local efficiency and characteristic path length consistently revealed disruptive sensorimotor network, and visual network to a less degree in PD. By contrast, default mode network (DMN) and cerebellum in PD showed higher nodal degree, global efficiency and local efficiency, and lower characteristic path length. Global and local efficiency in the midbrain was higher in PD excluding substantia nigra. PD group also exhibited lower cluster coefficient in the subcortical motor network (thalamus and caudate nucleus). No significant correlation was found between topographic properties and motor severity. PD exhibited disruptive sensorimotor and visual networks in early disease stage. DMN, a certain areas in the cerebellum and midbrain may compensate for disruptive sensorimotor and visual network in PD. Disruptive network architecture may be an early alteration of PD pathophysiology but may not serve as a valid biomarker yet. Copyright © 2017. Published by Elsevier B.V.

  19. An In-Home Digital Network Architecture for Real-Time and Non-Real-Time Communication

    NARCIS (Netherlands)

    Scholten, Johan; Jansen, P.G.; Hanssen, F.T.Y.; Hattink, Tjalling

    This paper describes an in-home digital network architecture that supports both realtime and non-real-time communication. The architecture deploys a distributed token mechanism to schedule communication streams and to offer guaranteed quality-ofservice. Essentially, the token mechanism prevents

  20. An In-Home Digital Network Architecture for Real-Time and Non-Real-Time Communication

    NARCIS (Netherlands)

    Scholten, Johan; Jansen, P.G.; Hanssen, F.T.Y.; Hattink, Tjalling

    2002-01-01

    This paper describes an in-home digital network architecture that supports both real-time and non-real-time communication. The architecture deploys a distributed token mechanism to schedule communication streams and to offer guaranteed quality-ofservice. Essentially, the token mechanism prevents

  1. An In-Home Digital Network Architecture for Real-Time and Non-Real-Time Communication

    NARCIS (Netherlands)

    Scholten, Johan; Jansen, P.G.; Hanssen, F.T.Y.; Hattink, Tjalling

    2002-01-01

    This paper describes an in-home digital network architecture that supports both realtime and non-real-time communication. The architecture deploys a distributed token mechanism to schedule communication streams and to offer guaranteed quality-ofservice. Essentially, the token mechanism prevents

  2. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  3. Network architecture design of an agile sensing system with sandwich wireless sensor nodes

    Science.gov (United States)

    Dorvash, S.; Li, X.; Pakzad, S.; Cheng, L.

    2012-04-01

    Wireless sensor network (WSN) is recently emerged as a powerful tool in the structural health monitoring (SHM). Due to the limitations of wireless channel capacity and the heavy data traffic, the control on the network is usually not real time. On the other hand, many SHM applications require quick response when unexpected events, such as earthquake, happen. Realizing the need to have an agile monitoring system, an approach, called sandwich node, was proposed. Sandwich is a design of complex sensor node where two Imote2 nodes are connected with each other to enhance the capabilities of the sensing units. The extra channel and processing power, added into the nodes, enable agile responses of the sensing network, particularly in interrupting the network and altering the undergoing tasks for burst events. This paper presents the design of a testbed for examination of the performance of wireless sandwich nodes in a network. The designed elements of the network are the software architecture of remote and local nodes, and the triggering strategies for coordinating the sensing units. The performance of the designed network is evaluated through its implementation in a monitoring test in the laboratory. For both original Imote2 and the sandwich node, the response time is estimated. The results show that the sandwich node is an efficient solution to the collision issue in existing interrupt approaches and the latency in dense wireless sensor networks.

  4. An Evaluation of Best Effort Traffic Management of Server and Agent-Based Active Network Management (SAAM) Architecture

    National Research Council Canada - National Science Library

    Ayvat, Birol

    2003-01-01

    The Server and Agent-based Active Network Management (SAAM) architecture was initially designed to work with the next generation Internet where increasingly sophisticated applications will require QoS guarantees...

  5. Architecture of the Multi-Modal Organizational Research and Production Heterogeneous Network (MORPHnet)

    Energy Technology Data Exchange (ETDEWEB)

    Aiken, R.J.; Carlson, R.A.; Foster, I.T. [and others

    1997-01-01

    The research and education (R&E) community requires persistent and scaleable network infrastructure to concurrently support production and research applications as well as network research. In the past, the R&E community has relied on supporting parallel network and end-node infrastructures, which can be very expensive and inefficient for network service managers and application programmers. The grand challenge in networking is to provide support for multiple, concurrent, multi-layer views of the network for the applications and the network researchers, and to satisfy the sometimes conflicting requirements of both while ensuring one type of traffic does not adversely affect the other. Internet and telecommunications service providers will also benefit from a multi-modal infrastructure, which can provide smoother transitions to new technologies and allow for testing of these technologies with real user traffic while they are still in the pre-production mode. The authors proposed approach requires the use of as much of the same network and end system infrastructure as possible to reduce the costs needed to support both classes of activities (i.e., production and research). Breaking the infrastructure into segments and objects (e.g., routers, switches, multiplexors, circuits, paths, etc.) gives the capability to dynamically construct and configure the virtual active networks to address these requirements. These capabilities must be supported at the campus, regional, and wide-area network levels to allow for collaboration by geographically dispersed groups. The Multi-Modal Organizational Research and Production Heterogeneous Network (MORPHnet) described in this report is an initial architecture and framework designed to identify and support the capabilities needed for the proposed combined infrastructure and to address related research issues.

  6. Architecture of basic building blocks in protein and domain structural interaction networks.

    Science.gov (United States)

    Moon, Hyun S; Bhak, Jonghwa; Lee, Kwang H; Lee, Doheon

    2005-04-15

    The structural interaction of proteins and their domains in networks is one of the most basic molecular mechanisms for biological cells. Topological analysis of such networks can provide an understanding of and solutions for predicting properties of proteins and their evolution in terms of domains. A single paradigm for the analysis of interactions at different layers, such as domain and protein layers, is needed. Applying a colored vertex graph model, we integrated two basic interaction layers under a unified model: (1) structural domains and (2) their protein/complex networks. We identified four basic and distinct elements in the model that explains protein interactions at the domain level. We searched for motifs in the networks to detect their topological characteristics using a pruning strategy and a hash table for rapid detection. We obtained the following results: first, compared with a random distribution, a substantial part of the protein interactions could be explained by domain-level structural interaction information. Second, there were distinct kinds of protein interaction patterns classified by specific and distinguishable numbers of domains. The intermolecular domain interaction was the most dominant protein interaction pattern. Third, despite the coverage of the protein interaction information differing among species, the similarity of their networks indicated shared architectures of protein interaction network in living organisms. Remarkably, there were only a few basic architectures in the model (>10 for a 4-node network topology), and we propose that most biological combinations of domains into proteins and complexes can be explained by a small number of key topological motifs. doheon@kaist.ac.kr.

  7. Devices and architectures for large-scale integrated silicon photonics circuits

    Science.gov (United States)

    Beausoleil, Raymond G.; Faraon, Andrei; Fattal, David; Fiorentino, Marco; Peng, Zhen; Santori, Charles

    2011-01-01

    We present DWDM nanophotonics architectures based on microring resonator modulators and detectors. We focus on two implementations: an on chip interconnect for multicore processor (Corona) and a high radix network switch (HyperX). Based on the requirements of these applications we discuss the key constraints on the photonic circuits' devices and fabrication techniques as well as strategies to improve their performance.

  8. Spatially constrained adaptive rewiring in cortical networks creates spatially modular small world architectures.

    Science.gov (United States)

    Jarman, Nicholas; Trengove, Chris; Steur, Erik; Tyukin, Ivan; van Leeuwen, Cees

    2014-12-01

    A modular small-world topology in functional and anatomical networks of the cortex is eminently suitable as an information processing architecture. This structure was shown in model studies to arise adaptively; it emerges through rewiring of network connections according to patterns of synchrony in ongoing oscillatory neural activity. However, in order to improve the applicability of such models to the cortex, spatial characteristics of cortical connectivity need to be respected, which were previously neglected. For this purpose we consider networks endowed with a metric by embedding them into a physical space. We provide an adaptive rewiring model with a spatial distance function and a corresponding spatially local rewiring bias. The spatially constrained adaptive rewiring principle is able to steer the evolving network topology to small world status, even more consistently so than without spatial constraints. Locally biased adaptive rewiring results in a spatial layout of the connectivity structure, in which topologically segregated modules correspond to spatially segregated regions, and these regions are linked by long-range connections. The principle of locally biased adaptive rewiring, thus, may explain both the topological connectivity structure and spatial distribution of connections between neuronal units in a large-scale cortical architecture.

  9. Level architecture in genetic regulatory networks and the role of microRNAs

    Science.gov (United States)

    Schwarz, J. M.

    2008-03-01

    It is well known that genes that code for proteins regulate the expression of each other through protein-mediated interactions. With the discovery of microRNAs^1 (miRNAs), it has been conjectured that there are many such regulatory miRNAs in the cell that are never transcribed into proteins but are important for regulation and, hence, could explain the nature of the non-coding (or junk) DNA.^2 Furthermore, miRNAs are highly conserved molecules. So, just as genes that code for proteins form regulatory networks, we conjecture that miRNAs form a higher-level regulatory network amongst themselves as mediated by the genes-coding-for-proteins regulatory network to form a complex organism. We investigate this conjecture within the framework of random Boolean networks where the two-level architecture is modelled via two coupled random Boolean networks with one network taking precedence over the other for various input/output values. Aspects of the evolution of the lower-level network will also be addressed. ^1 D. P. Bartel, Cell 116, 281 (2004). ^2 J. S. Mattick, Sci. Amer. 291, 60 (2004).

  10. Source-synchronous networks-on-chip circuit and architectural interconnect modeling

    CERN Document Server

    Mandal, Ayan; Mahapatra, Rabi

    2014-01-01

    This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

  11. A service-oriented architecture for integrating the modeling and formal verification of genetic regulatory networks.

    Science.gov (United States)

    Monteiro, Pedro T; Dumas, Estelle; Besson, Bruno; Mateescu, Radu; Page, Michel; Freitas, Ana T; de Jong, Hidde

    2009-12-30

    The study of biological networks has led to the development of increasingly large and detailed models. Computer tools are essential for the simulation of the dynamical behavior of the networks from the model. However, as the size of the models grows, it becomes infeasible to manually verify the predictions against experimental data or identify interesting features in a large number of simulation traces. Formal verification based on temporal logic and model checking provides promising methods to automate and scale the analysis of the models. However, a framework that tightly integrates modeling and simulation tools with model checkers is currently missing, on both the conceptual and the implementational level. We have developed a generic and modular web service, based on a service-oriented architecture, for integrating the modeling and formal verification of genetic regulatory networks. The architecture has been implemented in the context of the qualitative modeling and simulation tool GNA and the model checkers NUSMV and CADP. GNA has been extended with a verification module for the specification and checking of biological properties. The verification module also allows the display and visual inspection of the verification results. The practical use of the proposed web service is illustrated by means of a scenario involving the analysis of a qualitative model of the carbon starvation response in E. coli. The service-oriented architecture allows modelers to define the model and proceed with the specification and formal verification of the biological properties by means of a unified graphical user interface. This guarantees a transparent access to formal verification technology for modelers of genetic regulatory networks.

  12. A service-oriented architecture for integrating the modeling and formal verification of genetic regulatory networks

    Directory of Open Access Journals (Sweden)

    Page Michel

    2009-12-01

    Full Text Available Abstract Background The study of biological networks has led to the development of increasingly large and detailed models. Computer tools are essential for the simulation of the dynamical behavior of the networks from the model. However, as the size of the models grows, it becomes infeasible to manually verify the predictions against experimental data or identify interesting features in a large number of simulation traces. Formal verification based on temporal logic and model checking provides promising methods to automate and scale the analysis of the models. However, a framework that tightly integrates modeling and simulation tools with model checkers is currently missing, on both the conceptual and the implementational level. Results We have developed a generic and modular web service, based on a service-oriented architecture, for integrating the modeling and formal verification of genetic regulatory networks. The architecture has been implemented in the context of the qualitative modeling and simulation tool GNA and the model checkers NUSMV and CADP. GNA has been extended with a verification module for the specification and checking of biological properties. The verification module also allows the display and visual inspection of the verification results. Conclusions The practical use of the proposed web service is illustrated by means of a scenario involving the analysis of a qualitative model of the carbon starvation response in E. coli. The service-oriented architecture allows modelers to define the model and proceed with the specification and formal verification of the biological properties by means of a unified graphical user interface. This guarantees a transparent access to formal verification technology for modelers of genetic regulatory networks.

  13. A service-oriented architecture for integrating the modeling and formal verification of genetic regulatory networks

    Science.gov (United States)

    2009-01-01

    Background The study of biological networks has led to the development of increasingly large and detailed models. Computer tools are essential for the simulation of the dynamical behavior of the networks from the model. However, as the size of the models grows, it becomes infeasible to manually verify the predictions against experimental data or identify interesting features in a large number of simulation traces. Formal verification based on temporal logic and model checking provides promising methods to automate and scale the analysis of the models. However, a framework that tightly integrates modeling and simulation tools with model checkers is currently missing, on both the conceptual and the implementational level. Results We have developed a generic and modular web service, based on a service-oriented architecture, for integrating the modeling and formal verification of genetic regulatory networks. The architecture has been implemented in the context of the qualitative modeling and simulation tool GNA and the model checkers NUSMV and CADP. GNA has been extended with a verification module for the specification and checking of biological properties. The verification module also allows the display and visual inspection of the verification results. Conclusions The practical use of the proposed web service is illustrated by means of a scenario involving the analysis of a qualitative model of the carbon starvation response in E. coli. The service-oriented architecture allows modelers to define the model and proceed with the specification and formal verification of the biological properties by means of a unified graphical user interface. This guarantees a transparent access to formal verification technology for modelers of genetic regulatory networks. PMID:20042075

  14. A Networked Perspective on the Engineering Design Process: At the Intersection of Process and Organisation Architectures

    DEFF Research Database (Denmark)

    Parraguez, Pedro

    The design process of engineering systems frequently involves hundreds of activities and people over long periods of time and is implemented through complex networks of information exchanges. Such socio-technical complexity makes design processes hard to manage, and as a result, engineering design...... of a networked perspective also has limited the study of the relationships between process complexity and process performance. This thesis argues that to understand and improve design processes, we must look beyond the planned process and unfold the network structure and composition that actually implement...... the process. This combination of process structure—how people and activities are connected—and composition—the functional diversity of the groups participating in the process—is referred to as the actual design process architecture. This thesis reports on research undertaken to develop, apply and test...

  15. GPU: the biggest key processor for AI and parallel processing

    Science.gov (United States)

    Baji, Toru

    2017-07-01

    Two types of processors exist in the market. One is the conventional CPU and the other is Graphic Processor Unit (GPU). Typical CPU is composed of 1 to 8 cores while GPU has thousands of cores. CPU is good for sequential processing, while GPU is good to accelerate software with heavy parallel executions. GPU was initially dedicated for 3D graphics. However from 2006, when GPU started to apply general-purpose cores, it was noticed that this architecture can be used as a general purpose massive-parallel processor. NVIDIA developed a software framework Compute Unified Device Architecture (CUDA) that make it possible to easily program the GPU for these application. With CUDA, GPU started to be used in workstations and supercomputers widely. Recently two key technologies are highlighted in the industry. The Artificial Intelligence (AI) and Autonomous Driving Cars. AI requires a massive parallel operation to train many-layers of neural networks. With CPU alone, it was impossible to finish the training in a practical time. The latest multi-GPU system with P100 makes it possible to finish the training in a few hours. For the autonomous driving cars, TOPS class of performance is required to implement perception, localization, path planning processing and again SoC with integrated GPU will play a key role there. In this paper, the evolution of the GPU which is one of the biggest commercial devices requiring state-of-the-art fabrication technology will be introduced. Also overview of the GPU demanding key application like the ones described above will be introduced.

  16. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  17. Multithreading in vector processors

    Energy Technology Data Exchange (ETDEWEB)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  18. Design of Smart Power-Saving Architecture for Network on Chip

    Directory of Open Access Journals (Sweden)

    Trong-Yen Lee

    2014-01-01

    Full Text Available In network-on-chip (NoC, the data transferring by virtual channels can avoid the issue of data loss and deadlock. Many virtual channels on one input or output port in router are included. However, the router includes five I/O ports, and then the power issue is very important in virtual channels. In this paper, a novel architecture, namely, Smart Power-Saving (SPS, for low power consumption and low area in virtual channels of NoC is proposed. The SPS architecture can accord different environmental factors to dynamically save power and optimization area in NoC. Comparison with related works, the new proposed method reduces 37.31%, 45.79%, and 19.26% on power consumption and reduces 49.4%, 25.5% and 14.4% on area, respectively.

  19. A Web of Things-Based Emerging Sensor Network Architecture for Smart Control Systems

    Directory of Open Access Journals (Sweden)

    Murad Khan

    2017-02-01

    Full Text Available The Web of Things (WoT plays an important role in the representation of the objects connected to the Internet of Things in a more transparent and effective way. Thus, it enables seamless and ubiquitous web communication between users and the smart things. Considering the importance of WoT, we propose a WoT-based emerging sensor network (WoT-ESN, which collects data from sensors, routes sensor data to the web, and integrate smart things into the web employing a representational state transfer (REST architecture. A smart home scenario is introduced to evaluate the proposed WoT-ESN architecture. The smart home scenario is tested through computer simulation of the energy consumption of various household appliances, device discovery, and response time performance. The simulation results show that the proposed scheme significantly optimizes the energy consumption of the household appliances and the response time of the appliances.

  20. A Web of Things-Based Emerging Sensor Network Architecture for Smart Control Systems

    Science.gov (United States)

    Khan, Murad; Silva, Bhagya Nathali; Han, Kijun

    2017-01-01

    The Web of Things (WoT) plays an important role in the representation of the objects connected to the Internet of Things in a more transparent and effective way. Thus, it enables seamless and ubiquitous web communication between users and the smart things. Considering the importance of WoT, we propose a WoT-based emerging sensor network (WoT-ESN), which collects data from sensors, routes sensor data to the web, and integrate smart things into the web employing a representational state transfer (REST) architecture. A smart home scenario is introduced to evaluate the proposed WoT-ESN architecture. The smart home scenario is tested through computer simulation of the energy consumption of various household appliances, device discovery, and response time performance. The simulation results show that the proposed scheme significantly optimizes the energy consumption of the household appliances and the response time of the appliances.  PMID:28208787

  1. A Web of Things-Based Emerging Sensor Network Architecture for Smart Control Systems.

    Science.gov (United States)

    Khan, Murad; Silva, Bhagya Nathali; Han, Kijun

    2017-02-09

    The Web of Things (WoT) plays an important role in the representation of the objects connected to the Internet of Things in a more transparent and effective way. Thus, it enables seamless and ubiquitous web communication between users and the smart things. Considering the importance of WoT, we propose a WoT-based emerging sensor network (WoT-ESN), which collects data from sensors, routes sensor data to the web, and integrate smart things into the web employing a representational state transfer (REST) architecture. A smart home scenario is introduced to evaluate the proposed WoT-ESN architecture. The smart home scenario is tested through computer simulation of the energy consumption of various household appliances, device discovery, and response time performance. The simulation results show that the proposed scheme significantly optimizes the energy consumption of the household appliances and the response time of the appliances.

  2. Architectures and Design for Next-Generation Hybrid Circuit/Packet Networks

    Science.gov (United States)

    Vadrevu, Sree Krishna Chaitanya

    Internet traffic is increasing rapidly at an annual growth rate of 35% with aggregate traffic exceeding several Exabyte's per month. The traffic is also becoming heterogeneous in bandwidth and quality-of-service (QoS) requirements with growing popularity of cloud computing, video-on-demand (VoD), e-science, etc. Hybrid circuit/packet networks which can jointly support circuit and packet services along with the adoption of high-bit-rate transmission systems form an attractive solution to address the traffic growth. 10 Gbps and 40 Gbps transmission systems are widely deployed in telecom backbone networks such as Comcast, AT&T, etc., and network operators are considering migration to 100 Gbps and beyond. This dissertation proposes robust architectures, capacity migration strategies, and novel service frameworks for next-generation hybrid circuit/packet architectures. In this dissertation, we study two types of hybrid circuit/packet networks: a) IP-over-WDM networks, in which the packet (IP) network is overlaid on top of the circuit (optical WDM) network and b) Hybrid networks in which the circuit and packet networks are deployed side by side such as US DoE's ESnet. We investigate techniques to dynamically migrate capacity between the circuit and packet sections by exploiting traffic variations over a day, and our methods show that significant bandwidth savings can be obtained with improved reliability of services. Specifically, we investigate how idle backup circuit capacity can be used to support packet services in IP-over-WDM networks, and similarly, excess capacity in packet network to support circuit services in ESnet. Control schemes that enable our mechanisms are also discussed. In IP-over-WDM networks, with upcoming 100 Gbps and beyond, dedicated protection will induce significant under-utilization of backup resources. We investigate design strategies to loan idle circuit backup capacity to support IP/packet services. However, failure of backup circuits will

  3. Power estimation on functional level for programmable processors

    Directory of Open Access Journals (Sweden)

    M. Schneider

    2004-01-01

    Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

  4. Analysis and design of a new network architecture based on SOTDMA in mobile service and its application

    Science.gov (United States)

    Chen, Wei; Ren, Xiaoming; Liu, Ruheng

    2004-03-01

    Self-organized time division multiple access ( SOTDMA) is an advanced wireless communication technology used in quick automatic networking. Also self-organized network is an equity network, which is provided with selforganized characteristics. First, the paper analyses the technology and characteristics of self-organized network and puts forward network architecture with self-organized model for different environments. Then it discusses the message transport protocol of SOTDMA, further gives a clear description of the functions for each layer in the network architecture. Second, the paper studies the access algorithms of SOTDMA, providing a full flow for the realization of this algorithm. Finally, the paper induces the practical application of this technology, and raises an integrated principle diagram of wireless user terminal networking based on SOTDMA.

  5. Security Analysis of DTN Architecture and Bundle Protocol Specification for Space-Based Networks

    Science.gov (United States)

    Ivancic, William D.

    2009-01-01

    A Delay-Tolerant Network (DTN) Architecture (Request for Comment, RFC-4838) and Bundle Protocol Specification, RFC-5050, have been proposed for space and terrestrial networks. Additional security specifications have been provided via the Bundle Security Specification (currently a work in progress as an Internet Research Task Force internet-draft) and, for link-layer protocols applicable to Space networks, the Licklider Transport Protocol Security Extensions. This document provides a security analysis of the current DTN RFCs and proposed security related internet drafts with a focus on space-based communication networks, which is a rather restricted subset of DTN networks. Note, the original focus and motivation of DTN work was for the Interplanetary Internet . This document does not address general store-and-forward network overlays, just the current work being done by the Internet Research Task Force (IRTF) and the Consultative Committee for Space Data Systems (CCSDS) Space Internetworking Services Area (SIS) - DTN working group under the DTN and Bundle umbrellas. However, much of the analysis is relevant to general store-and-forward overlays.

  6. Seamless interworking architecture for WBAN in heterogeneous wireless networks with QoS guarantees.

    Science.gov (United States)

    Khan, Pervez; Ullah, Niamat; Ullah, Sana; Kwak, Kyung Sup

    2011-10-01

    The IEEE 802.15.6 standard is a communication standard optimized for low-power and short-range in-body/on-body nodes to serve a variety of medical, consumer electronics and entertainment applications. Providing high mobility with guaranteed Quality of Service (QoS) to a WBAN user in heterogeneous wireless networks is a challenging task. A WBAN uses a Personal Digital Assistant (PDA) to gather data from body sensors and forwards it to a remote server through wide range wireless networks. In this paper, we present a coexistence study of WBAN with Wireless Local Area Networks (WLAN) and Wireless Wide Area Networks (WWANs). The main issue is interworking of WBAN in heterogenous wireless networks including seamless handover, QoS, emergency services, cooperation and security. We propose a Seamless Interworking Architecture (SIA) for WBAN in heterogenous wireless networks based on a cost function. The cost function is based on power consumption and data throughput costs. Our simulation results show that the proposed scheme outperforms typical approaches in terms of throughput, delay and packet loss rate.

  7. Architecture of an antagonistic tree/fungus network: the asymmetric influence of past evolutionary history.

    Science.gov (United States)

    Vacher, Corinne; Piou, Dominique; Desprez-Loustau, Marie-Laure

    2008-03-05

    Compartmentalization and nestedness are common patterns in ecological networks. The aim of this study was to elucidate some of the processes shaping these patterns in a well resolved network of host/pathogen interactions. Based on a long-term (1972-2005) survey of forest health at the regional scale (all French forests; 15 million ha), we uncovered an almost fully connected network of 51 tree taxa and 157 parasitic fungal species. Our analyses revealed that the compartmentalization of the network maps out the ancient evolutionary history of seed plants, but not the ancient evolutionary history of fungal species. The very early divergence of the major fungal phyla may account for this asymmetric influence of past evolutionary history. Unlike compartmentalization, nestedness did not reflect any consistent phylogenetic signal. Instead, it seemed to reflect the ecological features of the current species, such as the relative abundance of tree species and the life-history strategies of fungal pathogens. We discussed how the evolution of host range in fungal species may account for the observed nested patterns. Overall, our analyses emphasized how the current complexity of ecological networks results from the diversification of the species and their interactions over evolutionary times. They confirmed that the current architecture of ecological networks is not only dependent on recent ecological processes.

  8. Communication Network Architectures for Smart-House with Renewable Energy Resources

    Directory of Open Access Journals (Sweden)

    Mohamed A. Ahmed

    2015-08-01

    Full Text Available With the microgrid revolution, each house will have the ability to meet its own energy needs locally from renewable energy sources such as solar or wind. However, real-time data gathering, energy management and control of renewable energy systems will depend mainly on the performance of the communications infrastructure. This paper describes the design of a communication network architecture using both wired and wireless technologies for monitoring and controlling distributed energy systems involving small-scale wind turbines and photovoltaic systems. The proposed communication architecture consists of three layers: device layer, network layer, and application layer. Two scenarios are considered: a smart-house and a smart-building. Various types of sensor nodes and measurement devices are defined to monitor the condition of the renewable energy systems based on the international electrotechnical commission standard. The OPNET Modeler is used for performance evaluation in terms of end-to-end (ETE delay. The network performance is compared in view of ETE delay, reliability and implementation cost for three different technologies: Ethernet-based, WiFi-based, and ZigBee-based.

  9. A Unified Robotic Software Architecture for Service Robotics and Networks of Smart Sensors

    Science.gov (United States)

    Westhoff, Daniel; Zhang, Jianwei

    This paper proposes a novel architecture for the programming of multi-modal service robots and networked sensors. The presented software framework eases the development of high-level applications for distributed systems. The software architecture is based upon the Roblet-Technology, which is an exceptionally powerful medium in robotics. The possibility to develop, compile and execute an application on one workstation and distribute parts of a program based on the idea of mobile code is pointed out. Since the Roblet-Technology uses Java the development is independent of the operation system. The framework hides the network communication and therefore greatly improves the programming and testing of applications in service robotics. The concept is evaluated in the context of the service robot TASER of the TAMS Institute at the University of Hamburg. This robot consists of a mobile platform with two manipulators equipped with artificial hands. Several multimodal input and output devices for interaction round off the robot. Networked cameras in the working environment of TASER provide additional information to the robot. The integration of these smart sensors shows the extendability of the proposed concept to general distributed systems.

  10. A FD/DAMA network architecture for the first generation land mobile satellite services

    Science.gov (United States)

    Yan, T.-Y.; Wang, C.; Cheng, U.; Dessouky, K.; Rafferty, W.

    1989-01-01

    A frequency division/demand assigned multiple access (FD/DAMA) network architecture for the first-generation land mobile satellite services is presented. Rationales and technical approaches are described. In this architecture, each mobile subscriber must follow a channel access protocol to make a service request to the network management center before transmission for either open-end or closed-end services. Open-end service requests will be processed on a blocked call cleared basis, while closed-end requests will be processed on a first-come-first-served basis. Two channel access protocols are investigated, namely, a recently proposed multiple channel collision resolution scheme which provides a significantly higher useful throughput, and the traditional slotted Aloha scheme. The number of channels allocated for either open-end or closed-end services can be adaptively changed according to aggregated traffic requests. Both theoretical and simulation results are presented. Theoretical results have been verified by simulation on the JPL network testbed.

  11. An Optimal Path Computation Architecture for the Cloud-Network on Software-Defined Networking

    Directory of Open Access Journals (Sweden)

    Hyunhun Cho

    2015-05-01

    Full Text Available Legacy networks do not open the precise information of the network domain because of scalability, management and commercial reasons, and it is very hard to compute an optimal path to the destination. According to today’s ICT environment change, in order to meet the new network requirements, the concept of software-defined networking (SDN has been developed as a technological alternative to overcome the limitations of the legacy network structure and to introduce innovative concepts. The purpose of this paper is to propose the application that calculates the optimal paths for general data transmission and real-time audio/video transmission, which consist of the major services of the National Research & Education Network (NREN in the SDN environment. The proposed SDN routing computation (SRC application is designed and applied in a multi-domain network for the efficient use of resources, selection of the optimal path between the multi-domains and optimal establishment of end-to-end connections.

  12. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  13. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2005-01-01

    On-chip networks for future system-on-chip designs need simple, high performance implementations. In order to promote system-level integrity, guaranteed services (GS) need to be provided. We propose a network-on-chip (NoC) router architecture to support this, and demonstrate with a CMOS standard...

  14. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks

    Science.gov (United States)

    Aghdasi, Hadi S.; Abbaspour, Maghsoud; Moghadam, Mohsen Ebrahimi; Samei, Yasaman

    2008-01-01

    Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS) and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN). With regards to the constraints of video-based sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture). This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality. PMID:27873772

  15. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks

    Directory of Open Access Journals (Sweden)

    Yasaman Samei

    2008-08-01

    Full Text Available Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN. With regards to the constraints of videobased sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture. This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality.

  16. An Energy-Efficient and High-Quality Video Transmission Architecture in Wireless Video-Based Sensor Networks.

    Science.gov (United States)

    Aghdasi, Hadi S; Abbaspour, Maghsoud; Moghadam, Mohsen Ebrahimi; Samei, Yasaman

    2008-08-04

    Technological progress in the fields of Micro Electro-Mechanical Systems (MEMS) and wireless communications and also the availability of CMOS cameras, microphones and small-scale array sensors, which may ubiquitously capture multimedia content from the field, have fostered the development of low-cost limited resources Wireless Video-based Sensor Networks (WVSN). With regards to the constraints of videobased sensor nodes and wireless sensor networks, a supporting video stream is not easy to implement with the present sensor network protocols. In this paper, a thorough architecture is presented for video transmission over WVSN called Energy-efficient and high-Quality Video transmission Architecture (EQV-Architecture). This architecture influences three layers of communication protocol stack and considers wireless video sensor nodes constraints like limited process and energy resources while video quality is preserved in the receiver side. Application, transport, and network layers are the layers in which the compression protocol, transport protocol, and routing protocol are proposed respectively, also a dropping scheme is presented in network layer. Simulation results over various environments with dissimilar conditions revealed the effectiveness of the architecture in improving the lifetime of the network as well as preserving the video quality.

  17. Space Communications and Navigation (SCaN) Integrated Network Architecture Definition Document (ADD). Volume 1; Executive Summary; Revision 1

    Science.gov (United States)

    Younes, Badri A.; Schier, James S.

    2010-01-01

    The SCaN Program has defined an integrated network architecture that fully meets the Administrator s mandate to the Program, and will result in a NASA infrastructure capable of providing the needed and enabling communications services to future space missions. The integrated network architecture will increase SCaN operational efficiency and interoperability through standardization, commonality and technology infusion. It will enable NASA missions requiring advanced communication and tracking capabilities such as: a. Optical communication b. Antenna arraying c. Lunar and Mars Relays d. Integrated network management (service management and network control) and integrated service execution e. Enhanced tracking for navigation f. Space internetworking with DTN and IP g. End-to-end security h. Enhanced security services Moreover, the SCaN Program has created an Integrated Network Roadmap that depicts an orchestrated and coherent evolution path toward the target architecture, encompassing all aspects that concern network assets (i.e., operations and maintenance, sustaining engineering, upgrade efforts, and major development). This roadmap identifies major NASA ADPs, and shows dependencies and drivers among the various planned undertakings and timelines. The roadmap is scalable to accommodate timely adjustments in response to Agency needs, goals, objectives and funding. Future challenges to implementing this architecture include balancing user mission needs, technology development, and the availability of funding within NASA s priorities. Strategies for addressing these challenges are to: define a flexible architecture, update the architecture periodically, use ADPs to evaluate options and determine when to make decisions, and to engage the stakeholders in these evaluations. In addition, the SCaN Program will evaluate and respond to mission need dates for technical and operational capabilities to be provided by the SCaN integrated network. In that regard, the architecture

  18. Lunar Relay Satellite Network for Space Exploration: Architecture, Technologies and Challenges

    Science.gov (United States)

    Bhasin, Kul B.; Hackenberg, Anthony W.; Slywczak, Richard A.; Bose, Prasanta; Bergamo, Marcos; Hayden, Jeffrey L.

    2006-01-01

    NASA is planning a series of short and long duration human and robotic missions to explore the Moon and then Mars. A key objective of these missions is to grow, through a series of launches, a system of systems infrastructure with the capability for safe and sustainable autonomous operations at minimum cost while maximizing the exploration capabilities and science return. An incremental implementation process will enable a buildup of the communication, navigation, networking, computing, and informatics architectures to support human exploration missions in the vicinities and on the surfaces of the Moon and Mars. These architectures will support all space and surface nodes, including other orbiters, lander vehicles, humans in spacesuits, robots, rovers, human habitats, and pressurized vehicles. This paper describes the integration of an innovative MAC and networking technology with an equally innovative position-dependent, data routing, network technology. The MAC technology provides the relay spacecraft with the capability to autonomously discover neighbor spacecraft and surface nodes, establish variable-rate links and communicate simultaneously with multiple in-space and surface clients at varying and rapidly changing distances while making optimum use of the available power. The networking technology uses attitude sensors, a time synchronization protocol and occasional orbit-corrections to maintain awareness of its instantaneous position and attitude in space as well as the orbital or surface location of its communication clients. A position-dependent data routing capability is used in the communication relay satellites to handle the movement of data among any of multiple clients (including Earth) that may be simultaneously in view; and if not in view, the relay will temporarily store the data from a client source and download it when the destination client comes into view. The integration of the MAC and data routing networking technologies would enable a relay

  19. On-Board Fiber-Optic Network Architectures for Radar and Avionics Signal Distribution

    Science.gov (United States)

    Alam, Mohammad F.; Atiquzzaman, Mohammed; Duncan, Bradley B.; Nguyen, Hung; Kunath, Richard

    2000-01-01

    Continued progress in both civil and military avionics applications is overstressing the capabilities of existing radio-frequency (RF) communication networks based on coaxial cables on board modem aircrafts. Future avionics systems will require high-bandwidth on- board communication links that are lightweight, immune to electromagnetic interference, and highly reliable. Fiber optic communication technology can meet all these challenges in a cost-effective manner. Recently, digital fiber-optic communication systems, where a fiber-optic network acts like a local area network (LAN) for digital data communications, have become a topic of extensive research and development. Although a fiber-optic system can be designed to transport radio-frequency (RF) signals, the digital fiber-optic systems under development today are not capable of transporting microwave and millimeter-wave RF signals used in radar and avionics systems on board an aircraft. Recent advances in fiber optic technology, especially wavelength division multiplexing (WDM), has opened a number of possibilities for designing on-board fiber optic networks, including all-optical networks for radar and avionics RF signal distribution. In this paper, we investigate a number of different novel approaches for fiber-optic transmission of on-board VHF and UHF RF signals using commercial off-the-shelf (COTS) components. The relative merits and demerits of each architecture are discussed, and the suitability of each architecture for particular applications is pointed out. All-optical approaches show better performance than other traditional approaches in terms of signal-to-noise ratio, power consumption, and weight requirements.

  20. Interferon-α acutely impairs whole-brain functional connectivity network architecture - A preliminary study.

    Science.gov (United States)

    Dipasquale, Ottavia; Cooper, Ella A; Tibble, Jeremy; Voon, Valerie; Baglio, Francesca; Baselli, Giuseppe; Cercignani, Mara; Harrison, Neil A

    2016-11-01

    Interferon-alpha (IFN-α) is a key mediator of antiviral immune responses used to treat Hepatitis C infection. Though clinically effective, IFN-α rapidly impairs mood, motivation and cognition, effects that can appear indistinguishable from major depression and provide powerful empirical support for the inflammation theory of depression. Though inflammation has been shown to modulate activity within discrete brain regions, how it affects distributed information processing and the architecture of whole brain functional connectivity networks have not previously been investigated. Here we use a graph theoretic analysis of resting state functional magnetic resonance imaging (rfMRI) to investigate acute effects of systemic interferon-alpha (IFN-α) on whole brain functional connectivity architecture and its relationship to IFN-α-induced mood change. Twenty-two patients with Hepatitis-C infection, initiating IFN-α-based therapy were scanned at baseline and 4h after their first IFN-α dose. The whole brain network was parcellated into 110 cortical and sub-cortical nodes based on the Oxford-Harvard Atlas and effects assessed on higher-level graph metrics, including node degree, betweenness centrality, global and local efficiency. IFN-α was associated with a significant reduction in global network connectivity (node degree) (p=0.033) and efficiency (p=0.013), indicating a global reduction of information transfer among the nodes forming the whole brain network. Effects were similar for highly connected (hub) and non-hub nodes, with no effect on betweenness centrality (p>0.1). At a local level, we identified regions with reduced efficiency of information exchange and a sub-network with decreased functional connectivity after IFN-α. Changes in local and particularly global functional connectivity correlated with associated changes in mood measured on the Profile of Mood States (POMS) questionnaire. IFN-α rapidly induced a profound shift in whole brain network structure

  1. Taking the 'work' out of networking: strategies for smarter, simpler network architecture and administration

    Science.gov (United States)

    Luna, C. de

    2003-01-01

    This session will help you tune up your skills and knowledge on the latest advances in network design and management, to keep your agency's data communications running at peak performance, with minimal cost and effort.

  2. Control Architecture for Intentional Island Operation in Distribution Network with High Penetration of Distributed Generation

    DEFF Research Database (Denmark)

    Chen, Yu

    , the feasibility of the application of Artificial Neural Network (ANN) to ICA is studied, in order to improve the computation efficiency for ISR calculation. Finally, the integration of ICA into Dynamic Security Assessment (DSA), the ICA implementation, and the development of ICA are discussed....... amount of DGs. As part of the NextGen project, this project focuses on the system modeling and simulation regarding the control architecture and recommends the development of a communication and information exchange system based on IEC 61850. This thesis starts with the background of this PhD project...

  3. A Novel Hierarchical Semi-centralized Telemedicine Network Architecture Proposition for Bangladesh

    DEFF Research Database (Denmark)

    Choudhury, Samiul; Peterson, Carrie Beth; Kyriazakos, Sofoklis

    2011-01-01

    One of the major functions of telemedicine is the prompt delivery of modern healthcare to the remotest areas with reduced cost and efficient use of communication resources. The establishment of a well organized telemedicine system is therefore exigent for the developing countries like Bangladesh...... where there are extreme paucities of efficient healthcare professionals and equipments, specifically in the rural areas. In this paper a novel, hierarchical and semi-centralized telemedicine network architecture has been proposed holisti-cally focusing on the rural underdeveloped areas of Bangladesh...

  4. A remote password authentication scheme for multiserver architecture using neural networks.

    Science.gov (United States)

    Li, L H; Lin, L C; Hwang, M S

    2001-01-01

    Conventional remote password authentication schemes allow a serviceable server to authenticate the legitimacy of a remote login user. However, these schemes are not used for multiserver architecture environments. We present a remote password authentication scheme for multiserver environments. The password authentication system is a pattern classification system based on an artificial neural network. In this scheme, the users only remember user identity and password numbers to log in to various servers. Users can freely choose their password. Furthermore, the system is not required to maintain a verification table and can withstand the replay attack.

  5. Architecture and biological applications of artificial neural networks: a tuberculosis perspective.

    Science.gov (United States)

    Darsey, Jerry A; Griffin, William O; Joginipelli, Sravanthi; Melapu, Venkata Kiran

    2015-01-01

    Advancement of science and technology has prompted researchers to develop new intelligent systems that can solve a variety of problems such as pattern recognition, prediction, and optimization. The ability of the human brain to learn in a fashion that tolerates noise and error has attracted many researchers and provided the starting point for the development of artificial neural networks: the intelligent systems. Intelligent systems can acclimatize to the environment or data and can maximize the chances of success or improve the efficiency of a search. Due to massive parallelism with large numbers of interconnected processers and their ability to learn from the data, neural networks can solve a variety of challenging computational problems. Neural networks have the ability to derive meaning from complicated and imprecise data; they are used in detecting patterns, and trends that are too complex for humans, or other computer systems. Solutions to the toughest problems will not be found through one narrow specialization; therefore we need to combine interdisciplinary approaches to discover the solutions to a variety of problems. Many researchers in different disciplines such as medicine, bioinformatics, molecular biology, and pharmacology have successfully applied artificial neural networks. This chapter helps the reader in understanding the basics of artificial neural networks, their applications, and methodology; it also outlines the network learning process and architecture. We present a brief outline of the application of neural networks to medical diagnosis, drug discovery, gene identification, and protein structure prediction. We conclude with a summary of the results from our study on tuberculosis data using neural networks, in diagnosing active tuberculosis, and predicting chronic vs. infiltrative forms of tuberculosis.

  6. Array processors in chemistry

    Energy Technology Data Exchange (ETDEWEB)

    Ostlund, N.S.

    1980-01-01

    The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.

  7. A super base station based centralized network architecture for 5G mobile communication systems

    Directory of Open Access Journals (Sweden)

    Manli Qian

    2015-04-01

    Full Text Available To meet the ever increasing mobile data traffic demand, the mobile operators are deploying a heterogeneous network with multiple access technologies and more and more base stations to increase the network coverage and capacity. However, the base stations are isolated from each other, so different types of radio resources and hardware resources cannot be shared and allocated within the overall network in a cooperative way. The mobile operators are thus facing increasing network operational expenses and a high system power consumption. In this paper, a centralized radio access network architecture, referred to as the super base station (super BS, is proposed, as a possible solution for an energy-efficient fifth-generation (5G mobile system. The super base station decouples the logical functions and physical entities of traditional base stations, so different types of system resources can be horizontally shared and statistically multiplexed among all the virtual base stations throughout the entire system. The system framework and main functionalities of the super BS are described. Some key technologies for system implementation, i.e., the resource pooling, real-time virtualization, adaptive hardware resource allocation are also highlighted.

  8. DReAM: Demand Response Architecture for Multi-level District Heating and Cooling Networks

    Energy Technology Data Exchange (ETDEWEB)

    Bhattacharya, Saptarshi; Chandan, Vikas; Arya, Vijay; Kar, Koushik

    2017-05-19

    In this paper, we exploit the inherent hierarchy of heat exchangers in District Heating and Cooling (DHC) networks and propose DReAM, a novel Demand Response (DR) architecture for Multi-level DHC networks. DReAM serves to economize system operation while still respecting comfort requirements of individual consumers. Contrary to many present day DR schemes that work on a consumer level granularity, DReAM works at a level of hierarchy above buildings, i.e. substations that supply heat to a group of buildings. This improves the overall DR scalability and reduce the computational complexity. In the first step of the proposed approach, mathematical models of individual substations and their downstream networks are abstracted into appropriately constructed low-complexity structural forms. In the second step, this abstracted information is employed by the utility to perform DR optimization that determines the optimal heat inflow to individual substations rather than buildings, in order to achieve the targeted objectives across the network. We validate the proposed DReAM framework through experimental results under different scenarios on a test network.

  9. LPI Optimization Framework for Target Tracking in Radar Network Architectures Using Information-Theoretic Criteria

    Directory of Open Access Journals (Sweden)

    Chenguang Shi

    2014-01-01

    Full Text Available Widely distributed radar network architectures can provide significant performance improvement for target detection and localization. For a fixed radar network, the achievable target detection performance may go beyond a predetermined threshold with full transmitted power allocation, which is extremely vulnerable in modern electronic warfare. In this paper, we study the problem of low probability of intercept (LPI design for radar network and propose two novel LPI optimization schemes based on information-theoretic criteria. For a predefined threshold of target detection, Schleher intercept factor is minimized by optimizing transmission power allocation among netted radars in the network. Due to the lack of analytical closed-form expression for receiver operation characteristics (ROC, we employ two information-theoretic criteria, namely, Bhattacharyya distance and J-divergence as the metrics for target detection performance. The resulting nonconvex and nonlinear LPI optimization problems associated with different information-theoretic criteria are cast under a unified framework, and the nonlinear programming based genetic algorithm (NPGA is used to tackle the optimization problems in the framework. Numerical simulations demonstrate that our proposed LPI strategies are effective in enhancing the LPI performance for radar network.

  10. Relations between the geometry of cortical gyrification and white-matter network architecture.

    Science.gov (United States)

    Henderson, James A; Robinson, Peter A

    2014-03-01

    A geometrically based network model of cortico-cortical white-matter connectivity is used in combination with diffusion spectrum MRI (DSI) data to show that white-matter cortical network architecture is founded on a homogeneous, isotropic geometric connection principle. No other special information about single connections or groups of connections is required to generate networks very similar to experimental ones. This model provides excellent agreement with experimental DSI frequency distributions of network measures-degree, clustering coefficient, path length, and betweenness centrality. In the model, these distributions are a result of geometrically induced spatial variations in the values of these measures with deep nodes having more hublike properties than superficial nodes. This leads to experimentally testable predictions of corresponding variations in real cortexes. The convoluted geometry of the cortex is also found to introduce weak modularity, similar to the lobe structure of the cortex, with the boundaries between modules having hublike properties. These findings mean that some putative discoveries regarding the structure of white-matter cortical networks are simply artifacts and/or consequences of geometry. This model may help provide insight into diseases associated with differences in gyrification as well as evolutionary development of the cortex.

  11. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  12. Support for Programming Models in Network-on-Chip-based Many-core Systems

    DEFF Research Database (Denmark)

    Rasmussen, Morten Sleth

    This thesis addresses aspects of support for programming models in Network-on- Chip-based many-core architectures. The main focus is to consider architectural support for a plethora of programming models in a single system. The thesis has three main parts. The first part considers parallelization...... models to be supported by a single architecture. The architecture features a specialized network interface processor which allows extensive configurability of the memory system. Based on this architecture, a detailed implementation of the cache coherent shared memory programming model is presented...

  13. Adaptive Monitoring and Control Architectures for Power Distribution Grids over Heterogeneous ICT Networks

    DEFF Research Database (Denmark)

    Olsen, Rasmus Løvenstein; Hägerling, Christian; Kurtz, Fabian M.

    2014-01-01

    The expected growth in distributed generation will significantly affect the operation and control of today’s distribution grids. Being confronted with short time power variations of distributed generations, the assurance of a reliable service (grid stability, avoidance of energy losses) and the q......The expected growth in distributed generation will significantly affect the operation and control of today’s distribution grids. Being confronted with short time power variations of distributed generations, the assurance of a reliable service (grid stability, avoidance of energy losses...... to the reliability due to the stochastic behaviour found in such networks. Therefore, key concepts are presented in this paper targeting the support of proper smart grid control in these network environments. An overview on the required Information and Communication Technology (ICT) architecture and its...

  14. AUTHENTICATION ARCHITECTURE USING THRESHOLD CRYPTOGRAPHY IN KERBEROS FOR MOBILE AD HOC NETWORKS

    Directory of Open Access Journals (Sweden)

    Hadj Gharib

    2014-06-01

    Full Text Available The use of wireless technologies is gradually increasing and risks related to the use of these technologies are considerable. Due to their dynamically changing topology and open environment without a centralized policy control of a traditional network, a mobile ad hoc network (MANET is vulnerable to the presence of malicious nodes and attacks. The ideal solution to overcome a myriad of security concerns in MANET’s is the use of reliable authentication architecture. In this paper we propose a new key management scheme based on threshold cryptography in kerberos for MANET’s, the proposed scheme uses the elliptic curve cryptography method that consumes fewer resources well adapted to the wireless environment. Our approach shows a strength and effectiveness against attacks.

  15. LIDeA: A Distributed Lightweight Intrusion Detection Architecture for Sensor Networks

    DEFF Research Database (Denmark)

    Giannetsos, Athanasios; Krontiris, Ioannis; Dimitriou, Tassos

    2008-01-01

    Wireless sensor networks are vulnerable to adversaries as they are frequently deployed in open and unattended environments. Preventive mechanisms can be applied to protect them from an assortment of attacks. However, more sophisticated methods, like intrusion detection systems, are needed...... to achieve a more autonomic and complete defense mechanism, even against attacks that have not been anticipated in advance. In this paper, we present a lightweight intrusion detection system, called LIDeA, designed for wireless sensor networks. LIDeA is based on a distributed architecture, in which nodes...... overhear their neighboring nodes and collaborate with each other in order to successfully detect an intrusion. We show how such a system can be implemented in TinyOS, which components and interfaces are needed, and what is the resulting overhead imposed....

  16. Evolution of gene regulatory network architectures: examples of subcircuit conservation and plasticity between classes of echinoderms.

    Science.gov (United States)

    Hinman, Veronica F; Yankura, Kristen A; McCauley, Brenna S

    2009-04-01

    Developmental gene regulatory networks (GRNs) explain how regulatory states are established in particular cells during development and how these states then determine the final form of the embryo. Evolutionary changes to the sequence of the genome will direct reorganization of GRN architectures, which in turn will lead to the alteration of developmental programs. A comparison of GRN architectures must consequently reveal the molecular basis for the evolution of developmental programs among different organisms. This review highlights some of the important findings that have emerged from the most extensive direct comparison of GRN architectures to date. Comparison of the orthologous GRNs for endomesodermal specification in the sea urchin and sea star, provides examples of several discrete, functional GRN subcircuits and shows that they are subject to diverse selective pressures. This demonstrates that different regulatory linkages may be more or less amenable to evolutionary change. One of the more surprising findings from this comparison is that GRN-level functions may be maintained while the factors performing the functions have changed, suggesting that GRNs have a high capacity for compensatory changes involving transcription factor binding to cis regulatory modules.

  17. The architecture of river networks can drive the evolutionary dynamics of aquatic populations.

    Science.gov (United States)

    Thomaz, Andréa T; Christie, Mark R; Knowles, L Lacey

    2016-03-01

    It is widely recognized that physical landscapes can shape genetic variation within and between populations. However, it is not well understood how riverscapes, with their complex architectures, affect patterns of neutral genetic diversity. Using a spatially explicit agent-based modeling (ABM) approach, we evaluate the genetic consequences of dendritic river shapes on local population structure. We disentangle the relative contribution of specific river properties to observed patterns of genetic variation by evaluating how different branching architectures and downstream flow regimes affect the genetic structure of populations situated within river networks. Irrespective of the river length, our results illustrate that the extent of river branching, confluence position, and levels of asymmetric downstream migration dictate patterns of genetic variation in riverine populations. Comparisons between simple and highly branched rivers show a 20-fold increase in the overall genetic diversity and a sevenfold increase in the genetic differentiation between local populations. Given that most rivers have complex architectures, these results highlight the importance of incorporating riverscape information into evolutionary models of aquatic species and could help explain why riverine fishes represent a disproportionately large amount of global vertebrate diversity per unit of habitable area. © 2016 The Author(s). Evolution © 2016 The Society for the Study of Evolution.

  18. Autonomous, Decentralized Grid Architecture: Prosumer-Based Distributed Autonomous Cyber-Physical Architecture for Ultra-Reliable Green Electricity Networks

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-01-11

    GENI Project: Georgia Tech is developing a decentralized, autonomous, internet-like control architecture and control software system for the electric power grid. Georgia Tech’s new architecture is based on the emerging concept of electricity prosumers—economically motivated actors that can produce, consume, or store electricity. Under Georgia Tech’s architecture, all of the actors in an energy system are empowered to offer associated energy services based on their capabilities. The actors achieve their sustainability, efficiency, reliability, and economic objectives, while contributing to system-wide reliability and efficiency goals. This is in marked contrast to the current one-way, centralized control paradigm.

  19. Experimental demonstration of OpenFlow-enabled media ecosystem architecture for high-end applications over metro and core networks.

    Science.gov (United States)

    Ntofon, Okung-Dike; Channegowda, Mayur P; Efstathiou, Nikolaos; Rashidi Fard, Mehdi; Nejabati, Reza; Hunter, David K; Simeonidou, Dimitra

    2013-02-25

    In this paper, a novel Software-Defined Networking (SDN) architecture is proposed for high-end Ultra High Definition (UHD) media applications. UHD media applications require huge amounts of bandwidth that can only be met with high-capacity optical networks. In addition, there are requirements for control frameworks capable of delivering effective application performance with efficient network utilization. A novel SDN-based Controller that tightly integrates application-awareness with network control and management is proposed for such applications. An OpenFlow-enabled test-bed demonstrator is reported with performance evaluations of advanced online and offline media- and network-aware schedulers.

  20. Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

    Directory of Open Access Journals (Sweden)

    Diana Göhringer

    2012-01-01

    Full Text Available This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC. The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.

  1. An efficient architecture for the integration of sensor and actuator networks into the future internet

    Science.gov (United States)

    Schneider, J.; Klein, A.; Mannweiler, C.; Schotten, H. D.

    2011-08-01

    In the future, sensors will enable a large variety of new services in different domains. Important application areas are service adaptations in fixed and mobile environments, ambient assisted living, home automation, traffic management, as well as management of smart grids. All these applications will share a common property, the usage of networked sensors and actuators. To ensure an efficient deployment of such sensor-actuator networks, concepts and frameworks for managing and distributing sensor data as well as for triggering actuators need to be developed. In this paper, we present an architecture for integrating sensors and actuators into the future Internet. In our concept, all sensors and actuators are connected via gateways to the Internet, that will be used as comprehensive transport medium. Additionally, an entity is needed for registering all sensors and actuators, and managing sensor data requests. We decided to use a hierarchical structure, comparable to the Domain Name Service. This approach realizes a cost-efficient architecture disposing of "plug and play" capabilities and accounting for privacy issues.

  2. Architecture for an integrated real-time air combat and sensor network simulation

    Science.gov (United States)

    Criswell, Evans A.; Rushing, John; Lin, Hong; Graves, Sara

    2007-04-01

    An architecture for an integrated air combat and sensor network simulation is presented. The architecture integrates two components: a parallel real-time sensor fusion and target tracking simulation, and an air combat simulation. By integrating these two simulations, it becomes possible to experiment with scenarios in which one or both sides in a battle have very large numbers of primitive passive sensors, and to assess the likely effects of those sensors on the outcome of the battle. Modern Air Power is a real-time theater-level air combat simulation that is currently being used as a part of the USAF Air and Space Basic Course (ASBC). The simulation includes a variety of scenarios from the Vietnam war to the present day, and also includes several hypothetical future scenarios. Modern Air Power includes a scenario editor, an order of battle editor, and full AI customization features that make it possible to quickly construct scenarios for any conflict of interest. The scenario editor makes it possible to place a wide variety of sensors including both high fidelity sensors such as radars, and primitive passive sensors that provide only very limited information. The parallel real-time sensor network simulation is capable of handling very large numbers of sensors on a computing cluster of modest size. It can fuse information provided by disparate sensors to detect and track targets, and produce target tracks.

  3. Information processing in network architecture of genome controlled signal transduction circuit. A proposed theoretical explanation.

    Science.gov (United States)

    Chakraborty, Chiranjib; Sarkar, Bimal Kumar; Patel, Pratiksha; Agoramoorthy, Govindasamy

    2012-01-01

    In this paper, Shannon information theory has been applied to elaborate cell signaling. It is proposed that in the cellular network architecture, four components viz. source (DNA), transmitter (mRNA), receiver (protein) and destination (another protein) are involved. The message transmits from source (DNA) to transmitter (mRNA) and then passes through a noisy channel reaching finally the receiver (protein). The protein synthesis process is here considered as the noisy channel. Ultimately, signal is transmitted from receiver to destination (another protein). The genome network architecture elements were compared with genetic alphabet L = {A, C, G, T} with a biophysical model based on the popular Shannon information theory. This study found the channel capacity as maximum for zero error (sigma = 0) and at this condition, transition matrix becomes a unit matrix with rank 4. The transition matrix will be erroneous and finally at sigma = 1 channel capacity will be localized maxima with a value of 0.415 due to the increased value at sigma. On the other hand, minima exists at sigma = 0.75, where all transition probabilities become 0.25 and uncertainty will be maximum resulting in channel capacity with the minima value of zero.

  4. Optimization of neural network architecture for classification of radar jamming FM signals

    Science.gov (United States)

    Soto, Alberto; Mendoza, Ariadna; Flores, Benjamin C.

    2017-05-01

    The purpose of this study is to investigate several artificial Neural Network (NN) architectures in order to design a cognitive radar system capable of optimally distinguishing linear Frequency-Modulated (FM) signals from bandlimited Additive White Gaussian Noise (AWGN). The goal is to create a theoretical framework to determine an optimal NN architecture to achieve a Probability of Detection (PD) of 95% or higher and a Probability of False Alarm (PFA) of 1.5% or lower at 5 dB Signal to Noise Ratio (SNR). Literature research reveals that the frequency-domain power spectral densities characterize a signal more efficiently than its time-domain counterparts. Therefore, the input data is preprocessed by calculating the magnitude square of the Discrete Fourier Transform of the digitally sampled bandlimited AWGN and linear FM signals to populate a matrix containing N number of samples and M number of spectra. This matrix is used as input for the NN, and the spectra are divided as follows: 70% for training, 15% for validation, and 15% for testing. The study begins by experimentally deducing the optimal number of hidden neurons (1-40 neurons), then the optimal number of hidden layers (1-5 layers), and lastly, the most efficient learning algorithm. The training algorithms examined are: Resilient Backpropagation, Scaled Conjugate Gradient, Conjugate Gradient with Powell/Beale Restarts, Polak-Ribiére Conjugate Gradient, and Variable Learning Rate Backpropagation. We determine that an architecture with ten hidden neurons (or higher), one hidden layer, and a Scaled Conjugate Gradient for training algorithm encapsulates an optimal architecture for our application.

  5. Implications of Multi-Core Architectures on the Development of Multiple Independent Levels of Security (MILS) Compliant Systems

    Science.gov (United States)

    2012-10-01

    40 Figure 16: CBEA spider network...processors, that we cannot be sure that any analysis or checklist is complete. We have found errors, discrepancies and incompleteness in the written...tasks. First, a process was defined to create a checklist for all the components needing evaluation in the multicore architecture. Second, a general

  6. A Programmer-Interpreter Neural Network Architecture for Prefrontal Cognitive Control.

    Science.gov (United States)

    Donnarumma, Francesco; Prevete, Roberto; Chersi, Fabian; Pezzulo, Giovanni

    2015-09-01

    There is wide consensus that the prefrontal cortex (PFC) is able to exert cognitive control on behavior by biasing processing toward task-relevant information and by modulating response selection. This idea is typically framed in terms of top-down influences within a cortical control hierarchy, where prefrontal-basal ganglia loops gate multiple input-output channels, which in turn can activate or sequence motor primitives expressed in (pre-)motor cortices. Here we advance a new hypothesis, based on the notion of programmability and an interpreter-programmer computational scheme, on how the PFC can flexibly bias the selection of sensorimotor patterns depending on internal goal and task contexts. In this approach, multiple elementary behaviors representing motor primitives are expressed by a single multi-purpose neural network, which is seen as a reusable area of "recycled" neurons (interpreter). The PFC thus acts as a "programmer" that, without modifying the network connectivity, feeds the interpreter networks with specific input parameters encoding the programs (corresponding to network structures) to be interpreted by the (pre-)motor areas. Our architecture is validated in a standard test for executive function: the 1-2-AX task. Our results show that this computational framework provides a robust, scalable and flexible scheme that can be iterated at different hierarchical layers, supporting the realization of multiple goals. We discuss the plausibility of the "programmer-interpreter" scheme to explain the functioning of prefrontal-(pre)motor cortical hierarchies.

  7. RoCoMAR: Robots’ Controllable Mobility Aided Routing and Relay Architecture for Mobile Sensor Networks

    Directory of Open Access Journals (Sweden)

    Seokhoon Yoon

    2013-07-01

    Full Text Available In a practical deployment, mobile sensor network (MSN suffers from a low performance due to high node mobility, time-varying wireless channel properties, and obstacles between communicating nodes. In order to tackle the problem of low network performance and provide a desired end-to-end data transfer quality, in this paper we propose a novel ad hoc routing and relaying architecture, namely RoCoMAR (Robots’ Controllable Mobility Aided Routing that uses robotic nodes’ controllable mobility. RoCoMAR repeatedly performs link reinforcement process with the objective of maximizing the network throughput, in which the link with the lowest quality on the path is identified and replaced with high quality links by placing a robotic node as a relay at an optimal position. The robotic node resigns as a relay if the objective is achieved or no more gain can be obtained with a new relay. Once placed as a relay, the robotic node performs adaptive link maintenance by adjusting its position according to the movements of regular nodes. The simulation results show that RoCoMAR outperforms existing ad hoc routing protocols for MSN in terms of network throughput and end-to-end delay.

  8. A Distributed Multiagent System Architecture for Body Area Networks Applied to Healthcare Monitoring

    Directory of Open Access Journals (Sweden)

    Filipe Felisberto

    2015-01-01

    Full Text Available In the last years the area of health monitoring has grown significantly, attracting the attention of both academia and commercial sectors. At the same time, the availability of new biomedical sensors and suitable network protocols has led to the appearance of a new generation of wireless sensor networks, the so-called wireless body area networks. Nowadays, these networks are routinely used for continuous monitoring of vital parameters, movement, and the surrounding environment of people, but the large volume of data generated in different locations represents a major obstacle for the appropriate design, development, and deployment of more elaborated intelligent systems. In this context, we present an open and distributed architecture based on a multiagent system for recognizing human movements, identifying human postures, and detecting harmful activities. The proposed system evolved from a single node for fall detection to a multisensor hardware solution capable of identifying unhampered falls and analyzing the users’ movement. The experiments carried out contemplate two different scenarios and demonstrate the accuracy of our proposal as a real distributed movement monitoring and accident detection system. Moreover, we also characterize its performance, enabling future analyses and comparisons with similar approaches.

  9. Massively parallel network architectures for automatic recognition of visual speech signals. Final technical report

    Energy Technology Data Exchange (ETDEWEB)

    Sejnowski, T.J.; Goldstein, M.

    1990-01-01

    This research sought to produce a massively-parallel network architecture that could interpret speech signals from video recordings of human talkers. This report summarizes the project's results: (1) A corpus of video recordings from two human speakers was analyzed with image processing techniques and used as the data for this study; (2) We demonstrated that a feed forward network could be trained to categorize vowels from these talkers. The performance was comparable to that of the nearest neighbors techniques and to trained humans on the same data; (3) We developed a novel approach to sensory fusion by training a network to transform from facial images to short-time spectral amplitude envelopes. This information can be used to increase the signal-to-noise ratio and hence the performance of acoustic speech recognition systems in noisy environments; (4) We explored the use of recurrent networks to perform the same mapping for continuous speech. Results of this project demonstrate the feasibility of adding a visual speech recognition component to enhance existing speech recognition systems. Such a combined system could be used in noisy environments, such as cockpits, where improved communication is needed. This demonstration of presymbolic fusion of visual and acoustic speech signals is consistent with our current understanding of human speech perception.

  10. Mapping the structural and functional network architecture of the medial temporal lobe using 7T MRI.

    Science.gov (United States)

    Shah, Preya; Bassett, Danielle S; Wisse, Laura E M; Detre, John A; Stein, Joel M; Yushkevich, Paul A; Shinohara, Russell T; Pluta, John B; Valenciano, Elijah; Daffner, Molly; Wolk, David A; Elliott, Mark A; Litt, Brian; Davis, Kathryn A; Das, Sandhitsu R

    2018-02-01

    Medial temporal lobe (MTL) subregions play integral roles in memory function and are differentially affected in various neurological and psychiatric disorders. The ability to structurally and functionally characterize these subregions may be important to understanding MTL physiology and diagnosing diseases involving the MTL. In this study, we characterized network architecture of the MTL in healthy subjects (n = 31) using both resting state functional MRI and MTL-focused T2-weighted structural MRI at 7 tesla. Ten MTL subregions per hemisphere, including hippocampal subfields and cortical regions of the parahippocampal gyrus, were segmented for each subject using a multi-atlas algorithm. Both structural covariance matrices from correlations of subregion volumes across subjects, and functional connectivity matrices from correlations between subregion BOLD time series were generated. We found a moderate structural and strong functional inter-hemispheric symmetry. Several bilateral hippocampal subregions (CA1, dentate gyrus, and subiculum) emerged as functional network hubs. We also observed that the structural and functional networks naturally separated into two modules closely corresponding to (a) bilateral hippocampal formations, and (b) bilateral extra-hippocampal structures. Finally, we found a significant correlation in structural and functional connectivity (r = 0.25). Our findings represent a comprehensive analysis of network topology of the MTL at the subregion level. We share our data, methods, and findings as a reference for imaging methods and disease-based research. © 2017 Wiley Periodicals, Inc.

  11. Reveal, A General Reverse Engineering Algorithm for Inference of Genetic Network Architectures

    Science.gov (United States)

    Liang, Shoudan; Fuhrman, Stefanie; Somogyi, Roland

    1998-01-01

    Given the immanent gene expression mapping covering whole genomes during development, health and disease, we seek computational methods to maximize functional inference from such large data sets. Is it possible, in principle, to completely infer a complex regulatory network architecture from input/output patterns of its variables? We investigated this possibility using binary models of genetic networks. Trajectories, or state transition tables of Boolean nets, resemble time series of gene expression. By systematically analyzing the mutual information between input states and output states, one is able to infer the sets of input elements controlling each element or gene in the network. This process is unequivocal and exact for complete state transition tables. We implemented this REVerse Engineering ALgorithm (REVEAL) in a C program, and found the problem to be tractable within the conditions tested so far. For n = 50 (elements) and k = 3 (inputs per element), the analysis of incomplete state transition tables (100 state transition pairs out of a possible 10(exp 15)) reliably produced the original rule and wiring sets. While this study is limited to synchronous Boolean networks, the algorithm is generalizable to include multi-state models, essentially allowing direct application to realistic biological data sets. The ability to adequately solve the inverse problem may enable in-depth analysis of complex dynamic systems in biology and other fields.

  12. A distributed multiagent system architecture for body area networks applied to healthcare monitoring.

    Science.gov (United States)

    Felisberto, Filipe; Laza, Rosalía; Fdez-Riverola, Florentino; Pereira, António

    2015-01-01

    In the last years the area of health monitoring has grown significantly, attracting the attention of both academia and commercial sectors. At the same time, the availability of new biomedical sensors and suitable network protocols has led to the appearance of a new generation of wireless sensor networks, the so-called wireless body area networks. Nowadays, these networks are routinely used for continuous monitoring of vital parameters, movement, and the surrounding environment of people, but the large volume of data generated in different locations represents a major obstacle for the appropriate design, development, and deployment of more elaborated intelligent systems. In this context, we present an open and distributed architecture based on a multiagent system for recognizing human movements, identifying human postures, and detecting harmful activities. The proposed system evolved from a single node for fall detection to a multisensor hardware solution capable of identifying unhampered falls and analyzing the users' movement. The experiments carried out contemplate two different scenarios and demonstrate the accuracy of our proposal as a real distributed movement monitoring and accident detection system. Moreover, we also characterize its performance, enabling future analyses and comparisons with similar approaches.

  13. Smart Building: Decision Making Architecture for Thermal Energy Management

    OpenAIRE

    Oscar Hernández Uribe; Juan Pablo San Martin; María C. Garcia-Alegre; Matilde Santos; Domingo Guinea

    2015-01-01

    Smart applications of the Internet of Things are improving the performance of buildings, reducing energy demand. Local and smart networks, soft computing methodologies, machine intelligence algorithms and pervasive sensors are some of the basics of energy optimization strategies developed for the benefit of environmental sustainability and user comfort. This work presents a distributed sensor-processor-communication decision-making architecture to improve the acquisition, stora...

  14. Effect of chain rigidity on network architecture and deformation behavior of glassy polymer networks

    Science.gov (United States)

    Knowles, Kyler Reser

    Processing carbon fiber composite laminates creates molecular-level strains in the thermoset matrix upon curing and cooling which can lead to failures such as geometry deformations, micro-cracking, and other issues. It is known strain creation is attributed to the significant volume and physical state changes undergone by the polymer matrix throughout the curing process, though storage and relaxation of cure-induced strains remain poorly understood. This dissertation establishes two approaches to address the issue. The first establishes testing methods to simultaneously measure key volumetric properties of a carbon fiber composite laminate and its polymer matrix. The second approach considers the rigidity of the polymer matrix in regards to strain storage and relaxation mechanisms which ultimately control composite performance throughout manufacturing and use. Through the use of a non-contact, full-field strain measurement technique known as digital image correlation (DIC), we describe and implement useful experiments which quantify matrix and composite parameters necessary for simulation efforts and failure models. The methods are compared to more traditional techniques and show excellent correlation. Further, we established relationships which represent matrix-fiber compatibility in regards to critical processing constraints. The second approach involves a systematic study of epoxy-amine networks which are chemically-similar but differ in chain segment rigidity. Prior research has investigated the isomer effect of glassy polymers, showing sizeable differences in thermal, volumetric, physical, and mechanical properties. This work builds on these themes and shows the apparent isomer effect is rather an effect of chain rigidity. Indeed, it was found that structurally-dissimilar polymer networks exhibit very similar properties as a consequence of their shared average network rigidity. Differences in chain packing, as a consequence of chain rigidity, were shown to

  15. A Neural Network Architecture For Rapid Model Indexing In Computer Vision Systems

    Science.gov (United States)

    Pawlicki, Ted

    1988-03-01

    Models of objects stored in memory have been shown to be useful for guiding the processing of computer vision systems. A major consideration in such systems, however, is how stored models are initially accessed and indexed by the system. As the number of stored models increases, the time required to search memory for the correct model becomes high. Parallel distributed, connectionist, neural networks' have been shown to have appealing content addressable memory properties. This paper discusses an architecture for efficient storage and reference of model memories stored as stable patterns of activity in a parallel, distributed, connectionist, neural network. The emergent properties of content addressability and resistance to noise are exploited to perform indexing of the appropriate object centered model from image centered primitives. The system consists of three network modules each of which represent information relative to a different frame of reference. The model memory network is a large state space vector where fields in the vector correspond to ordered component objects and relative, object based spatial relationships between the component objects. The component assertion network represents evidence about the existence of object primitives in the input image. It establishes local frames of reference for object primitives relative to the image based frame of reference. The spatial relationship constraint network is an intermediate representation which enables the association between the object based and the image based frames of reference. This intermediate level represents information about possible object orderings and establishes relative spatial relationships from the image based information in the component assertion network below. It is also constrained by the lawful object orderings in the model memory network above. The system design is consistent with current psychological theories of recognition by component. It also seems to support Marr's notions

  16. Adaptive reconfigurable distributed sensor architecture

    Science.gov (United States)

    Akey, Mark L.

    1997-07-01

    The infancy of unattended ground based sensors is quickly coming to an end with the arrival of on-board GPS, networking, and multiple sensing capabilities. Unfortunately, their use is only first-order at best: GPS assists with sensor report registration; networks push sensor reports back to the warfighter and forwards control information to the sensors; multispectral sensing is a preset, pre-deployment consideration; and the scalability of large sensor networks is questionable. Current architectures provide little synergy among or within the sensors either before or after deployment, and do not map well to the tactical user's organizational structures and constraints. A new distributed sensor architecture is defined which moves well beyond single sensor, single task architectures. Advantages include: (1) automatic mapping of tactical direction to multiple sensors' tasks; (2) decentralized, distributed management of sensor resources and tasks; (3) software reconfiguration of deployed sensors; (4) network scalability and flexibility to meet the constraints of tactical deployments, and traditional combat organizations and hierarchies; and (5) adaptability to new battlefield communication paradigms such as BADD (Battlefield Analysis and Data Dissemination). The architecture is supported in two areas: a recursive, structural definition of resource configuration and management via loose associations; and a hybridization of intelligent software agents with tele- programming capabilities. The distributed sensor architecture is examined within the context of air-deployed ground sensors with acoustic, communication direction finding, and infra-red capabilities. Advantages and disadvantages of the architecture are examined. Consideration is given to extended sensor life (up to 6 months), post-deployment sensor reconfiguration, limited on- board sensor resources (processor and memory), and bandwidth. It is shown that technical tasking of the sensor suite can be automatically

  17. Distributed Processor/Memory Architectures Design Program

    Science.gov (United States)

    1975-02-01

    3 Pt- Pfkieg. %lnsmul and lldl.rIftu F.7 ill e .. . . . 4. Pt- I.Ascal] And ( Globil " hl~tterti+ Viml .. .. .. . . . . 5. P- 1 0 Il.zertax I nit .. -1...top-Down System Design Process ............... 370 162 Relationship Between the Prxce.s. Its Environment , and Its Response to the Environment ...systems and Air Force tiiandardN for components in these s.stems, suLh present standards as those for environmental and elef’trikal power interlace were

  18. Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

    Science.gov (United States)

    Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

    2013-03-11

    The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

  19. Improved Vehicular Information Network Architecture Using Fuzzy Based Named Data NetworkingNDN

    Directory of Open Access Journals (Sweden)

    Kanwalpreet Kaur

    2015-08-01

    Full Text Available Vehicular Ad-hoc System VANETs is really a component with smart transport systems. It has ability to prevent accidents and the road congestion issues on highways but it suffers from the accomplishment and scalability issues. To handle these difficulties from the Inter Vehicular Communication IVC we apply Name Data Networking NDN. All though in NDN the users are only concerned about necessary data and give no attention on the number of locations from where the data is coming. The NDN layout is usually much more worthy for IVC circumstance getting the ordered material labeling design as well as amp64258exible material retrieval. In this report we propose vehicular network dependent on fuzzy membership function which offers the fundamental NDN style to improve support location dependent forwarding content aggregation and distributed mobility management. This paper finally winds up the several boundaries regarding earlier approaches.

  20. Enabling direct connectivity between heterogeneous objects in the internet of things through a network-service-oriented architecture

    Directory of Open Access Journals (Sweden)

    De Poorter Eli

    2011-01-01

    Full Text Available Abstract In a future internet of things, an increasing number of everyday objects are connected with each other. These objects can be very diverse in terms of the used network protocols and communication technologies, which leads to a wild growth of co-located networking technologies. Unfortunately, current consumer items are not designed to communicate with co-located devices that use different communication technologies. In addition, commercially available internet of things devices, such as sensor nodes, often use vendor-specific propriety network solutions. As a result, communication between these devices is only possible through the use of gateway nodes, resulting in inefficient use of the wireless medium. To remedy this situation, this paper discusses which features are required to integrate such a diverse number of heterogeneous objects into a single internet of things. In addition, the paper introduces the IDRA architecture, which is designed specifically to enable connectivity between heterogeneous resource-constrained objects. The IDRA architecture has the following advantages. (1 IDRA can connect co-located objects directly, without the need for complex translation gateways. (2 The architecture is clean slate, but supports backward compatibility with existing deployments. (3 Due to its low memory footprint, the architecture can be used in resource-constrained objects. Finally, the paper evaluates the performance of the IDRA architecture and discusses the feasibility of introducing IDRA in existing networks.

  1. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  2. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  3. Graphics Processor Units (GPUs)

    Science.gov (United States)

    Wyrwas, Edward J.

    2017-01-01

    This presentation will include information about Graphics Processor Units (GPUs) technology, NASA Electronic Parts and Packaging (NEPP) tasks, The test setup, test parameter considerations, lessons learned, collaborations, a roadmap, NEPP partners, results to date, and future plans.

  4. Determination of Algorithm Parallelism in NP Complete Problems for Distributed Architectures

    Science.gov (United States)

    1990-03-05

    exchange, the two-dimensional mesh, and the cube as shown in Figure 2.5 (25:23). Each Bus Architecture Shuffle Exchange Network -8 node Q nef[work MMRE CPU ... CPU ... CPU MEMRIE option W2 - 2 switch m m memories CPU I Two Dimensional Mesh Topology Cube Network Node is complete computer including memory. I...an 80386 microcomputer, an 80387 numeric coprocessor, an optional SX scalar processor module based on the Weitek 1167 floating-point unit, an

  5. Architecture of the human interactome defines protein communities and disease networks.

    Science.gov (United States)

    Huttlin, Edward L; Bruckner, Raphael J; Paulo, Joao A; Cannon, Joe R; Ting, Lily; Baltier, Kurt; Colby, Greg; Gebreab, Fana; Gygi, Melanie P; Parzen, Hannah; Szpyt, John; Tam, Stanley; Zarraga, Gabriela; Pontano-Vaites, Laura; Swarup, Sharan; White, Anne E; Schweppe, Devin K; Rad, Ramin; Erickson, Brian K; Obar, Robert A; Guruharsha, K G; Li, Kejie; Artavanis-Tsakonas, Spyros; Gygi, Steven P; Harper, J Wade

    2017-05-25

    The physiology of a cell can be viewed as the product of thousands of proteins acting in concert to shape the cellular response. Coordination is achieved in part through networks of protein-protein interactions that assemble functionally related proteins into complexes, organelles, and signal transduction pathways. Understanding the architecture of the human proteome has the potential to inform cellular, structural, and evolutionary mechanisms and is critical to elucidating how genome variation contributes to disease. Here we present BioPlex 2.0 (Biophysical Interactions of ORFeome-derived complexes), which uses robust affinity purification-mass spectrometry methodology to elucidate protein interaction networks and co-complexes nucleated by more than 25% of protein-coding genes from the human genome, and constitutes, to our knowledge, the largest such network so far. With more than 56,000 candidate interactions, BioPlex 2.0 contains more than 29,000 previously unknown co-associations and provides functional insights into hundreds of poorly characterized proteins while enhancing network-based analyses of domain associations, subcellular localization, and co-complex formation. Unsupervised Markov clustering of interacting proteins identified more than 1,300 protein communities representing diverse cellular activities. Genes essential for cell fitness are enriched within 53 communities representing central cellular functions. Moreover, we identified 442 communities associated with more than 2,000 disease annotations, placing numerous candidate disease genes into a cellular framework. BioPlex 2.0 exceeds previous experimentally derived interaction networks in depth and breadth, and will be a valuable resource for exploring the biology of incompletely characterized proteins and for elucidating larger-scale patterns of proteome organization.

  6. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  7. eQTL Networks Reveal Complex Genetic Architecture in the Immature Soybean Seed

    Directory of Open Access Journals (Sweden)

    Yung-Tsi Bolon

    2014-03-01

    Full Text Available The complex network of regulatory factors and interactions involved in transcriptional regulation within the seed is not well understood. To evaluate gene expression regulation in the immature seed, we utilized a genetical genomics approach on a soybean [ (L. Merr.] recombinant inbred line (RIL population and produced a genome-wide expression quantitative trait loci (eQTL dataset. The validity of the dataset was confirmed by mapping the eQTL hotspot for flavonoid biosynthesis-related genes to a region containing repeats of chalcone synthase (CHS genes known to correspond to the soybean inhibitor locus that regulates seed color. We then identified eQTL for genes with seed-specific expression and discovered striking eQTL hotspots at distinct genomic intervals on chromosomes (Chr 20, 7, and 13. The main eQTL hotspot for transcriptional regulation of fatty acid biosynthesis genes also coincided with regulation of oleosin genes. Transcriptional upregulation of genesets from eQTL with opposite allelic effects were also found. Gene–eQTL networks were constructed and candidate regulatory genes were identified from these three key loci specific to seed expression and enriched in genes involved in seed oil accumulation. Our data provides new insight into the complex nature of gene networks in the immature soybean seed and the genetic architecture that contributes to seed development.

  8. Semi-Interpenetrating Polymer Networks with Predefined Architecture for Metal Ion Fluorescence Monitoring

    Directory of Open Access Journals (Sweden)

    Kyriakos Christodoulou

    2016-11-01

    Full Text Available The development of new synthetic approaches for the preparation of efficient 3D luminescent chemosensors for transition metal ions receives considerable attention nowadays, owing to the key role of the latter as elements in biological systems and their harmful environmental effects when present in aquatic media. In this work, we describe an easy and versatile synthetic methodology that leads to the generation of nonconjugated 3D luminescent semi-interpenetrating amphiphilic networks (semi-IPN with structure-defined characteristics. More precisely, the synthesis involves the encapsulation of well-defined poly(9-anthrylmethyl methacrylate (pAnMMA (hydrophobic, luminescent linear polymer chains within a covalent poly(2-(dimethylaminoethyl methacrylate (pDMAEMA hydrophilic polymer network, derived via the 1,2-bis-(2-iodoethoxyethane (BIEE-induced crosslinking process of well-defined pDMAEMA linear chains. Characterization of their fluorescence properties demonstrated that these materials act as strong blue emitters when exposed to UV irradiation. This, combined with the presence of the metal-binding tertiary amino functionalities of the pDMAEMA segments, allowed for their applicability as sorbents and fluorescence chemosensors for transition metal ions (Fe3+, Cu2+ in solution via a chelation-enhanced fluorescence-quenching effect promoted within the semi-IPN network architecture. Ethylenediaminetetraacetic acid (EDTA-induced metal ion desorption and thus material recyclability has been also demonstrated.

  9. REAL-TIME VIDEO SCALING BASED ON CONVOLUTION NEURAL NETWORK ARCHITECTURE

    Directory of Open Access Journals (Sweden)

    S Safinaz

    2017-08-01

    Full Text Available In recent years, video super resolution techniques becomes mandatory requirements to get high resolution videos. Many super resolution techniques researched but still video super resolution or scaling is a vital challenge. In this paper, we have presented a real-time video scaling based on convolution neural network architecture to eliminate the blurriness in the images and video frames and to provide better reconstruction quality while scaling of large datasets from lower resolution frames to high resolution frames. We compare our outcomes with multiple exiting algorithms. Our extensive results of proposed technique RemCNN (Reconstruction error minimization Convolution Neural Network shows that our model outperforms the existing technologies such as bicubic, bilinear, MCResNet and provide better reconstructed motioning images and video frames. The experimental results shows that our average PSNR result is 47.80474 considering upscale-2, 41.70209 for upscale-3 and 36.24503 for upscale-4 for Myanmar dataset which is very high in contrast to other existing techniques. This results proves our proposed model real-time video scaling based on convolution neural network architecture’s high efficiency and better performance.

  10. Heterogeneous radio-over-fiber passive access network architecture to mitigate Rayleigh backscattering interferometric beat noise.

    Science.gov (United States)

    Yeh, C H; Chow, C W

    2011-03-28

    We propose and experimentally demonstrate a hybrid radio-over-fiber (ROF) wavelength division multiplexed and time division multiplexed passive optical network (WDM-TDM PON) architecture to mitigate Rayleigh backscattering (RB) interferometric beat noises. Here, only a single wavelength is needed at the central office (CO) to generate the downstream baseband data for optical wired application and optical millimeter-wave (mm-wave) signal for wireless application. The upstream signal is produced by remodulating the downstream signal. No optical filter is required at the optical network unit/remote antenna unit (ONU/RAU) to separate the optical wired and optical mm-wave signals. In the proposed network, 10 Gb/s differential phase shift keying (DPSK) signal is used for the downstream optical wired application and 2.5 Gb/s on-off keying (OOK) signal on 20 GHz carrier is used for the optical mm-wave signal. In each ONU, a reflective optical semiconductor amplifier (RSOA) is used to remodulate and produce a 2.5 Gb/s OOK format for upstream traffic. As the back-refection produced by the downstream DPSK signal and the upstream OOK signal is traveling in different fiber path, RB noise at the CO can be completely mitigated.

  11. The probabilistic neural network architecture for high speed classification of remotely sensed imagery

    Science.gov (United States)

    Chettri, Samir R.; Cromp, Robert F.

    1993-01-01

    In this paper we discuss a neural network architecture (the Probabilistic Neural Net or the PNN) that, to the best of our knowledge, has not previously been applied to remotely sensed data. The PNN is a supervised non-parametric classification algorithm as opposed to the Gaussian maximum likelihood classifier (GMLC). The PNN works by fitting a Gaussian kernel to each training point. The width of the Gaussian is controlled by a tuning parameter called the window width. If very small widths are used, the method is equivalent to the nearest neighbor method. For large windows, the PNN behaves like the GMLC. The basic implementation of the PNN requires no training time at all. In this respect it is far better than the commonly used backpropagation neural network which can be shown to take O(N6) time for training where N is the dimensionality of the input vector. In addition the PNN can be implemented in a feed forward mode in hardware. The disadvantage of the PNN is that it requires all the training data to be stored. Some solutions to this problem are discussed in the paper. Finally, we discuss the accuracy of the PNN with respect to the GMLC and the backpropagation neural network (BPNN). The PNN is shown to be better than GMLC and not as good as the BPNN with regards to classification accuracy.

  12. QoS Management and Control for an All-IP WiMAX Network Architecture: Design, Implementation and Evaluation

    Directory of Open Access Journals (Sweden)

    Thomas Michael Bohnert

    2008-01-01

    Full Text Available The IEEE 802.16 standard provides a specification for a fixed and mobile broadband wireless access system, offering high data rate transmission of multimedia services with different Quality-of-Service (QoS requirements through the air interface. The WiMAX Forum, going beyond the air interface, defined an end-to-end WiMAX network architecture, based on an all-IP platform in order to complete the standards required for a commercial rollout of WiMAX as broadband wireless access solution. As the WiMAX network architecture is only a functional specification, this paper focuses on an innovative solution for an end-to-end WiMAX network architecture offering in compliance with the WiMAX Forum specification. To our best knowledge, this is the first WiMAX architecture built by a research consortium globally and was performed within the framework of the European IST project WEIRD (WiMAX Extension to Isolated Research Data networks. One of the principal features of our architecture is support for end-to-end QoS achieved by the integration of resource control in the WiMAX wireless link and the resource management in the wired domains in the network core. In this paper we present the architectural design of these QoS features in the overall WiMAX all-IP framework and their functional as well as performance evaluation. The presented results can safely be considered as unique and timely for any WiMAX system integrator.

  13. Development of an ease-of-use remote healthcare system architecture using RFID and networking technologies.

    Science.gov (United States)

    Lin, Shih-Sung; Hung, Min-Hsiung; Tsai, Chang-Lung; Chou, Li-Ping

    2012-12-01

    The study aims to provide an ease-of-use approach for senior patients to utilize remote healthcare systems. An ease-of-use remote healthcare system (RHS) architecture using RFID (Radio Frequency Identification) and networking technologies is developed. Specifically, the codes in RFID tags are used for authenticating the patients' ID to secure and ease the login process. The patient needs only to take one action, i.e. placing a RFID tag onto the reader, to automatically login and start the RHS and then acquire automatic medical services. An ease-of-use emergency monitoring and reporting mechanism is developed as well to monitor and protect the safety of the senior patients who have to be left alone at home. By just pressing a single button, the RHS can automatically report the patient's emergency information to the clinic side so that the responsible medical personnel can take proper urgent actions for the patient. Besides, Web services technology is used to build the Internet communication scheme of the RHS so that the interoperability and data transmission security between the home server and the clinical server can be enhanced. A prototype RHS is constructed to validate the effectiveness of our designs. Testing results show that the proposed RHS architecture possesses the characteristics of ease to use, simplicity to operate, promptness in login, and no need to preserve identity information. The proposed RHS architecture can effectively increase the willingness of senior patients who act slowly or are unfamiliar with computer operations to use the RHS. The research results can be used as an add-on for developing future remote healthcare systems.

  14. Deep learning architecture for iris recognition based on optimal Gabor filters and deep belief network

    Science.gov (United States)

    He, Fei; Han, Ye; Wang, Han; Ji, Jinchao; Liu, Yuanning; Ma, Zhiqiang

    2017-03-01

    Gabor filters are widely utilized to detect iris texture information in several state-of-the-art iris recognition systems. However, the proper Gabor kernels and the generative pattern of iris Gabor features need to be predetermined in application. The traditional empirical Gabor filters and shallow iris encoding ways are incapable of dealing with such complex variations in iris imaging including illumination, aging, deformation, and device variations. Thereby, an adaptive Gabor filter selection strategy and deep learning architecture are presented. We first employ particle swarm optimization approach and its binary version to define a set of data-driven Gabor kernels for fitting the most informative filtering bands, and then capture complex pattern from the optimal Gabor filtered coefficients by a trained deep belief network. A succession of comparative experiments validate that our optimal Gabor filters may produce more distinctive Gabor coefficients and our iris deep representations be more robust and stable than traditional iris Gabor codes. Furthermore, the depth and scales of the deep learning architecture are also discussed.

  15. Historical building monitoring using an energy-efficient scalable wireless sensor network architecture.

    Science.gov (United States)

    Capella, Juan V; Perles, Angel; Bonastre, Alberto; Serrano, Juan J

    2011-01-01

    We present a set of novel low power wireless sensor nodes designed for monitoring wooden masterpieces and historical buildings, in order to perform an early detection of pests. Although our previous star-based system configuration has been in operation for more than 13 years, it does not scale well for sensorization of large buildings or when deploying hundreds of nodes. In this paper we demonstrate the feasibility of a cluster-based dynamic-tree hierarchical Wireless Sensor Network (WSN) architecture where realistic assumptions of radio frequency data transmission are applied to cluster construction, and a mix of heterogeneous nodes are used to minimize economic cost of the whole system and maximize power saving of the leaf nodes. Simulation results show that the specialization of a fraction of the nodes by providing better antennas and some energy harvesting techniques can dramatically extend the life of the entire WSN and reduce the cost of the whole system. A demonstration of the proposed architecture with a new routing protocol and applied to termite pest detection has been implemented on a set of new nodes and should last for about 10 years, but it provides better scalability, reliability and deployment properties.

  16. An Improved PMSM Drive Architecture Based on BFO and Neural Network

    Directory of Open Access Journals (Sweden)

    Flah Aymen

    2013-04-01

    Full Text Available In this paper, an improved robust vector control strategy is designed to drive the Permanent magnet synchronous motor in a wide speed range mode. The designed control method guarantees the precision and robustness of speed regulation performance by using recurrent neural network architecture. The stator current controller parameter tuning problems, which characterize this control strategy, are resolved using a bacterial foraging optimization algorithm to find the optimal parameters of the current controllers used. A field weakening control algorithm generates an adaptive magnetizing current command to achieve the desired high speed mode. The robustness and effectiveness of the global control scheme are verified through computer simulations established under a Matlab-Simulink environment.

  17. Monitoring Architectural Heritage by Wireless Sensors Networks: San Gimignano — A Case Study

    Directory of Open Access Journals (Sweden)

    Alessandro Mecocci

    2014-01-01

    Full Text Available This paper describes a wireless sensor network (WSN used to monitor the health state of architectural heritage in real-time. The WSN has been deployed and tested on the “Rognosa” tower in the medieval village of San Gimignano, Tuscany, Italy. This technology, being non-invasive, mimetic, and long lasting, is particularly well suited for long term monitoring and on-line diagnosis of the conservation state of heritage buildings. The proposed monitoring system comprises radio-equipped nodes linked to suitable sensors capable of monitoring crucial parameters like: temperature, humidity, masonry cracks, pouring rain, and visual light. The access to data is granted by a user interface for remote control. The WSN can autonomously send remote alarms when predefined thresholds are reached.

  18. Monitoring Architectural Heritage by Wireless Sensors Networks: San Gimignano — A Case Study

    Science.gov (United States)

    Mecocci, Alessandro; Abrardo, Andrea

    2014-01-01

    This paper describes a wireless sensor network (WSN) used to monitor the health state of architectural heritage in real-time. The WSN has been deployed and tested on the “Rognosa” tower in the medieval village of San Gimignano, Tuscany, Italy. This technology, being non-invasive, mimetic, and long lasting, is particularly well suited for long term monitoring and on-line diagnosis of the conservation state of heritage buildings. The proposed monitoring system comprises radio-equipped nodes linked to suitable sensors capable of monitoring crucial parameters like: temperature, humidity, masonry cracks, pouring rain, and visual light. The access to data is granted by a user interface for remote control. The WSN can autonomously send remote alarms when predefined thresholds are reached. PMID:24394600

  19. Data Optical Networking Architecture Using Wavelength-Division Multiplexing Method for Optical Sensors

    Science.gov (United States)

    Nguyen, Hung D.

    2008-01-01

    Recently there has been a growth in the number of fiber optical sensors used for health monitoring in the hostile environment of commercial aircraft. Health monitoring to detect the onset of failure in structural systems from such causes as corrosion, stress corrosion cracking, and fatigue is a critical factor in safety as well in aircraft maintenance costs. This report presents an assessment of an analysis model of optical data networking architectures used for monitoring data signals among these optical sensors. Our model is focused on the design concept of the wavelength-division multiplexing (WDM) method since most of the optical sensors deployed in the aircraft for health monitoring typically operate in a wide spectrum of optical wavelengths from 710 to 1550 nm.

  20. Monitoring architectural heritage by wireless sensors networks: San Gimignano--a case study.

    Science.gov (United States)

    Mecocci, Alessandro; Abrardo, Andrea

    2014-01-03

    This paper describes a wireless sensor network (WSN) used to monitor the health state of architectural heritage in real-time. The WSN has been deployed and tested on the "Rognosa" tower in the medieval village of San Gimignano, Tuscany, Italy. This technology, being non-invasive, mimetic, and long lasting, is particularly well suited for long term monitoring and on-line diagnosis of the conservation state of heritage buildings. The proposed monitoring system comprises radio-equipped nodes linked to suitable sensors capable of monitoring crucial parameters like: temperature, humidity, masonry cracks, pouring rain, and visual light. The access to data is granted by a user interface for remote control. The WSN can autonomously send remote alarms when predefined thresholds are reached.