WorldWideScience

Sample records for network hardware options

  1. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  2. Artificial Neural Network with Hardware Training and Hardware Refresh

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2003-01-01

    A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently. The validation network has a separate transfer function circuits each being coupled to the charge storage circuits so as to replicate the training network s coupling of the plurality of charge storage to the plurality of transfer function circuits. The plurality of transfer function circuits may be constructed each having a transconductance amplifier providing differential currents combined to provide an output in accordance with a transfer function. The derivative circuits may have a circuit constructed to generate a biased differential currents combined so as to provide the derivative of the transfer function.

  3. Basket Option Pricing Using GP-GPU Hardware Acceleration

    KAUST Repository

    Douglas, Craig C.

    2010-08-01

    We introduce a basket option pricing problem arisen in financial mathematics. We discretized the problem based on the alternating direction implicit (ADI) method and parallel cyclic reduction is applied to solve the set of tridiagonal matrices generated by the ADI method. To reduce the computational time of the problem, a general purpose graphics processing units (GP-GPU) environment is considered. Numerical results confirm the convergence and efficiency of the proposed method. © 2010 IEEE.

  4. Routing Aware Switch Hardware Customization for Networks on Chips

    OpenAIRE

    Meloni, Paolo; Murali, Srinivasan; Carta, Salvatore; Camplani, Massimo; Raffo, Luigi; Micheli, Giovanni,

    2006-01-01

    Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC with low hardware overhead, matching the application requirements are essential. In this work, we present a method for reducing the hardware complexity of the NoC by automatically configuring the architecture of the NoC switches to suit the app...

  5. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Lucani Rötter, Daniel Enrique; Barros, joao

    2014-01-01

    The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware...... specifications of common sensors reveals, however, that other equally important culprits exist, such as the reception and processing energy. Hence, there is a need for a more complete hardware abstraction of a sensor node to reduce effectively the total energy consumption of the network by designing energy......-efficient protocols that use such an abstraction, as well as mechanisms to optimize a communication protocol in terms of energy consumption. The problem is modeled for different feedback-based techniques, where sensors are connected to a base station, either directly or through relays. We show that for four example...

  6. Hardware demonstration of high-speed networks for satellite applications.

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  7. HARDWARE IMPLEMENTATION OF SECURE AODV FOR WIRELESS SENSOR NETWORKS

    Directory of Open Access Journals (Sweden)

    S. Sharmila

    2010-12-01

    Full Text Available Wireless Sensor Networks are extremely vulnerable to any kind of routing attacks due to several factors such as wireless transmission and resource-constrained nodes. In this respect, securing the packets is of great importance when designing the infrastructure and protocols of sensor networks. This paper describes the hardware architecture of secure routing for wireless sensor networks. The routing path is selected using Ad-hoc on demand distance vector routing protocol (AODV. The data packets are converted into digest using hash functions. The functionality of the proposed method is modeled using Verilog HDL in MODELSIM simulator and the performance is compared with various target devices. The results show that the data packets are secured and defend against the routing attacks with minimum energy consumption.

  8. Computer, Network, Software, and Hardware Engineering with Applications

    CERN Document Server

    Schneidewind, Norman F

    2012-01-01

    There are many books on computers, networks, and software engineering but none that integrate the three with applications. Integration is important because, increasingly, software dominates the performance, reliability, maintainability, and availability of complex computer and systems. Books on software engineering typically portray software as if it exists in a vacuum with no relationship to the wider system. This is wrong because a system is more than software. It is comprised of people, organizations, processes, hardware, and software. All of these components must be considered in an integr

  9. Space station common module network topology and hardware development

    Science.gov (United States)

    Anderson, P.; Braunagel, L.; Chwirka, S.; Fishman, M.; Freeman, K.; Eason, D.; Landis, D.; Lech, L.; Martin, J.; Mccorkle, J.

    1990-01-01

    Conceptual space station common module power management and distribution (SSM/PMAD) network layouts and detailed network evaluations were developed. Individual pieces of hardware to be developed for the SSM/PMAD test bed were identified. A technology assessment was developed to identify pieces of equipment requiring development effort. Equipment lists were developed from the previously selected network schematics. Additionally, functional requirements for the network equipment as well as other requirements which affected the suitability of specific items for use on the Space Station Program were identified. Assembly requirements were derived based on the SSM/PMAD developed requirements and on the selected SSM/PMAD network concepts. Basic requirements and simplified design block diagrams are included. DC remote power controllers were successfully integrated into the DC Marshall Space Flight Center breadboard. Two DC remote power controller (RPC) boards experienced mechanical failure of UES 706 stud-mounted diodes during mechanical installation of the boards into the system. These broken diodes caused input to output shorting of the RPC's. The UES 706 diodes were replaced on these RPC's which eliminated the problem. The DC RPC's as existing in the present breadboard configuration do not provide ground fault protection because the RPC was designed to only switch the hot side current. If ground fault protection were to be implemented, it would be necessary to design the system so the RPC switched both the hot and the return sides of power.

  10. SPANNER: A Self-Repairing Spiking Neural Network Hardware Architecture.

    Science.gov (United States)

    Liu, Junxiu; Harkin, Jim; Maguire, Liam P; McDaid, Liam J; Wade, John J

    2017-03-06

    Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel hardware architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing architecture is significantly damaged at a fault density of 80%.

  11. Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors...... in the platform. Our design takes a different approach and connects the hardware accelerators to the network-on-chip in the same way as processor cores. Each processor that uses a hardware accelerator is assigned a virtual channel for sending instructions to the hardware accelerator and a virtual channel...

  12. Network Architecture, Security Issues, and Hardware Implementation of a Home Area Network for Smart Grid

    OpenAIRE

    Saponara, Sergio; Bacchillone, Tony

    2012-01-01

    This paper discusses aims, architecture, and security issues of Smart Grid, taking care of the lesson learned at University of Pisa in research projects on smart energy and grid. A key element of Smart Grid is the energy home area network (HAN), for which an implementation is proposed, dealing with its security aspects and showing some solutions for realizing a wireless network based on ZigBee. Possible hardware-software architectures and implementations using COTS (Commercial Off The Shelf) ...

  13. Wireless multimedia sensor networks on reconfigurable hardware information reduction techniques

    CERN Document Server

    Ang, Li-minn; Chew, Li Wern; Yeong, Lee Seng; Chia, Wai Chong

    2013-01-01

    Traditional wireless sensor networks (WSNs) capture scalar data such as temperature, vibration, pressure, or humidity. Motivated by the success of WSNs and also with the emergence of new technology in the form of low-cost image sensors, researchers have proposed combining image and audio sensors with WSNs to form wireless multimedia sensor networks (WMSNs).

  14. Network Architecture, Security Issues, and Hardware Implementation of a Home Area Network for Smart Grid

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2012-01-01

    Full Text Available This paper discusses aims, architecture, and security issues of Smart Grid, taking care of the lesson learned at University of Pisa in research projects on smart energy and grid. A key element of Smart Grid is the energy home area network (HAN, for which an implementation is proposed, dealing with its security aspects and showing some solutions for realizing a wireless network based on ZigBee. Possible hardware-software architectures and implementations using COTS (Commercial Off The Shelf components are presented for key building blocks of the energy HAN such as smart power meters and plugs and a home smart information box providing energy management policy and supporting user's energy awareness.

  15. Open hardware: a role to play in wireless sensor networks?

    Science.gov (United States)

    Fisher, Roy; Ledwaba, Lehlogonolo; Hancke, Gerhard; Kruger, Carel

    2015-03-20

    The concept of the Internet of Things is rapidly becoming a reality, with many applications being deployed within industrial and consumer sectors. At the 'thing' level-devices and inter-device network communication-the core technical building blocks are generally the same as those found in wireless sensor network implementations. For the Internet of Things to continue growing, we need more plentiful resources for building intelligent devices and sensor networks. Unfortunately, current commercial devices, e.g., sensor nodes and network gateways, tend to be expensive and proprietary, which presents a barrier to entry and arguably slows down further development. There are, however, an increasing number of open embedded platforms available and also a wide selection of off-the-shelf components that can quickly and easily be built into device and network gateway solutions. The question is whether these solutions measure up to built-for-purpose devices. In the paper, we provide a comparison of existing built-for-purpose devices against open source devices. For comparison, we have also designed and rapidly prototyped a sensor node based on off-the-shelf components. We show that these devices compare favorably to built-for-purpose devices in terms of performance, power and cost. Using open platforms and off-the-shelf components would allow more developers to build intelligent devices and sensor networks, which could result in a better overall development ecosystem, lower barriers to entry and rapid growth in the number of IoT applications.

  16. A technique for choosing an option for SDH network upgrade

    Directory of Open Access Journals (Sweden)

    V. A. Bulanov

    2014-01-01

    Full Text Available Rapidly developing data transmission technologies result in making the network equipment modernization inevitable. There are various options to upgrade the SDH networks, for example, by increasing the capacity of network overloaded sites, the entire network capacity by replacement of the equipment or by creation of a parallel network, by changing the network structure with the organization of multilevel hierarchy of a network, etc. All options vary in a diversity of parameters starting with the solution cost and ending with the labor intensiveness of their realization. Thus, there are no certain standard approaches to the rules to choose an option for the network development. The article offers the technique for choosing the SHD network upgrade based on method of expert evaluations using as a tool the software complex that allows us to have quickly the quantitative characteristics of proposed network option. The technique is as follows:1. Forming a perspective matrix of services inclination to the SDH networks.2. Developing the several possible options for a network modernization.3. Formation of the list of criteria and a definition of indicators to characterize them by two groups, namely costs of the option implementation and arising losses; positive effect from the option introduction.4. Criteria weight coefficients purpose.5. Indicators value assessment within each criterion for each option by each expert. Rationing of the obtained values of indicators in relation to the maximum value of an indicator among all options.6. Calculating the integrated indicators of for each option by criteria groups.7. Creating a set of Pareto by drawing two criteria groups of points, which correspond to all options in the system of coordinates on the plane. Option choice.In implementation of point 2 the indicators derivation owing to software complex plays a key role. This complex should produce a structure of the network equipment, types of multiplexer sections

  17. Open Hardware: A Role to Play in Wireless Sensor Networks?

    Directory of Open Access Journals (Sweden)

    Roy Fisher

    2015-03-01

    Full Text Available The concept of the Internet of Things is rapidly becoming a reality, with many applications being deployed within industrial and consumer sectors. At the ‘thing’ level—devices and inter-device network communication—the core technical building blocks are generally the same as those found in wireless sensor network implementations. For the Internet of Things to continue growing, we need more plentiful resources for building intelligent devices and sensor networks. Unfortunately, current commercial devices, e.g., sensor nodes and network gateways, tend to be expensive and proprietary, which presents a barrier to entry and arguably slows down further development. There are, however, an increasing number of open embedded platforms available and also a wide selection of off-the-shelf components that can quickly and easily be built into device and network gateway solutions. The question is whether these solutions measure up to built-for-purpose devices. In the paper, we provide a comparison of existing built-for-purpose devices against open source devices. For comparison, we have also designed and rapidly prototyped a sensor node based on off-the-shelf components. We show that these devices compare favorably to built-for-purpose devices in terms of performance, power and cost. Using open platforms and off-the-shelf components would allow more developers to build intelligent devices and sensor networks, which could result in a better overall development ecosystem, lower barriers to entry and rapid growth in the number of IoT applications.

  18. Open hardware: a role to play in wireless sensor networks?

    CSIR Research Space (South Africa)

    Fisher, R

    2015-03-01

    Full Text Available The concept of the Internet of Things is rapidly becoming a reality, with many applications being deployed within industrial and consumer sectors. At the ‘thing’ level—devices and inter-device network communication—the core technical building blocks...

  19. Effect of Heterogeneity on Decorrelation Mechanisms in Spiking Neural Networks: A Neuromorphic-Hardware Study

    Directory of Open Access Journals (Sweden)

    Thomas Pfeil

    2016-05-01

    Full Text Available High-level brain function, such as memory, classification, or reasoning, can be realized by means of recurrent networks of simplified model neurons. Analog neuromorphic hardware constitutes a fast and energy-efficient substrate for the implementation of such neural computing architectures in technical applications and neuroscientific research. The functional performance of neural networks is often critically dependent on the level of correlations in the neural activity. In finite networks, correlations are typically inevitable due to shared presynaptic input. Recent theoretical studies have shown that inhibitory feedback, abundant in biological neural networks, can actively suppress these shared-input correlations and thereby enable neurons to fire nearly independently. For networks of spiking neurons, the decorrelating effect of inhibitory feedback has so far been explicitly demonstrated only for homogeneous networks of neurons with linear subthreshold dynamics. Theory, however, suggests that the effect is a general phenomenon, present in any system with sufficient inhibitory feedback, irrespective of the details of the network structure or the neuronal and synaptic properties. Here, we investigate the effect of network heterogeneity on correlations in sparse, random networks of inhibitory neurons with nonlinear, conductance-based synapses. Emulations of these networks on the analog neuromorphic-hardware system Spikey allow us to test the efficiency of decorrelation by inhibitory feedback in the presence of hardware-specific heterogeneities. The configurability of the hardware substrate enables us to modulate the extent of heterogeneity in a systematic manner. We selectively study the effects of shared input and recurrent connections on correlations in membrane potentials and spike trains. Our results confirm that shared-input correlations are actively suppressed by inhibitory feedback also in highly heterogeneous networks exhibiting broad

  20. UPGRADE FOR HARDWARE/SOFTWARE SERVER AND NETWORK TOPOLOGY IN INFORMATION SYSTEMS

    Directory of Open Access Journals (Sweden)

    Oleksii O. Kaplun

    2011-02-01

    Full Text Available The network modernization, educational information systems software and hardware updates problem is actual in modern term of information technologies prompt development. There are server applications and network topology of Institute of Information Technology and Learning Tools of National Academy of Pedagogical Sciences of Ukraine analysis and their improvement methods expound in the article. The article materials represent modernization results implemented to increase network efficiency and reliability, decrease response time in Institute’s network information systems. The article gives diagrams of network topology before upgrading and after finish of optimization and upgrading processes.

  1. Hardware Neural Networks Modeling for Computing Different Performance Parameters of Rectangular, Circular, and Triangular Microstrip Antennas

    Directory of Open Access Journals (Sweden)

    Taimoor Khan

    2014-01-01

    Full Text Available In the last one decade, neural networks-based modeling has been used for computing different performance parameters of microstrip antennas because of learning and generalization features. Most of the created neural models are based on software simulation. As the neural networks show massive parallelism inherently, a parallel hardware needs to be created for creating faster computing machine by taking the advantages of the parallelism of the neural networks. This paper demonstrates a generalized neural networks model created on field programmable gate array- (FPGA- based reconfigurable hardware platform for computing different performance parameters of microstrip antennas. Thus, the proposed approach provides a platform for developing low-cost neural network-based FPGA simulators for microwave applications. Also, the results obtained by this approach are in very good agreement with the measured results available in the literature.

  2. Wireless Plug and Play Control Systems: Hardware, Networks, and Protocols

    DEFF Research Database (Denmark)

    Meybodi, Soroush Afkhami

    2012-01-01

    D project are presented in two distinct areas which are: 1) Signal propagation in underground and confined areas, and 2) Access and Networking protocols that accommodate the required flexibility, scalability, and quality of services for plug and play control systems. The first category finds application...... the damp soil medium. To overcome the challenge, all potentially useful signal propagation methods are surveyed either by reviewing the open literature, or by doing simulations, or even running experiments. At the end, Magnetic Induction (MI) is chosen as the winning candidate. New findings are achieved...... in antenna design of magneto-inductive communication systems. They are verified by simulations and experiments. It is shown, via simulations, that MI is a reliable signal propagation technique for the full-scale case study: Distributed Control of the New Generation of District Heating Systems...

  3. Hardware-and-software-based collective communication on the Quadrics network.

    Energy Technology Data Exchange (ETDEWEB)

    Petrini, F. (Fabrizio); Coll, S. (Salvador); Frachtemberg, E. (Eitan); Hoisie, A. (Adolfy)

    2001-01-01

    The efficient implementation of collective communication patterns in a parallel machine is a challenging design effort, that requires the solution of many problems. In this paper we present an in-depth description of how the Quadrics network supports both hardware- and software-based collectives. We describe the main features of the two building blocks of this network, a network interface that can perform zero-copy user-level communication and a wormhole switch. We also focus our attention on the routing and $ow control algorithms, deadlock avoidance and on how the processing nodes are integrated in a global, virtual shared memory. Experimental results conducted on 64-node AlphaServer cluster indicate that the time to complete the hardware-based barrier synchronization on the whole network is as low as 6 ps, with veiy good scalability. Good latency and scalability are also achieved with the software-based synchronization, which takes about 15 ps. With the broadcast, similar performance is achieved by the hardware- and software-based implementations, which can deliver messages of up to 256 b,ytes in 13 ps and can get a sustained bandwidth of 288 Mbyteshec on all the nodes, with wressages larger than 64KB. The hardware-based barrier is almost insensitive to the network congestion, with 93% of the synchronizations taking less than 20 ps. On the other hand, the software based implementation suflers from a signif cant performance degradation. In high load environments the hardware broadcast maintains a reasonably good performance, delivering messages up to 2KB in 200 ps, while the software broadcast suffers from slightly higher latencies inherited by the synchronization mechanism.

  4. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    Science.gov (United States)

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

  5. Event management for large scale event-driven digital hardware spiking neural networks.

    Science.gov (United States)

    Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

    2013-09-01

    The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

  6. DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

    Science.gov (United States)

    Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

    2017-07-18

    Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

  7. PAX: A mixed hardware/software simulation platform for spiking neural networks.

    Science.gov (United States)

    Renaud, S; Tomas, J; Lewis, N; Bornat, Y; Daouzli, A; Rudolph, M; Destexhe, A; Saïghi, S

    2010-09-01

    Many hardware-based solutions now exist for the simulation of bio-like neural networks. Less conventional than software-based systems, these types of simulators generally combine digital and analog forms of computation. In this paper we present a mixed hardware-software platform, specifically designed for the simulation of spiking neural networks, using conductance-based models of neurons and synaptic connections with dynamic adaptation rules (Spike-Timing-Dependent Plasticity). The neurons and networks are configurable, and are computed in 'biological real time' by which we mean that the difference between simulated time and simulation time is guaranteed lower than 50 mus. After presenting the issues and context involved in the design and use of hardware-based spiking neural networks, we describe the analog neuromimetic integrated circuits which form the core of the platform. We then explain the organization and computation principles of the modules within the platform, and present experimental results which validate the system. Designed as a tool for computational neuroscience, the platform is exploited in collaborative research projects together with neurobiology and computer science partners. Copyright 2010 Elsevier Ltd. All rights reserved.

  8. Locating hardware faults in a data communications network of a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-01-12

    Hardware faults location in a data communications network of a parallel computer. Such a parallel computer includes a plurality of compute nodes and a data communications network that couples the compute nodes for data communications and organizes the compute node as a tree. Locating hardware faults includes identifying a next compute node as a parent node and a root of a parent test tree, identifying for each child compute node of the parent node a child test tree having the child compute node as root, running a same test suite on the parent test tree and each child test tree, and identifying the parent compute node as having a defective link connected from the parent compute node to a child compute node if the test suite fails on the parent test tree and succeeds on all the child test trees.

  9. Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

    Science.gov (United States)

    Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

    2017-10-01

    Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

  10. Implementation of Karp-Rabin string matching algorithm in reconfigurable hardware for network intrusion prevention system

    Science.gov (United States)

    Botwicz, Jakub; Buciak, Piotr; Sapiecha, Piotr

    2006-03-01

    Intrusion Prevention Systems (IPSs) have become widely recognized as a powerful tool and an important element of IT security safeguards. The essential feature of network IPSs is searching through network packets and matching multiple strings, that are fingerprints of known attacks. String matching is highly resource consuming and also the most significant bottleneck of IPSs. In this article an extension of the classical Karp-Rabin algorithm and its implementation architectures were examined. The result is a software, which generates a source code of a string matching module in hardware description language, that could be easily used to create an Intrusion Prevention System implemented in reconfigurable hardware. The prepared module matches the complete set of Snort IPS signatures achieving throughput of over 2 Gbps on an Altera Stratix I1 evaluation board. The most significant advantage of the proposed architecture is that the update of the patterns database does not require reconfiguration of the circuitry.

  11. An evaluation of options to mitigate voltage rise due to increasing PV penetration in distribution networks

    Directory of Open Access Journals (Sweden)

    Carter Craig E.

    2017-01-01

    Full Text Available Australia and most other countries are adopting renewable energy generation as the dominant means of reducing dependence on fossil fuels. This has been made more feasible by the exponential take-up of solar photovoltaic (PV systems and their concurrent production scale-up and cost decline. Rooftop solar PV, combined with battery storage, seems likely to be the dominant means of providing household electricity needs. In response to the technical challenges from rooftop PV, network utilities have implemented various low cost options to cope with PV’s impact on network voltages. However, if we want this clean energy technology to fully utilise the available roof space and eventually meet residential electricity needs, additional hardware, control and commercial options will need to be adopted by both network utilities and their customers to overcome the technical barriers, especially voltage rise. This paper presents the authors’ evaluations of options to mitigate voltage rise, including operating solar inverters with reactive power absorption (var absorbing, dependent only on solar power output or operating the solar inverters in a volt–var response mode (voltage droop control where the inverter adjusts its reactive power (Q in response to changes in its terminal voltage – Q(V. This paper also considers the fulltime Q(V option, where an inverter’s reactive power capacity is independent of solar conditions – statcom mode. The network utility option of using line drop compensation (LDC – used on long rural MV feeders on urban MV feeders during daylight hours is assessed to lessen voltage rise on LV feeders with low net loading or reverse power flow due to high solar PV generation. The paper concludes that a combination of solar inverters performing fast fulltime voltage droop control outside a voltage deadband (statcom mode and HV/MV substation transformers with slow acting daytime LDC mitigates voltage rise, whilst limiting feeder

  12. IT Career JumpStart An Introduction to PC Hardware, Software, and Networking

    CERN Document Server

    Alpern, Naomi J; Muller, Randy

    2011-01-01

    A practical approach for anyone looking to enter the IT workforce Before candidates can begin to prepare for any kind of certification, they need a basic understanding of the various hardware and software components used in a computer network. Aimed at aspiring IT professionals, this invaluable book strips down a network to its bare basics, and discusses this complex topic in a clear and concise manner so that IT beginners can confidently gain an understanding of fundamental IT concepts. In addition, a base knowledge has been established so that more advanced topics and technologies can be lea

  13. Joint preprocesser-based detector for cooperative networks with limited hardware processing capability

    KAUST Repository

    Abuzaid, Abdulrahman I.

    2015-02-01

    In this letter, a joint detector for cooperative communication networks is proposed when the destination has limited hardware processing capability. The transmitter sends its symbols with the help of L relays. As the destination has limited hardware, only U out of L signals are processed and the energy of the remaining relays is lost. To solve this problem, a joint preprocessing based detector is proposed. This joint preprocessor based detector operate on the principles of minimizing the symbol error rate (SER). For a realistic assessment, pilot symbol aided channel estimation is incorporated for this proposed detector. From our simulations, it can be observed that our proposed detector achieves the same SER performance as that of the maximum likelihood (ML) detector with all participating relays. Additionally, our detector outperforms selection combining (SC), channel shortening (CS) scheme and reduced-rank techniques when using the same U. Our proposed scheme has low computational complexity.

  14. Hardware-in-the-loop simulation, a systematic test option for ESP control systems; Hardware-in-the-Loop Simulation als systematische Testmoeglichkeit fuer ESP-Steuergeraete

    Energy Technology Data Exchange (ETDEWEB)

    Grund, C. [Audi AG, Ingolstadt (Germany)

    1999-07-01

    Modern slip control systems as well as the required test procedures are getting increasingly complex. With the aid or real-time simulations, the software and diagnosis functions of the control unit, actuators and sensors can be tested systematically, reproducibly and at low cost. In hardware-in-the-loop (HIL) simulation, the control unit to be tested is integrated into the simulation as hardware while the vehicle behaviour is displayed on the computer in real-time. The braking hydraulics is integrated as a simulation model as well and is controlled via an analog circuit for recording the magnetic valve signals using Hall sensors. The following slip control systems are tested by Audi: The antiblocking system (ABS), the electronic differential lock (EDS), the driving slip control system (ASR), and the electronic stability program (ESP) which comprises all of the other systems. All systems have one thing in common: As input data, they use the measured wheel speeds which in the case of HIL simulation are simulated using a real-time vehicle model instead of being measured in a real vehicle. In the case of ESP, other sensor signals such as must be simulated as well, and the steering angle must be preselected by the driver model. In the case of ASR, the engine momentum and speed must be simulated. The control variables are largely set by the control unit (brake actuation and, in the case of ASR, also engine actuation). [German] Moderne Radschlupfregelsysteme werden immer komplexer und stellen an den Fahrzeughersteller hohe Anforderungen an seine Testmoeglichkeiten. Mit Hilfe von Echtzeitsimulationen koennen die Software- und Diagnosefunktionen des Steuergeraets bzw. die Aktuatoren und Sensoren systematisch, reproduzierbar und kostensparend getestet werden. Die Idee bei einer Hardware-in-the-Loop (HIL)-Simulation ist, das zu testende Steuergeraet als Hardware in den Simulationslauf einzubeziehen, waehrend das Verhalten des Fahrzeugs in Echtzeit auf dem Rechner nachgebildet

  15. Condition monitoring of planetary gearbox by hardware implementation of artificial neural networks

    DEFF Research Database (Denmark)

    Dabrowski, Dariusz

    2016-01-01

    -stationary conditions and are exposed to extreme events. Also bucket-wheel excavators are equipped with high-power gearboxes that are exposed to shocks. Continuous monitoring of their condition is crucial in view of early failures, and to ensure safety of exploitation. Artificial neural networks allow for a quick...... and effective association of the symptoms with the condition of the machine. Extensive research shows that neural networks can be successfully used to recognize gearboxes' failures; they allow for detection of new failures which were not known at the time of training and can be applied for identification...... of failures in variable-speed applications. In a majority of the studies conducted so far neural networks were implemented in the software, but for dedicated engineering applications the hardware implementation is being used increasingly, due to high efficiency, flexibility and resistant to harsh...

  16. Back-propagation operation for analog neural network hardware with synapse components having hysteresis characteristics.

    Directory of Open Access Journals (Sweden)

    Michihito Ueda

    Full Text Available To realize an analog artificial neural network hardware, the circuit element for synapse function is important because the number of synapse elements is much larger than that of neuron elements. One of the candidates for this synapse element is a ferroelectric memristor. This device functions as a voltage controllable variable resistor, which can be applied to a synapse weight. However, its conductance shows hysteresis characteristics and dispersion to the input voltage. Therefore, the conductance values vary according to the history of the height and the width of the applied pulse voltage. Due to the difficulty of controlling the accurate conductance, it is not easy to apply the back-propagation learning algorithm to the neural network hardware having memristor synapses. To solve this problem, we proposed and simulated a learning operation procedure as follows. Employing a weight perturbation technique, we derived the error change. When the error reduced, the next pulse voltage was updated according to the back-propagation learning algorithm. If the error increased the amplitude of the next voltage pulse was set in such way as to cause similar memristor conductance but in the opposite voltage scanning direction. By this operation, we could eliminate the hysteresis and confirmed that the simulation of the learning operation converged. We also adopted conductance dispersion numerically in the simulation. We examined the probability that the error decreased to a designated value within a predetermined loop number. The ferroelectric has the characteristics that the magnitude of polarization does not become smaller when voltages having the same polarity are applied. These characteristics greatly improved the probability even if the learning rate was small, if the magnitude of the dispersion is adequate. Because the dispersion of analog circuit elements is inevitable, this learning operation procedure is useful for analog neural network hardware.

  17. Open-source hardware and software and web application for gamma dose rate network operation.

    Science.gov (United States)

    Luff, R; Zähringer, M; Harms, W; Bleher, M; Prommer, B; Stöhlker, U

    2014-08-01

    The German Federal Office for Radiation Protection operates a network of about 1800 gamma dose rate stations as a part of the national emergency preparedness plan. Each of the six network centres is capable of operating the network alone. Most of the used hardware and software have been developed in-house under open-source license. Short development cycles and close cooperation between developers and users ensure robustness, transparency and fast maintenance procedures, thus avoiding unnecessary complex solutions. This also reduces the overall costs of the network operation. An easy-to-expand web interface has been developed to make the complete system available to other interested network operators in order to increase cooperation between different countries. The interface is also regularly in use for education during scholarships of trainees supported, e.g. by the 'International Atomic Energy Agency' to operate a local area dose rate monitoring test network. © The Author 2014. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

  18. Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

    Directory of Open Access Journals (Sweden)

    Marcelo Urbina

    2018-02-01

    Full Text Available Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA, to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP. Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850. The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA. The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM, defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.

  19. Large-Scale Simulations of Plastic Neural Networks on Neuromorphic Hardware

    Science.gov (United States)

    Knight, James C.; Tully, Philip J.; Kaplan, Bernhard A.; Lansner, Anders; Furber, Steve B.

    2016-01-01

    SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Rather than using bespoke analog or digital hardware, the basic computational unit of a SpiNNaker system is a general-purpose ARM processor, allowing it to be programmed to simulate a wide variety of neuron and synapse models. This flexibility is particularly valuable in the study of biological plasticity phenomena. A recently proposed learning rule based on the Bayesian Confidence Propagation Neural Network (BCPNN) paradigm offers a generic framework for modeling the interaction of different plasticity mechanisms using spiking neurons. However, it can be computationally expensive to simulate large networks with BCPNN learning since it requires multiple state variables for each synapse, each of which needs to be updated every simulation time-step. We discuss the trade-offs in efficiency and accuracy involved in developing an event-based BCPNN implementation for SpiNNaker based on an analytical solution to the BCPNN equations, and detail the steps taken to fit this within the limited computational and memory resources of the SpiNNaker architecture. We demonstrate this learning rule by learning temporal sequences of neural activity within a recurrent attractor network which we simulate at scales of up to 2.0 × 104 neurons and 5.1 × 107 plastic synapses: the largest plastic neural network ever to be simulated on neuromorphic hardware. We also run a comparable simulation on a Cray XC-30 supercomputer system and find that, if it is to match the run-time of our SpiNNaker simulation, the super computer system uses approximately 45× more power. This suggests that cheaper, more power efficient neuromorphic systems are becoming useful discovery tools in the study of plasticity in large-scale brain models. PMID:27092061

  20. Large-scale simulations of plastic neural networks on neuromorphic hardware

    Directory of Open Access Journals (Sweden)

    James Courtney Knight

    2016-04-01

    Full Text Available SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Rather than using bespoke analog or digital hardware, the basic computational unit of a SpiNNaker system is a general-purpose ARM processor, allowing it to be programmed to simulate a wide variety of neuron and synapse models. This flexibility is particularly valuable in the study of biological plasticity phenomena. A recently proposed learning rule based on the Bayesian Confidence Propagation Neural Network (BCPNN paradigm offers a generic framework for modeling the interaction of different plasticity mechanisms using spiking neurons. However, it can be computationally expensive to simulate large networks with BCPNN learning since it requires multiple state variables for each synapse, each of which needs to be updated every simulation time-step. We discuss the trade-offs in efficiency and accuracy involved in developing an event-based BCPNN implementation for SpiNNaker based on an analytical solution to the BCPNN equations, and detail the steps taken to fit this within the limited computational and memory resources of the SpiNNaker architecture. We demonstrate this learning rule by learning temporal sequences of neural activity within a recurrent attractor network which we simulate at scales of up to 20000 neurons and 51200000 plastic synapses: the largest plastic neural network ever to be simulated on neuromorphic hardware. We also run a comparable simulation on a Cray XC-30 supercomputer system and find that, if it is to match the run-time of our SpiNNaker simulation, the super computer system uses approximately more power. This suggests that cheaper, more power efficient neuromorphic systems are becoming useful discovery tools in the study of plasticity in large-scale brain models.

  1. The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

    Energy Technology Data Exchange (ETDEWEB)

    Tierney, Brian L; Vallentin, Matthias; Sommer, Robin; Lee, Jason; Leres, Craig; Paxson, Vern; Tierney, Brian

    2007-09-19

    In this work we present a NIDS cluster as a scalable solution for realizing high-performance, stateful network intrusion detection on commodity hardware. The design addresses three challenges: (i) distributing traffic evenly across an extensible set of analysis nodes in a fashion that minimizes the communication required for coordination, (ii) adapting the NIDS's operation to support coordinating its low-level analysis rather than just aggregating alerts; and (iii) validating that the cluster produces sound results. Prototypes of our NIDS cluster now operate at the Lawrence Berkeley National Laboratory and the University of California at Berkeley. In both environments the clusters greatly enhance the power of the network security monitoring.

  2. CRYSNET manual. Informal report. [Hardware and software of crystallographic computing network

    Energy Technology Data Exchange (ETDEWEB)

    None,

    1976-07-01

    This manual describes the hardware and software which together make up the crystallographic computing network (CRYSNET). The manual is intended as a users' guide and also provides general information for persons without any experience with the system. CRYSNET is a network of intelligent remote graphics terminals that are used to communicate with the CDC Cyber 70/76 computing system at the Brookhaven National Laboratory (BNL) Central Scientific Computing Facility. Terminals are in active use by four research groups in the field of crystallography. A protein data bank has been established at BNL to store in machine-readable form atomic coordinates and other crystallographic data for macromolecules. The bank currently includes data for more than 20 proteins. This structural information can be accessed at BNL directly by the CRYSNET graphics terminals. More than two years of experience has been accumulated with CRYSNET. During this period, it has been demonstrated that the terminals, which provide access to a large, fast third-generation computer, plus stand-alone interactive graphics capability, are useful for computations in crystallography, and in a variety of other applications as well. The terminal hardware, the actual operations of the terminals, and the operations of the BNL Central Facility are described in some detail, and documentation of the terminal and central-site software is given. (RWR)

  3. Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

    Directory of Open Access Journals (Sweden)

    Daniel Litinski

    2017-09-01

    Full Text Available We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall–superconductor hybrids.

  4. Cyber-Physical Test Platform for Microgrids: Combining Hardware, Hardware-in-the-Loop, and Network-Simulator-in-the-Loop

    Energy Technology Data Exchange (ETDEWEB)

    Nelson, Austin; Chakraborty, Sudipta; Wang, Dexin; Singh, Pawan; Cui, Qiang; Yang, Liuqing; Suryanarayanan, Siddharth

    2016-11-14

    This paper presents a cyber-physical testbed, developed to investigate the complex interactions between emerging microgrid technologies such as grid-interactive power sources, control systems, and a wide variety of communication platforms and bandwidths. The cyber-physical testbed consists of three major components for testing and validation: real time models of a distribution feeder model with microgrid assets that are integrated into the National Renewable Energy Laboratory's (NREL) power hardware-in-the-loop (PHIL) platform; real-time capable network-simulator-in-the-loop (NSIL) models; and physical hardware including inverters and a simple system controller. Several load profiles and microgrid configurations were tested to examine the effect on system performance with increasing channel delays and router processing delays in the network simulator. Testing demonstrated that the controller's ability to maintain a target grid import power band was severely diminished with increasing network delays and laid the foundation for future testing of more complex cyber-physical systems.

  5. Autonomous target tracking of UAVs based on low-power neural network hardware

    Science.gov (United States)

    Yang, Wei; Jin, Zhanpeng; Thiem, Clare; Wysocki, Bryant; Shen, Dan; Chen, Genshe

    2014-05-01

    Detecting and identifying targets in unmanned aerial vehicle (UAV) images and videos have been challenging problems due to various types of image distortion. Moreover, the significantly high processing overhead of existing image/video processing techniques and the limited computing resources available on UAVs force most of the processing tasks to be performed by the ground control station (GCS) in an off-line manner. In order to achieve fast and autonomous target identification on UAVs, it is thus imperative to investigate novel processing paradigms that can fulfill the real-time processing requirements, while fitting the size, weight, and power (SWaP) constrained environment. In this paper, we present a new autonomous target identification approach on UAVs, leveraging the emerging neuromorphic hardware which is capable of massively parallel pattern recognition processing and demands only a limited level of power consumption. A proof-of-concept prototype was developed based on a micro-UAV platform (Parrot AR Drone) and the CogniMemTMneural network chip, for processing the video data acquired from a UAV camera on the y. The aim of this study was to demonstrate the feasibility and potential of incorporating emerging neuromorphic hardware into next-generation UAVs and their superior performance and power advantages towards the real-time, autonomous target tracking.

  6. Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.

    Science.gov (United States)

    Carrillo, Snaider; Harkin, Jim; McDaid, Liam; Pande, Sandeep; Cawley, Seamus; McGinley, Brian; Morgan, Fearghal

    2012-09-01

    The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware. Copyright © 2012 Elsevier Ltd. All rights reserved.

  7. Three applications of pulse-coupled neural networks and an optoelectronic hardware implementation

    Science.gov (United States)

    Banish, Michele R.; Ranganath, Heggere S.; Karpinsky, John R.; Clark, Rodney L.; Germany, Glynn A.; Richards, Philip G.

    1999-03-01

    Pulse Coupled Neural Networks have been extended and modified to suit image segmentation applications. Previous research demonstrated the ability of a PCNN to ignore noisy variations in intensity and small spatial discontinuities in images that prove beneficial to image segmentation and image smoothing. This paper describes four research and development projects that relate to PCNN segmentation - three different signal processing applications and a CMOS integrated circuit implementation. The software for the diagnosis of Pulmonary Embolism from VQ lung scans uses PCNN in single burst mode for segmenting perfusion and ventilation images. The second project is attempting to detect ischemia by comparing 3D SPECT images of the heart obtained during stress and rest conditions, respectively. The third application is a space science project which deals with the study of global aurora images obtained from UV Imager. The paper also describes the hardware implementation of PCNN algorithm as an electro-optical chip.

  8. Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

    Science.gov (United States)

    Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

    2015-01-01

    Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

  9. Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

    Directory of Open Access Journals (Sweden)

    Diana Göhringer

    2012-01-01

    Full Text Available This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC. The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.

  10. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain

    Science.gov (United States)

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-01-01

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture. PMID:27527180

  11. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain.

    Science.gov (United States)

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-08-04

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN systems are mandatory. This paper focuses on the hardware design architectures of the WSANs for real-world agricultural applications. It presents the available alternatives in hardware design and identifies their difficulties and problems for real-life implementations. The paper introduces SensoTube, a new WSAN hardware architecture, which is proposed as a solution to the various existing design constraints of WSANs. The establishment of the proposed architecture is based, firstly on an abstraction approach in the functional requirements context, and secondly, on the standardization of the subsystems connectivity, in order to allow for an open, expandable, flexible, reconfigurable, energy optimized, reliable and robust hardware system. The SensoTube implementation reference model together with its encapsulation design and installation are analyzed and presented in details. Furthermore, as a proof of concept, certain use cases have been studied in order to demonstrate the benefits of migrating existing designs based on the available open-source hardware platforms to SensoTube architecture.

  12. A networked modular hardware and software system for MRI-guided robotic prostate interventions

    Science.gov (United States)

    Su, Hao; Shang, Weijian; Harrington, Kevin; Camilo, Alex; Cole, Gregory; Tokuda, Junichi; Hata, Nobuhiko; Tempany, Clare; Fischer, Gregory S.

    2012-02-01

    Magnetic resonance imaging (MRI) provides high resolution multi-parametric imaging, large soft tissue contrast, and interactive image updates making it an ideal modality for diagnosing prostate cancer and guiding surgical tools. Despite a substantial armamentarium of apparatuses and systems has been developed to assist surgical diagnosis and therapy for MRI-guided procedures over last decade, the unified method to develop high fidelity robotic systems in terms of accuracy, dynamic performance, size, robustness and modularity, to work inside close-bore MRI scanner still remains a challenge. In this work, we develop and evaluate an integrated modular hardware and software system to support the surgical workflow of intra-operative MRI, with percutaneous prostate intervention as an illustrative case. Specifically, the distinct apparatuses and methods include: 1) a robot controller system for precision closed loop control of piezoelectric motors, 2) a robot control interface software that connects the 3D Slicer navigation software and the robot controller to exchange robot commands and coordinates using the OpenIGTLink open network communication protocol, and 3) MRI scan plane alignment to the planned path and imaging of the needle as it is inserted into the target location. A preliminary experiment with ex-vivo phantom validates the system workflow, MRI-compatibility and shows that the robotic system has a better than 0.01mm positioning accuracy.

  13. Medium access control and hardware prototype designs for low-energy wireless sensor networks

    Energy Technology Data Exchange (ETDEWEB)

    Kohvakka, M.

    2009-07-01

    A Wireless Sensor Network (WSN) is an emerging technology consisting of small, cheap, and ultra-low energy sensor nodes, which cooperatively monitor physical quantities, actuate, and perform data processing tasks. A deployment may comprise thousands of randomly distributed autonomous nodes, which must self-configure and create a multi-hop network topology.This thesis focuses on low-energy WSNs targeting to long network lifetime. The main research problem is the combination of adaptive and scalable multi-hop networking with constrained energy budget, processing power, and communication bandwidth. The research problem is approached by energy-efficient protocols and low-power sensor node platforms. The main contribution of this thesis is an energy-efficient Medium Access Control (MAC) design for TUTWSN (Tampere University of Technology Wireless Sensor Network). The design comprises channel access and networking mechanisms, which specify data exchange, link synchronization, network self-configuration, and neighbor discovery operations. The second outcome are several low-power sensor node platforms, which have been designed and implemented to evaluate the performance of the MAC design and hardware components in real deployments. The third outcome are the performance models and analysis of several MAC designs including TUTWSN, IEEE 802.15.4, and the most essential research proposals.The results and conclusion of this Thesis indicate that it is possible to implement multi-hop WSNs in harsh and dynamic operation conditions with years of lifetime using current low-cost components and batteries. Energy analysis results indicate that the lowest energy consumption is achieved by using simple and high data-rate transceivers. It is also critical to minimize sleep mode power consumption of all components and to use accurate wake-up timers. However, the selection of components constitutes only a minor part of the solution, and an energy-efficient MAC layer design being able to

  14. Easy Handling of Sensors and Actuators over TCP/IP Networks by Open Source Hardware/Software.

    Science.gov (United States)

    Mejías, Andrés; Herrera, Reyes S; Márquez, Marco A; Calderón, Antonio José; González, Isaías; Andújar, José Manuel

    2017-01-05

    There are several specific solutions for accessing sensors and actuators present in any process or system through a TCP/IP network, either local or a wide area type like the Internet. The usage of sensors and actuators of different nature and diverse interfaces (SPI, I2C, analogue, etc.) makes access to them from a network in a homogeneous and secure way more complex. A framework, including both software and hardware resources, is necessary to simplify and unify networked access to these devices. In this paper, a set of open-source software tools, specifically designed to cover the different issues concerning the access to sensors and actuators, and two proposed low-cost hardware architectures to operate with the abovementioned software tools are presented. They allow integrated and easy access to local or remote sensors and actuators. The software tools, integrated in the free authoring tool Easy Java and Javascript Simulations (EJS) solve the interaction issues between the subsystem that integrates sensors and actuators into the network, called convergence subsystem in this paper, and the Human Machine Interface (HMI)-this one designed using the intuitive graphical system of EJS-located on the user's computer. The proposed hardware architectures and software tools are described and experimental implementations with the proposed tools are presented.

  15. Easy Handling of Sensors and Actuators over TCP/IP Networks by Open Source Hardware/Software

    Directory of Open Access Journals (Sweden)

    Andrés Mejías

    2017-01-01

    Full Text Available There are several specific solutions for accessing sensors and actuators present in any process or system through a TCP/IP network, either local or a wide area type like the Internet. The usage of sensors and actuators of different nature and diverse interfaces (SPI, I2C, analogue, etc. makes access to them from a network in a homogeneous and secure way more complex. A framework, including both software and hardware resources, is necessary to simplify and unify networked access to these devices. In this paper, a set of open-source software tools, specifically designed to cover the different issues concerning the access to sensors and actuators, and two proposed low-cost hardware architectures to operate with the abovementioned software tools are presented. They allow integrated and easy access to local or remote sensors and actuators. The software tools, integrated in the free authoring tool Easy Java and Javascript Simulations (EJS solve the interaction issues between the subsystem that integrates sensors and actuators into the network, called convergence subsystem in this paper, and the Human Machine Interface (HMI—this one designed using the intuitive graphical system of EJS—located on the user’s computer. The proposed hardware architectures and software tools are described and experimental implementations with the proposed tools are presented.

  16. SensoTube: A Scalable Hardware Design Architecture for Wireless Sensors and Actuators Networks Nodes in the Agricultural Domain

    OpenAIRE

    Piromalis, Dimitrios; Arvanitis, Konstantinos

    2016-01-01

    Wireless Sensor and Actuators Networks (WSANs) constitute one of the most challenging technologies with tremendous socio-economic impact for the next decade. Functionally and energy optimized hardware systems and development tools maybe is the most critical facet of this technology for the achievement of such prospects. Especially, in the area of agriculture, where the hostile operating environment comes to add to the general technological and technical issues, reliable and robust WSAN system...

  17. Comparison of GPU- and CPU-implementations of mean-firing rate neural networks on parallel hardware.

    Science.gov (United States)

    Dinkelbach, Helge Ülo; Vitay, Julien; Beuth, Frederik; Hamker, Fred H

    2012-01-01

    Modern parallel hardware such as multi-core processors (CPUs) and graphics processing units (GPUs) have a high computational power which can be greatly beneficial to the simulation of large-scale neural networks. Over the past years, a number of efforts have focused on developing parallel algorithms and simulators best suited for the simulation of spiking neural models. In this article, we aim at investigating the advantages and drawbacks of the CPU and GPU parallelization of mean-firing rate neurons, widely used in systems-level computational neuroscience. By comparing OpenMP, CUDA and OpenCL implementations towards a serial CPU implementation, we show that GPUs are better suited than CPUs for the simulation of very large networks, but that smaller networks would benefit more from an OpenMP implementation. As this performance strongly depends on data organization, we analyze the impact of various factors such as data structure, memory alignment and floating precision. We then discuss the suitability of the different hardware depending on the networks' size and connectivity, as random or sparse connectivities in mean-firing rate networks tend to break parallel performance on GPUs due to the violation of coalescence.

  18. PUFKEY: A High-Security and High-Throughput Hardware True Random Number Generator for Sensor Networks

    Directory of Open Access Journals (Sweden)

    Dongfang Li

    2015-10-01

    Full Text Available Random number generators (RNG play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST randomness tests and is resilient to a wide range of security attacks.

  19. PUFKEY: a high-security and high-throughput hardware true random number generator for sensor networks.

    Science.gov (United States)

    Li, Dongfang; Lu, Zhaojun; Zou, Xuecheng; Liu, Zhenglin

    2015-10-16

    Random number generators (RNG) play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF) elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST) randomness tests and is resilient to a wide range of security attacks.

  20. A Hardware Design of Neuromolecular Network with Enhanced Evolvability: A Bioinspired Approach

    Directory of Open Access Journals (Sweden)

    Yo-Hsien Lin

    2012-01-01

    Full Text Available Silicon-based computer systems have powerful computational capability. However, they are easy to malfunction because of a slight program error. Organisms have better adaptability than computer systems in dealing with environmental changes or noise. A close structure-function relation inherent in biological structures is an important feature for providing great malleability to environmental changes. An evolvable neuromolecular hardware motivated by some biological evidence, which integrates inter- and intraneuronal information processing, was proposed. The hardware was further applied to the pattern-recognition domain. The circuit was tested with Quartus II system, a digital circuit simulation tool. The experimental result showed that the artificial neuromolecularware exhibited a close structure-function relationship, possessed several evolvability-enhancing features combined to facilitate evolutionary learning, and was capable of functioning continuously in the face of noise.

  1. Occupational skin diseases: options for multidisciplinary networking in preventive medicine.

    Science.gov (United States)

    John, Swen Malte

    2008-10-27

    and educational intervention seminars (secondary individual prevention, SIP) are offered to affected employees. We recently demonstrated the sustainability of the SIP approach in hairdressing for periods of up to 10 years. For those cases of OD, in which the abovementioned outpatient prevention measures are not sufficiently successful, specific interdisciplinary inpatient prevention measures have been developed (tertiary individual prevention, or TIP). TIP represents the ultima ratio within the hierarchical prevention concept of the Osnabrück Model. TIP comprises 2-3 weeks of inpatient dermatological diagnostics and treatment as well as intensive health-related pedagogic and psychological counseling. Subsequent to this, 3 consecutive weeks of outpatient treatment are given by a local dermatologist. Each patient remains on sick-leave for a total of 6 weeks to allow full barrier recovery. A total of 764 out of 1164 (66%) TIP patients treated in our university, followed-up regularly by a local dermatologist for up to 1 year, were successful in remaining in their respective (risk-) professions as assessed by questionnaire 1 year after discharge. Recently obtained SIP and TIP data reveal that there are reliable, evidence-based options for multidisciplinary prevention and patient management of OD, using a combined approach by a network of clinics, practices and statutory social insurance bodies. A multicentre study, which aims to further standardize TIP and evaluate sustainability of prevention in more depth (3-year dermatological follow-up of 1000 OD patients) is currently being conducted in Germany.

  2. Social network sites: Indispensable or optional social tools?

    DEFF Research Database (Denmark)

    Shklovski, Irina

    2012-01-01

    Much research has enumerated potential benefits of online social network sites. Given the pervasiveness of these sites and the numbers of people that use them daily, both re-search and media tend to make the assumption that social network sites have become indispensible to their users. Based...... on the analysis of qualitative data from users of social network sites in Russia and Kazakhstan, this paper consid-ers under what conditions social network sites can become indispensable to their users and when these technologies remain on the periphery of life despite fulfilling useful func-tions. For some...... respondents, these sites had become indis-pensable tools as they were integrated into everyday rou-tines of communicating with emotionally important and proximal contacts and were often used for coordination of offline activities. For others social network sites remained spaces where they occasionally visited...

  3. Sign Language Recognition System using Neural Network for Digital Hardware Implementation

    Energy Technology Data Exchange (ETDEWEB)

    Vargas, Lorena P [Lorena Vargas Quintero, Optic and Computer Science Group - Universidad Popular del Cesar (Colombia); Barba, Leiner; Torres, C O; Mattos, L, E-mail: vargas.lorena@yahoo.com [Optic and Computer Science Group - Popular of Cesar University, Km 12, Valledupar (Colombia)

    2011-01-01

    This work presents an image pattern recognition system using neural network for the identification of sign language to deaf people. The system has several stored image that show the specific symbol in this kind of language, which is employed to teach a multilayer neural network using a back propagation algorithm. Initially, the images are processed to adapt them and to improve the performance of discriminating of the network, including in this process of filtering, reduction and elimination noise algorithms as well as edge detection. The system is evaluated using the signs without including movement in their representation.

  4. Applying Real Options Thinking to Information Security in Networked Organizations

    NARCIS (Netherlands)

    Daneva, Maia

    2006-01-01

    An information security strategy of an organization participating in a networked business sets out the plans for designing a variety of actions that ensure confidentiality, availability, and integrity of company’s key information assets. The actions are concerned with authentication and

  5. Hardware design of the median filter based on window structure and batcher′s oddeven sort network

    Directory of Open Access Journals (Sweden)

    SUN Kaimin

    2013-06-01

    Full Text Available Area and speed are two important factors to be considered in designing Median Filter with digital circuits.Area consideration requires the use of logical resources as little as possible,while speed consideration requires the system capable of working on higher clock frequencies,with as few clock cycles as possible to complete a frame filtering or real time filtering.This paper gives a new design of Median Filter,the hardware structure of which is a 3×3 window structure with two buffers.The filter function module is based on Batcher′s Odd-Even Sort network theory.Structural design is implemented in FPGA,verified by ModelSim software and realizes video image filtering.The experimental analysis shows that this new structure of Median Filter effectively decreases logical resources (merely using 741 Logic Elements,and accelerates the pixel processing speed up to 27MHz.This filter achieves realtime processing of video images of 30 frames/s.This design not only has a certain practicality,but also provides a reference for the hardware structure design ideas in digital image processing.

  6. Privacy-preserving telecardiology sensor networks: toward a low-cost portable wireless hardware/software codesign.

    Science.gov (United States)

    Hu, Fei; Jiang, Meng; Wagner, Mark; Dong, De-Cun

    2007-11-01

    Recently, a remote-sensing platform based on wireless interconnection of tiny ECG sensors called Telecardiology Sensor Networks (TSN) provided a promising approach to perform low-cost real-time cardiac patient monitoring at any time in community areas (such as elder nursing homes or hospitals). The contribution of this research is the design of a practical TSN hardware/software platform for a typical U.S. healthcare community scenario (such as large nursing homes with many elder patients) to perform real-time healthcare data collections. On the other hand, due to the radio broadcasting nature of MANET, a TSN has the risk of losing the privacy of patients' data. Medical privacy has been highly emphasized by U.S. Department of Health and Human Services. This research also designs a medical security scheme with low communication overhead to achieve confidential electrocardiogram data transmission in wireless medium.

  7. Fixed latency on-chip interconnect for hardware spiking neural network architectures

    NARCIS (Netherlands)

    Pande, Sandeep; Morgan, Fearghal; Smit, Gerardus Johannes Maria; Bruintjes, Tom; Rutgers, J.H.; Cawley, Seamus; Harkin, Jim; McDaid, Liam

    Information in a Spiking Neural Network (SNN) is encoded as the relative timing between spikes. Distortion in spike timings can impact the accuracy of SNN operation by modifying the precise firing time of neurons within the SNN. Maintaining the integrity of spike timings is crucial for reliable

  8. Sensor fault detection and isolation over wireless sensor network based on hardware redundancy

    Science.gov (United States)

    Hao, Jingjing; Kinnaert, Michel

    2017-01-01

    In order to diagnose sensor faults with small magnitude in wireless sensor networks, distinguishability measures are defined to indicate the performance for fault detection and isolation (FDI) at each node. A systematic method is then proposed to determine the information to be exchanged between nodes to achieve FDI specifications while limiting the computation complexity and communication cost.

  9. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  10. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  11. The VMTG Hardware Description

    CERN Document Server

    Puccio, B

    1998-01-01

    The document describes the hardware features of the CERN Master Timing Generator. This board is the common platform for the transmission of General Timing Machine required by the CERN accelerators. In addition, the paper shows the various jumper options to customise the card which is compliant to the VMEbus standard.

  12. Large research infrastructure for Earth-Ocean Science: Challenges of multidisciplinary integration across hardware, software, and people networks

    Science.gov (United States)

    Best, M.; Barnes, C. R.; Johnson, F.; Pautet, L.; Pirenne, B.; Founding Scientists Of Neptune Canada

    2010-12-01

    NEPTUNE Canada is operating a regional cabled ocean observatory across the northern Juan de Fuca Plate in the northeastern Pacific. Installation of the first suite of instruments and connectivity equipment was completed in 2009, so this system now provides the continuous power and bandwidth to collect integrated data on physical, chemical, geological, and biological gradients at temporal resolutions relevant to the dynamics of the earth-ocean system. The building of this facility integrates hardware, software, and people networks. Hardware progress to date includes: installation of the 800km powered fiber-optic backbone in the Fall of 2007; development of Nodes and Junction Boxes; acquisition/development and testing of Instruments; development of mobile instrument platforms such as a) a Vertical Profiler and b) a Crawler (University of Bremmen); and integration of over a thousand components into an operating subsea sensor system. Nodes, extension cables, junction boxes, and instruments were installed at 4 out of 5 locations in 2009; the fifth Node is instrumented in September 2010. In parallel, software and hardware systems are acquiring, archiving, and delivering the continuous real-time data through the internet to the world - already many terabytes of data. A web environment (Oceans 2.0) to combine this data access with analysis and visualization, collaborative tools, interoperability, and instrument control is being released. Finally, a network of scientists and technicians are contributing to the process in every phase, and data users already number in the thousands. Initial experiments were planned through a series of workshops and international proposal competitions. At inshore Folger Passage, Barkley Sound, understanding controls on biological productivity help evaluate the effects that marine processes have on fish and marine mammals. Experiments around Barkley Canyon allow quantification of changes in biological and chemical activity associated with

  13. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  14. Comparison of High Performance Network Options: EDR InfiniBand vs.100Gb RDMA Capable Ethernet

    Energy Technology Data Exchange (ETDEWEB)

    Kachelmeier, Luke Anthony [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Univ. of New Mexico, Albuquerque, NM (United States); Van Wig, Faith Virginia [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Missouri Univ. of Science and Technology, Rolla, MO (United States); Erickson, Kari Natania [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); New Mexico Inst. of Mining and Technology, Socorro, NM (United States)

    2016-08-08

    These are the slides for a presentation at the HPC Mini Showcase. This is a comparison of two different high performance network options: EDR InfiniBand and 100Gb RDMA capable ethernet. The conclusion of this comparison is the following: there is good potential, as shown with the direct results; 100Gb technology is too new and not standardized, thus deployment effort is complex for both options; different companies are not necessarily compatible; if you want 100Gb/s, you must get it all from one place.

  15. Hardly Hardware

    Science.gov (United States)

    Lott, Debra

    2007-01-01

    In a never-ending search for new and inspirational still-life objects, the author discovered that home improvement retailers make great resources for art teachers. Hardware and building materials are inexpensive and have interesting and variable shapes. She especially liked the dryer-vent coils and the electrical conduit. These items can be…

  16. A low cost network of spectrometer radiation detectors based on the ArduSiPM a compact transportable Software/Hardware Data Acquisition system with Arduino DUE

    Energy Technology Data Exchange (ETDEWEB)

    Bocci, Valerio; Chiodi, Giacomo; Iacoangeli, Francesco; Nuccetelli, Massimo; Recchia, Luigi [INFN Sezione di Roma, P.le Aldo moro 2, Rome, I-00185 (Italy)

    2015-07-01

    The necessity to use Photo Multipliers (PM) as light detector limited in the past the use of crystals in radiation handled device preferring the Geiger approach. The Silicon Photomultipliers (SiPMs) are very small and cheap, solid photon detectors with good dynamic range and single photon detection capability, they are usable to supersede cumbersome and difficult to use Photo Multipliers (PM). A SiPM can be coupled with a scintillator crystal to build efficient, small and solid radiation detector. A cost effective and easily replicable Hardware software module for SiPM detector readout is made using the ArduSiPM solution. The ArduSiPM is an easily battery operable handled device using an Arduino DUE (an open Software/Hardware board) as processor board and a piggy-back custom designed board (ArduSiPM Shield), the Shield contains all the blocks features to monitor, set and acquire the SiPM using internet network. (authors)

  17. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  18. Hardware for soft computing and soft computing for hardware

    CERN Document Server

    Nedjah, Nadia

    2014-01-01

    Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

  19. Analysis of Probability of Non-zero Secrecy Capacity for Multi-hop Networks in Presence of Hardware Impairments over Nakagami-m Fading Channels

    Directory of Open Access Journals (Sweden)

    T.-T. Phu

    2016-12-01

    Full Text Available In this paper, we evaluate probability of non-zero secrecy capacity of multi-hop relay networks over Nakagami-m fading channels in presence of hardware impairments. In the considered protocol, a source attempts to transmit its data to a destination by using multi-hop randomize-and-forward (RF strategy. The data transmitted by the source and relays are overheard by an eavesdropper. For performance evaluation, we derive exact expressions of probability of non-zero secrecy capacity (PoNSC, which are expressed by sums of infinite series of exponential functions and exponential integral functions. We then perform Monte Carlo simulations to verify the theoretical analysis.

  20. An Evaluation of Feral Cat Management Options Using a Decision Analysis Network

    Directory of Open Access Journals (Sweden)

    Kerrie Anne T. Loyd

    2010-12-01

    Full Text Available The feral domestic cat (Felis catus is a predatory invasive species with documented negative effects on native wildlife. The issue of appropriate and acceptable feral cat management is a matter of contentious debate in cities and states across the United States due to concerns for wildlife conservation, cat welfare, and public health. Common management strategies include: Trap-Neuter-Release, Trap-Neuter-Release with removal of kittens for adoption and Trap-Euthanize. Very little empirical evidence exists relevant to the efficacy of alternative options and a model-based approach is needed to predict population response and extend calculations to impact on wildlife. We have created a structured decision support model representing multiple stakeholder groups to facilitate the coordinated management of feral cats. We used a probabilistic graphical model (a Bayesian Belief Network to evaluate and rank alternative management decisions according to efficacy, societal preferences, and cost. Our model predicts that Trap-Neuter-Release strategies would be optimal management decisions for small local populations of less than fifty cats while Trap-Euthanize would be the optimal management decision for populations greater than 50 cats. Removal is predicted to reduce feral cat populations quickly and prevent cats from taking a large number of wildlife prey.

  1. Handbook of networking & connectivity

    CERN Document Server

    McClain, Gary R

    1994-01-01

    Handbook of Networking & Connectivity focuses on connectivity standards in use, including hardware and software options. The book serves as a guide for solving specific problems that arise in designing and maintaining organizational networks.The selection first tackles open systems interconnection, guide to digital communications, and implementing TCP/IP in an SNA environment. Discussions focus on elimination of the SNA backbone, routing SNA over internets, connectionless versus connection-oriented networks, internet concepts, application program interfaces, basic principles of layering, proto

  2. Interval type-2 fuzzy neural network controller for a multivariable anesthesia system based on a hardware-in-the-loop simulation.

    Science.gov (United States)

    El-Nagar, Ahmad M; El-Bardini, Mohammad

    2014-05-01

    This manuscript describes the use of a hardware-in-the-loop simulation to simulate the control of a multivariable anesthesia system based on an interval type-2 fuzzy neural network (IT2FNN) controller. The IT2FNN controller consists of an interval type-2 fuzzy linguistic process as the antecedent part and an interval neural network as the consequent part. It has been proposed that the IT2FNN controller can be used for the control of a multivariable anesthesia system to minimize the effects of surgical stimulation and to overcome the uncertainty problem introduced by the large inter-individual variability of the patient parameters. The parameters of the IT2FNN controller were trained online using a back-propagation algorithm. Three experimental cases are presented. All of the experimental results show good performance for the proposed controller over a wide range of patient parameters. Additionally, the results show better performance than the type-1 fuzzy neural network (T1FNN) controller under the effect of surgical stimulation. The response of the proposed controller has a smaller settling time and a smaller overshoot compared with the T1FNN controller and the adaptive interval type-2 fuzzy logic controller (AIT2FLC). The values of the performance indices for the proposed controller are lower than those obtained for the T1FNN controller and the AIT2FLC. The IT2FNN controller is superior to the T1FNN controller for the handling of uncertain information due to the structure of type-2 fuzzy logic systems (FLSs), which are able to model and minimize the numerical and linguistic uncertainties associated with the inputs and outputs of the FLSs. Copyright © 2014 Elsevier B.V. All rights reserved.

  3. Introduction to Hardware Security

    Directory of Open Access Journals (Sweden)

    Yier Jin

    2015-10-01

    Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

  4. 'Unstructured Data' Practices in Polar Institutions and Networks: a Case Study with the Arctic Options Project

    Directory of Open Access Journals (Sweden)

    Paul Arthur Berkman

    2014-10-01

    Full Text Available Arctic Options: Holistic Integration for Arctic Coastal-Marine Sustainability is a new three-year research project to assess future infrastructure associated with the Arctic Ocean regarding: (1 natural and living environment; (2 built environment; (3 natural resource development; and (4 governance. For the assessments, Arctic Options will generate objective relational schema from numeric data as well as textual data. This paper will focus on the ‘long tail of smaller, heterogeneous, and often unstructured datasets’ that ‘usually receive minimal data management consideration’,as observed in the 2013 Communiqué from the International Forum on Polar Data Activities in Global Data Systems.

  5. Options for efficient use of social networks for small and medium-sized enterprises

    OpenAIRE

    Král, Marek

    2011-01-01

    This bachelor thesis concerns the problematic of social networks and their usage for marketing purposes. In theoretical part there are described tools of the most famous social site -- Facebook, that are usable for marketing purposes, as well as its advantages and disadvantages. In practical part there is analysed outdoor segment and suitable usage of social networks as Facebook. Furthermore analysis of electivity and current usefulness is done. In last practical part there are suggested and ...

  6. Delay/Disruption Tolerance Networking (DTN) Implementation and Utilization Options on the International Space Station

    Science.gov (United States)

    Holbrook, Mark; Pitts, Robert Lee; Gifford, Kevin K.; Jenkins, Andrew; Kuzminsky, Sebastian

    2010-01-01

    The International Space Station (ISS) is in an operational configuration and nearing final assembly. With its maturity and diverse payloads onboard, the opportunity exists to extend the orbital lab into a facility to exercise and demonstrate Delay/Disruption Tolerant Networking (DTN). DTN is an end-to-end network service providing communications through environments characterized by intermittent connectivity, variable delays, high bit error rates, asymmetric links and simplex links. The DTN protocols, also known as bundle protocols, provide a store-and-forward capability to accommodate end-to-end network services. Key capabilities of the bundling protocols include: the Ability to cope with intermittent connectivity, the Ability to take advantage of scheduled and opportunistic connectivity (in addition to always up connectivity), Custody Transfer, and end-to-end security. Colorado University at Boulder and the Huntsville Operational Support Center (HOSC) have been developing a DTN capability utilizing the Commercial Generic Bioprocessing Apparatus (CGBA) payload resources onboard the ISS, at the Boulder Payload Operations Center (POC) and at the HOSC. The DTN capability is in parallel with and is designed to augment current capabilities. The architecture consists of DTN endpoint nodes on the ISS and at the Boulder POC, and a DTN node at the HOSC. The DTN network is composed of two implementations; the Interplanetary Overlay Network (ION) and the open source DTN2 implementation. This paper presents the architecture, implementation, and lessons learned. By being able to handle the types of environments described above, the DTN technology will be instrumental in extending networks into deep space to support future missions to other planets and other solar system points of interest. Thus, this paper also discusses how this technology will be applicable to these types of deep space exploration missions.

  7. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  8. Gene regulatory networks reused to build novel traits: co-option of an eye-related gene regulatory network in eye-like organs and red wing patches on insect wings is suggested by optix expression.

    Science.gov (United States)

    Monteiro, Antónia

    2012-03-01

    Co-option of the eye developmental gene regulatory network may have led to the appearance of novel functional traits on the wings of flies and butterflies. The first trait is a recently described wing organ in a species of extinct midge resembling the outer layers of the midge's own compound eye. The second trait is red pigment patches on Heliconius butterfly wings connected to the expression of an eye selector gene, optix. These examples, as well as others, are discussed regarding the type of empirical evidence and burden of proof that have been used to infer gene network co-option underlying the origin of novel traits. A conceptual framework describing increasing confidence in inference of network co-option is proposed. Novel research directions to facilitate inference of network co-option are also highlighted, especially in cases where the pre-existent and novel traits do not resemble each other. Copyright © 2012 WILEY Periodicals, Inc.

  9. LHCb: Hardware Data Injector

    CERN Multimedia

    Delord, V; Neufeld, N

    2009-01-01

    The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions. A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data. These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system. The architecture, ...

  10. Improving Hardware Reusability: Software Defined Hardware

    Science.gov (United States)

    2017-03-01

    performance improvements over software, specialization is likely the future of hardware design. This trend will manifest in an increased demand for chip ...design methodologies is critical to meeting the incoming demand for chip diversity. Acknowledgements Research partially funded by DARPA Award Number...DARPA; and ASPIRE Lab industrial sponsors and affiliates Intel, Google, HPE, Huawei, LGE, Nokia, NVIDIA, Oracle, and Samsung. References [1

  11. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  12. GENI: Grid Hardware and Software

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  13. Quantitative Evaluation of Biologic Therapy Options for Psoriasis: A Systematic Review and Network Meta-Analysis.

    Science.gov (United States)

    Jabbar-Lopez, Zarif K; Yiu, Zenas Z N; Ward, Victoria; Exton, Lesley S; Mohd Mustapa, M Firouz; Samarasekera, Eleanor; Burden, A David; Murphy, Ruth; Owen, Caroline M; Parslew, Richard; Venning, Vanessa; Warren, Richard B; Smith, Catherine H

    2017-08-01

    Multiple biologic treatments are licensed for psoriasis. The lack of head-to-head randomized controlled trials makes choosing between them difficult for patients, clinicians, and guideline developers. To establish their relative efficacy and tolerability, we searched MEDLINE, PubMed, Embase, and Cochrane for randomized controlled trials of licensed biologic treatments for skin psoriasis. We performed a network meta-analysis to identify direct and indirect evidence comparing biologics with one another, methotrexate, or placebo. We combined this with hierarchical cluster analysis to consider multiple outcomes related to efficacy and tolerability in combination for each treatment. Study quality, heterogeneity, and inconsistency were evaluated. Direct comparisons from 41 randomized controlled trials (20,561 participants) were included. All included biologics were efficacious compared with placebo or methotrexate at 3-4 months. Overall, cluster analysis showed adalimumab, secukinumab, and ustekinumab were comparable in terms of high efficacy and tolerability. Ixekizumab and infliximab were differentiated by very high efficacy but poorer tolerability. The lack of longer term controlled data limited our analysis to short-term outcomes. Trial performance may not equate to real-world performance, and so results need to be considered alongside real-world, long-term safety and effectiveness data. These data suggest that it is possible to discriminate between biologics to inform clinical practice and decision making (PROSPERO 2015:CRD42015017538). Copyright © 2017 The Authors. Published by Elsevier Inc. All rights reserved.

  14. Hardware protection through obfuscation

    CERN Document Server

    Bhunia, Swarup; Tehranipoor, Mark

    2017-01-01

    This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

  15. Hardware removal - extremity

    Science.gov (United States)

    ... enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help fix a broken bone ... SW, Hotchkiss RN, Pederson WC, Kozin SH, Cohen MS, eds. Green's Operative Hand Surgery . 7th ed. Philadelphia, ...

  16. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  17. Hardware and Software Co-design: An Architecture Proposal for a Network-on-Chip Switch based on Bufferless Data Flow

    Directory of Open Access Journals (Sweden)

    S. Ortega-Cisneros

    2014-02-01

    Full Text Available The use of on chip networks as interconnection media for systems implemented in FPGAs is limited by the amount of logical resources necessary to deploy the network in the target device, and the time necessary to adjust the network parameters to achieve the performance goal for the system. In this paper we present a switch architecture, with data flow control based on circuit switching and aimed for on-chip networks with a Spidergon topology, which seeks to reduce the area occupied without severely affecting the overall network performance. As a result, we obtained a switch that requires only 114 slices in its most economic version on a Virtex 4-device. We also provide a performance profile, obtained by subjecting a network formed by these switches to different synthetic workloads within a simulator. This simulator was developed as part of the design flow of the switch, and it proves to be an essential tool for the test and validation process.

  18. NASA HUNCH Hardware

    Science.gov (United States)

    Hall, Nancy R.; Wagner, James; Phelps, Amanda

    2014-01-01

    What is NASA HUNCH? High School Students United with NASA to Create Hardware-HUNCH is an instructional partnership between NASA and educational institutions. This partnership benefits both NASA and students. NASA receives cost-effective hardware and soft goods, while students receive real-world hands-on experiences. The 2014-2015 was the 12th year of the HUNCH Program. NASA Glenn Research Center joined the program that already included the NASA Johnson Space Flight Center, Marshall Space Flight Center, Langley Research Center and Goddard Space Flight Center. The program included 76 schools in 24 states and NASA Glenn worked with the following five schools in the HUNCH Build to Print Hardware Program: Medina Career Center, Medina, OH; Cattaraugus Allegheny-BOCES, Olean, NY; Orleans Niagara-BOCES, Medina, NY; Apollo Career Center, Lima, OH; Romeo Engineering and Tech Center, Washington, MI. The schools built various parts of an International Space Station (ISS) middeck stowage locker and learned about manufacturing process and how best to build these components to NASA specifications. For the 2015-2016 school year the schools will be part of a larger group of schools building flight hardware consisting of 20 ISS middeck stowage lockers for the ISS Program. The HUNCH Program consists of: Build to Print Hardware; Build to Print Soft Goods; Design and Prototyping; Culinary Challenge; Implementation: Web Page and Video Production.

  19. CERN Neutrino Platform Hardware

    CERN Document Server

    Nelson, Kevin

    2017-01-01

    My summer research was broadly in CERN's neutrino platform hardware efforts. This project had two main components: detector assembly and data analysis work for ICARUS. Specifically, I worked on assembly for the ProtoDUNE project and monitored the safety of ICARUS as it was transported to Fermilab by analyzing the accelerometer data from its move.

  20. Design and Benchmarking of a Network-In-the-Loop Simulation for Use in a Hardware-In-the-Loop System

    Science.gov (United States)

    Aretskin-Hariton, Eliot; Thomas, George; Culley, Dennis; Kratz, Jonathan

    2017-01-01

    Distributed engine control (DEC) systems alter aircraft engine design constraints because of fundamental differences in the input and output communication between DEC and centralized control architectures. The change in the way communication is implemented may create new optimum engine-aircraft configurations. This paper continues the exploration of digital network communication by demonstrating a Network-In-the-Loop simulation at the NASA Glenn Research Center. This simulation incorporates a real-time network protocol, the Engine Area Distributed Interconnect Network Lite (EADIN Lite), with the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) software. The objective of this study is to assess digital control network impact to the control system. Performance is evaluated relative to a truth model for large transient maneuvers and a typical flight profile for commercial aircraft. Results show that a decrease in network bandwidth from 250 Kbps (sampling all sensors every time step) to 40 Kbps, resulted in very small differences in control system performance.

  1. Design and Benchmarking of a Network-In-the-Loop Simulation for Use in a Hardware-In-the-Loop System

    Science.gov (United States)

    Aretskin-Hariton, Eliot D.; Thomas, George Lindsey; Culley, Dennis E.; Kratz, Jonathan L.

    2017-01-01

    Distributed engine control (DEC) systems alter aircraft engine design constraints be- cause of fundamental differences in the input and output communication between DEC and centralized control architectures. The change in the way communication is implemented may create new optimum engine-aircraft configurations. This paper continues the exploration of digital network communication by demonstrating a Network-In-the-Loop simulation at the NASA Glenn Research Center. This simulation incorporates a real-time network protocol, the Engine Area Distributed Interconnect Network Lite (EADIN Lite), with the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) software. The objective of this study is to assess digital control network impact to the control system. Performance is evaluated relative to a truth model for large transient maneuvers and a typical flight profile for commercial aircraft. Results show that a decrease in network bandwidth from 250 Kbps (sampling all sensors every time step) to 40 Kbps, resulted in very small differences in control system performance.

  2. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  3. DCSP hardware maintenance system

    Energy Technology Data Exchange (ETDEWEB)

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  4. Hardware Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  5. Sterilization of space hardware.

    Science.gov (United States)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  6. Economic impact of syndesmosis hardware removal.

    Science.gov (United States)

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system

  7. Combining hardware and simulation for datacenter scaling studies

    DEFF Research Database (Denmark)

    Ruepp, Sarah Renée; Pilimon, Artur; Thrane, Jakob

    2017-01-01

    Datacenter networks are becoming crucial foundations for our information technology based society. However, commercial datacenter infrastructure is often unavailable to researchers for conducting experiments. In this work, we therefore elaborate on the possibility of combining commercial hardware...

  8. Rehabilitation Options

    Science.gov (United States)

    ... for e-updates Please leave this field empty Rehabilitation Options SHARE Home > Treatment and Care > Continuum of Care > Rehabilitation Options Listen Beginning the Healing Process After undergoing ...

  9. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  10. Foundations of hardware IP protection

    CERN Document Server

    Torres, Lionel

    2017-01-01

    This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

  11. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  12. The Software and Hardware of Macrophages: A Diversity of Options.

    Science.gov (United States)

    Kierdorf, Katrin; Dionne, Marc S

    2016-07-25

    Macrophages play important immune and homeostatic roles that depend on the ability to receive and interpret specific signals from environmental stimuli. Here we describe the different activation states these cells can exhibit in response to signals and how these states affect and can be affected by bacterial pathogens. Copyright © 2016 Elsevier Inc. All rights reserved.

  13. Space hardware microbial contamination

    Science.gov (United States)

    Baker, A.; Kern, R.; Mancinelli, R.; Venkateswaren, K.; Wainwright, N.

    Planetary Protection (PP) requirements imposed on unmanned planetary missions require that the spacecraft undergo rigorous bioload reduction prior to launch. The ability to quantitate bioburden on such spacecraft is dependent on developing new analytical methodologies that can be used to identify and trace biological contamination on flight hardware. The focus of new method development is to move forward and to augment the current spore analysis method which was first used on Viking. The ultimate goal of the new techniques is not to increase the cleanliness requirement currently levied on various missions, b ut instead to better understand the nature of the bioburden through the use of well-characterized standard methods. Subsequently an array of standard techniques is needed to provide various analytical methodologies that can be used to access bioburden, depending upon mission specifications. This poster will provide information on two workshops that have been held to review the status of the development of new quantitative techniques for determining the bioload on spacecraft at the time of launch. The purpose of the workshops was to review and revise NASA Standard Operation Procedure NPG:5340.1C "Microbiological Examination of Space Hardware and Associated Environments" to incorporate improvements in the procedure and to reflect current field practices. I addition the paneln reviewed the status of new analytical methods currently under study for planetary protection applications, defining expected research that would bring the individual methods to a point where they can be drafted for submittal to the NASA standard procedure process. The poster will highlight changes to current standard procedures as well as review the status of new methods currently being studied. Methods included Polymerase Chain Reaction (PCR), Epifluorescence Techniques, Live/Dead Cell Analysis, Capillary Electrophoresis of Amino Acids and Ionic Contaminants, High Sensitivity Assay for

  14. Compact hardware liquid state machines on FPGA for real-time speech recognition.

    Science.gov (United States)

    Schrauwen, Benjamin; D'Haene, Michiel; Verstraeten, David; Campenhout, Jan Van

    2008-01-01

    Hardware implementations of Spiking Neural Networks are numerous because they are well suited for implementation in digital and analog hardware, and outperform classic neural networks. This work presents an application driven digital hardware exploration where we implement real-time, isolated digit speech recognition using a Liquid State Machine. The Liquid State Machine is a recurrent neural network of spiking neurons where only the output layer is trained. First we test two existing hardware architectures which we improve and extend, but that appears to be too fast and thus area consuming for this application. Next, we present a scalable, serialized architecture that allows a very compact implementation of spiking neural networks that is still fast enough for real-time processing. All architectures support leaky integrate-and-fire membranes with exponential synaptic models. This work shows that there is actually a large hardware design space of Spiking Neural Network hardware that can be explored. Existing architectures have only spanned part of it.

  15. Supplementing online surveys with a mailed option to reduce bias and improve response rate: the National Dental Practice-Based Research Network.

    Science.gov (United States)

    Funkhouser, Ellen; Fellows, Jeffrey L; Gordan, Valeria V; Rindal, D Brad; Foy, Patrick J; Gilbert, Gregg H

    2014-01-01

    Dentists in the National Dental Practice-Based Research Network are offered online and mail options for most questionnaire studies. We sought to quantify differences a) in characteristics of dentists who completed a questionnaire online as compared with those who completed a mail option offered to online nonresponders and b) in prevalence estimates for certain practice characteristics. Invitation letters to participants provided an identification number and log-in code with which to complete the online survey. Nonrespondents received a reminder letter after the fourth week, and after an additional 4-week period, a final reminder was sent, along with a paper questionnaire version, allowing completion online or by paper. Of 632 US dentists who completed the survey, 84 (13 percent) used the paper version. Completion by paper was more common among males, older dentists, and those in general practice (Psurvey using the paper-mail version than among those who completed it online; these differences remained significant in models adjusted for gender, age, and practice type. Even in an era of increasingly electronic communication by dentists, not including a paper option when conducting surveys can result in overestimation of the prevalence of key dental practice characteristics. © 2014 American Association of Public Health Dentistry.

  16. Hardware Removal in Craniomaxillofacial Trauma

    Science.gov (United States)

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  17. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...

  18. Secure coupling of hardware components

    NARCIS (Netherlands)

    Hoepman, J.H.; Joosten, H.J.M.; Knobbe, J.W.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and,

  19. The hardware accelerator array for logic simulation

    Energy Technology Data Exchange (ETDEWEB)

    Hansen, N H [Washington State Univ., Pullman, WA (USA)

    1991-05-01

    Hardware acceleration exploits the parallelism inherent in large circuit simulations to achieve significant increases in performance. Simulation accelerators have been developed based on the compiled code algorithm or the event-driven algorithm. The greater flexibility of the event-driven algorithm has resulted in several important developments in hardware acceleration architecture. Some popular commercial products have been developed based on the event-driven algorithm and data-flow architectures. Conventional data-flow architectures require complex switching networks to distribute operands among processing elements resulting in considerable overhead. An accelerator array architecture based on a nearest-neighbor communication has been developed in this thesis. The design is simulated in detail at the behavioral level. Its performance is evaluated and shown to be superior to that of a conventional data-flow accelerator. 14 refs., 48 figs., 5 tabs.

  20. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  1. Open source hardware solutions for low-cost, do-it-yourself environmental monitoring, citizen science, and STEM education

    Science.gov (United States)

    Hicks, S. D.; Aufdenkampe, A. K.; Horsburgh, J. S.; Arscott, D. B.; Muenz, T.; Bressler, D. W.

    2016-12-01

    The explosion in DIY open-source hardware and software has resulted in the development of affordable and accessible technologies, like drones and weather stations, that can greatly assist the general public in monitoring environmental health and its degradation. It is widely recognized that education and support of audiences in pursuit of STEM literacy and the application of emerging technologies is a challenge for the future of citizen science and for preparing high school graduates to be actively engaged in environmental stewardship. It is also clear that detecting environmental change/degradation over time and space will be greatly enhanced with expanded use of networked, remote monitoring technologies by watershed organizations and citizen scientists if data collection and reporting are properly carried out and curated. However, there are few focused efforts to link citizen scientists and school programs with these emerging tools. We have started a multi-year program to develop hardware and teaching materials for training students and citizen scientists about the use of open source hardware in environmental monitoring. Scientists and educators around the world have started building their own dataloggers and devices using a variety of boards based on open source electronics. This new hardware is now providing researchers with an inexpensive alternative to commercial data logging and transmission hardware. We will present a variety of hardware solutions using the Arduino-compatible EnviroDIY Mayfly board (http://envirodiy.org/mayfly) that can be used to build and deploy a rugged environmental monitoring station using a wide variety of sensors and options, giving the users a fully customizable device for making measurements almost anywhere. A database and visualization system is being developed that will allow the users to view and manage the data their devices are collecting. We will also present our plan for developing curricula and leading workshops to various

  2. Business and regulation of access networks of new generation. an approximation to the Spanish case using real options; Negocio y regulacion de las redes de acceso de nueva generacion. Aproximacion al caso espanol aplicando opciones reales

    Energy Technology Data Exchange (ETDEWEB)

    Gallardo Olmedo, F.; Perez Amaral, T.

    2010-07-01

    Telecommunications carriers are deploying the so called New Generation Access (NGA) networks. These networks consist in substituting the last part of the network (the one that ends in the premises of the client) with optical fiber. This part of the network used to be made of copper. The investments in NGA imply considerable risks but can also constitute an impulse for other sectors. This research proposes a method for the evaluation of these investments including the implied real options. We also consider the regulatory implications of the obligations of renting the network to competitors. (Author) 22 refs.

  3. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  4. Hardware for dynamic quantum computing.

    Science.gov (United States)

    Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

    2017-10-01

    We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

  5. Hardware for dynamic quantum computing

    Science.gov (United States)

    Ryan, Colm A.; Johnson, Blake R.; Ristè, Diego; Donovan, Brian; Ohki, Thomas A.

    2017-10-01

    We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

  6. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  7. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  8. Hardware and Software Integration to Support Real-Time Space-Link Emulation

    Science.gov (United States)

    Murawski, Robert; Bhasin, Kul; Bittner, David

    2012-01-01

    Prior to operational use, communications hardware and software must be thoroughly tested and verified. In space-link communications, field testing equipment can be prohibitively expensive and cannot test to non-ideal situations. In this paper, we show how software and hardware emulation tools can be used to accurately model the characteristics of a satellite communication channel in a lab environment. We describe some of the challenges associated with developing an emulation lab and present results to demonstrate the channel modeling. We then show how network emulation software can be used to extend a hardware emulation model without requiring additional network and channel simulation hardware.

  9. Hardware and Software Integration to Support Real-Time Space Link Emulation

    Science.gov (United States)

    Murawski, Robert; Bhasin, Kul; Bittner, David; Sweet, Aaron; Coulter, Rachel; Schwab, Devin

    2012-01-01

    Prior to operational use, communications hardware and software must be thoroughly tested and verified. In space-link communications, field testing equipment can be prohibitively expensive and cannot test to non-ideal situations. In this paper, we show how software and hardware emulation tools can be used to accurately model the characteristics of a satellite communication channel in a lab environment. We describe some of the challenges associated with developing an emulation lab and present results to demonstrate the channel modeling. We then show how network emulation software can be used to extend a hardware emulation model without requiring additional network and channel simulation hardware.

  10. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  11. 16 CFR 1508.6 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the hardware's...

  12. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  13. Exercising options

    Science.gov (United States)

    Carlowicz, Michael

    In a recent speech to graduates of the College of Computer, Mathematical, and Physical Sciences at the University of Maryland, Anne Petersen, deputy director of the National Science Foundation, encouraged a new generation of scientists to embrace opportunity and choice, and to use their scientific training as an employment credential, not a limit. In her May 23 commencement address, Petersen exhorted students to view their freshly minted diplomas as tickets to a broad and diverse job market, not just one-way trips to the laboratory.“Looking for the options and alternatives open to us—and creating options for ourselves where they are not apparent—can give us a sense of direction and volition that enriches our lives immensely…

  14. Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Andreas Stöckel

    2017-08-01

    Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

  15. Hardware-Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  16. The principles of computer hardware

    CERN Document Server

    Clements, Alan

    2000-01-01

    Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

  17. Understanding Thermal Convection Effects of Venus Surface Atmosphere on the Design and Performance of Venus Mission Hardware

    Science.gov (United States)

    Pandey, S. P.

    2017-05-01

    Work focuses on transient effects of thermal convection in Venus surface atmosphere on exposed mission hardware. Review of accurate and efficient state equation options for CFD modeling is presented. Convective heat transfer experiment plan presented.

  18. W-026 acceptance test report plant control system hardware (submittal {number_sign} 220.C)

    Energy Technology Data Exchange (ETDEWEB)

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP1 Plant Control System Hardware was conducted throughout the construction of WRAPI with the final testing on the Process Area hardware being completed in November 1996. The hardware tests were broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DMS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document contains a completed copy of each of the hardware tests along with the applicable test logs and completed test exception reports.

  19. W-026 acceptance test plan plant control system hardware (submittal {number_sign} 216)

    Energy Technology Data Exchange (ETDEWEB)

    Watson, T.L., Fluor Daniel Hanford

    1997-02-14

    Acceptance Testing of the WRAP 1 Plant Control System Hardware will be conducted throughout the construction of WRAP I with the final testing on the Process Area hardware being completed in November 1996. The hardware tests will be broken out by the following functional areas; Local Control Units, Operator Control Stations in the WRAP Control Room, DMS Server, PCS Server, Operator Interface Units, printers, DNS terminals, WRAP Local Area Network/Communications, and bar code equipment. This document will contain completed copies of each of the hardware tests along with the applicable test logs and completed test exception reports.

  20. Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

    Science.gov (United States)

    Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

    2000-01-01

    The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

  1. Tuple spaces in hardware for accelerated implicit routing

    Energy Technology Data Exchange (ETDEWEB)

    Baker, Zachary Kent [Los Alamos National Laboratory; Tripp, Justin [Los Alamos National Laboratory

    2010-12-01

    Organizing and optimizing data objects on networks with support for data migration and failing nodes is a complicated problem to handle as systems grow. The goal of this work is to demonstrate that high levels of speedup can be achieved by moving responsibility for finding, fetching, and staging data into an FPGA-based network card. We present a system for implicit routing of data via FPGA-based network cards. In this system, data structures are requested by name, and the network of FPGAs finds the data within the network and relays the structure to the requester. This is acheived through successive examination of hardware hash tables implemented in the FPGA. By avoiding software stacks between nodes, the data is quickly fetched entirely through FPGA-FPGA interaction. The performance of this system is orders of magnitude faster than software implementations due to the improved speed of the hash tables and lowered latency between the network nodes.

  2. Hardware and software reliability estimation using simulations

    Science.gov (United States)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  3. Hardware complications in oromandibular defects: Comparing scapular and fibular based free flap reconstructions.

    Science.gov (United States)

    Tsang, Gordon F Z; Zhang, Han; Yao, Christopher; Kolarski, Mirko; Gullane, Patrick J; Irish, Jonathan C; Brown, Dale H; Chepeha, Douglas B; Goldstein, David P; Gilbert, Ralph W; de Almeida, John R

    2017-08-01

    Despite improvements in surgical technique and technology, hardware complications occur relatively frequently. This study analyzes hardware complications in patients undergoing oromandibular reconstruction using scapular (SFF) or fibular (FFF) free flaps. Retrospective data for 178 patients was obtained (1999-2014) at University Hospital Network (Toronto, Canada). Univariable and multivariable analyses were performed to identify risk factors for hardware complications. Patients with FFF reconstruction (n=129) had significantly more hardware complications than those with SFF (n=49) (16% vs. 2%;p=0.01). Surgical site infection (SSI) (OR=7.05; phardware complications on univariable analysis. Flap type (OR=0.12; p=0.04) was an independent predictor of plate complication after adjusting for SSI. A subgroup analysis suggested a trend towards fewer hardware complications with SFF stratified by mandibular defect type. Scapular free flaps are associated with a lower rate of hardware-related complications in oromandibular reconstruction. Copyright © 2017 Elsevier Ltd. All rights reserved.

  4. The reconstructive management of hardware-related scalp erosion in deep brain stimulation for Parkinson disease.

    Science.gov (United States)

    Gómez, Raúl; Hontanilla, Bernardo

    2014-09-01

    The presence of foreign material in deep brain stimulation is a risk factor for infection, and hardware-related pressure under the scalp may cause skin erosion. The aim of this article is to present our experience in the coverage of scalp in relation to underlying hardware. We analyzed 21 patients with Parkinson disease who had undergone deep brain stimulation surgery and developed scalp erosion with hardware exposition during follow-up. Nine patients were programmed for a scalp rotation flap, whereas free tisue transfer was performed in the rest of the patients. Minimum follow-up was 2 years. A hardware-related ulcer appeared in 5 of 9 rotation flap patients. No ulceration or major complications were observed in free flap patients. Free flaps are probably the best option for stable coverage in hardware-related scalp erosion with a high rate of success.

  5. 16 CFR 1509.7 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall be...

  6. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  7. Hardware complications in scoliosis surgery

    Energy Technology Data Exchange (ETDEWEB)

    Bagchi, Kaushik; Mohaideen, Ahamed [Department of Orthopaedic Surgery and Musculoskeletal Services, Maimonides Medical Center, Brooklyn, NY (United States); Thomson, Jeffrey D. [Connecticut Children' s Medical Center, Department of Orthopaedics, Hartford, CT (United States); Foley, Christopher L. [Department of Radiology, Connecticut Children' s Medical Center, Hartford, Connecticut (United States)

    2002-07-01

    Background: Scoliosis surgery has undergone a dramatic evolution over the past 20 years with the advent of new surgical techniques and sophisticated instrumentation. Surgeons have realized scoliosis is a complex multiplanar deformity that requires thorough knowledge of spinal anatomy and pathophysiology in order to manage patients afflicted by it. Nonoperative modalities such as bracing and casting still play roles in the treatment of scoliosis; however, it is the operative treatment that has revolutionized the treatment of this deformity that affects millions worldwide. As part of the evolution of scoliosis surgery, newer implants have resulted in improved outcomes with respect to deformity correction, reliability of fixation, and paucity of complications. Each technique and implant has its own set of unique complications, and the surgeon must appreciate these when planning surgery. Materials and methods: Various surgical techniques and types of instrumentation typically used in scoliosis surgery are briefly discussed. Though scoliosis surgery is associated with a wide variety of complications, only those that directly involve the hardware are discussed. The current literature is reviewed and several illustrative cases of patients treated for scoliosis at the Connecticut Children's Medical Center and the Newington Children's Hospital in Connecticut are briefly presented. Conclusion: Spine surgeons and radiologists should be familiar with the different types of instrumentation in the treatment of scoliosis. Furthermore, they should recognize the clinical and roentgenographic signs of hardware failure as part of prompt and effective treatment of such complications. (orig.)

  8. Hardware and Software Interfacing at New Mexico Geochronology Research Laboratory: Distributed Control Using Pychron and RemoteControlServer.cs

    Science.gov (United States)

    McIntosh, W. C.; Ross, J. I.

    2012-12-01

    We developed a system for interfacing existing hardware and software to two new Thermo Scientific Argus VI mass spectrometers and three Photon Machines Fusions laser systems at New Mexico Geochronology Research Laboratory. NMGRL's upgrade to the new analytical equipment required the design and implementation of a software ecosystem that allows seamless communication between various software and hardware components. Based on past experience and initial testing we choose to pursue a "Fully Distributed Control" model. In this model, hardware is compartmentalized and controlled by customized software running on individual computers. Each computer is connected to a Local Area Network (LAN) facilitating inter-process communication using TCP or UDP Internet Protocols. Two other options for interfacing are 1) Single Control, in which all hardware is controlled by a single application on a single computer and 2), Partial Distributed Control, in which the mass spectrometer is controlled directly by Thermo Scientific's Qtegra and all other hardware is controlled by a separate application. The "Fully Distributed Control" model offers the most efficient use of software resources, leveraging our in-house laboratory software with proprietary third-party applications, such as Qtegra and Mass Spec. Two software products resulted from our efforts. 1) Pychron, a configurable and extensible package for hardware control, data acquisition and preprocessing, and 2) RemoteControlServer.cs, a C# script for Thermo's Qtegra software that implements a TCP/UDP command server. Pychron is written in python and uses standard well-established libraries such as, Numpy, Scipy, and Enthought ETS. Pychron is flexible and extensible, encouraging experimentation and rapid development of new features. A project page for Pychron is located at http://code.google.com/p/arlab, featuring an issue tracker and a Version Control System (Mercurial). RemoteControlServer.cs is a simple socket server that listens

  9. Software and Hardware for Suborbital Telepresence: UAVs on the Web

    Science.gov (United States)

    Sorenson, C. E.; Freudinger, L. C.; Yarbrough, S. K.; Jennison, C. D.; Miller, M. J.; Friets, E. M.; Blakeslee, R. J.; Mach, D. M.; Bateman, M. G.; Bailey, J. C.; Hall, J. M.

    2005-12-01

    A NASA Dryden project creating prototype sensor web tools has resulted in software and hardware for implementing network telemetry, telepresence, and other data system functions for platforms including UAVs. The Research Environment for Vehicle-Embedded Analysis on Linux (REVEAL) software is a self-configuring/verifying/documenting framework for realtime embedded and distributed data systems based on open standards XML. With interfaces for instruments, avionics, and networking, using small PC/104 hardware with one or more Iridium modems, REVEAL systems are well suited to long endurance UAVs. These systems serve as a telemetry and communications gateway for internet-based experimenters. REVEAL systems also provide traditional Earth Science platform data system services, configured by and for each experimenter in a secure manner. On the ground segment, buffering middleware enables efficient data distribution across the internet. The innovative REVEAL architecture and its use by experimenters on recent missions using NASA's ER-2 and General Atomics Altair aircraft is described.

  10. Imaging of current spinal hardware: lumbar spine.

    Science.gov (United States)

    Ha, Alice S; Petscavage-Thomas, Jonelle M

    2014-09-01

    The purposes of this article are to review the indications for and the materials and designs of hardware more commonly used in the lumbar spine; to discuss alternatives for each of the types of hardware; to review normal postoperative imaging findings; to describe the appropriateness of different imaging modalities for postoperative evaluation; and to show examples of hardware complications. Stabilization and fusion of the lumbar spine with intervertebral disk replacement, artificial ligaments, spinous process distraction devices, plate-and-rod systems, dynamic posterior fusion devices, and newer types of material incorporation are increasingly more common in contemporary surgical practice. These spinal hardware devices will be seen more often in radiology practice. Successful postoperative radiologic evaluation of this spinal hardware necessitates an understanding of fundamental hardware design, physiologic objectives, normal postoperative imaging appearances, and unique complications. Radiologists may have little training and experience with the new and modified types of hardware used in the lumbar spine.

  11. Louisiana Speaks Transportation Option C Roadway Improvements, UTM Zone 15N NAD 83, Louisiana Recovery Authority (2007), [louisiana_speaks_transportation_option_c_roadway_improvements

    Data.gov (United States)

    Louisiana Geographic Information Center — This GIS shapefile data illustrates the regional roadways included in the Louisiana Speaks community growth option of compact development (Option C). This network...

  12. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Madsen, Jan; Knudsen, Peter Voigt

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search...

  13. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search....

  14. Neurostimulation options for failed back surgery syndrome: The need for rational and objective measurements. Proposal of an international clinical network using an integrated database and health economic analysis: the PROBACK network.

    Science.gov (United States)

    Rigoard, P; Slavin, K

    2015-03-01

    In the context of failed back surgery syndrome (FBSS) treatment, the current practice in neurostimulation varies from center-to-center and most clinical decisions are based on an individual diagnosis. Neurostimulation evaluation tools and pain relief assessment are of major concern, as they now constitute one of the main biases of clinical trials. Moreover, the proliferation of technological devices, in a fertile and unsatisfied market, fosters and only furthers the confusion. There are three options available to apply scientific debates to our daily neurostimulation practice: intentional ignorance, standardized evidence-based practice or alternative data mining approach. In view of the impossibility of conducting multiple randomized clinical trials comparing various devices, one by one, the proposed concept would be to redefine the indications and the respective roles of the various spinal cord and peripheral nerve stimulation devices with large-scale computational modeling/data mining approach, by conducting a multicenter prospective database registry, supported by a clinician's global network called "PROBACK". We chose to specifically analyze 6 parameters: device coverage performance/coverage selectivity/persistence of the long-term electrical response (technical criteria) and comparative mapping of patient pain relief/persistence of the long-term clinical response/safety and complications occurrence (clinical criteria). Two types of analysis will be performed: immediate analysis (including cost analysis) and computational analysis, i.e. demonstration of the robustness of certain correlations of variables, in order to extract response predictors. By creating an international prospective database, the purpose of the PROBACK project was to set up a process of extraction and comparative analysis of data derived from the selection, implantation and follow-up of FBSS patients candidates for implanted neurostimulation. This evaluation strategy should help to change

  15. Projecto de hardware digital orientado por objectos

    OpenAIRE

    Fernandes, João M.; Machado, Ricardo J.

    1997-01-01

    Os limites entre os domínios do software e do hardware são cada vez mais ténues, pelo que técnicas inicialmente experimentadas no software têm vindo a ser gradualmente aplicadas no hardware. Este artigo pretende descrever o estado actual da utilização da tecnologia de programação orientada por objectos no projecto de hardware digital. São analisadas as vantagens e implicações quando se introduzem conceitos ligados à tecnologia orientada por objectos em projectos de hardware e é apresent...

  16. Open-source hardware for medical devices.

    Science.gov (United States)

    Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

    2016-04-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

  17. Thermal Hardware for the Thermal Analyst

    Science.gov (United States)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  18. Hardware platform for multiple mobile robots

    Science.gov (United States)

    Parzhuber, Otto; Dolinsky, D.

    2004-12-01

    This work is concerned with software and communications architectures that might facilitate the operation of several mobile robots. The vehicles should be remotely piloted or tele-operated via a wireless link between the operator and the vehicles. The wireless link will carry control commands from the operator to the vehicle, telemetry data from the vehicle back to the operator and frequently also a real-time video stream from an on board camera. For autonomous driving the link will carry commands and data between the vehicles. For this purpose we have developed a hardware platform which consists of a powerful microprocessor, different sensors, stereo- camera and Wireless Local Area Network (WLAN) for communication. The adoption of IEEE802.11 standard for the physical and access layer protocols allow a straightforward integration with the internet protocols TCP/IP. For the inspection of the environment the robots are equipped with a wide variety of sensors like ultrasonic, infrared proximity sensors and a small inertial measurement unit. Stereo cameras give the feasibility of the detection of obstacles, measurement of distance and creation of a map of the room.

  19. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    Science.gov (United States)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  20. TileCal ROD Hardware and Software Requirements

    CERN Document Server

    Castelo, J; Cuenca, C; Ferrer, A; Fullana, E; Higón, E; Iglesias, C; Munar, A; Poveda, J; Ruiz-Martínez, A; Salvachúa, B; Solans, C; Valls, J A

    2005-01-01

    In this paper we present the specific hardware and firmware requirements and modifications to operate the Liquid Argon Calorimeter (LiArg) ROD motherboard in the Hadronic Tile Calorimeter (TileCal) environment. Although the use of the board is similar for both calorimeters there are still some differences in the operation of the front-end associated to both detectors which make the use of the same board incompatible. We review the evolution of the design of the ROD from the early prototype stages (ROD based on commercial and Demonstrator boards) to the production phases (ROD final board based on the LiArg design), with emphasis on the different operation modes for the TileCal detector. We start with a short review of the TileCal ROD system functionality and then we detail the different ROD hardware requirements for options, the baseline (ROD Demo board) and the final (ROD final high density board). We also summarize the performance parameters of the ROD motherboard based on the final high density option and s...

  1. Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

    NARCIS (Netherlands)

    Pham-Quoc Cuong, P.

    2015-01-01

    Heterogeneous multicore systems are becoming increasingly important as the need for computation power grows, especially when we are entering into the big data era. As one of the main trends in heterogeneous multicore, hardware accelerator systems provide application specific hardware circuits and

  2. Relational Algebra as formalism for Hardware Design

    NARCIS (Netherlands)

    ten Berg, A.J.W.M.; ten Berg, A.J.W.M.; Huijs, C.; Krol, Th.

    1993-01-01

    This paper introduces relational algebra as an elegant formalism to describe hardware behaviour. Hardware behaviour is modelled by functions that are represented by sets of tables. Relational algebra, developed for designing large and consistent databases is capable to operate on sets of tables and

  3. Arthroscopy combined with hardware removal for chronic pain after ankle fracture.

    Science.gov (United States)

    Kim, Hyong-Nyun; Park, Yoo-Jung; Kim, Gab-Lae; Park, Yong-Wook

    2013-06-01

    The purpose of this study was to evaluate the effectiveness of arthroscopy combined with hardware removal for chronic pain after satisfactory healing of an ankle fracture. We hypothesized that combining hardware removal with arthroscopy for the intra-articular pathology would improve residual complaints more so than hardware removal alone. The outcomes of the 53 young male patients with chronic pain after healed ankle fracture treated with two different therapeutic plans: (1) conservative treatment after hardware removal (group A) and (2) arthroscopic intervention with hardware removal (group B) were prospectively studied. Patients were reviewed preoperatively and 6 and 12 months postoperatively using American Foot and Ankle Society (AOFAS) scale. Median AOFAS scores improved from 74 (66-80) points to 76 (73-92) points in group A and from 75 (64-80) points to 85 (72-100) points in group B, and this improvement was significantly higher for patients in group B (p = 0.001). This study supports the notion that when there is a definite diagnosis such as loose body, bony impingement, or anterolateral soft-tissue impingement causing chronic pain after healed ankle fracture, arthroscopic treatment with hardware removal is a better treatment option than hardware removal and conservative treatment.

  4. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip...... communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  5. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  6. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    Science.gov (United States)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  7. Comparative Modal Analysis of Sieve Hardware Designs

    Science.gov (United States)

    Thompson, Nathaniel

    2012-01-01

    The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

  8. Perforating the atretic pulmonary valve with CTO hardware: Technical aspects.

    Science.gov (United States)

    Patil, Nilkanth C; Saxena, Anita; Gupta, Saurabh K; Juneja, Rajnish; Mishra, Sundeep; Ramakrishnan, Sivasubramanian; Kothari, Shyam S

    2016-11-01

    To review the success and technical aspects of pulmonary valve (PV) perforation using chronic total occlusion (CTO) hardware in patients with pulmonary atresia and intact ventricular septum (PA-IVS). Interventional therapy is possible in selected patients with PA-IVS. Among the various interventional options available, radiofrequency and laser assisted perforation may be more successful, but require expertise and may be substantially costly. We describe the technique of mechanical catheter PV perforation using currently available coronary hardware meant for coronary CTO in nine cases with PA-IVS. After complete echocardiographic evaluation and informed parental consent was obtained, patients were electively intubated, mechanically ventilated, adequately heparinized and were placed on intravenous prostaglandin infusion. Basic steps involved were-localizing the atretic segment and accomplishing coaxial alignment of catheters using biplane fluoroscopy, crossing the atretic segment with the soft end of perforating guidewire, stabilizing the assembly and performing graded balloon dilatation with the balloon size never exceeding 130% of pulmonary annulus diameter. For crossing the atretic PV, a retrograde approach was used in one patient where the antegrade approach was not possible. The procedure was successful in 8/9 cases (89%). Valve opening was achieved in all eight patients with immediate fall in right ventricular (RV) systolic pressures. One neonate died following surgery after catheter induced RV perforation. All surviving cases were discharged from the hospital in good general condition with no evidence of heart failure and a room air oxygen saturation of >85%. No patient required an additional pulmonary irrigation procedure. With appropriate patient and hardware selection, PV perforation using readily available coronary hardware is feasible in PA-IVS. © 2014 Wiley Periodicals, Inc. © 2014 Wiley Periodicals, Inc.

  9. Optimal exploitation of client texture hardware capabilities on a client-server remote visualization framework

    OpenAIRE

    Boada, Imma; Navazo Álvaro, Isabel

    2003-01-01

    Given a client-server communication network, with workstations equipped with 3D texture hardware, we propose a technique that guarantees the optimal use of the client texture hardware. We consider the best representation of a data model that has to be rendered on the client side as the one that requires the minimal texture space while preserving image quality. Taking into account this consideration the basis of the proposed technique is the selection of the best multiresolution representat...

  10. The evolvability of programmable hardware

    Science.gov (United States)

    Raman, Karthik; Wagner, Andreas

    2011-01-01

    In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 1045 logic circuits (‘genotypes’) and 1019 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry. PMID:20534598

  11. Stability and Accuracy Considerations in the Design and Implementation of Wind Turbine Power Hardware in the Loop Platform

    DEFF Research Database (Denmark)

    Luo, Kui; Shi, Wenhui; Chi, Yongning

    2017-01-01

    There is increasing interest in the evaluation of wind turbine control capabilities for providing grid support. Power hardware in the loop (PHIL) simulation is an advanced method that can be used for studying the interaction of hardware with the power network, as the scaled-down actual wind turbine...

  12. Use of CCSDS Packets Over SpaceWire to Control Hardware

    Science.gov (United States)

    Haddad, Omar; Blau, Michael; Haghani, Noosha; Yuknis, William; Albaijes, Dennis

    2012-01-01

    For the Lunar Reconnaissance Orbiter, the Command and Data Handling subsystem consisted of several electronic hardware assemblies that were connected with SpaceWire serial links. Electronic hardware would be commanded/controlled and telemetry data was obtained using the SpaceWire links. Prior art focused on parallel data buses and other types of serial buses, which were not compatible with the SpaceWire and the core flight executive (CFE) software bus. This innovation applies to anything that utilizes both SpaceWire networks and the CFE software. The CCSDS (Consultative Committee for Space Data Systems) packet contains predetermined values in its payload fields that electronic hardware attached at the terminus of the SpaceWire node would decode, interpret, and execute. The hardware s interpretation of the packet data would enable the hardware to change its state/configuration (command) or generate status (telemetry). The primary purpose is to provide an interface that is compatible with the hardware and the CFE software bus. By specifying the format of the CCSDS packet, it is possible to specify how the resulting hardware is to be built (in terms of digital logic) that results in a hardware design that can be controlled by the CFE software bus in the final application

  13. Hardware removal after osseous free flap reconstruction.

    Science.gov (United States)

    Day, Kristine E; Desmond, Renee; Magnuson, J Scott; Carroll, William R; Rosenthal, Eben L

    2014-01-01

    Identifying risk factors for hardware removal in patients undergoing mandibular reconstruction with vascularized osseous free flaps remains a challenge. The purpose of this study is to identify potential risk factors, including osteocutaneous radial forearm versus fibular flap, for need for removal and to describe the fate of implanted hardware. Case series with chart review Setting Academic tertiary care medical center. Two hundred thirteen patients undergoing 227 vascularized osseous mandibular reconstructions between the years 2004 and 2012. Data were compiled through a manual chart review, and patients incurring hardware removals were identified. Thirty-four of 213 evaluable vascularized osseous free flaps (16%) underwent surgical removal of hardware. The average length of time to removal was 16.2 months (median 10 months), with the majority of removals occurring within the first year. Osteocutaneous radial forearm free flaps (OCRFFF) incurred a slightly higher percentage of hardware removals (9.9%) compared to fibula flaps (6.1%). Partial removal was performed in 8 of 34 cases, and approximately 38% of these required additional surgery for removal. Hardware removal was associated with continued tobacco use after mandibular reconstruction (P = .03). Removal of the supporting hardware most commonly occurs from infection or exposure in the first year. In the majority of cases the bone is well healed and the problem resolves with removal.

  14. Hardware and Software Implementations of Prim’s Algorithm for Efficient Minimum Spanning Tree Computation

    OpenAIRE

    Mariano, Artur; Lee, Dongwook; Gerstlauer, Andreas; Chiou, Derek

    2013-01-01

    Part 4: Performance Analysis; International audience; Minimum spanning tree (MST) problems play an important role in many networking applications, such as routing and network planning. In many cases, such as wireless ad-hoc networks, this requires efficient high-performance and low-power implementations that can run at regular intervals in real time on embedded platforms. In this paper, we study custom software and hardware realizations of one common algorithm for MST computations, Prim’s alg...

  15. Conceptual Design Approach to Implementing Hardware-based Security Controls in Data Communication Systems

    Energy Technology Data Exchange (ETDEWEB)

    Ibrahim, Ahmad Salah; Jung, Jaecheon [KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

    2016-10-15

    In the Korean Advanced Power Reactor (APR1400), safety control systems network is electrically isolated and physically separated from non-safety systems data network. Unidirectional gateways, include data diode fiber-optic cabling and computer-based servers, transmit the plant safety critical parameters to the main control room (MCR) for control and monitoring processes. The data transmission is only one-way from safety to non-safety. Reverse communication is blocked so that safety systems network is protected from potential cyberattacks or intrusions from non-safety side. Most of commercials off-the-shelf (COTS) security devices are software-based solutions that require operating systems and processors to perform its functions. Field Programmable Gate Arrays (FPGAs) offer digital hardware solutions to implement security controls such as data packet filtering and deep data packet inspection. This paper presents a conceptual design to implement hardware-based network security controls for maintaining the availability of gateway servers. A conceptual design of hardware-based network security controls was discussed in this paper. The proposed design is aiming at utilizing the hardware-based capabilities of FPGAs together with filtering and DPI functions of COTS software-based firewalls and intrusion detection and prevention systems (IDPS). The proposed design implemented a network security perimeter between the DCN-I zone and gateway servers zone. Security control functions are to protect the gateway servers from potential DoS attacks that could affect the data availability and integrity.

  16. 2D neural hardware versus 3D biological ones

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

  17. Efficient Hardware Implementation of the Lightweight Block Encryption Algorithm LEA

    Directory of Open Access Journals (Sweden)

    Donggeon Lee

    2014-01-01

    Full Text Available Recently, due to the advent of resource-constrained trends, such as smartphones and smart devices, the computing environment is changing. Because our daily life is deeply intertwined with ubiquitous networks, the importance of security is growing. A lightweight encryption algorithm is essential for secure communication between these kinds of resource-constrained devices, and many researchers have been investigating this field. Recently, a lightweight block cipher called LEA was proposed. LEA was originally targeted for efficient implementation on microprocessors, as it is fast when implemented in software and furthermore, it has a small memory footprint. To reflect on recent technology, all required calculations utilize 32-bit wide operations. In addition, the algorithm is comprised of not complex S-Box-like structures but simple Addition, Rotation, and XOR operations. To the best of our knowledge, this paper is the first report on a comprehensive hardware implementation of LEA. We present various hardware structures and their implementation results according to key sizes. Even though LEA was originally targeted at software efficiency, it also shows high efficiency when implemented as hardware.

  18. A Hardware Filesystem Implementation with Multidisk Support

    National Research Council Canada - National Science Library

    Mendon, Ashwin A; Schmidt, Andrew G; Sass, Ron

    2009-01-01

    .... This article describes one such innovation: a filesystem implemented in hardware. This has the potential of improving the performance of data-intensive applications by connecting secondary storage directly to FPGA compute accelerators...

  19. Hardware device binding and mutual authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  20. Hardware-in-the-Loop Testing

    Data.gov (United States)

    Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

  1. Challenges on Probabilistic Modeling for Evolving Networks

    OpenAIRE

    Ding, Jianguo; Bouvry, Pascal

    2013-01-01

    With the emerging of new networks, such as wireless sensor networks, vehicle networks, P2P networks, cloud computing, mobile Internet, or social networks, the network dynamics and complexity expands from system design, hardware, software, protocols, structures, integration, evolution, application, even to business goals. Thus the dynamics and uncertainty are unavoidable characteristics, which come from the regular network evolution and unexpected hardware defects, unavoidable software errors,...

  2. Special issue on network coding

    Science.gov (United States)

    Monteiro, Francisco A.; Burr, Alister; Chatzigeorgiou, Ioannis; Hollanti, Camilla; Krikidis, Ioannis; Seferoglu, Hulya; Skachek, Vitaly

    2017-12-01

    Future networks are expected to depart from traditional routing schemes in order to embrace network coding (NC)-based schemes. These have created a lot of interest both in academia and industry in recent years. Under the NC paradigm, symbols are transported through the network by combining several information streams originating from the same or different sources. This special issue contains thirteen papers, some dealing with design aspects of NC and related concepts (e.g., fountain codes) and some showcasing the application of NC to new services and technologies, such as data multi-view streaming of video or underwater sensor networks. One can find papers that show how NC turns data transmission more robust to packet losses, faster to decode, and more resilient to network changes, such as dynamic topologies and different user options, and how NC can improve the overall throughput. This issue also includes papers showing that NC principles can be used at different layers of the networks (including the physical layer) and how the same fundamental principles can lead to new distributed storage systems. Some of the papers in this issue have a theoretical nature, including code design, while others describe hardware testbeds and prototypes.

  3. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  4. Implementation of Hardware Accelerators on Zynq

    OpenAIRE

    Toft, Jakob Kenn; Nannarelli, Alberto

    2016-01-01

    In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented o...

  5. Software for Managing Inventory of Flight Hardware

    Science.gov (United States)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  6. A few modeling and rendering techniques for computer graphics and their implementation on ultra hardware

    Science.gov (United States)

    Bidasaria, Hari

    1989-01-01

    Ultra network is a recently installed very high speed graphic hardware at NASA Langley Research Center. The Ultra Network interfaced to Voyager through its HSX channel is capable of transmitting up to 800 million bits of information per second. It is capable of displaying fifteen to twenty frames of precomputed images of size 1024 x 2368 with 24 bits of color information per pixel per second. Modeling and rendering techniques are being developed in computer graphics and implemented on Ultra hardware. A ray tracer is being developed for use at the Flight Software and Graphic branch. Changes were made to make the ray tracer compatible with Voyager.

  7. Hardware Testing and System Evaluation: Procedures to Evaluate Commodity Hardware for Production Clusters

    Energy Technology Data Exchange (ETDEWEB)

    Goebel, J

    2004-02-27

    Without stable hardware any program will fail. The frustration and expense of supporting bad hardware can drain an organization, delay progress, and frustrate everyone involved. At Stanford Linear Accelerator Center (SLAC), we have created a testing method that helps our group, SLAC Computer Services (SCS), weed out potentially bad hardware and purchase the best hardware at the best possible cost. Commodity hardware changes often, so new evaluations happen periodically each time we purchase systems and minor re-evaluations happen for revised systems for our clusters, about twice a year. This general framework helps SCS perform correct, efficient evaluations. This article outlines SCS's computer testing methods and our system acceptance criteria. We expanded the basic ideas to other evaluations such as storage, and we think the methods outlined in this article has helped us choose hardware that is much more stable and supportable than our previous purchases. We have found that commodity hardware ranges in quality, so systematic method and tools for hardware evaluation were necessary. This article is based on one instance of a hardware purchase, but the guidelines apply to the general problem of purchasing commodity computer systems for production computational work.

  8. Using Innovative Technologies for Manufacturing Rocket Engine Hardware

    Science.gov (United States)

    Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  9. A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, Dale; Farrington, Phillip

    2016-01-01

    Within the space flight community, reusability has taken center stage as the new buzzword. In order for reusable hardware to be competitive with its expendable counterpart, two major elements must be closely scrutinized. First, recovery and refurbishment costs must be lower than the development and acquisition costs. Additionally, the reliability for reused hardware must remain the same (or nearly the same) as "first use" hardware. Therefore, it is imperative that a systematic approach be established to enhance the development of reusable systems. However, before the decision can be made on whether it is more beneficial to reuse hardware or to replace it, the parameters that are needed to deem hardware worthy of reuse must be identified. For reusable hardware to be successful, the factors that must be considered are reliability (integrity, life, number of uses), operability (maintenance, accessibility), and cost (procurement, retrieval, refurbishment). These three factors are essential to the successful implementation of reusability while enabling the ability to meet performance goals. Past and present strategies and attempts at reuse within the space industry will be examined to identify important attributes of reusability that can be used to evaluate hardware when contemplating reusable versus expendable options. This paper will examine why reuse must be stated as an initial requirement rather than included as an afterthought in the final design. Late in the process, changes in the overall objective/purpose of components typically have adverse effects that potentially negate the benefits. A methodology for assessing the viability of reusing hardware will be presented by using the Space Shuttle Main Engine (SSME) to validate the approach. Because reliability, operability, and costs are key drivers in making this critical decision, they will be used to assess requirements for reuse as applied to components of the SSME.

  10. Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Narayan eSrinivasa

    2015-12-01

    Full Text Available Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that are can exhibit adaptive behaviors.Many such designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoid it.

  11. Criticality as a Set-Point for Adaptive Behavior in Neuromorphic Hardware.

    Science.gov (United States)

    Srinivasa, Narayan; Stepp, Nigel D; Cruz-Albrecht, Jose

    2015-01-01

    Neuromorphic hardware are designed by drawing inspiration from biology to overcome limitations of current computer architectures while forging the development of a new class of autonomous systems that can exhibit adaptive behaviors. Several designs in the recent past are capable of emulating large scale networks but avoid complexity in network dynamics by minimizing the number of dynamic variables that are supported and tunable in hardware. We believe that this is due to the lack of a clear understanding of how to design self-tuning complex systems. It has been widely demonstrated that criticality appears to be the default state of the brain and manifests in the form of spontaneous scale-invariant cascades of neural activity. Experiment, theory and recent models have shown that neuronal networks at criticality demonstrate optimal information transfer, learning and information processing capabilities that affect behavior. In this perspective article, we argue that understanding how large scale neuromorphic electronics can be designed to enable emergent adaptive behavior will require an understanding of how networks emulated by such hardware can self-tune local parameters to maintain criticality as a set-point. We believe that such capability will enable the design of truly scalable intelligent systems using neuromorphic hardware that embrace complexity in network dynamics rather than avoiding it.

  12. Optical Properties of Nanosatellite Hardware

    Science.gov (United States)

    Finckenor, M. M.; Coker, R. F.

    2014-01-01

    Over the last decade, a number of very small satellites have been launched into space. These have been called nanosatellites (generally of a weight between 1 and 10 kg) or picosatellites (weight optical and physical parameters necessary for accurate thermal analysis. Marshall Space Flight Center participated in the development and analysis of the Space Missile Defense Command-Operational Nanosatellite Effect (SMDC-ONE) and the Edison Demonstration of Smallsat Networks (EDSN) nanosatellites. These optical property measurements are documented here in hopes that they may benefit future nanosatellite and picosatellite programs and aid thermal analysis to ensure project goals are met, with the understanding that material properties may vary by vendor, batch, manufacturing process, and preflight handling. Where possible, complementary data are provided from ground simulations of the space environment and flight experiments, such as the Materials on International Space Station Experiment (MISSE) series. NASA gives no recommendation, endorsement, or preference, either expressed or implied, concerning materials and vendors used. Solar absorptance was calculated from spectral reflectance measurements made from 250 to 2,800 nm with an AZ Technology Laboratory Portable Spectroreflectometer (LPSR) model 300. ASTM E-903 was the test method used under normal laboratory conditions, and ASTM E-490 was the solar spectral irradiance data used to calculate solar absorptance. Most of the samples were flat, but stray light was minimized as much as possible with either a blackbody or black cloth as sample background. The LPSR has repeatability of approximately +/-1%, where solar absorptance is given as range, that is, from actual measurements taken across the sample. Infrared emittance measurements were made with an AZ Technology TEMP 2000A infrared reflectometer. This instrument measures the total hemispheric reflectance averaged over 3-35 micrometer wavelengths. ASTM E-408 was the test

  13. Nintedanib plus docetaxel as second-line therapy in patients with non-small-cell lung cancer of adenocarcinoma histology: a network meta-analysis vs new therapeutic options.

    Science.gov (United States)

    Popat, Sanjay; Mellemgaard, Anders; Reck, Martin; Hastedt, Claudia; Griebsch, Ingolf

    2017-06-01

    We provide an update to a network meta-analysis evaluating the relative efficacy of nintedanib + docetaxel versus other second-line agents in adenocarcinoma histology non-small-cell lung cancer. Overall similarity of nintedanib + docetaxel versus ramucirumab + docetaxel, and versus nivolumab. Comparing nintedanib + docetaxel with nivolumab, hazards ratio (HR) of overall survival and progression-free survival (PFS) pointed in opposite directions (overall survival: HR: 1.20 [95% credible interval: 0.92-1.58]; PFS: HR: 0.91 [0.68-1.21]). Exploratory subgroup analysis indicated superiority of nivolumab in high PD-L1 expression level subgroups; results were more favorable for nintedanib in all subgroups with low (nintedanib + docetaxel compared with the new therapeutic options ramucirumab + docetaxel and nivolumab, with potential differences in subgroups according to PD-L1 expression level.

  14. Spinal fusion-hardware construct: Basic concepts and imaging review

    Science.gov (United States)

    Nouh, Mohamed Ragab

    2012-01-01

    The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging. PMID:22761979

  15. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    Science.gov (United States)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2015-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  16. Packet Tracer network simulator

    CERN Document Server

    Jesin, A

    2014-01-01

    A practical, fast-paced guide that gives you all the information you need to successfully create networks and simulate them using Packet Tracer.Packet Tracer Network Simulator is aimed at students, instructors, and network administrators who wish to use this simulator to learn how to perform networking instead of investing in expensive, specialized hardware. This book assumes that you have a good amount of Cisco networking knowledge, and it will focus more on Packet Tracer rather than networking.

  17. Multi-user software of radio therapeutical calculation using a computational network; Software multiusuario de calculo radioterapeutico usando una red de computo

    Energy Technology Data Exchange (ETDEWEB)

    Allaucca P, J.J.; Picon C, C.; Zaharia B, M. [Departamento de Radioterapia, Instituto de Enfermedades Neoplasicas, Av. Angamos Este 2520, Lima 34 (Peru)

    1998-12-31

    It has been designed a hardware and software system for a radiotherapy Department. It runs under an Operative system platform Novell Network sharing the existing resources and of the server, it is centralized, multi-user and of greater safety. It resolves a variety of problems and calculation necessities, patient steps and administration, it is very fast and versatile, it contains a set of menus and options which may be selected with mouse, direction arrows or abbreviated keys. (Author)

  18. Breast Cancer: Treatment Options

    Science.gov (United States)

    ... Breast Cancer > Breast Cancer: Treatment Options Request Permissions Breast Cancer: Treatment Options Approved by the Cancer.Net Editorial ... as possible. Learn more about palliative care . Recurrent breast cancer If the cancer does return after treatment for ...

  19. Porphyria Treatment Options

    Science.gov (United States)

    ... Safe/Unsafe Drugs Search form Search About the APF About Porphyria Testing for Porphyria Treatment Options Panhematin ... Gary Eyster Art Sale Featured Items Support the APF You are here Home Treatment Options Click on ...

  20. Quantitative hardware prediction modeling for hardware/software co-design

    NARCIS (Netherlands)

    Meeuws, R.J.

    2012-01-01

    Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity

  1. Hardware Acceleration of Adaptive Neural Algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    James, Conrad D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-11-01

    As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

  2. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

  3. Options for Next Generation Digital Acquisition Systems

    CERN Document Server

    Boccardi, A

    2011-01-01

    Digital acquisition system designers have an always increasing number of options in terms of bus standards and digital signal processing hardware among which to choose. This allows for high flexibility but also opens the door to a proliferation of different architectures, potentially limiting the reusability and the design synergies among the various instrumentation groups. This contribution illustrates the design trends in some of the major institutes around the world with design examples including VME, PCI and TCA based modular systems using AMC and/or FMC mezzanines. Some examples of FPGA design practices aimed at increasing reusability of code will be mentioned together with some of the tools already available to designers to improve the information exchange and collaboration, like the Open Hardware Repository project.

  4. Quantum neuromorphic hardware for quantum artificial intelligence

    Science.gov (United States)

    Prati, Enrico

    2017-08-01

    The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

  5. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  6. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  7. Distributed Energy Implementation Options

    Energy Technology Data Exchange (ETDEWEB)

    Shah, Chandralata N [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

    2017-09-13

    This presentation covers the options for implementing distributed energy projects. It distinguishes between options available for distributed energy that is government owned versus privately owned, with a focus on the privately owned options including Energy Savings Performance Contract Energy Sales Agreements (ESPC ESAs). The presentation covers the new ESPC ESA Toolkit and other Federal Energy Management Program resources.

  8. ANNarchy: a code generation approach to neural simulations on parallel hardware

    Directory of Open Access Journals (Sweden)

    Julien eVitay

    2015-07-01

    Full Text Available Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit. Several numerical methods are available to transform ordinary differential equations into an efficient C++ code. We compare the parallel performance of the simulator to existing solutions.

  9. SEnviro: A Sensorized Platform Proposal Using Open Hardware and Open Standards

    Directory of Open Access Journals (Sweden)

    Sergio Trilles

    2015-03-01

    Full Text Available The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN. The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things. Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

  10. The Effect of Superstar Software on Hardware Sales in System Markets

    NARCIS (Netherlands)

    J.L.G. Binken (Jeroen); S. Stremersch (Stefan)

    2008-01-01

    textabstractSystems are composed of complementary products (e.g., video game systems are composed of the video game console and video games). Prior literature on indirect network effects argues that, in system markets, sales of the primary product (often referred to as "hardware") largely depend on

  11. SEnviro: a sensorized platform proposal using open hardware and open standards.

    Science.gov (United States)

    Trilles, Sergio; Luján, Alejandro; Belmonte, Óscar; Montoliu, Raúl; Torres-Sospedra, Joaquín; Huerta, Joaquín

    2015-03-06

    The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN). The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP) communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things). Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC) SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

  12. TANK SPACE OPTIONS REPORT

    Energy Technology Data Exchange (ETDEWEB)

    WILLIS WL; AHRENDT MR

    2009-08-11

    Since this report was originally issued in 2001, several options proposed for increasing double-shell tank (DST) storage space were implemented or are in the process of implementation. Changes to the single-shell tank (SST) waste retrieval schedule, completion of DST space saving options, and the DST space saving options in progress have delayed the projected shortfall of DST storage space from the 2007-2011 to the 2018-2025 timeframe (ORP-11242, River Protection Project System Plan). This report reevaluates options from Rev. 0 and includes evaluations of new options for alleviating projected restrictions on SST waste retrieval beginning in 2018 because of the lack of DST storage space.

  13. Design considerations for space flight hardware

    Science.gov (United States)

    Glover, Daniel

    1990-01-01

    The environmental and design constraints are reviewed along with some insight into the established design and quality assurance practices that apply to low earth orbit (LEO) space flight hardware. It is intended as an introduction for people unfamiliar with space flight considerations. Some basic data and a bibliography are included.

  14. Enabling Open Hardware through FOSS tools

    CERN Multimedia

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  15. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  16. QCE : A Simulator for Quantum Computer Hardware

    NARCIS (Netherlands)

    Michielsen, Kristel; Raedt, Hans De

    2003-01-01

    The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms.

  17. Proof Carrying Hardware based IP Protection

    Science.gov (United States)

    2017-03-01

    service to the hardware. Note that in this paper, we only consider Trojans which can be activated by a specific digital input vector. Further, we...acquisition,” IEEE Transactions on Information Forensics and Security, vol. 7, no. 1, pp. 25–40, 2012. [7] Y. Jin, B. Yang, and Y. Makris, “Cycle-accurate

  18. Efficient Runtime Management of Reconfigurable Hardware Resources

    NARCIS (Netherlands)

    Marconi, T.

    2011-01-01

    Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford

  19. Environmental Control System Software & Hardware Development

    Science.gov (United States)

    Vargas, Daniel Eduardo

    2017-01-01

    ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

  20. Hardware Accelerated Point Rendering of Isosurfaces

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Christensen, Niels Jørgen

    2003-01-01

    and that the advantage of rendering points as opposed to triangles increases with the size and complexity of the volumes. To gauge the visual quality of future hardware accelerated point rendering schemes, we have implemented a software based point rendering method and compare the quality to both MC and our OpenGL based...

  1. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  2. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  3. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  4. 78 FR 45279 - Self-Regulatory Organizations; Chicago Board Options Exchange, Incorporated; Notice of Filing and...

    Science.gov (United States)

    2013-07-26

    ... associated with hardware and maintenance services to third-party vendors that provide quoting software used... Index Options Rate Table--All Index Products Excluding SPX, SPXW, SPXpm, SRO, OEX, XEO, VIX and... create separate lines for ] Customer rates in SPXPM on the Specified Proprietary Index Options Rate Table...

  5. Interfacing Networks-on-Chip: Hardware meeting Software

    NARCIS (Netherlands)

    van de Burgwal, M.D.

    2010-01-01

    Next generation multi-media broadcast standards use encoded high-bandwidth streams of data to efficiently utilize the spectrum, at the cost of computation intensive processing. For battery powered portable devices this is challenging, as the energy source has limited capacity. By optimizing the

  6. HARDWARE AND SOFTWARE FOR A ROBOTIC NETWORK OF TELESCOPES - SONG

    OpenAIRE

    M. F. Andersen; F. Grundahl; J. Christensen-Dalsgaard; S. Frandsen; U. G. Jorgensen; H. Kjeldsen; P. Pallé; J. Skottfelt; A. N. Sorensen; E. Weiss

    2014-01-01

    E l p r o y e c t o S O N G b u s c a e s t a b l e c e r u n a r e d d e p e q u e ̃ n o s t e l e s c o p i o s p o r t o d o e l m u n d o p a r a o b s e r v a r l a s estrellas de manera ininterrumpida durante d ́ıas, semanas y hasta meses. Ac ́a describimos los aspectos fun- damentales para la construcci ́on de una red de este tipo y c ́omo operaremos cada observatorio como parte de la red entera. Los observatorios SONG trabajar ́an con autonom ́ıa y pueden ser controlados completamente...

  7. Combining multi-layered bitmap files using network specific hardware

    Science.gov (United States)

    DuBois, David H [Los Alamos, NM; DuBois, Andrew J [Santa Fe, NM; Davenport, Carolyn Connor [Los Alamos, NM

    2012-02-28

    Images and video can be produced by compositing or alpha blending a group of image layers or video layers. Increasing resolution or the number of layers results in increased computational demands. As such, the available computational resources limit the images and videos that can be produced. A computational architecture in which the image layers are packetized and streamed through processors can be easily scaled so to handle many image layers and high resolutions. The image layers are packetized to produce packet streams. The packets in the streams are received, placed in queues, and processed. For alpha blending, ingress queues receive the packetized image layers which are then z sorted and sent to egress queues. The egress queue packets are alpha blended to produce an output image or video.

  8. Developing hydrological monitoring networks with Arduino

    Science.gov (United States)

    Buytaert, Wouter; Vega, Andres; Villacis, Marcos; Moulds, Simon

    2015-04-01

    The open source hardware platform Arduino is very cost-effective and versatile for the development of sensor networks. Here we report on experiments on the use of Arduino-related technologies to develop and implement hydrological monitoring networks. Arduino Uno boards were coupled to a variety of commercially available hydrological sensors and programmed for automatic data collection. Tested sensors include water level, temperature, humidity, radiation, and precipitation. Our experiments show that most of the tested analogue sensors are quite straightforward to couple to Arduino based data loggers, especially if the electronic characteristics of the sensor are available. However, some sensors have internal digital interfaces, which are more challenging to connect. Lastly, tipping bucket rain gauges prove the most challenging because of the very specific methodology, i.e. registration of bucket tips instead of measurements at regular intervals. The typically low data generation rate of hydrological instruments is very compatible with available technologies for wireless data transmission. Mesh networks such as Xbee prove very convenient and robust for dispersed networks, while wifi is also an option for shorter distances and particular topographies. Lastly, the GSM shield of the Arduino can be used to transfer data to centralized databases. In regions where no mobile internet (i.e. 3G) connection is available, data transmission via text messages may be an option, depending on the bandwidth requirements.

  9. Traffic Light Options

    DEFF Research Database (Denmark)

    Jørgensen, Peter Løchte

    2006, and supervisory authorities in many other European countries have implemented similar regulation. Traffic light options are therefore likely to attract the attention of a wider audience of pension fund managers in the future. Focusing on the valuation of the traffic light option we set up a Black......This paper introduces, prices, and analyzes traffic light options. The traffic light option is an innovative structured OTC derivative developed independently by several London-based investment banks to suit the needs of Danish life and pension (L&P) companies, which must comply with the traffic...

  10. Traffic Light Options

    DEFF Research Database (Denmark)

    Jørgensen, Peter Løchte

    2007-01-01

    2006, and supervisory authorities in many other European countries have implemented similar regulation. Traffic light options are therefore likely to attract the attention of a wider audience of pension fund managers in the future. Focusing on the valuation of the traffic light option we set up a Black......This paper introduces, prices, and analyzes traffic light options. The traffic light option is an innovative structured OTC derivative developed independently by several London-based investment banks to suit the needs of Danish life and pension (L&P) companies, which must comply with the traffic...

  11. SYNTHESIS OF INFORMATION SYSTEM FOR SMART HOUSE HARDWARE MANAGEMENT

    Directory of Open Access Journals (Sweden)

    Vikentyeva Olga Leonidovna

    2017-10-01

    Full Text Available Subject: smart house maintenance requires taking into account a number of factors: resource-saving, reduction of operational expenditures, safety enhancement, providing comfortable working and leisure conditions. Automation of the corresponding engineering systems of illumination, climate control, security as well as communication systems and networks via utilization of contemporary technologies (e.g., IoT - Internet of Things poses a significant challenge related to storage and processing of the overwhelmingly massive volume of data whose utilization extent is extremely low nowadays. Since a building’s lifespan is large enough and exceeds the lifespan of codes and standards that take into account the requirements of safety, comfort, energy saving, etc., it is necessary to consider management aspects in the context of rational use of large data at the stage of information modeling. Research objectives: increase the efficiency of managing the subsystems of smart buildings hardware on the basis of a web-based information system that has a flexible multi-level architecture with several control loops and an adaptation model. Materials and methods: since a smart house belongs to man-machine systems, the cybernetic approach is considered as the basic method for design and research of information management system. Instrumental research methods are represented by set-theoretical modelling, automata theory and architectural principles of organization of information management systems. Results: a flexible architecture of information system for management of smart house hardware subsystems has been synthesized. This architecture encompasses several levels: client level, application level and data level as well as three layers: presentation level, actuating device layer and analytics layer. The problem of growing volumes of information processed by realtime message controller is attended by employment of sensors and actuating mechanisms with configurable

  12. An Overview of Reconfigurable Hardware in Embedded Systems

    Directory of Open Access Journals (Sweden)

    Wenyin Fu

    2006-09-01

    Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

  13. An Overview of Reconfigurable Hardware in Embedded Systems

    Directory of Open Access Journals (Sweden)

    Garcia Philip

    2006-01-01

    Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

  14. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  15. HARDWARE AND SOFTWARE STATUS OF QCDOC.

    Energy Technology Data Exchange (ETDEWEB)

    BOYLE,P.A.; CHEN,D.; CHRIST,N.H.; PETROV.K.; ET AL.

    2003-07-15

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  16. Particle Transport Simulation on Heterogeneous Hardware

    CERN Multimedia

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  17. Hex-Chrome Free Hardware - BAE Experience

    Science.gov (United States)

    2010-06-01

    Trane S 3201063A1 • TRW TS 2-25-60, Class A • Volkswagen TL 233 • Volvo VCS5737.29, .19 6/23/2010 Magni is one of several coatings, others such...installation and part must be revised. • Example: Panther FOV identified approximately 500 fasteners/ hardware that are being updated to “clean” within...particular program require coordination and funding to revise/ update (ex: MMPV common with MRAP) COTS, Government furnished, proprietary items and

  18. Instrumentation Hardware Abstraction Language (IHAL) Handbook

    Science.gov (United States)

    2017-01-01

    guidelines and thereby eliminating any misinterpretations that may exist. The RCC IRIG 106 sets forth standards for various aspects of telemetry (TM... community . At the time the task was initiated, IHAL had been shown to support configuration of analog signal conditioning hardware and pulse code...configurations were displayed in a single view. The settings on each device were then changed and immediately communicated to the appropriate vendor

  19. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  20. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    Directory of Open Access Journals (Sweden)

    Cancare Fabio

    2009-07-01

    Full Text Available Abstract Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs have more memory bandwidth and computational capability than Central Processing Units (CPUs and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective

  1. Trainable hardware for dynamical computing using error backpropagation through physical media.

    Science.gov (United States)

    Hermans, Michiel; Burm, Michaël; Van Vaerenbergh, Thomas; Dambre, Joni; Bienstman, Peter

    2015-03-24

    Neural networks are currently implemented on digital Von Neumann machines, which do not fully leverage their intrinsic parallelism. We demonstrate how to use a novel class of reconfigurable dynamical systems for analogue information processing, mitigating this problem. Our generic hardware platform for dynamic, analogue computing consists of a reciprocal linear dynamical system with nonlinear feedback. Thanks to reciprocity, a ubiquitous property of many physical phenomena like the propagation of light and sound, the error backpropagation-a crucial step for tuning such systems towards a specific task-can happen in hardware. This can potentially speed up the optimization process significantly, offering important benefits for the scalability of neuro-inspired hardware. In this paper, we show, using one experimentally validated and one conceptual example, that such systems may provide a straightforward mechanism for constructing highly scalable, fully dynamical analogue computers.

  2. Electricity Real Options Valuation

    OpenAIRE

    Broszkiewicz-Suwaj, Ewa

    2006-01-01

    In this paper a real option approach for the valuation of real assets is presented. Two continuous time models used for valuation are described: geometric Brownian motion model and interest rate model. The valuation for electricity spread option under Vasicek interest model is placed and the formulas for parameter estimators are calculated. The theoretical part is confronted with real data from electricity market.

  3. Americal options analyzed differently

    NARCIS (Netherlands)

    Nieuwenhuis, J.W.

    2003-01-01

    In this note we analyze in a discrete-time context and with a finite outcome space American options starting with the idea that every tradable should be a martingale under a certain measure. We believe that in this way American options become more understandable to people with a good working

  4. Early Option Exercise

    DEFF Research Database (Denmark)

    Heje Pedersen, Lasse; Jensen, Mads Vestergaard

    A classic result by Merton (1973) is that, except just before expiration or dividend payments, one should never exercise a call option and never convert a convertible bond. We show theoretically that this result is overturned when investors face frictions. Early option exercise can be optimal whe...

  5. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    Science.gov (United States)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  6. Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property

    Science.gov (United States)

    2015-05-22

    hardware intellectual property (PCHIP) framework, which aims to ensure the trustworthiness of third-party hardware IPs utilizing formal methods. We...published in non peer-reviewed journals: Final Report: Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property Report Title By...borrowing ideas from the proof carrying code (PCC) in software domain, in this project we introduced the proof carrying hardware intellectual property

  7. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  8. Class network routing

    Science.gov (United States)

    Bhanot, Gyan [Princeton, NJ; Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Takken, Todd E [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

    2009-09-08

    Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

  9. Polish Toxic Currency Options

    Directory of Open Access Journals (Sweden)

    Waldemar Gontarski

    2009-04-01

    Full Text Available Toxic currency options are defined on the basis of the opposition to the nature (essence of an option contract, which is justified in terms of norms founded on the general law clause of characteristics (nature of a relation (which represents an independent premise for imposing restrictions on the freedom of contracts. So-understood toxic currency options are unlawful. Indeed they contravene iuris cogentis regulations. These include for instance option contracts, which are concluded with a bank, if the bank has not informed about option risk before concluding the contract; or the barrier options, which focus only on the protection of banks interests. Therefore, such options may appear to be invalid. Therefore, performing contracts for toxic currency options may be qualified as a criminal mismanagement. For the sake of security, the manager should then take into consideration filing a claim for stating invalidity (which can be made in a court verdict. At the same time, if the supervisory board member in a commercial company, who can also be a subject to mismanagement offences, commits an omission involving lack of reaction (for example, if he/she fails to notify of the suspected offence committed by the management board members acting to the companys detriment when the management board makes the company conclude option contracts which are charged with absolute invalidity the supervisory board member so acting may be considered to act to the companys detriment. In the most recent Polish jurisprudence and judicature the standard of a good host is treated to be the last resort for determining whether the managers powers resulting from criminal regulations were performed. The manager of the exporter should not, as a rule, issue any options. Issuing options always means assuming an obligation. In the case of currency put options it is an absolute obligation to purchase a given amount in euro at exchange rate set in advance. On the other hand issuing

  10. Management options for recycling radioactive scrap metals

    Energy Technology Data Exchange (ETDEWEB)

    Dehmel, J.C.; MacKinney, J.; Bartlett, J.

    1997-02-01

    The feasibility and advantages of recycling radioactive scrap metals (RSM) have yet to be assessed, given the unique technical, regulatory, safety, and cost-benefit issues that have already been raised by a concerned recycling industry. As is known, this industry has been repeatedly involved with the accidental recycling of radioactive sources and, in some cases, with costly consequences. If recycling were deemed to be a viable option, it might have to be implemented with regulatory monitoring and controls. Its implementation may have to consider various and complex issues and address the requirements and concerns of distinctly different industries. There are three basic options for the recycling of such scraps. They are: (1) recycling through the existing network of metal-scrap dealers and brokers, (2) recycling directly and only with specific steelmills, or (3) recycling through regional processing centers. Under the first option, scrap dealers and brokers would receive material from RSM generators and determine at which steelmills such scraps would be recycled. For the second option, RSM generators would deal directly with selected steelmills under specific agreements. For the third option, generators would ship scraps only to regional centers for processing and shipment to participating steelmills. This paper addresses the potential advantages of each option, identifies the types of arrangements that would need to be secured among all parties, and attempts to assess the receptivity of the recycling industry to each option.

  11. Safe to Fly: Certifying COTS Hardware for Spaceflight

    Science.gov (United States)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  12. Is Hardware Removal Recommended after Ankle Fracture Repair?

    Directory of Open Access Journals (Sweden)

    Hong-Geun Jung

    2016-01-01

    Full Text Available The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients’ daily activities. This study was conducted on 80 consecutive cases (78 patients treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6 and decreased to 1.3 (range 0 to 6 after removal. 58 (72.5% patients experienced improved ankle stiffness and 65 (81.3% less discomfort while walking on uneven ground and 63 (80.8% patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

  13. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on...

  14. Unifying Approach to Software and Hardware Design for Scientific Calculations

    OpenAIRE

    Litvinov, G. L.; Maslov, V. P.; Rodionov, A. Ya.

    1999-01-01

    A unifying approach to software and hardware design generated by ideas of Idempotent Mathematics is discussed. The so-called idempotent correspondence principle for algorithms, programs and hardware units is described. A software project based on this approach is presented. Key words: universal algorithms, idempotent calculus, software design, hardware design, object oriented programming

  15. Is Hardware Removal Recommended after Ankle Fracture Repair?

    Science.gov (United States)

    Jung, Hong-Geun; Kim, Jin-Il; Park, Jae-Yong; Park, Jong-Tae; Eom, Joon-Sang; Lee, Dong-Oh

    2016-01-01

    The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients' daily activities. This study was conducted on 80 consecutive cases (78 patients) treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6) and decreased to 1.3 (range 0 to 6) after removal. 58 (72.5%) patients experienced improved ankle stiffness and 65 (81.3%) less discomfort while walking on uneven ground and 63 (80.8%) patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

  16. A Framework for Assessing the Reusability of Hardware (Reusable Rocket Engines)

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, Dale; Farrington, Philip

    2016-01-01

    Within the past few years, there has been a renewed interest in reusability as it applies to space flight hardware. Commercial companies such as Space Exploration Technologies Corporation (SpaceX), Blue Origin, and United Launch Alliance (ULA) are pursuing reusable hardware. Even foreign companies are pursuing this option. The Indian Space Research Organization (ISRO) launched a reusable space plane technology demonstrator and Airbus Defense and Space is planning to recover the main engines and avionics from its Advanced Expendable Launcher with Innovative engine Economy [1] [2]. To date, the Space Shuttle remains as the only Reusable Launch (RLV) to have flown repeated missions and the Space Shutte Main Engine (SSME) is the only demonstrated reusable engine. Whether the hardware being considered for reuse is a launch vehicle (fully reusable), a first stage (partially reusable), or a booster engine (single component), the overall governing process is the same; it must be recovered and recertified for flight. Therefore, there is a need to identify the key factors in determining the reusability of flight hardware. This paper begins with defining reusability to set the context, addresses the significance of reuse, and discusses areas that limit successful implementation. Finally, this research identifies the factors that should be considered when incorporating reuse.

  17. Early Option Exercise

    DEFF Research Database (Denmark)

    Jensen, Mads Vestergaard; Heje Pedersen, Lasse

    2016-01-01

    A classic result by Merton (1973) is that, except just before expiration or dividend payments, one should never exercise a call option and never convert a convertible bond. We show theoretically that this result is overturned when investors face frictions. Early option exercise can be optimal when...... it reduces short-sale costs, transaction costs, or funding costs. We provide consistent empirical evidence, documenting billions of dollars of early exercise for options and convertible bonds using unique data on actual exercise decisions and frictions. Our model can explain as much as 98% of early exercises...

  18. Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

    Directory of Open Access Journals (Sweden)

    Ikbel Belaid

    2011-01-01

    Full Text Available Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

  19. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  20. Methodology for Assessing Reusability of Spaceflight Hardware

    Science.gov (United States)

    Childress-Thompson, Rhonda; Thomas, L. Dale; Farrington, Phillip

    2017-01-01

    In 2011 the Space Shuttle, the only Reusable Launch Vehicle (RLV) in the world, returned to earth for the final time. Upon retirement of the Space Shuttle, the United States (U.S.) no longer possessed a reusable vehicle or the capability to send American astronauts to space. With the National Aeronautics and Space Administration (NASA) out of the RLV business and now only pursuing Expendable Launch Vehicles (ELV), not only did companies within the U.S. start to actively pursue the development of either RLVs or reusable components, but entities around the world began to venture into the reusable market. For example, SpaceX and Blue Origin are developing reusable vehicles and engines. The Indian Space Research Organization is developing a reusable space plane and Airbus is exploring the possibility of reusing its first stage engines and avionics housed in the flyback propulsion unit referred to as the Advanced Expendable Launcher with Innovative engine Economy (Adeline). Even United Launch Alliance (ULA) has announced plans for eventually replacing the Atlas and Delta expendable rockets with a family of RLVs called Vulcan. Reuse can be categorized as either fully reusable, the situation in which the entire vehicle is recovered, or partially reusable such as the National Space Transportation System (NSTS) where only the Space Shuttle, Space Shuttle Main Engines (SSME), and Solid Rocket Boosters (SRB) are reused. With this influx of renewed interest in reusability for space applications, it is imperative that a systematic approach be developed for assessing the reusability of spaceflight hardware. The partially reusable NSTS offered many opportunities to glean lessons learned; however, when it came to efficient operability for reuse the Space Shuttle and its associated hardware fell short primarily because of its two to four-month turnaround time. Although there have been several attempts at designing RLVs in the past with the X-33, Venture Star and Delta Clipper

  1. List search hardware for interpretive software

    CERN Document Server

    Altaber, Jacques; Mears, B; Rausch, R

    1979-01-01

    Interpreted languages, e.g. BASIC, are simple to learn, easy to use, quick to modify and in general 'user-friendly'. However, a critically time consuming process during interpretation is that of list searching. A special microprogrammed device for fast list searching has therefore been developed at the SPS Division of CERN. It uses bit- sliced hardware. Fast algorithms perform search, insert and delete of a six-character name and its value in a list of up to 1000 pairs. The prototype shows retrieval times of the order of 10-30 microseconds. (11 refs).

  2. Development of Hardware Dual Modality Tomography System

    Directory of Open Access Journals (Sweden)

    R. M. Zain

    2009-06-01

    Full Text Available The paper describes the hardware development and performance of the Dual Modality Tomography (DMT system. DMT consists of optical and capacitance sensors. The optical sensors consist of 16 LEDs and 16 photodiodes. The Electrical Capacitance Tomography (ECT electrode design use eight electrode plates as the detecting sensor. The digital timing and the control unit have been developing in order to control the light projection of optical emitters, switching the capacitance electrodes and to synchronize the operation of data acquisition. As a result, the developed system is able to provide a maximum 529 set data per second received from the signal conditioning circuit to the computer.

  3. Hardware Trigger Processor for the MDT System

    CERN Document Server

    Costa De Paiva, Thiago; The ATLAS collaboration

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the ATLAS Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  4. Yale's Tuition Postponement Option

    Science.gov (United States)

    Curran, William E.

    1973-01-01

    Discusses Yale's Tuition Postponement Option which bases a student's repayment obligation on the student's future income. Under this system, some students will pay Yale less than the amounts they postponed plus interest and some will pay more. (JF)

  5. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  6. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  7. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  8. Options Study - Phase II

    Energy Technology Data Exchange (ETDEWEB)

    R. Wigeland; T. Taiwo; M. Todosow; W. Halsey; J. Gehin

    2010-09-01

    The Options Study has been conducted for the purpose of evaluating the potential of alternative integrated nuclear fuel cycle options to favorably address the issues associated with a continuing or expanding use of nuclear power in the United States. The study produced information that can be used to inform decisions identifying potential directions for research and development on such fuel cycle options. An integrated nuclear fuel cycle option is defined in this study as including all aspects of the entire nuclear fuel cycle, from obtaining natural resources for fuel to the ultimate disposal of used nuclear fuel (UNF) or radioactive wastes. Issues such as nuclear waste management, especially the increasing inventory of used nuclear fuel, the current uncertainty about used fuel disposal, and the risk of nuclear weapons proliferation have contributed to the reluctance to expand the use of nuclear power, even though it is recognized that nuclear power is a safe and reliable method of producing electricity. In this Options Study, current, evolutionary, and revolutionary nuclear energy options were all considered, including the use of uranium and thorium, and both once-through and recycle approaches. Available information has been collected and reviewed in order to evaluate the ability of an option to clearly address the challenges associated with the current implementation and potential expansion of commercial nuclear power in the United States. This Options Study is a comprehensive consideration and review of fuel cycle and technology options, including those for disposal, and is not constrained by any limitations that may be imposed by economics, technical maturity, past policy, or speculated future conditions. This Phase II report is intended to be used in conjunction with the Phase I report, and much information in that report is not repeated here, although some information has been updated to reflect recent developments. The focus in this Options Study was to

  9. Hierarchical Simulation to Assess Hardware and Software Dependability

    Science.gov (United States)

    Ries, Gregory Lawrence

    1997-01-01

    This thesis presents a method for conducting hierarchical simulations to assess system hardware and software dependability. The method is intended to model embedded microprocessor systems. A key contribution of the thesis is the idea of using fault dictionaries to propagate fault effects upward from the level of abstraction where a fault model is assumed to the system level where the ultimate impact of the fault is observed. A second important contribution is the analysis of the software behavior under faults as well as the hardware behavior. The simulation method is demonstrated and validated in four case studies analyzing Myrinet, a commercial, high-speed networking system. One key result from the case studies shows that the simulation method predicts the same fault impact 87.5% of the time as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. Of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulations was therefore reduced from 500 to 145. Finally, the case studies show how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injections into the real system.

  10. Multi-criteria Classification for Pricing European Options

    OpenAIRE

    Nikola Gradojevic

    2015-01-01

    This paper builds a novel multi-criteria, non-parametric classification framework in order to improve the accuracy of pricing European options. The proposed approach is based on classifying financial options according to their implied volatility, time to maturity and moneyness. Using a recent data set for the daily S&P 500 index call options traded in 2012, the multi-criteria modular neural network model demonstrates its superior out-of-sample pricing performance relative to competing paramet...

  11. Exploring Infiniband Hardware Virtualization in OpenNebula towards Efficient High-Performance Computing

    Energy Technology Data Exchange (ETDEWEB)

    Pais Pitta de Lacerda Ruivo, Tiago [IIT, Chicago; Bernabeu Altayo, Gerard [Fermilab; Garzoglio, Gabriele [Fermilab; Timm, Steven [Fermilab; Kim, Hyun-Woo [Fermilab; Noh, Seo-Young [KISTI, Daejeon; Raicu, Ioan [IIT, Chicago

    2014-11-11

    has been widely accepted that software virtualization has a big negative impact on high-performance computing (HPC) application performance. This work explores the potential use of Infiniband hardware virtualization in an OpenNebula cloud towards the efficient support of MPI-based workloads. We have implemented, deployed, and tested an Infiniband network on the FermiCloud private Infrastructure-as-a-Service (IaaS) cloud. To avoid software virtualization towards minimizing the virtualization overhead, we employed a technique called Single Root Input/Output Virtualization (SRIOV). Our solution spanned modifications to the Linux’s Hypervisor as well as the OpenNebula manager. We evaluated the performance of the hardware virtualization on up to 56 virtual machines connected by up to 8 DDR Infiniband network links, with micro-benchmarks (latency and bandwidth) as well as w a MPI-intensive application (the HPL Linpack benchmark).

  12. Reverse total shoulder arthroplasty: a biomechanical evaluation of humeral and glenosphere hardware configuration.

    Science.gov (United States)

    Tashjian, Robert Z; Burks, Robert T; Zhang, Yue; Henninger, Heath B

    2015-03-01

    Various reverse total shoulder arthroplasty (rTSA) implant options are available for the humeral and glenosphere components. This study used a cadaveric biomechanical shoulder simulator to evaluate how hardware configurations in 2 common rTSA systems affect (1) abduction/adduction range of motion (ROM), (2) rotational ROM, and (3) forces to elevate the arm. Seven pairs of shoulders were tested on a biomechanical shoulder simulator before and after rTSA implantation. The Aequalis Reverse Shoulder (Tornier, Edina, MN, USA) and the Reverse Shoulder Prosthesis (RSP; DJO Surgical, Austin, TX, USA) were implanted in opposing shoulders. Aequalis implant options included humeral polymer insert thickness and eccentricity and glenosphere tilt. RSP implant options included glenosphere diameter and lateralization, humeral shell offset, and polymer insert depth. Both the RSP and Aequalis shifted the center of rotation inferior and medially compared with native shoulders (P Hardware configurations in rTSA have different effects on passive ROM and deltoid forces required for abduction. Identifying these changes may guide surgical decision making during rTSA placement. Copyright © 2015 Journal of Shoulder and Elbow Surgery Board of Trustees. Published by Elsevier Inc. All rights reserved.

  13. Essential Tremor (ET): Surgical Options

    Science.gov (United States)

    ... Next IETF > Treatment Options > Surgical Treatments > Surgical Options Surgical Options Click to share on Facebook (Opens in ... Magnetic resonance imaging (MRI) uses a powerful magnetic field and radio frequency pulses to produce detailed pictures ...

  14. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus......This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...

  15. Hardware codec for digital HDTV recording

    Science.gov (United States)

    Stammnitz, Peter; Boettcher, K.; Grueneberg, Kirsten A.; Hoefker, U.; Klein, H.

    1993-11-01

    For the purpose of digital recording of HDTV signals (EUREKA standard, 1250/50/2:1) a codec has been realized (HDI-codec) which can reduce the initial data rate from 1,152 GBit/s down to one fifth. According to the desired reduction, the playtime of a digital VCR (Video Cassette Recorder) can be increased from about 40 - 60 minutes up to at least the length of a feature film. This paper describes the hardware realization of the data rate reduction codec. Algorithms utilized for data rate reduction are adaptive intraframe/intrafield discrete cosine transform (DCT), adaptive quantization and variable length encoding (VLC). Interframe editing, multiple copy and shuttle mode are supported by a special codec architecture.

  16. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  17. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  18. Handbook of hardware/software codesign

    CERN Document Server

    Teich, Jürgen

    2017-01-01

    This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook. .

  19. Current conveyors variants, applications and hardware implementations

    CERN Document Server

    Senani, Raj; Singh, A K

    2015-01-01

    This book serves as a single-source reference to Current Conveyors and their use in modern Analog Circuit Design. The authors describe the various types of current conveyors discovered over the past 45 years, details of all currently available, off-the-shelf integrated circuit current conveyors, and implementations of current conveyors using other, off-the-shelf IC building blocks. Coverage includes prominent bipolar/CMOS/Bi-CMOS architectures of current conveyors, as well as all varieties of starting from third generation current conveyors to universal current conveyors, their implementations and applications. •Describes all commercially available off-the-shelf IC current conveyors, as well as hardware implementations of current conveyors using other off-the-shelf ICs; • Describes numerous variants of current conveyors evolved over the past forty five years; • Describes a number of Bipolar/CMOS/Bi-CMOS architectures of current conveyors, along with their characteristic features; • Includes a comprehe...

  20. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S.-H.

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  1. Perspectives in Simulation Hardware and Software Architecture

    Directory of Open Access Journals (Sweden)

    W.O. Grierson

    1985-10-01

    Full Text Available Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more complex models and the demand for greater simulation accuracy. The decision was to design an all-digital system to satisfy these growing requirements (see Gilbert and Howe, (1978. This all-digital approach was called the SYSTEM 10. The SYSTEM 10 has been effective in solving time-critical simulation problems and in replacing the previous approach of utilizing hybrid computers. Recent advances in 100 K emitter coupled logic (ECL now make it possible to support a new generation of equipment that expands modeling capabilities to serve simulation needs. The hardware and software concepts of this system, called the SYSTEM 100, are the subject of this paper.

  2. Extravehicular Activity (EVA) Hardware & Operations Overview

    Science.gov (United States)

    Moore, Sandra; Marmolejo, Jose

    2014-01-01

    The objectives of this presentation are to: Define Extravehicular Activity (EVA), identify the reasons for conducting an EVA, and review the role that EVA has played in the space program; Identify the types of EVAs that may be performed; Describe some of the U.S. Space Station equipment and tools that are used during an EVA, such as the Extravehicular Mobility Unit (EMU), the Simplified Aid For EVA Rescue (SAFER), the International Space Station (ISS) Joint Airlock and Russian Docking Compartment 1 (DC-1), and EVA Tools & Equipment; Outline the methods and procedures of EVA Preparation, EVA, and Post-EVA operations; Describe the Russian spacesuit used to perform an EVA; Provide a comparison between U.S. and Russian spacesuit hardware and EVA support; and Define the roles that different training facilities play in EVA training.

  3. Antihistamines: Understanding Your OTC Options

    Science.gov (United States)

    ... Resources Drugs, Procedures & Devices Over-the-counter Products Antihistamines: Understanding Your OTC Options Antihistamines: Understanding Your OTC Options Share Print Antihistamines: Understanding ...

  4. Providing Self-Healing Ability for Wireless Sensor Node by Using Reconfigurable Hardware

    Science.gov (United States)

    Yuan, Shenfang; Qiu, Lei; Gao, Shang; Tong, Yao; Yang, Weiwei

    2012-01-01

    Wireless sensor networks (WSNs) have received tremendous attention over the past ten years. In engineering applications of WSNs, a number of sensor nodes are usually spread across some specific geographical area. Some of these nodes have to work in harsh environments. Dependability of the Wireless Sensor Network (WSN) is very important for its successful applications in the engineering area. In ordinary research, when a node has a failure, it is usually discarded and the network is reorganized to ensure the normal operation of the WSN. Using appropriate WSN re-organization methods, though the sensor networks can be reorganized, this causes additional maintenance costs and sometimes still decreases the function of the networks. In those situations where the sensor networks cannot be reorganized, the performance of the whole WSN will surely be degraded. In order to ensure the reliable and low cost operation of WSNs, a method to develop a wireless sensor node with self-healing ability based on reconfigurable hardware is proposed in this paper. Two self-healing WSN node realization paradigms based on reconfigurable hardware are presented, including a redundancy-based self-healing paradigm and a whole FPAA/FPGA based self-healing paradigm. The nodes designed with the self-healing ability can dynamically change their node configurations to repair the nodes' hardware failures. To demonstrate these two paradigms, a strain sensor node is adopted as an illustration to show the concepts. Two strain WSN sensor nodes with self-healing ability are developed respectively according to the proposed self-healing paradigms. Evaluation experiments on self-healing ability and power consumption are performed. Experimental results show that the developed nodes can self-diagnose the failures and recover to a normal state automatically. The research presented can improve the robustness of WSNs and reduce the maintenance cost of WSNs in engineering applications. PMID:23202176

  5. Scan image compression-encryption hardware system

    Science.gov (United States)

    Bourbakis, Nikolaos G.; Brause, R.; Alexopoulos, C.

    1995-04-01

    This paper deals with the hardware design of an image compression/encryption scheme called SCAN. The scheme is based on the principles and ideas reflected by the specification of the SCAN language. SCAN is a fractal based context-free language which accesses sequentially the data of a 2D array, by describing and generating a wide range (near (nxn)) of space filling curves (or SCAN patterns) from a short set of simple ones. The SCAN method uses the algorithmic description of each 2D image as SCAN patterns combinations for the compression and encryption of the image data. Note that each SCAN letter or word accesses the image data with a different order (or sequence), thus the application of a variety of SCAN words associated with the compression scheme will produce various compressed versions of the same image. The compressed versions are compared in memory size and the best of them with the smallest size in bits could be used for the image compression/encryption. Note that the encryption of the image data is a result of the great number of possible space filling curves which could be generated by SCAN. Since the software implementation of the SCAN compression/encryption scheme requires some time, the hardware design and implementation of the SCAN scheme is necessary in order to reduce the image compression/encryption time to the real-time one. The development of such an image compression encryption system will have a significant impact on the transmission and storage of images. It will be applicable in multimedia and transmission of images through communication lines.

  6. 15 MW HArdware-in-the-loop Grid Simulation Project

    Energy Technology Data Exchange (ETDEWEB)

    Rigas, Nikolaos [Clemson Univ., SC (United States); Fox, John Curtiss [Clemson Univ., SC (United States); Collins, Randy [Clemson Univ., SC (United States); Tuten, James [Clemson Univ., SC (United States); Salem, Thomas [Clemson Univ., SC (United States); McKinney, Mark [Clemson Univ., SC (United States); Hadidi, Ramtin [Clemson Univ., SC (United States); Gislason, Benjamin [Clemson Univ., SC (United States); Boessneck, Eric [Clemson Univ., SC (United States); Leonard, Jesse [Clemson Univ., SC (United States)

    2014-10-31

    The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA

  7. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  8. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  9. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  10. Options in Compensation

    DEFF Research Database (Denmark)

    Flor, Christian Riis; Frimor, Hans; Munk, Claus

    2014-01-01

    to motivate effort. If rewarding low outcomes is infeasible, compensation consisting of stocks and options is a near-efficient means of overcoming the manager's induced aversion to undertaking risky investments, whereas stock compensation is not. However, stock plus option compensation may induce excessively......We derive the optimal compensation contract in a principal–agent setting in which outcome is used to provide incentives for both effort and risky investments. To motivate investment, optimal compensation entails rewards for high as well as low outcomes, and it is increasing at the mean outcome...... risky investments, and capping pay can be important in curbing such behavior....

  11. PACE: A dynamic programming algorithm for hardware/software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper presents the PACE partitioning algorithm which is used in the LYCOS co-synthesis system for partitioning control/dataflow graphs into hardware and software parts. The algorithm is a dynamic programming algorithm which solves both the problem of minimizing system execution time...... communication model and thus attempts to minimize communication overhead. The time-complexity of the algorithm is O(n2·𝒜) and the space-complexity is O(n·𝒜) where 𝒜 is the total area of the hardware chip and n the number of code fragments which may be placed in either hardware or software...... with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic...

  12. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    Energy Technology Data Exchange (ETDEWEB)

    Williamson, Douglas Alan [Univ. of Florida, Gainesville, FL (United States)

    1991-01-01

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas & Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States` utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste.

  13. Embedded Hardware-Efficient Real-Time Classification With Cascade Support Vector Machines.

    Science.gov (United States)

    Kyrkou, Christos; Bouganis, Christos-Savvas; Theocharides, Theocharis; Polycarpou, Marios M

    2016-01-01

    Cascade support vector machines (SVMs) are optimized to efficiently handle problems, where the majority of the data belong to one of the two classes, such as image object classification, and hence can provide speedups over monolithic (single) SVM classifiers. However, SVM classification is a computationally demanding task and existing hardware architectures for SVMs only consider monolithic classifiers. This paper proposes the acceleration of cascade SVMs through a hybrid processing hardware architecture optimized for the cascade SVM classification flow, accompanied by a method to reduce the required hardware resources for its implementation, and a method to improve the classification speed utilizing cascade information to further discard data samples. The proposed SVM cascade architecture is implemented on a Spartan-6 field-programmable gate array (FPGA) platform and evaluated for object detection on 800×600 (Super Video Graphics Array) resolution images. The proposed architecture, boosted by a neural network that processes cascade information, achieves a real-time processing rate of 40 frames/s for the benchmark face detection application. Furthermore, the hardware-reduction method results in the utilization of 25% less FPGA custom-logic resources and 20% peak power reduction compared with a baseline implementation.

  14. Distributed and Modular CAN-Based Architecture for Hardware Control and Sensor Data Integration.

    Science.gov (United States)

    Losada, Diego P; Fernández, Joaquín L; Paz, Enrique; Sanz, Rafael

    2017-05-03

    In this article, we present a CAN-based (Controller Area Network) distributed system to integrate sensors, actuators and hardware controllers in a mobile robot platform. With this work, we provide a robust, simple, flexible and open system to make hardware elements or subsystems communicate, that can be applied to different robots or mobile platforms. Hardware modules can be connected to or disconnected from the CAN bus while the system is working. It has been tested in our mobile robot Rato, based on a RWI (Real World Interface) mobile platform, to replace the old sensor and motor controllers. It has also been used in the design of two new robots: BellBot and WatchBot. Currently, our hardware integration architecture supports different sensors, actuators and control subsystems, such as motor controllers and inertial measurement units. The integration architecture was tested and compared with other solutions through a performance analysis of relevant parameters such as transmission efficiency and bandwidth usage. The results conclude that the proposed solution implements a lightweight communication protocol for mobile robot applications that avoids transmission delays and overhead.

  15. Distributed and Modular CAN-Based Architecture for Hardware Control and Sensor Data Integration

    Science.gov (United States)

    Losada, Diego P.; Fernández, Joaquín L.; Paz, Enrique; Sanz, Rafael

    2017-01-01

    In this article, we present a CAN-based (Controller Area Network) distributed system to integrate sensors, actuators and hardware controllers in a mobile robot platform. With this work, we provide a robust, simple, flexible and open system to make hardware elements or subsystems communicate, that can be applied to different robots or mobile platforms. Hardware modules can be connected to or disconnected from the CAN bus while the system is working. It has been tested in our mobile robot Rato, based on a RWI (Real World Interface) mobile platform, to replace the old sensor and motor controllers. It has also been used in the design of two new robots: BellBot and WatchBot. Currently, our hardware integration architecture supports different sensors, actuators and control subsystems, such as motor controllers and inertial measurement units. The integration architecture was tested and compared with other solutions through a performance analysis of relevant parameters such as transmission efficiency and bandwidth usage. The results conclude that the proposed solution implements a lightweight communication protocol for mobile robot applications that avoids transmission delays and overhead. PMID:28467381

  16. An Open Hardware seismic data recorder - a solid basis for citizen science

    Science.gov (United States)

    Mertl, Stefan

    2015-04-01

    "Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

  17. Heterogeneity and option pricing

    NARCIS (Netherlands)

    Benninga, Simon; Mayshar, Joram

    2000-01-01

    An economy with agents having constant yet heterogeneous degrees of relative risk aversion prices assets as though there were a single decreasing relative risk aversion pricing representative agent. The pricing kernel has fat tails and option prices do not conform to the Black-Scholes formula.

  18. Community Options for Elders.

    Science.gov (United States)

    Poulsen, Joyce G.

    This paper describes the Winnebago County (Wisconsin) Community Options Program, begun in January, 1982, which provides for a comprehensive assessment of all elderly persons within the target area who are at risk of becoming institutionalized. The paper focuses on the planning activities for the first year of the pilot program including community…

  19. Idaho's Energy Options

    Energy Technology Data Exchange (ETDEWEB)

    Robert M. Neilson

    2006-03-01

    This report, developed by the Idaho National Laboratory, is provided as an introduction to and an update of the status of technologies for the generation and use of energy. Its purpose is to provide information useful for identifying and evaluating Idaho’s energy options, and for developing and implementing Idaho’s energy direction and policies.

  20. Yale Tuition Postponement Option.

    Science.gov (United States)

    Yale Univ., New Haven, CT. Office of the President.

    This paper offers a detailed explanation of Yale University's tuition postponement option. The purposes of the Plan are: (1) to enable students to defer part of the expense of education; (2) to enable students to contribute to the support of the University in approximate proportion to their ability to do so and to the economic benefit they have…

  1. Why Open Source Hardware matters and why you should care

    OpenAIRE

    Gürkaynak, Frank K.

    2017-01-01

    Open source hardware is currently where open source software was about 30 years ago. The idea is well received by enthusiasts, there is interest and the open source hardware has gained visible momentum recently, with several well-known universities including UC Berkeley, Cambridge and ETH Zürich actively working on large projects involving open source hardware, attracting the attention of companies big and small. But it is still not quite there yet. In this talk, based on my experience on the...

  2. Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

    Science.gov (United States)

    2016-02-05

    SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware -based security techniques on future microprocessors in a way that they...can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of hardware . For this purpose, the...Mar-2011 31-May-2014 Approved for Public Release; Distribution Unlimited Final Report: Hardware -Enabled Security Through On-Chip Reconfigurable Fabric

  3. Using networking and communications software in business

    CERN Document Server

    McBride, PK

    2014-01-01

    Using Networking and Communications Software in Business covers the importance of networks in a business firm, the benefits of computer communications within a firm, and the cost-benefit in putting up networks in businesses. The book is divided into six parts. Part I looks into the nature and varieties of networks, networking standards, and network software. Part II discusses the planning of a networked system, which includes analyzing the requirements for the network system, the hardware for the network, and network management. The installation of the network system and the network managemen

  4. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  5. Testing FlexRay ECUs with a hardware-in-the-loop simulator; Test von FlexRay-Steuergeraeten am Hardware-in-the-Loop Simulator

    Energy Technology Data Exchange (ETDEWEB)

    Stroop, J.; Koehl, S. [dSPACE GmbH, Paderborn (Germany); Peller, M.; Riedesser, P. [BMW AG, Muenchen (Germany)

    2005-07-01

    To master the data communication of complex and safety relevant systems within future vehicles, the BMW Group prepares the application of FlexRay. The accompanying development process plays an important role for the quality, stability and reliability of those systems. Hardware-in-the-loop simulation and test stands are indispensable constituents and they are an integral part of the validation process. The following contribution describes the technology that is used within the BMW Group in more detail, especially in terms of communication networks with FlexRay. (orig.)

  6. Dynamic Privacy Management in Pervasive Sensor Networks

    Science.gov (United States)

    Gong, Nan-Wei; Laibowitz, Mathew; Paradiso, Joseph A.

    This paper describes the design and implementation of a dynamic privacy management system aimed at enabling tangible privacy control and feedback in a pervasive sensor network. Our work began with the development of a potentially invasive sensor network (with high resolution video, audio, and motion tracking capabilities) featuring different interactive applications that created incentive for accepting this network as an extension of people's daily social space. A user study was then conducted to evaluate several privacy management approaches - an active badge system for both online and on-site control, on/off power switches for physically disabling the hardware, and touch screen input control. Results from a user study indicated that an active badge for on-site privacy control is the most preferable method among all provided options. We present a set of results that yield insight into the privacy/benefit tradeoff from various sensing capabilities in pervasive sensor networks and how privacy settings and user behavior relate in these environments.

  7. Implementation of Hardware Accelerators on Zynq

    DEFF Research Database (Denmark)

    Toft, Jakob Kenn

    benchmarks, a Monte Carlo simulation of European stock options and a Telco telephone billing application. Each of the accelerators test different aspects of the Zynq platform in terms of floating-point and binary coded decimal processing speed. The two accelerators are compared with the performance......In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose...

  8. Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

    Science.gov (United States)

    Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

    2012-01-01

    Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

  9. Is a 4-Bit Synaptic Weight Resolution Enough? – Constraints on Enabling Spike-Timing Dependent Plasticity in Neuromorphic Hardware

    Science.gov (United States)

    Pfeil, Thomas; Potjans, Tobias C.; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

    2012-01-01

    Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists. PMID:22822388

  10. A Hardware Track Finder for ATLAS Trigger

    CERN Document Server

    Volpi, G; The ATLAS collaboration; Andreazza, A; Citterio, M; Favareto, A; Liberali, V; Meroni, C; Riva, M; Sabatini, F; Stabile, A; Annovi, A; Beretta, M; Castegnaro, A; Bevacqua, V; Crescioli, F; Francesco, C; Dell'Orso, M; Giannetti, P; Magalotti, D; Piendibene, M; Roda, C; Sacco, I; Tripiccione, R; Fabbri, L; Franchini, M; Giorgi, F; Giannuzzi, F; Lasagni, F; Sbarra, C; Valentinetti, S; Villa, M; Zoccoli, A; Lanza, A; Negri, A; Vercesi, V; Bogdan, M; Boveia, A; Canelli, F; Cheng, Y; Dunford, M; Li, H L; Kapliy, A; Kim, Y K; Melachrinos, C; Shochet, M; Tang, F; Tang, J; Tuggle, J; Tompkins, L; Webster, J; Atkinson, M; Cavaliere, V; Chang, P; Kasten, M; McCarn, A; Neubauer, M; Hoff, J; Liu, T; Okumura, Y; Olsen, J; Penning, B; Todri, A; Wu, J; Drake, G; Proudfoot, J; Zhang, J; Blair, R; Anderson, J; Auerbach, B; Blazey, G; Kimura, N; Yorita, K; Sakurai, Y; Mitani, T; Iizawa, T

    2012-01-01

    The existing three level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~400 Hz for permanent storage at the LHC design luminosity of 10^34 cm^-2 s^-1. When the LHC reaches beyond the design luminosity, the load on the Level-2 trigger system will significantly increase due to both the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast TracKer (FTK) is a custom electronics system that will operate at the full Level-1 accepted rate of 100 KHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories and FPGAs. The performance in important physics areas including b-tagging, tau-tagging and lepton isolation will be demonstrated with the ATLAS MC simulation at different LHC luminosities. The system design will be overviewed. The latest R&D progress of individual components...

  11. Mechanics of Granular Materials labeled hardware

    Science.gov (United States)

    2000-01-01

    Mechanics of Granular Materials (MGM) flight hardware takes two twin double locker assemblies in the Space Shuttle middeck or the Spacehab module. Sand and soil grains have faces that can cause friction as they roll and slide against each other, or even cause sticking and form small voids between grains. This complex behavior can cause soil to behave like a liquid under certain conditions such as earthquakes or when powders are handled in industrial processes. MGM experiments aboard the Space Shuttle use the microgravity of space to simulate this behavior under conditions that carnot be achieved in laboratory tests on Earth. MGM is shedding light on the behavior of fine-grain materials under low effective stresses. Applications include earthquake engineering, granular flow technologies (such as powder feed systems for pharmaceuticals and fertilizers), and terrestrial and planetary geology. Nine MGM specimens have flown on two Space Shuttle flights. Another three are scheduled to fly on STS-107. The principal investigator is Stein Sture of the University of Colorado at Boulder. (Credit: NASA/MSFC).

  12. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  13. Nanorobot Hardware Architecture for Medical Defense.

    Science.gov (United States)

    Cavalcanti, Adriano; Shirinzadeh, Bijan; Zhang, Mingjun; Kretly, Luiz C

    2008-05-06

    This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  14. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  15. Employing ISRU Models to Improve Hardware Design

    Science.gov (United States)

    Linne, Diane L.

    2010-01-01

    An analytical model for hydrogen reduction of regolith was used to investigate the effects of several key variables on the energy and mass performance of reactors for a lunar in-situ resource utilization oxygen production plant. Reactor geometry, reaction time, number of reactors, heat recuperation, heat loss, and operating pressure were all studied to guide hardware designers who are developing future prototype reactors. The effects of heat recuperation where the incoming regolith is pre-heated by the hot spent regolith before transfer was also investigated for the first time. In general, longer reaction times per batch provide a lower overall energy, but also result in larger and heavier reactors. Three reactors with long heat-up times results in similar energy requirements as a two-reactor system with all other parameters the same. Three reactors with heat recuperation results in energy reductions of 20 to 40 percent compared to a three-reactor system with no heat recuperation. Increasing operating pressure can provide similar energy reductions as heat recuperation for the same reaction times.

  16. Flow testing rear face hardware combinations

    Energy Technology Data Exchange (ETDEWEB)

    Haun, F.E. Jr.

    1962-06-01

    The purpose of these tests is to provide necessary laboratory data in support of an R,PEO program in determining the energy loss associated with various hardware size combinations on the rear face of the B-D-F reactors. The original method used to check for critical flow was determined to be faulty. A revised method demonstrated critical flow did occur in the 5/8-inch inconel connector and combination 1 fittings. The remaining fitting combinations with the 5/8-inch inconel and 3/4-inch aluminum connector were not rechecked because of the reaming of the I.D. to permit the continuation of the original tests. During test number 6, audible cavitation was heard with the highest severity at a point midway between pressure points 3 and 4 on the connector. This condition appeared again in tests 6A, 7, and 7A, with incipient cavitation at approximately 40 gpm in each test, regardless of the rear header pressure and/or temperature.

  17. Clarifying evacuation options through fire behavior and traffic modeling

    Science.gov (United States)

    Carol L. Rice; Ronny J. Coleman; Mike. Price

    2011-01-01

    Communities are becoming increasingly concerned with the variety of choices related to wildfire evacuation. We used ArcView with Network Analyst to evaluate the different options for evacuations during wildfire in a case study community. We tested overlaying fire growth patterns with the road network and population characteristics to determine recommendations for...

  18. Real-Time Hardware-in-the-Loop Laboratory Testing for Multisensor Sense and Avoid Systems

    Directory of Open Access Journals (Sweden)

    Giancarmine Fasano

    2013-01-01

    Full Text Available This paper focuses on a hardware-in-the-loop facility aimed at real-time testing of architectures and algorithms of multisensor sense and avoid systems. It was developed within a research project aimed at flight demonstration of autonomous non-cooperative collision avoidance for Unmanned Aircraft Systems. In this framework, an optionally piloted Very Light Aircraft was used as experimental platform. The flight system is based on multiple-sensor data integration and it includes a Ka-band radar, four electro-optical sensors, and two dedicated processing units. The laboratory test system was developed with the primary aim of prototype validation before multi-sensor tracking and collision avoidance flight tests. System concept, hardware/software components, and operating modes are described in the paper. The facility has been built with a modular approach including both flight hardware and simulated systems and can work on the basis of experimentally tested or synthetically generated scenarios. Indeed, hybrid operating modes are also foreseen which enable performance assessment also in the case of alternative sensing architectures and flight scenarios that are hardly reproducible during flight tests. Real-time multisensor tracking results based on flight data are reported, which demonstrate reliability of the laboratory simulation while also showing the effectiveness of radar/electro-optical fusion in a non-cooperative collision avoidance architecture.

  19. Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback

    Directory of Open Access Journals (Sweden)

    Dingankar Ajit

    2010-01-01

    Full Text Available Abstract Manycore architectures are expected to dominate future general-purpose and application-specific computing systems. The ever-increasing number of on-chip processor cores and the associated interconnect complexities present significant challenges in the design, optimization and operation of these systems. In this paper we investigate the applicability of intelligent, dynamic system-level optimization techniques in addressing some manycore design challenges such as dynamic resource allocation. In particular, we introduce hardware enabled system-level bidding-based algorithms as an efficient and real-time on-chip mechanism for resource allocation in homogeneous and heterogeneous (MPSoC manycore architectures. We have also developed a low-level simulation framework, to evaluate the proposed bidding-based algorithms in several on-chip network-connected manycore configurations. Experimental results indicate performance improvements between 8%–44%, when compared to a standard on-chip static allocation, while achieving a balanced workload distribution. The proposed hardware was synthesized to show that it imposes a very small hardware overhead to the overall system. Power consumption of the embedded mechanism as well as energy consumption due to additional network traffic for collecting system feedback are also estimated to be very small. The obtained results encourage further investigation of the applicability of such intelligent, dynamic system-level algorithms for addressing additional issues in manycore architectures.

  20. Ultrasound and clinical evaluation of soft-tissue versus hardware biceps tenodesis: is hardware tenodesis worth the cost?

    Science.gov (United States)

    Elkousy, Hussein; Romero, Jose A; Edwards, T Bradley; Gartsman, Gary M; O'Connor, Daniel P

    2014-02-01

    This study assesses the failure rate of soft-tissue versus hardware fixation of biceps tenodesis by ultrasound to determine if the expense of a hardware tenodesis technique is warranted. Seventy-two patients that underwent arthroscopic biceps tenodesis over a 3-year period were evaluated using postoperative ultrasonography and clinical examination. The tenodesis technique employed was either a soft-tissue technique with sutures or an interference screw technique using hardware based on surgeon preference. Patient age was 57.9 years on average with ultrasound and clinical examination done at an average of 9.3 months postoperatively. Thirty-one patients had a hardware technique and 41 a soft-tissue technique. Overall, 67.7% of biceps tenodesis done with hardware were intact, compared with 75.6% for the soft-tissue technique by ultrasound (P = .46). Clinical evaluation indicated that 80.7% of hardware techniques and 78% of soft-tissue techniques were intact. Average material cost to the hospital for the hardware technique was $514.32, compared with $32.05 for the soft-tissue technique. Biceps tenodesis success, as determined by clinical deformity and ultrasound, was not improved using hardware as compared to soft-tissue techniques. Soft-tissue techniques are equally efficacious and more cost effective than hardware techniques.

  1. Design of FPGA Based Neural Network Controller for Earth Station Power System

    OpenAIRE

    Hassen T. Dorrah; Ninet M. A. El-Rahman; Faten H. Fahmy; Hanaa T. El-Madany

    2012-01-01

    Automation of generating hardware description language code from neural networks models can highly decrease time of implementation those networks into a digital devices, thus significant money savings. To implement the neural network into hardware designer, it is required to translate generated model into device structure. VHDL language is used to describe those networks into hardware. VHDL code has been proposed to implement ANNs as well as to present simulation results with floating point a...

  2. Real-time high speed generator system emulation with hardware-in-the-loop application

    Science.gov (United States)

    Stroupe, Nicholas

    The emerging emphasis and benefits of distributed generation on smaller scale networks has prompted much attention and focus to research in this field. Much of the research that has grown in distributed generation has also stimulated the development of simulation software and techniques. Testing and verification of these distributed power networks is a complex task and real hardware testing is often desired. This is where simulation methods such as hardware-in-the-loop become important in which an actual hardware unit can be interfaced with a software simulated environment to verify proper functionality. In this thesis, a simulation technique is taken one step further by utilizing a hardware-in-the-loop technique to emulate the output voltage of a generator system interfaced to a scaled hardware distributed power system for testing. The purpose of this thesis is to demonstrate a new method of testing a virtually simulated generation system supplying a scaled distributed power system in hardware. This task is performed by using the Non-Linear Loads Test Bed developed by the Energy Conversion and Integration Thrust at the Center for Advanced Power Systems. This test bed consists of a series of real hardware developed converters consistent with the Navy's All-Electric-Ship proposed power system to perform various tests on controls and stability under the expected non-linear load environment of the Navy weaponry. This test bed can also explore other distributed power system research topics and serves as a flexible hardware unit for a variety of tests. In this thesis, the test bed will be utilized to perform and validate this newly developed method of generator system emulation. In this thesis, the dynamics of a high speed permanent magnet generator directly coupled with a micro turbine are virtually simulated on an FPGA in real-time. The calculated output stator voltage will then serve as a reference for a controllable three phase inverter at the input of the test bed

  3. Management options of varicoceles

    Directory of Open Access Journals (Sweden)

    Peter Chan

    2011-01-01

    Full Text Available Varicocele is one of the most common causes of male infertility. Treatment options for varicoceles includes open varicocelectomy performed at various anatomical levels. Laparoscopic varicocelectomy has been established to be a safe and effective treatment for varicoceles. Robotic surgery has been introduced recently as an alternative surgical option for varicocelectomy. Microsurgical varicocelectomy has gained increasing popularity among experts in male reproductive medicine as the treatment of choice for varicocele because of its superior surgical outcomes. There is a growing volume of literature in the recent years on minimal invasive varicocele treatment with percutaneous retrograde and anterograde venous embolization/sclerotherapy. In this review, we will discuss the advantages and limitations associated with each treatment modality for varicoceles. Employment of these advanced techniques of varicocelectomy can provide a safe and effective approach aiming to eliminate varicocele, preserve testicular function and, in a substantial number of men, increase semen quality and the likelihood of pregnancy.

  4. Shungnak Energy Configuration Options.

    Energy Technology Data Exchange (ETDEWEB)

    Rosewater, David Martin [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Eddy, John P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-10-01

    Power systems in rural Alaska villages face a unique combination of challenges that can increase the cost of energy and lowers energy supply reliability. In the case of the remote village of Shungnak, diesel and heating fuel is either shipped in by barge or flown in by aircraft. This report presents a technical analysis of several energy infrastructure upgrade and modification options to reduce the amount of fuel consumed by the community of Shungnak. Reducing fuel usage saves money and makes the village more resilient to disruptions in fuel supply. The analysis considers demand side options, such as energy efficiency, alongside the installation of wind and solar power generation options. Some novel approaches are also considered including battery energy storage and the use of electrical home heating stoves powered by renewable generation that would otherwise be spilled and wasted. This report concludes with specific recommendations for Shungnak based on economic factors, and fuel price sensitivity. General conclusions are also included to support future work analyzing similar energy challenges in remote arctic regions.

  5. Ventriculobiliary Shunts, Another Option.

    Science.gov (United States)

    Rivero-Garvía, Mónica; Pancucci, Giovanni; Morcillo, Juan; Millán, Ana; Márquez-Rivas, Javier

    2015-01-01

    The basic management of hydrocephalus includes shunts to the peritoneum and atrium. However, there are particularly complex patients in whom it is necessary to look for atypical places for implanting the distal catheter. Since 2000, 1,325 shunts have been implanted in pediatric patients. Only 3 patients required a ventriculobiliary shunt. We report 3 cases: a 7-year-old boy with a surgically treated complex heart disease, a 16-month-old girl with hydrocephalus secondary to a brain tumor and multiple bacteremias secondary to an infection of the central venous reservoir, and a 4-year-old girl with nonreabsorptive hydrocephalus caused by intraventricular bleeding due to premature birth, necrotizing enterocolitis and shunt infections with abdominal pseudocysts, which caused multiple abdominal septations and, finally, a nonreabsorptive peritoneum. At present, cases 1 [45 months after ventriculobiliary shunt (VBS)] and 3 (27 months after VBS) are symptom free, while case 2 (14 months after VBS) died of infectious respiratory complications. The gold standard for the treatment of nonreabsorptive hydrocephalus is a ventriculoperitoneal shunt, the second option is a ventriculoatrial shunt, and the third option is uncertain. In our short experience, a ventriculo-gallbladder shunt is a good option when there is no abdominal hypertension. © 2015 S. Karger AG, Basel.

  6. The safeguards options study

    Energy Technology Data Exchange (ETDEWEB)

    Hakkila, E.A.; Mullen, M.F.; Olinger, C.T.; Stanbro, W.D. [Los Alamos National Lab., NM (United States); Olsen, A.P.; Roche, C.T.; Rudolph, R.R. [Argonne National Lab., IL (United States); Bieber, A.M.; Lemley, J. [Brookhaven National Lab., Upton, NY (United States); Filby, E. [Idaho National Engineering Lab., Idaho Falls, ID (United States)] [and others

    1995-04-01

    The Safeguards Options Study was initiated to aid the International Safeguards Division (ISD) of the DOE Office of Arms Control and Nonproliferation in developing its programs in enhanced international safeguards. The goal was to provide a technical basis for the ISD program in this area. The Safeguards Options Study has been a cooperative effort among ten organizations. These are Argonne National Laboratory, Brookhaven National Laboratory, Idaho National Engineering Laboratory, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Mound Laboratory, Oak Ridge National Laboratory, Pacific Northwest Laboratories, Sandia National Laboratories, and Special Technologies Laboratory. Much of the Motivation for the Safeguards Options Study is the recognition after the Iraq experience that there are deficiencies in the present approach to international safeguards. While under International Atomic Energy Agency (IAEA) safeguards at their declared facilities, Iraq was able to develop a significant weapons program without being noticed. This is because negotiated safeguards only applied at declared sites. Even so, their nuclear weapons program clearly conflicted with Iraq`s obligations under the Nuclear Nonproliferation Treaty (NPT) as a nonnuclear weapon state.

  7. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  8. The role of the visual hardware system in rugby performance ...

    African Journals Online (AJOL)

    This study explores the importance of the 'hardware' factors of the visual system in the game of rugby. A group of professional and club rugby players were tested and the results compared. The results were also compared with the established norms for elite athletes. The findings indicate no significant difference in hardware ...

  9. The role of the visual hardware system in rugby performance ...

    African Journals Online (AJOL)

    This suggests that in the game of rugby the hardware skills may be of less importance and that visual enhancement programmes should focus more on improving the players' software skills. Key words: Vision, hardware, rugby, sports performance. (Af. J. Physical, Health Education, Recreation and Dance: 2003 Special ...

  10. [Hardware and software for X-ray therapy planning].

    Science.gov (United States)

    Zhizniakov, A L; Semenov, S I; Sushkova, L T; Troitskii, D P; Chirkov, K V

    2007-01-01

    Hardware, circuitry, and software suggested in this work make it possible to use the SLS-9 X-ray simulator for classical and computer tomographic imaging. The suggested hardware and software can be used as a basis for designing special-purpose tomographic systems.

  11. Hardware design of a submerged buoy system based on electromagnetic inductive coupling

    Directory of Open Access Journals (Sweden)

    Song Dalei

    2016-01-01

    Full Text Available This paper mainly introduces the hardware design of a new type of ocean buoy for multi-scale marine dynamic process. The buoy system can collect a number of real-time marine environment data and then transmit all the data back to the landing site through wireless module. The authors mainly designed the hardware circuit of the buoy system, including data collection system, data communication system, data storage system. Due to the buoy system will complete the marine observation work continuously for at least a month, so we add the low power consumption function which can realize the intermittent work for the data collection system. This paper also introduces the electromagnetic induction coupling technology of underwater sensors, the sea surface communication network technology, etc. The system can also extends to the ecological regional anomaly monitoring and the early warning of disaster weather.

  12. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  13. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  14. Strategic Options Development and Analysis

    Science.gov (United States)

    Ackermann, Fran; Eden, Colin

    Strategic Options Development and Analysis (SODA) enables a group or individual to construct a graphical representation of a problematic situation, and thus explore options and their ramifications with respect to a complex system of goals or objectives. In addition the method aims to help groups arrive at a negotiated agreement about how to act to resolve the situation. It is based upon the use of causal mapping - a formally constructed means-ends network - as representation form. Because the picture has been constructed using the natural language of the problem owners it becomes a model of the situation that is ‘owned' by those who define the problem. The use of formalities for the construction of the model makes it amenable to a range of analyses as well as encouraging reflection and a deeper understanding. These analyses can be used in a ‘rough and ready' manner by visual inspection or through the use of specialist causal mapping software (Decision Explorer). Each of the analyses helps a group or individual discover important features of the problem situation, and these features facilitate agreeing agood solution. The SODA process is aimed at helping a group learn about the situation they face before they reach agreements. Most significantly the exploration through the causal map leads to a higher probability of more creative solutions and promotes solutions that are more likely to be implemented because the problem construction process is wider and more likely to include richer social dimensions about the blockages to action and organizational change. The basic theories that inform SODA derive from cognitive psychology and social negotiation, where the model acts as a continuously changing representation of the problematic situation - changing as the views of a person or group shift through learning and exploration. This chapter, jointly written by two leading practitioner academics and the original developers of SODA, Colin Eden and Fran Ackermann

  15. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  16. Deliberating emission reduction options

    Energy Technology Data Exchange (ETDEWEB)

    Dowd, A.M.; Rodriguez, M.; Jeanneret, T. [Commonwealth Scientific and Industrial Research Organisation CSIRO, 37 Graham Rd, Highett VIC 3190 (Australia); De Best-Waldhober, M.; Straver, K.; Mastop, J.; Paukovic, M. [Energy research Centre of the Netherlands ECN, Policy Studies, Amsterdam (Netherlands)

    2012-06-15

    For more than 20 years there has been a concerted international effort toward addressing climate change. International conventions, such as the United Nations Foreign Convention on Climate Change (UNFCCC; ratified in 1994), have been established by committed nations seeking to address global climate change through the reduction of greenhouse gases emitted into the Earth's atmosphere (Global CCS Institute, 2011). Long recognised as the most crucial of the greenhouse gases to impact global warming, the majority of carbon dioxide's anthropogenic global emissions are directly related to fuel combustion of which both Australia and the Netherlands' energy production is significantly reliant. Both these nations will need to consider many opinions and make hard decisions if alternative energy options are to be implemented at the scale that is required to meet international emission targets. The decisions that are required not only need to consider the many options available but also their consequences. Along with politicians, policy developers and industry, the general public also need to be active participants in deciding which energy options, and their subsequent consequences, are acceptable for implementation at the national level. Access to balanced and factual information is essential in establishing informed opinions on the many policy options available. Past research has used several methods to measure public perceptions and opinions yet for complex issues, such as emission reduction, some of these methods have shown to be problematic. For example, semi structured interviews can provide data that is flexible and context rich yet is does also come with the limitations such as it seldom provides a practical assessment that can be utilised from researcher to researcher, across disciplines and public participation techniques. Surveys on the other hand usually address these limitations but surveys that do not encourage comparison of information or ask

  17. Telecommunication Networks

    DEFF Research Database (Denmark)

    Olsen, Rasmus Løvenstein; Balachandran, Kartheepan; Hald, Sara Ligaard

    2014-01-01

    In this chapter, we look into the role of telecommunication networks and their capability of supporting critical infrastructure systems and applications. The focus is on smart grids as the key driving example, bearing in mind that other such systems do exist, e.g., water management, traffic control......, etc. First, the role of basic communication is examined with a focus on critical infrastructures. We look at heterogenic networks and standards for smart grids, to give some insight into what has been done to ensure inter-operability in this direction. We then go to the physical network, and look...... at the deployment of the physical layout of the communication network and the related costs. This is an important aspect as one option to use existing networks is to deploy dedicated networks. Following this, we look at some generic models that describe reliability for accessing dynamic information. This part...

  18. Lattice QCD with commodity hardware and software

    Energy Technology Data Exchange (ETDEWEB)

    Holmgren, D.J. [and others

    2000-01-25

    Large scale QCD Monte Carlo calculations have typically been performed on either commercial supercomputers or specially built massively parallel computers such as Fermilab's ACPMAPS. Commodity computer systems offer impressive floating point performance-to-cost ratios which exceed those of commercial supercomputers. As high performance networking components approach commodity pricing, it becomes reasonable to assemble a massively parallel supercomputer from commodity parts. The authors describe the work and progress to date of a collaboration working on this problem.

  19. The Art of Space Flight Exercise Hardware: Design and Implementation

    Science.gov (United States)

    Beyene, Nahom M.

    2004-01-01

    The design of space flight exercise hardware depends on experience with crew health maintenance in a microgravity environment, history in development of flight-quality exercise hardware, and a foundation for certifying proper project management and design methodology. Developed over the past 40 years, the expertise in designing exercise countermeasures hardware at the Johnson Space Center stems from these three aspects of design. The medical community has steadily pursued an understanding of physiological changes in humans in a weightless environment and methods of counteracting negative effects on the cardiovascular and musculoskeletal system. The effects of weightlessness extend to the pulmonary and neurovestibular system as well with conditions ranging from motion sickness to loss of bone density. Results have shown losses in water weight and muscle mass in antigravity muscle groups. With the support of university-based research groups and partner space agencies, NASA has identified exercise to be the primary countermeasure for long-duration space flight. The history of exercise hardware began during the Apollo Era and leads directly to the present hardware on the International Space Station. Under the classifications of aerobic and resistive exercise, there is a clear line of development from the early devices to the countermeasures hardware used today. In support of all engineering projects, the engineering directorate has created a structured framework for project management. Engineers have identified standards and "best practices" to promote efficient and elegant design of space exercise hardware. The quality of space exercise hardware depends on how well hardware requirements are justified by exercise performance guidelines and crew health indicators. When considering the microgravity environment of the device, designers must consider performance of hardware separately from the combined human-in-hardware system. Astronauts are the caretakers of the hardware

  20. Achilles tendinosis: treatment options.

    Science.gov (United States)

    Lopez, Roberto Gabriel L; Jung, Hong-Geun

    2015-03-01

    Athletes usually complain of an ongoing or chronic pain over the Achilles tendon, but recently even non-athletes are experiencing the same kind of pain which affects their daily activities. Achilles tendinosis refers to a degenerative process of the tendon without histologic or clinical signs of intratendinous inflammation. Treatment is based on whether to stimulate or prevent neovascularization. Thus, until now, there is no consensus as to the best treatment for this condition. This paper aims to review the common ways of treating this condition from the conservative to the surgical options.

  1. Brain inspired hardware architectures - Can they be used for particle physics ?

    CERN Multimedia

    CERN. Geneva

    2016-01-01

    After their inception in the 1940s and several decades of moderate success, artificial neural networks have recently demonstrated impressive achievements in analysing big data volumes. Wide and deep network architectures can now be trained using high performance computing systems, graphics card clusters in particular. Despite their successes these state-of-the-art approaches suffer from very long training times and huge energy consumption, in particular during the training phase. The biological brain can perform similar and superior classification tasks in the space and time domains, but at the same time exhibits very low power consumption, rapid unsupervised learning capabilities and fault tolerance. In the talk the differences between classical neural networks and neural circuits in the brain will be presented. Recent hardware implementations of neuromorphic computing systems and their applications will be shown. Finally, some initial ideas to use accelerated neural architectures as trigger processors i...

  2. An experimental study on nonlinear function computation for neural/fuzzy hardware design.

    Science.gov (United States)

    Basterretxea, Koldo; Tarela, José Manuel; del Campo, Inés; Bosque, Guillermo

    2007-01-01

    An experimental study on the influence of the computation of basic nodal nonlinear functions on the performance of (NFSs) is described in this paper. Systems' architecture size, their approximation capability, and the smoothness of provided mappings are used as performance indexes for this comparative paper. Two widely used kernel functions, the sigmoid-logistic function and the Gaussian function, are analyzed by their computation through an accuracy-controllable approximation algorithm designed for hardware implementation. Two artificial neural network (ANN) paradigms are selected for the analysis: backpropagation neural networks (BPNNs) with one hidden layer and radial basis function (RBF) networks. Extensive simulation of simple benchmark approximation problems is used in order to achieve generalizable conclusions. For the performance analysis of fuzzy systems, a functional equivalence theorem is used to extend obtained results to fuzzy inference systems (FISs). Finally, the adaptive neurofuzzy inference system (ANFIS) paradigm is used to observe the behavior of neurofuzzy systems with learning capabilities.

  3. Installment options close to expiry

    Directory of Open Access Journals (Sweden)

    G. Alobaidi

    2006-01-01

    Full Text Available We use an asymptotic expansion to study the behavior of installment options close to expiry. Installment options are contracts where the price is paid over the life of the option rather than as a lump sum at the time of purchase, and where the contract can be allowed to lapse at any time. Series solutions are obtained for the location of the free boundary and the price of the option.

  4. Mixed waste management options

    Energy Technology Data Exchange (ETDEWEB)

    Owens, C.B.; Kirner, N.P. [EG and G Idaho, Inc., Idaho Falls, ID (United States). Idaho National Engineering Lab.

    1991-12-31

    Disposal fees for mixed waste at proposed commercial disposal sites have been estimated to be $15,000 to $40,000 per cubit foot. If such high disposal fees are imposed, generators may be willing to apply extraordinary treatment or regulatory approaches to properly dispose of their mixed waste. This paper explores the feasibility of several waste management scenarios and attempts to answer the question: Can mixed waste be managed out of existence? Existing data on commercially generated mixed waste streams are used to identify the realm of mixed waste known to be generated. Each waste stream is evaluated from both a regulatory and technical perspective in order to convert the waste into a strictly low-level radioactive or a hazardous waste. Alternative regulatory approaches evaluated in this paper include a delisting petition, no migration petition, and a treatability variance. For each waste stream, potentially available treatment options are identified that could lead to these variances. Waste minimization methodology and storage for decay are also considered. Economic feasibility of each option is discussed broadly.

  5. Novel preventive treatment options.

    Science.gov (United States)

    Longbottom, C; Ekstrand, K; Zero, D; Kambara, M

    2009-01-01

    A number of novel preventive treatment options which, as with traditional methods, can be differentiated into 3 categories of prevention (primary, secondary and tertiary), have been and are being currently investigated. Those reviewed are either commercially available or appear relatively close to that point. These include: approximal sealants; fluoride applications, including slow-release devices; measures to help remineralize demineralized tissue, including 3 different methods of delivering amorphous calcium phosphate; measures to help modify the biofilm to reduce the cariogenic challenge, including ozone therapy and probiotics; measures to increase enamel resistance to demineralization, including laser treatment of enamel, and a novel 'hybrid' technique for the treatment of primary molar caries which involves 'overlapping' of secondary and tertiary prevention--the Hall technique. Although many of these techniques show considerable promise and dentists should be aware of these developments and follow their progress, the evidence for each of these novel preventive treatment options is currently insufficient to make widespread recommendations. Changes in dental practice should be explored to see how oral health can be best supported through novel preventive systems. Further research is also required involving double-blind randomized controlled trials in order to bring further benefits of more effective caries control to patients. Implementation in practice should follow promptly as new techniques are shown to be clinically valuable for individual patients. Copyright 2009 S. Karger AG, Basel

  6. Retrieval options study

    Energy Technology Data Exchange (ETDEWEB)

    1980-03-01

    This Retrieval Options Study is part of the systems analysis activities of the Office of Nuclear Waste Isolation to develop the scientific and technological bases for radioactive waste repositories in various geologic media. The study considers two waste forms, high level waste and spent fuel, and defines various classes of waste retrieval and recovery. A methodology and data base are developed which allow the relative evaluation of retrieval and recovery costs and the following technical criteria: safety; technical feasibility; ease of retrieval; probable intact retrieval time; safeguards; monitoring; criticality; and licensability. A total of 505 repository options are defined and the cost and technical criteria evaluated utilizing a combination of facts and engineering judgments. The repositories evaluated are selected combinations of the following parameters: Geologic Media (salt, granite, basalt, shale); Retrieval Time after Emplacement (5 and 25 years); Emplacement Design (nominal hole, large hole, carbon steel canister, corrosion resistant canister, backfill in hole, nominal sleeves, thick wall sleeves); Emplacement Configuration (single vertical, multiple vertical, single horizontal, multiple horizontal, vaults; Thermal Considerations; (normal design, reduced density, once-through ventilation, recirculated ventilation); Room Backfill; (none, run-of-mine, early, 5 year delay, 25 year delay, decommissioned); and Rate of Retrieval; (same as emplacement, variably slower depending on repository/canister condition).

  7. Dimensionality reduction in conic section function neural network

    Indian Academy of Sciences (India)

    This paper details how dimensionality can be reduced in conic section function neural networks (CSFNN). This is particularly important for hardware implementation of networks. One of the main problems to be solved when considering the hardware design is the high connectivity requirement. If the effect that each of the ...

  8. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  9. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  10. Hardware Implementation of Serially Concatenated PPM Decoder

    Science.gov (United States)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  11. How to create successful Open Hardware projects - About White Rabbits and open fields

    CERN Document Server

    van der Bij, E; Lewis, J; Stana, T; Wlostowski, T; Gousiou, E; Serrano, J; Arruat, M; Lipinski, M M; Daniluk, G; Voumard, N; Cattin, M

    2013-01-01

    CERN's accelerator control group has embraced "Open Hardware" (OH) to facilitate peer review, avoid vendor lock-in and make support tasks scalable. A web-based tool for easing collaborative work was set up and the CERN OH Licence was created. New ADC, TDC, fine delay and carrier cards based on VITA and PCI-SIG standards were designed and drivers for Linux were written. Often industry was paid for developments, while quality and documentation was controlled by CERN. An innovative timing network was also developed with the OH paradigm. Industry now sells and supports these designs that find their way into new fields.

  12. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  13. Optional Defaultable Markets

    Directory of Open Access Journals (Sweden)

    Mohamed N. Abdelghani

    2017-10-01

    Full Text Available The paper deals with defaultable markets, one of the main research areas of mathematical finance. It proposes a new approach to the theory of such markets using techniques from the calculus of optional stochastic processes on unusual probability spaces, which was not presented before. The paper is a foundation paper and contains a number of fundamental results on modeling of defaultable markets, pricing and hedging of defaultable claims and results on the probability of default under such conditions. Moreover, several important examples are presented: a new pricing formula for a defaultable bond and a new pricing formula for credit default swap. Furthermore, some results on the absence of arbitrage for markets on unusual probability spaces and markets with default are also provided.

  14. Traditional preventive treatment options

    DEFF Research Database (Denmark)

    Longbottom, C; Ekstrand, K; Zero, D

    2009-01-01

    Preventive treatment options can be divided into primary, secondary and tertiary prevention techniques, which can involve patient- or professionally applied methods. These include: oral hygiene (instruction), pit and fissure sealants ('temporary' or 'permanent'), fluoride applications (patient...... prevention of caries in children, e.g. pit and fissure sealants and topically applied fluorides (including patient-applied fluoride toothpastes and professionally applied fluoride varnishes), but limited strong evidence for these techniques for secondary prevention--i.e. where early to established lesions...... conventional operative care, and since controlling the caries process prior to first restoration is the key to breaking the repair cycle and improving care for patients, future research should address the shortcomings in the current level of supporting evidence for the various traditional preventive treatment...

  15. Network Physics anounces first product to provide business-level management of the most complex and dynamic networks

    CERN Multimedia

    2003-01-01

    Network Physics, provider of business-level, traffic flow-based network management solutions, today announced the introduction of the Network Physics NP/BizFlow-1000. With the NP/BizFlow-1000, Fortune 1000 companies with complex and dynamic networks can analyze the flows that link business groups, critical applications, and network software and hardware (1 page).

  16. PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

    Directory of Open Access Journals (Sweden)

    O. Ahmed

    2011-01-01

    Full Text Available Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.

  17. Hardware design to accelerate PNG encoder for binary mask compression on FPGA

    Science.gov (United States)

    Kachouri, Rostom; Akil, Mohamed

    2015-02-01

    PNG (Portable Network Graphics) is a lossless compression method for real-world pictures. Since its specification, it continues to attract the interest of the image processing community. Indeed, PNG is an extensible file format for portable and well-compressed storage of raster images. In addition, it supports all of Black and White (binary mask), grayscale, indexed-color, and truecolor images. Within the framework of the Demat+ project which intend to propose a complete solution for storage and retrieval of scanned documents, we address in this paper a hardware design to accelerate the PNG encoder for binary mask compression on FPGA. For this, an optimized architecture is proposed as part of an hybrid software and hardware co-operating system. For its evaluation, the new designed PNG IP has been implemented on the ALTERA Arria II GX EP2AGX125EF35" FPGA. The experimental results show a good match between the achieved compression ratio, the computational cost and the used hardware resources.

  18. An improved non-uniformity correction algorithm and its hardware implementation on FPGA

    Science.gov (United States)

    Rong, Shenghui; Zhou, Huixin; Wen, Zhigang; Qin, Hanlin; Qian, Kun; Cheng, Kuanhong

    2017-09-01

    The Non-uniformity of Infrared Focal Plane Arrays (IRFPA) severely degrades the infrared image quality. An effective non-uniformity correction (NUC) algorithm is necessary for an IRFPA imaging and application system. However traditional scene-based NUC algorithm suffers the image blurring and artificial ghosting. In addition, few effective hardware platforms have been proposed to implement corresponding NUC algorithms. Thus, this paper proposed an improved neural-network based NUC algorithm by the guided image filter and the projection-based motion detection algorithm. First, the guided image filter is utilized to achieve the accurate desired image to decrease the artificial ghosting. Then a projection-based moving detection algorithm is utilized to determine whether the correction coefficients should be updated or not. In this way the problem of image blurring can be overcome. At last, an FPGA-based hardware design is introduced to realize the proposed NUC algorithm. A real and a simulated infrared image sequences are utilized to verify the performance of the proposed algorithm. Experimental results indicated that the proposed NUC algorithm can effectively eliminate the fix pattern noise with less image blurring and artificial ghosting. The proposed hardware design takes less logic elements in FPGA and spends less clock cycles to process one frame of image.

  19. Hardware locks for a real-time Java chip multiprocessor

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2016-01-01

    A software locking mechanism commonly protects shared resources for multithreaded applications. This mechanism can, especially in chip-multiprocessor systems, result in a large synchronization overhead. For real-time systems in particular, this overhead increases the worst-case execution time...... and may void a task set's schedulability. This paper presents 2 hardware locking mechanisms to reduce the worst-case time required to acquire and release synchronization locks. These solutions are implemented for the chip-multiprocessor version of the Java Optimized Processor. The 2 hardware locking...... mechanisms are compared with a software locking solution as well as the original locking system of the processor. The hardware cost and performance are evaluated for all presented locking mechanisms. The performance of the better-performing hardware locks is comparable with that of the original single global...

  20. A versatile hardware platform for brain computer interfaces.

    Science.gov (United States)

    Garcia, Pablo A; Haberman, Marcelo; Spinelli, Enrique M

    2010-01-01

    This article presents the development of a versatile hardware platform for brain computer interfaces (BCI). The aim of this work is to produce a small, autonomous and configurable BCI platform adaptable to the user's needs.

  1. Scientific Computing Using Consumer Video-Gaming Hardware Devices

    CERN Document Server

    Volkema, Glenn

    2016-01-01

    Commodity video-gaming hardware (consoles, graphics cards, tablets, etc.) performance has been advancing at a rapid pace owing to strong consumer demand and stiff market competition. Gaming hardware devices are currently amongst the most powerful and cost-effective computational technologies available in quantity. In this article, we evaluate a sample of current generation video-gaming hardware devices for scientific computing and compare their performance with specialized supercomputing general purpose graphics processing units (GPGPUs). We use the OpenCL SHOC benchmark suite, which is a measure of the performance of compute hardware on various different scientific application kernels, and also a popular public distributed computing application, Einstein@Home in the field of gravitational physics for the purposes of this evaluation.

  2. Hardware device to physical structure binding and authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  3. Hardware problems encountered in solar heating and cooling systems

    Science.gov (United States)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  4. Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

    NARCIS (Netherlands)

    Rauwerda, G.K.; Jha, N.K.; Heysters, P.M.; Smit, Gerardus Johannes Maria

    Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband

  5. Towards hardware-intrinsic security foundations and practice

    CERN Document Server

    Sadeghi, Ahmad-Reza; Tuyls, Pim

    2010-01-01

    Hardware-intrinsic security is a young field dealing with secure secret key storage. This book features contributions from researchers and practitioners with backgrounds in physics, mathematics, cryptography, coding theory and processor theory.

  6. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

    DEFF Research Database (Denmark)

    Bonnichsen, Lars Frydendal; Probst, Christian W.; Karlsson, Sven

    2015-01-01

    synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them...... efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than...... traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps....

  7. The $2000 Electric Powertrain Option-1 Program. Final technical report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1999-06-01

    This report describes the tasks accomplished as part of Northrop Grumman's TRP $2000 Electric Powertrain Option-1 program. Northrop Grumman has strived to achieve technology advances and development considered as high priority to the success of future electric vehicles. Northrop Grumman has achieved the intent of the program by taking several steps toward reducing the cost of the electric vehicle powertrain, demonstrating technologies in the form of hardware and introducing enhancements into production that are consistent with the needs of the market.

  8. A Survey on Hardware Implementations of Visual Object Trackers

    OpenAIRE

    El-Shafie, Al-Hussein A.; Habib, S. E. D.

    2017-01-01

    Visual object tracking is an active topic in the computer vision domain with applications extending over numerous fields. The main sub-tasks required to build an object tracker (e.g. object detection, feature extraction and object tracking) are computation-intensive. In addition, real-time operation of the tracker is indispensable for almost all of its applications. Therefore, complete hardware or hardware/software co-design approaches are pursued for better tracker implementations. This pape...

  9. Top Down Approach: SIMULINK Mixed Hardware / Software Design

    OpenAIRE

    Atat, Youssef; Rizk, Mostafa

    2012-01-01

    System-level design methodologies have been introduced as a solution to handle the design complexity of mixed Hardware / Software systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: System Simulink model, Transaction Simulink model, Macro architecture, and micro architecture. We used the MP3 CodeC application, to validate our approach and m...

  10. The aerospace energy systems laboratory: Hardware and software implementation

    Science.gov (United States)

    Glover, Richard D.; Oneil-Rood, Nora

    1989-01-01

    For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

  11. Hardware And Software For Development Of Robot Arms

    Science.gov (United States)

    Usikov, Daniel

    1995-01-01

    System of modular, reusable hardware and software assembled for use in developing remotely controlled robotic arms. Includes (1) central computer and peripheral equipment at control and monitoring station and (2) remote mechanical platform that supports robotic arm. Central computer controls motor drives of robotic arm, but optically, platform holds on-board computer for autonomous operation. Consists mostly of commercial hardware and software. Simulated results of commands viewed in three dimensions.

  12. Standards for School Networking.

    Science.gov (United States)

    Carlitz, Robert D.; And Others

    1995-01-01

    Discusses standards for the design and implementation of the electronic data networks developed for, and adopted by, the Pittsburgh Public Schools as district policy. Describes the layered approach which includes the physical layer, the protocol layer, and the application layer, and recommends hardware. A sidebar features court television in high…

  13. Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

    Directory of Open Access Journals (Sweden)

    Prasanna ViktorK

    2006-01-01

    Full Text Available By allowing parts of the applications to be executed either on soft processors (as software programs or on customized hardware peripherals attached to the processors, FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step, a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step, the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer/gate level ("low-level" implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab/Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10% estimation accuracy. Compared with the measured results, our experimental results show that the proposed technique achieves an average estimation error of less than 12%.

  14. Precontoured plating of clavicle fractures: decreased hardware-related complications?

    Science.gov (United States)

    VanBeek, Corinne; Boselli, Karen J; Cadet, Edwin R; Ahmad, Christopher S; Levine, William N

    2011-12-01

    Operative treatment of displaced midshaft clavicle fractures reportedly decreases the risk of symptomatic malunion, nonunion, and residual shoulder disability. Plating these fractures, however, may trade these complications for hardware-related problems. Low-profile anatomically precontoured plates may reduce the rates of plate prominence and hardware removal. We compared the outcomes after precontoured and noncontoured superior plating of acute displaced midshaft clavicle fractures. Primary outcomes were rate of plate prominence, rate of hardware removal, and rate of complications. Secondary outcomes were ROM and pain and function scores. We retrospectively reviewed 52 patients with 52 acute, displaced midshaft clavicle fractures treated with either noncontoured or precontoured superior clavicle plate fixation. Fourteen patients with noncontoured plates and 28 with precontoured plates were available for followup at a minimum of 1 year postoperatively. Postoperative assessment included ROM, radiographs, and subjective scores including visual analog scale for pain, American Shoulder and Elbow Surgeons questionnaire, and Simple Shoulder Test. Patients complained of prominent hardware in nine of 14 in the noncontoured group and nine of 28 in the precontoured group. Hardware removal rates were three of 14 in the noncontoured group and three of 28 in the precontoured group. Postoperative ROM and postoperative subjective scores were similar in the two groups. Precontoured plating versus noncontoured plating of displaced midshaft clavicle fractures results in a lower rate of plate prominence in patients who do not undergo hardware removal. Level III, therapeutic study. See Guidelines for Authors for a complete description of levels of evidence.

  15. On the use of inexact, pruned hardware in atmospheric modelling.

    Science.gov (United States)

    Düben, Peter D; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V; Palmer, T N

    2014-06-28

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.

  16. Hello! Kids Network around the World.

    Science.gov (United States)

    Lynes, Kristine

    1996-01-01

    Describes Kids Network, an educational network available from the National Geographic Society that allows students in grades four through six to become part of research teams that include students from around the world. Computer hardware requirements and a list of Kids Network research questions are listed in a sidebar. (JMV)

  17. Treatment Options for Narcolepsy.

    Science.gov (United States)

    Barateau, Lucie; Lopez, Régis; Dauvilliers, Yves

    2016-05-01

    Narcolepsy type 1 and narcolepsy type 2 are central disorders of hypersomnolence. Narcolepsy type 1 is characterized by excessive daytime sleepiness and cataplexy and is associated with hypocretin-1 deficiency. On the other hand, in narcolepsy type 2, cerebrospinal fluid hypocretin-1 levels are normal and cataplexy absent. Despite major advances in our understanding of narcolepsy mechanisms, its current management is only symptomatic. Treatment options may vary from a single drug that targets several symptoms, or multiple medications that each treats a specific symptom. In recent years, narcolepsy treatment has changed with the widespread use of modafinil/armodafinil for daytime sleepiness, antidepressants (selective serotonin and dual serotonin and noradrenalin reuptake inhibitors) for cataplexy, and sodium oxybate for both symptoms. Other psychostimulants can also be used, such as methylphenidate, pitolisant and rarely amphetamines, as third-line therapy. Importantly, clinically relevant subjective and objective measures of daytime sleepiness are required to monitor the treatment efficacy and to provide guidance on whether the treatment goals are met. Associated symptoms and comorbid conditions, such as hypnagogic/hypnopompic hallucinations, sleep paralysis, disturbed nighttime sleep, unpleasant dreams, REM- and non REM-related parasomnias, depressive symptoms, overweight/obesity, and obstructive sleep apnea, should also be taken into account and managed, if required. In the near future, the efficacy of new wake-promoting drugs, anticataplectic agents, hypocretin replacement therapy and immunotherapy at the early stages of the disease should also be evaluated.

  18. AFCI Options Study

    Energy Technology Data Exchange (ETDEWEB)

    R. Wigeland; T. Taiwo; M. Todosow; W. Halsey; J. Gehin

    2009-09-01

    This report describes the background and framework for both organizing the discussion and providing information on the potential for nuclear energy R&D to develop alternative nuclear fuel cycles that would address the issues with the current implementations of nuclear power, including nuclear waste disposal, proliferation risk, safety, security, economics, and sustainability. The disposition of used fuel is the cause of many of the concerns, and the possible approaches to used fuel management identify a number of basic technology areas that need to be considered. The basic science in each of the technology areas is discussed, emphasizing what science is currently available, where scientific knowledge may be insufficient, and especially to identify specific areas where transformational discoveries may allow achievement of performance goals not currently attainable. These discussions lead to the wide range of technical options that have been the basis for past and current research and development on advanced nuclear fuel cycles in the United States. The results of this work are then briefly reviewed to show the extent to which such approaches are capable of addressing the issues with nuclear power, the potential for moving further, and the inherent limitations.

  19. Incontinence Treatment: Newer Treatment Options

    Science.gov (United States)

    ... Bowel Incontinence Signs & Symptoms Symptoms of Incontinence Diarrhea Treatment Lifestyle Changes Dietary Tips Medication Bowel Management Biofeedback Surgical Treatments Newer Treatment Options Tips on Finding a Doctor ...

  20. Option price and market instability

    Science.gov (United States)

    Baaquie, Belal E.; Yu, Miao

    2017-04-01

    An option pricing formula, for which the price of an option depends on both the value of the underlying security as well as the velocity of the security, has been proposed in Baaquie and Yang (2014). The FX (foreign exchange) options price was empirically studied in Baaquie et al., (2014), and it was found that the model in general provides an excellent fit for all strike prices with a fixed model parameters-unlike the Black-Scholes option price Hull and White (1987) that requires the empirically determined implied volatility surface to fit the option data. The option price proposed in Baaquie and Cao Yang (2014) did not fit the data during the crisis of 2007-2008. We make a hypothesis that the failure of the option price to fit data is an indication of the market's large deviation from its near equilibrium behavior due to the market's instability. Furthermore, our indicator of market's instability is shown to be more accurate than the option's observed volatility. The market prices of the FX option for various currencies are studied in the light of our hypothesis.

  1. ORGANIZATIONAL DEVELOPMENT OPTIONS TOWARDS SUSTAINABILITY

    National Research Council Canada - National Science Library

    Patricia Ingrid, Keller

    2012-01-01

    .... So for the present study we researched the possible strategies, identifying those options to successfully integrate the dimensions of sustainability into organizational development from a systems...

  2. Real time hardware implementation of power converters for grid integration of distributed generation and STATCOM systems

    Science.gov (United States)

    Jaithwa, Ishan

    Deployment of smart grid technologies is accelerating. Smart grid enables bidirectional flows of energy and energy-related communications. The future electricity grid will look very different from today's power system. Large variable renewable energy sources will provide a greater portion of electricity, small DERs and energy storage systems will become more common, and utilities will operate many different kinds of energy efficiency. All of these changes will add complexity to the grid and require operators to be able to respond to fast dynamic changes to maintain system stability and security. This thesis investigates advanced control technology for grid integration of renewable energy sources and STATCOM systems by verifying them on real time hardware experiments using two different systems: d SPACE and OPAL RT. Three controls: conventional, direct vector control and the intelligent Neural network control were first simulated using Matlab to check the stability and safety of the system and were then implemented on real time hardware using the d SPACE and OPAL RT systems. The thesis then shows how dynamic-programming (DP) methods employed to train the neural networks are better than any other controllers where, an optimal control strategy is developed to ensure effective power delivery and to improve system stability. Through real time hardware implementation it is proved that the neural vector control approach produces the fastest response time, low overshoot, and, the best performance compared to the conventional standard vector control method and DCC vector control technique. Finally the entrepreneurial approach taken to drive the technologies from the lab to market via ORANGE ELECTRIC is discussed in brief.

  3. Space station data system analysis/architecture study. Task 2: Options development DR-5. Volume 1: Technology options

    Science.gov (United States)

    1985-01-01

    The second task in the Space Station Data System (SSDS) Analysis/Architecture Study is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This volume identifies the preferred options in the technology category and characterizes these options with respect to performance attributes, constraints, cost, and risk. The technology category includes advanced materials, processes, and techniques that can be used to enhance the implementation of SSDS design structures. The specific areas discussed are mass storage, including space and round on-line storage and off-line storage; man/machine interface; data processing hardware, including flight computers and advanced/fault tolerant computer architectures; and software, including data compression algorithms, on-board high level languages, and software tools. Also discussed are artificial intelligence applications and hard-wire communications.

  4. The Security Research of Digital Library Network

    Science.gov (United States)

    Zhang, Xin; Song, Ding-Li; Yan, Shu

    Digital library is a self-development needs for the modern library to meet the development requirements of the times, changing the way services and so on. digital library from the hardware, technology, management and other aspects to objective analysis of the factors of threats to digital library network security. We should face up the problems of digital library network security: digital library network hardware are "not hard", the technology of digital library is relatively lag, digital library management system is imperfect and other problems; the government should take active measures to ensure that the library funding, to enhance the level of network hardware, to upgrade LAN and prevention technology, to improve network control technology, network monitoring technology; to strengthen safety management concepts, to prefect the safety management system; and to improve the level of security management modernization for digital library.

  5. Simulation Of Networking Protocols On Software Emulated Network Stack

    Directory of Open Access Journals (Sweden)

    Hrushikesh Nimkar

    2015-08-01

    Full Text Available With the increasing number and complexity of network based applications the need to easy configuration development and integration of network applications has taken a high precedence. Trivial activities such as configuration can be carried out efficiently if network services are software based rather than hardware based. Project aims at enabling the network engineers to easily include network functionalities into hisher configuration and define hisher own network stack without using the kernel network stack. Having thought of this we have implemented two functionalities UPNP and MDNS. The multicast Domain Name System MDNS resolves host names to IP addresses within small ad-hoc networks and without having need of special DNS server and its configuration. MDNS application provides every host with functionality to register itself to the router make a multicast DNS request and its resolution. To make adding network devices and networked programs to a network as easy as it is to plug in a piece of hardware into a PC we make use of UPnP. The devices and programs find out about the network setup and other networked devices and programs through discovery and advertisements of services and configure themselves accordingly. UPNP application provides every host with functionality of discovering services of other hosts and serving requests on demand. To implement these applications we have used snabbswitch framework which an open source virtualized ethernet networking stack.

  6. SENHANCE: A Semantic Web framework for integrating social and hardware sensors in e-Health.

    Science.gov (United States)

    Pagkalos, Ioannis; Petrou, Loukas

    2016-09-01

    Self-reported data are very important in Healthcare, especially when combined with data from sensors. Social Networking Sites, such as Facebook, are a promising source of not only self-reported data but also social data, which are otherwise difficult to obtain. Due to their unstructured nature, providing information that is meaningful to health professionals from this source is a daunting task. To this end, we employ Social Network Applications as Social Sensors that gather structured data and use Semantic Web technologies to fuse them with hardware sensor data, effectively integrating both sources. We show that this combination of social and hardware sensor observations creates a novel space that can be used for a variety of feature-rich e-Health applications. We present the design of our prototype framework, SENHANCE, and our findings from its pilot application in the NutriHeAl project, where a Facebook app is integrated with Fitbit digital pedometers for Lifestyle monitoring. © The Author(s) 2015.

  7. Software and hardware package for justification of safety of nuclear legacy facilities

    Directory of Open Access Journals (Sweden)

    P.A. Blokhin

    2017-03-01

    Full Text Available Determination of future fate for nuclear legacy facilities is becoming an extremely important near-term issue. This includes decommissioning options to be identified based on detailed justifications of respective designs. No general practice has been developed in Russia to address such issues, while the initial steps to this end have been made as part of the federal target program “Ensuring Nuclear and Radiation Safety for 2008 and Up to the Year 2015”. Problems arising in justification of decommissioning options for such facilities, in terms of radiation protection and safety assessments both for the public and personnel, differ greatly from tasks involved in design of new nuclear installations. The explanation is a critical shortage of information on both nuclear legacy facilities as such and on the RW they contain. Extra complexities stem from regulatory requirements to facilities of this type having changed greatly since the time these facilities were built. This puts priority on development of approaches to justification of nuclear, radiation and environmental safety. A software and hardware package, OBOYAN, has been developed to solve a great variety of tasks to be addressed as part of this problem based on a combination of software and hardware tools enabling analysis and justification of the NLS safety in their current state and in a long term. The package's key components are computational modules used to model radiation fields, radionuclide migration and distribution of contamination in water and air, as well as to estimate human doses and risks. The purpose of the study is to describe the structure and the functional capabilities of the package and to provide examples of the package application.

  8. Treatment Options for Gout.

    Science.gov (United States)

    Engel, Bettina; Just, Johannes; Bleckwenn, Markus; Weckbecker, Klaus

    2017-03-31

    1-2% of adults in Germany suffer from gout. Gout is one of the few rheumatological diseases that can be cured. It arises through the deposition of uric acid crystals in joints as a result of hyperuricemia. Painful redness and swelling of the affected joints are typical findings. Multiple pertinent guidelines and treatment recommendations have been published, but there is reason to believe that patients with gout are not always treated accordingly. This review is based on relevant publications from the years 2000-2016 that were retrieved by a selective search in the Cochrane and PubMed databases. In a person with normal renal function, asymptomatic hyperuricemia is not an indication for treatment to lower the serum uric acid level. The drugs of first choice for acute gouty arthritis are nonsteroidal antiinflammatory drugs (NSAID), corticosteroids, and colchicine. Treatment with xanthine oxidase inhibitors (XOI) or uricosuric drugs is indicated for patients with a recurrent or severe course; the target uric acid value is lesinurad (approved in February 2016) in combination with XOI is a new treatment option that can be considered. Comprehensive patient education and counseling is an important component of the treatment of patients with gout. Regular laboratory follow-up is necessary as well. The prevalence of gout is rising around the world. Patients with gout could benefit greatly from consistent implementation of the existing treatment guidelines and recommendations. In the future, controlled trials should be conducted to determine the best time to start treatment and the optimal target level for the serum uric acid concentration in terms of a risk/benefit analysis.

  9. Hardware failure in patients with metastatic cancer to the spine.

    Science.gov (United States)

    Pedreira, Rachel; Abu-Bonsrah, Nancy; Karim Ahmed, A; De la Garza-Ramos, Rafael; Rory Goodwin, C; Gokaslan, Ziya L; Sacks, Justin; Sciubba, Daniel M

    2017-11-01

    The spine is the most common site of skeletal metastases, affecting approximately 30% of individuals with cancer. The aim of surgical treatment for metastatic spine disease is generally palliative to address pain and/or neurologic compromise, significantly improving patients' quality of life. Patients with metastatic spine disease, however, represent a vulnerable cohort and may have comorbidities or previous treatments that impair the structural integrity of spinal hardware. As such, identifying factors that may contribute to hardware failure is an essential component in treating individuals with metastatic spine disease. The aim of this study was to identify pre-operative risk factors associated with hardware failure in patients undergoing surgical treatment for metastatic spine disease. A retrospective cohort study was conducted to include patients surgically treated for metastatic spine tumors between 2003 and 2013, at a single institution. A univariate analysis was initially performed to identify associated factors. Any associated factor with a p-value failure of the spine instrumentation. 1 patient had metastatic prostate cancer, and 2 had metastatic breast cancer. Patient demographics, co-morbidities, tumor location, and primary tumor etiology were not found to be statistically significant, with respect to hardware failure. Predictive factors included in the multivariate model were other bone metastasis, visceral metastasis, brain metastasis, Modified Rankin scale, previous systemic chemotherapy, previous radiation to the spine, and mean survival. Previous radiation to the spine was the only factor to be significantly associated (p=0.029), present in all three patients with hardware failure. Of note, there was a trend indicating that patients with longer life expectancies were more likely to experience hardware failure (mean survival of 16.7months in non-failure cohort vs. 33months in failure cohort), though this did not achieve statistical significance due

  10. Village power options

    Energy Technology Data Exchange (ETDEWEB)

    Lilienthal, P. [National Renewable Energy Laboratory, Golden, CO (United States)

    1997-12-01

    This paper describes three different computer codes which have been written to model village power applications. The reasons which have driven the development of these codes include: the existance of limited field data; diverse applications can be modeled; models allow cost and performance comparisons; simulations generate insights into cost structures. The models which are discussed are: Hybrid2, a public code which provides detailed engineering simulations to analyze the performance of a particular configuration; HOMER - the hybrid optimization model for electric renewables - which provides economic screening for sensitivity analyses; and VIPOR the village power model - which is a network optimization model for comparing mini-grids to individual systems. Examples of the output of these codes are presented for specific applications.

  11. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  12. Color science demonstration kit from open source hardware and software

    Science.gov (United States)

    Zollers, Michael W.

    2014-09-01

    Color science is perhaps the most universally tangible discipline within the optical sciences for people of all ages. Excepting a small and relatively well-understood minority, we can see that the world around us consists of a multitude of colors; yet, describing the "what", "why", and "how" of these colors is not an easy task, especially without some sort of equally colorful visual aids. While static displays (e.g., poster boards, etc.) serve their purpose, there is a growing trend, aided by the recent permeation of small interactive devices into our society, for interactive and immersive learning. However, for the uninitiated, designing software and hardware for this purpose may not be within the purview of all optical scientists and engineers. Enter open source. Open source "anything" are those tools and designs -- hardware or software -- that are available and free to use, often without any restrictive licensing. Open source software may be familiar to some, but the open source hardware movement is relatively new. These are electronic circuit board designs that are provided for free and can be implemented in physical hardware by anyone. This movement has led to the availability of some relatively inexpensive, but quite capable, computing power for the creation of small devices. This paper will showcase the design and implementation of the software and hardware that was used to create an interactive demonstration kit for color. Its purpose is to introduce and demonstrate the concepts of color spectra, additive color, color rendering, and metamers.

  13. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  14. Analysis of Options Contract, Option Pricing in Agricultural Products

    Directory of Open Access Journals (Sweden)

    H. Tamidy

    2016-03-01

    Full Text Available Introduction: Risk is an essential component in the production and sale of agricultural products. Due to the nature of agricultural products, the people who act in this area including farmers and businesspersons encounter unpredictable fluctuations of prices. On the other hand, the firms that process agricultural products also face fluctuation of price of agricultural inputs. Given that the Canola is considered as one of the inputs of product processing factories, control of unpredictable fluctuations of the price of this product would increase the possibility of correct decision making for farmers and managers of food processing industries. The best available tool for control and management of the price risk is the use of future markets and options. It is evident that the pricing is the main pillar in every trade. Therefore, offering a fair price for the options will be very important. In fact, options trading in the options market create cost insurance stopped. In this way, which can reduce the risks of deflation created in the future, if the person entitled to the benefits of the price increase occurs in the future. Unlike the futures, market where the seller had to deliver the product on time, in the options market, there is no such compulsion. In addition, this is one of the strengths of this option contract, because if there is not enough product for delivery to the futures market as result of chilling, in due course, the farmers suffer, but in the options market there will be a loss. In this study, the setup options of rape, as a product, as well as inputs has been paid for industry. Materials and Methods: In this section. The selection criteria of the disposal of asset base for valuation of European put options and call option is been introduced. That for obtain this purpose, some characteristics of the goods must considered: 1-Unpredictable fluctuations price of underlying asset 2 -large underlying asset cash market 3- The possibility

  15. 77 FR 25319 - Commodity Options

    Science.gov (United States)

    2012-04-27

    ... the ability of the NFP Electric End Users to engage in energy and energy-related commodity options, or conditions the use of such trade options on the NFP Electric End Users qualifying as eligible contract participants, it will have a significant and detrimental effect on the NFP Electric End Users' ability to hedge...

  16. Bounds for Asian basket options

    Science.gov (United States)

    Deelstra, Griselda; Diallo, Ibrahima; Vanmaele, Michèle

    2008-09-01

    In this paper we propose pricing bounds for European-style discrete arithmetic Asian basket options in a Black and Scholes framework. We start from methods used for basket options and Asian options. First, we use the general approach for deriving upper and lower bounds for stop-loss premia of sums of non-independent random variables as in Kaas et al. [Upper and lower bounds for sums of random variables, Insurance Math. Econom. 27 (2000) 151-168] or Dhaene et al. [The concept of comonotonicity in actuarial science and finance: theory, Insurance Math. Econom. 31(1) (2002) 3-33]. We generalize the methods in Deelstra et al. [Pricing of arithmetic basket options by conditioning, Insurance Math. Econom. 34 (2004) 55-57] and Vanmaele et al. [Bounds for the price of discrete sampled arithmetic Asian options, J. Comput. Appl. Math. 185(1) (2006) 51-90]. Afterwards we show how to derive an analytical closed-form expression for a lower bound in the non-comonotonic case. Finally, we derive upper bounds for Asian basket options by applying techniques as in Thompson [Fast narrow bounds on the value of Asian options, Working Paper, University of Cambridge, 1999] and Lord [Partially exact and bounded approximations for arithmetic Asian options, J. Comput. Finance 10 (2) (2006) 1-52]. Numerical results are included and on the basis of our numerical tests, we explain which method we recommend depending on moneyness and time-to-maturity.

  17. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  18. XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Gaurav Purohit

    2016-01-01

    Full Text Available This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW implementation of new architecture uses Lookup Table (LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

  19. Bringing the power of dynamic languages to hardware control systems

    CERN Document Server

    Caicedo, J M; Neufeld, N

    2009-01-01

    Hardware control systems are normally programmed using high-performance languages like C or C++ and increasingly also Java. All these languages are strongly typed and compiled which brings usually good performance but at the cost of a longer development and testing cycle and the need for more programming expertise. Dynamic languages which were long thought to be too slow and not powerful enough for control purposes are, thanks to modern powerful computers and advanced implementation techniques, fast enough for many of these tasks. We present examples from the LHCb Experiment Control System (ECS), which is based on a commercial SCADA software. We have successfully used Python to integrate hardware devices into the ECS. We present the necessary lightweight middle-ware we have developed, including examples for controlling hardware and software devices. We also discuss the development cycle, tools used and compare the effort to traditional solutions.

  20. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  1. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah

    2017-02-22

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  2. Mapping of topological quantum circuits to physical hardware.

    Science.gov (United States)

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-04-11

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  3. Hardware Architecture Study for NASA's Space Software Defined Radios

    Science.gov (United States)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  4. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  5. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

    2016-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  6. Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs

    Directory of Open Access Journals (Sweden)

    Viktor K. Prasanna

    2006-09-01

    Full Text Available By allowing parts of the applications to be executed either on soft processors (as software programs or on customized hardware peripherals attached to the processors, FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper, we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step, a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step, the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer/gate level (“low-level” implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab/Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10% estimation accuracy. Compared with the measured results, our experimental results show that the proposed technique achieves an average estimation error of less than 12%.

  7. Options for small employers.

    Science.gov (United States)

    Miller, L; Miller, J

    1993-01-01

    Although offering health benefits is very expensive, many employers (small, medium, and large) make health care purchasing decisions based on very little information. This is largely because employers have not taken the time to learn how to be knowledgeable health care purchasers. Higher health care costs result when employers: purchase programs and services that employees and their dependents do not need and seldom use; pay (unknowingly) for services not offered in their benefit plan; accept and pay for ineffective cost containment programs that increase (not decrease) health care costs (remember that cost containment is a business in itself); make standard recommended changes (e.g., increased copays or deductibles) to their benefit plans, hoping to reduce costs (the result has been higher costs for too many employees); fail to assess whether health plans and insurance companies have effective internal quality and cost management programs; use financial incentives to encourage employees and dependents to enroll in managed care plans without examining whether the health plan or insurer used quality criteria, high standards, and capable processes in developing provider networks. (Capable processes consistently deliver quality products or services.) Most health plans and insurance companies have chosen providers based on their willingness to discount their charges, which places all parties (health plans or insurance companies, employers, and patients) at risk. Most of the problems listed above could be avoided if small employers based their health care purchasing decisions on information obtained from a careful analysis of needs and expectations.(ABSTRACT TRUNCATED AT 250 WORDS)

  8. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  9. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  10. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  11. Towards Shop Floor Hardware Reconfiguration for Industrial Collaborative Robots

    DEFF Research Database (Denmark)

    Schou, Casper; Madsen, Ole

    2016-01-01

    In this paper we propose a roadmap for hardware reconfiguration of industrial collaborative robots. As a flexible resource, the collaborative robot will often need transitioning to a new task. Our goal is, that this transitioning should be done by the shop floor operators, not highly specialized...... engineers. The hard- ware reconfiguration framework adopts a modular architecture for the collabo- rative robot which dictates a clear segmentation of the robot into well-defined exchangeable modules. Four main objectives for the hardware reconfiguration framework; 1) Modular architecture, 2) Module...

  12. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  13. Nios II hardware acceleration of the epsilon quadratic sieve algorithm

    Science.gov (United States)

    Meyer-Bäse, Uwe; Botella, Guillermo; Castillo, Encarnacion; García, Antonio

    2010-04-01

    The quadratic sieve (QS) algorithm is one of the most powerful algorithms to factor large composite primes used to break RSA cryptographic systems. The hardware structure of the QS algorithm seems to be a good fit for FPGA acceleration. Our new ɛ-QS algorithm further simplifies the hardware architecture making it an even better candidate for C2H acceleration. This paper shows our design results in FPGA resource and performance when implementing very long arithmetic on the Nios microprocessor platform with C2H acceleration for different libraries (GMP, LIP, FLINT, NRMP) and QS architecture choices for factoring 32-2048 bit RSA numbers.

  14. Hardware-assisted software clock synchronization for homogeneous distributed systems

    Science.gov (United States)

    Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

    1990-01-01

    A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

  15. On Issues of Precision for Hardware-based Volume Visualization

    Energy Technology Data Exchange (ETDEWEB)

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  16. Design of a Single Channel Modulated Wideband Converter for Wideband Spectrum Sensing: Theory, Architecture and Hardware Implementation.

    Science.gov (United States)

    Liu, Weisong; Huang, Zhitao; Wang, Xiang; Sun, Weichao

    2017-05-04

    In a cognitive radio sensor network (CRSN), wideband spectrum sensing devices which aims to effectively exploit temporarily vacant spectrum intervals as soon as possible are of great importance. However, the challenge of increasingly high signal frequency and wide bandwidth requires an extremely high sampling rate which may exceed today's best analog-to-digital converters (ADCs) front-end bandwidth. Recently, the newly proposed architecture called modulated wideband converter (MWC), is an attractive analog compressed sensing technique that can highly reduce the sampling rate. However, the MWC has high hardware complexity owing to its parallel channel structure especially when the number of signals increases. In this paper, we propose a single channel modulated wideband converter (SCMWC) scheme for spectrum sensing of band-limited wide-sense stationary (WSS) signals. With one antenna or sensor, this scheme can save not only sampling rate but also hardware complexity. We then present a new, SCMWC based, single node CR prototype System, on which the spectrum sensing algorithm was tested. Experiments on our hardware prototype show that the proposed architecture leads to successful spectrum sensing. And the total sampling rate as well as hardware size is only one channel's consumption of MWC.

  17. Making real options really work.

    Science.gov (United States)

    van Putten, Alexander B; MacMillan, Ian C

    2004-12-01

    As a way to value growth opportunities, real options have had a difficult time catching on with managers. Many CFOs believe the method ensures the overvaluation of risky projects. This concern is legitimate, but abandoning real options as a valuation model isn't the solution. Companies that rely solely on discounted cash flow (DCF) analysis underestimate the value of their projects and may fail to invest enough in uncertain but highly promising opportunities. CFOs need not--and should not--choose one approach over the other. Far from being a replacement for DCF analysis, real options are an essential complement, and a project's total value should encompass both. DCF captures a base estimate of value; real options take into account the potential for big gains. This is not to say that there aren't problems with real options. As currently applied, they focus almost exclusively on the risks associated with revenues, ignoring the risks associated with a project's costs. It's also true that option valuations almost always ignore assets that an initial investment in a subsequently abandoned project will often leave the company. In this article, the authors present a simple formula for combining DCF and option valuations that addresses these two problems. Using an integrated approach, managers will, in the long run, select better projects than their more timid competitors while keeping risk under control. Thus, they will outperform their rivals in both the product and the capital markets.

  18. A Computer Scientist’s Evaluation of Publically Available Hardware Trojan Benchmarks

    Science.gov (United States)

    2015-09-01

    in, design for trust, hardware intellectual property cores, Hardware Oriented Security and Trust, hardware synthesis, hardware Trojans, HDL...that this XOR gate also handles multiple bits, but that no visual cue is given. ...................................................16 Figure 4. Part...1-bit input clk is represented by graphical lows and highs, but multi-bit inputs are represented by numerical values. For clarity, we have edited

  19. Controversial reversal of nuclear option

    Directory of Open Access Journals (Sweden)

    Mesarović Miodrag

    2002-01-01

    Full Text Available Nuclear option is in a unique position to restore its original role of the main source of energy with an increased attention paid to the security of electricity supply as well as regulatory changes affecting fossil fuels, particularly with due introduction of climate change prevention measures. Recent developments indicate the advantages of nuclear option over other possible options in terms of sustainable development. However, a large number of controversial issues on nuclear energy make its reversal less clear. These are discussed with particular attention paid to recent developments worldwide, including the World Summit on Sustainable Development held in September 2002 in Johannesburg, South Africa.

  20. Exotic Options: a Chooser Option and its Pricing

    Directory of Open Access Journals (Sweden)

    Raimonda Martinkutė-Kaulienė

    2012-12-01

    Full Text Available Financial instruments traded in the markets and investors’ situation in such markets are getting more and more complex. This leads to more complex derivative structures used for hedging that are harder to analyze and which risk is harder managed. Because of the complexity of these instruments, the basic characteristics of many exotic options may sometimes be not clearly understood. Most scientific studies have been focused on developing models for pricing various types of exotic options, but it is important to study their unique characteristics and to understand them correctly in order to use them in proper market situations. The paper examines main aspects of options, emphasizing the variety of exotic options and their place in financial markets and risk management process. As the exact valuation of exotic options is quite difficult, the article deals with the theoretical and practical aspects of pricing of chooser options that suggest a broad range of usage and application in different market conditions. The calculations made in the article showed that the price of the chooser is closely correlated with the choice time and low correlated with its strike price. So the first mentioned factor should be taken into consideration when making appropriate hedging and investing decisions.

  1. Applying Model Based Systems Engineering to NASA's Space Communications Networks

    Science.gov (United States)

    Bhasin, Kul; Barnes, Patrick; Reinert, Jessica; Golden, Bert

    2013-01-01

    System engineering practices for complex systems and networks now require that requirement, architecture, and concept of operations product development teams, simultaneously harmonize their activities to provide timely, useful and cost-effective products. When dealing with complex systems of systems, traditional systems engineering methodology quickly falls short of achieving project objectives. This approach is encumbered by the use of a number of disparate hardware and software tools, spreadsheets and documents to grasp the concept of the network design and operation. In case of NASA's space communication networks, since the networks are geographically distributed, and so are its subject matter experts, the team is challenged to create a common language and tools to produce its products. Using Model Based Systems Engineering methods and tools allows for a unified representation of the system in a model that enables a highly related level of detail. To date, Program System Engineering (PSE) team has been able to model each network from their top-level operational activities and system functions down to the atomic level through relational modeling decomposition. These models allow for a better understanding of the relationships between NASA's stakeholders, internal organizations, and impacts to all related entities due to integration and sustainment of existing systems. Understanding the existing systems is essential to accurate and detailed study of integration options being considered. In this paper, we identify the challenges the PSE team faced in its quest to unify complex legacy space communications networks and their operational processes. We describe the initial approaches undertaken and the evolution toward model based system engineering applied to produce Space Communication and Navigation (SCaN) PSE products. We will demonstrate the practice of Model Based System Engineering applied to integrating space communication networks and the summary of its

  2. Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.

    Science.gov (United States)

    Rast, Alexander; Galluppi, Francesco; Davies, Sergio; Plana, Luis; Patterson, Cameron; Sharp, Thomas; Lester, David; Furber, Steve

    2011-11-01

    Dedicated hardware is becoming increasingly essential to simulate emerging very-large-scale neural models. Equally, however, it needs to be able to support multiple models of the neural dynamics, possibly operating simultaneously within the same system. This may be necessary either to simulate large models with heterogeneous neural types, or to simplify simulation and analysis of detailed, complex models in a large simulation by isolating the new model to a small subpopulation of a larger overall network. The SpiNNaker neuromimetic chip is a dedicated neural processor able to support such heterogeneous simulations. Implementing these models on-chip uses an integrated library-based tool chain incorporating the emerging PyNN interface that allows a modeller to input a high-level description and use an automated process to generate an on-chip simulation. Simulations using both LIF and Izhikevich models demonstrate the ability of the SpiNNaker system to generate and simulate heterogeneous networks on-chip, while illustrating, through the network-scale effects of wavefront synchronisation and burst gating, methods that can provide effective behavioural abstractions for large-scale hardware modelling. SpiNNaker's asynchronous virtual architecture permits greater scope for model exploration, with scalable levels of functional and temporal abstraction, than conventional (or neuromorphic) computing platforms. The complete system illustrates a potential path to understanding the neural model of computation, by building (and breaking) neural models at various scales, connecting the blocks, then comparing them against the biology: computational cognitive neuroscience. Copyright © 2011 Elsevier Ltd. All rights reserved.

  3. Distally based saphenous neurocutaneous perforator flap combined with vac therapy for soft tissue reconstruction and hardware salvage in the lower extremities.

    Science.gov (United States)

    Wen, Gen; Wang, Chun-Yang; Chai, Yi-Min; Cheng, Liang; Chen, Ming; Yi-Min, L V

    2013-11-01

    The complex wound with the exposed hardware and infection is one of the common complications after the internal fixation of the tibia fracture. The salvage of hardware and reconstruction of soft tissue defect remain challenging. In this report, we presented our experience on the use of the distally based saphenous neurocutaneous perforator flap combined with vacuum-assisted closure (VAC) therapy for the coverage of the soft tissue defect and the exposed hardware in the lower extremity with fracture. Between January 2008 and July 2010, seven patients underwent the VAC therapy followed by transferring a reversed saphenous neurocutaneous perforator flap for reconstruction of the wound with exposed hardware around the distal tibia. The sizes of the flaps ranged from 6 × 3 cm to 15 × 6 cm. Six flaps survived completely. Partial necrosis occurred in one patient. There were no other complications of repair and donor sites. Bone healing was achieved in all patients. In conclusion, the reversed saphenous neurocutaneous perfortor flaps combined with the VAC therapy might be one of the options to cover the complex wound with exposed hardware in the lower extremities. © 2013 Wiley Periodicals, Inc.

  4. Comprehensive risk reduction in patients with atrial fibrillation: emerging diagnostic and therapeutic options--a report from the 3rd Atrial Fibrillation Competence NETwork/European Heart Rhythm Association consensus conference

    DEFF Research Database (Denmark)

    Kirchhof, Paulus; Lip, Gregory Y H; Van Gelder, Isabelle C

    2012-01-01

    the proceedings of the 3rd Atrial Fibrillation NETwork (AFNET)/European Heart Rhythm Association (EHRA) consensus conference that convened over 60 scientists and representatives from industry to jointly discuss emerging therapeutic and diagnostic improvements to achieve better management of AF patients. The paper...... covers four chapters: (i) risk factors and risk markers for AF; (ii) pathophysiological classification of AF; (iii) relevance of monitored AF duration for AF-related outcomes; and (iv) perspectives and needs for implementing better antithrombotic therapy. Relevant published literature for each section...

  5. Towards automated construction of dependable software/hardware systems

    Energy Technology Data Exchange (ETDEWEB)

    Yakhnis, A.; Yakhnis, V. [Pioneer Technologies & Rockwell Science Center, Albuquerque, NM (United States)

    1997-11-01

    This report contains viewgraphs on the automated construction of dependable computer architecture systems. The outline of this report is: examples of software/hardware systems; dependable systems; partial delivery of dependability; proposed approach; removing obstacles; advantages of the approach; criteria for success; current progress of the approach; and references.

  6. Use of Heritage Hardware on MPCV Exploration Flight Test One

    Science.gov (United States)

    Rains, George Edward; Cross, Cynthia D.

    2011-01-01

    Due to an aggressive schedule for the first orbital test flight of an unmanned Orion capsule, known as Exploration Flight Test One (EFT1), combined with severe programmatic funding constraints, an effort was made to identify heritage hardware, i.e., already existing, flight-certified components from previous manned space programs, which might be available for use on EFT1. With the end of the Space Shuttle Program, no current means exists to launch Multi Purpose Logistics Modules (MPLMs) to the International Space Station (ISS), and so the inventory of many flight-certified Shuttle and MPLM components are available for other purposes. Two of these items are the Shuttle Ground Support Equipment Heat Exchanger (GSE Hx) and the MPLM cabin Positive Pressure Relief Assembly (PPRA). In preparation for the utilization of these components by the Orion Program, analyses and testing of the hardware were performed. The PPRA had to be analyzed to determine its susceptibility to pyrotechnic shock, and vibration testing had to be performed, since those environments are predicted to be significantly more severe during an Orion mission than those the hardware was originally designed to accommodate. The GSE Hx had to be tested for performance with the Orion thermal working fluids, which are different from those used by the Space Shuttle. This paper summarizes the certification of the use of heritage hardware for EFT1.

  7. Hardware Approach for Real Time Machine Stereo Vision

    Directory of Open Access Journals (Sweden)

    Michael Tornow

    2006-02-01

    Full Text Available Image processing is an effective tool for the analysis of optical sensor information for driver assistance systems and controlling of autonomous robots. Algorithms for image processing are often very complex and costly in terms of computation. In robotics and driver assistance systems, real-time processing is necessary. Signal processing algorithms must often be drastically modified so they can be implemented in the hardware. This task is especially difficult for continuous real-time processing at high speeds. This article describes a hardware-software co-design for a multi-object position sensor based on a stereophotogrammetric measuring method. In order to cover a large measuring area, an optimized algorithm based on an image pyramid is implemented in an FPGA as a parallel hardware solution for depth map calculation. Object recognition and tracking are then executed in real-time in a processor with help of software. For this task a statistical cluster method is used. Stabilization of the tracking is realized through use of a Kalman filter. Keywords: stereophotogrammetry, hardware-software co-design, FPGA, 3-d image analysis, real-time, clustering and tracking.

  8. Hardware realization of an SVM algorithm implemented in FPGAs

    Science.gov (United States)

    Wiśniewski, Remigiusz; Bazydło, Grzegorz; Szcześniak, Paweł

    2017-08-01

    The paper proposes a technique of hardware realization of a space vector modulation (SVM) of state function switching in matrix converter (MC), oriented on the implementation in a single field programmable gate array (FPGA). In MC the SVM method is based on the instantaneous space-vector representation of input currents and output voltages. The traditional computation algorithms usually involve digital signal processors (DSPs) which consumes the large number of power transistors (18 transistors and 18 independent PWM outputs) and "non-standard positions of control pulses" during the switching sequence. Recently, hardware implementations become popular since computed operations may be executed much faster and efficient due to nature of the digital devices (especially concurrency). In the paper, we propose a hardware algorithm of SVM computation. In opposite to the existing techniques, the presented solution applies COordinate Rotation DIgital Computer (CORDIC) method to solve the trigonometric operations. Furthermore, adequate arithmetic modules (that is, sub-devices) used for intermediate calculations, such as code converters or proper sectors selectors (for output voltages and input current) are presented in detail. The proposed technique has been implemented as a design described with the use of Verilog hardware description language. The preliminary results of logic implementation oriented on the Xilinx FPGA (particularly, low-cost device from Artix-7 family from Xilinx was used) are also presented.

  9. Visual basic application in computer hardware control and data ...

    African Journals Online (AJOL)

    Speech Recognition Technology enables text acquisition via users' dictation and knowledge gain through system dictation. In this paper the application of speech recognition technology in hardware device control and data acquisition is experimented using Visual Basic and the Speech Application Programming Interface ...

  10. Security Primitives for Reconfigurable Hardware-Based Systems

    Science.gov (United States)

    2010-05-01

    based architectures. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS ’07). FIORIN, L...and System Synthesis (CODES+ ISSS ’07). Received April 2008; revised October 2008; accepted March 2009 ACM Transactions on Reconfigurable Technology and Systems, Vol. 3, No. 2, Article 10, Pub. date: May 2010.

  11. Graph based communication analysis for hardware/software codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1999-01-01

    In this paper we present a coarse grain CDFG (Control/Data Flow Graph) model suitable for hardware/software partitioning of single processes and demonstrate how it is necessary to perform various transformations on the graph structure before partitioning in order to achieve a structure that allows...

  12. Detecting System of Nested Hardware Virtual Machine Monitor

    Directory of Open Access Journals (Sweden)

    Artem Vladimirovich Iuzbashev

    2015-03-01

    Full Text Available Method of nested hardware virtual machine monitor detection was proposed in this work. The method is based on HVM timing attack. In case of HVM presence in system, the number of different instruction sequences execution time values will increase. We used this property as indicator in our detection.

  13. Hardware prototype with component specification and usage description

    NARCIS (Netherlands)

    Azam, Tre; Aswat, Soyeb; Klemke, Roland; Sharma, Puneet; Wild, Fridolin

    2017-01-01

    Following on from D3.1 and the final selection of sensors, in this D3.2 report we present the first version of the experience capturing hardware prototype design and API architecture taking into account the current limitations of the Hololens not being available until early next month in time for

  14. Know Your Personal Computer The Personal Computer Hardware

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 1; Issue 2. Know Your Personal Computer The Personal Computer Hardware. Siddhartha Kumar ... Author Affiliations. Siddhartha Kumar Ghoshal1. Supercomputer Education and Research Centre, Indian Institute of Science, Bangalore 560 012, India.

  15. Smart Home Hardware-in-the-Loop Testing

    Energy Technology Data Exchange (ETDEWEB)

    Pratt, Annabelle

    2017-07-12

    This presentation provides a high-level overview of NREL's smart home hardware-in-the-loop testing. It was presented at the Fourth International Workshop on Grid Simulator Testing of Energy Systems and Wind Turbine Powertrains, held April 25-26, 2017, hosted by NREL and Clemson University at the Energy Systems Integration Facility in Golden, Colorado.

  16. Foundations of digital signal processing theory, algorithms and hardware design

    CERN Document Server

    Gaydecki, Patrick

    2005-01-01

    An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.

  17. Hardware-in-the-loop testing of marine control system

    Directory of Open Access Journals (Sweden)

    Roger Skjetne

    2006-10-01

    Full Text Available Hardware-in-the-Loop (HIL testing is proposed as a new methodology for verification and certification of marine control systems. Formalizing such testing necessitates the development of a vocabulary and set of definitions. This paper treats these issues by constructing a framework suitable for industrial HIL test applications and certification of marine systems.

  18. Implementing Strategic Management of Producibility in Military Hardware Design

    Science.gov (United States)

    1985-05-01

    APPROVAL L~og No. OF TECHNICAL ARTICLE, PAPER OR SPEECH TO BE PRESENTED OR PUBLISH ED SubmIt 4 bcop" of Clearance Request and 2 copies of * spech or paper...in many free world nations. The common denominator is recognition that the development and acquisition process of military hardware mandates a team

  19. RDV77 VLBA Hardware/Software Correlator Comparisons

    Science.gov (United States)

    Gordon, David

    2010-01-01

    Results of a hardware vs. software correlation of the RDV77 session are presented. Group delays are found to agree (WRMS differences) at an average level of 4.2 psec and with a noise floor of 2.5 psec. These RDV77 comparisons agree well with several previous correlator comparison studies.

  20. An Integrated Hardware Array for Very High Speed Logic Simulation

    Directory of Open Access Journals (Sweden)

    E. Scott Fehr

    1996-01-01

    boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

  1. Leveraging Information Technology. Track VI: Hardware/Software Strategies.

    Science.gov (United States)

    CAUSE, Boulder, CO.

    Seven papers from the 1987 CAUSE conference's Track VI, Hardware/Software Strategies, are presented. They include: "Integrated Systems--The Next Steps" (Morris A. Hicks); "Administrative Microcomputing--Roads Traveled, Lessons Learned" (David L. Smallen); "Murphy's First Law and Its Application to Administrative…

  2. TreeBASIS Feature Descriptor and Its Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Spencer Fowers

    2014-01-01

    Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

  3. Efficient architecture for spike sorting in reconfigurable hardware.

    Science.gov (United States)

    Hwang, Wen-Jyi; Lee, Wei-Hao; Lin, Shiow-Jyu; Lai, Sheng-Ying

    2013-11-01

    This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.

  4. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...

  5. 3D IBFV : Hardware-Accelerated 3D Flow Visualization

    NARCIS (Netherlands)

    Telea, Alexandru; Wijk, Jarke J. van

    2003-01-01

    We present a hardware-accelerated method for visualizing 3D flow fields. The method is based on insertion, advection, and decay of dye. To this aim, we extend the texture-based IBFV technique for 2D flow visualization in two main directions. First, we decompose the 3D flow visualization problem in a

  6. Alternate Protocol for Detecting Biological Contamination on Sensitive Hardware

    Science.gov (United States)

    Berlin, David; Lalime, Erin; Carosso, Nancy

    2015-01-01

    The purpose of this project is to develop a sterile water based rapid bioburden test. Contamination engineers use two tests to assess the level of biological contamination on hardware: the rapid five minute bioburden test, which is a molecular screening for Adenosine triphosphate (ATP), a molecule found in all cells on the hardware, and a slower colony growth test, which is used to give a more accurate representation of the amount of microbes on the hardware. However, the rapid bioburden test has limited application because it leaves a residue that can be detrimental to sensitive hardware. This can cause project delays while waiting for the results from the three day colony growth test. We address this problem by adapting the commercial germicide based ATP system to a sterile water based system. The test works by reacting ATP with D-Luciferin and Luciferase protein to yield light. The light is then detected by a luminometer that outputs a Relative Light Unit (RLU) amount depending on how much ATP is present. To analyze the effectiveness of the new test, we developed a correlation between amounts of ATP and the RLU produced using the germicide based system. From these experiments, we've generated a consistent relationship between the two in the form of a power curve. From there, we developed a correlation curve between the amount of colonies and the RLU they produced. Initial tests of the new protocol have shown that the water based system isn't as sensitive as the germicide based test.

  7. Osseodensification for enhancement of spinal surgical hardware fixation.

    Science.gov (United States)

    Lopez, Christopher D; Alifarag, Adham M; Torroni, Andrea; Tovar, Nick; Diaz-Siso, J Rodrigo; Witek, Lukasz; Rodriguez, Eduardo D; Coelho, Paulo G

    2017-05-01

    Integration between implant and bone is an essential concept for osseous healing requiring hardware placement. A novel approach to hardware implantation, termed osseodensification, is described here as an effective alternative. 12 sheep averaging 65kg had fixation devices installed in their C2, C3, and C4 vertebral bodies; each device measured 4mm diameter×10mm length. The left-sided vertebral body devices were implanted using regular surgical drilling (R) while the right-sided devices were implanted using osseodensification drilling (OD). The C2 and C4 vertebra provided the t=0 in vivo time point, while the C3 vertebra provided the t=3 and t=6 week time points, in vivo. Structural competence of hardware was measured using biomechanical testing of pullout strength, while the quality and degree of new bone formation and remodeling was assessed via histomorphometry. Pullout strength demonstrated osseodensification drilling to provide superior anchoring when compared to the control group collapsed over time with statistical significance (phardware implantation encourages assessment of current surgical approaches to hardware implantation. Copyright © 2017 Elsevier Ltd. All rights reserved.

  8. Hardware Location and Clinical Outcome in Ulna Shortening Osteotomy.

    Science.gov (United States)

    Megerle, Kai; Hellmich, Susanne; Germann, Günter; Sauerbier, Michael

    2015-10-01

    The purpose of this study was to investigate the influence of plate location during ulna shortening osteotomy on the incidence of hardware irritation and clinical outcome. Forty patients (17 women, 23 men; mean age, 47 years) who underwent a shortening osteotomy of the ulna due to idiopathic ulna impaction syndrome were examined after a mean of 36 months. All complications and secondary procedures were extracted from the patients' records. The rate of hardware removal was higher in patients who had a dorsal placement of the plate in comparison with ulnar or palmar placements, although this difference was not statistically significant. Apart from hardware irritation, there were 4 nonunions, 1 secondary osteoarthritis of the distal radioulnar joint, and 1 case of chronic irritation of the dorsal branch of the ulnar nerve, which required secondary surgery. The incidence of secondary surgery other than hardware removal was not significantly related to the original location of the plate. Secondary surgery after ulnar shortening osteotomy is common. However, we found no difference in clinical outcomes based on plate location.

  9. Hiding State in CλaSH Hardware Descriptions

    NARCIS (Netherlands)

    Gerards, Marco Egbertus Theodorus; Baaij, C.P.R.; Kuper, Jan; Kooijman, Matthijs

    Synchronous hardware can be modelled as a mapping from input and state to output and a new state, such mappings are referred to as transition functions. It is natural to use a functional language to implement transition functions. The CaSH compiler is capable of translating transition functions to

  10. A Cache-Based Hardware Accelerator for Memory Data Movements

    NARCIS (Netherlands)

    Duarte, F.

    2008-01-01

    This dissertation presents a hardware accelerator that is able to accelerate large (including non-parallel) memory data movements, in particular memory copies, performed traditionally by the processors. As todays processors are tied with or have integrated caches with varying sizes (from several

  11. Cache-based memory copy hardware accelerator for multicore systems

    NARCIS (Netherlands)

    Duarte, F.; Wong, S.

    2010-01-01

    In this paper, we present a new architecture of the cache-based memory copy hardware accelerator in a multicore system supporting message passing. The accelerator is able to accelerate memory data movements, in particular memory copies. We perform an analytical analysis based on open-queuing theory

  12. Chip-Multiprocessor Hardware Locks for Safety-Critical Java

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2013-01-01

    and may void a task set's schedulability. In this paper we present a hardware locking mechanism to reduce the synchronization overhead. The solution is implemented for the chip-multiprocessor version of the Java Optimized Processor in the context of safety-critical Java. The implementation is compared...

  13. Hardware Descriptive Languages: An Efficient Approach to Device ...

    African Journals Online (AJOL)

    Contemporarily, owing to astronomical advancements in the very large scale integration (VLSI) market segments, hardware engineers are now focusing on how to develop their new digital system designs in programmable languages like very high speed integrated circuit hardwaredescription language (VHDL) and Verilog ...

  14. Tattoo Removal: Options and Results

    Science.gov (United States)

    ... Products For Consumers Home For Consumers Consumer Updates Tattoo Removal: Options and Results Share Tweet Linkedin Pin ... for tattoo lightening or removal. A Rise in Tattoo Removal According to a Harris Interactive poll conducted ...

  15. Essential Tremor (ET): Surgical Options

    Science.gov (United States)

    ... option for severe depression, epilepsy, Tourette’s syndrome, stroke, addiction, and dementia. Top Focused Ultrasound Thalamotomy The FDA ... ultrasound but in a very different way. This technology uses multiple beams of sound focused in on ...

  16. Treatment Option Overview (Anal Cancer)

    Science.gov (United States)

    ... Cancer Treatment Anal Cancer Prevention Research Anal Cancer Treatment (PDQ®)–Patient Version General Information About Anal Cancer ... factors affect the prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends on ...

  17. Treatment Option Overview (Rectal Cancer)

    Science.gov (United States)

    ... Colorectal Cancer Colorectal Cancer Screening Research Rectal Cancer Treatment (PDQ®)–Patient Version General Information About Rectal Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  18. Treatment Options for Kaposi Sarcoma

    Science.gov (United States)

    ... Treatment Childhood Vascular Tumors Treatment Research Kaposi Sarcoma Treatment (PDQ®)–Patient Version General Information About Kaposi Sarcoma ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  19. Treatment Option Overview (Vulvar Cancer)

    Science.gov (United States)

    ... Health Professional Vulvar Cancer Treatment Research Vulvar Cancer Treatment (PDQ®)–Patient Version General Information About Vulvar Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  20. Treatment Options for Actinic Keratosis

    Science.gov (United States)

    ... Skin Cancer Skin Cancer Screening Research Skin Cancer Treatment (PDQ®)–Patient Version General Information About Skin Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends mostly ...

  1. Treatment Option Overview (Esophageal Cancer)

    Science.gov (United States)

    ... Cancer Prevention Esophageal Cancer Screening Research Esophageal Cancer Treatment (PDQ®)–Patient Version General Information About Esophageal Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  2. Treatment Option Overview (Bladder Cancer)

    Science.gov (United States)

    ... Cancer Treatment Bladder Cancer Screening Research Bladder Cancer Treatment (PDQ®)–Patient Version General Information About Bladder Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends on ...

  3. Treatment Option Overview (Prostate Cancer)

    Science.gov (United States)

    ... Prostate Cancer Prostate Cancer Screening Research Prostate Cancer Treatment (PDQ®)–Patient Version General Information About Prostate Cancer ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  4. Treatment Option Overview (Uterine Sarcoma)

    Science.gov (United States)

    ... Cancer Prevention Endometrial Cancer Screening Research Uterine Sarcoma Treatment (PDQ®)–Patient Version General Information About Uterine Sarcoma ... Certain factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment ...

  5. FS65 Disposition Option Report

    Energy Technology Data Exchange (ETDEWEB)

    Wenz, Tracy R. [Los Alamos National Lab. (LANL), Los Alamos, NM (United States)

    2015-09-25

    This report outlines the options for dispositioning the MOX fuel stored in FS65 containers at LANL. Additional discussion regarding the support equipment for loading and unloading the FS65 transport containers is included at the end of the report.

  6. Integrated Hardware and Software for No-Loss Computing

    Science.gov (United States)

    James, Mark

    2007-01-01

    When an algorithm is distributed across multiple threads executing on many distinct processors, a loss of one of those threads or processors can potentially result in the total loss of all the incremental results up to that point. When implementation is massively hardware distributed, then the probability of a hardware failure during the course of a long execution is potentially high. Traditionally, this problem has been addressed by establishing checkpoints where the current state of some or part of the execution is saved. Then in the event of a failure, this state information can be used to recompute that point in the execution and resume the computation from that point. A serious problem arises when one distributes a problem across multiple threads and physical processors is that one increases the likelihood of the algorithm failing due to no fault of the scientist but as a result of hardware faults coupled with operating system problems. With good reason, scientists expect their computing tools to serve them and not the other way around. What is novel here is a unique combination of hardware and software that reformulates an application into monolithic structure that can be monitored in real-time and dynamically reconfigured in the event of a failure. This unique reformulation of hardware and software will provide advanced aeronautical technologies to meet the challenges of next-generation systems in aviation, for civilian and scientific purposes, in our atmosphere and in atmospheres of other worlds. In particular, with respect to NASA s manned flight to Mars, this technology addresses the critical requirements for improving safety and increasing reliability of manned spacecraft.

  7. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    Science.gov (United States)

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  8. Overview of PWR chemistry options

    Energy Technology Data Exchange (ETDEWEB)

    Nordmann, F.; Stutzmann, A.; Bretelle, J.L. [Electricite de France, Central Labs. (France)

    2002-07-01

    EDF Central Laboratories, in charge of engineering in chemistry, of defining the chemistry specifications and studying the operation feedback and improvement for 58 PWR units, have the opportunity to evaluate many options of operation developed and applied all around the world. Thanks to these international relationships and to the benefit of a large feedback from many units, some general evaluation of the various options is discussed in this paper. (authors)

  9. Merger options and risk arbitrage

    OpenAIRE

    Van Tassel, Peter

    2016-01-01

    Option prices embed predictive content for the outcomes of pending mergers and acquisitions. This is particularly important in merger arbitrage, where deal failure is a key risk. In this paper, I propose a dynamic asset pricing model that exploits the joint information in target stock and option prices to forecast deal outcomes. By analyzing how deal announcements affect the level and higher moments of target stock prices, the model yields better forecasts than existing methods. In addition, ...

  10. Hardware-in-the-Loop Simulation of a Distribution System with Air Conditioners under Model Predictive Control: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Sparn, Bethany F [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Ruth, Mark F [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Krishnamurthy, Dheepak [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Pratt, Annabelle [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Lunacek, Monte S [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Jones, Wesley B [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Wu, Hongyu [Kansas State University; Mittal, Saurabh [Mitre Corporation; Marks, Jesse [University of Missouri

    2017-08-01

    Many have proposed that responsive load provided by distributed energy resources (DERs) and demand response (DR) are an option to provide flexibility to the grid and especially to distribution feeders. However, because responsive load involves a complex interplay between tariffs and DER and DR technologies, it is challenging to test and evaluate options without negatively impacting customers. This paper describes a hardware-in-the-loop (HIL) simulation system that has been developed to reduce the cost of evaluating the impact of advanced controllers (e.g., model predictive controllers) and technologies (e.g., responsive appliances). The HIL simulation system combines large-scale software simulation with a small set of representative building equipment hardware. It is used to perform HIL simulation of a distribution feeder and the loads on it under various tariff structures. In the reported HIL simulation, loads include many simulated air conditioners and one physical air conditioner. Independent model predictive controllers manage operations of all air conditioners under a time-of-use tariff. Results from this HIL simulation and a discussion of future development work of the system are presented.

  11. Network testbed creation and validation

    Energy Technology Data Exchange (ETDEWEB)

    Thai, Tan Q.; Urias, Vincent; Van Leeuwen, Brian P.; Watts, Kristopher K.; Sweeney, Andrew John

    2017-03-21

    Embodiments of network testbed creation and validation processes are described herein. A "network testbed" is a replicated environment used to validate a target network or an aspect of its design. Embodiments describe a network testbed that comprises virtual testbed nodes executed via a plurality of physical infrastructure nodes. The virtual testbed nodes utilize these hardware resources as a network "fabric," thereby enabling rapid configuration and reconfiguration of the virtual testbed nodes without requiring reconfiguration of the physical infrastructure nodes. Thus, in contrast to prior art solutions which require a tester manually build an emulated environment of physically connected network devices, embodiments receive or derive a target network description and build out a replica of this description using virtual testbed nodes executed via the physical infrastructure nodes. This process allows for the creation of very large (e.g., tens of thousands of network elements) and/or very topologically complex test networks.

  12. Network testbed creation and validation

    Science.gov (United States)

    Thai, Tan Q.; Urias, Vincent; Van Leeuwen, Brian P.; Watts, Kristopher K.; Sweeney, Andrew John

    2017-04-18

    Embodiments of network testbed creation and validation processes are described herein. A "network testbed" is a replicated environment used to validate a target network or an aspect of its design. Embodiments describe a network testbed that comprises virtual testbed nodes executed via a plurality of physical infrastructure nodes. The virtual testbed nodes utilize these hardware resources as a network "fabric," thereby enabling rapid configuration and reconfiguration of the virtual testbed nodes without requiring reconfiguration of the physical infrastructure nodes. Thus, in contrast to prior art solutions which require a tester manually build an emulated environment of physically connected network devices, embodiments receive or derive a target network description and build out a replica of this description using virtual testbed nodes executed via the physical infrastructure nodes. This process allows for the creation of very large (e.g., tens of thousands of network elements) and/or very topologically complex test networks.

  13. Logistic control in automated transportation networks

    NARCIS (Netherlands)

    Ebben, Mark

    2001-01-01

    Increasing congestion problems lead to a search for alternative transportation systems. Automated transportation networks, possibly underground, are an option. Logistic control systems are essential for future implementations of such automated transportation networks. This book contributes to the

  14. Software and hardware complex for research and management of the separation process

    Science.gov (United States)

    Borisov, A. P.

    2018-01-01

    The article is devoted to the development of a program for studying the operation of an asynchronous electric drive using vector-algorithmic switching of windings, as well as the development of a hardware-software complex for controlling parameters and controlling the speed of rotation of an asynchronous electric drive for investigating the operation of a cyclone. To study the operation of an asynchronous electric drive, a method was used in which the average value of flux linkage is found and a method for vector-algorithmic calculation of the power and electromagnetic moment of an asynchronous electric drive feeding from a single-phase network is developed, with vector-algorithmic commutation, and software for calculating parameters. The software part of the complex allows to regulate the speed of rotation of the motor by vector-algorithmic switching of transistors or, using pulse-width modulation (PWM), set any engine speed. Also sensors are connected to the hardware-software complex at the inlet and outlet of the cyclone. The developed cyclone with an inserted complex allows to receive high efficiency of product separation at various entrance speeds. At an inlet air speed of 18 m / s, the cyclone’s maximum efficiency is achieved. For this, it is necessary to provide the rotational speed of an asynchronous electric drive with a frequency of 45 Hz.

  15. Neuromorphic Hardware Architecture Using the Neural Engineering Framework for Pattern Recognition.

    Science.gov (United States)

    Wang, Runchun; Thakur, Chetan Singh; Cohen, Gregory; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, Andre

    2017-06-01

    We present a hardware architecture that uses the neural engineering framework (NEF) to implement large-scale neural networks on field programmable gate arrays (FPGAs) for performing massively parallel real-time pattern recognition. NEF is a framework that is capable of synthesising large-scale cognitive systems from subnetworks and we have previously presented an FPGA implementation of the NEF that successfully performs nonlinear mathematical computations. That work was developed based on a compact digital neural core, which consists of 64 neurons that are instantiated by a single physical neuron using a time-multiplexing approach. We have now scaled this approach up to build a pattern recognition system by combining identical neural cores together. As a proof of concept, we have developed a handwritten digit recognition system using the MNIST database and achieved a recognition rate of 96.55%. The system is implemented on a state-of-the-art FPGA and can process 5.12 million digits per second. The architecture and hardware optimisations presented offer high-speed and resource-efficient means for performing high-speed, neuromorphic, and massively parallel pattern recognition and classification tasks.

  16. A portable hardware-in-the-loop (HIL) device for automotive diagnostic control systems.

    Science.gov (United States)

    Palladino, A; Fiengo, G; Lanzo, D

    2012-01-01

    In-vehicle driving tests for evaluating the performance and diagnostic functionalities of engine control systems are often time consuming, expensive, and not reproducible. Using a hardware-in-the-loop (HIL) simulation approach, new control strategies and diagnostic functions on a controller area network (CAN) line can be easily tested in real time, in order to reduce the effort and the cost of the testing phase. Nowadays, spark ignition engines are controlled by an electronic control unit (ECU) with a large number of embedded sensors and actuators. In order to meet the rising demand of lower emissions and fuel consumption, an increasing number of control functions are added into such a unit. This work aims at presenting a portable electronic environment system, suited for HIL simulations, in order to test the engine control software and the diagnostic functionality on a CAN line, respectively, through non-regression and diagnostic tests. The performances of the proposed electronic device, called a micro hardware-in-the-loop system, are presented through the testing of the engine management system software of a 1.6 l Fiat gasoline engine with variable valve actuation for the ECU development version. Copyright © 2011 ISA. Published by Elsevier Ltd. All rights reserved.

  17. Design and Control of Compliant Tensegrity Robots Through Simulation and Hardware Validation

    Science.gov (United States)

    Caluwaerts, Ken; Despraz, Jeremie; Iscen, Atil; Sabelhaus, Andrew P.; Bruce, Jonathan; Schrauwen, Benjamin; Sunspiral, Vytas

    2014-01-01

    To better understand the role of tensegrity structures in biological systems and their application to robotics, the Dynamic Tensegrity Robotics Lab at NASA Ames Research Center has developed and validated two different software environments for the analysis, simulation, and design of tensegrity robots. These tools, along with new control methodologies and the modular hardware components developed to validate them, are presented as a system for the design of actuated tensegrity structures. As evidenced from their appearance in many biological systems, tensegrity ("tensile-integrity") structures have unique physical properties which make them ideal for interaction with uncertain environments. Yet these characteristics, such as variable structural compliance, and global multi-path load distribution through the tension network, make design and control of bio-inspired tensegrity robots extremely challenging. This work presents the progress in using these two tools in tackling the design and control challenges. The results of this analysis includes multiple novel control approaches for mobility and terrain interaction of spherical tensegrity structures. The current hardware prototype of a six-bar tensegrity, code-named ReCTeR, is presented in the context of this validation.

  18. Design and implementation of a local computer network

    Energy Technology Data Exchange (ETDEWEB)

    Fortune, P. J.; Lidinsky, W. P.; Zelle, B. R.

    1977-01-01

    An intralaboratory computer communications network was designed and is being implemented at Argonne National Laboratory. Parameters which were considered to be important in the network design are discussed; and the network, including its hardware and software components, is described. A discussion of the relationship between computer networks and distributed processing systems is also presented. The problems which the network is designed to solve and the consequent network structure represent considerations which are of general interest. 5 figures.

  19. Improving the Stability and Accuracy of Power Hardware-in-the-Loop Simulation Using Virtual Impedance Method

    Directory of Open Access Journals (Sweden)

    Xiaoming Zha

    2016-11-01

    Full Text Available Power hardware-in-the-loop (PHIL systems are advanced, real-time platforms for combined software and hardware testing. Two paramount issues in PHIL simulations are the closed-loop stability and simulation accuracy. This paper presents a virtual impedance (VI method for PHIL simulations that improves the simulation’s stability and accuracy. Through the establishment of an impedance model for a PHIL simulation circuit, which is composed of a voltage-source converter and a simple network, the stability and accuracy of the PHIL system are analyzed. Then, the proposed VI method is implemented in a digital real-time simulator and used to correct the combined impedance in the impedance model, achieving higher stability and accuracy of the results. The validity of the VI method is verified through the PHIL simulation of two typical PHIL examples.

  20. Financing School Infrastructure: What Are the Options?

    Science.gov (United States)

    Sielke, Catherine C.

    2001-01-01

    Describes local, state, and federal school infrastructure funding options. Local funding options include bond issues, special local-option sales taxes, and voter-approved mills and sinking funds. Describes use of federal Qualified Zone Academy Bonds. (PKP)

  1. Options for the second commitment period of the Kyoto Protocol

    Energy Technology Data Exchange (ETDEWEB)

    Hoehne, Niklas; Phylipsen, Dian; Ullrich, Simone; Blok, Kornelis

    2005-02-15

    This study assesses available options for the second commitment period of the Kyoto Protocol. The study includes the following sections: An introduction, an overview of proposals and establishing a network, analysis of interests of countries, selected country case studies, an overview of the issues to be considered, options for adaptation to climate change, a new approach ''Common but Differentiated Convergence'', an update of the Triptych approach, a comprehensive compromise proposal, the comparison of emission allowances under various approaches and a negotiation strategy for the EU and Germany. (orig.)

  2. Precision Time Protocol support hardware for ATCA control and data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Correia, Miguel, E-mail: miguelfc@ipfn.ist.utl.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Sousa, Jorge; Carvalho, Bernardo B.; Santos, Bruno; Carvalho, Paulo F.; Rodrigues, António P.; Combo, Álvaro M.; Pereira, Rita C. [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentação, Departamento de Física, Universidade de Coimbra, 3004-516 Coimbra (Portugal); Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2015-10-15

    Highlights: • ATCA based control and data acquisition subsystem has been developed at IPFN. • PTP and time stamping were implemented with VHDL and PTP daemon (PTPd) codes. • The RTM (…) provides PTP synchronization with an external GMC. • The main advantage is that timestamps are generated closer to the Physical Layer at the GMII. • IPFN's upgrade consistently exhibited jitter values below 25 ns RMS. - Abstract: An in-house, Advanced Telecom Computing Architecture (ATCA) based control and data acquisition (C&DAQ) subsystem has been developed at Instituto de Plasmas e Fusão Nuclear (IPFN), aiming for compliance with the ITER Fast Plant System Controller (FPSC). Timing and synchronization for the ATCA modules connects to ITER Control, Data Access and Communication (CODAC) through the Timing Communication Network (TCN), which uses IEEE 1588-2008 Precision Time Protocol (PTP) to synchronize devices to a Grand Master Clock (GMC). The TCN infrastructure was tested for an RMS jitter under the limit of 50 ns. Therefore, IPFN's hardware, namely the ATCA-PTSW-AMC4 hub-module, which is in charge of timing and synchronization distribution for all subsystem endpoints, shall also perform within this jitter limit. This paper describes a relevant upgrade, applied to the ATCA-PTSW-AMC4 hardware, to comply with these requirements – in particular, the integration of an add-on module “RMC-TMG-1588” on its Rear Transition Module (RTM). This add-on is based on a commercial FPGA-based module from Trenz Electronic, using the ZHAW “PTP VHDL code for timestamping unit and clock”, which features clock offset and drift correction and hardware-assisted time stamping. The main advantage is that timestamps are generated closer to the Physical Layer, at the Gigabit Ethernet Media Independent Interface (GMII), avoiding the timing uncertainties accumulated through the upper layers. PTP code and user software run in a MicroBlaze™ soft-core CPU with Linux in the

  3. Hardware Acceleration of SQL-Queries Processing in MDM-Systems Based on MISDSolution

    Directory of Open Access Journals (Sweden)

    V. E. Podol'skii

    2015-01-01

    Full Text Available In this article we examine the possibility of hardware support for functions of mobile device management platform (MDM-platform using a Multiple Instructions and Single Data stream computer system, developed within the framework of the project in Bauman Moscow State Technical University. At the universities the MDM-platform is used to provide various mobile services for the faculty, students and administration to facilitate the learning process: a mobile schedule, document sharing, text messages, and other interactive activities. Most of these services are provided by the extensive use of data stored in MDM-platform databases. When accessing the databases SQL- queries are commonly used. These queries comprise operators of SQL-language that are based on mathematical sets theory. Hardware support for operations on sets is implemented in Multiple Instructions and Single Data stream computer system (MISD System. This allows performance improvement of algorithms and operations on sets. Thus, the hardware support for the processing of SQL-queries in MISD system allows us to benefit from the implementation of SQL-queries in the MISD paradigm.The scientific novelty of the work lies in the fact that it is the first time a set of algorithms for basic SQL statements has been presented in a format supported by MISD system. In addition, for the first time operators INNER JOIN, LEFT JOIN and LEFT OUTER JOIN have been implemented for MISD system and tested for it (testing was done for FPGA Xilinx Virtex-II Pro XC2VP30 implementation of MISD system. The practical significance of the work lies in the fact that the results of the study will be used in the project "Development of the Russian analogue of the system software for centralized management of personal devices and platforms in enterprise networks" of the St. Petersburg Polytechnic University (with the financial support of the state represented by the Ministry of Education and Science of the Russian

  4. Hardware emulation of Memristor based Ternary Content Addressable Memory

    KAUST Repository

    Bahloul, Mohamed A.

    2017-12-13

    MTCAM (Memristor Ternary Content Addressable Memory) is a special purpose storage medium in which data could be retrieved based on the stored content. Using Memristors as the main storage element provides the potential of achieving higher density and more efficient solutions than conventional methods. A key missing item in the validation of such approaches is the wide spread availability of hardware emulation platforms that can provide reliable and repeatable performance statistics. In this paper, we present a hardware MTCAM emulation based on 2-Transistors-2Memristors (2T2M) bit-cell. It builds on a bipolar memristor model with storing and fetching capabilities based on the actual current-voltage behaviour. The proposed design offers a flexible verification environment with quick design revisions, high execution speeds and powerful debugging techniques. The proposed design is modeled using VHDL and prototyped on Xilinx Virtex® FPGA.

  5. Advances in neuromorphic hardware exploiting emerging nanoscale devices

    CERN Document Server

    2017-01-01

    This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

  6. Verification of OpenSSL version via hardware performance counters

    Science.gov (United States)

    Bruska, James; Blasingame, Zander; Liu, Chen

    2017-05-01

    Many forms of malware and security breaches exist today. One type of breach downgrades a cryptographic program by employing a man-in-the-middle attack. In this work, we explore the utilization of hardware events in conjunction with machine learning algorithms to detect which version of OpenSSL is being run during the encryption process. This allows for the immediate detection of any unknown downgrade attacks in real time. Our experimental results indicated this detection method is both feasible and practical. When trained with normal TLS and SSL data, our classifier was able to detect which protocol was being used with 99.995% accuracy. After the scope of the hardware event recording was enlarged, the accuracy diminished greatly, but to 53.244%. Upon removal of TLS 1.1 from the data set, the accuracy returned to 99.905%.

  7. Fast and Reliable Mouse Picking Using Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Hanli Zhao

    2009-01-01

    Full Text Available Mouse picking is the most commonly used intuitive operation to interact with 3D scenes in a variety of 3D graphics applications. High performance for such operation is necessary in order to provide users with fast responses. This paper proposes a fast and reliable mouse picking algorithm using graphics hardware for 3D triangular scenes. Our approach uses a multi-layer rendering algorithm to perform the picking operation in linear time complexity. The objectspace based ray-triangle intersection test is implemented in a highly parallelized geometry shader. After applying the hardware-supported occlusion queries, only a small number of objects (or sub-objects are rendered in subsequent layers, which accelerates the picking efficiency. Experimental results demonstrate the high performance of our novel approach. Due to its simplicity, our algorithm can be easily integrated into existing real-time rendering systems.

  8. Follow-the-Leader Control for the PIPS Prototype Hardware

    Science.gov (United States)

    Williams, Robert L. II; Lippitt, Thimas

    1996-01-01

    This report describes the payload inspection and processing system (PIPS), an automated system programmed off-line for inspection of space shuttle payloads after integration and prior to launch. PIPS features a hyper-redundant 18-degree of freedom (DOF) serpentine truss manipulator capable of snake like motions to avoid obstacles. During the summer of 1995, the author worked on the same project, developing a follow-the-leader (FTL) algorithm in graphical simulation which ensures whole arm collision avoidance by forcing ensuing links to follow the same tip trajectory. The summer 1996 work was to control the prototype PIPS hardware in follow-the-leader mode. The project was successful in providing FTL control in hardware. The STS-82 payload mockup was used in the laboratory to demonstrate serpentine motions to avoid obstacles in a realistic environment.

  9. Commercial Aircraft Maintenance Experience Relating to Engine External Hardware

    Science.gov (United States)

    Soditus, Sharon M.

    2006-01-01

    Airlines are extremely sensitive to the amount of dollars spent on maintaining the external engine hardware in the field. Analysis reveals that many problems revolve around a central issue, reliability. Fuel and oil leakage due to seal failure and electrical fault messages due to wire harness failures play a major role in aircraft delays and cancellations (D&C's) and scheduled maintenance. Correcting these items on the line requires a large investment of engineering resources and manpower after the fact. The smartest and most cost effective philosophy is to build the best hardware the first time. The only way to do that is to completely understand and model the operating environment, study the field experience of similar designs and to perform extensive testing.

  10. The LISA Pathfinder interferometry-hardware and system testing

    Energy Technology Data Exchange (ETDEWEB)

    Audley, H; Danzmann, K; MarIn, A Garcia; Heinzel, G; Monsky, A; Nofrarias, M; Steier, F; Bogenstahl, J [Albert-Einstein-Institut, Max-Planck-Institut fuer Gravitationsphysik und Universitaet Hannover, 30167 Hannover (Germany); Gerardi, D; Gerndt, R; Hechenblaikner, G; Johann, U; Luetzow-Wentzky, P; Wand, V [EADS Astrium GmbH, Friedrichshafen (Germany); Antonucci, F [Dipartimento di Fisica, Universita di Trento and INFN, Gruppo Collegato di Trento, 38050 Povo, Trento (Italy); Armano, M [European Space Astronomy Centre, European Space Agency, Villanueva de la Canada, 28692 Madrid (Spain); Auger, G; Binetruy, P [APC UMR7164, Universite Paris Diderot, Paris (France); Benedetti, M [Dipartimento di Ingegneria dei Materiali e Tecnologie Industriali, Universita di Trento and INFN, Gruppo Collegato di Trento, Mesiano, Trento (Italy); Boatella, C, E-mail: antonio.garcia@aei.mpg.de [CNES, DCT/AQ/EC, 18 Avenue Edouard Belin, 31401 Toulouse, Cedex 9 (France)

    2011-05-07

    Preparations for the LISA Pathfinder mission have reached an exciting stage. Tests of the engineering model (EM) of the optical metrology system have recently been completed at the Albert Einstein Institute, Hannover, and flight model tests are now underway. Significantly, they represent the first complete integration and testing of the space-qualified hardware and are the first tests on an optical system level. The results and test procedures of these campaigns will be utilized directly in the ground-based flight hardware tests, and subsequently during in-flight operations. In addition, they allow valuable testing of the data analysis methods using the MATLAB-based LTP data analysis toolbox. This paper presents an overview of the results from the EM test campaign that was successfully completed in December 2009.

  11. Hardware and software fault tolerance - A unified architectural approach

    Science.gov (United States)

    Lala, Jaynarayan H.; Alger, Linda S.

    1988-01-01

    The loss of hardware fault tolerance which often arises when design diversity is used to improve the fault tolerance of computer software is considered analytically, and a unified design approach is proposed to avoid the problem. The fundamental theory of fault-tolerant (FT) architectures is reviewed; the current status of design-diversity software development is surveyed; and the FT-processor/attached-processor (FTP/AP) architecture developed by Lala et al. (1986) is described in detail and illustrated with diagrams. FTP/AP is shown to permit efficient implementation of N-version FT software while still tolerating random hardware failures with very high coverage; the reliability is found to be significantly higher than that of conventional majority-vote N-version software.

  12. Reconfigurable hardware-software codesign methodology for protein identification.

    Science.gov (United States)

    Gudur, Venkateshwarlu Y; Thallada, Sandeep; Deevi, Abhinay R; Gande, Venkata Krishna; Acharyya, Amit; Bhandari, Vasundhra; Sharma, Paresh; Khursheed, Saqib; Naik, Ganesh R

    2016-08-01

    In this paper we propose an on-the-fly reconfigurable hardware-software codesign based reconfigurable solution for real-time protein identification. Reconfigurable string matching is performed in the disciplines of protein identification and biomarkers discovery. With the generation of plethora of sequenced data and number of biomarkers for several diseases, it is becoming necessary to have an accelerated processing and on-the-fly reconfigurable system design methodology to bring flexibility to its usage in the medical science community without the need of changing the entire hardware every time with the advent of new biomarker or protein. The proteome database of human at UniProtKB (Proteome ID up000005640) comprising of 42132 canonical and isoform proteins with variable database-size are used for testing the proposed design and the performance of the proposed system has been found to compare favorably with the state-of-the-art approaches with the additional advantage of real-time reconfigurability.

  13. Cumulative Measurement Errors for Dynamic Testing of Space Flight Hardware

    Science.gov (United States)

    Winnitoy, Susan

    2012-01-01

    Located at the NASA Johnson Space Center in Houston, TX, the Six-Degree-of-Freedom Dynamic Test System (SDTS) is a real-time, six degree-of-freedom, short range motion base simulator originally designed to simulate the relative dynamics of two bodies in space mating together (i.e., docking or berthing). The SDTS has the capability to test full scale docking and berthing systems utilizing a two body dynamic docking simulation for docking operations and a Space Station Remote Manipulator System (SSRMS) simulation for berthing operations. The SDTS can also be used for nonmating applications such as sensors and instruments evaluations requiring proximity or short range motion operations. The motion base is a hydraulic powered Stewart platform, capable of supporting a 3,500 lb payload with a positional accuracy of 0.03 inches. The SDTS is currently being used for the NASA Docking System testing and has been also used by other government agencies. The SDTS is also under consideration for use by commercial companies. Examples of tests include the verification of on-orbit robotic inspection systems, space vehicle assembly procedures and docking/berthing systems. The facility integrates a dynamic simulation of on-orbit spacecraft mating or de-mating using flight-like mechanical interface hardware. A force moment sensor is used for input during the contact phase, thus simulating the contact dynamics. While the verification of flight hardware presents unique challenges, one particular area of interest involves the use of external measurement systems to ensure accurate feedback of dynamic contact. The measurement systems for the test facility have two separate functions. The first is to take static measurements of facility and test hardware to determine both the static and moving frames used in the simulation and control system. The test hardware must be measured after each configuration change to determine both sets of reference frames. The second function is to take dynamic

  14. Reliable Event Detectors for Constrained Resources Wireless Sensor Node Hardware

    Directory of Open Access Journals (Sweden)

    López Trinidad MarcoAntonio

    2009-01-01

    Full Text Available Abstract A novel event detector algorithm, which points out in-door acoustic human activities, for constrained wireless sensor node hardware is proposed in the present paper. In our approach, event detections are computed from the signal energy statistics change rate at two instants separated by an samples interval. The experimentation is run in two phases: (i the detector characterisation and tuning seek detector configurations that enable event detections from three acoustic human activities: closing a door, dropping a plastic bottle, and clapping;(ii event detector validation tests measure the reliability to signal events from general acoustic activities, people talking particularly. The test results, which included emulated node hardware, actual sensor node, and a one-hop WSN, demonstrate the detector implementations signaled successfully events. And for the WSN, we found that event detections decay in a nonlinear fashion as the distance , between the acoustic signal source and the sensor, is increased.

  15. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele......In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA......-based accelerator. Results show that significant speed-up can be obtained by the proposed acceleration framework on system-on-chips where reconfigurable fabric is placed next to the CPUs. The speed-up is due to both the intrinsic acceleration in the application-specific processors, and to the increased parallelism....

  16. New Techniques for Implementation of Hardware Algorithms inside FPGA Circuits

    Directory of Open Access Journals (Sweden)

    IOAN, A. D.

    2010-05-01

    Full Text Available This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the "Altium Designer" software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a "Digilent Spartan-3" FPGA development board, which includes the user interface too.

  17. Computer organization and design the hardware/software interface

    CERN Document Server

    Patterson, David A

    2013-01-01

    The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O. Optimization techniques featured throughout the text. It covers parallelism in depth with...

  18. Summary of multi-core hardware and programming model investigations

    Energy Technology Data Exchange (ETDEWEB)

    Kelly, Suzanne Marie; Pedretti, Kevin Thomas Tauke; Levenhagen, Michael J.

    2008-05-01

    This report summarizes our investigations into multi-core processors and programming models for parallel scientific applications. The motivation for this study was to better understand the landscape of multi-core hardware, future trends, and the implications on system software for capability supercomputers. The results of this study are being used as input into the design of a new open-source light-weight kernel operating system being targeted at future capability supercomputers made up of multi-core processors. A goal of this effort is to create an agile system that is able to adapt to and efficiently support whatever multi-core hardware and programming models gain acceptance by the community.

  19. Object oriented hardware-software test bench for OMTF diagnosis

    Science.gov (United States)

    Drabik, Pawel; Pozniak, Krzysztof T.; Bunkowski, Karol; Zawistowski, Krystian; Byszuk, Adrian; Bluj, Michał; Doroba, Krzysztof; Górski, Maciej; Kalinowski, Artur; Kierzkowski, Krzysztof; Konecki, Marcin; Królikowski, Jan; Oklinski, Wojciech; Olszewski, Michał; Skala, Aleksander; Zabołotny, Wojciech M.

    2015-09-01

    In this paper the object oriented hardware-software model and its sample implementation of diagnostics for the Overlap Muon Track Finder trigger for the CMS experiment in CERN is described. It presents realization of test-bench for control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The test-bench fulfills requirements for system's rapid changes, configurability and efficiency. This ability is very significant and desirable by expanded electronic systems. The solution described is a software model based on a method of address space management called the Component Internal Interface (CII). Establishment of stable link between hardware and software, as a purpose of designed and realized programming environment, is presented. The test-bench implementation and example of OMTF algorithm test is presented.

  20. Corrosion Testing of Stainless Steel Fuel Cell Hardware

    Energy Technology Data Exchange (ETDEWEB)

    Wilson, M.S.; Zawodzinski, C.; Gottesfeld, S.

    1998-11-01

    Metal hardware is gaining increasing interest in polymer electrolyte fuel cell (PEFC) development as a possible alternative to machined graphite hardware because of its potential for low-cost manufacturing combined with its intrinsic high conductivity, minimal permeability and advantageous mechanical properties. A major barrier to more widespread use of metal hardware has been the susceptibility of various metals to corrosion. Few pure metals can withstand the relatively aggressive environment of a fuel cell and thus the choices for hardware are quite limited. Precious metals such as platinum or gold are prohibitively expensive and so tend to be utilized as coatings on inexpensive substrates such as aluminum or stainless steel. The main challenge with coatings has been to achieve pin-hole free surfaces that will remain so after years of use. Titanium has been used to some extent and though it is very corrosion-resistant, it is also relatively expensive and often still requires some manner of surface coating to prevent the formation of a poorly conducting oxide layer. In contrast, metal alloys may hold promise as potentially low-cost, corrosion-resistant materials for bipolar plates. The dozens of commercially available stainless steel and nickel based alloys have been specifically formulated to offer a particular advantage depending upon their application. In the case of austenitic stainless steels, for example, 316 SS contains molybdenum and a higher chromium content than its more common counterpart, 304 SS, that makes it more noble and increases its corrosion resistance. Likewise, 316L SS contains less carbon than 316 SS to make it easier to weld. A number of promising corrosion-resistant, highly noble alloys such as Hastelloy{trademark} or Duplex{trademark} (a stainless steel developed for seawater service) are available commercially, but are expensive and difficult to obtain in various forms (i.e. wire screen, foil, etc.) or in small amounts for R and D