WorldWideScience

Sample records for network hardware options

  1. Hardware implementation of stochastic spiking neural networks.

    Science.gov (United States)

    Rosselló, Josep L; Canals, Vincent; Morro, Antoni; Oliver, Antoni

    2012-08-01

    Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

  2. Artificial Neural Network with Hardware Training and Hardware Refresh

    Science.gov (United States)

    Duong, Tuan A. (Inventor)

    2003-01-01

    A neural network circuit is provided having a plurality of circuits capable of charge storage. Also provided is a plurality of circuits each coupled to at least one of the plurality of charge storage circuits and constructed to generate an output in accordance with a neuron transfer function. Each of a plurality of circuits is coupled to one of the plurality of neuron transfer function circuits and constructed to generate a derivative of the output. A weight update circuit updates the charge storage circuits based upon output from the plurality of transfer function circuits and output from the plurality of derivative circuits. In preferred embodiments, separate training and validation networks share the same set of charge storage circuits and may operate concurrently. The validation network has a separate transfer function circuits each being coupled to the charge storage circuits so as to replicate the training network s coupling of the plurality of charge storage to the plurality of transfer function circuits. The plurality of transfer function circuits may be constructed each having a transconductance amplifier providing differential currents combined to provide an output in accordance with a transfer function. The derivative circuits may have a circuit constructed to generate a biased differential currents combined so as to provide the derivative of the transfer function.

  3. Basket Option Pricing Using GP-GPU Hardware Acceleration

    KAUST Repository

    Douglas, Craig C.; Lee, Hyoseop

    2010-01-01

    We introduce a basket option pricing problem arisen in financial mathematics. We discretized the problem based on the alternating direction implicit (ADI) method and parallel cyclic reduction is applied to solve the set of tridiagonal matrices

  4. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

    2015-01-01

    The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware speci...

  5. Basket Option Pricing Using GP-GPU Hardware Acceleration

    KAUST Repository

    Douglas, Craig C.

    2010-08-01

    We introduce a basket option pricing problem arisen in financial mathematics. We discretized the problem based on the alternating direction implicit (ADI) method and parallel cyclic reduction is applied to solve the set of tridiagonal matrices generated by the ADI method. To reduce the computational time of the problem, a general purpose graphics processing units (GP-GPU) environment is considered. Numerical results confirm the convergence and efficiency of the proposed method. © 2010 IEEE.

  6. Hardware demonstration of high-speed networks for satellite applications.

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, Jonathon W.; Lee, David S.

    2008-09-01

    This report documents the implementation results of a hardware demonstration utilizing the Serial RapidIO{trademark} and SpaceWire protocols that was funded by Sandia National Laboratories (SNL's) Laboratory Directed Research and Development (LDRD) office. This demonstration was one of the activities in the Modeling and Design of High-Speed Networks for Satellite Applications LDRD. This effort has demonstrated the transport of application layer packets across both RapidIO and SpaceWire networks to a common downlink destination using small topologies comprised of commercial-off-the-shelf and custom devices. The RapidFET and NEX-SRIO debug and verification tools were instrumental in the successful implementation of the RapidIO hardware demonstration. The SpaceWire hardware demonstration successfully demonstrated the transfer and routing of application data packets between multiple nodes and also was able reprogram remote nodes using configuration bitfiles transmitted over the network, a key feature proposed in node-based architectures (NBAs). Although a much larger network (at least 18 to 27 nodes) would be required to fully verify the design for use in a real-world application, this demonstration has shown that both RapidIO and SpaceWire are capable of routing application packets across a network to a common downlink node, illustrating their potential use in real-world NBAs.

  7. HARDWARE IMPLEMENTATION OF SECURE AODV FOR WIRELESS SENSOR NETWORKS

    Directory of Open Access Journals (Sweden)

    S. Sharmila

    2010-12-01

    Full Text Available Wireless Sensor Networks are extremely vulnerable to any kind of routing attacks due to several factors such as wireless transmission and resource-constrained nodes. In this respect, securing the packets is of great importance when designing the infrastructure and protocols of sensor networks. This paper describes the hardware architecture of secure routing for wireless sensor networks. The routing path is selected using Ad-hoc on demand distance vector routing protocol (AODV. The data packets are converted into digest using hash functions. The functionality of the proposed method is modeled using Verilog HDL in MODELSIM simulator and the performance is compared with various target devices. The results show that the data packets are secured and defend against the routing attacks with minimum energy consumption.

  8. Hardware and software constructs for a vibration analysis network

    International Nuclear Information System (INIS)

    Cook, S.A.; Crowe, R.D.; Toffer, H.

    1985-01-01

    Vibration level monitoring and analysis has been initiated at N Reactor, the dual purpose reactor operated at Hanford, Washington by UNC Nuclear Industries (UNC) for the Department of Energy (DOE). The machinery to be monitored was located in several buildings scattered over the plant site, necessitating an approach using satellite stations to collect, monitor and temporarily store data. The satellite stations are, in turn, linked to a centralized processing computer for further analysis. The advantages of a networked data analysis system are discussed in this paper along with the hardware and software required to implement such a system

  9. Computer, Network, Software, and Hardware Engineering with Applications

    CERN Document Server

    Schneidewind, Norman F

    2012-01-01

    There are many books on computers, networks, and software engineering but none that integrate the three with applications. Integration is important because, increasingly, software dominates the performance, reliability, maintainability, and availability of complex computer and systems. Books on software engineering typically portray software as if it exists in a vacuum with no relationship to the wider system. This is wrong because a system is more than software. It is comprised of people, organizations, processes, hardware, and software. All of these components must be considered in an integr

  10. Hardware Prototyping of Neural Network based Fetal Electrocardiogram Extraction

    Science.gov (United States)

    Hasan, M. A.; Reaz, M. B. I.

    2012-01-01

    The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

  11. Space station common module network topology and hardware development

    Science.gov (United States)

    Anderson, P.; Braunagel, L.; Chwirka, S.; Fishman, M.; Freeman, K.; Eason, D.; Landis, D.; Lech, L.; Martin, J.; Mccorkle, J.

    1990-01-01

    Conceptual space station common module power management and distribution (SSM/PMAD) network layouts and detailed network evaluations were developed. Individual pieces of hardware to be developed for the SSM/PMAD test bed were identified. A technology assessment was developed to identify pieces of equipment requiring development effort. Equipment lists were developed from the previously selected network schematics. Additionally, functional requirements for the network equipment as well as other requirements which affected the suitability of specific items for use on the Space Station Program were identified. Assembly requirements were derived based on the SSM/PMAD developed requirements and on the selected SSM/PMAD network concepts. Basic requirements and simplified design block diagrams are included. DC remote power controllers were successfully integrated into the DC Marshall Space Flight Center breadboard. Two DC remote power controller (RPC) boards experienced mechanical failure of UES 706 stud-mounted diodes during mechanical installation of the boards into the system. These broken diodes caused input to output shorting of the RPC's. The UES 706 diodes were replaced on these RPC's which eliminated the problem. The DC RPC's as existing in the present breadboard configuration do not provide ground fault protection because the RPC was designed to only switch the hot side current. If ground fault protection were to be implemented, it would be necessary to design the system so the RPC switched both the hot and the return sides of power.

  12. Hardware Implementation of Artificial Neural Network for Data Ciphering

    Directory of Open Access Journals (Sweden)

    Sahar L. Kadoory

    2016-10-01

    Full Text Available This paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays. A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are trained to encrypt the data, after obtaining the suitable weights, biases, activation function and layout. Afterward, they are described using VHDL and implemented using Xilinx Spartan-3E FPGA using two approaches: serial and parallel versions. The simulation results obtained with Xilinx ISE 9.2i software. The numerical precision is chosen carefully when implementing the Neural Network on FPGA. Obtained results from the hardware designs show accurate numeric values to cipher the data. As expected, the synthesis results indicate that the serial version requires less area resources than the parallel version. As, the data throughput in parallel version is higher than the serial version in rang between (1.13-1.5 times. Also, a slight difference can be observed in the maximum frequency.

  13. NEURAL NETWORKS FOR STOCK MARKET OPTION PRICING

    Directory of Open Access Journals (Sweden)

    Sergey A. Sannikov

    2017-03-01

    Full Text Available Introduction: The use of neural networks for non-linear models helps to understand where linear model drawbacks, coused by their specification, reveal themselves. This paper attempts to find this out. The objective of research is to determine the meaning of “option prices calculation using neural networks”. Materials and Methods: We use two kinds of variables: endogenous (variables included in the model of neural network and variables affecting on the model (permanent disturbance. Results: All data are divided into 3 sets: learning, affirming and testing. All selected variables are normalised from 0 to 1. Extreme values of income were shortcut. Discussion and Conclusions: Using the 33-14-1 neural network with direct links we obtained two sets of forecasts. Optimal criteria of strategies in stock markets’ option pricing were developed.

  14. Neural Networks as Semiparametric Option Pricing Tool

    Czech Academy of Sciences Publication Activity Database

    Baruník, Jozef; Baruníková, M.

    2011-01-01

    Roč. 18, č. 28 (2011), s. 66-83 ISSN 1212-074X R&D Projects: GA ČR GD402/09/H045; GA ČR GA402/09/0965 Grant - others:GA ČR(CZ) GA402/09/0732 Institutional research plan: CEZ:AV0Z10750506 Keywords : option valuation * neural network * S&P 500 index options Subject RIV: AH - Economics http://library.utia.cas.cz/separaty/2011/E/barunik-0367688.pdf

  15. Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices

    OpenAIRE

    Lim, Suhwan; Bae, Jong-Ho; Eum, Jai-Ho; Lee, Sungtae; Kim, Chul-Heung; Kwon, Dongseok; Park, Byung-Gook; Lee, Jong-Ho

    2017-01-01

    In this paper, we propose a learning rule based on a back-propagation (BP) algorithm that can be applied to a hardware-based deep neural network (HW-DNN) using electronic devices that exhibit discrete and limited conductance characteristics. This adaptive learning rule, which enables forward, backward propagation, as well as weight updates in hardware, is helpful during the implementation of power-efficient and high-speed deep neural networks. In simulations using a three-layer perceptron net...

  16. Wireless multimedia sensor networks on reconfigurable hardware information reduction techniques

    CERN Document Server

    Ang, Li-minn; Chew, Li Wern; Yeong, Lee Seng; Chia, Wai Chong

    2013-01-01

    Traditional wireless sensor networks (WSNs) capture scalar data such as temperature, vibration, pressure, or humidity. Motivated by the success of WSNs and also with the emergence of new technology in the form of low-cost image sensors, researchers have proposed combining image and audio sensors with WSNs to form wireless multimedia sensor networks (WMSNs).

  17. Software/hardware distributed processing network supporting the Ada environment

    Science.gov (United States)

    Wood, Richard J.; Pryk, Zen

    1993-09-01

    A high-performance, fault-tolerant, distributed network has been developed, tested, and demonstrated. The network is based on the MIPS Computer Systems, Inc. R3000 Risc for processing, VHSIC ASICs for high speed, reliable, inter-node communications and compatible commercial memory and I/O boards. The network is an evolution of the Advanced Onboard Signal Processor (AOSP) architecture. It supports Ada application software with an Ada- implemented operating system. A six-node implementation (capable of expansion up to 256 nodes) of the RISC multiprocessor architecture provides 120 MIPS of scalar throughput, 96 Mbytes of RAM and 24 Mbytes of non-volatile memory. The network provides for all ground processing applications, has merit for space-qualified RISC-based network, and interfaces to advanced Computer Aided Software Engineering (CASE) tools for application software development.

  18. The Model of the Software Running on a Computer Equipment Hardware Included in the Grid network

    Directory of Open Access Journals (Sweden)

    T. A. Mityushkina

    2012-12-01

    Full Text Available A new approach to building a cloud computing environment using Grid networks is proposed in this paper. The authors describe the functional capabilities, algorithm, model of software running on a computer equipment hardware included in the Grid network, that will allow to implement cloud computing environment using Grid technologies.

  19. Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network

    NARCIS (Netherlands)

    Pande, Sandeep; Morgan, Fearghal; Cawley, Seamus; Bruintjes, Tom; Smit, Gerardus Johannes Maria; McGinley, Brian; Carrillo, Snaider; Harkin, Jim; McDaid, Liam

    2013-01-01

    Biologically-inspired packet switched network on chip (NoC) based hardware spiking neural network (SNN) architectures have been proposed as an embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in

  20. Open hardware: a role to play in wireless sensor networks?

    Science.gov (United States)

    Fisher, Roy; Ledwaba, Lehlogonolo; Hancke, Gerhard; Kruger, Carel

    2015-03-20

    The concept of the Internet of Things is rapidly becoming a reality, with many applications being deployed within industrial and consumer sectors. At the 'thing' level-devices and inter-device network communication-the core technical building blocks are generally the same as those found in wireless sensor network implementations. For the Internet of Things to continue growing, we need more plentiful resources for building intelligent devices and sensor networks. Unfortunately, current commercial devices, e.g., sensor nodes and network gateways, tend to be expensive and proprietary, which presents a barrier to entry and arguably slows down further development. There are, however, an increasing number of open embedded platforms available and also a wide selection of off-the-shelf components that can quickly and easily be built into device and network gateway solutions. The question is whether these solutions measure up to built-for-purpose devices. In the paper, we provide a comparison of existing built-for-purpose devices against open source devices. For comparison, we have also designed and rapidly prototyped a sensor node based on off-the-shelf components. We show that these devices compare favorably to built-for-purpose devices in terms of performance, power and cost. Using open platforms and off-the-shelf components would allow more developers to build intelligent devices and sensor networks, which could result in a better overall development ecosystem, lower barriers to entry and rapid growth in the number of IoT applications.

  1. Open Hardware: A Role to Play in Wireless Sensor Networks?

    Directory of Open Access Journals (Sweden)

    Roy Fisher

    2015-03-01

    Full Text Available The concept of the Internet of Things is rapidly becoming a reality, with many applications being deployed within industrial and consumer sectors. At the ‘thing’ level—devices and inter-device network communication—the core technical building blocks are generally the same as those found in wireless sensor network implementations. For the Internet of Things to continue growing, we need more plentiful resources for building intelligent devices and sensor networks. Unfortunately, current commercial devices, e.g., sensor nodes and network gateways, tend to be expensive and proprietary, which presents a barrier to entry and arguably slows down further development. There are, however, an increasing number of open embedded platforms available and also a wide selection of off-the-shelf components that can quickly and easily be built into device and network gateway solutions. The question is whether these solutions measure up to built-for-purpose devices. In the paper, we provide a comparison of existing built-for-purpose devices against open source devices. For comparison, we have also designed and rapidly prototyped a sensor node based on off-the-shelf components. We show that these devices compare favorably to built-for-purpose devices in terms of performance, power and cost. Using open platforms and off-the-shelf components would allow more developers to build intelligent devices and sensor networks, which could result in a better overall development ecosystem, lower barriers to entry and rapid growth in the number of IoT applications.

  2. Open hardware: a role to play in wireless sensor networks?

    CSIR Research Space (South Africa)

    Fisher, R

    2015-03-01

    Full Text Available and cost. Using open platforms and off-the-shelf components would allow more developers to build intelligent devices and sensor networks, which could result in a better overall development ecosystem, lower barriers to entry and rapid growth in the number...

  3. Wireless Plug and Play Control Systems: Hardware, Networks, and Protocols

    DEFF Research Database (Denmark)

    Meybodi, Soroush Afkhami

    2012-01-01

    This dissertation reports the result of efforts to identify and solve the problems that arise when a control system is to be designed for various industrial case studies of the Plug and Play Process Control (P3C) project that require autonomous addition/removal of sensors, actuators and subsystems...... in only one of the P3C case studies where all of the nodes of the wireless networked control system are placed underground and should be able to transmit data among themselves. It is not a trivial problem because the well known radio frequency electromagnetic waves face serious difficulties penetrating...... is recommended for wireless plug and play control systems. Formation and maintenance of clusters of nodes are directly linked to the top level application layer via a novel application-based routing metric. The proposed routing metric facilitates implementation of the networking topology in accordance...

  4. UPGRADE FOR HARDWARE/SOFTWARE SERVER AND NETWORK TOPOLOGY IN INFORMATION SYSTEMS

    Directory of Open Access Journals (Sweden)

    Oleksii O. Kaplun

    2011-02-01

    Full Text Available The network modernization, educational information systems software and hardware updates problem is actual in modern term of information technologies prompt development. There are server applications and network topology of Institute of Information Technology and Learning Tools of National Academy of Pedagogical Sciences of Ukraine analysis and their improvement methods expound in the article. The article materials represent modernization results implemented to increase network efficiency and reliability, decrease response time in Institute’s network information systems. The article gives diagrams of network topology before upgrading and after finish of optimization and upgrading processes.

  5. A technique for choosing an option for SDH network upgrade

    Directory of Open Access Journals (Sweden)

    V. A. Bulanov

    2014-01-01

    Full Text Available Rapidly developing data transmission technologies result in making the network equipment modernization inevitable. There are various options to upgrade the SDH networks, for example, by increasing the capacity of network overloaded sites, the entire network capacity by replacement of the equipment or by creation of a parallel network, by changing the network structure with the organization of multilevel hierarchy of a network, etc. All options vary in a diversity of parameters starting with the solution cost and ending with the labor intensiveness of their realization. Thus, there are no certain standard approaches to the rules to choose an option for the network development. The article offers the technique for choosing the SHD network upgrade based on method of expert evaluations using as a tool the software complex that allows us to have quickly the quantitative characteristics of proposed network option. The technique is as follows:1. Forming a perspective matrix of services inclination to the SDH networks.2. Developing the several possible options for a network modernization.3. Formation of the list of criteria and a definition of indicators to characterize them by two groups, namely costs of the option implementation and arising losses; positive effect from the option introduction.4. Criteria weight coefficients purpose.5. Indicators value assessment within each criterion for each option by each expert. Rationing of the obtained values of indicators in relation to the maximum value of an indicator among all options.6. Calculating the integrated indicators of for each option by criteria groups.7. Creating a set of Pareto by drawing two criteria groups of points, which correspond to all options in the system of coordinates on the plane. Option choice.In implementation of point 2 the indicators derivation owing to software complex plays a key role. This complex should produce a structure of the network equipment, types of multiplexer sections

  6. Virtual reality hardware and graphic display options for brain-machine interfaces.

    Science.gov (United States)

    Marathe, Amar R; Carey, Holle L; Taylor, Dawn M

    2008-01-15

    Virtual reality hardware and graphic displays are reviewed here as a development environment for brain-machine interfaces (BMIs). Two desktop stereoscopic monitors and one 2D monitor were compared in a visual depth discrimination task and in a 3D target-matching task where able-bodied individuals used actual hand movements to match a virtual hand to different target hands. Three graphic representations of the hand were compared: a plain sphere, a sphere attached to the fingertip of a realistic hand and arm, and a stylized pacman-like hand. Several subjects had great difficulty using either stereo monitor for depth perception when perspective size cues were removed. A mismatch in stereo and size cues generated inappropriate depth illusions. This phenomenon has implications for choosing target and virtual hand sizes in BMI experiments. Target-matching accuracy was about as good with the 2D monitor as with either 3D monitor. However, users achieved this accuracy by exploring the boundaries of the hand in the target with carefully controlled movements. This method of determining relative depth may not be possible in BMI experiments if movement control is more limited. Intuitive depth cues, such as including a virtual arm, can significantly improve depth perception accuracy with or without stereo viewing.

  7. Hardware realization of a fast neural network algorithm for real-time tracking in HEP experiments

    International Nuclear Information System (INIS)

    Leimgruber, F.R.; Pavlopoulos, P.; Steinacher, M.; Tauscher, L.; Vlachos, S.; Wendler, H.

    1995-01-01

    A fast pattern recognition system for HEP experiments, based on artificial neural network algorithms (ANN), has been realized with standard electronics. The multiplicity and location of tracks in an event are determined in less than 75 ns. Hardware modules of this first level trigger were extensively tested for performance and reliability with data from the CPLEAR experiment. (orig.)

  8. Interfacing Hardware Accelerators to a Time-Division Multiplexing Network-on-Chip

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Sørensen, Rasmus Bo; Schoeberl, Martin

    2015-01-01

    This paper addresses the integration of stateless hardware accelerators into time-predictable multi-core platforms based on time-division multiplexing networks-on-chip. Stateless hardware accelerators, like floating-point units, are typically attached as co-processors to individual processors in ...... implementation. The design evaluation is carried out using the open source T-CREST multi-core platform implemented on an Altera Cyclone IV FPGA. The size of the proposed design, including a floating-point accelerator, is about two-thirds of a processor....

  9. Open-source hardware and software and web application for gamma dose rate network operation

    International Nuclear Information System (INIS)

    Luff, R.; Zaehringer, M.; Harms, W.; Bleher, M.; Prommer, B.; Stoehlker, U.

    2014-01-01

    The German Federal Office for Radiation Protection operates a network of about 1800 gamma dose rate stations as a part of the national emergency preparedness plan. Each of the six network centres is capable of operating the network alone. Most of the used hardware and software have been developed in-house under open-source license. Short development cycles and close cooperation between developers and users ensure robustness, transparency and fast maintenance procedures, thus avoiding unnecessary complex solutions. This also reduces the overall costs of the network operation. An easy-to-expand web interface has been developed to make the complete system available to other interested network operators in order to increase cooperation between different countries. The interface is also regularly in use for education during scholarships of trainees supported, e.g. by the 'international Atomic Energy Agency' to operate a local area dose rate monitoring test network. (authors)

  10. Event management for large scale event-driven digital hardware spiking neural networks.

    Science.gov (United States)

    Caron, Louis-Charles; D'Haene, Michiel; Mailhot, Frédéric; Schrauwen, Benjamin; Rouat, Jean

    2013-09-01

    The interest in brain-like computation has led to the design of a plethora of innovative neuromorphic systems. Individually, spiking neural networks (SNNs), event-driven simulation and digital hardware neuromorphic systems get a lot of attention. Despite the popularity of event-driven SNNs in software, very few digital hardware architectures are found. This is because existing hardware solutions for event management scale badly with the number of events. This paper introduces the structured heap queue, a pipelined digital hardware data structure, and demonstrates its suitability for event management. The structured heap queue scales gracefully with the number of events, allowing the efficient implementation of large scale digital hardware event-driven SNNs. The scaling is linear for memory, logarithmic for logic resources and constant for processing time. The use of the structured heap queue is demonstrated on a field-programmable gate array (FPGA) with an image segmentation experiment and a SNN of 65,536 neurons and 513,184 synapses. Events can be processed at the rate of 1 every 7 clock cycles and a 406×158 pixel image is segmented in 200 ms. Copyright © 2013 Elsevier Ltd. All rights reserved.

  11. DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

    Science.gov (United States)

    Zhou, Xichuan; Li, Shengli; Tang, Fang; Hu, Shengdong; Lin, Zhi; Zhang, Lei

    2017-07-18

    Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.

  12. A Hardware-Supported Algorithm for Self-Managed and Choreographed Task Execution in Sensor Networks

    Directory of Open Access Journals (Sweden)

    Borja Bordel

    2018-03-01

    Full Text Available Nowadays, sensor networks are composed of a great number of tiny resource-constraint nodes, whose management is increasingly more complex. In fact, although collaborative or choreographic task execution schemes are which fit in the most perfect way with the nature of sensor networks, they are rarely implemented because of the high resource consumption of these algorithms (especially if networks include many resource-constrained devices. On the contrary, hierarchical networks are usually designed, in whose cusp it is included a heavy orchestrator with a remarkable processing power, being able to implement any necessary management solution. However, although this orchestration approach solves most practical management problems of sensor networks, a great amount of the operation time is wasted while nodes request the orchestrator to address a conflict and they obtain the required instructions to operate. Therefore, in this paper it is proposed a new mechanism for self-managed and choreographed task execution in sensor networks. The proposed solution considers only a lightweight gateway instead of traditional heavy orchestrators and a hardware-supported algorithm, which consume a negligible amount of resources in sensor nodes. The gateway avoids the congestion of the entire sensor network and the hardware-supported algorithm enables a choreographed task execution scheme, so no particular node is overloaded. The performance of the proposed solution is evaluated through numerical and electronic ModelSim-based simulations.

  13. Locating hardware faults in a data communications network of a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-01-12

    Hardware faults location in a data communications network of a parallel computer. Such a parallel computer includes a plurality of compute nodes and a data communications network that couples the compute nodes for data communications and organizes the compute node as a tree. Locating hardware faults includes identifying a next compute node as a parent node and a root of a parent test tree, identifying for each child compute node of the parent node a child test tree having the child compute node as root, running a same test suite on the parent test tree and each child test tree, and identifying the parent compute node as having a defective link connected from the parent compute node to a child compute node if the test suite fails on the parent test tree and succeeds on all the child test trees.

  14. Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system

    Science.gov (United States)

    Kim, Hyungjin; Hwang, Sungmin; Park, Jungjin; Park, Byung-Gook

    2017-10-01

    Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.

  15. Wireless Energy Harvesting Two-Way Relay Networks with Hardware Impairments.

    Science.gov (United States)

    Peng, Chunling; Li, Fangwei; Liu, Huaping

    2017-11-13

    This paper considers a wireless energy harvesting two-way relay (TWR) network where the relay has energy-harvesting abilities and the effects of practical hardware impairments are taken into consideration. In particular, power splitting (PS) receiver is adopted at relay to harvests the power it needs for relaying the information between the source nodes from the signals transmitted by the source nodes, and hardware impairments is assumed suffered by each node. We analyze the effect of hardware impairments [-20]on both decode-and-forward (DF) relaying and amplify-and-forward (AF) relaying networks. By utilizing the obtained new expressions of signal-to-noise-plus-distortion ratios, the exact analytical expressions of the achievable sum rate and ergodic capacities for both DF and AF relaying protocols are derived. Additionally, the optimal power splitting (OPS) ratio that maximizes the instantaneous achievable sum rate is formulated and solved for both protocols. The performances of DF and AF protocols are evaluated via numerical results, which also show the effects of various network parameters on the system performance and on the OPS ratio design.

  16. IT Career JumpStart An Introduction to PC Hardware, Software, and Networking

    CERN Document Server

    Alpern, Naomi J; Muller, Randy

    2011-01-01

    A practical approach for anyone looking to enter the IT workforce Before candidates can begin to prepare for any kind of certification, they need a basic understanding of the various hardware and software components used in a computer network. Aimed at aspiring IT professionals, this invaluable book strips down a network to its bare basics, and discusses this complex topic in a clear and concise manner so that IT beginners can confidently gain an understanding of fundamental IT concepts. In addition, a base knowledge has been established so that more advanced topics and technologies can be lea

  17. Joint preprocesser-based detector for cooperative networks with limited hardware processing capability

    KAUST Repository

    Abuzaid, Abdulrahman I.

    2015-02-01

    In this letter, a joint detector for cooperative communication networks is proposed when the destination has limited hardware processing capability. The transmitter sends its symbols with the help of L relays. As the destination has limited hardware, only U out of L signals are processed and the energy of the remaining relays is lost. To solve this problem, a joint preprocessing based detector is proposed. This joint preprocessor based detector operate on the principles of minimizing the symbol error rate (SER). For a realistic assessment, pilot symbol aided channel estimation is incorporated for this proposed detector. From our simulations, it can be observed that our proposed detector achieves the same SER performance as that of the maximum likelihood (ML) detector with all participating relays. Additionally, our detector outperforms selection combining (SC), channel shortening (CS) scheme and reduced-rank techniques when using the same U. Our proposed scheme has low computational complexity.

  18. Large-scale simulations of plastic neural networks on neuromorphic hardware

    Directory of Open Access Journals (Sweden)

    James Courtney Knight

    2016-04-01

    Full Text Available SpiNNaker is a digital, neuromorphic architecture designed for simulating large-scale spiking neural networks at speeds close to biological real-time. Rather than using bespoke analog or digital hardware, the basic computational unit of a SpiNNaker system is a general-purpose ARM processor, allowing it to be programmed to simulate a wide variety of neuron and synapse models. This flexibility is particularly valuable in the study of biological plasticity phenomena. A recently proposed learning rule based on the Bayesian Confidence Propagation Neural Network (BCPNN paradigm offers a generic framework for modeling the interaction of different plasticity mechanisms using spiking neurons. However, it can be computationally expensive to simulate large networks with BCPNN learning since it requires multiple state variables for each synapse, each of which needs to be updated every simulation time-step. We discuss the trade-offs in efficiency and accuracy involved in developing an event-based BCPNN implementation for SpiNNaker based on an analytical solution to the BCPNN equations, and detail the steps taken to fit this within the limited computational and memory resources of the SpiNNaker architecture. We demonstrate this learning rule by learning temporal sequences of neural activity within a recurrent attractor network which we simulate at scales of up to 20000 neurons and 51200000 plastic synapses: the largest plastic neural network ever to be simulated on neuromorphic hardware. We also run a comparable simulation on a Cray XC-30 supercomputer system and find that, if it is to match the run-time of our SpiNNaker simulation, the super computer system uses approximately more power. This suggests that cheaper, more power efficient neuromorphic systems are becoming useful discovery tools in the study of plasticity in large-scale brain models.

  19. Secure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grid

    Directory of Open Access Journals (Sweden)

    Marcelo Urbina

    2018-02-01

    Full Text Available Nowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA, to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP. Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850. The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA. The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM, defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.

  20. The NIDS Cluster: Scalable, Stateful Network Intrusion Detection on Commodity Hardware

    Energy Technology Data Exchange (ETDEWEB)

    Tierney, Brian L; Vallentin, Matthias; Sommer, Robin; Lee, Jason; Leres, Craig; Paxson, Vern; Tierney, Brian

    2007-09-19

    In this work we present a NIDS cluster as a scalable solution for realizing high-performance, stateful network intrusion detection on commodity hardware. The design addresses three challenges: (i) distributing traffic evenly across an extensible set of analysis nodes in a fashion that minimizes the communication required for coordination, (ii) adapting the NIDS's operation to support coordinating its low-level analysis rather than just aggregating alerts; and (iii) validating that the cluster produces sound results. Prototypes of our NIDS cluster now operate at the Lawrence Berkeley National Laboratory and the University of California at Berkeley. In both environments the clusters greatly enhance the power of the network security monitoring.

  1. CRYSNET manual. Informal report. [Hardware and software of crystallographic computing network

    Energy Technology Data Exchange (ETDEWEB)

    None,

    1976-07-01

    This manual describes the hardware and software which together make up the crystallographic computing network (CRYSNET). The manual is intended as a users' guide and also provides general information for persons without any experience with the system. CRYSNET is a network of intelligent remote graphics terminals that are used to communicate with the CDC Cyber 70/76 computing system at the Brookhaven National Laboratory (BNL) Central Scientific Computing Facility. Terminals are in active use by four research groups in the field of crystallography. A protein data bank has been established at BNL to store in machine-readable form atomic coordinates and other crystallographic data for macromolecules. The bank currently includes data for more than 20 proteins. This structural information can be accessed at BNL directly by the CRYSNET graphics terminals. More than two years of experience has been accumulated with CRYSNET. During this period, it has been demonstrated that the terminals, which provide access to a large, fast third-generation computer, plus stand-alone interactive graphics capability, are useful for computations in crystallography, and in a variety of other applications as well. The terminal hardware, the actual operations of the terminals, and the operations of the BNL Central Facility are described in some detail, and documentation of the terminal and central-site software is given. (RWR)

  2. Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

    Science.gov (United States)

    Litinski, Daniel; Kesselring, Markus S.; Eisert, Jens; von Oppen, Felix

    2017-07-01

    We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall-superconductor hybrids.

  3. Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

    Directory of Open Access Journals (Sweden)

    Daniel Litinski

    2017-09-01

    Full Text Available We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall–superconductor hybrids.

  4. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Directory of Open Access Journals (Sweden)

    Huan-Yuan Chen

    2017-09-01

    Full Text Available This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

  5. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Science.gov (United States)

    Chen, Huan-Yuan; Chen, Chih-Chang

    2017-01-01

    This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

  6. Autonomous target tracking of UAVs based on low-power neural network hardware

    Science.gov (United States)

    Yang, Wei; Jin, Zhanpeng; Thiem, Clare; Wysocki, Bryant; Shen, Dan; Chen, Genshe

    2014-05-01

    Detecting and identifying targets in unmanned aerial vehicle (UAV) images and videos have been challenging problems due to various types of image distortion. Moreover, the significantly high processing overhead of existing image/video processing techniques and the limited computing resources available on UAVs force most of the processing tasks to be performed by the ground control station (GCS) in an off-line manner. In order to achieve fast and autonomous target identification on UAVs, it is thus imperative to investigate novel processing paradigms that can fulfill the real-time processing requirements, while fitting the size, weight, and power (SWaP) constrained environment. In this paper, we present a new autonomous target identification approach on UAVs, leveraging the emerging neuromorphic hardware which is capable of massively parallel pattern recognition processing and demands only a limited level of power consumption. A proof-of-concept prototype was developed based on a micro-UAV platform (Parrot AR Drone) and the CogniMemTMneural network chip, for processing the video data acquired from a UAV camera on the y. The aim of this study was to demonstrate the feasibility and potential of incorporating emerging neuromorphic hardware into next-generation UAVs and their superior performance and power advantages towards the real-time, autonomous target tracking.

  7. Noise reduction and image enhancement using a hardware implementation of artificial neural networks

    Science.gov (United States)

    David, Robert; Williams, Erin; de Tremiolles, Ghislain; Tannhof, Pascal

    1999-03-01

    In this paper, we present a neural based solution developed for noise reduction and image enhancement using the ZISC, an IBM hardware processor which implements the Restricted Coulomb Energy algorithm and the K-Nearest Neighbor algorithm. Artificial neural networks present the advantages of processing time reduction in comparison with classical models, adaptability, and the weighted property of pattern learning. The goal of the developed application is image enhancement in order to restore old movies (noise reduction, focus correction, etc.), to improve digital television images, or to treat images which require adaptive processing (medical images, spatial images, special effects, etc.). Image results show a quantitative improvement over the noisy image as well as the efficiency of this system. Further enhancements are being examined to improve the output of the system.

  8. Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms.

    Science.gov (United States)

    Stromatias, Evangelos; Neil, Daniel; Pfeiffer, Michael; Galluppi, Francesco; Furber, Steve B; Liu, Shih-Chii

    2015-01-01

    Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs) are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks require vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost two bits, and show that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

  9. Superior Generalization Capability of Hardware-Learing Algorithm Developed for Self-Learning Neuron-MOS Neural Networks

    Science.gov (United States)

    Kondo, Shuhei; Shibata, Tadashi; Ohmi, Tadahiro

    1995-02-01

    We have investigated the learning performance of the hardware backpropagation (HBP) algorithm, a hardware-oriented learning algorithm developed for the self-learning architecture of neural networks constructed using neuron MOS (metal-oxide-semiconductor) transistors. The solution to finding a mirror symmetry axis in a 4×4 binary pixel array was tested by computer simulation based on the HBP algorithm. Despite the inherent restrictions imposed on the hardware-learning algorithm, HBP exhibits equivalent learning performance to that of the original backpropagation (BP) algorithm when all the pertinent parameters are optimized. Very importantly, we have found that HBP has a superior generalization capability over BP; namely, HBP exhibits higher performance in solving problems that the network has not yet learnt.

  10. Medium access control and hardware prototype designs for low-energy wireless sensor networks

    Energy Technology Data Exchange (ETDEWEB)

    Kohvakka, M.

    2009-07-01

    A Wireless Sensor Network (WSN) is an emerging technology consisting of small, cheap, and ultra-low energy sensor nodes, which cooperatively monitor physical quantities, actuate, and perform data processing tasks. A deployment may comprise thousands of randomly distributed autonomous nodes, which must self-configure and create a multi-hop network topology.This thesis focuses on low-energy WSNs targeting to long network lifetime. The main research problem is the combination of adaptive and scalable multi-hop networking with constrained energy budget, processing power, and communication bandwidth. The research problem is approached by energy-efficient protocols and low-power sensor node platforms. The main contribution of this thesis is an energy-efficient Medium Access Control (MAC) design for TUTWSN (Tampere University of Technology Wireless Sensor Network). The design comprises channel access and networking mechanisms, which specify data exchange, link synchronization, network self-configuration, and neighbor discovery operations. The second outcome are several low-power sensor node platforms, which have been designed and implemented to evaluate the performance of the MAC design and hardware components in real deployments. The third outcome are the performance models and analysis of several MAC designs including TUTWSN, IEEE 802.15.4, and the most essential research proposals.The results and conclusion of this Thesis indicate that it is possible to implement multi-hop WSNs in harsh and dynamic operation conditions with years of lifetime using current low-cost components and batteries. Energy analysis results indicate that the lowest energy consumption is achieved by using simple and high data-rate transceivers. It is also critical to minimize sleep mode power consumption of all components and to use accurate wake-up timers. However, the selection of components constitutes only a minor part of the solution, and an energy-efficient MAC layer design being able to

  11. Robustness of spiking Deep Belief Networks to noise and reduced bit precision of neuro-inspired hardware platforms

    Directory of Open Access Journals (Sweden)

    Evangelos eStromatias

    2015-07-01

    Full Text Available Increasingly large deep learning architectures, such as Deep Belief Networks (DBNs are the focus of current machine learning research and achieve state-of-the-art results in different domains. However, both training and execution of large-scale Deep Networks requires vast computing resources, leading to high power requirements and communication overheads. The on-going work on design and construction of spike-based hardware platforms offers an alternative for running deep neural networks with significantly lower power consumption, but has to overcome hardware limitations in terms of noise and limited weight precision, as well as noise inherent in the sensor signal. This article investigates how such hardware constraints impact the performance of spiking neural network implementations of DBNs. In particular, the influence of limited bit precision during execution and training, and the impact of silicon mismatch in the synaptic weight parameters of custom hybrid VLSI implementations is studied. Furthermore, the network performance of spiking DBNs is characterized with regard to noise in the spiking input signal. Our results demonstrate that spiking DBNs can tolerate very low levels of hardware bit precision down to almost 2 bits, and shows that their performance can be improved by at least 30% through an adapted training mechanism that takes the bit precision of the target platform into account. Spiking DBNs thus present an important use-case for large-scale hybrid analog-digital or digital neuromorphic platforms such as SpiNNaker, which can execute large but precision-constrained deep networks in real time.

  12. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    International Nuclear Information System (INIS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Cicero, F. Lo; Lonardo, A; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Simula, F.; Tosoratto, L.; Vicini, P.; Rossetti, D.

    2015-01-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology.The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network.The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols.Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design. (paper)

  13. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    Science.gov (United States)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  14. Hardware-Efficient On-line Learning through Pipelined Truncated-Error Backpropagation in Binary-State Networks

    Directory of Open Access Journals (Sweden)

    Hesham Mostafa

    2017-09-01

    Full Text Available Artificial neural networks (ANNs trained using backpropagation are powerful learning architectures that have achieved state-of-the-art performance in various benchmarks. Significant effort has been devoted to developing custom silicon devices to accelerate inference in ANNs. Accelerating the training phase, however, has attracted relatively little attention. In this paper, we describe a hardware-efficient on-line learning technique for feedforward multi-layer ANNs that is based on pipelined backpropagation. Learning is performed in parallel with inference in the forward pass, removing the need for an explicit backward pass and requiring no extra weight lookup. By using binary state variables in the feedforward network and ternary errors in truncated-error backpropagation, the need for any multiplications in the forward and backward passes is removed, and memory requirements for the pipelining are drastically reduced. Further reduction in addition operations owing to the sparsity in the forward neural and backpropagating error signal paths contributes to highly efficient hardware implementation. For proof-of-concept validation, we demonstrate on-line learning of MNIST handwritten digit classification on a Spartan 6 FPGA interfacing with an external 1Gb DDR2 DRAM, that shows small degradation in test error performance compared to an equivalently sized binary ANN trained off-line using standard back-propagation and exact errors. Our results highlight an attractive synergy between pipelined backpropagation and binary-state networks in substantially reducing computation and memory requirements, making pipelined on-line learning practical in deep networks.

  15. Hardware-Efficient On-line Learning through Pipelined Truncated-Error Backpropagation in Binary-State Networks.

    Science.gov (United States)

    Mostafa, Hesham; Pedroni, Bruno; Sheik, Sadique; Cauwenberghs, Gert

    2017-01-01

    Artificial neural networks (ANNs) trained using backpropagation are powerful learning architectures that have achieved state-of-the-art performance in various benchmarks. Significant effort has been devoted to developing custom silicon devices to accelerate inference in ANNs. Accelerating the training phase, however, has attracted relatively little attention. In this paper, we describe a hardware-efficient on-line learning technique for feedforward multi-layer ANNs that is based on pipelined backpropagation. Learning is performed in parallel with inference in the forward pass, removing the need for an explicit backward pass and requiring no extra weight lookup. By using binary state variables in the feedforward network and ternary errors in truncated-error backpropagation, the need for any multiplications in the forward and backward passes is removed, and memory requirements for the pipelining are drastically reduced. Further reduction in addition operations owing to the sparsity in the forward neural and backpropagating error signal paths contributes to highly efficient hardware implementation. For proof-of-concept validation, we demonstrate on-line learning of MNIST handwritten digit classification on a Spartan 6 FPGA interfacing with an external 1Gb DDR2 DRAM, that shows small degradation in test error performance compared to an equivalently sized binary ANN trained off-line using standard back-propagation and exact errors. Our results highlight an attractive synergy between pipelined backpropagation and binary-state networks in substantially reducing computation and memory requirements, making pipelined on-line learning practical in deep networks.

  16. PUFKEY: a high-security and high-throughput hardware true random number generator for sensor networks.

    Science.gov (United States)

    Li, Dongfang; Lu, Zhaojun; Zou, Xuecheng; Liu, Zhenglin

    2015-10-16

    Random number generators (RNG) play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF) elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST) randomness tests and is resilient to a wide range of security attacks.

  17. PUFKEY: A High-Security and High-Throughput Hardware True Random Number Generator for Sensor Networks

    Directory of Open Access Journals (Sweden)

    Dongfang Li

    2015-10-01

    Full Text Available Random number generators (RNG play an important role in many sensor network systems and applications, such as those requiring secure and robust communications. In this paper, we develop a high-security and high-throughput hardware true random number generator, called PUFKEY, which consists of two kinds of physical unclonable function (PUF elements. Combined with a conditioning algorithm, true random seeds are extracted from the noise on the start-up pattern of SRAM memories. These true random seeds contain full entropy. Then, the true random seeds are used as the input for a non-deterministic hardware RNG to generate a stream of true random bits with a throughput as high as 803 Mbps. The experimental results show that the bitstream generated by the proposed PUFKEY can pass all standard national institute of standards and technology (NIST randomness tests and is resilient to a wide range of security attacks.

  18. Attacks on the Network Synchronization Systems Counteraction Method Implemented in the Software and Hardware Device «MARSH! 3.0»

    Directory of Open Access Journals (Sweden)

    Dmitry Anatolevich Melnikov

    2013-12-01

    Full Text Available This paper proposes attacks on the network synchronization systems counteraction technique, method, algorithm and realizable aspects. The network synchronization systems are included in information technology systems or networks. This method is implemented in software and hardware device (means «MARSH! 3.0» providing trusted session.

  19. Applicability of line outage distribution factors to evaluate distribution network expansion options

    NARCIS (Netherlands)

    Grond, M.O.W.; Pouw, J.I.P.; Morren, J.; Slootweg, J.G.

    2014-01-01

    Distribution network operators require more advanced planning tools to deal with the challenges of future network planning. An appropriate planning and optimization tool can identify which option for network extension should be selected from available alternatives. However, the evaluation part in

  20. Space station common module power system network topology and hardware development

    Science.gov (United States)

    Landis, D. M.

    1985-01-01

    Candidate power system newtork topologies for the space station common module are defined and developed and the necessary hardware for test and evaluation is provided. Martin Marietta's approach to performing the proposed program is presented. Performance of the tasks described will assure systematic development and evaluation of program results, and will provide the necessary management tools, visibility, and control techniques for performance assessment. The plan is submitted in accordance with the data requirements given and includes a comprehensive task logic flow diagram, time phased manpower requirements, a program milestone schedule, and detailed descriptions of each program task.

  1. Setting Up a Public Use Local Area Network.

    Science.gov (United States)

    Flower, Eric; Thulstrup, Lisa

    1988-01-01

    Describes a public use microcomputer cluster at the University of Maine, Orono. Various network topologies, hardware and software options, installation problems, system management, and performance are discussed. (MES)

  2. Sign Language Recognition System using Neural Network for Digital Hardware Implementation

    International Nuclear Information System (INIS)

    Vargas, Lorena P; Barba, Leiner; Torres, C O; Mattos, L

    2011-01-01

    This work presents an image pattern recognition system using neural network for the identification of sign language to deaf people. The system has several stored image that show the specific symbol in this kind of language, which is employed to teach a multilayer neural network using a back propagation algorithm. Initially, the images are processed to adapt them and to improve the performance of discriminating of the network, including in this process of filtering, reduction and elimination noise algorithms as well as edge detection. The system is evaluated using the signs without including movement in their representation.

  3. Standard cell-based implementation of a digital optoelectronic neural-network hardware.

    Science.gov (United States)

    Maier, K D; Beckstein, C; Blickhan, R; Erhard, W

    2001-03-10

    A standard cell-based implementation of a digital optoelectronic neural-network architecture is presented. The overall structure of the multilayer perceptron network that was used, the optoelectronic interconnection system between the layers, and all components required in each layer are defined. The design process from VHDL-based modeling from synthesis and partly automatic placing and routing to the final editing of one layer of the circuit of the multilayer perceptrons are described. A suitable approach for the standard cell-based design of optoelectronic systems is presented, and shortcomings of the design tool that was used are pointed out. The layout for the microelectronic circuit of one layer in a multilayer perceptron neural network with a performance potential 1 magnitude higher than neural networks that are purely electronic based has been successfully designed.

  4. Social network sites: Indispensable or optional social tools?

    DEFF Research Database (Denmark)

    Shklovski, Irina

    2012-01-01

    Much research has enumerated potential benefits of online social network sites. Given the pervasiveness of these sites and the numbers of people that use them daily, both re-search and media tend to make the assumption that social network sites have become indispensible to their users. Based...... on the analysis of qualitative data from users of social network sites in Russia and Kazakhstan, this paper consid-ers under what conditions social network sites can become indispensable to their users and when these technologies remain on the periphery of life despite fulfilling useful func-tions. For some...... respondents, these sites had become indis-pensable tools as they were integrated into everyday rou-tines of communicating with emotionally important and proximal contacts and were often used for coordination of offline activities. For others social network sites remained spaces where they occasionally visited...

  5. Hardware Module for the Security Enhancement of Optical Telecom Network Equipment

    International Nuclear Information System (INIS)

    Nadeem; Ali, M.

    2015-01-01

    The telecommunication equipment physical security threats have increased not only in Pakistan but also anywhere in the world and hence, reducing the revenue. This new challenging and alarming situation is created for the telecom network provider. The main focus of this paper is to provide a low cost economical design for reducing the theft of the costly telecommunication equipment like optical network units (ONU). This system is based on instant messaging on the mobile in the event of theft through GSM modem. The proposed security module is dynamic, flexible and can also be integrated in the existing networks and separately having its own independent low power consumption source. The module will continuously work successfully under different scenarios such as completely isolated from other devices by power break down or by fibre cut. (author)

  6. Simple techniques for improving deep neural network outcomes on commodity hardware

    Science.gov (United States)

    Colina, Nicholas Christopher A.; Perez, Carlos E.; Paraan, Francis N. C.

    2017-08-01

    We benchmark improvements in the performance of deep neural networks (DNN) on the MNIST data test upon imple-menting two simple modifications to the algorithm that have little overhead computational cost. First is GPU parallelization on a commodity graphics card, and second is initializing the DNN with random orthogonal weight matrices prior to optimization. Eigenspectra analysis of the weight matrices reveal that the initially orthogonal matrices remain nearly orthogonal after training. The probability distributions from which these orthogonal matrices are drawn are also shown to significantly affect the performance of these deep neural networks.

  7. Hardware implementation of an adaptive resonance theory (ART) neural network using compensated operational amplifiers

    Science.gov (United States)

    Ho, Ching S.; Liou, Juin J.; Georgiopoulos, Michael; Christodoulou, Christos G.

    1994-03-01

    This paper presents an analog circuit design and implementation for an adaptive resonance theory neural network architecture called the augmented ART1 neural network (AART1-NN). Practical monolithic operational amplifiers (Op-Amps) LM741 and LM318 are selected to implement the circuit, and a simple compensation scheme is developed to adjust the Op-Amp electrical characteristics to meet the design requirement. A 7-node prototype circuit has been designed and verified using the Pspice circuit simulator run on a Sun workstation. Results simulated from the AART1-NN circuit using the LM741, LM318, and ideal Op-Amps are presented and compared.

  8. Hardware design of the median filter based on window structure and batcher′s oddeven sort network

    Directory of Open Access Journals (Sweden)

    SUN Kaimin

    2013-06-01

    Full Text Available Area and speed are two important factors to be considered in designing Median Filter with digital circuits.Area consideration requires the use of logical resources as little as possible,while speed consideration requires the system capable of working on higher clock frequencies,with as few clock cycles as possible to complete a frame filtering or real time filtering.This paper gives a new design of Median Filter,the hardware structure of which is a 3×3 window structure with two buffers.The filter function module is based on Batcher′s Odd-Even Sort network theory.Structural design is implemented in FPGA,verified by ModelSim software and realizes video image filtering.The experimental analysis shows that this new structure of Median Filter effectively decreases logical resources (merely using 741 Logic Elements,and accelerates the pixel processing speed up to 27MHz.This filter achieves realtime processing of video images of 30 frames/s.This design not only has a certain practicality,but also provides a reference for the hardware structure design ideas in digital image processing.

  9. Performance Evaluation of User Selection Protocols in Random Networks with Energy Harvesting and Hardware Impairments

    Directory of Open Access Journals (Sweden)

    Tan Nhat Nguyen

    2016-01-01

    Full Text Available In this paper, we evaluate performances of various user selection protocols under impact of hardware impairments. In the considered protocols, a Base Station (BS selects one of available Users (US to serve, while the remaining USs harvest the energy from the Radio Frequency (RF transmitted by the BS. We assume that all of the US randomly appear around the BS. In the Random Selection Protocol (RAN, the BS randomly selects a US to transmit the data. In the second proposed protocol, named Minimum Distance Protocol (MIND, the US that is nearest to the BS will be chosen. In the Optimal Selection Protocol (OPT, the US providing the highest channel gain between itself and the BS will be served. For performance evaluation, we derive exact and asymptotic closed-form expressions of average Outage Probability (OP over Rayleigh fading channels. We also consider average harvested energy per a US. Finally, Monte-Carlo simulations are then performed to verify the theoretical results.

  10. Condition monitoring of planetary gearbox by hardware implementation of artificial neural networks

    DEFF Research Database (Denmark)

    Dabrowski, Dariusz

    2016-01-01

    for a selected neural network, which is based on a Learning Vector Quantization (LVQ) algorithm. Presented classifier can be used as an independent diagnostic system or can be combined with traditional data acquisition systems using FPGAs. (C) 2016 Elsevier Ltd. All rights reserved....

  11. Privacy-preserving telecardiology sensor networks: toward a low-cost portable wireless hardware/software codesign.

    Science.gov (United States)

    Hu, Fei; Jiang, Meng; Wagner, Mark; Dong, De-Cun

    2007-11-01

    Recently, a remote-sensing platform based on wireless interconnection of tiny ECG sensors called Telecardiology Sensor Networks (TSN) provided a promising approach to perform low-cost real-time cardiac patient monitoring at any time in community areas (such as elder nursing homes or hospitals). The contribution of this research is the design of a practical TSN hardware/software platform for a typical U.S. healthcare community scenario (such as large nursing homes with many elder patients) to perform real-time healthcare data collections. On the other hand, due to the radio broadcasting nature of MANET, a TSN has the risk of losing the privacy of patients' data. Medical privacy has been highly emphasized by U.S. Department of Health and Human Services. This research also designs a medical security scheme with low communication overhead to achieve confidential electrocardiogram data transmission in wireless medium.

  12. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  13. Architectural Options for a Future Deep Space Optical Communications Network

    Science.gov (United States)

    Edwards, B. L.; Benjamin, T.; Scozzafava, J.; Khatri, F.; Sharma, J.; Parvin, B.; Liebrecht, P. E.; Fitzgerald, R. J.

    2004-01-01

    This paper provides an overview of different options at Earth to provide Deep Space optical communication services. It is based mainly on work done for the Mars Laser Communications Demonstration (MLCD) Project, a joint project between NASA's Goddard Space Flight Center (GSFC), the Jet Propulsion Laboratory, California Institute of Technology (JPL), and the Massachusetts Institute of Technology Lincoln Laboratory (MIT/LL). It also reports preliminary conclusions from the Tracking and Data Relay Satellite System Continuation Study at GSFC. A lasercom flight terminal will be flown on the Mars Telecommunications Orbiter (MTO) to be launched by NASA in 2009, and will be the first high rate deep space demonstration of this revolutionary technology.

  14. Applying Real Options Thinking to Information Security in Networked Organizations

    NARCIS (Netherlands)

    Daneva, Maia

    2006-01-01

    An information security strategy of an organization participating in a networked business sets out the plans for designing a variety of actions that ensure confidentiality, availability, and integrity of company’s key information assets. The actions are concerned with authentication and

  15. An exploration of options and functions of climate technology centres and networks. Discussion paper

    International Nuclear Information System (INIS)

    De Coninck, H.C.; Wuertenberger, L.; Cochran, J.; Cox, S.; Benioff, R.

    2010-11-01

    This paper responds to a request to UNEP from the UNFCCC Expert Group on Technology Transfer to examine operational modalities for climate technology centres and networks. The paper first discusses possible dimensions for the climate technology centre and network, and it reviews a number of existing networks and centres. It then distinguishes five options for the organizational structure and describes potential operational characteristics for each of these options. All options examined seek to build from existing climate and non-climate-related public and private technology centres, networks, and initiatives. Consistent with the UNFCCC negotiating text and draft technology decision, the paper evaluates potential implementation options and outcomes for each of the functions tentatively assigned to the climate technology centre and network, as well as selected functions of the technology executive committee. Approaches are offered for integrating delivery of these functions through coordinated programmes, and hypothetical examples are given to explain how the technology mechanism might add value in practice. The options presented in this paper are not an exhaustive treatment of potential structures or implementation approaches, and other approaches can be considered.

  16. Real-time prediction of acute cardiovascular events using hardware-implemented Bayesian networks.

    Science.gov (United States)

    Tylman, Wojciech; Waszyrowski, Tomasz; Napieralski, Andrzej; Kamiński, Marek; Trafidło, Tamara; Kulesza, Zbigniew; Kotas, Rafał; Marciniak, Paweł; Tomala, Radosław; Wenerski, Maciej

    2016-02-01

    This paper presents a decision support system that aims to estimate a patient׳s general condition and detect situations which pose an immediate danger to the patient׳s health or life. The use of this system might be especially important in places such as accident and emergency departments or admission wards, where a small medical team has to take care of many patients in various general conditions. Particular stress is laid on cardiovascular and pulmonary conditions, including those leading to sudden cardiac arrest. The proposed system is a stand-alone microprocessor-based device that works in conjunction with a standard vital signs monitor, which provides input signals such as temperature, blood pressure, pulseoxymetry, ECG, and ICG. The signals are preprocessed and analysed by a set of artificial intelligence algorithms, the core of which is based on Bayesian networks. The paper focuses on the construction and evaluation of the Bayesian network, both its structure and numerical specification. Copyright © 2015 Elsevier Ltd. All rights reserved.

  17. HARDWARE IMPLEMENTATION OF PIPELINE BASED ROUTER DESIGN FOR ON-CHIP NETWORK

    Directory of Open Access Journals (Sweden)

    U. Saravanakumar

    2012-12-01

    Full Text Available As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.

  18. The VMTG Hardware Description

    CERN Document Server

    Puccio, B

    1998-01-01

    The document describes the hardware features of the CERN Master Timing Generator. This board is the common platform for the transmission of General Timing Machine required by the CERN accelerators. In addition, the paper shows the various jumper options to customise the card which is compliant to the VMEbus standard.

  19. Optimization of a hardware implementation for pulse coupled neural networks for image applications

    Science.gov (United States)

    Gimeno Sarciada, Jesús; Lamela Rivera, Horacio; Warde, Cardinal

    2010-04-01

    Pulse Coupled Neural Networks are a very useful tool for image processing and visual applications, since it has the advantages of being invariant to image changes as rotation, scale, or certain distortion. Among other characteristics, the PCNN changes a given image input into a temporal representation which can be easily later analyzed for pattern recognition. The structure of a PCNN though, makes it necessary to determine all of its parameters very carefully in order to function optimally, so that the responses to the kind of inputs it will be subjected are clearly discriminated allowing for an easy and fast post-processing yielding useful results. This tweaking of the system is a taxing process. In this paper we analyze and compare two methods for modeling PCNNs. A purely mathematical model is programmed and a similar circuital model is also designed. Both are then used to determine the optimal values of the several parameters of a PCNN: gain, threshold, time constants for feed-in and threshold and linking leading to an optimal design for image recognition. The results are compared for usefulness, accuracy and speed, as well as the performance and time requirements for fast and easy design, thus providing a tool for future ease of management of a PCNN for different tasks.

  20. ZEUS hardware control system

    Science.gov (United States)

    Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

    1989-12-01

    The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

  1. ZEUS hardware control system

    International Nuclear Information System (INIS)

    Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

    1989-01-01

    The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users. (orig.)

  2. Augmented lagrange hopfield network for economic dispatch with multiple fuel options

    International Nuclear Information System (INIS)

    Dieu, Vo Ngoc; Ongsakul, Weerakorn; Polprasert, Jirawadee

    2011-01-01

    This paper proposes an augmented Lagrange Hopfield network (ALHN) for solving economic dispatch (ED) problem with multiple fuel options. The proposed ALHN method is a continuous Hopfield neural network with its energy function based on augmented Lagrangian function. The advantages of ALHN over the conventional Hopfield neural network are easier use, more general applications, faster convergence, better optimal solution, and larger scale of problem implementation. The method solves the problem by directly searching the most suitable fuel among the available fuels of each unit and finding the optimal solution for the problem based on minimization of the energy function of the continuous Hopfield neural network. The proposed method is tested on systems up to 100 units and the obtained results are compared to those from other methods in the literature. The results have shown that the proposed method is efficient for solving the ED problem with multiple fuel options and favorable for implementation in large scale problems.

  3. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  4. Comparison of High Performance Network Options: EDR InfiniBand vs.100Gb RDMA Capable Ethernet

    Energy Technology Data Exchange (ETDEWEB)

    Kachelmeier, Luke Anthony [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Univ. of New Mexico, Albuquerque, NM (United States); Van Wig, Faith Virginia [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Missouri Univ. of Science and Technology, Rolla, MO (United States); Erickson, Kari Natania [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); New Mexico Inst. of Mining and Technology, Socorro, NM (United States)

    2016-08-08

    These are the slides for a presentation at the HPC Mini Showcase. This is a comparison of two different high performance network options: EDR InfiniBand and 100Gb RDMA capable ethernet. The conclusion of this comparison is the following: there is good potential, as shown with the direct results; 100Gb technology is too new and not standardized, thus deployment effort is complex for both options; different companies are not necessarily compatible; if you want 100Gb/s, you must get it all from one place.

  5. A low cost network of spectrometer radiation detectors based on the ArduSiPM a compact transportable Software/Hardware Data Acquisition system with Arduino DUE

    International Nuclear Information System (INIS)

    Bocci, Valerio; Chiodi, Giacomo; Iacoangeli, Francesco; Nuccetelli, Massimo; Recchia, Luigi

    2015-01-01

    The necessity to use Photo Multipliers (PM) as light detector limited in the past the use of crystals in radiation handled device preferring the Geiger approach. The Silicon Photomultipliers (SiPMs) are very small and cheap, solid photon detectors with good dynamic range and single photon detection capability, they are usable to supersede cumbersome and difficult to use Photo Multipliers (PM). A SiPM can be coupled with a scintillator crystal to build efficient, small and solid radiation detector. A cost effective and easily replicable Hardware software module for SiPM detector readout is made using the ArduSiPM solution. The ArduSiPM is an easily battery operable handled device using an Arduino DUE (an open Software/Hardware board) as processor board and a piggy-back custom designed board (ArduSiPM Shield), the Shield contains all the blocks features to monitor, set and acquire the SiPM using internet network. (authors)

  6. A low cost network of spectrometer radiation detectors based on the ArduSiPM a compact transportable Software/Hardware Data Acquisition system with Arduino DUE

    Energy Technology Data Exchange (ETDEWEB)

    Bocci, Valerio; Chiodi, Giacomo; Iacoangeli, Francesco; Nuccetelli, Massimo; Recchia, Luigi [INFN Sezione di Roma, P.le Aldo moro 2, Rome, I-00185 (Italy)

    2015-07-01

    The necessity to use Photo Multipliers (PM) as light detector limited in the past the use of crystals in radiation handled device preferring the Geiger approach. The Silicon Photomultipliers (SiPMs) are very small and cheap, solid photon detectors with good dynamic range and single photon detection capability, they are usable to supersede cumbersome and difficult to use Photo Multipliers (PM). A SiPM can be coupled with a scintillator crystal to build efficient, small and solid radiation detector. A cost effective and easily replicable Hardware software module for SiPM detector readout is made using the ArduSiPM solution. The ArduSiPM is an easily battery operable handled device using an Arduino DUE (an open Software/Hardware board) as processor board and a piggy-back custom designed board (ArduSiPM Shield), the Shield contains all the blocks features to monitor, set and acquire the SiPM using internet network. (authors)

  7. Optimization of European call options considering physical delivery network and reservoir operation rules

    Science.gov (United States)

    Cheng, Wei-Chen; Hsu, Nien-Sheng; Cheng, Wen-Ming; Yeh, William W.-G.

    2011-10-01

    This paper develops alternative strategies for European call options for water purchase under hydrological uncertainties that can be used by water resources managers for decision making. Each alternative strategy maximizes its own objective over a selected sequence of future hydrology that is characterized by exceedance probability. Water trade provides flexibility and enhances water distribution system reliability. However, water trade between two parties in a regional water distribution system involves many issues, such as delivery network, reservoir operation rules, storage space, demand, water availability, uncertainty, and any existing contracts. An option is a security giving the right to buy or sell an asset; in our case, the asset is water. We extend a flow path-based water distribution model to include reservoir operation rules. The model simultaneously considers both the physical distribution network as well as the relationships between water sellers and buyers. We first test the model extension. Then we apply the proposed optimization model for European call options to the Tainan water distribution system in southern Taiwan. The formulation lends itself to a mixed integer linear programming model. We use the weighing method to formulate a composite function for a multiobjective problem. The proposed methodology provides water resources managers with an overall picture of water trade strategies and the consequence of each strategy. The results from the case study indicate that the strategy associated with a streamflow exceedence probability of 50% or smaller should be adopted as the reference strategy for the Tainan water distribution system.

  8. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  9. Network approach for decision making under risk—How do we choose among probabilistic options with the same expected value?

    Science.gov (United States)

    Chen, Yi-Shin

    2018-01-01

    Conventional decision theory suggests that under risk, people choose option(s) by maximizing the expected utility. However, theories deal ambiguously with different options that have the same expected utility. A network approach is proposed by introducing ‘goal’ and ‘time’ factors to reduce the ambiguity in strategies for calculating the time-dependent probability of reaching a goal. As such, a mathematical foundation that explains the irrational behavior of choosing an option with a lower expected utility is revealed, which could imply that humans possess rationality in foresight. PMID:29702665

  10. Network approach for decision making under risk-How do we choose among probabilistic options with the same expected value?

    Science.gov (United States)

    Pan, Wei; Chen, Yi-Shin

    2018-01-01

    Conventional decision theory suggests that under risk, people choose option(s) by maximizing the expected utility. However, theories deal ambiguously with different options that have the same expected utility. A network approach is proposed by introducing 'goal' and 'time' factors to reduce the ambiguity in strategies for calculating the time-dependent probability of reaching a goal. As such, a mathematical foundation that explains the irrational behavior of choosing an option with a lower expected utility is revealed, which could imply that humans possess rationality in foresight.

  11. Network approach for decision making under risk-How do we choose among probabilistic options with the same expected value?

    Directory of Open Access Journals (Sweden)

    Wei Pan

    Full Text Available Conventional decision theory suggests that under risk, people choose option(s by maximizing the expected utility. However, theories deal ambiguously with different options that have the same expected utility. A network approach is proposed by introducing 'goal' and 'time' factors to reduce the ambiguity in strategies for calculating the time-dependent probability of reaching a goal. As such, a mathematical foundation that explains the irrational behavior of choosing an option with a lower expected utility is revealed, which could imply that humans possess rationality in foresight.

  12. Cross-Layer Protocol as a Better Option in Wireless Mesh Network with Respect to Layered-Protocol

    OpenAIRE

    Ahmed Abdulwahab Al-Ahdal; Dr. V. P. Pawar; G. N. Shinde

    2014-01-01

    The Optimal way to improve Wireless Mesh Networks (WMNs) performance is to use a better network protocol, but whether layered-protocol design or cross-layer design is a better option to optimize protocol performance in WMNs is still an on-going research topic. In this paper, we focus on cross-layer protocol as a better option with respect to layered-protocol. The layered protocol architecture (OSI) model divides networking tasks into layers and defines a pocket of services for each layer to b...

  13. Hardware for soft computing and soft computing for hardware

    CERN Document Server

    Nedjah, Nadia

    2014-01-01

    Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

  14. Reconfigurable antenna options for 2.45/5 GHz wireless body area networks in healthcare applications.

    Science.gov (United States)

    Abbas, Syed Muzahir; Ranga, Yogesh; Esselle, Karu P

    2015-01-01

    This paper presents electronically reconfigurable antenna options in healthcare applications. They are suitable for wireless body area network devices operating in the industrial, scientific, and medical (ISM) band at 2.45 GHz and IEEE 802.11 Wireless Local Area Network (WLAN) band at 5 GHz (5.15-5.35 GHz, 5.25-5.35 GHz). Two types of antennas are investigated: Antenna-I has a full ground plane and Antenna-II has a partial ground plane. The proposed antennas provide ISM operation in one mode while in another mode they support 5 GHz WLAN band. Their performance is assessed for body centric wireless communication using a simplified human body model. Antenna sensitivity to the gap between the antenna and the human body is investigated for both modes of each antenna. The proposed antennas exhibit a wide radiation pattern along the body surface to provide wide coverage and their small width (14 mm) makes them suitable for on-body communication in healthcare applications.

  15. Analysis of Probability of Non-zero Secrecy Capacity for Multi-hop Networks in Presence of Hardware Impairments over Nakagami-m Fading Channels

    Directory of Open Access Journals (Sweden)

    T.-T. Phu

    2016-12-01

    Full Text Available In this paper, we evaluate probability of non-zero secrecy capacity of multi-hop relay networks over Nakagami-m fading channels in presence of hardware impairments. In the considered protocol, a source attempts to transmit its data to a destination by using multi-hop randomize-and-forward (RF strategy. The data transmitted by the source and relays are overheard by an eavesdropper. For performance evaluation, we derive exact expressions of probability of non-zero secrecy capacity (PoNSC, which are expressed by sums of infinite series of exponential functions and exponential integral functions. We then perform Monte Carlo simulations to verify the theoretical analysis.

  16. Open Source Hardware for DIY Environmental Sensing

    Science.gov (United States)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  17. An Evaluation of Feral Cat Management Options Using a Decision Analysis Network

    Directory of Open Access Journals (Sweden)

    Kerrie Anne T. Loyd

    2010-12-01

    Full Text Available The feral domestic cat (Felis catus is a predatory invasive species with documented negative effects on native wildlife. The issue of appropriate and acceptable feral cat management is a matter of contentious debate in cities and states across the United States due to concerns for wildlife conservation, cat welfare, and public health. Common management strategies include: Trap-Neuter-Release, Trap-Neuter-Release with removal of kittens for adoption and Trap-Euthanize. Very little empirical evidence exists relevant to the efficacy of alternative options and a model-based approach is needed to predict population response and extend calculations to impact on wildlife. We have created a structured decision support model representing multiple stakeholder groups to facilitate the coordinated management of feral cats. We used a probabilistic graphical model (a Bayesian Belief Network to evaluate and rank alternative management decisions according to efficacy, societal preferences, and cost. Our model predicts that Trap-Neuter-Release strategies would be optimal management decisions for small local populations of less than fifty cats while Trap-Euthanize would be the optimal management decision for populations greater than 50 cats. Removal is predicted to reduce feral cat populations quickly and prevent cats from taking a large number of wildlife prey.

  18. Handbook of networking & connectivity

    CERN Document Server

    McClain, Gary R

    1994-01-01

    Handbook of Networking & Connectivity focuses on connectivity standards in use, including hardware and software options. The book serves as a guide for solving specific problems that arise in designing and maintaining organizational networks.The selection first tackles open systems interconnection, guide to digital communications, and implementing TCP/IP in an SNA environment. Discussions focus on elimination of the SNA backbone, routing SNA over internets, connectionless versus connection-oriented networks, internet concepts, application program interfaces, basic principles of layering, proto

  19. Near Earth Architectural Options for a Future Deep Space Optical Communications Network

    Science.gov (United States)

    Edwards, B. L.; Liebrecht, P. E.; Fitzgerald, R. J.

    2004-01-01

    In the near future the National Aeronautics and Space Administration anticipates a significant increase in demand for long-haul communications services from deep space to Earth. Distances will range from 0.1 to 40 AU, with data rate requirements in the 1's to 1000's of Mbits/second. The near term demand is driven by NASA's Space Science Enterprise which wishes to deploy more capable instruments onboard spacecraft and increase the number of deep space missions. The long term demand is driven by missions with extreme communications challenges such as very high data rates from the outer planets, supporting sub-surface exploration, or supporting NASA's Human Exploration and Development of Space Enterprise beyond Earth orbit. Laser communications is a revolutionary communications technology that will dramatically increase NASA's ability to transmit information across the solar system. Lasercom sends information using beams of light and optical elements, such as telescopes and optical amplifiers, rather than RF signals, amplifiers, and antennas. This paper provides an overview of different network options at Earth to meet NASA's deep space lasercom requirements. It is based mainly on work done for the Mars Laser Communications Demonstration Project, a joint project between NASA's Goddard Space Flight Center (GSFC), the Jet Propulsion Laboratory, California Institute of Technology (JPL), and the Massachusetts Institute of Technology Lincoln Laboratory (MIT/LL). It reports preliminary conclusions from the Mars Lasercom Study conducted at MIT/LL and on additional work done for the Tracking and Data Relay Satellite System Continuation Study at GSFC. A lasercom flight terminal will be flown on the Mars Telesat Orbiter (MTO) to be launched by NASA in 2009, and will be the first high rate deep space demonstration of this revolutionary technology.

  20. Performance Evaluation of Relay Selection Schemes in Beacon-Assisted Dual-Hop Cognitive Radio Wireless Sensor Networks under Impact of Hardware Noises.

    Science.gov (United States)

    Hieu, Tran Dinh; Duy, Tran Trung; Dung, Le The; Choi, Seong Gon

    2018-06-05

    To solve the problem of energy constraints and spectrum scarcity for cognitive radio wireless sensor networks (CR-WSNs), an underlay decode-and-forward relaying scheme is considered, where the energy constrained secondary source and relay nodes are capable of harvesting energy from a multi-antenna power beacon (PB) and using that harvested energy to forward the source information to the destination. Based on the time switching receiver architecture, three relaying protocols, namely, hybrid partial relay selection (H-PRS), conventional opportunistic relay selection (C-ORS), and best opportunistic relay selection (B-ORS) protocols are considered to enhance the end-to-end performance under the joint impact of maximal interference constraint and transceiver hardware impairments. For performance evaluation and comparison, we derive the exact and asymptotic closed-form expressions of outage probability (OP) and throughput (TP) to provide significant insights into the impact of our proposed protocols on the system performance over Rayleigh fading channel. Finally, simulation results validate the theoretical results.

  1. Introduction to Hardware Security

    Directory of Open Access Journals (Sweden)

    Yier Jin

    2015-10-01

    Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

  2. Identifying options for regulating the coordination of network investments with investments in distributed electricity generation

    International Nuclear Information System (INIS)

    Nisten, E.

    2010-02-01

    The increase in the distributed generation of electricity, with wind turbines and solar panels, necessitates investments in the distribution network. The current tariff regulation in the Dutch electricity industry, with its ex post evaluation of the efficiency of investments and the frontier shift in the x-factor, delays these investments. In the unbundled electricity industry, the investments in the network need to be coordinated with those in the distributed generation of electricity to enable the DSOs to build enough network capacity. The current Dutch regulations do not provide for a sufficient information exchange between the generators and the system operators to coordinate the investments. This paper analyses these two effects of the Dutch regulation, and suggests improvements to the regulation of the network connection and transportation tariffs to allow for sufficient network capacity and coordination between the investments in the network and in the generation of electricity. These improvements include locally differentiated tariffs that increase with an increasing concentration of distributed generators.

  3. 'Unstructured Data' Practices in Polar Institutions and Networks: a Case Study with the Arctic Options Project

    Directory of Open Access Journals (Sweden)

    Paul Arthur Berkman

    2014-10-01

    Full Text Available Arctic Options: Holistic Integration for Arctic Coastal-Marine Sustainability is a new three-year research project to assess future infrastructure associated with the Arctic Ocean regarding: (1 natural and living environment; (2 built environment; (3 natural resource development; and (4 governance. For the assessments, Arctic Options will generate objective relational schema from numeric data as well as textual data. This paper will focus on the ‘long tail of smaller, heterogeneous, and often unstructured datasets’ that ‘usually receive minimal data management consideration’,as observed in the 2013 Communiqué from the International Forum on Polar Data Activities in Global Data Systems.

  4. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  5. Open Hardware Business Models

    OpenAIRE

    Edy Ferreira

    2008-01-01

    In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  6. LHCb: Hardware Data Injector

    CERN Multimedia

    Delord, V; Neufeld, N

    2009-01-01

    The LHCb High Level Trigger and Data Acquisition system selects about 2 kHz of events out of the 1 MHz of events, which have been selected previously by the first-level hardware trigger. The selected events are consolidated into files and then sent to permanent storage for subsequent analysis on the Grid. The goal of the upgrade of the LHCb readout is to lift the limitation to 1 MHz. This means speeding up the DAQ to 40 MHz. Such a DAQ system will certainly employ 10 Gigabit or technologies and might also need new networking protocols: a customized TCP or proprietary solutions. A test module is being presented, which integrates in the existing LHCb infrastructure. It is a 10-Gigabit traffic generator, flexible enough to generate LHCb's raw data packets using dummy data or simulated data. These data are seen as real data coming from sub-detectors by the DAQ. The implementation is based on an FPGA using 10 Gigabit Ethernet interface. This module is integrated in the experiment control system. The architecture, ...

  7. Development of a tracer transport option for the NAPSAC fracture network computer code

    International Nuclear Information System (INIS)

    Herbert, A.W.

    1990-06-01

    The Napsac computer code predicts groundwater flow through fractured rock using a direct fracture network approach. This paper describes the development of a tracer transport algorithm for the NAPSAC code. A very efficient particle-following approach is used enabling tracer transport to be predicted through large fracture networks. The new algorithm is tested against three test examples. These demonstrations confirm the accuracy of the code for simple networks, where there is an analytical solution to the transport problem, and illustrates the use of the computer code on a more realistic problem. (author)

  8. Delay/Disruption Tolerance Networking (DTN) Implementation and Utilization Options on the International Space Station

    Science.gov (United States)

    Holbrook, Mark; Pitts, Robert Lee; Gifford, Kevin K.; Jenkins, Andrew; Kuzminsky, Sebastian

    2010-01-01

    The International Space Station (ISS) is in an operational configuration and nearing final assembly. With its maturity and diverse payloads onboard, the opportunity exists to extend the orbital lab into a facility to exercise and demonstrate Delay/Disruption Tolerant Networking (DTN). DTN is an end-to-end network service providing communications through environments characterized by intermittent connectivity, variable delays, high bit error rates, asymmetric links and simplex links. The DTN protocols, also known as bundle protocols, provide a store-and-forward capability to accommodate end-to-end network services. Key capabilities of the bundling protocols include: the Ability to cope with intermittent connectivity, the Ability to take advantage of scheduled and opportunistic connectivity (in addition to always up connectivity), Custody Transfer, and end-to-end security. Colorado University at Boulder and the Huntsville Operational Support Center (HOSC) have been developing a DTN capability utilizing the Commercial Generic Bioprocessing Apparatus (CGBA) payload resources onboard the ISS, at the Boulder Payload Operations Center (POC) and at the HOSC. The DTN capability is in parallel with and is designed to augment current capabilities. The architecture consists of DTN endpoint nodes on the ISS and at the Boulder POC, and a DTN node at the HOSC. The DTN network is composed of two implementations; the Interplanetary Overlay Network (ION) and the open source DTN2 implementation. This paper presents the architecture, implementation, and lessons learned. By being able to handle the types of environments described above, the DTN technology will be instrumental in extending networks into deep space to support future missions to other planets and other solar system points of interest. Thus, this paper also discusses how this technology will be applicable to these types of deep space exploration missions.

  9. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  10. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  11. Hardware description languages

    Science.gov (United States)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  12. Hardware protection through obfuscation

    CERN Document Server

    Bhunia, Swarup; Tehranipoor, Mark

    2017-01-01

    This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

  13. Ditch network maintenance in peat-dominated boreal forests: Review and analysis of water quality management options.

    Science.gov (United States)

    Nieminen, Mika; Piirainen, Sirpa; Sikström, Ulf; Löfgren, Stefan; Marttila, Hannu; Sarkkola, Sakari; Laurén, Ari; Finér, Leena

    2018-03-27

    The objective of this study was to evaluate the potential of different water management options to mitigate sediment and nutrient exports from ditch network maintenance (DNM) areas in boreal peatland forests. Available literature was reviewed, past data reanalyzed, effects of drainage intensity modeled, and major research gaps identified. The results indicate that excess downstream loads may be difficult to prevent. Water protection structures constructed to capture eroded matter are either inefficient (sedimentation ponds) or difficult to apply (wetland buffers). It may be more efficient to decrease erosion, either by limiting peak water velocity (dam structures) or by adjusting ditch depth and spacing to enable satisfactory drainage without exposing the mineral soil below peat. Future research should be directed towards the effects of ditch breaks and adjusted ditch depth and spacing in managing water quality in DNM areas.

  14. CHOICE OF OPTION FOR IMPLEMENTATION OF THE MULTILEVEL SECURE ACCESS TO THE EXTERNAL NETWORK

    Directory of Open Access Journals (Sweden)

    V. S. Kolomoitcev

    2016-01-01

    Full Text Available We study the optimal way for design of access scheme called "Direct Connection. This scheme provides a secure access to external network resources, and consists of several groups of routers and two kinds of firewalls. The scheme is considered in view of the fact that the system has got common areas of removing threats in the channel for different means of protection. Parameters of average residence time of request in the system and its reliability were obtained for each variant of access scheme. Based on the results, comparison of the ways of design for access scheme was carried out between themselves and with the standard access scheme (with onefirewall. It was found out that design of access scheme with a single group of routers for the whole system has better performance and reliability than the other variants of "Direct Connection" access scheme.

  15. Accounting for water management issues within hydrological simulation: Alternative modelling options and a network optimization approach

    Science.gov (United States)

    Efstratiadis, Andreas; Nalbantis, Ioannis; Rozos, Evangelos; Koutsoyiannis, Demetris

    2010-05-01

    In mixed natural and artificialized river basins, many complexities arise due to anthropogenic interventions in the hydrological cycle, including abstractions from surface water bodies, groundwater pumping or recharge and water returns through drainage systems. Typical engineering approaches adopt a multi-stage modelling procedure, with the aim to handle the complexity of process interactions and the lack of measured abstractions. In such context, the entire hydrosystem is separated into natural and artificial sub-systems or components; the natural ones are modelled individually, and their predictions (i.e. hydrological fluxes) are transferred to the artificial components as inputs to a water management scheme. To account for the interactions between the various components, an iterative procedure is essential, whereby the outputs of the artificial sub-systems (i.e. abstractions) become inputs to the natural ones. However, this strategy suffers from multiple shortcomings, since it presupposes that pure natural sub-systems can be located and that sufficient information is available for each sub-system modelled, including suitable, i.e. "unmodified", data for calibrating the hydrological component. In addition, implementing such strategy is ineffective when the entire scheme runs in stochastic simulation mode. To cope with the above drawbacks, we developed a generalized modelling framework, following a network optimization approach. This originates from the graph theory, which has been successfully implemented within some advanced computer packages for water resource systems analysis. The user formulates a unified system which is comprised of the hydrographical network and the typical components of a water management network (aqueducts, pumps, junctions, demand nodes etc.). Input data for the later include hydraulic properties, constraints, targets, priorities and operation costs. The real-world system is described through a conceptual graph, whose dummy properties

  16. Quantitative Evaluation of Biologic Therapy Options for Psoriasis: A Systematic Review and Network Meta-Analysis.

    Science.gov (United States)

    Jabbar-Lopez, Zarif K; Yiu, Zenas Z N; Ward, Victoria; Exton, Lesley S; Mohd Mustapa, M Firouz; Samarasekera, Eleanor; Burden, A David; Murphy, Ruth; Owen, Caroline M; Parslew, Richard; Venning, Vanessa; Warren, Richard B; Smith, Catherine H

    2017-08-01

    Multiple biologic treatments are licensed for psoriasis. The lack of head-to-head randomized controlled trials makes choosing between them difficult for patients, clinicians, and guideline developers. To establish their relative efficacy and tolerability, we searched MEDLINE, PubMed, Embase, and Cochrane for randomized controlled trials of licensed biologic treatments for skin psoriasis. We performed a network meta-analysis to identify direct and indirect evidence comparing biologics with one another, methotrexate, or placebo. We combined this with hierarchical cluster analysis to consider multiple outcomes related to efficacy and tolerability in combination for each treatment. Study quality, heterogeneity, and inconsistency were evaluated. Direct comparisons from 41 randomized controlled trials (20,561 participants) were included. All included biologics were efficacious compared with placebo or methotrexate at 3-4 months. Overall, cluster analysis showed adalimumab, secukinumab, and ustekinumab were comparable in terms of high efficacy and tolerability. Ixekizumab and infliximab were differentiated by very high efficacy but poorer tolerability. The lack of longer term controlled data limited our analysis to short-term outcomes. Trial performance may not equate to real-world performance, and so results need to be considered alongside real-world, long-term safety and effectiveness data. These data suggest that it is possible to discriminate between biologics to inform clinical practice and decision making (PROSPERO 2015:CRD42015017538). Copyright © 2017 The Authors. Published by Elsevier Inc. All rights reserved.

  17. Hardware Objects for Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan

    2008-01-01

    Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

  18. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  19. CERN Neutrino Platform Hardware

    CERN Document Server

    Nelson, Kevin

    2017-01-01

    My summer research was broadly in CERN's neutrino platform hardware efforts. This project had two main components: detector assembly and data analysis work for ICARUS. Specifically, I worked on assembly for the ProtoDUNE project and monitored the safety of ICARUS as it was transported to Fermilab by analyzing the accelerometer data from its move.

  20. RRFC hardware operation manual

    International Nuclear Information System (INIS)

    Abhold, M.E.; Hsue, S.T.; Menlove, H.O.; Walton, G.

    1996-05-01

    The Research Reactor Fuel Counter (RRFC) system was developed to assay the 235 U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the 235 U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics

  1. Hardware Accelerated Simulated Radiography

    International Nuclear Information System (INIS)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-01-01

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists

  2. Sterilization of space hardware.

    Science.gov (United States)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  3. Hardware characteristic and application

    International Nuclear Information System (INIS)

    Gu, Dong Hyeon

    1990-03-01

    The contents of this book are system board on memory, performance, system timer system click and specification, coprocessor such as programing interface and hardware interface, power supply on input and output, protection for DC output, Power Good signal, explanation on 84 keyboard and 101/102 keyboard,BIOS system, 80286 instruction set and 80287 coprocessor, characters, keystrokes and colors, communication and compatibility of IBM personal computer on application direction, multitasking and code for distinction of system.

  4. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  5. Hardware/software virtualization for the reconfigurable multicore platform.

    NARCIS (Netherlands)

    Ferger, M.; Al Kadi, M.; Hübner, M.; Koedam, M.L.P.J.; Sinha, S.S.; Goossens, K.G.W.; Marchesan Almeida, Gabriel; Rodrigo Azambuja, J.; Becker, Juergen

    2012-01-01

    This paper presents the Flex Tiles approach for the virtualization of hardware and software for a reconfigurable multicore architecture. The approach enables the virtualization of a dynamic tile-based hardware architecture consisting of processing tiles connected via a network-on-chip and a

  6. Emerging Radio and Manet Technology Study: Research Support for a Survey of State-of-the-art Commercial and Military Hardware/Software for Mobile Ad Hoc Networks

    Science.gov (United States)

    2014-10-01

    Exynos 4412 Prime, 1.17GHz ARMS Cortex -A9 quad core processor . It features Ethernet, 2x USB ports, audio, power connectors, micro HDMI, and micro SD...uses a camera mounted on the soldier’s helmet and a Harris video processor to gather and share video over the radio network. 3.1.1.4 Thales Group...on ARM processors . There are a limited few based on MIPS processors but they are uncommon and not well supported. This is in contrast to routers

  7. Utilizing IXP1200 hardware and software for packet filtering

    OpenAIRE

    Lindholm, Jeffery L.

    2004-01-01

    As network processors have advanced in speed and efficiency they have become more and more complex in both hardware and software configurations. Intel's IXP1200 is one of these new network processors that has been given to different universities worldwide to conduct research on. The goal of this thesis is to take the first step in starting that research by providing a stable system that can provide a reliable platform for further research. This thesis introduces the fundamental hardware of In...

  8. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  9. Targeting multiple heterogeneous hardware platforms with OpenCL

    Science.gov (United States)

    Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

    2014-06-01

    The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

  10. Energy options

    International Nuclear Information System (INIS)

    Hampton, Michael

    1999-01-01

    This chapter focuses on energy options as a means of managing exposure to energy prices. An intuitive approach to energy options is presented, and traditional definitions of call and put options are given. The relationship between options and swaps, option value and option exercises, commodity options, and option pricing are described. An end-user's guide to energy option strategy is outlined, and straight options, collars, participating swaps and collars, bull and bear spreads, and swaption are examined. Panels explaining the defining of basis risk, and discussing option pricing and the Greeks, delta hedging, managing oil options using the Black-Scholes model, caps, floors and collars, and guidelines on hedging versus speculation with options are included in the paper

  11. Foundations of hardware IP protection

    CERN Document Server

    Torres, Lionel

    2017-01-01

    This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

  12. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  13. Management of cladding hulls and fuel hardware

    International Nuclear Information System (INIS)

    1985-01-01

    The reprocessing of spent fuel from power reactors based on chop-leach technology produces a solid waste product of cladding hulls and other metallic residues. This report describes the current situation in the management of fuel cladding hulls and hardware. Information is presented on the material composition of such waste together with the heating effects due to neutron-induced activation products and fuel contamination. As no country has established a final disposal route and the corresponding repository, this report also discusses possible disposal routes and various disposal options under consideration at present

  14. HARDWARE TROJAN IDENTIFICATION AND DETECTION

    OpenAIRE

    Samer Moein; Fayez Gebali; T. Aaron Gulliver; Abdulrahman Alkandari

    2017-01-01

    ABSTRACT The majority of techniques developed to detect hardware trojans are based on specific attributes. Further, the ad hoc approaches employed to design methods for trojan detection are largely ineffective. Hardware trojans have a number of attributes which can be used to systematically develop detection techniques. Based on this concept, a detailed examination of current trojan detection techniques and the characteristics of existing hardware trojans is presented. This is used to dev...

  15. Hardware assisted hypervisor introspection.

    Science.gov (United States)

    Shi, Jiangyong; Yang, Yuexiang; Tang, Chuan

    2016-01-01

    In this paper, we introduce hypervisor introspection, an out-of-box way to monitor the execution of hypervisors. Similar to virtual machine introspection which has been proposed to protect virtual machines in an out-of-box way over the past decade, hypervisor introspection can be used to protect hypervisors which are the basis of cloud security. Virtual machine introspection tools are usually deployed either in hypervisor or in privileged virtual machines, which might also be compromised. By utilizing hardware support including nested virtualization, EPT protection and #BP, we are able to monitor all hypercalls belongs to the virtual machines of one hypervisor, include that of privileged virtual machine and even when the hypervisor is compromised. What's more, hypercall injection method is used to simulate hypercall-based attacks and evaluate the performance of our method. Experiment results show that our method can effectively detect hypercall-based attacks with some performance cost. Lastly, we discuss our furture approaches of reducing the performance cost and preventing the compromised hypervisor from detecting the existence of our introspector, in addition with some new scenarios to apply our hypervisor introspection system.

  16. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  17. Secure coupling of hardware components

    NARCIS (Netherlands)

    Hoepman, J.H.; Joosten, H.J.M.; Knobbe, J.W.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and,

  18. Combining hardware and simulation for datacenter scaling studies

    DEFF Research Database (Denmark)

    Ruepp, Sarah Renée; Pilimon, Artur; Thrane, Jakob

    2017-01-01

    and simulation to illustrate the scalability and performance of datacenter networks. We simulate a Datacenter network and interconnect it with real world traffic generation hardware. Analysis of the introduced packet conversion and virtual queueing delays shows that the conversion efficiency is at the order...

  19. LHC challenges and upgrade options

    Energy Technology Data Exchange (ETDEWEB)

    Bruning, O [CERN AB/ABP, Y03600, 1211 Geneva 23 (Switzerland)], E-mail: Oliver.Bruning@cern.ch

    2008-05-15

    The presentation summarizes the key parameters of the LHC collider. Following a discussion of the main challenges for reaching the nominal machine performance the presentation identifies options for increasing the operation tolerances and the potential performance reach of the LHC by means of future hardware upgrades of the LHC and its injector complex.

  20. LHC challenges and upgrade options

    International Nuclear Information System (INIS)

    Bruning, O

    2008-01-01

    The presentation summarizes the key parameters of the LHC collider. Following a discussion of the main challenges for reaching the nominal machine performance the presentation identifies options for increasing the operation tolerances and the potential performance reach of the LHC by means of future hardware upgrades of the LHC and its injector complex

  1. Performance comparison between ISCSI and other hardware and software solutions

    CERN Document Server

    Gug, M

    2003-01-01

    We report on our investigations on some technologies that can be used to build disk servers and networks of disk servers using commodity hardware and software solutions. It focuses on the performance that can be achieved by these systems and gives measured figures for different configurations. It is divided into two parts : iSCSI and other technologies and hardware and software RAID solutions. The first part studies different technologies that can be used by clients to access disk servers using a gigabit ethernet network. It covers block access technologies (iSCSI, hyperSCSI, ENBD). Experimental figures are given for different numbers of clients and servers. The second part compares a system based on 3ware hardware RAID controllers, a system using linux software RAID and IDE cards and a system mixing both hardware RAID and software RAID. Performance measurements for reading and writing are given for different RAID levels.

  2. Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification

    OpenAIRE

    Drzevitzky, Stephanie; Kastens, Uwe; Platzner, Marco

    2010-01-01

    Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity but at the same time poses new challenges for security and safety. In this paper, we elaborate on the presentation of proof carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes ...

  3. Improving distribution efficiency of electrical network using geo-electrical options. A case study in a rural area of Assam (India)

    Energy Technology Data Exchange (ETDEWEB)

    Hazarika, S.; Hiloidhari, M.; Baruah, D.C. [Energy Conservation Laboratory, Department of Energy, Tezpur University, Tezpur, Assam (India)

    2012-11-15

    Reduction of electricity distribution loss is a major area of focus in India. This paper aims to investigate geo-electrical options to improve distribution efficiency of electrical network. Distribution efficiencies corresponding to several possible electrical network options are assessed using Geographical Information System (GIS) integrated electrical theory. An existing electrical distribution network of a rural area in Assam (India) is considered for the present investigation. Information related to characteristics of loads, features of conductors, and transformers of the existing network are used for this investigation. The line losses of the three existing transformers are estimated at about 36, 20, and 3 % of their respective connected loads. Longer distribution lines associated with higher loads are the causes of higher line losses. Using basic electrical theory and GIS tools, it is found that line losses can be reduced in the existing distribution system through management of distribution transformer and reconductoring. Two alternative locations for each of the three transformers are identified for optimal management of distribution transformers. Similarly, five different types of commercially available conductors are identified for possible reconductoring to reduce line loss. The economic viability of reconductoring of distribution lines are also assessed through an economic analysis. Net present values of total expenditure comprising purchase prices of conductor and cost attributed to line losses are estimated considering 30 years of useful life. The existing conductor has the worst economic merit, though it is the cheapest amongst all. A net saving of about USD 24,084 is possible through the best choice of distribution conductor for the village.

  4. Hardware Development Process for Human Research Facility Applications

    Science.gov (United States)

    Bauer, Liz

    2000-01-01

    well as modifications needed to meet program requirements. Options are consolidated and the hardware development team reaches a hardware development decision point. Within budget and schedule constraints, the team must decide whether or not to complete the hardware as an in-house, subcontract with vendor, or commercial-off-the-shelf (COTS) development. An in-house development indicates NASA personnel or a contractor builds the hardware at a NASA site. A subcontract development is completed off-site by a commercial company. A COTS item is a vendor product available by ordering a specific part number. The team evaluates the pros and cons of each development path. For example, in-bouse developments utilize existing corporate knowledge regarding bow to build equipment for use in space. However, technical expertise would be required to fully understand the medical equipment capabilities, such as for an ultrasound system. It may require additional time and funding to gain the expertise that commercially exists. The major benefit of subcontracting a hardware development is the product is delivered as an end-item and commercial expertise is utilized. On the other hand, NASA has limited control over schedule delays. The final option of COTS or modified COTS equipment is a compromise between in-house and subcontracts. A vendor product may exist that meets all functional requirements but req uires in-house modifications for successful operation in a space environment. The HRF utilizes equipment developed using all of the paths described: inhouse, subcontract, and modified COTS.

  5. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  6. Rehabilitation Options

    Science.gov (United States)

    ... Speech Pathology Occupational Therapy Art Therapy Recreational therapy Neuropsychology Home Care Options Advanced Care Planning Palliative Care ... Speech Pathology Occupational Therapy Art Therapy Recreational therapy Neuropsychology Home Care Options Advanced Care Planning Palliative Care ...

  7. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  8. Open source hardware solutions for low-cost, do-it-yourself environmental monitoring, citizen science, and STEM education

    Science.gov (United States)

    Hicks, S. D.; Aufdenkampe, A. K.; Horsburgh, J. S.; Arscott, D. B.; Muenz, T.; Bressler, D. W.

    2016-12-01

    The explosion in DIY open-source hardware and software has resulted in the development of affordable and accessible technologies, like drones and weather stations, that can greatly assist the general public in monitoring environmental health and its degradation. It is widely recognized that education and support of audiences in pursuit of STEM literacy and the application of emerging technologies is a challenge for the future of citizen science and for preparing high school graduates to be actively engaged in environmental stewardship. It is also clear that detecting environmental change/degradation over time and space will be greatly enhanced with expanded use of networked, remote monitoring technologies by watershed organizations and citizen scientists if data collection and reporting are properly carried out and curated. However, there are few focused efforts to link citizen scientists and school programs with these emerging tools. We have started a multi-year program to develop hardware and teaching materials for training students and citizen scientists about the use of open source hardware in environmental monitoring. Scientists and educators around the world have started building their own dataloggers and devices using a variety of boards based on open source electronics. This new hardware is now providing researchers with an inexpensive alternative to commercial data logging and transmission hardware. We will present a variety of hardware solutions using the Arduino-compatible EnviroDIY Mayfly board (http://envirodiy.org/mayfly) that can be used to build and deploy a rugged environmental monitoring station using a wide variety of sensors and options, giving the users a fully customizable device for making measurements almost anywhere. A database and visualization system is being developed that will allow the users to view and manage the data their devices are collecting. We will also present our plan for developing curricula and leading workshops to various

  9. Comparative efficacy and safety of treatment options for MDR and XDR Acinetobacter baumannii infections: a systematic review and network meta-analysis.

    Science.gov (United States)

    Kengkla, Kirati; Kongpakwattana, Khachen; Saokaew, Surasak; Apisarnthanarak, Anucha; Chaiyakunapruk, Nathorn

    2018-01-01

    To comprehensively compare and rank the efficacy and safety of available treatment options for patients with MDR and XDR Acinetobacter baumannii (AB) infection. We searched PubMed, Embase and the Cochrane register of trials systematically for studies that examined treatment options for patients with MDR- and XDR-AB infections until April 2016. Network meta-analysis (NMA) was performed to estimate the risk ratio (RR) and 95% CI from both direct and indirect evidence. Primary outcomes were clinical cure and microbiological cure. Secondary outcomes were all-cause mortality and nephrotoxic and non-nephrotoxic adverse events. A total of 29 studies with 2529 patients (median age 60 years; 65% male; median APACHE II score 19.0) were included. Although there were no statistically significant differences between treatment options, triple therapy with colistin, sulbactam and tigecycline had the highest clinical cure rate. Colistin in combination with sulbactam was associated with a significantly higher microbiological cure rate compared with colistin in combination with tigecycline (RR 1.23; 95% CI 1.03-1.47) and colistin monotherapy (RR 1.21; 95% CI 1.06-1.38). No significant differences in all-cause mortality were noted between treatment options. Tigecycline-based therapy also appeared less effective for achieving a microbiological cure and is not appropriate for treating bloodstream MDR- and XDR-AB infections. Combination therapy of colistin with sulbactam demonstrates superiority in terms of microbiological cure with a safety profile similar to that of colistin monotherapy. Thus, our findings support the use of this combination as a treatment for MDR- and XDR-AB infections. © The Author 2017. Published by Oxford University Press on behalf of the British Society for Antimicrobial Chemotherapy. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

  10. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  11. Hardware for dynamic quantum computing.

    Science.gov (United States)

    Ryan, Colm A; Johnson, Blake R; Ristè, Diego; Donovan, Brian; Ohki, Thomas A

    2017-10-01

    We describe the hardware, gateware, and software developed at Raytheon BBN Technologies for dynamic quantum information processing experiments on superconducting qubits. In dynamic experiments, real-time qubit state information is fed back or fed forward within a fraction of the qubits' coherence time to dynamically change the implemented sequence. The hardware presented here covers both control and readout of superconducting qubits. For readout, we created a custom signal processing gateware and software stack on commercial hardware to convert pulses in a heterodyne receiver into qubit state assignments with minimal latency, alongside data taking capability. For control, we developed custom hardware with gateware and software for pulse sequencing and steering information distribution that is capable of arbitrary control flow in a fraction of superconducting qubit coherence times. Both readout and control platforms make extensive use of field programmable gate arrays to enable tailored qubit control systems in a reconfigurable fabric suitable for iterative development.

  12. FY1995 evolvable hardware chip; 1995 nendo shinkasuru hardware chip

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    This project aims at the development of 'Evolvable Hardware' (EHW) which can adapt its hardware structure to the environment to attain better hardware performance, under the control of genetic algorithms. EHW is a key technology to explore the new application area requiring real-time performance and on-line adaptation. 1. Development of EHW-LSI for function level hardware evolution, which includes 15 DSPs in one chip. 2. Application of the EHW to the practical industrial applications such as data compression, ATM control, digital mobile communication. 3. Two patents : (1) the architecture and the processing method for programmable EHW-LSI. (2) The method of data compression for loss-less data, using EHW. 4. The first international conference for evolvable hardware was held by authors: Intl. Conf. on Evolvable Systems (ICES96). It was determined at ICES96 that ICES will be held every two years between Japan and Europe. So the new society has been established by us. (NEDO)

  13. The origins of options.

    Science.gov (United States)

    Smaldino, Paul E; Richerson, Peter J

    2012-01-01

    Most research on decision making has focused on how human or animal decision makers choose between two or more options, posed in advance by the researchers. The mechanisms by which options are generated for most decisions, however, are not well understood. Models of sequential search have examined the trade-off between continued exploration and choosing one's current best option, but still cannot explain the processes by which new options are generated. We argue that understanding the origins of options is a crucial but untapped area for decision making research. We explore a number of factors which influence the generation of options, which fall broadly into two categories: psycho-biological and socio-cultural. The former category includes factors such as perceptual biases and associative memory networks. The latter category relies on the incredible human capacity for culture and social learning, which doubtless shape not only our choices but the options available for choice. Our intention is to start a discussion that brings us closer toward understanding the origins of options.

  14. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  15. Evaluation of options for energy recovery from municipal solid waste in India using the hierarchical analytical network process

    International Nuclear Information System (INIS)

    Nixon, J.D.; Dey, P.K.; Ghosh, S.K.; Davies, P.A.

    2013-01-01

    In this paper a Hierarchical Analytical Network Process (HANP) model is demonstrated for evaluating alternative technologies for generating electricity from MSW in India. The technological alternatives and evaluation criteria for the HANP study are characterised by reviewing the literature and consulting experts in the field of waste management. Technologies reviewed in the context of India include landfill, anaerobic digestion, incineration, pelletisation and gasification. To investigate the sensitivity of the result, we examine variations in expert opinions and carry out an Analytical Hierarchy Process (AHP) analysis for comparison. We find that anaerobic digestion is the preferred technology for generating electricity from MSW in India. Gasification is indicated as the preferred technology in an AHP model due to the exclusion of criteria dependencies and in an HANP analysis when placing a high priority on net output and retention time. We conclude that HANP successfully provides a structured framework for recommending which technologies to pursue in India, and the adoption of such tools is critical at a time when key investments in infrastructure are being made. Therefore the presented methodology is thought to have a wider potential for investors, policy makers, researchers and plant developers in India and elsewhere. - Highlights: • We evaluate alternative technologies for generating electricity from waste. • The methodology we develop is based on the analytical network process. • Assessment is made against technical, financial, environmental and risk criteria. • Anaerobic digestion and gasification are the preferred technologies for India. • The method reduces risk and ensures sustainability in energy project planning

  16. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  17. Hardware standardization for embedded systems

    International Nuclear Information System (INIS)

    Sharma, M.K.; Kalra, Mohit; Patil, M.B.; Mohanty, Ashutos; Ganesh, G.; Biswas, B.B.

    2010-01-01

    Reactor Control Division (RCnD) has been one of the main designers of safety and safety related systems for power reactors. These systems have been built using in-house developed hardware. Since the present set of hardware was designed long ago, a need was felt to design a new family of hardware boards. A Working Group on Electronics Hardware Standardization (WG-EHS) was formed with an objective to develop a family of boards, which is general purpose enough to meet the requirements of the system designers/end users. RCnD undertook the responsibility of design, fabrication and testing of boards for embedded systems. VME and a proprietary I/O bus were selected as the two system buses. The boards have been designed based on present day technology and components. The intelligence of these boards has been implemented on FPGA/CPLD using VHDL. This paper outlines the various boards that have been developed with a brief description. (author)

  18. Commodity hardware and software summary

    International Nuclear Information System (INIS)

    Wolbers, S.

    1997-04-01

    A review is given of the talks and papers presented in the Commodity Hardware and Software Session at the CHEP97 conference. An examination of the trends leading to the consideration of PC's for HEP is given, and a status of the work that is being done at various HEP labs and Universities is given

  19. Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Christophe Bobda

    2009-01-01

    Full Text Available We present a methodology based on self-organization to manage resources in networked embedded systems based on reconfigurable hardware. Two points are detailed in this paper, the monitoring system used to analyse the system and the Local Marketplaces Global Symbiosis (LMGS concept defined for self-organization of dynamically reconfigurable nodes.

  20. Budget Options

    National Research Council Canada - National Science Library

    2000-01-01

    This volume-part of the Congressional Budget Office's (CBO's) annual report to the House and Senate Committees on the Budget-is intended to help inform policymakers about options for the federal budget...

  1. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  2. Computer hardware for radiologists: Part 2

    International Nuclear Information System (INIS)

    Indrajit, IK; Alam, A

    2010-01-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future

  3. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...... language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one...... or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has...

  4. Hardware-Accelerated Simulated Radiography

    International Nuclear Information System (INIS)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S.; Frank, R

    2005-01-01

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester

  5. The principles of computer hardware

    CERN Document Server

    Clements, Alan

    2000-01-01

    Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

  6. Hunting for hardware changes in data centres

    International Nuclear Information System (INIS)

    Coelho dos Santos, M; Steers, I; Szebenyi, I; Xafi, A; Barring, O; Bonfillou, E

    2012-01-01

    With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

  7. Binary Associative Memories as a Benchmark for Spiking Neuromorphic Hardware

    Directory of Open Access Journals (Sweden)

    Andreas Stöckel

    2017-08-01

    Full Text Available Large-scale neuromorphic hardware platforms, specialized computer systems for energy efficient simulation of spiking neural networks, are being developed around the world, for example as part of the European Human Brain Project (HBP. Due to conceptual differences, a universal performance analysis of these systems in terms of runtime, accuracy and energy efficiency is non-trivial, yet indispensable for further hard- and software development. In this paper we describe a scalable benchmark based on a spiking neural network implementation of the binary neural associative memory. We treat neuromorphic hardware and software simulators as black-boxes and execute exactly the same network description across all devices. Experiments on the HBP platforms under varying configurations of the associative memory show that the presented method allows to test the quality of the neuron model implementation, and to explain significant deviations from the expected reference output.

  8. Reconfigurable network processing platforms

    NARCIS (Netherlands)

    Kachris, C.

    2007-01-01

    This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network

  9. Speed challenge: a case for hardware implementation in soft-computing

    Science.gov (United States)

    Daud, T.; Stoica, A.; Duong, T.; Keymeulen, D.; Zebulum, R.; Thomas, T.; Thakoor, A.

    2000-01-01

    For over a decade, JPL has been actively involved in soft computing research on theory, architecture, applications, and electronics hardware. The driving force in all our research activities, in addition to the potential enabling technology promise, has been creation of a niche that imparts orders of magnitude speed advantage by implementation in parallel processing hardware with algorithms made especially suitable for hardware implementation. We review our work on neural networks, fuzzy logic, and evolvable hardware with selected application examples requiring real time response capabilities.

  10. Qualification of software and hardware

    International Nuclear Information System (INIS)

    Gossner, S.; Schueller, H.; Gloee, G.

    1987-01-01

    The qualification of on-line process control equipment is subdivided into three areas: 1) materials and structural elements; 2) on-line process-control components and devices; 3) electrical systems (reactor protection and confinement system). Microprocessor-aided process-control equipment are difficult to verify for failure-free function owing to the complexity of the functional structures of the hardware and to the variety of the software feasible for microprocessors. Hence, qualification will make great demands on the inspecting expert. (DG) [de

  11. Door Hardware and Installations; Carpentry: 901894.

    Science.gov (United States)

    Dade County Public Schools, Miami, FL.

    The curriculum guide outlines a course designed to provide instruction in the selection, preparation, and installation of hardware for door assemblies. The course is divided into five blocks of instruction (introduction to doors and hardware, door hardware, exterior doors and jambs, interior doors and jambs, and a quinmester post-test) totaling…

  12. High-performance reconfigurable hardware architecture for restricted Boltzmann machines.

    Science.gov (United States)

    Ly, Daniel Le; Chow, Paul

    2010-11-01

    Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications has been limited. A primary cause for this lack of adoption is that neural networks are usually implemented as software running on general-purpose processors. Hence, a hardware implementation that can exploit the inherent parallelism in neural networks is desired. This paper investigates how the restricted Boltzmann machine (RBM), which is a popular type of neural network, can be mapped to a high-performance hardware architecture on field-programmable gate array (FPGA) platforms. The proposed modular framework is designed to reduce the time complexity of the computations through heavily customized hardware engines. A method to partition large RBMs into smaller congruent components is also presented, allowing the distribution of one RBM across multiple FPGA resources. The framework is tested on a platform of four Xilinx Virtex II-Pro XC2VP70 FPGAs running at 100 MHz through a variety of different configurations. The maximum performance was obtained by instantiating an RBM of 256 × 256 nodes distributed across four FPGAs, which resulted in a computational speed of 3.13 billion connection-updates-per-second and a speedup of 145-fold over an optimized C program running on a 2.8-GHz Intel processor.

  13. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  14. Energy exotic options

    International Nuclear Information System (INIS)

    Kaminski, V.; Gibner, S.; Pinnamaneni, K.

    1999-01-01

    This chapter with 88 references focuses on the use of exotic options to control exposure to energy prices. Exotic options are defined, and the conversion of a standard option into an exotic option and pricing models are examined. Pricing and hedging exotic options, path-dependent options, multi-commodity options, options on the minimum-or-maximum of two commodities, compound options, digital options, hybrid and complex structures, and natural gas daily options are described. Formulas for option pricing for vanilla, barrier, compound, options on minimum or maximum of two assets, and look back options are given in an appendix

  15. Hardware Support for Dynamic Languages

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven; Probst, Christian W.

    2011-01-01

    In recent years, dynamic programming languages have enjoyed increasing popularity. For example, JavaScript has become one of the most popular programming languages on the web. As the complexity of web applications is growing, compute-intensive workloads are increasingly handed off to the client...... side. While a lot of effort is put in increasing the performance of web browsers, we aim for multicore systems with dedicated cores to effectively support dynamic languages. We have designed Tinuso, a highly flexible core for experimentation that is optimized for high performance when implemented...... on FPGA. We composed a scalable multicore configuration where we study how hardware support for software speculation can be used to increase the performance of dynamic languages....

  16. Peculiarities of hardware implementation of generalized cellular tetra automaton

    OpenAIRE

    Аноприенко, Александр Яковлевич; Федоров, Евгений Евгениевич; Иваница, Сергей Васильевич; Альрабаба, Хамза

    2015-01-01

    Cellular automata are widely used in many fields of knowledge for the study of variety of complex real processes: computer engineering and computer science, cryptography, mathematics, physics, chemistry, ecology, biology, medicine, epidemiology, geology, architecture, sociology, theory of neural networks. Thus, cellular automata (CA) and tetra automata are gaining relevance taking into account the hardware and software solutions.Also it is marked a trend towards an increase in the number of p...

  17. Options theory

    International Nuclear Information System (INIS)

    Markland, J.T.

    1992-01-01

    Techniques used in conventional project appraisal are mathematically very simple in comparison to those used in reservoir modelling, and in the geosciences. Clearly it would be possible to value assets in mathematically more sophisticated ways if it were meaningful and worthwhile so to do. The DCf approach in common use has recognized limitations; the inability to select a meaningful discount rate being particularly significant. Financial Theory has advanced enormously over the last few years, along with computational techniques, and methods are beginning to appear which may change the way we do project evaluations in practice. The starting point for all of this was a paper by Black and Scholes, which asserts that almost all corporate liabilities can be viewed as options of varying degrees of complexity. Although the financial presentation may be unfamiliar to engineers and geoscientists, some of the concepts used will not be. This paper outlines, in plain English, the basis of option pricing theory for assessing the market value of a project. it also attempts to assess the future role of this type of approach in practical Petroleum Exploration and Engineering economics. Reference is made to relevant published Natural Resource literature

  18. Hardware implementation of on -chip learning using re configurable FPGAS

    International Nuclear Information System (INIS)

    Kelash, H.M.; Sorour, H.S; Mahmoud, I.I.; Zaki, M; Haggag, S.S.

    2009-01-01

    The multilayer perceptron (MLP) is a neural network model that is being widely applied in the solving of diverse problems. A supervised training is necessary before the use of the neural network.A highly popular learning algorithm called back-propagation is used to train this neural network model. Once trained, the MLP can be used to solve classification problems. An interesting method to increase the performance of the model is by using hardware implementations. The hardware can do the arithmetical operations much faster than software. In this paper, a design and implementation of the sequential mode (stochastic mode) of backpropagation algorithm with on-chip learning using field programmable gate arrays (FPGA) is presented, a pipelined adaptation of the on-line back propagation algorithm (BP) is shown.The hardware implementation of forward stage, backward stage and update weight of backpropagation algorithm is also presented. This implementation is based on a SIMD parallel architecture of the forward propagation the diagnosis of the multi-purpose research reactor of Egypt accidents is used to test the proposed system

  19. Demonstration of Supervisory Control and Data Acquisition (SCADA) Virtualization Capability in the US Army Research Laboratory (ARL)/Sustaining Base Network Assurance Branch (SBNAB) US Army Cyber Analytics Laboratory (ACAL) SCADA Hardware Testbed

    Science.gov (United States)

    2015-05-01

    application ,1 while the simulated PLC software is the open source ModbusPal Java application . When queried using the Modbus TCP protocol, ModbusPal reports...and programmable logic controller ( PLC ) components. The HMI and PLC components were instantiated with software and installed in multiple virtual...creating and capturing HMI– PLC network traffic over a 24-h period in the virtualized network and inspect the packets for errors.  Test the

  20. Total knee arthroplasty using patient-specific blocks after prior femoral fracture without hardware removal

    Directory of Open Access Journals (Sweden)

    Raju Vaishya

    2018-01-01

    Full Text Available Background: The options to perform total knee arthroplasty (TKA with retained hardware in femur are mainly – removal of hardware, use of extramedullary guide, or computer-assisted surgery. Patient-specific blocks (PSBs have been introduced with many potential advantages, but their use in retained hardware has not been adequately explored. The purpose of the present study was to outline and assess the usefulness of the PSBs in performing TKA in patients with retained femoral hardware. Materials and Materials and Methods: Nine patients with retained femoral hardware underwent TKA using PSBs. All the surgeries were performed by the same surgeon using same implants. Nine cases (7 males and 2 females out of total of 120 primary TKA had retained hardware. The average age of the patients was 60.55 years. The retained hardware were 6 patients with nails, 2 with plates and one patient had screws. Out of the nine cases, only one patient needed removal of a screw which was hindering placement of pin for the PSB. Results: All the patients had significant improvement in their Knee Society Score (KSS which improved from 47.0 to postoperative KSS of 86.77 (P < 0.00. The mechanical axis was significantly improved (P < 0.03 after surgery. No patient required blood transfusion and the average tourniquet time was 41 min. Conclusion: TKA using PSBs is useful and can be used in patients with retained hardware with good functional and radiological outcome.

  1. Constructing Hardware in a Scale Embedded Language

    Energy Technology Data Exchange (ETDEWEB)

    2014-08-21

    Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

  2. Open-source hardware for medical devices.

    Science.gov (United States)

    Niezen, Gerrit; Eslambolchilar, Parisa; Thimbleby, Harold

    2016-04-01

    Open-source hardware is hardware whose design is made publicly available so anyone can study, modify, distribute, make and sell the design or the hardware based on that design. Some open-source hardware projects can potentially be used as active medical devices. The open-source approach offers a unique combination of advantages, including reducing costs and faster innovation. This article compares 10 of open-source healthcare projects in terms of how easy it is to obtain the required components and build the device.

  3. CT image reconstruction system based on hardware implementation

    International Nuclear Information System (INIS)

    Silva, Hamilton P. da; Evseev, Ivan; Schelin, Hugo R.; Paschuk, Sergei A.; Milhoretto, Edney; Setti, Joao A.P.; Zibetti, Marcelo; Hormaza, Joel M.; Lopes, Ricardo T.

    2009-01-01

    Full text: The timing factor is very important for medical imaging systems, which can nowadays be synchronized by vital human signals, like heartbeats or breath. The use of hardware implemented devices in such a system has advantages considering the high speed of information treatment combined with arbitrary low cost on the market. This article refers to a hardware system which is based on electronic programmable logic called FPGA, model Cyclone II from ALTERA Corporation. The hardware was implemented on the UP3 ALTERA Kit. A partially connected neural network with unitary weights was programmed. The system was tested with 60 topographic projections, 100 points in each, of the Shepp and Logan phantom created by MATLAB. The main restriction was found to be the memory size available on the device: the dynamic range of reconstructed image was limited to 0 65535. Also, the normalization factor must be observed in order to do not saturate the image during the reconstruction and filtering process. The test shows a principal possibility to build CT image reconstruction systems for any reasonable amount of input data by arranging the parallel work of the hardware units like we have tested. However, further studies are necessary for better understanding of the error propagation from topographic projections to reconstructed image within the implemented method. (author)

  4. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search.......This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...

  5. Louisiana Speaks Transportation Option C Roadway Improvements, UTM Zone 15N NAD 83, Louisiana Recovery Authority (2007), [louisiana_speaks_transportation_option_c_roadway_improvements

    Data.gov (United States)

    Louisiana Geographic Information Center — This GIS shapefile data illustrates the regional roadways included in the Louisiana Speaks community growth option of compact development (Option C). This network...

  6. Using Innovative Technologies for Manufacturing and Evaluating Rocket Engine Hardware

    Science.gov (United States)

    Betts, Erin M.; Hardin, Andy

    2011-01-01

    Many of the manufacturing and evaluation techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing and evaluating hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) and white light scanning are being adopted and evaluated for their use on J-2X, with hopes of employing both technologies on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powdered metal manufacturing process in order to produce complex part geometries. The white light technique is a non-invasive method that can be used to inspect for geometric feature alignment. Both the DMLS manufacturing method and the white light scanning technique have proven to be viable options for manufacturing and evaluating rocket engine hardware, and further development and use of these techniques is recommended.

  7. Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

    Directory of Open Access Journals (Sweden)

    O. Ahmed

    2013-01-01

    Full Text Available Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA that is scalable, fast, and efficient. GBSA consumes an average of 0.4 megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on an Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP implementation and two pure Register-Transfer Level (RTL implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on an Xeon processor.

  8. Computer hardware description languages - A tutorial

    Science.gov (United States)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  9. Wireless Sensor Networks Approach

    Science.gov (United States)

    Perotti, Jose M.

    2003-01-01

    This viewgraph presentation provides information on hardware and software configurations for a network architecture for sensors. The hardware configuration uses a central station and remote stations. The software configuration uses the 'lost station' software algorithm. The presentation profiles a couple current examples of this network architecture in use.

  10. An evaluation of Skylab habitability hardware

    Science.gov (United States)

    Stokes, J.

    1974-01-01

    For effective mission performance, participants in space missions lasting 30-60 days or longer must be provided with hardware to accommodate their personal needs. Such habitability hardware was provided on Skylab. Equipment defined as habitability hardware was that equipment composing the food system, water system, sleep system, waste management system, personal hygiene system, trash management system, and entertainment equipment. Equipment not specifically defined as habitability hardware but which served that function were the Wardroom window, the exercise equipment, and the intercom system, which was occasionally used for private communications. All Skylab habitability hardware generally functioned as intended for the three missions, and most items could be considered as adequate concepts for future flights of similar duration. Specific components were criticized for their shortcomings.

  11. Comparative Modal Analysis of Sieve Hardware Designs

    Science.gov (United States)

    Thompson, Nathaniel

    2012-01-01

    The CMTB Thwacker hardware operates as a testbed analogue for the Flight Thwacker and Sieve components of CHIMRA, a device on the Curiosity Rover. The sieve separates particles with a diameter smaller than 150 microns for delivery to onboard science instruments. The sieving behavior of the testbed hardware should be similar to the Flight hardware for the results to be meaningful. The elastodynamic behavior of both sieves was studied analytically using the Rayleigh Ritz method in conjunction with classical plate theory. Finite element models were used to determine the mode shapes of both designs, and comparisons between the natural frequencies and mode shapes were made. The analysis predicts that the performance of the CMTB Thwacker will closely resemble the performance of the Flight Thwacker within the expected steady state operating regime. Excitations of the testbed hardware that will mimic the flight hardware were recommended, as were those that will improve the efficiency of the sieving process.

  12. Neurostimulation options for failed back surgery syndrome: The need for rational and objective measurements. Proposal of an international clinical network using an integrated database and health economic analysis: the PROBACK network.

    Science.gov (United States)

    Rigoard, P; Slavin, K

    2015-03-01

    In the context of failed back surgery syndrome (FBSS) treatment, the current practice in neurostimulation varies from center-to-center and most clinical decisions are based on an individual diagnosis. Neurostimulation evaluation tools and pain relief assessment are of major concern, as they now constitute one of the main biases of clinical trials. Moreover, the proliferation of technological devices, in a fertile and unsatisfied market, fosters and only furthers the confusion. There are three options available to apply scientific debates to our daily neurostimulation practice: intentional ignorance, standardized evidence-based practice or alternative data mining approach. In view of the impossibility of conducting multiple randomized clinical trials comparing various devices, one by one, the proposed concept would be to redefine the indications and the respective roles of the various spinal cord and peripheral nerve stimulation devices with large-scale computational modeling/data mining approach, by conducting a multicenter prospective database registry, supported by a clinician's global network called "PROBACK". We chose to specifically analyze 6 parameters: device coverage performance/coverage selectivity/persistence of the long-term electrical response (technical criteria) and comparative mapping of patient pain relief/persistence of the long-term clinical response/safety and complications occurrence (clinical criteria). Two types of analysis will be performed: immediate analysis (including cost analysis) and computational analysis, i.e. demonstration of the robustness of certain correlations of variables, in order to extract response predictors. By creating an international prospective database, the purpose of the PROBACK project was to set up a process of extraction and comparative analysis of data derived from the selection, implantation and follow-up of FBSS patients candidates for implanted neurostimulation. This evaluation strategy should help to change

  13. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  14. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on......-chip communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  15. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  16. Multi-user software of radio therapeutical calculation using a computational network

    International Nuclear Information System (INIS)

    Allaucca P, J.J.; Picon C, C.; Zaharia B, M.

    1998-01-01

    It has been designed a hardware and software system for a radiotherapy Department. It runs under an Operative system platform Novell Network sharing the existing resources and of the server, it is centralized, multi-user and of greater safety. It resolves a variety of problems and calculation necessities, patient steps and administration, it is very fast and versatile, it contains a set of menus and options which may be selected with mouse, direction arrows or abbreviated keys. (Author)

  17. No-hardware-signature cybersecurity-crypto-module: a resilient cyber defense agent

    Science.gov (United States)

    Zaghloul, A. R. M.; Zaghloul, Y. A.

    2014-06-01

    We present an optical cybersecurity-crypto-module as a resilient cyber defense agent. It has no hardware signature since it is bitstream reconfigurable, where single hardware architecture functions as any selected device of all possible ones of the same number of inputs. For a two-input digital device, a 4-digit bitstream of 0s and 1s determines which device, of a total of 16 devices, the hardware performs as. Accordingly, the hardware itself is not physically reconfigured, but its performance is. Such a defense agent allows the attack to take place, rendering it harmless. On the other hand, if the system is already infected with malware sending out information, the defense agent allows the information to go out, rendering it meaningless. The hardware architecture is immune to side attacks since such an attack would reveal information on the attack itself and not on the hardware. This cyber defense agent can be used to secure a point-to-point, point-to-multipoint, a whole network, and/or a single entity in the cyberspace. Therefore, ensuring trust between cyber resources. It can provide secure communication in an insecure network. We provide the hardware design and explain how it works. Scalability of the design is briefly discussed. (Protected by United States Patents No.: US 8,004,734; US 8,325,404; and other National Patents worldwide.)

  18. Multistage switching hardware and software implementations for student experiment purpose

    Science.gov (United States)

    Sani, A.; Suherman

    2018-02-01

    Current communication and internet networks are underpinned by the switching technologies that interconnect one network to the others. Students’ understanding on networks rely on how they conver the theories. However, understanding theories without touching the reality may exert spots in the overall knowledge. This paper reports the progress of the multistage switching design and implementation for student laboratory activities. The hardware and software designs are based on three stages clos switching architecture with modular 2x2 switches, controlled by an arduino microcontroller. The designed modules can also be extended for batcher and bayan switch, and working on circuit and packet switching systems. The circuit analysis and simulation show that the blocking probability for each switch combinations can be obtained by generating random or patterned traffics. The mathematic model and simulation analysis shows 16.4% blocking probability differences as the traffic generation is uniform. The circuits design components and interfacing solution have been identified to allow next step implementation.

  19. Transmission delays in hardware clock synchronization

    Science.gov (United States)

    Shin, Kang G.; Ramanathan, P.

    1988-01-01

    Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in a system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been studied extensively in the communication area in the absence of malicious or Byzantine faults. The authors show that it is easy to incorporate the ideas from the communication area into the existing hardware clock synchronization algorithms to take into account the presence of both malicious faults and nonzero transmission delays.

  20. An Evaluation of optional timing/synchronization features to support selection of an optimum design for the DCS digital communication network

    Science.gov (United States)

    Bradley, D. B.; Cain, J. B., III; Williard, M. W.

    1978-01-01

    The task was to evaluate the ability of a set of timing/synchronization subsystem features to provide a set of desirable characteristics for the evolving Defense Communications System digital communications network. The set of features related to the approaches by which timing/synchronization information could be disseminated throughout the network and the manner in which this information could be utilized to provide a synchronized network. These features, which could be utilized in a large number of different combinations, included mutual control, directed control, double ended reference links, independence of clock error measurement and correction, phase reference combining, and self organizing.

  1. Hardware-in-the-Loop Testing

    Data.gov (United States)

    Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

  2. Hardware device binding and mutual authentication

    Science.gov (United States)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  3. Implementation of Hardware Accelerators on Zynq

    DEFF Research Database (Denmark)

    Toft, Jakob Kenn

    of the ARM Cortex-9 processor featured on the Zynq SoC, with regard to execution time, power dissipation and energy consumption. The implementation of the hardware accelerators were successful. Use of the Monte Carlo processor resulted in a significant increase in performance. The Telco hardware accelerator......In the recent years it has become obvious that the performance of general purpose processors are having trouble meeting the requirements of high performance computing applications of today. This is partly due to the relatively high power consumption, compared to the performance, of general purpose...... processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented on a Xilinx Zynq SoC platform mounted on the ZedBoard platform. The two accelerators are based on two different...

  4. Online Infrastructure in Supply Chain for Hardware Shops

    OpenAIRE

    Sørensen , Karl ,

    2014-01-01

    Part 4: Private Services; International audience; This article describes how the Scandinavian network communication system DATEX was used to build an online infrastructure in a retail chain of privately owned hardware shops and Do-It-Yourself (DIY) centers. The solution gave the staff in the shops the possibility to use EDP as early as in 1983. The Internet did not exist at the time. EDP was not part of the daily work in the shop and was for most employees something unknown that took place at...

  5. Designing Secure Systems on Reconfigurable Hardware

    OpenAIRE

    Huffmire, Ted; Brotherton, Brett; Callegari, Nick; Valamehr, Jonathan; White, Jeff; Kastner, Ryan; Sherwood, Ted

    2008-01-01

    The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers often have no choice but to use soft IP cores obtained from third parties, the cores operate at different trust levels, resulting in mixed trust designs. The goal of this project is to evaluate recently proposed security primitives for reconfigurab...

  6. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  7. Optimized design of embedded DSP system hardware supporting complex algorithms

    Science.gov (United States)

    Li, Yanhua; Wang, Xiangjun; Zhou, Xinling

    2003-09-01

    The paper presents an optimized design method for a flexible and economical embedded DSP system that can implement complex processing algorithms as biometric recognition, real-time image processing, etc. It consists of a floating-point DSP, 512 Kbytes data RAM, 1 Mbytes FLASH program memory, a CPLD for achieving flexible logic control of input channel and a RS-485 transceiver for local network communication. Because of employing a high performance-price ratio DSP TMS320C6712 and a large FLASH in the design, this system permits loading and performing complex algorithms with little algorithm optimization and code reduction. The CPLD provides flexible logic control for the whole DSP board, especially in input channel, and allows convenient interface between different sensors and DSP system. The transceiver circuit can transfer data between DSP and host computer. In the paper, some key technologies are also introduced which make the whole system work efficiently. Because of the characters referred above, the hardware is a perfect flat for multi-channel data collection, image processing, and other signal processing with high performance and adaptability. The application section of this paper presents how this hardware is adapted for the biometric identification system with high identification precision. The result reveals that this hardware is easy to interface with a CMOS imager and is capable of carrying out complex biometric identification algorithms, which require real-time process.

  8. 2D neural hardware versus 3D biological ones

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    This paper will present important limitations of hardware neural nets as opposed to biological neural nets (i.e. the real ones). The author starts by discussing neural structures and their biological inspirations, while mentioning the simplifications leading to artificial neural nets. Going further, the focus will be on hardware constraints. The author will present recent results for three different alternatives of implementing neural networks: digital, threshold gate, and analog, while the area and the delay will be related to neurons' fan-in and weights' precision. Based on all of these, it will be shown why hardware implementations cannot cope with their biological inspiration with respect to their power of computation: the mapping onto silicon lacking the third dimension of biological nets. This translates into reduced fan-in, and leads to reduced precision. The main conclusion is that one is faced with the following alternatives: (1) try to cope with the limitations imposed by silicon, by speeding up the computation of the elementary silicon neurons; (2) investigate solutions which would allow one to use the third dimension, e.g. using optical interconnections.

  9. Software for Managing Inventory of Flight Hardware

    Science.gov (United States)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  10. Conceptual Design Approach to Implementing Hardware-based Security Controls in Data Communication Systems

    Energy Technology Data Exchange (ETDEWEB)

    Ibrahim, Ahmad Salah; Jung, Jaecheon [KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

    2016-10-15

    In the Korean Advanced Power Reactor (APR1400), safety control systems network is electrically isolated and physically separated from non-safety systems data network. Unidirectional gateways, include data diode fiber-optic cabling and computer-based servers, transmit the plant safety critical parameters to the main control room (MCR) for control and monitoring processes. The data transmission is only one-way from safety to non-safety. Reverse communication is blocked so that safety systems network is protected from potential cyberattacks or intrusions from non-safety side. Most of commercials off-the-shelf (COTS) security devices are software-based solutions that require operating systems and processors to perform its functions. Field Programmable Gate Arrays (FPGAs) offer digital hardware solutions to implement security controls such as data packet filtering and deep data packet inspection. This paper presents a conceptual design to implement hardware-based network security controls for maintaining the availability of gateway servers. A conceptual design of hardware-based network security controls was discussed in this paper. The proposed design is aiming at utilizing the hardware-based capabilities of FPGAs together with filtering and DPI functions of COTS software-based firewalls and intrusion detection and prevention systems (IDPS). The proposed design implemented a network security perimeter between the DCN-I zone and gateway servers zone. Security control functions are to protect the gateway servers from potential DoS attacks that could affect the data availability and integrity.

  11. Conceptual Design Approach to Implementing Hardware-based Security Controls in Data Communication Systems

    International Nuclear Information System (INIS)

    Ibrahim, Ahmad Salah; Jung, Jaecheon

    2016-01-01

    In the Korean Advanced Power Reactor (APR1400), safety control systems network is electrically isolated and physically separated from non-safety systems data network. Unidirectional gateways, include data diode fiber-optic cabling and computer-based servers, transmit the plant safety critical parameters to the main control room (MCR) for control and monitoring processes. The data transmission is only one-way from safety to non-safety. Reverse communication is blocked so that safety systems network is protected from potential cyberattacks or intrusions from non-safety side. Most of commercials off-the-shelf (COTS) security devices are software-based solutions that require operating systems and processors to perform its functions. Field Programmable Gate Arrays (FPGAs) offer digital hardware solutions to implement security controls such as data packet filtering and deep data packet inspection. This paper presents a conceptual design to implement hardware-based network security controls for maintaining the availability of gateway servers. A conceptual design of hardware-based network security controls was discussed in this paper. The proposed design is aiming at utilizing the hardware-based capabilities of FPGAs together with filtering and DPI functions of COTS software-based firewalls and intrusion detection and prevention systems (IDPS). The proposed design implemented a network security perimeter between the DCN-I zone and gateway servers zone. Security control functions are to protect the gateway servers from potential DoS attacks that could affect the data availability and integrity

  12. Treatment Options for Retinoblastoma

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other places in the body. Treatment Option Overview Key Points There are different types of ...

  13. A hybrid modeling approach for option pricing

    Science.gov (United States)

    Hajizadeh, Ehsan; Seifi, Abbas

    2011-11-01

    The complexity of option pricing has led many researchers to develop sophisticated models for such purposes. The commonly used Black-Scholes model suffers from a number of limitations. One of these limitations is the assumption that the underlying probability distribution is lognormal and this is so controversial. We propose a couple of hybrid models to reduce these limitations and enhance the ability of option pricing. The key input to option pricing model is volatility. In this paper, we use three popular GARCH type model for estimating volatility. Then, we develop two non-parametric models based on neural networks and neuro-fuzzy networks to price call options for S&P 500 index. We compare the results with those of Black-Scholes model and show that both neural network and neuro-fuzzy network models outperform Black-Scholes model. Furthermore, comparing the neural network and neuro-fuzzy approaches, we observe that for at-the-money options, neural network model performs better and for both in-the-money and an out-of-the money option, neuro-fuzzy model provides better results.

  14. VEG-01: Veggie Hardware Verification Testing

    Science.gov (United States)

    Massa, Gioia; Newsham, Gary; Hummerick, Mary; Morrow, Robert; Wheeler, Raymond

    2013-01-01

    The Veggie plant/vegetable production system is scheduled to fly on ISS at the end of2013. Since much of the technology associated with Veggie has not been previously tested in microgravity, a hardware validation flight was initiated. This test will allow data to be collected about Veggie hardware functionality on ISS, allow crew interactions to be vetted for future improvements, validate the ability of the hardware to grow and sustain plants, and collect data that will be helpful to future Veggie investigators as they develop their payloads. Additionally, food safety data on the lettuce plants grown will be collected to help support the development of a pathway for the crew to safely consume produce grown on orbit. Significant background research has been performed on the Veggie plant growth system, with early tests focusing on the development of the rooting pillow concept, and the selection of fertilizer, rooting medium and plant species. More recent testing has been conducted to integrate the pillow concept into the Veggie hardware and to ensure that adequate water is provided throughout the growth cycle. Seed sanitation protocols have been established for flight, and hardware sanitation between experiments has been studied. Methods for shipping and storage of rooting pillows and the development of crew procedures and crew training videos for plant activities on-orbit have been established. Science verification testing was conducted and lettuce plants were successfully grown in prototype Veggie hardware, microbial samples were taken, plant were harvested, frozen, stored and later analyzed for microbial growth, nutrients, and A TP levels. An additional verification test, prior to the final payload verification testing, is desired to demonstrate similar growth in the flight hardware and also to test a second set of pillows containing zinnia seeds. Issues with root mat water supply are being resolved, with final testing and flight scheduled for later in 2013.

  15. From Open Source Software to Open Source Hardware

    OpenAIRE

    Viseur , Robert

    2012-01-01

    Part 2: Lightning Talks; International audience; The open source software principles progressively give rise to new initiatives for culture (free culture), data (open data) or hardware (open hardware). The open hardware is experiencing a significant growth but the business models and legal aspects are not well known. This paper is dedicated to the economics of open hardware. We define the open hardware concept and determine intellectual property tools we can apply to open hardware, with a str...

  16. Special issue on network coding

    Science.gov (United States)

    Monteiro, Francisco A.; Burr, Alister; Chatzigeorgiou, Ioannis; Hollanti, Camilla; Krikidis, Ioannis; Seferoglu, Hulya; Skachek, Vitaly

    2017-12-01

    Future networks are expected to depart from traditional routing schemes in order to embrace network coding (NC)-based schemes. These have created a lot of interest both in academia and industry in recent years. Under the NC paradigm, symbols are transported through the network by combining several information streams originating from the same or different sources. This special issue contains thirteen papers, some dealing with design aspects of NC and related concepts (e.g., fountain codes) and some showcasing the application of NC to new services and technologies, such as data multi-view streaming of video or underwater sensor networks. One can find papers that show how NC turns data transmission more robust to packet losses, faster to decode, and more resilient to network changes, such as dynamic topologies and different user options, and how NC can improve the overall throughput. This issue also includes papers showing that NC principles can be used at different layers of the networks (including the physical layer) and how the same fundamental principles can lead to new distributed storage systems. Some of the papers in this issue have a theoretical nature, including code design, while others describe hardware testbeds and prototypes.

  17. Using Innovative Technologies for Manufacturing Rocket Engine Hardware

    Science.gov (United States)

    Betts, E. M.; Eddleman, D. E.; Reynolds, D. C.; Hardin, N. A.

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As the United States enters into the next space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, rapid manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on NASA s Space Launch System (SLS) upper stage engine, J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator (GG) discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using a workhorse gas generator (WHGG) test fixture at MSFC's East Test Area, the duct was subjected to extreme J-2X hot gas environments during 7 tests for a total of 537 seconds of hot-fire time. The duct underwent extensive post-test evaluation and showed no signs of degradation. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  18. Using Innovative Techniques for Manufacturing Rocket Engine Hardware

    Science.gov (United States)

    Betts, Erin M.; Reynolds, David C.; Eddleman, David E.; Hardin, Andy

    2011-01-01

    Many of the manufacturing techniques that are currently used for rocket engine component production are traditional methods that have been proven through years of experience and historical precedence. As we enter into a new space age where new launch vehicles are being designed and propulsion systems are being improved upon, it is sometimes necessary to adopt new and innovative techniques for manufacturing hardware. With a heavy emphasis on cost reduction and improvements in manufacturing time, manufacturing techniques such as Direct Metal Laser Sintering (DMLS) are being adopted and evaluated for their use on J-2X, with hopes of employing this technology on a wide variety of future projects. DMLS has the potential to significantly reduce the processing time and cost of engine hardware, while achieving desirable material properties by using a layered powder metal manufacturing process in order to produce complex part geometries. Marshall Space Flight Center (MSFC) has recently hot-fire tested a J-2X gas generator discharge duct that was manufactured using DMLS. The duct was inspected and proof tested prior to the hot-fire test. Using the Workhorse Gas Generator (WHGG) test setup at MSFC?s East Test Area test stand 116, the duct was subject to extreme J-2X gas generator environments and endured a total of 538 seconds of hot-fire time. The duct survived the testing and was inspected after the test. DMLS manufacturing has proven to be a viable option for manufacturing rocket engine hardware, and further development and use of this manufacturing method is recommended.

  19. Flight Hardware Virtualization for On-Board Science Data Processing

    Data.gov (United States)

    National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

  20. THE INFLUENCE OF MAC BUFFER ON THE CONTENTION-BASED ACCESS SCHEME WITH BURSTING OPTION FOR IEEE 802.11E WIRELESS NETWORKS

    Directory of Open Access Journals (Sweden)

    S. SELVAKENNEDY

    2006-12-01

    Full Text Available Wireless LANs are increasingly being used for inelastic applications. Currently, there is little support for quality of service in the IEEE 802.11 MAC protocol, and IEEE task group E has defined the 802.11e MAC extension. Enhanced distributed channel access (EDCA is a contention-based scheme of the 802.11e standard. To allow a station to transmit more than one frame from a single contention, an optional feature known as controlled frame-bursting (CFB is introduced in the standard. In this paper, we initially performed an average analysis to determine a suitable burst duration limit. Then, a detailed evaluation and comparison of the EDCA protocol with the CFB option is carried out through simulation to quantify its performance gain. The impact of the MAC transmit buffer size is also incorporated. Accordingly, we have proposed a suitable approach to guide the configuration of the burst duration limit. It is demonstrated that an optimized CFB configuration allows the MAC protocol to achieve 30% more capacity than the basic EDCA scheme.

  1. GNSS CORS hardware and software enabling new science

    Science.gov (United States)

    Drummond, P.

    2009-12-01

    GNSS CORS networks are enabling new opportunities for science and public and private sector business. This paper will explore how the newest geodetic monitoring software and GNSS receiver hardware from Trimble Navigation Ltd are enabling new science. Technology trends and science opportunities will be explored. These trends include the installation of active GNSS control, automation of observations and processing, and the advantages of multi-observable and multi-constellation observations, all performed with the use of off the shelf products and industry standard open-source data formats. Also the possibilities with moving science from an after-the-fact postprocessed model to a real-time epoch-by-epoch solution will be explored. This presentation will also discuss the combination of existing GNSS CORS networks with project specific installations used for monitoring. Experience is showing GNSS is able to provide higher resolution data than previous methods, providing new tools for science, decision makers and financial planners.

  2. Spinal fusion-hardware construct: Basic concepts and imaging review

    Science.gov (United States)

    Nouh, Mohamed Ragab

    2012-01-01

    The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging. PMID:22761979

  3. Non-fuel bearing hardware melting technology

    International Nuclear Information System (INIS)

    Newman, D.F.

    1993-01-01

    Battelle has developed a portable hardware melter concept that would allow spent fuel rod consolidation operations at commercial nuclear power plants to provide significantly more storage space for other spent fuel assemblies in existing pool racks at lower cost. Using low pressure compaction, the non-fuel bearing hardware (NFBH) left over from the removal of spent fuel rods from the stainless steel end fittings and the Zircaloy guide tubes and grid spacers still occupies 1/3 to 2/5 of the volume of the consolidated fuel rod assemblies. Melting the non-fuel bearing hardware reduces its volume by a factor 4 from that achievable with low-pressure compaction. This paper describes: (1) the configuration and design features of Battelle's hardware melter system that permit its portability, (2) the system's throughput capacity, (3) the bases for capital and operating estimates, and (4) the status of NFBH melter demonstration to reduce technical risks for implementation of the concept. Since all NFBH handling and processing operations would be conducted at the reactor site, costs for shipping radioactive hardware to and from a stationary processing facility for volume reduction are avoided. Initial licensing, testing, and installation in the field would follow the successful pattern achieved with rod consolidation technology

  4. A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

    Science.gov (United States)

    Zinnecker, Alicia M.; Culley, Dennis E.; Aretskin-Hariton, Eliot D.

    2015-01-01

    Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

  5. Geographically Locating an Internet Node Using Network Latency Measurement

    National Research Council Canada - National Science Library

    Turnbaugh, Eugene

    2004-01-01

    .... The difficulties include accurate latency measure, network address translation (NAT) masking, service blocking, disparate physical configuration, dissimilar network hardware, and inaccurate and limited measuring tools...

  6. Coded Network Function Virtualization

    DEFF Research Database (Denmark)

    Al-Shuwaili, A.; Simone, O.; Kliewer, J.

    2016-01-01

    Network function virtualization (NFV) prescribes the instantiation of network functions on general-purpose network devices, such as servers and switches. While yielding a more flexible and cost-effective network architecture, NFV is potentially limited by the fact that commercial off......-the-shelf hardware is less reliable than the dedicated network elements used in conventional cellular deployments. The typical solution for this problem is to duplicate network functions across geographically distributed hardware in order to ensure diversity. In contrast, this letter proposes to leverage channel...... coding in order to enhance the robustness on NFV to hardware failure. The proposed approach targets the network function of uplink channel decoding, and builds on the algebraic structure of the encoded data frames in order to perform in-network coding on the signals to be processed at different servers...

  7. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

  8. Hardware Acceleration of Adaptive Neural Algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    James, Conrad D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-11-01

    As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

  9. MFTF supervisory control and diagnostics system hardware

    International Nuclear Information System (INIS)

    Butner, D.N.

    1979-01-01

    The Supervisory Control and Diagnostics System (SCDS) for the Mirror Fusion Test Facility (MFTF) is a multiprocessor minicomputer system designed so that for most single-point failures, the hardware may be quickly reconfigured to provide continued operation of the experiment. The system is made up of nine Perkin-Elmer computers - a mixture of 8/32's and 7/32's. Each computer has ports on a shared memory system consisting of two independent shared memory modules. Each processor can signal other processors through hardware external to the shared memory. The system communicates with the Local Control and Instrumentation System, which consists of approximately 65 microprocessors. Each of the six system processors has facilities for communicating with a group of microprocessors; the groups consist of from four to 24 microprocessors. There are hardware switches so that if an SCDS processor communicating with a group of microprocessors fails, another SCDS processor takes over the communication

  10. Australian Asian Options

    OpenAIRE

    Manuel Moreno; Javier F. Navas

    2003-01-01

    We study European options on the ratio of the stock price to its average and viceversa. Some of these options are traded in the Australian Stock Exchange since 1992, thus we call them Australian Asian options. For geometric averages, we obtain closed-form expressions for option prices. For arithmetic means, we use different approximations that produce very similar results.

  11. Options with Extreme Strikes

    Directory of Open Access Journals (Sweden)

    Lingjiong Zhu

    2015-07-01

    Full Text Available In this short paper, we study the asymptotics for the price of call options for very large strikes and put options for very small strikes. The stock price is assumed to follow the Black–Scholes models. We analyze European, Asian, American, Parisian and perpetual options and conclude that the tail asymptotics for these option types fall into four scenarios.

  12. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  13. Quantum neuromorphic hardware for quantum artificial intelligence

    Science.gov (United States)

    Prati, Enrico

    2017-08-01

    The development of machine learning methods based on deep learning boosted the field of artificial intelligence towards unprecedented achievements and application in several fields. Such prominent results were made in parallel with the first successful demonstrations of fault tolerant hardware for quantum information processing. To which extent deep learning can take advantage of the existence of a hardware based on qubits behaving as a universal quantum computer is an open question under investigation. Here I review the convergence between the two fields towards implementation of advanced quantum algorithms, including quantum deep learning.

  14. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  15. Penggunaan Power of Ethernet untuk Mengalirkan Arus Listrik ke Hardware yang Terhubung dengan Kabel UTP

    Directory of Open Access Journals (Sweden)

    Muhammad Safri Lubis

    2012-10-01

    Full Text Available Development of a local area network (LAN needs a network cable such as UTP twisted pair especially for connecting hardware like personal computer with CCTV. The connection should be on the basis of IP address which is connected with switch, and then the data eventually is sent to server. Generally, in the field, a hardware network has two main connection; first, connections to electricity for switching on the software by using an electricity cable which is suitable to the need of electrical capacity; second, connection to UTP twisted network for sending the data to the server. This process can be simplified by using network cable both for sending the data to server and for electrical pathway. Some pairs of network cable which are not used for sending data to server can be occupied to convey electrical wave to switch on and to operate the hardware. In order to use network cable for multiple purposes, it needs electrical configuration such as power of ethernet (PoE. The PoE is a system to utilize the UTP twisted pair cable to transmit unoccupied power for electrical pathway so that it can increase the efficiency of system.

  16. Packet Tracer network simulator

    CERN Document Server

    Jesin, A

    2014-01-01

    A practical, fast-paced guide that gives you all the information you need to successfully create networks and simulate them using Packet Tracer.Packet Tracer Network Simulator is aimed at students, instructors, and network administrators who wish to use this simulator to learn how to perform networking instead of investing in expensive, specialized hardware. This book assumes that you have a good amount of Cisco networking knowledge, and it will focus more on Packet Tracer rather than networking.

  17. CANDU Digital Control Computer upgrade options

    International Nuclear Information System (INIS)

    De Jong, M.S.; De Grosbois, J.; Qian, T.

    1997-01-01

    This paper reviews the evolution of Digital Control Computers (DCC) in CANDU power plants to the present day. Much of this evolution has been to meeting changing control or display requirements as well as the replacement of obsolete, or old and less reliable technology with better equipment that is now available. The current work at AECL and Canadian utilities to investigate DCC upgrade options, alternatives, and strategies are examined. The dependence of a particular upgrade strategy on the overall plant refurbishment plans are also discussed. Presently, the upgrade options range from replacement of individual obsolete system components, to replacement of the entire DCC hardware without changing the software, to complete replacement of the DCCs with a functionally equivalent system using new control computer equipment and software. Key issues, constraints and objectives associated with these DCC upgrade options are highlighted. (author)

  18. How to choose the right capitalization option.

    Science.gov (United States)

    Vaughan, J; Wise, J

    1996-12-01

    Physician group practices and networks must have ready access to capital to finance their working capital needs, capital equipment acquisitions, and real estate purchases, as well as to fund the acquisition of additional practices. At least three options for capitalization are available to group practices and networks: debt financing, equity financing, or a combination of the two. The best option for physician group practices and networks depends on the costs of capital and the impact the strategy will have on decision making and governance.

  19. Survey of Network Visualization Tools

    Science.gov (United States)

    2007-12-01

    programming language such as Java, C #, Delphi and Visual basic. AlgoCOMs Network also supports Visual Basic for Applications ( VBA ). Hardware: Users...AlgoCOMs Network also supports Visual Basic for Applications ( VBA ). Hardware: Users: Availability: • Commercially Available Cost $101...Application Monitoring - Constantly watch the health of your mission-critical applications: MS SQL , MS Exchange, MS IIS, Active Directory. Event

  20. ANNarchy: a code generation approach to neural simulations on parallel hardware

    Science.gov (United States)

    Vitay, Julien; Dinkelbach, Helge Ü.; Hamker, Fred H.

    2015-01-01

    Many modern neural simulators focus on the simulation of networks of spiking neurons on parallel hardware. Another important framework in computational neuroscience, rate-coded neural networks, is mostly difficult or impossible to implement using these simulators. We present here the ANNarchy (Artificial Neural Networks architect) neural simulator, which allows to easily define and simulate rate-coded and spiking networks, as well as combinations of both. The interface in Python has been designed to be close to the PyNN interface, while the definition of neuron and synapse models can be specified using an equation-oriented mathematical description similar to the Brian neural simulator. This information is used to generate C++ code that will efficiently perform the simulation on the chosen parallel hardware (multi-core system or graphical processing unit). Several numerical methods are available to transform ordinary differential equations into an efficient C++code. We compare the parallel performance of the simulator to existing solutions. PMID:26283957

  1. Enabling Open Hardware through FOSS tools

    CERN Multimedia

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  2. Hardware and layout aspects affecting maintainability

    International Nuclear Information System (INIS)

    Jayaraman, V.N.; Surendar, Ch.

    1977-01-01

    It has been found from maintenance experience at the Rajasthan Atomic Power Station that proper hardware and instrumentation layout can reduce maintenance and down-time on the related equipment. The problems faced in this connection and how they were solved is narrated. (M.G.B.)

  3. CAMAC high energy physics electronics hardware

    International Nuclear Information System (INIS)

    Kolpakov, I.F.

    1977-01-01

    CAMAC hardware for high energy physics large spectrometers and control systems is reviewed as is the development of CAMAC modules at the High Energy Laboratory, JINR (Dubna). The total number of crates used at the Laboratory is 179. The number of CAMAC modules of 120 different types exceeds 1700. The principles of organization and the structure of developed CAMAC systems are described. (author)

  4. Design of hardware accelerators for demanding applications.

    NARCIS (Netherlands)

    Jozwiak, L.; Jan, Y.

    2010-01-01

    This paper focuses on mastering the architecture development of hardware accelerators. It presents the results of our analysis of the main issues that have to be addressed when designing accelerators for modern demanding applications, when using as an example the accelerator design for LDPC decoding

  5. Building Correlators with Many-Core Hardware

    NARCIS (Netherlands)

    van Nieuwpoort, R.V.

    2010-01-01

    Radio telescopes typically consist of multiple receivers whose signals are cross-correlated to filter out noise. A recent trend is to correlate in software instead of custom-built hardware, taking advantage of the flexibility that software solutions offer. Examples include e-VLBI and LOFAR. However,

  6. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  7. Computer hardware for radiologists: Part I

    International Nuclear Information System (INIS)

    Indrajit, IK; Alam, A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium ® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration

  8. Environmental Control System Software & Hardware Development

    Science.gov (United States)

    Vargas, Daniel Eduardo

    2017-01-01

    ECS hardware: (1) Provides controlled purge to SLS Rocket and Orion spacecraft. (2) Provide mission-focused engineering products and services. ECS software: (1) NASA requires Compact Unique Identifiers (CUIs); fixed-length identifier used to identify information items. (2) CUI structure; composed of nine semantic fields that aid the user in recognizing its purpose.

  9. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  10. The fast Amsterdam multiprocessor (FAMP) system hardware

    International Nuclear Information System (INIS)

    Hertzberger, L.O.; Kieft, G.; Kisielewski, B.; Wiggers, L.W.; Engster, C.; Koningsveld, L. van

    1981-01-01

    The architecture of a multiprocessor system is described that will be used for on-line filter and second stage trigger applications. The system is based on the MC 68000 microprocessor from Motorola. Emphasis is paid to hardware aspects, in particular the modularity, processor communication and interfacing, whereas the system software and the applications will be described in separate articles. (orig.)

  11. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  12. The Effect of Superstar Software on Hardware Sales in System Markets

    NARCIS (Netherlands)

    J.L.G. Binken (Jeroen); S. Stremersch (Stefan)

    2008-01-01

    textabstractSystems are composed of complementary products (e.g., video game systems are composed of the video game console and video games). Prior literature on indirect network effects argues that, in system markets, sales of the primary product (often referred to as "hardware") largely depend on

  13. SEnviro: A Sensorized Platform Proposal Using Open Hardware and Open Standards

    Directory of Open Access Journals (Sweden)

    Sergio Trilles

    2015-03-01

    Full Text Available The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN. The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things. Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

  14. SEnviro: a sensorized platform proposal using open hardware and open standards.

    Science.gov (United States)

    Trilles, Sergio; Luján, Alejandro; Belmonte, Óscar; Montoliu, Raúl; Torres-Sospedra, Joaquín; Huerta, Joaquín

    2015-03-06

    The need for constant monitoring of environmental conditions has produced an increase in the development of wireless sensor networks (WSN). The drive towards smart cities has produced the need for smart sensors to be able to monitor what is happening in our cities. This, combined with the decrease in hardware component prices and the increase in the popularity of open hardware, has favored the deployment of sensor networks based on open hardware. The new trends in Internet Protocol (IP) communication between sensor nodes allow sensor access via the Internet, turning them into smart objects (Internet of Things and Web of Things). Currently, WSNs provide data in different formats. There is a lack of communication protocol standardization, which turns into interoperability issues when connecting different sensor networks or even when connecting different sensor nodes within the same network. This work presents a sensorized platform proposal that adheres to the principles of the Internet of Things and theWeb of Things. Wireless sensor nodes were built using open hardware solutions, and communications rely on the HTTP/IP Internet protocols. The Open Geospatial Consortium (OGC) SensorThings API candidate standard was used as a neutral format to avoid interoperability issues. An environmental WSN developed following the proposed architecture was built as a proof of concept. Details on how to build each node and a study regarding energy concerns are presented.

  15. Comparison of hardware firewalls in a network environment

    OpenAIRE

    Elnerud, Albin

    2017-01-01

    Today’s market offers a wide range of available firewalls, there are many manufacturers andeach of them has at least several series of possible solutions. As organisations and companiesseek to protect their assets against current and new hostile threats, the demands for networksecurity increases and drives the development of firewalls forward. With new firewalltechnologies emerging from a wide variety of firewall vendors, choosing the right firewall canbe both costly and time consuming. Requi...

  16. Interfacing Networks-on-Chip: Hardware meeting Software

    NARCIS (Netherlands)

    van de Burgwal, M.D.

    2010-01-01

    Next generation multi-media broadcast standards use encoded high-bandwidth streams of data to efficiently utilize the spectrum, at the cost of computation intensive processing. For battery powered portable devices this is challenging, as the energy source has limited capacity. By optimizing the

  17. Multi-user software of radio therapeutical calculation using a computational network; Software multiusuario de calculo radioterapeutico usando una red de computo

    Energy Technology Data Exchange (ETDEWEB)

    Allaucca P, J.J.; Picon C, C.; Zaharia B, M. [Departamento de Radioterapia, Instituto de Enfermedades Neoplasicas, Av. Angamos Este 2520, Lima 34 (Peru)

    1998-12-31

    It has been designed a hardware and software system for a radiotherapy Department. It runs under an Operative system platform Novell Network sharing the existing resources and of the server, it is centralized, multi-user and of greater safety. It resolves a variety of problems and calculation necessities, patient steps and administration, it is very fast and versatile, it contains a set of menus and options which may be selected with mouse, direction arrows or abbreviated keys. (Author)

  18. Networking

    OpenAIRE

    Rauno Lindholm, Daniel; Boisen Devantier, Lykke; Nyborg, Karoline Lykke; Høgsbro, Andreas; Fries, de; Skovlund, Louise

    2016-01-01

    The purpose of this project was to examine what influencing factor that has had an impact on the presumed increasement of the use of networking among academics on the labour market and how it is expressed. On the basis of the influence from globalization on the labour market it can be concluded that the globalization has transformed the labour market into a market based on the organization of networks. In this new organization there is a greater emphasis on employees having social qualificati...

  19. Traditional preventive treatment options

    DEFF Research Database (Denmark)

    Longbottom, C; Ekstrand, K; Zero, D

    2009-01-01

    Preventive treatment options can be divided into primary, secondary and tertiary prevention techniques, which can involve patient- or professionally applied methods. These include: oral hygiene (instruction), pit and fissure sealants ('temporary' or 'permanent'), fluoride applications (patient...... options....

  20. Breast Cancer: Treatment Options

    Science.gov (United States)

    ... Breast Cancer > Breast Cancer: Treatment Options Request Permissions Breast Cancer: Treatment Options Approved by the Cancer.Net Editorial ... can be addressed as quickly as possible. Recurrent breast cancer If the cancer does return after treatment for ...

  1. Options for Next Generation Digital Acquisition Systems

    CERN Document Server

    Boccardi, A

    2011-01-01

    Digital acquisition system designers have an always increasing number of options in terms of bus standards and digital signal processing hardware among which to choose. This allows for high flexibility but also opens the door to a proliferation of different architectures, potentially limiting the reusability and the design synergies among the various instrumentation groups. This contribution illustrates the design trends in some of the major institutes around the world with design examples including VME, PCI and TCA based modular systems using AMC and/or FMC mezzanines. Some examples of FPGA design practices aimed at increasing reusability of code will be mentioned together with some of the tools already available to designers to improve the information exchange and collaboration, like the Open Hardware Repository project.

  2. Distributed Energy Implementation Options

    Energy Technology Data Exchange (ETDEWEB)

    Shah, Chandralata N [National Renewable Energy Laboratory (NREL), Golden, CO (United States)

    2017-09-13

    This presentation covers the options for implementing distributed energy projects. It distinguishes between options available for distributed energy that is government owned versus privately owned, with a focus on the privately owned options including Energy Savings Performance Contract Energy Sales Agreements (ESPC ESAs). The presentation covers the new ESPC ESA Toolkit and other Federal Energy Management Program resources.

  3. Fuel cell hardware-in-loop

    Energy Technology Data Exchange (ETDEWEB)

    Moore, R.M.; Randolf, G.; Virji, M. [University of Hawaii, Hawaii Natural Energy Institute (United States); Hauer, K.H. [Xcellvision (Germany)

    2006-11-08

    Hardware-in-loop (HiL) methodology is well established in the automotive industry. One typical application is the development and validation of control algorithms for drive systems by simulating the vehicle plus the vehicle environment in combination with specific control hardware as the HiL component. This paper introduces the use of a fuel cell HiL methodology for fuel cell and fuel cell system design and evaluation-where the fuel cell (or stack) is the unique HiL component that requires evaluation and development within the context of a fuel cell system designed for a specific application (e.g., a fuel cell vehicle) in a typical use pattern (e.g., a standard drive cycle). Initial experimental results are presented for the example of a fuel cell within a fuel cell vehicle simulation under a dynamic drive cycle. (author)

  4. Hardware and software status of QCDOC

    International Nuclear Information System (INIS)

    Boyle, P.A.; Chen, D.; Christ, N.H.; Clark, M.; Cohen, S.D.; Cristian, C.; Dong, Z.; Gara, A.; Joo, B.; Jung, C.; Kim, C.; Levkova, L.; Liao, X.; Liu, G.; Mawhinney, R.D.; Ohta, S.; Petrov, K.; Wettig, T.; Yamaguchi, A.

    2004-01-01

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation

  5. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  6. A Scalable Approach for Hardware Semiformal Verification

    OpenAIRE

    Grimm, Tomas; Lettnin, Djones; Hübner, Michael

    2018-01-01

    The current verification flow of complex systems uses different engines synergistically: virtual prototyping, formal verification, simulation, emulation and FPGA prototyping. However, none is able to verify a complete architecture. Furthermore, hybrid approaches aiming at complete verification use techniques that lower the overall complexity by increasing the abstraction level. This work focuses on the verification of complex systems at the RT level to handle the hardware peculiarities. Our r...

  7. Hardware Design of a Smart Meter

    OpenAIRE

    Ganiyu A. Ajenikoko; Anthony A. Olaomi

    2014-01-01

    Smart meters are electronic measurement devices used by utilities to communicate information for billing customers and operating their electric systems. This paper presents the hardware design of a smart meter. Sensing and circuit protection circuits are included in the design of the smart meter in which resistors are naturally a fundamental part of the electronic design. Smart meters provides a route for energy savings, real-time pricing, automated data collection and elimina...

  8. Optimization Strategies for Hardware-Based Cofactorization

    Science.gov (United States)

    Loebenberger, Daniel; Putzka, Jens

    We use the specific structure of the inputs to the cofactorization step in the general number field sieve (GNFS) in order to optimize the runtime for the cofactorization step on a hardware cluster. An optimal distribution of bitlength-specific ECM modules is proposed and compared to existing ones. With our optimizations we obtain a speedup between 17% and 33% of the cofactorization step of the GNFS when compared to the runtime of an unoptimized cluster.

  9. Particle Transport Simulation on Heterogeneous Hardware

    CERN Multimedia

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  10. High exposure rate hardware ALARA plan

    International Nuclear Information System (INIS)

    Nellesen, A.L.

    1996-10-01

    This as low as reasonably achievable review provides a description of the engineering and administrative controls used to manage personnel exposure and to control contamination levels and airborne radioactivity concentrations. HERH waste is hardware found in the N-Fuel Storage Basin, which has a contact dose rate greater than 1 R/hr and used filters. This waste will be collected in the fuel baskets at various locations in the basins

  11. SYNTHESIS OF INFORMATION SYSTEM FOR SMART HOUSE HARDWARE MANAGEMENT

    Directory of Open Access Journals (Sweden)

    Vikentyeva Olga Leonidovna

    2017-10-01

    Full Text Available Subject: smart house maintenance requires taking into account a number of factors: resource-saving, reduction of operational expenditures, safety enhancement, providing comfortable working and leisure conditions. Automation of the corresponding engineering systems of illumination, climate control, security as well as communication systems and networks via utilization of contemporary technologies (e.g., IoT - Internet of Things poses a significant challenge related to storage and processing of the overwhelmingly massive volume of data whose utilization extent is extremely low nowadays. Since a building’s lifespan is large enough and exceeds the lifespan of codes and standards that take into account the requirements of safety, comfort, energy saving, etc., it is necessary to consider management aspects in the context of rational use of large data at the stage of information modeling. Research objectives: increase the efficiency of managing the subsystems of smart buildings hardware on the basis of a web-based information system that has a flexible multi-level architecture with several control loops and an adaptation model. Materials and methods: since a smart house belongs to man-machine systems, the cybernetic approach is considered as the basic method for design and research of information management system. Instrumental research methods are represented by set-theoretical modelling, automata theory and architectural principles of organization of information management systems. Results: a flexible architecture of information system for management of smart house hardware subsystems has been synthesized. This architecture encompasses several levels: client level, application level and data level as well as three layers: presentation level, actuating device layer and analytics layer. The problem of growing volumes of information processed by realtime message controller is attended by employment of sensors and actuating mechanisms with configurable

  12. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    International Nuclear Information System (INIS)

    Pappas, I; Kalenteridis, V; Vassiliadis, N; Pournara, H; Siozios, K; Koutroumpezis, G; Tatas, K; Nikolaidis, S; Siskos, S; Soudris, D J; Thanailakis, A

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 μm CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools

  13. Fine-grain reconfigurable platform: FPGA hardware design and software toolset development

    Energy Technology Data Exchange (ETDEWEB)

    Pappas, I [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Kalenteridis, V [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Vassiliadis, N [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Pournara, H [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siozios, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Koutroumpezis, G [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Tatas, K [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Nikolaidis, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Siskos, S [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece); Soudris, D J [VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100 Xanthi (Greece); Thanailakis, A [Electronics and Computers Div., Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki (Greece)

    2005-01-01

    A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts. The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. A novel energy-efficient FPGA architecture is presented (CLB, interconnect network, configuration hardware) and simulated in STM 0.18 {mu}m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

  14. The design of a hardware testing system for the D Zero Detector

    International Nuclear Information System (INIS)

    Angstadt, R.; Johnson, M.; Martin, M.; Matulik, M.; Utes, M.

    1991-11-01

    Testing a system as large as the D Zero data acquisition system is difficult. This paper describes the use of IBM compatible personal computers in a hardware test system that can run on any size system from an engineer's test bench to the entire subsystem in the D Zero Detector. The test system uses a PC to VME bus interface for the local testing and the Token Ring network for more global testing. This system has been implemented for several different hardware systems in D Zero

  15. Cognon Neural Model Software Verification and Hardware Implementation Design

    Science.gov (United States)

    Haro Negre, Pau

    Little is known yet about how the brain can recognize arbitrary sensory patterns within milliseconds using neural spikes to communicate information between neurons. In a typical brain there are several layers of neurons, with each neuron axon connecting to ˜104 synapses of neurons in an adjacent layer. The information necessary for cognition is contained in theses synapses, which strengthen during the learning phase in response to newly presented spike patterns. Continuing on the model proposed in "Models for Neural Spike Computation and Cognition" by David H. Staelin and Carl H. Staelin, this study seeks to understand cognition from an information theoretic perspective and develop potential models for artificial implementation of cognition based on neuronal models. To do so we focus on the mathematical properties and limitations of spike-based cognition consistent with existing neurological observations. We validate the cognon model through software simulation and develop concepts for an optical hardware implementation of a network of artificial neural cognons.

  16. An Overview of Reconfigurable Hardware in Embedded Systems

    Directory of Open Access Journals (Sweden)

    Wenyin Fu

    2006-09-01

    Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

  17. Trends in computer hardware and software.

    Science.gov (United States)

    Frankenfeld, F M

    1993-04-01

    Previously identified and current trends in the development of computer systems and in the use of computers for health care applications are reviewed. Trends identified in a 1982 article were increasing miniaturization and archival ability, increasing software costs, increasing software independence, user empowerment through new software technologies, shorter computer-system life cycles, and more rapid development and support of pharmaceutical services. Most of these trends continue today. Current trends in hardware and software include the increasing use of reduced instruction-set computing, migration to the UNIX operating system, the development of large software libraries, microprocessor-based smart terminals that allow remote validation of data, speech synthesis and recognition, application generators, fourth-generation languages, computer-aided software engineering, object-oriented technologies, and artificial intelligence. Current trends specific to pharmacy and hospitals are the withdrawal of vendors of hospital information systems from the pharmacy market, improved linkage of information systems within hospitals, and increased regulation by government. The computer industry and its products continue to undergo dynamic change. Software development continues to lag behind hardware, and its high cost is offsetting the savings provided by hardware.

  18. Software error masking effect on hardware faults

    International Nuclear Information System (INIS)

    Choi, Jong Gyun; Seong, Poong Hyun

    1999-01-01

    Based on the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), in this work, a simulation model for fault injection is developed to estimate the dependability of the digital system in operational phase. We investigated the software masking effect on hardware faults through the single bit-flip and stuck-at-x fault injection into the internal registers of the processor and memory cells. The fault location reaches all registers and memory cells. Fault distribution over locations is randomly chosen based on a uniform probability distribution. Using this model, we have predicted the reliability and masking effect of an application software in a digital system-Interposing Logic System (ILS) in a nuclear power plant. We have considered four the software operational profiles. From the results it was found that the software masking effect on hardware faults should be properly considered for predicting the system dependability accurately in operation phase. It is because the masking effect was formed to have different values according to the operational profile

  19. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  20. Instrument hardware and software upgrades at IPNS

    International Nuclear Information System (INIS)

    Worlton, Thomas; Hammonds, John; Mikkelson, D.; Mikkelson, Ruth; Porter, Rodney; Tao, Julian; Chatterjee, Alok

    2006-01-01

    IPNS is in the process of upgrading their time-of-flight neutron scattering instruments with improved hardware and software. The hardware upgrades include replacing old VAX Qbus and Multibus-based data acquisition systems with new systems based on VXI and VME. Hardware upgrades also include expanded detector banks and new detector electronics. Old VAX Fortran-based data acquisition and analysis software is being replaced with new software as part of the ISAW project. ISAW is written in Java for ease of development and portability, and is now used routinely for data visualization, reduction, and analysis on all upgraded instruments. ISAW provides the ability to process and visualize the data from thousands of detector pixels, each having thousands of time channels. These operations can be done interactively through a familiar graphical user interface or automatically through simple scripts. Scripts and operators provided by end users are automatically included in the ISAW menu structure, along with those distributed with ISAW, when the application is started

  1. TANK SPACE OPTIONS REPORT

    International Nuclear Information System (INIS)

    Willis, W.L.; Ahrendt, M.R.

    2009-01-01

    Since this report was originally issued in 2001, several options proposed for increasing double-shell tank (DST) storage space were implemented or are in the process of implementation. Changes to the single-shell tank (SST) waste retrieval schedule, completion of DST space saving options, and the DST space saving options in progress have delayed the projected shortfall of DST storage space from the 2007-2011 to the 2018-2025 timeframe (ORP-11242, River Protection Project System Plan). This report reevaluates options from Rev. 0 and includes evaluations of new options for alleviating projected restrictions on SST waste retrieval beginning in 2018 because of the lack of DST storage space.

  2. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    Directory of Open Access Journals (Sweden)

    Cancare Fabio

    2009-07-01

    Full Text Available Abstract Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs have more memory bandwidth and computational capability than Central Processing Units (CPUs and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective

  3. Accelerating epistasis analysis in human genetics with consumer graphics hardware.

    Science.gov (United States)

    Sinnott-Armstrong, Nicholas A; Greene, Casey S; Cancare, Fabio; Moore, Jason H

    2009-07-24

    Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR) is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs) have more memory bandwidth and computational capability than Central Processing Units (CPUs) and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective performance while leaving the CPU available for other

  4. Trainable hardware for dynamical computing using error backpropagation through physical media.

    Science.gov (United States)

    Hermans, Michiel; Burm, Michaël; Van Vaerenbergh, Thomas; Dambre, Joni; Bienstman, Peter

    2015-03-24

    Neural networks are currently implemented on digital Von Neumann machines, which do not fully leverage their intrinsic parallelism. We demonstrate how to use a novel class of reconfigurable dynamical systems for analogue information processing, mitigating this problem. Our generic hardware platform for dynamic, analogue computing consists of a reciprocal linear dynamical system with nonlinear feedback. Thanks to reciprocity, a ubiquitous property of many physical phenomena like the propagation of light and sound, the error backpropagation-a crucial step for tuning such systems towards a specific task-can happen in hardware. This can potentially speed up the optimization process significantly, offering important benefits for the scalability of neuro-inspired hardware. In this paper, we show, using one experimentally validated and one conceptual example, that such systems may provide a straightforward mechanism for constructing highly scalable, fully dynamical analogue computers.

  5. FPGA-based network data transmission scheme for CSNS

    International Nuclear Information System (INIS)

    Wang Xiuku; Zhang Hongyu; Gu Minhao; Xiao Liang

    2012-01-01

    This paper presents the FPGA-based network data transmission solutions for the Data Acquisition System of China Spallation Neutron Source (CSNS). The board with FPGA as the core is used as the hardware platform to realize the transmission of network data. A SOPC system is built and an embedded Linux is transplanted on PowerPC Core. An application program based on Linux has been finished to realize the data transmission via embedded Gigabit Ethernet. The relationship between network transfer performance and packet size was obtained by a test program. In addition, the paper also tried to realize some other ways to transfer data: transplanting PetaLinux on Microblaze, transplanting Lwip protocol stack on PowerPC Core and Microblaze. Their advantages and disadvantages are analyzed and compared in this paper, so that different options and recommendations can be given to meet the actual needs of different projects in the future. (authors)

  6. D0 HVAC System Controls Evaluation of Upgrade Options

    International Nuclear Information System (INIS)

    Markley, D.; Simon, P.

    1998-01-01

    This engineering note documents three different options for upgrading the Dzero HVAC control system. All three options leave the current field hardware and field devices intact and upgrade the computer control hardware and software. Dzero will be heading into a physics run starting in 2000. This physics run could last several years. The Dzero HVAC system is an integral part of climate control and electronics cooling. The current HVAC control system is based upon a 1985 Johnson Controls System. In order to enter the next long-term physics run with a solid HVAC control system, the current control system needs to be upgraded. This proposal investigates three options: (1) Replacement to the next generation of Johnson Controls Hardware and Software with the Johnson Controls operator interface - FESS; (2) Replacement to the next generation of Johnson Controls Hardware and Software with the FIX32 Operator Interface - FESS/Dzero; and (3) Replacement with a commercially available Programmable Logic Controller (PLC) WITH THE FIX 32 Operator Interface - Dzero.

  7. Hardware implementation of a GFSR pseudo-random number generator

    Science.gov (United States)

    Aiello, G. R.; Budinich, M.; Milotti, E.

    1989-12-01

    We describe the hardware implementation of a pseudo-random number generator of the "Generalized Feedback Shift Register" (GFSR) type. After brief theoretical considerations we describe two versions of the hardware, the tests done and the performances achieved.

  8. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  9. Open Hardware for CERN's accelerator control systems

    International Nuclear Information System (INIS)

    Bij, E van der; Serrano, J; Wlostowski, T; Cattin, M; Gousiou, E; Sanchez, P Alvarez; Boccardi, A; Voumard, N; Penacoba, G

    2012-01-01

    The accelerator control systems at CERN will be upgraded and many electronics modules such as analog and digital I/O, level converters and repeaters, serial links and timing modules are being redesigned. The new developments are based on the FPGA Mezzanine Card, PCI Express and VME64x standards while the Wishbone specification is used as a system on a chip bus. To attract partners, the projects are developed in an 'Open' fashion. Within this Open Hardware project new ways of working with industry are being evaluated and it has been proven that industry can be involved at all stages, from design to production and support.

  10. Hardware for computing the integral image

    OpenAIRE

    Fernández-Berni, J.; Rodríguez-Vázquez, Ángel; Río, Rocío del; Carmona-Galán, R.

    2015-01-01

    La presente invención, según se expresa en el enunciado de esta memoria descriptiva, consiste en hardware de señal mixta para cómputo de la imagen integral en el plano focal mediante una agrupación de celdas básicas de sensado-procesamiento cuya interconexión puede ser reconfigurada mediante circuitería periférica que hace posible una implementación muy eficiente de una tarea de procesamiento muy útil en visión artificial como es el cálculo de la imagen integral en escenarios tales como monit...

  11. Development of Hardware Dual Modality Tomography System

    Directory of Open Access Journals (Sweden)

    R. M. Zain

    2009-06-01

    Full Text Available The paper describes the hardware development and performance of the Dual Modality Tomography (DMT system. DMT consists of optical and capacitance sensors. The optical sensors consist of 16 LEDs and 16 photodiodes. The Electrical Capacitance Tomography (ECT electrode design use eight electrode plates as the detecting sensor. The digital timing and the control unit have been developing in order to control the light projection of optical emitters, switching the capacitance electrodes and to synchronize the operation of data acquisition. As a result, the developed system is able to provide a maximum 529 set data per second received from the signal conditioning circuit to the computer.

  12. Fast Gridding on Commodity Graphics Hardware

    DEFF Research Database (Denmark)

    Sørensen, Thomas Sangild; Schaeffter, Tobias; Noe, Karsten Østergaard

    2007-01-01

    is the far most time consuming of the three steps (Table 1). Modern graphics cards (GPUs) can be utilised as a fast parallel processor provided that algorithms are reformulated in a parallel solution. The purpose of this work is to test the hypothesis, that a non-cartesian reconstruction can be efficiently...... implemented on graphics hardware giving a significant speedup compared to CPU based alternatives. We present a novel GPU implementation of the convolution step that overcomes the problems of memory bandwidth that has limited the speed of previous GPU gridding algorithms [2]....

  13. Reconfigurable Hardware for Compressing Hyperspectral Image Data

    Science.gov (United States)

    Aranki, Nazeeh; Namkung, Jeffrey; Villapando, Carlos; Kiely, Aaron; Klimesh, Matthew; Xie, Hua

    2010-01-01

    High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of

  14. List search hardware for interpretive software

    CERN Document Server

    Altaber, Jacques; Mears, B; Rausch, R

    1979-01-01

    Interpreted languages, e.g. BASIC, are simple to learn, easy to use, quick to modify and in general 'user-friendly'. However, a critically time consuming process during interpretation is that of list searching. A special microprogrammed device for fast list searching has therefore been developed at the SPS Division of CERN. It uses bit- sliced hardware. Fast algorithms perform search, insert and delete of a six-character name and its value in a list of up to 1000 pairs. The prototype shows retrieval times of the order of 10-30 microseconds. (11 refs).

  15. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  16. Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices

    Directory of Open Access Journals (Sweden)

    Ikbel Belaid

    2011-01-01

    Full Text Available Task graph scheduling for reconfigurable hardware devices can be defined as finding a schedule for a set of periodic tasks with precedence, dependence, and deadline constraints as well as their optimal allocations on the available heterogeneous hardware resources. This paper proposes a new methodology comprising three main stages. Using these three main stages, dynamic partial reconfiguration and mixed integer programming, pipelined scheduling and efficient placement are achieved and enable parallel computing of the task graph on the reconfigurable devices by optimizing placement/scheduling quality. Experiments on an application of heterogeneous hardware tasks demonstrate an improvement of resource utilization of 12.45% of the available reconfigurable resources corresponding to a resource gain of 17.3% compared to a static design. The configuration overhead is reduced to 2% of the total running time. Due to pipelined scheduling, the task graph spanning is minimized by 4% compared to sequential execution of the graph.

  17. Is Hardware Removal Recommended after Ankle Fracture Repair?

    Directory of Open Access Journals (Sweden)

    Hong-Geun Jung

    2016-01-01

    Full Text Available The indications and clinical necessity for routine hardware removal after treating ankle or distal tibia fracture with open reduction and internal fixation are disputed even when hardware-related pain is insignificant. Thus, we determined the clinical effects of routine hardware removal irrespective of the degree of hardware-related pain, especially in the perspective of patients’ daily activities. This study was conducted on 80 consecutive cases (78 patients treated by surgery and hardware removal after bony union. There were 56 ankle and 24 distal tibia fractures. The hardware-related pain, ankle joint stiffness, discomfort on ambulation, and patient satisfaction were evaluated before and at least 6 months after hardware removal. Pain score before hardware removal was 3.4 (range 0 to 6 and decreased to 1.3 (range 0 to 6 after removal. 58 (72.5% patients experienced improved ankle stiffness and 65 (81.3% less discomfort while walking on uneven ground and 63 (80.8% patients were satisfied with hardware removal. These results suggest that routine hardware removal after ankle or distal tibia fracture could ameliorate hardware-related pain and improves daily activities and patient satisfaction even when the hardware-related pain is minimal.

  18. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  19. CASIS Fact Sheet: Hardware and Facilities

    Science.gov (United States)

    Solomon, Michael R.; Romero, Vergel

    2016-01-01

    Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

  20. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  1. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  2. Fast image processing on parallel hardware

    International Nuclear Information System (INIS)

    Bittner, U.

    1988-01-01

    Current digital imaging modalities in the medical field incorporate parallel hardware which is heavily used in the stage of image formation like the CT/MR image reconstruction or in the DSA real time subtraction. In order to image post-processing as efficient as image acquisition, new software approaches have to be found which take full advantage of the parallel hardware architecture. This paper describes the implementation of two-dimensional median filter which can serve as an example for the development of such an algorithm. The algorithm is analyzed by viewing it as a complete parallel sort of the k pixel values in the chosen window which leads to a generalization to rank order operators and other closely related filters reported in literature. A section about the theoretical base of the algorithm gives hints for how to characterize operations suitable for implementations on pipeline processors and the way to find the appropriate algorithms. Finally some results that computation time and usefulness of medial filtering in radiographic imaging are given

  3. Class network routing

    Science.gov (United States)

    Bhanot, Gyan [Princeton, NJ; Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Takken, Todd E [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

    2009-09-08

    Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

  4. Americal options analyzed differently

    NARCIS (Netherlands)

    Nieuwenhuis, J.W.

    2003-01-01

    In this note we analyze in a discrete-time context and with a finite outcome space American options starting with the idea that every tradable should be a martingale under a certain measure. We believe that in this way American options become more understandable to people with a good working

  5. Traffic Light Options

    DEFF Research Database (Denmark)

    Jørgensen, Peter Løchte

    This paper introduces, prices, and analyzes traffic light options. The traffic light option is an innovative structured OTC derivative developed independently by several London-based investment banks to suit the needs of Danish life and pension (L&P) companies, which must comply with the traffic...... 2006, and supervisory authorities in many other European countries have implemented similar regulation. Traffic light options are therefore likely to attract the attention of a wider audience of pension fund managers in the future. Focusing on the valuation of the traffic light option we set up a Black...... light scenarios. These stress scenarios entail drops in interest rates as well as in stock prices, and traffic light options are thus designed to pay off and preserve sufficient capital when interest rates and stock prices fall simultaneously. Sweden's FSA implemented a traffic light system in January...

  6. Traffic Light Options

    DEFF Research Database (Denmark)

    Jørgensen, Peter Løchte

    2007-01-01

    This paper introduces, prices, and analyzes traffic light options. The traffic light option is an innovative structured OTC derivative developed independently by several London-based investment banks to suit the needs of Danish life and pension (L&P) companies, which must comply with the traffic...... 2006, and supervisory authorities in many other European countries have implemented similar regulation. Traffic light options are therefore likely to attract the attention of a wider audience of pension fund managers in the future. Focusing on the valuation of the traffic light option we set up a Black...... light scenarios. These stress scenarios entail drops in interest rates as well as in stock prices, and traffic light options are thus designed to pay off and preserve sufficient capital when interest rates and stock prices fall simultaneously. Sweden's FSA implemented a traffic light system in January...

  7. Exploring Infiniband Hardware Virtualization in OpenNebula towards Efficient High-Performance Computing

    Energy Technology Data Exchange (ETDEWEB)

    Pais Pitta de Lacerda Ruivo, Tiago [IIT, Chicago; Bernabeu Altayo, Gerard [Fermilab; Garzoglio, Gabriele [Fermilab; Timm, Steven [Fermilab; Kim, Hyun-Woo [Fermilab; Noh, Seo-Young [KISTI, Daejeon; Raicu, Ioan [IIT, Chicago

    2014-11-11

    has been widely accepted that software virtualization has a big negative impact on high-performance computing (HPC) application performance. This work explores the potential use of Infiniband hardware virtualization in an OpenNebula cloud towards the efficient support of MPI-based workloads. We have implemented, deployed, and tested an Infiniband network on the FermiCloud private Infrastructure-as-a-Service (IaaS) cloud. To avoid software virtualization towards minimizing the virtualization overhead, we employed a technique called Single Root Input/Output Virtualization (SRIOV). Our solution spanned modifications to the Linux’s Hypervisor as well as the OpenNebula manager. We evaluated the performance of the hardware virtualization on up to 56 virtual machines connected by up to 8 DDR Infiniband network links, with micro-benchmarks (latency and bandwidth) as well as w a MPI-intensive application (the HPL Linpack benchmark).

  8. [Hardware Implementation of Numerical Simulation Function of Hodgkin-Huxley Model Neurons Action Potential Based on Field Programmable Gate Array].

    Science.gov (United States)

    Wang, Jinlong; Lu, Mai; Hu, Yanwen; Chen, Xiaoqiang; Pan, Qiangqiang

    2015-12-01

    Neuron is the basic unit of the biological neural system. The Hodgkin-Huxley (HH) model is one of the most realistic neuron models on the electrophysiological characteristic description of neuron. Hardware implementation of neuron could provide new research ideas to clinical treatment of spinal cord injury, bionics and artificial intelligence. Based on the HH model neuron and the DSP Builder technology, in the present study, a single HH model neuron hardware implementation was completed in Field Programmable Gate Array (FPGA). The neuron implemented in FPGA was stimulated by different types of current, the action potential response characteristics were analyzed, and the correlation coefficient between numerical simulation result and hardware implementation result were calculated. The results showed that neuronal action potential response of FPGA was highly consistent with numerical simulation result. This work lays the foundation for hardware implementation of neural network.

  9. Handbook of hardware/software codesign

    CERN Document Server

    Teich, Jürgen

    2017-01-01

    This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook. .

  10. Battery Management System Hardware Concepts: An Overview

    Directory of Open Access Journals (Sweden)

    Markus Lelie

    2018-03-01

    Full Text Available This paper focuses on the hardware aspects of battery management systems (BMS for electric vehicle and stationary applications. The purpose is giving an overview on existing concepts in state-of-the-art systems and enabling the reader to estimate what has to be considered when designing a BMS for a given application. After a short analysis of general requirements, several possible topologies for battery packs and their consequences for the BMS’ complexity are examined. Four battery packs that were taken from commercially available electric vehicles are shown as examples. Later, implementation aspects regarding measurement of needed physical variables (voltage, current, temperature, etc. are discussed, as well as balancing issues and strategies. Finally, safety considerations and reliability aspects are investigated.

  11. EPICS: Allen-Bradley hardware reference manual

    International Nuclear Information System (INIS)

    Nawrocki, G.

    1993-01-01

    This manual covers the following hardware: Allen-Bradley 6008 -- SV VMEbus I/O scanner; Allen-Bradley universal I/O chassis 1771-A1B, -A2B, -A3B, and -A4B; Allen-Bradley power supply module 1771-P4S; Allen-Bradley 1771-ASB remote I/O adapter module; Allen-Bradley 1771-IFE analog input module; Allen-Bradley 1771-OFE analog output module; Allen-Bradley 1771-IG(D) TTL input module; Allen-Bradley 1771-OG(d) TTL output; Allen-Bradley 1771-IQ DC selectable input module; Allen-Bradley 1771-OW contact output module; Allen-Bradley 1771-IBD DC (10--30V) input module; Allen-Bradley 1771-OBD DC (10--60V) output module; Allen-Bradley 1771-IXE thermocouple/millivolt input module; and the Allen-Bradley 2705 RediPANEL push button module

  12. Theorem Proving in Intel Hardware Design

    Science.gov (United States)

    O'Leary, John

    2009-01-01

    For the past decade, a framework combining model checking (symbolic trajectory evaluation) and higher-order logic theorem proving has been in production use at Intel. Our tools and methodology have been used to formally verify execution cluster functionality (including floating-point operations) for a number of Intel products, including the Pentium(Registered TradeMark)4 and Core(TradeMark)i7 processors. Hardware verification in 2009 is much more challenging than it was in 1999 - today s CPU chip designs contain many processor cores and significant firmware content. This talk will attempt to distill the lessons learned over the past ten years, discuss how they apply to today s problems, outline some future directions.

  13. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...

  14. The double Chooz hardware trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Cucoanes, Andi; Beissel, Franz; Reinhold, Bernd; Roth, Stefan; Stahl, Achim; Wiebusch, Christopher [RWTH Aachen (Germany)

    2008-07-01

    The double Chooz neutrino experiment aims to improve the present knowledge on {theta}{sub 13} mixing angle using two similar detectors placed at {proportional_to}280 m and respectively 1 km from the Chooz power plant reactor cores. The detectors measure the disappearance of reactor antineutrinos. The hardware trigger has to be very efficient for antineutrinos as well as for various types of background events. The triggering condition is based on discriminated PMT sum signals and the multiplicity of groups of PMTs. The talk gives an outlook to the double Chooz experiment and explains the requirements of the trigger system. The resulting concept and its performance is shown as well as first results from a prototype system.

  15. The Effect of Superstar Software on Hardware Sales in System Markets

    OpenAIRE

    Binken, Jeroen; Stremersch, Stefan

    2008-01-01

    textabstractSystems are composed of complementary products (e.g., video game systems are composed of the video game console and video games). Prior literature on indirect network effects argues that, in system markets, sales of the primary product (often referred to as "hardware") largely depend on the availability of complementary products (often referred to as "software"). Mathematical and empirical analyses have almost exclusively operationalized software availability as software quantity....

  16. Management options for recycling radioactive scrap metals

    Energy Technology Data Exchange (ETDEWEB)

    Dehmel, J.C.; MacKinney, J.; Bartlett, J.

    1997-02-01

    The feasibility and advantages of recycling radioactive scrap metals (RSM) have yet to be assessed, given the unique technical, regulatory, safety, and cost-benefit issues that have already been raised by a concerned recycling industry. As is known, this industry has been repeatedly involved with the accidental recycling of radioactive sources and, in some cases, with costly consequences. If recycling were deemed to be a viable option, it might have to be implemented with regulatory monitoring and controls. Its implementation may have to consider various and complex issues and address the requirements and concerns of distinctly different industries. There are three basic options for the recycling of such scraps. They are: (1) recycling through the existing network of metal-scrap dealers and brokers, (2) recycling directly and only with specific steelmills, or (3) recycling through regional processing centers. Under the first option, scrap dealers and brokers would receive material from RSM generators and determine at which steelmills such scraps would be recycled. For the second option, RSM generators would deal directly with selected steelmills under specific agreements. For the third option, generators would ship scraps only to regional centers for processing and shipment to participating steelmills. This paper addresses the potential advantages of each option, identifies the types of arrangements that would need to be secured among all parties, and attempts to assess the receptivity of the recycling industry to each option.

  17. Polish Toxic Currency Options

    Directory of Open Access Journals (Sweden)

    Waldemar Gontarski

    2009-06-01

    Full Text Available Toxic currency options are defined on the basis of the opposition to the nature (essence of an option contract, which is justified in terms of norms founded on the general law clause of characteristics (nature of a relation (which represents an independent premise for imposing restrictions on the freedom of contracts. So-understood toxic currency options are unlawful. Indeed they contravene iuris cogentis regulations. These include for instance option contracts, which are concluded with a bank, if the bank has not informed about option risk before concluding the contract; or the barrier options, which focus only on the protection of bank’s interests. Therefore, such options may appear to be invalid. Therefore, performing contracts for toxic currency options may be qualified as a criminal mismanagement. For the sake of security, the manager should then take into consideration filing a claim for stating invalidity (which can be made in a court verdict. At the same time, if the supervisory board member in a commercial company, who can also be a subject to mismanagement offences, commits an omission involving lack of reaction (for example, if he/she fails to notify of the suspected offence committed by the management board members acting to the company’s detriment when the management board makes the company conclude option contracts which are charged with absolute invalidity the supervisory board member so acting may be considered to act to the company’s detriment. In the most recent Polish jurisprudence and judicature the standard of a “good host” is treated to be the last resort for determining whether the manager’s powers resulting from criminal regulations were performed. The manager of the exporter should not, as a rule, issue any options. Issuing options always means assuming an obligation. In the case of currency put options it is an absolute obligation to purchase a given amount in euro at exchange rate set in advance. On the

  18. 2005 resource options report

    International Nuclear Information System (INIS)

    Morris, T.

    2005-01-01

    This resource options report (ROR) fulfils regulatory requirements in British Columbia's two-year resource planning process. It identifies a wide range of resources and technologies that could be used to meet BC Hydro's future electricity demand. As such, it facilitates a transparent public review of resource options which include both supply-side and demand-side options. The resource options that will be used in the 2005 integrated electricity plan (IEP) were characterized. This ROR also documents where there is a general agreement or disagreement on the resource type characterization, based on the First Nations and Stakeholder engagement. BC Hydro used current information to provide realistic ranges on volume and cost to characterize environmental and social attributes. The BC Hydro system was modelled to assess the benefit and cost of various resource options. The information resulting from this ROR and IEP will help in making decisions on how to structure competitive acquisition calls and to determine the level of transmission services needed to advance certain BC Hydro projects. The IEP forecasts the nature and quantity of domestic resources required over the next 20 years. A strategic direction on how those needs will be met has been created to guide the management of BC Hydro's energy resources. Supply-side options include near-commercial technologies such as energy storage, ocean waves, tidal, fuel cells and integrated coal gasification combined cycle technology. Supply-side options also include natural gas, coal, biomass, geothermal, wind, and hydro. 120 refs., 39 tabs., 21 figs., 6 appendices

  19. Expensing options solves nothing.

    Science.gov (United States)

    Sahlman, William A

    2002-12-01

    The use of stock options for executive compensation has become a lightning rod for public anger, and it's easy to see why. Many top executives grew hugely rich on the back of the gains they made on their options, profits they've been able to keep even as the value they were supposed to create disappeared. The supposed scam works like this: Current accounting regulations let companies ignore the cost of option grants on their income statements, so they can award valuable option packages without affecting reported earnings. Not charging the cost of the grants supposedly leads to overstated earnings, which purportedly translate into unrealistically high share prices, permitting top executives to realize big gains when they exercise their options. If an accounting anomaly is the problem, then the solution seems obvious: Write off executive share options against the current year's revenues. The trouble is, Sahlman writes, expensing option grants won't give us a more accurate view of earnings, won't add any information not already included in the financial statements, and won't even lead to equal treatment of different forms of executive pay. Far worse, expensing evades the real issue, which is whether compensation (options and other-wise) does what it's supposed to do--namely, help a company recruit, retain, and provide the right people with appropriate performance incentives. Any performance-based compensation system has the potential to encourage cheating. Only ethical management, sensible governance, adequate internal control systems, and comprehensive disclosure will save the investor from disaster. If, Sahlman warns, we pass laws that require the expensing of options, thinking that's fixed the fundamental flaws in corporate America's accounting, we will have missed a golden opportunity to focus on the much more extensive defects in the present system.

  20. Early Option Exercise

    DEFF Research Database (Denmark)

    Heje Pedersen, Lasse; Jensen, Mads Vestergaard

    A classic result by Merton (1973) is that, except just before expiration or dividend payments, one should never exercise a call option and never convert a convertible bond. We show theoretically that this result is overturned when investors face frictions. Early option exercise can be optimal when...... it reduces short-sale costs, transaction costs, or funding costs. We provide consistent empirical evidence, documenting billions of dollars of early exercise for options and convertible bonds using unique data on actual exercise decisions and frictions. Our model can explain as much as 98% of early exercises...

  1. Early Option Exercise

    DEFF Research Database (Denmark)

    Jensen, Mads Vestergaard; Heje Pedersen, Lasse

    2016-01-01

    A classic result by Merton (1973) is that, except just before expiration or dividend payments, one should never exercise a call option and never convert a convertible bond. We show theoretically that this result is overturned when investors face frictions. Early option exercise can be optimal when...... it reduces short-sale costs, transaction costs, or funding costs. We provide consistent empirical evidence, documenting billions of dollars of early exercise for options and convertible bonds using unique data on actual exercise decisions and frictions. Our model can explain as much as 98% of early exercises...

  2. 15 MW HArdware-in-the-loop Grid Simulation Project

    Energy Technology Data Exchange (ETDEWEB)

    Rigas, Nikolaos [Clemson Univ., SC (United States); Fox, John Curtiss [Clemson Univ., SC (United States); Collins, Randy [Clemson Univ., SC (United States); Tuten, James [Clemson Univ., SC (United States); Salem, Thomas [Clemson Univ., SC (United States); McKinney, Mark [Clemson Univ., SC (United States); Hadidi, Ramtin [Clemson Univ., SC (United States); Gislason, Benjamin [Clemson Univ., SC (United States); Boessneck, Eric [Clemson Univ., SC (United States); Leonard, Jesse [Clemson Univ., SC (United States)

    2014-10-31

    The 15MW Hardware-in-the-loop (HIL) Grid Simulator project was to (1) design, (2) construct and (3) commission a state-of-the-art grid integration testing facility for testing of multi-megawatt devices through a ‘shared facility’ model open to all innovators to promote the rapid introduction of new technology in the energy market to lower the cost of energy delivered. The 15 MW HIL Grid Simulator project now serves as the cornerstone of the Duke Energy Electric Grid Research, Innovation and Development (eGRID) Center. This project leveraged the 24 kV utility interconnection and electrical infrastructure of the US DOE EERE funded WTDTF project at the Clemson University Restoration Institute in North Charleston, SC. Additionally, the project has spurred interest from other technology sectors, including large PV inverter and energy storage testing and several leading edge research proposals dealing with smart grid technologies, grid modernization and grid cyber security. The key components of the project are the power amplifier units capable of providing up to 20MW of defined power to the research grid. The project has also developed a one of a kind solution to performing fault ride-through testing by combining a reactive divider network and a large power converter into a hybrid method. This unique hybrid method of performing fault ride-through analysis will allow for the research team at the eGRID Center to investigate the complex differences between the alternative methods of performing fault ride-through evaluations and will ultimately further the science behind this testing. With the final goal of being able to perform HIL experiments and demonstration projects, the eGRID team undertook a significant challenge with respect to developing a control system that is capable of communicating with several different pieces of equipment with different communication protocols in real-time. The eGRID team developed a custom fiber optical network that is based upon FPGA

  3. Network SCADA System

    International Nuclear Information System (INIS)

    Milivojevic, Dragan R.; Tasic, Visa; Karabasevic, Dejan

    2003-01-01

    Copper Institute, Industrial Informatics department, is developing and applying network real time process monitoring and control systems. Some of these systems are already in use. The paper presents some hardware and software general remarks and performances, with special regard to communication sub-systems and network possibilities. (Author)

  4. [Abscess at the implant site following apical parodontitis. Hardware-related complications of deep brain stimulation].

    Science.gov (United States)

    Sixel-Döring, F; Trenkwalder, C; Kappus, C; Hellwig, D

    2006-08-01

    Deep brain stimulation of the subthalamic nucleus is an important treatment option for advanced stages of idiopathic Parkinson's disease, leading to significant improvement of motor symptoms in suited patients. Hardware-related complications such as technical malfunction, skin erosion, and infections however cause patient discomfort and additional expense. The patient presented here suffered a putrid infection of the impulse generator site following only local dental treatment of apical parodontitis. Therefore, prophylactic systemic antibiotic treatment is recommended for patients with implanted deep brain stimulation devices in case of operations, dental procedures, or infectious disease.

  5. Thermometers: Understand the Options

    Science.gov (United States)

    ... the options Thermometers come in a variety of styles. Understand the different types of thermometers and how ... MA. Fever in infants and children: Pathophysiology and management. http://www.uptodate.com/home. Accessed July 23, ...

  6. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  7. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  8. Options for human intrusion

    International Nuclear Information System (INIS)

    Bauser, M.; Williams, R.

    1993-01-01

    This paper addresses options for dealing with human intrusion in terms of performance requirements and repository siting and design requirements. Options are presented, along with the advantages and disadvantages of certain approaches. At the conclusion, a conceptual approach is offered emphasizing both the minimization of subjective judgements concerning future human activity, and specification of repository requirements to minimize the likelihood of human intrusion and any resulting, harmful effects should intrusion occur

  9. Hardware descriptions of the I and C systems for NPP

    International Nuclear Information System (INIS)

    Lee, Cheol Kwon; Oh, In Suk; Park, Joo Hyun; Kim, Dong Hoon; Han, Jae Bok; Shin, Jae Whal; Kim, Young Bak

    2003-09-01

    The hardware specifications for I and C Systems of SNPP(Standard Nuclear Power Plant) are reviewed in order to acquire the hardware requirement and specification of KNICS (Korea Nuclear Instrumentation and Control System). In the study, we investigated hardware requirements, hardware configuration, hardware specifications, man-machine hardware requirements, interface requirements with the other system, and data communication requirements that are applicable to SNP. We reviewed those things of control systems, protection systems, monitoring systems, information systems, and process instrumentation systems. Through the study, we described the requirements and specifications of digital systems focusing on a microprocessor and a communication interface, and repeated it for analog systems focusing on the manufacturing companies. It is expected that the experience acquired from this research will provide vital input for the development of the KNICS

  10. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    International Nuclear Information System (INIS)

    Williamson, D.A.

    1991-01-01

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas ampersand Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States' utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste

  11. Nevada Transportation Options Study

    International Nuclear Information System (INIS)

    P. GEHNER; E.M. WEAVER; L. FOSSUM

    2006-01-01

    This study performs a cost and schedule analysis of three Nevada Transportation options that support waste receipt at the repository. Based on the U.S. Department of Energy preference for rail transportation in Nevada (given in the Final Environmental Impact Statement), it has been assumed that a branch rail line would be constructed to support waste receipt at the repository. However, due to potential funding constraints, it is uncertain when rail will be available. The three Nevada Transportation options have been developed to meet a varying degree of requirements for transportation and to provide cost variations used in meeting the funding constraints given in the Technical Direction Letter guidelines for this study. The options include combinations of legal-weight truck, heavy-haul truck, and rail. Option 1 uses a branch rail line that would support initial waste receipt at the repository in 2010. Rail transportation would be the primary mode, supplemented by legal weight trucks. This option provides the highest level of confidence in cost and schedule, lowest public visibility, greatest public acceptability, lowest public dose, and is the recommended option for support of waste receipt. The completion of rail by 2010 will require spending approximately $800 million prior to 2010. Option 2 uses a phased rail approach to address a constrained funding scenario. To meet funding constraints, Option 2 uses a phased approach to delay high cost activities (final design and construction) until after initial waste receipt in 2010. By doing this, approximately 95 percent of the cost associated with completion of a branch rail line is deferred until after 2010. To support waste receipt until a branch rail line is constructed in Nevada, additional legal-weight truck shipments and heavy-haul truck shipments (on a limited basis for naval spent nuclear fuel) would be used to meet the same initial waste receipt rates as in Option 1. Use of heavy-haul shipments in the absence

  12. Options Study - Phase II

    Energy Technology Data Exchange (ETDEWEB)

    R. Wigeland; T. Taiwo; M. Todosow; W. Halsey; J. Gehin

    2010-09-01

    The Options Study has been conducted for the purpose of evaluating the potential of alternative integrated nuclear fuel cycle options to favorably address the issues associated with a continuing or expanding use of nuclear power in the United States. The study produced information that can be used to inform decisions identifying potential directions for research and development on such fuel cycle options. An integrated nuclear fuel cycle option is defined in this study as including all aspects of the entire nuclear fuel cycle, from obtaining natural resources for fuel to the ultimate disposal of used nuclear fuel (UNF) or radioactive wastes. Issues such as nuclear waste management, especially the increasing inventory of used nuclear fuel, the current uncertainty about used fuel disposal, and the risk of nuclear weapons proliferation have contributed to the reluctance to expand the use of nuclear power, even though it is recognized that nuclear power is a safe and reliable method of producing electricity. In this Options Study, current, evolutionary, and revolutionary nuclear energy options were all considered, including the use of uranium and thorium, and both once-through and recycle approaches. Available information has been collected and reviewed in order to evaluate the ability of an option to clearly address the challenges associated with the current implementation and potential expansion of commercial nuclear power in the United States. This Options Study is a comprehensive consideration and review of fuel cycle and technology options, including those for disposal, and is not constrained by any limitations that may be imposed by economics, technical maturity, past policy, or speculated future conditions. This Phase II report is intended to be used in conjunction with the Phase I report, and much information in that report is not repeated here, although some information has been updated to reflect recent developments. The focus in this Options Study was to

  13. Why Open Source Hardware matters and why you should care

    OpenAIRE

    Gürkaynak, Frank K.

    2017-01-01

    Open source hardware is currently where open source software was about 30 years ago. The idea is well received by enthusiasts, there is interest and the open source hardware has gained visible momentum recently, with several well-known universities including UC Berkeley, Cambridge and ETH Zürich actively working on large projects involving open source hardware, attracting the attention of companies big and small. But it is still not quite there yet. In this talk, based on my experience on the...

  14. Support for NUMA hardware in HelenOS

    OpenAIRE

    Horký, Vojtěch

    2011-01-01

    The goal of this master thesis is to extend HelenOS operating system with the support for ccNUMA hardware. The text of the thesis contains a brief introduction to ccNUMA hardware, an overview of NUMA features and relevant features of HelenOS (memory management, scheduling, etc.). The thesis analyses various design decisions of the implementation of NUMA support -- introducing the hardware topology into the kernel data structures, propagating this information to user space, thread affinity to ...

  15. Optical Neural Network Classifier Architectures

    National Research Council Canada - National Science Library

    Getbehead, Mark

    1998-01-01

    We present an adaptive opto-electronic neural network hardware architecture capable of exploiting parallel optics to realize real-time processing and classification of high-dimensional data for Air...

  16. Option for Flexibility; Option fuer Flexibilitaet

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2013-05-15

    The establishment of reserves with which one can take off again after a lean period is already known from the vegetation. With increasing wind power and solar power energy storages are becoming increasingly important in energy systems in the long term, either as a power to gas, as a heat storage or as a battery. Networked systems can be used to control power.

  17. An Open Hardware seismic data recorder - a solid basis for citizen science

    Science.gov (United States)

    Mertl, Stefan

    2015-04-01

    "Ruwai" is a 24-Bit Open Hardware seismic data recorder. It is built up of four stackable printed circuit boards fitting the Arduino Mega 2560 microcontroller prototyping platform. An interface to the BeagleBone Black single-board computer enables extensive data storage, -processing and networking capabilities. The four printed circuit boards provide a uBlox Lea-6T GPS module and real-time clock (GPS Timing shield), an Texas Instruments ADS1274 24-Bit analog to digital converter (ADC main shield), an analog input section with a Texas Instruments PGA281 programmable gain amplifier and an analog anti-aliasing filter (ADC analog interface pga) and the power conditioning based on 9-36V DC input (power supply shield). The Arduino Mega 2560 is used for controlling the hardware components, timestamping sampled data using the GPS timing information and transmitting the data to the BeagleBone Black single-board computer. The BeagleBone Black provides local data storage, wireless mesh networking using the optimized link state routing daemon and differential GNSS positioning using the RTKLIB software. The complete hardware and software is published under free software - or open hardware licenses and only free software (e.g. KiCad) was used for the development to facilitate the reusability of the design and increases the sustainability of the project. "Ruwai" was developed within the framework of the "Community Environmental Observation Network (CEON)" (http://www.mertl-research.at/ceon/) which was supported by the Internet Foundation Austria (IPA) within the NetIdee 2013 call.

  18. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  19. Environmental Friendly Coatings and Corrosion Prevention For Flight Hardware Project

    Science.gov (United States)

    Calle, Luz

    2014-01-01

    Identify, test and develop qualification criteria for environmentally friendly corrosion protective coatings and corrosion preventative compounds (CPC's) for flight hardware an ground support equipment.

  20. A Systematic Hardware Sharing Method for Unified Architecture Design of H.264 Transforms

    Directory of Open Access Journals (Sweden)

    Po-Hung Chen

    2015-01-01

    Full Text Available Multitransform techniques have been widely used in modern video coding and have better compression efficiency than the single transform technique that is used conventionally. However, every transform needs a corresponding hardware implementation, which results in a high hardware cost for multiple transforms. A novel method that includes a five-step operation sharing synthesis and architecture-unification techniques is proposed to systematically share the hardware and reduce the cost of multitransform coding. In order to demonstrate the effectiveness of the method, a unified architecture is designed using the method for all of the six transforms involved in the H.264 video codec: 2D 4 × 4 forward and inverse integer transforms, 2D 4 × 4 and 2 × 2 Hadamard transforms, and 1D 8 × 8 forward and inverse integer transforms. Firstly, the six H.264 transform architectures are designed at a low cost using the proposed five-step operation sharing synthesis technique. Secondly, the proposed architecture-unification technique further unifies these six transform architectures into a low cost hardware-unified architecture. The unified architecture requires only 28 adders, 16 subtractors, 40 shifters, and a proposed mux-based routing network, and the gate count is only 16308. The unified architecture processes 8 pixels/clock-cycle, up to 275 MHz, which is equal to 707 Full-HD 1080 p frames/second.

  1. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  2. Magnetic qubits as hardware for quantum computers

    International Nuclear Information System (INIS)

    Tejada, J.; Chudnovsky, E.; Barco, E. del

    2000-01-01

    We propose two potential realisations for quantum bits based on nanometre scale magnetic particles of large spin S and high anisotropy molecular clusters. In case (1) the bit-value basis states vertical bar-0> and vertical bar-1> are the ground and first excited spin states S z = S and S-1, separated by an energy gap given by the ferromagnetic resonance (FMR) frequency. In case (2), when there is significant tunnelling through the anisotropy barrier, the qubit states correspond to the symmetric, vertical bar-0>, and antisymmetric, vertical bar-1>, combinations of the two-fold degenerate ground state S z = ± S. In each case the temperature of operation must be low compared to the energy gap, Δ, between the states vertical bar-0> and vertical bar-1>. The gap Δ in case (2) can be controlled with an external magnetic field perpendicular to the easy axis of the molecular cluster. The states of different molecular clusters and magnetic particles may be entangled by connecting them by superconducting lines with Josephson switches, leading to the potential for quantum computing hardware. (author)

  3. Magnetic qubits as hardware for quantum computers

    Energy Technology Data Exchange (ETDEWEB)

    Tejada, J.; Chudnovsky, E.; Barco, E. del [and others

    2000-07-01

    We propose two potential realisations for quantum bits based on nanometre scale magnetic particles of large spin S and high anisotropy molecular clusters. In case (1) the bit-value basis states vertical bar-0> and vertical bar-1> are the ground and first excited spin states S{sub z} = S and S-1, separated by an energy gap given by the ferromagnetic resonance (FMR) frequency. In case (2), when there is significant tunnelling through the anisotropy barrier, the qubit states correspond to the symmetric, vertical bar-0>, and antisymmetric, vertical bar-1>, combinations of the two-fold degenerate ground state S{sub z} = {+-} S. In each case the temperature of operation must be low compared to the energy gap, {delta}, between the states vertical bar-0> and vertical bar-1>. The gap {delta} in case (2) can be controlled with an external magnetic field perpendicular to the easy axis of the molecular cluster. The states of different molecular clusters and magnetic particles may be entangled by connecting them by superconducting lines with Josephson switches, leading to the potential for quantum computing hardware. (author)

  4. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  5. Hardware upgrade for A2 data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Ostrick, Michael; Gradl, Wolfgang; Otte, Peter-Bernd; Neiser, Andreas; Steffen, Oliver; Wolfes, Martin; Koerner, Tito [Institut fuer Kernphysik, Mainz (Germany); Collaboration: A2-Collaboration

    2014-07-01

    The A2 Collaboration uses an energy tagged photon beam which is produced via bremsstrahlung off the MAMI electron beam. The detector system consists of Crystal Ball and TAPS and covers almost the whole solid angle. A frozen-spin polarized target allows to perform high precision measurements of polarization observables in meson photo-production. During the last summer, a major upgrade of the data acquisition system was performed, both on the hardware and the software side. The goal of this upgrade was increased reliability of the system and an improvement in the data rate to disk. By doubling the number of readout CPUs and employing special VME crates with a split backplane, the number of bus accesses per readout cycle and crate was cut by a factor of two, giving almost a factor of two gain in the readout rate. In the course of the upgrade, we also switched most of the detector control system to using the distributed control system EPICS. For the upgraded control system, some new tools were developed to make full use of the capabilities of this decentralised slow control and monitoring system. The poster presents some of the major contributions to this project.

  6. UniBoard: generic hardware for radio astronomy signal processing

    Science.gov (United States)

    Hargreaves, J. E.

    2012-09-01

    UniBoard is a generic high-performance computing platform for radio astronomy, developed as a Joint Research Activity in the RadioNet FP7 Programme. The hardware comprises eight Altera Stratix IV Field Programmable Gate Arrays (FPGAs) interconnected by a high speed transceiver mesh. Each FPGA is connected to two DDR3 memory modules and three external 10Gbps ports. In addition, a total of 128 low voltage differential input lines permit connection to external ADC cards. The DSP capability of the board exceeds 644E9 complex multiply-accumulate operations per second. The first production run of eight boards was distributed to partners in The Netherlands, France, Italy, UK, China and Korea in May 2011, with a further production runs completed in December 2011 and early 2012. The function of the board is determined by the firmware loaded into its FPGAs. Current applications include beamformers, correlators, digital receivers, RFI mitigation for pulsar astronomy, and pulsar gating and search machines The new UniBoard based correlator for the European VLBI network (EVN) uses an FX architecture with half the resources of the board devoted to station based processing: delay and phase correction and channelization, and half to the correlation function. A single UniBoard can process a 64MHz band from 32 stations, 2 polarizations, sampled at 8 bit. Adding more UniBoards can expand the total bandwidth of the correlator. The design is able to process both prerecorded and real time (eVLBI) data.

  7. Treatment Options for Wilms Tumor

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... come back) after it has been treated. Treatment Option Overview Key Points There are different types of ...

  8. Treatment Options for Myelodysplastic Syndromes

    Science.gov (United States)

    ... special light. Certain factors affect prognosis and treatment options. The prognosis (chance of recovery) and treatment options ... age and general health of the patient. Treatment Option Overview Key Points There are different types of ...

  9. Treatment Option Overview (Prostate Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  10. Treatment Option Overview (Myelodysplastic Syndromes)

    Science.gov (United States)

    ... special light. Certain factors affect prognosis and treatment options. The prognosis (chance of recovery) and treatment options ... age and general health of the patient. Treatment Option Overview Key Points There are different types of ...

  11. Treatment Option Overview (Esophageal Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  12. Treatment Option Overview (Childhood Rhabdomyosarcoma)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  13. Treatment Option Overview (Penile Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  14. Treatment Option Overview (Vulvar Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  15. Treatment Option Overview (Pancreatic Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  16. Treatment Option Overview (Adrenocortical Carcinoma)

    Science.gov (United States)

    ... affect the prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  17. Treatment Options for Childhood Rhabdomyosarcoma

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  18. Treatment Options for Kaposi Sarcoma

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  19. Treatment Options for Childhood Craniopharyngioma

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... the brain where it was first found. Treatment Option Overview Key Points There are different types of ...

  20. Testing FlexRay ECUs with a hardware-in-the-loop simulator; Test von FlexRay-Steuergeraeten am Hardware-in-the-Loop Simulator

    Energy Technology Data Exchange (ETDEWEB)

    Stroop, J.; Koehl, S. [dSPACE GmbH, Paderborn (Germany); Peller, M.; Riedesser, P. [BMW AG, Muenchen (Germany)

    2005-07-01

    To master the data communication of complex and safety relevant systems within future vehicles, the BMW Group prepares the application of FlexRay. The accompanying development process plays an important role for the quality, stability and reliability of those systems. Hardware-in-the-loop simulation and test stands are indispensable constituents and they are an integral part of the validation process. The following contribution describes the technology that is used within the BMW Group in more detail, especially in terms of communication networks with FlexRay. (orig.)

  1. Reconfigurable network systems and software-defined networking

    OpenAIRE

    Zilberman, N.; Watts, P. M.; Rotsos, C.; Moore, A. W.

    2015-01-01

    Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of software-defined n...

  2. FTR-option formulation and pricing

    International Nuclear Information System (INIS)

    Parmeshwaran, Vijay; Muthuraman, Kumar

    2009-01-01

    Recent changes in electricity markets have advocated the use of Local Marginal Prices (LMP) for congestion management and pricing. From the perspective of market participants, the LMPs pose a risk since they are not known before a transaction on the grid is made. Financial transmission rights (FTR) are instruments that help market participants hedge this risk and are issuable in two flavors - obligations and options. While pricing obligations are much easier, pricing FTR options pose a significant challenge. In this paper we develop a computational method for pricing FTR options. We also discuss the problem of designing financial instrument sets that assure revenue adequacy for the issuer. We point out the difficulty in assuring revenue adequacy when FTR options are present and propose a scheme for overcoming the difficulty. The proposed pricing method can be used to compute prices of options and obligations in the primary market or as a reliable pricing tool to compute option prices in the secondary market. Finally using a test network we present and discuss numerical results. (author)

  3. Using networking and communications software in business

    CERN Document Server

    McBride, PK

    2014-01-01

    Using Networking and Communications Software in Business covers the importance of networks in a business firm, the benefits of computer communications within a firm, and the cost-benefit in putting up networks in businesses. The book is divided into six parts. Part I looks into the nature and varieties of networks, networking standards, and network software. Part II discusses the planning of a networked system, which includes analyzing the requirements for the network system, the hardware for the network, and network management. The installation of the network system and the network managemen

  4. Is a 4-bit synaptic weight resolution enough? - constraints on enabling spike-timing dependent plasticity in neuromorphic hardware.

    Science.gov (United States)

    Pfeil, Thomas; Potjans, Tobias C; Schrader, Sven; Potjans, Wiebke; Schemmel, Johannes; Diesmann, Markus; Meier, Karlheinz

    2012-01-01

    Large-scale neuromorphic hardware systems typically bear the trade-off between detail level and required chip resources. Especially when implementing spike-timing dependent plasticity, reduction in resources leads to limitations as compared to floating point precision. By design, a natural modification that saves resources would be reducing synaptic weight resolution. In this study, we give an estimate for the impact of synaptic weight discretization on different levels, ranging from random walks of individual weights to computer simulations of spiking neural networks. The FACETS wafer-scale hardware system offers a 4-bit resolution of synaptic weights, which is shown to be sufficient within the scope of our network benchmark. Our findings indicate that increasing the resolution may not even be useful in light of further restrictions of customized mixed-signal synapses. In addition, variations due to production imperfections are investigated and shown to be uncritical in the context of the presented study. Our results represent a general framework for setting up and configuring hardware-constrained synapses. We suggest how weight discretization could be considered for other backends dedicated to large-scale simulations. Thus, our proposition of a good hardware verification practice may rise synergy effects between hardware developers and neuroscientists.

  5. Real-Time Hardware-in-the-Loop Laboratory Testing for Multisensor Sense and Avoid Systems

    Directory of Open Access Journals (Sweden)

    Giancarmine Fasano

    2013-01-01

    Full Text Available This paper focuses on a hardware-in-the-loop facility aimed at real-time testing of architectures and algorithms of multisensor sense and avoid systems. It was developed within a research project aimed at flight demonstration of autonomous non-cooperative collision avoidance for Unmanned Aircraft Systems. In this framework, an optionally piloted Very Light Aircraft was used as experimental platform. The flight system is based on multiple-sensor data integration and it includes a Ka-band radar, four electro-optical sensors, and two dedicated processing units. The laboratory test system was developed with the primary aim of prototype validation before multi-sensor tracking and collision avoidance flight tests. System concept, hardware/software components, and operating modes are described in the paper. The facility has been built with a modular approach including both flight hardware and simulated systems and can work on the basis of experimentally tested or synthetically generated scenarios. Indeed, hybrid operating modes are also foreseen which enable performance assessment also in the case of alternative sensing architectures and flight scenarios that are hardly reproducible during flight tests. Real-time multisensor tracking results based on flight data are reported, which demonstrate reliability of the laboratory simulation while also showing the effectiveness of radar/electro-optical fusion in a non-cooperative collision avoidance architecture.

  6. Experience with procuring, deploying and maintaining hardware at remote co-location centre

    International Nuclear Information System (INIS)

    Bärring, O; Bonfillou, E; Clement, B; Santos, M Coelho Dos; Dore, V; Gentit, A; Grossir, A; Salter, W; Valsan, L; Xafi, A

    2014-01-01

    In May 2012 CERN signed a contract with the Wigner Data Centre in Budapest for an extension to CERN's central computing facility beyond its current boundaries set by electrical power and cooling available for computing. The centre is operated as a remote co-location site providing rack-space, electrical power and cooling for server, storage and networking equipment acquired by CERN. The contract includes a 'remote-hands' services for physical handling of hardware (rack mounting, cabling, pushing power buttons, ...) and maintenance repairs (swapping disks, memory modules, ...). However, only CERN personnel have network and console access to the equipment for system administration. This report gives an insight to adaptations of hardware architecture, procurement and delivery procedures undertaken enabling remote physical handling of the hardware. We will also describe tools and procedures developed for automating the registration, burn-in testing, acceptance and maintenance of the equipment as well as an independent but important change to the IT assets management (ITAM) developed in parallel as part of the CERN IT Agile Infrastructure project. Finally, we will report on experience from the first large delivery of 400 servers and 80 SAS JBOD expansion units (24 drive bays) to Wigner in March 2013. Changes were made to the abstract file on 13/06/2014 to correct errors, the pdf file was unchanged.

  7. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  8. Bayesian Estimation and Inference using Stochastic Hardware

    Directory of Open Access Journals (Sweden)

    Chetan Singh Thakur

    2016-03-01

    Full Text Available In this paper, we present the implementation of two types of Bayesian inference problems to demonstrate the potential of building probabilistic algorithms in hardware using single set of building blocks with the ability to perform these computations in real time. The first implementation, referred to as the BEAST (Bayesian Estimation and Stochastic Tracker, demonstrates a simple problem where an observer uses an underlying Hidden Markov Model (HMM to track a target in one dimension. In this implementation, sensors make noisy observations of the target position at discrete time steps. The tracker learns the transition model for target movement, and the observation model for the noisy sensors, and uses these to estimate the target position by solving the Bayesian recursive equation online. We show the tracking performance of the system and demonstrate how it can learn the observation model, the transition model, and the external distractor (noise probability interfering with the observations. In the second implementation, referred to as the Bayesian INference in DAG (BIND, we show how inference can be performed in a Directed Acyclic Graph (DAG using stochastic circuits. We show how these building blocks can be easily implemented using simple digital logic gates. An advantage of the stochastic electronic implementation is that it is robust to certain types of noise, which may become an issue in integrated circuit (IC technology with feature sizes in the order of tens of nanometers due to their low noise margin, the effect of high-energy cosmic rays and the low supply voltage. In our framework, the flipping of random individual bits would not affect the system performance because information is encoded in a bit stream.

  9. Available hardware for automated entry control

    International Nuclear Information System (INIS)

    Holmes, J.P.

    1990-01-01

    Automated entry control has become an increasingly important issue at facilities where budget constraints are limiting options for manned entry control points. Ongoing work at Sandia National Laboratories is attempting to establish a data base for use by facility security managers working the problem of how to maintain security on a limited budget. Sandia National Laboratories conducted a performance test of the following biometric verifiers: (1) voice verifier by Alpha Microsystems of Santa Ana, California; (2) signature dynamics verifier by Autosig Systems of Irving, Texas; (3) voice verifier by Ecco Industries of Danvers, Massachusetts (now International Electronics); (4) retinal pattern verifier by EyeDentify of Portland, Oregon; (5) fingerprint verifier by Identix of Sunnyvale, California; and (6) hand geometry verifier by Recognition Systems of San Jose, California

  10. 20 CFR 416.2035 - Optional supplementation: Additional State options.

    Science.gov (United States)

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Optional supplementation: Additional State options. 416.2035 Section 416.2035 Employees' Benefits SOCIAL SECURITY ADMINISTRATION SUPPLEMENTAL... § 416.2035 Optional supplementation: Additional State options. (a) Residency requirement. A State or...

  11. Novel preventive treatment options

    DEFF Research Database (Denmark)

    Longbottom, C; Ekstrand, K; Zero, D

    2009-01-01

    A number of novel preventive treatment options which, as with traditional methods, can be differentiated into 3 categories of prevention (primary, secondary and tertiary), have been and are being currently investigated. Those reviewed are either commercially available or appear relatively close...... of these techniques show considerable promise and dentists should be aware of these developments and follow their progress, the evidence for each of these novel preventive treatment options is currently insufficient to make widespread recommendations. Changes in dental practice should be explored to see how oral...

  12. Tank Space Options Report

    International Nuclear Information System (INIS)

    BOYLES, V.C.

    2001-01-01

    A risk-based priority for the retrieval of Hanford Site waste from the 149 single-shell tanks (SSTs) has been adopted as a result of changes to the Hanford Federal Facility Agreement and Consent Order (HFFACO) (Ecology et al. 1997) negotiated in 2000. Retrieval of the first three tanks in the retrieval sequence fills available capacity in the double-shell tanks (DSTs) by 2007. As a result, the HFFACO change established a milestone (M-45-12-TO1) requiring the determination of options that could increase waste storage capacity for single-shell tank waste retrieval. The information will be considered in future negotiations. This document fulfills the milestone requirement. This study presents options that were reviewed for the purpose of increasing waste storage capacity. Eight options are identified that have the potential for increasing capacity from 5 to 10 million gallons, thus allowing uninterrupted single-shell tank retrieval until the planned Waste Treatment Plant begins processing substantial volumes of waste from the double-shell tanks in 2009. The cost of implementing these options is estimated to range from less than $1 per gallon to more than $14 per gallon. Construction of new double-shell tanks is estimated to cost about $63 per gallon. Providing 5 to 10 million gallons of available double-shell tank space could enable early retrieval of 5 to 9 high-risk single-shell tanks beyond those identified for retrieval by 2007. These tanks are A-101, AX-101, AX-103, BY-102, C-107, S-105, S-106, S-108, and S-109 (Garfield et al. 2000). This represents a potential to retrieve approximately 14 million total curies, including 3,200 curies of long-lived mobile radionuclides. The results of the study reflect qualitative analyses conducted to identify promising options. The estimated costs are rough-order-of magnitude and, therefore, subject to change. Implementing some of the options would represent a departure from the current baseline and may adversely impact the

  13. Alternative energy options

    International Nuclear Information System (INIS)

    Bennett, K.F.

    1983-01-01

    It is accepted that coal will continue to play the major role in the supply of energy to the country for the remainder of the century. In this paper, however, emphasis has been directed to those options which could supplement coal in an economic and technically sound manner. The general conclusion is that certain forms of solar energy hold the most promise and it is in this direction that research, development and implementation programmes should be directed. Tidal energy, fusion energy, geothermal energy, hydrogen energy and fuel cells are also discussed as alternative energy options

  14. Thermal test options

    International Nuclear Information System (INIS)

    Koski, J.A.; Keltner, N.R.; Sobolik, K.B.

    1993-02-01

    Shipping containers for radioactive materials must be qualified to meet a thermal accident environment specified in regulations, such at Title 10, Code of Federal Regulations, Part 71. Aimed primarily at the shipping container design, this report discusses the thermal testing options available for meeting the regulatory requirements, and states the advantages and disadvantages of each approach. The principal options considered are testing with radiant heat, furnaces, and open pool fires. The report also identifies some of the facilities available and current contacts. Finally, the report makes some recommendations on the appropriate use of these different testing methods

  15. Lighting Options for Homes.

    Energy Technology Data Exchange (ETDEWEB)

    Baker, W.S.

    1991-04-01

    This report covers many aspects of various lighting options for homes. Types of light sources described include natural light, artificial light, incandescent lamps, fluorescent lamps, and high intensity discharge lamps. A light source selection guide gives the physical characteristics of these, design considerations, and common applications. Color, strategies for efficient lighting, and types of lighting are discussed. There is one section giving tips for various situations in specific rooms. Rooms and types of fixtures are shown on a matrix with watts saved by using the recommended type lighting for that room and room location. A major emphasis of this report is saving energy by utilizing the most suitable, recommended lighting option. (BN)

  16. Sharing open hardware through ROP, the robotic open platform

    NARCIS (Netherlands)

    Lunenburg, J.; Soetens, R.P.T.; Schoenmakers, F.; Metsemakers, P.M.G.; van de Molengraft, M.J.G.; Steinbuch, M.; Behnke, S.; Veloso, M.; Visser, A.; Xiong, R.

    2014-01-01

    The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

  17. Sharing open hardware through ROP, the Robotic Open Platform

    NARCIS (Netherlands)

    Lunenburg, J.J.M.; Soetens, R.P.T.; Schoenmakers, Ferry; Metsemakers, P.M.G.; Molengraft, van de M.J.G.; Steinbuch, M.

    2013-01-01

    The robot open source software community, in particular ROS, drastically boosted robotics research. However, a centralized place to exchange open hardware designs does not exist. Therefore we launched the Robotic Open Platform (ROP). A place to share and discuss open hardware designs. Among others

  18. The role of the visual hardware system in rugby performance ...

    African Journals Online (AJOL)

    This study explores the importance of the 'hardware' factors of the visual system in the game of rugby. A group of professional and club rugby players were tested and the results compared. The results were also compared with the established norms for elite athletes. The findings indicate no significant difference in hardware ...

  19. Flexible hardware design for RSA and Elliptic Curve Cryptosystems

    NARCIS (Netherlands)

    Batina, L.; Bruin - Muurling, G.; Örs, S.B.; Okamoto, T.

    2004-01-01

    This paper presents a scalable hardware implementation of both commonly used public key cryptosystems, RSA and Elliptic Curve Cryptosystem (ECC) on the same platform. The introduced hardware accelerator features a design which can be varied from very small (less than 20 Kgates) targeting wireless

  20. Hardware and software for image acquisition in nuclear medicine

    International Nuclear Information System (INIS)

    Fideles, E.L.; Vilar, G.; Silva, H.S.

    1992-01-01

    A system for image acquisition and processing in nuclear medicine is presented, including the hardware and software referring to acquisition. The hardware is consisted of an analog-digital conversion card, developed in wire-wape. Its function is digitate the analogic signs provided by gamma camera. The acquisitions are made in list or frame mode. (C.G.C.)

  1. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  2. Hardware design of a submerged buoy system based on electromagnetic inductive coupling

    Directory of Open Access Journals (Sweden)

    Song Dalei

    2016-01-01

    Full Text Available This paper mainly introduces the hardware design of a new type of ocean buoy for multi-scale marine dynamic process. The buoy system can collect a number of real-time marine environment data and then transmit all the data back to the landing site through wireless module. The authors mainly designed the hardware circuit of the buoy system, including data collection system, data communication system, data storage system. Due to the buoy system will complete the marine observation work continuously for at least a month, so we add the low power consumption function which can realize the intermittent work for the data collection system. This paper also introduces the electromagnetic induction coupling technology of underwater sensors, the sea surface communication network technology, etc. The system can also extends to the ecological regional anomaly monitoring and the early warning of disaster weather.

  3. Hardware Acceleration on Cloud Services: The use of Restricted Boltzmann Machines on Handwritten Digits Recognition

    Directory of Open Access Journals (Sweden)

    Eleni Bougioukou

    2018-02-01

    Full Text Available Cloud computing allows users and enterprises to process their data in high performance servers, thus reducing the need for advanced hardware at the client side. Although local processing is viable in many cases, collecting data from multiple clients and processing them in a server gives the best possible performance in terms of processing rate. In this work, the implementation of a high performance cloud computing engine for recognizing handwritten digits is presented. The engine exploits the benefits of cloud and uses a powerful hardware accelerator in order to classify the images received concurrently from multiple clients. The accelerator implements a number of neural networks, operating in parallel, resulting to a processing rate of more than 10 MImages/sec.

  4. Mixed waste management options

    International Nuclear Information System (INIS)

    Owens, C.B.; Kirner, N.P.

    1992-01-01

    Currently, limited storage and treatment capacity exists for commercial mixed waste streams. No commercial mixed waste disposal is available, and it has been estimated that if and when commercial mixed waste disposal becomes available, the costs will be high. If high disposal fees are imposed, generators may be willing to apply extraordinary treatment or regulatory approaches to properly dispose of their mixed waste. This paper explores the feasibility of several waste management scenarios and management options. Existing data on commercially generated mixed waste streams are used to identify the realm of mixed waste known to be generated. Each waste stream is evaluated from both a regulatory and technical perspective in order to convert the waste into a strictly low-level radioactive or a hazardous waste. Alternative regulatory approaches evaluated in this paper include a delisting petition) no migration petition) and a treatability variance. For each waste stream, potentially available treatment options are identified that could lead to these variances. Waste minimization methodology and storage for decay are also considered. Economic feasibility of each option is discussed broadly. Another option for mixed waste management that is being explored is the feasibility of Department of Energy (DOE) accepting commercial mixed waste for treatment, storage, and disposal. A study has been completed that analyzes DOE treatment capacity in comparison with commercial mixed waste streams. (author)

  5. Strategic growth options

    NARCIS (Netherlands)

    Kulatilaka, N.; Perotti, E.C.

    1998-01-01

    We provide a strategic rationale for growth options under uncertainty and imperfect corn-petition. In a market with strategic competition, investment confers a greater capability to take advantage of future growth opportunities. This strategic advantage leads to the capture of a greater share of the

  6. New Options, Old Concerns.

    Science.gov (United States)

    O'Neil, John

    1996-01-01

    Will greater school choice result in more responsive, higher quality schools and happier parents? Or will proliferating options further sort students and families by race, social class, and special interest? Increasingly, education is viewed as a private good. If parents become autonomous, self-interested consumers, erosion of common purposes and…

  7. Heterogeneity and option pricing

    NARCIS (Netherlands)

    Benninga, Simon; Mayshar, Joram

    2000-01-01

    An economy with agents having constant yet heterogeneous degrees of relative risk aversion prices assets as though there were a single decreasing relative risk aversion pricing representative agent. The pricing kernel has fat tails and option prices do not conform to the Black-Scholes formula.

  8. Option Pricing and Momentum

    NARCIS (Netherlands)

    Rodriguez, J.C.

    2007-01-01

    If managers are reluctant to fully adjust dividends to changes in earnings, stock returns and changes in the dividend yield will tend to be negatively correlated. When this is the case, stock returns will exhibit positive autocorrelation, or mo- mentum. This paper studies the pricing of options in

  9. Idaho's Energy Options

    Energy Technology Data Exchange (ETDEWEB)

    Robert M. Neilson

    2006-03-01

    This report, developed by the Idaho National Laboratory, is provided as an introduction to and an update of the status of technologies for the generation and use of energy. Its purpose is to provide information useful for identifying and evaluating Idaho’s energy options, and for developing and implementing Idaho’s energy direction and policies.

  10. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  11. Clarifying evacuation options through fire behavior and traffic modeling

    Science.gov (United States)

    Carol L. Rice; Ronny J. Coleman; Mike. Price

    2011-01-01

    Communities are becoming increasingly concerned with the variety of choices related to wildfire evacuation. We used ArcView with Network Analyst to evaluate the different options for evacuations during wildfire in a case study community. We tested overlaying fire growth patterns with the road network and population characteristics to determine recommendations for...

  12. Brain inspired hardware architectures - Can they be used for particle physics ?

    CERN Multimedia

    CERN. Geneva

    2016-01-01

    After their inception in the 1940s and several decades of moderate success, artificial neural networks have recently demonstrated impressive achievements in analysing big data volumes. Wide and deep network architectures can now be trained using high performance computing systems, graphics card clusters in particular. Despite their successes these state-of-the-art approaches suffer from very long training times and huge energy consumption, in particular during the training phase. The biological brain can perform similar and superior classification tasks in the space and time domains, but at the same time exhibits very low power consumption, rapid unsupervised learning capabilities and fault tolerance. In the talk the differences between classical neural networks and neural circuits in the brain will be presented. Recent hardware implementations of neuromorphic computing systems and their applications will be shown. Finally, some initial ideas to use accelerated neural architectures as trigger processors i...

  13. Hardware Implementation of a Bilateral Subtraction Filter

    Science.gov (United States)

    Huertas, Andres; Watson, Robert; Villalpando, Carlos; Goldberg, Steven

    2009-01-01

    A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for

  14. Inexpensive, Low Power, Open-Source Data Logging hardware development

    Science.gov (United States)

    Sandell, C. T.; Schulz, B.; Wickert, A. D.

    2017-12-01

    Over the past six years, we have developed a suite of open-source, low-cost, and lightweight data loggers for scientific research. These loggers employ the popular and easy-to-use Arduino programming environment, but consist of custom hardware optimized for field research. They may be connected to a broad and expanding range of off-the-shelf sensors, with software support built in directly to the "ALog" library. Three main models exist: The ALog (for Autonomous or Arduino Logger) is the extreme low-power model for years-long deployments with only primary AA or D batteries. The ALog shield is a stripped-down ALog that nests with a standard Arduino board for prototyping or education. The TLog (for Telemetering Logger) contains an embedded radio with 500 m range and a GPS for communications and precision timekeeping. This enables meshed networks of loggers that can send their data back to an internet-connected "home base" logger for near-real-time field data retrieval. All boards feature feature a high-precision clock, full size SD card slot for high-volume data storage, large screw terminals to connect sensors, interrupts, SPI and I2C communication capability, and 3.3V/5V power outputs. The ALog and TLog have fourteen 16-bit analog inputs with a precision voltage reference for precise analog measurements. Their components are rated -40 to +85 degrees C, and they have been tested in harsh field conditions. These low-cost and open-source data loggers have enabled our research group to collect field data across North and South America on a limited budget, support student projects, and build toward better future scientific data systems.

  15. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  16. Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

    DEFF Research Database (Denmark)

    Esposito, A.; Lomuscio, A.; Nunzio, L. Di

    2016-01-01

    In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors......, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. The proposed architecture provides excellent flexibility with respect to the different audio applications implemented, high quality audio, and an energy efficient solution....

  17. Acceleration of Meshfree Radial Point Interpolation Method on Graphics Hardware

    International Nuclear Information System (INIS)

    Nakata, Susumu

    2008-01-01

    This article describes a parallel computational technique to accelerate radial point interpolation method (RPIM)-based meshfree method using graphics hardware. RPIM is one of the meshfree partial differential equation solvers that do not require the mesh structure of the analysis targets. In this paper, a technique for accelerating RPIM using graphics hardware is presented. In the method, the computation process is divided into small processes suitable for processing on the parallel architecture of the graphics hardware in a single instruction multiple data manner.

  18. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  19. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...... the importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

  20. Management options of varicoceles

    Directory of Open Access Journals (Sweden)

    Peter Chan

    2011-01-01

    Full Text Available Varicocele is one of the most common causes of male infertility. Treatment options for varicoceles includes open varicocelectomy performed at various anatomical levels. Laparoscopic varicocelectomy has been established to be a safe and effective treatment for varicoceles. Robotic surgery has been introduced recently as an alternative surgical option for varicocelectomy. Microsurgical varicocelectomy has gained increasing popularity among experts in male reproductive medicine as the treatment of choice for varicocele because of its superior surgical outcomes. There is a growing volume of literature in the recent years on minimal invasive varicocele treatment with percutaneous retrograde and anterograde venous embolization/sclerotherapy. In this review, we will discuss the advantages and limitations associated with each treatment modality for varicoceles. Employment of these advanced techniques of varicocelectomy can provide a safe and effective approach aiming to eliminate varicocele, preserve testicular function and, in a substantial number of men, increase semen quality and the likelihood of pregnancy.

  1. Energy options?; Energie opties?

    Energy Technology Data Exchange (ETDEWEB)

    Van Sark, W. (ed.)

    2006-05-15

    March 2006 the so-called Options Document was published by the Energy research Centre of the Netherlands (ECN) and the Netherlands Environmental Assessment Agency (MNP). The document is an overview of technical options to reduce energy consumption and emission of greenhouse gases up to 2020. Next to a brief summary of the document a few reactions and comments on the contents of the document are given. [Dutch] Maart 2006 publiceerde het Energieonderzoek Centrum Nederland (ECN) en het Milieu- en Natuurplanbureau (MNP) het zogenaamde Optiedocument energie en emissies 2010-2020. Daarin wordt een overzicht gegeven van de technische mogelijkheden voor vermindering van het energieverbruik en de uitstoot van broeikasgassen en luchtverontreinigende stoffen tot 2020. Naast een korte samenvatting van het document worden enkele reacties gegeven op de inhoud.

  2. Evaluating technology service options.

    Science.gov (United States)

    Blumberg, D F

    1997-05-01

    Four service and support options are available to healthcare organizations for maintaining their growth arsenals of medical and information technology. These options include maintaining and servicing all equipment using a facility-based biomedical engineering and MIS service department; using a combination of facility-based service and subcontracted service; expanding facility-based biomedical and MIS service departments to provide service to other healthcare organizations to achieve economies of scale; and outsourcing all maintenance, repair, and technical support services. Independent service companies and original equipment manufacturers (OEMs) are offering healthcare organizations a wider array of service and support capabilities than ever before. However, some health systems have successfully developed their own independent service organizations to take care of their own--and other healthcare organizations'--service and support needs.

  3. Network on Target: Remotely Configured Adaptive Tactical Networks

    National Research Council Canada - National Science Library

    Bordetsky, Alex; Bourakov, Eugene

    2006-01-01

    .... The node mobility as well as ad hoc network topology reconfiguration becomes a powerful control option, which network operators or intelligent management agents could apply to provide for self...

  4. Optioner eller betingede aktier?

    DEFF Research Database (Denmark)

    Bechmann, Ken L.; Thorsell, Christopher

    2016-01-01

    Incitamentsaflønning – og herunder især aktieaflønning – fortsætter med at tiltrække sig stor opmærksomhed fra en lang række sider. Et spørgsmål, der ofte diskuteres, er selskabernes anvendelse af aktieaflønning, dvs. aflønning med optioner, betingede aktier o. lign. Diskussionerne har blandt andet...

  5. Shungnak Energy Configuration Options.

    Energy Technology Data Exchange (ETDEWEB)

    Rosewater, David Martin [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Eddy, John P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-10-01

    Power systems in rural Alaska villages face a unique combination of challenges that can increase the cost of energy and lowers energy supply reliability. In the case of the remote village of Shungnak, diesel and heating fuel is either shipped in by barge or flown in by aircraft. This report presents a technical analysis of several energy infrastructure upgrade and modification options to reduce the amount of fuel consumed by the community of Shungnak. Reducing fuel usage saves money and makes the village more resilient to disruptions in fuel supply. The analysis considers demand side options, such as energy efficiency, alongside the installation of wind and solar power generation options. Some novel approaches are also considered including battery energy storage and the use of electrical home heating stoves powered by renewable generation that would otherwise be spilled and wasted. This report concludes with specific recommendations for Shungnak based on economic factors, and fuel price sensitivity. General conclusions are also included to support future work analyzing similar energy challenges in remote arctic regions.

  6. The safeguards options study

    Energy Technology Data Exchange (ETDEWEB)

    Hakkila, E.A.; Mullen, M.F.; Olinger, C.T.; Stanbro, W.D. [Los Alamos National Lab., NM (United States); Olsen, A.P.; Roche, C.T.; Rudolph, R.R. [Argonne National Lab., IL (United States); Bieber, A.M.; Lemley, J. [Brookhaven National Lab., Upton, NY (United States); Filby, E. [Idaho National Engineering Lab., Idaho Falls, ID (United States)] [and others

    1995-04-01

    The Safeguards Options Study was initiated to aid the International Safeguards Division (ISD) of the DOE Office of Arms Control and Nonproliferation in developing its programs in enhanced international safeguards. The goal was to provide a technical basis for the ISD program in this area. The Safeguards Options Study has been a cooperative effort among ten organizations. These are Argonne National Laboratory, Brookhaven National Laboratory, Idaho National Engineering Laboratory, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Mound Laboratory, Oak Ridge National Laboratory, Pacific Northwest Laboratories, Sandia National Laboratories, and Special Technologies Laboratory. Much of the Motivation for the Safeguards Options Study is the recognition after the Iraq experience that there are deficiencies in the present approach to international safeguards. While under International Atomic Energy Agency (IAEA) safeguards at their declared facilities, Iraq was able to develop a significant weapons program without being noticed. This is because negotiated safeguards only applied at declared sites. Even so, their nuclear weapons program clearly conflicted with Iraq`s obligations under the Nuclear Nonproliferation Treaty (NPT) as a nonnuclear weapon state.

  7. The safeguards options study

    International Nuclear Information System (INIS)

    Hakkila, E.A.; Mullen, M.F.; Olinger, C.T.; Stanbro, W.D.; Olsen, A.P.; Roche, C.T.; Rudolph, R.R.; Bieber, A.M.; Lemley, J.; Filby, E.

    1995-04-01

    The Safeguards Options Study was initiated to aid the International Safeguards Division (ISD) of the DOE Office of Arms Control and Nonproliferation in developing its programs in enhanced international safeguards. The goal was to provide a technical basis for the ISD program in this area. The Safeguards Options Study has been a cooperative effort among ten organizations. These are Argonne National Laboratory, Brookhaven National Laboratory, Idaho National Engineering Laboratory, Lawrence Livermore National Laboratory, Los Alamos National Laboratory, Mound Laboratory, Oak Ridge National Laboratory, Pacific Northwest Laboratories, Sandia National Laboratories, and Special Technologies Laboratory. Much of the Motivation for the Safeguards Options Study is the recognition after the Iraq experience that there are deficiencies in the present approach to international safeguards. While under International Atomic Energy Agency (IAEA) safeguards at their declared facilities, Iraq was able to develop a significant weapons program without being noticed. This is because negotiated safeguards only applied at declared sites. Even so, their nuclear weapons program clearly conflicted with Iraq's obligations under the Nuclear Nonproliferation Treaty (NPT) as a nonnuclear weapon state

  8. Energy Harvesting-based Spectrum Access with Incremental Cooperation, Relay Selection and Hardware Noises

    Directory of Open Access Journals (Sweden)

    T. N. Nguyen

    2017-04-01

    Full Text Available In this paper, we propose an energy harvesting (EH-based spectrum access model in cognitive radio (CR network. In the proposed scheme, one of available secondary transmitters (STs helps a primary transmitter (PT forward primary signals to a primary receiver (PR. Via the cooperation, the selected ST finds opportunities to access licensed bands to transmit secondary signals to its intended secondary receiver (SR. Secondary users are assumed to be mobile, hence, optimization of energy consumption for these users is interested. The EH STs have to harvest energy from the PT's radio-frequency (RF signals to serve the PT-PR communication as well as to transmit their signals. The proposed scheme employs incremental relaying technique in which the PR only requires the assistance from the STs when the transmission between PT and PR is not successful. Moreover, we also investigate impact of hardware impairments on performance of the primary and secondary networks. For performance evaluation, we derive exact and lower-bound expressions of outage probability (OP over Rayleigh fading channel. Monte-Carlo simulations are performed to verify the theoretical results. The results present that the outage performance of both networks can be enhanced by increasing the number of the ST-SR pairs. In addition, it is also shown that fraction of time used for EH, positions of the secondary users and the hardware-impairment level significantly impact on the system performance.

  9. Strategic Options Development and Analysis

    Science.gov (United States)

    Ackermann, Fran; Eden, Colin

    Strategic Options Development and Analysis (SODA) enables a group or individual to construct a graphical representation of a problematic situation, and thus explore options and their ramifications with respect to a complex system of goals or objectives. In addition the method aims to help groups arrive at a negotiated agreement about how to act to resolve the situation. It is based upon the use of causal mapping - a formally constructed means-ends network - as representation form. Because the picture has been constructed using the natural language of the problem owners it becomes a model of the situation that is ‘owned' by those who define the problem. The use of formalities for the construction of the model makes it amenable to a range of analyses as well as encouraging reflection and a deeper understanding. These analyses can be used in a ‘rough and ready' manner by visual inspection or through the use of specialist causal mapping software (Decision Explorer). Each of the analyses helps a group or individual discover important features of the problem situation, and these features facilitate agreeing agood solution. The SODA process is aimed at helping a group learn about the situation they face before they reach agreements. Most significantly the exploration through the causal map leads to a higher probability of more creative solutions and promotes solutions that are more likely to be implemented because the problem construction process is wider and more likely to include richer social dimensions about the blockages to action and organizational change. The basic theories that inform SODA derive from cognitive psychology and social negotiation, where the model acts as a continuously changing representation of the problematic situation - changing as the views of a person or group shift through learning and exploration. This chapter, jointly written by two leading practitioner academics and the original developers of SODA, Colin Eden and Fran Ackermann

  10. Spent fuel reprocessing options

    International Nuclear Information System (INIS)

    2008-08-01

    The objective of this publication is to provide an update on the latest developments in nuclear reprocessing technologies in the light of new developments on the global nuclear scene. The background information on spent fuel reprocessing is provided in Section One. Substantial global growth of nuclear electricity generation is expected to occur during this century, in response to environmental issues and to assure the sustainability of the electrical energy supply in both industrial and less-developed countries. This growth carries with it an increasing responsibility to ensure that nuclear fuel cycle technologies are used only for peaceful purposes. In Section Two, an overview of the options for spent fuel reprocessing and their level of development are provided. A number of options exist for the treatment of spent fuel. Some, including those that avoid separation of a pure plutonium stream, are at an advanced level of technological maturity. These could be deployed in the next generation of industrial-scale reprocessing plants, while others (such as dry methods) are at a pilot scale, laboratory scale or conceptual stage of development. In Section Three, research and development in support of advanced reprocessing options is described. Next-generation spent fuel reprocessing plants are likely to be based on aqueous extraction processes that can be designed to a country specific set of spent fuel partitioning criteria for recycling of fissile materials to advanced light water reactors or fast spectrum reactors. The physical design of these plants must incorporate effective means for materials accountancy, safeguards and physical protection. Section four deals with issues and challenges related to spent fuel reprocessing. The spent fuel reprocessing options assessment of economics, proliferation resistance, and environmental impact are discussed. The importance of public acceptance for a reprocessing strategy is discussed. A review of modelling tools to support the

  11. Deliberating emission reduction options

    Energy Technology Data Exchange (ETDEWEB)

    Dowd, A. M.; Rodriguez, M.; Jeanneret, T. [Commonwealth Scientific and Industrial Research Organisation CSIRO, 37 Graham Rd, Highett VIC 3190 (Australia); De Best-Waldhober, M.; Straver, K.; Mastop, J.; Paukovic, M. [Energy research Centre of the Netherlands ECN, Policy Studies, Amsterdam (Netherlands)

    2012-06-15

    For more than 20 years there has been a concerted international effort toward addressing climate change. International conventions, such as the United Nations Foreign Convention on Climate Change (UNFCCC; ratified in 1994), have been established by committed nations seeking to address global climate change through the reduction of greenhouse gases emitted into the Earth's atmosphere (Global CCS Institute, 2011). Long recognised as the most crucial of the greenhouse gases to impact global warming, the majority of carbon dioxide's anthropogenic global emissions are directly related to fuel combustion of which both Australia and the Netherlands' energy production is significantly reliant. Both these nations will need to consider many opinions and make hard decisions if alternative energy options are to be implemented at the scale that is required to meet international emission targets. The decisions that are required not only need to consider the many options available but also their consequences. Along with politicians, policy developers and industry, the general public also need to be active participants in deciding which energy options, and their subsequent consequences, are acceptable for implementation at the national level. Access to balanced and factual information is essential in establishing informed opinions on the many policy options available. Past research has used several methods to measure public perceptions and opinions yet for complex issues, such as emission reduction, some of these methods have shown to be problematic. For example, semi structured interviews can provide data that is flexible and context rich yet is does also come with the limitations such as it seldom provides a practical assessment that can be utilised from researcher to researcher, across disciplines and public participation techniques. Surveys on the other hand usually address these limitations but surveys that do not encourage comparison of information or ask participants to

  12. Deliberating emission reduction options

    Energy Technology Data Exchange (ETDEWEB)

    Dowd, A.M.; Rodriguez, M.; Jeanneret, T. [Commonwealth Scientific and Industrial Research Organisation CSIRO, 37 Graham Rd, Highett VIC 3190 (Australia); De Best-Waldhober, M.; Straver, K.; Mastop, J.; Paukovic, M. [Energy research Centre of the Netherlands ECN, Policy Studies, Amsterdam (Netherlands)

    2012-06-15

    For more than 20 years there has been a concerted international effort toward addressing climate change. International conventions, such as the United Nations Foreign Convention on Climate Change (UNFCCC; ratified in 1994), have been established by committed nations seeking to address global climate change through the reduction of greenhouse gases emitted into the Earth's atmosphere (Global CCS Institute, 2011). Long recognised as the most crucial of the greenhouse gases to impact global warming, the majority of carbon dioxide's anthropogenic global emissions are directly related to fuel combustion of which both Australia and the Netherlands' energy production is significantly reliant. Both these nations will need to consider many opinions and make hard decisions if alternative energy options are to be implemented at the scale that is required to meet international emission targets. The decisions that are required not only need to consider the many options available but also their consequences. Along with politicians, policy developers and industry, the general public also need to be active participants in deciding which energy options, and their subsequent consequences, are acceptable for implementation at the national level. Access to balanced and factual information is essential in establishing informed opinions on the many policy options available. Past research has used several methods to measure public perceptions and opinions yet for complex issues, such as emission reduction, some of these methods have shown to be problematic. For example, semi structured interviews can provide data that is flexible and context rich yet is does also come with the limitations such as it seldom provides a practical assessment that can be utilised from researcher to researcher, across disciplines and public participation techniques. Surveys on the other hand usually address these limitations but surveys that do not encourage comparison of information or ask

  13. Generation of Embedded Hardware/Software from SystemC

    Directory of Open Access Journals (Sweden)

    Dominique Houzet

    2006-08-01

    Full Text Available Designers increasingly rely on reusing intellectual property (IP and on raising the level of abstraction to respect system-on-chip (SoC market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propose a design flow intended to reduce the SoC design cost. This design flow unifies hardware and software using a single high-level language. It integrates hardware/software (HW/SW generation tools and an automatic interface synthesis through a custom library of adapters. We have validated our interface synthesis approach on a hardware producer/consumer case study and on the design of a given software radiocommunication application.

  14. Generation of Embedded Hardware/Software from SystemC

    Directory of Open Access Journals (Sweden)

    Ouadjaout Salim

    2006-01-01

    Full Text Available Designers increasingly rely on reusing intellectual property (IP and on raising the level of abstraction to respect system-on-chip (SoC market characteristics. However, most hardware and embedded software codes are recoded manually from system level. This recoding step often results in new coding errors that must be identified and debugged. Thus, shorter time-to-market requires automation of the system synthesis from high-level specifications. In this paper, we propose a design flow intended to reduce the SoC design cost. This design flow unifies hardware and software using a single high-level language. It integrates hardware/software (HW/SW generation tools and an automatic interface synthesis through a custom library of adapters. We have validated our interface synthesis approach on a hardware producer/consumer case study and on the design of a given software radiocommunication application.

  15. Hardware device to physical structure binding and authentication

    Science.gov (United States)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  16. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-01-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations

  17. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  18. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-01-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally

  19. Improvement of hardware basic testing : Identification and development of a scripted automation tool that will support hardware basic testing

    OpenAIRE

    Rask, Ulf; Mannestig, Pontus

    2002-01-01

    In the ever-increasing development pace, circuits and hardware are no exception. Hardware designs grow and circuits gets more complex at the same time as the market pressure lowers the expected time-to-market. In this rush, verification methods often lag behind. Hardware manufacturers must be aware of the importance of total verification if they want to avoid quality flaws and broken deadlines which in the long run will lead to delayed time-to-market, bad publicity and a decreasing market sha...

  20. How to create successful Open Hardware projects — About White Rabbits and open fields

    International Nuclear Information System (INIS)

    Bij, E van der; Arruat, M; Cattin, M; Daniluk, G; Cobas, J D Gonzalez; Gousiou, E; Lewis, J; Lipinski, M M; Serrano, J; Stana, T; Voumard, N; Wlostowski, T

    2013-01-01

    CERN's accelerator control group has embraced ''Open Hardware'' (OH) to facilitate peer review, avoid vendor lock-in and make support tasks scalable. A web-based tool for easing collaborative work was set up and the CERN OH Licence was created. New ADC, TDC, fine delay and carrier cards based on VITA and PCI-SIG standards were designed and drivers for Linux were written. Often industry was paid for developments, while quality and documentation was controlled by CERN. An innovative timing network was also developed with the OH paradigm. Industry now sells and supports these designs that find their way into new fields

  1. Modern computer hardware and the role of central computing facilities in particle physics

    International Nuclear Information System (INIS)

    Zacharov, V.

    1981-01-01

    Important recent changes in the hardware technology of computer system components are reviewed, and the impact of these changes assessed on the present and future pattern of computing in particle physics. The place of central computing facilities is particularly examined, to answer the important question as to what, if anything, should be their future role. Parallelism in computing system components is considered to be an important property that can be exploited with advantage. The paper includes a short discussion of the position of communications and network technology in modern computer systems. (orig.)

  2. How to create successful Open Hardware projects - About White Rabbits and open fields

    CERN Document Server

    van der Bij, E; Lewis, J; Stana, T; Wlostowski, T; Gousiou, E; Serrano, J; Arruat, M; Lipinski, M M; Daniluk, G; Voumard, N; Cattin, M

    2013-01-01

    CERN's accelerator control group has embraced "Open Hardware" (OH) to facilitate peer review, avoid vendor lock-in and make support tasks scalable. A web-based tool for easing collaborative work was set up and the CERN OH Licence was created. New ADC, TDC, fine delay and carrier cards based on VITA and PCI-SIG standards were designed and drivers for Linux were written. Often industry was paid for developments, while quality and documentation was controlled by CERN. An innovative timing network was also developed with the OH paradigm. Industry now sells and supports these designs that find their way into new fields.

  3. A video imaging system and related control hardware for nuclear safeguards surveillance applications

    International Nuclear Information System (INIS)

    Whichello, J.V.

    1987-03-01

    A novel video surveillance system has been developed for safeguards applications in nuclear installations. The hardware was tested at a small experimental enrichment facility located at the Lucas Heights Research Laboratories. The system uses digital video techniques to store, encode and transmit still television pictures over the public telephone network to a receiver located in the Australian Safeguards Office at Kings Cross, Sydney. A decoded, reconstructed picture is then obtained using a second video frame store. A computer-controlled video cassette recorder is used automatically to archive the surveillance pictures. The design of the surveillance system is described with examples of its operation

  4. Basics of spectroscopic instruments. Hardware of NMR spectrometer

    International Nuclear Information System (INIS)

    Sato, Hajime

    2009-01-01

    NMR is a powerful tool for structure analysis of small molecules, natural products, biological macromolecules, synthesized polymers, samples from material science and so on. Magnetic Resonance Imaging (MRI) is applicable to plants and animals Because most of NMR experiments can be done by an automation mode, one can forget hardware of NMR spectrometers. It would be good to understand features and performance of NMR spectrometers. Here I present hardware of a modern NMR spectrometer which is fully equipped with digital technology. (author)

  5. Security challenges and opportunities in adaptive and reconfigurable hardware

    OpenAIRE

    Costan, Victor Marius; Devadas, Srinivas

    2011-01-01

    We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two pa...

  6. Review of Maxillofacial Hardware Complications and Indications for Salvage

    OpenAIRE

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L.; Sanati-Mehrizy, Paymon; Factor, Stephanie H.; Taub, Peter J.

    2015-01-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances w...

  7. Testing Microgravity Flight Hardware Concepts on the NASA KC-135

    Science.gov (United States)

    Motil, Susan M.; Harrivel, Angela R.; Zimmerli, Gregory A.

    2001-01-01

    This paper provides an overview of utilizing the NASA KC-135 Reduced Gravity Aircraft for the Foam Optics and Mechanics (FOAM) microgravity flight project. The FOAM science requirements are summarized, and the KC-135 test-rig used to test hardware concepts designed to meet the requirements are described. Preliminary results regarding foam dispensing, foam/surface slip tests, and dynamic light scattering data are discussed in support of the flight hardware development for the FOAM experiment.

  8. Accelerator Technology: Injection and Extraction Related Hardware: Kickers and Septa

    CERN Document Server

    Barnes, M J; Mertens, V

    2013-01-01

    This document is part of Subvolume C 'Accelerators and Colliders' of Volume 21 'Elementary Particles' of Landolt-Börnstein - Group I 'Elementary Particles, Nuclei and Atoms'. It contains the the Section '8.7 Injection and Extraction Related Hardware: Kickers and Septa' of the Chapter '8 Accelerator Technology' with the content: 8.7 Injection and Extraction Related Hardware: Kickers and Septa 8.7.1 Fast Pulsed Systems (Kickers) 8.7.2 Electrostatic and Magnetic Septa

  9. Learning Machines Implemented on Non-Deterministic Hardware

    OpenAIRE

    Gupta, Suyog; Sindhwani, Vikas; Gopalakrishnan, Kailash

    2014-01-01

    This paper highlights new opportunities for designing large-scale machine learning systems as a consequence of blurring traditional boundaries that have allowed algorithm designers and application-level practitioners to stay -- for the most part -- oblivious to the details of the underlying hardware-level implementations. The hardware/software co-design methodology advocated here hinges on the deployment of compute-intensive machine learning kernels onto compute platforms that trade-off deter...

  10. Hardware control system using modular software under RSX-11D

    International Nuclear Information System (INIS)

    Kittell, R.S.; Helland, J.A.

    1978-01-01

    A modular software system used to control extensive hardware is described. The development, operation, and experience with this software are discussed. Included are the methods employed to implement this system while taking advantage of the Real-Time features of RSX-11D. Comparisons are made between this system and an earlier nonmodular system. The controlled hardware includes magnet power supplies, stepping motors, DVM's, and multiplexors, and is interfaced through CAMAC. 4 figures

  11. PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability

    Directory of Open Access Journals (Sweden)

    O. Ahmed

    2011-01-01

    Full Text Available Packet classification plays a crucial role for a number of network services such as policy-based routing, firewalls, and traffic billing, to name a few. However, classification can be a bottleneck in the above-mentioned applications if not implemented properly and efficiently. In this paper, we propose PCIU, a novel classification algorithm, which improves upon previously published work. PCIU provides lower preprocessing time, lower memory consumption, ease of incremental rule update, and reasonable classification time compared to state-of-the-art algorithms. The proposed algorithm was evaluated and compared to RFC and HiCut using several benchmarks. Results obtained indicate that PCIU outperforms these algorithms in terms of speed, memory usage, incremental update capability, and preprocessing time. The algorithm, furthermore, was improved and made more accessible for a variety of applications through implementation in hardware. Two such implementations are detailed and discussed in this paper. The results indicate that a hardware/software codesign approach results in a slower, but easier to optimize and improve within time constraints, PCIU solution. A hardware accelerator based on an ESL approach using Handel-C, on the other hand, resulted in a 31x speed-up over a pure software implementation running on a state of the art Xeon processor.

  12. MRI monitoring of focused ultrasound sonications near metallic hardware.

    Science.gov (United States)

    Weber, Hans; Ghanouni, Pejman; Pascal-Tenorio, Aurea; Pauly, Kim Butts; Hargreaves, Brian A

    2018-07-01

    To explore the temperature-induced signal change in two-dimensional multi-spectral imaging (2DMSI) for fast thermometry near metallic hardware to enable MR-guided focused ultrasound surgery (MRgFUS) in patients with implanted metallic hardware. 2DMSI was optimized for temperature sensitivity and applied to monitor focus ultrasound surgery (FUS) sonications near metallic hardware in phantoms and ex vivo porcine muscle tissue. Further, we evaluated its temperature sensitivity for in vivo muscle in patients without metallic hardware. In addition, we performed a comparison of temperature sensitivity between 2DMSI and conventional proton-resonance-frequency-shift (PRFS) thermometry at different distances from metal devices and different signal-to-noise ratios (SNR). 2DMSI thermometry enabled visualization of short ultrasound sonications near metallic hardware. Calibration using in vivo muscle yielded a constant temperature sensitivity for temperatures below 43 °C. For an off-resonance coverage of ± 6 kHz, we achieved a temperature sensitivity of 1.45%/K, resulting in a minimum detectable temperature change of ∼2.5 K for an SNR of 100 with a temporal resolution of 6 s per frame. The proposed 2DMSI thermometry has the potential to allow MR-guided FUS treatments of patients with metallic hardware and therefore expand its reach to a larger patient population. Magn Reson Med 80:259-271, 2018. © 2017 International Society for Magnetic Resonance in Medicine. © 2017 International Society for Magnetic Resonance in Medicine.

  13. Compiling quantum circuits to realistic hardware architectures using temporal planners

    Science.gov (United States)

    Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy

    2018-04-01

    To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.

  14. Complexity optimization and high-throughput low-latency hardware implementation of a multi-electrode spike-sorting algorithm.

    Science.gov (United States)

    Dragas, Jelena; Jackel, David; Hierlemann, Andreas; Franke, Felix

    2015-03-01

    Reliable real-time low-latency spike sorting with large data throughput is essential for studies of neural network dynamics and for brain-machine interfaces (BMIs), in which the stimulation of neural networks is based on the networks' most recent activity. However, the majority of existing multi-electrode spike-sorting algorithms are unsuited for processing high quantities of simultaneously recorded data. Recording from large neuronal networks using large high-density electrode sets (thousands of electrodes) imposes high demands on the data-processing hardware regarding computational complexity and data transmission bandwidth; this, in turn, entails demanding requirements in terms of chip area, memory resources and processing latency. This paper presents computational complexity optimization techniques, which facilitate the use of spike-sorting algorithms in large multi-electrode-based recording systems. The techniques are then applied to a previously published algorithm, on its own, unsuited for large electrode set recordings. Further, a real-time low-latency high-performance VLSI hardware architecture of the modified algorithm is presented, featuring a folded structure capable of processing the activity of hundreds of neurons simultaneously. The hardware is reconfigurable “on-the-fly” and adaptable to the nonstationarities of neuronal recordings. By transmitting exclusively spike time stamps and/or spike waveforms, its real-time processing offers the possibility of data bandwidth and data storage reduction.

  15. H-II Transfer Vehicle (HTV) and the Operations Concept for Extravehicular Activity (EVA) Hardware

    Science.gov (United States)

    Chullen, Cinda; Blome, Elizabeth; Tetsuya, Sakashita

    2011-01-01

    With the retirement of the Space Shuttle fleet imminent in 2011, a new operations concept will become reality to meet the transportation challenges of the International Space Station (ISS). The planning associated with the retirement of the Space Shuttle has been underway since the announcement in 2004. Since then, several companies and government entities have had to look for innovative low-cost commercial orbital transportation systems to continue to achieve the objectives of ISS delivery requirements. Several options have been assessed and appear ready to meet the large and demanding delivery requirements of the ISS. Options that have been identified that can facilitate the challenge include the Russian Federal Space Agency's Soyuz and Progress spacecraft, European Space Agency's Automated Transfer Vehicle (ATV), and the Japan Aerospace Exploration Agency's (JAXA s) H-II Transfer Vehicle (HTV). The newest of these options is the JAXA's HTV. This paper focuses on the HTV, mission architecture and operations concept for Extra-Vehicular Activities (EVA) hardware, the associated launch system, and details of the launch operations approach.

  16. Treatment Options for Actinic Keratosis

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends mostly on ... helped by lip balm or petroleum jelly . Treatment Option Overview Key Points There are different types of ...

  17. Treatment Option Overview (Vaginal Cancer)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends on the ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  18. Treatment Option Overview (Anal Cancer)

    Science.gov (United States)

    ... affect the prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) depends on the ... or in other parts of the body. Treatment Option Overview Key Points There are different types of ...

  19. Pricing American and Asian Options

    OpenAIRE

    Pat Muldowney

    2015-01-01

    An analytic method for pricing American call options is provided; followed by an empirical method for pricing Asian call options. The methodology is the pricing theory presented in "A Modern Theory of Random Variation", by Patrick Muldowney, 2012.

  20. Adaptive Hardware Cryptography Engine Based on FPGA

    International Nuclear Information System (INIS)

    Afify, M.A.A.

    2011-01-01

    In the last two decades, with spread of the real time applications over public networks or communications the need for information security become more important but with very high speed for data processing, to keep up with the real time applications requirements, that is the reason for using FPGA as an implementation platform for the proposed cryptography engine. Hence in this thesis a new S-Box design has been demonstrated and implemented, there is a comparison for the simulation results for proposed S-Box simulation results with respect to different designs for S-Box in DES, Two fish and Rijndael algorithms and another comparison among proposed S-Box with different sizes. The proposed S-Box implemented with 32-bits Input data lines and compared with different designs in the encryption algorithms with the same input lines, the proposed S-Box gives implementation results for the maximum frequency 120 MHz but the DES S-Box gives 34 MHz and Rijndael gives 71 MHz, on the other hand the proposed design gives the best implementation area, hence it gives 50 Configurable logic Block CLB but DES gives 88 CLB. The proposed S-Box implemented in different sizes 64-bits, 128-bits, and 256-bits for input data lines. The implementation carried out by using UniDAq PCI card with FPGA Chip XCV 800, synthesizing carried out for all designs by using Leonardo spectrum and simulation carried out by using model sim simulator program form the FPGA advantage package. Finally the results evaluation and verifications carried out using the UniDAq FPGA PCI card with chip XCV 800. Different cases study have been implemented, data encryption, images encryption, voice encryption, and video encryption. A prototype for Remote Monitoring Control System has been implemented. Finally the proposed design for S-Box has a significant achievement in maximum frequency, implementation area, and encryption strength.

  1. The information content of options

    OpenAIRE

    Navon, Yonatan

    2017-01-01

    The objective of this thesis is to examine the information content of stock options in financial markets. A key question in financial economics is how information diffuses across markets and how quickly it is reflected in security prices. This thesis aims at exploring this question by investigating the informational role that options play in financial markets. This is achieved by exploring the joint cross section of option and bond prices, the informational role of options in seasoned equity ...

  2. Balancing of solar heating options

    NARCIS (Netherlands)

    Veltkamp, W.B.; van Koppen, C.W.J.; Ouden, den C.

    1984-01-01

    In the field of energy conservation many options are presently competing. This study aims at providing more rational criteria for selection between these options.The options considered are; insulation of the walls, regeneration of the heat in the waste air, double glazing, attached sunspace at the

  3. Stock option repricing in Europe

    NARCIS (Netherlands)

    Sauer, M.; Sautner, Z.

    2008-01-01

    This paper investigates the link between option repricing, firm performance and corporate governance in Europe. Our sample consists of 77 European firms that repriced their stock option between 1987 and 2003. We document that option repricing is mainly a phenomenon for young and fast growing firms

  4. Neural networks at the Tevatron

    International Nuclear Information System (INIS)

    Badgett, W.; Burkett, K.; Campbell, M.K.; Wu, D.Y.; Bianchin, S.; DeNardi, M.; Pauletta, G.; Santi, L.; Caner, A.; Denby, B.; Haggerty, H.; Lindsey, C.S.; Wainer, N.; Dall'Agata, M.; Johns, K.; Dickson, M.; Stanco, L.; Wyss, J.L.

    1992-10-01

    This paper summarizes neural network applications at the Fermilab Tevatron, including the first online hardware application in high energy physics (muon tracking): the CDF and DO neural network triggers; offline quark/gluon discrimination at CDF; ND a new tool for top to multijets recognition at CDF

  5. Network Physics anounces first product to provide business-level management of the most complex and dynamic networks

    CERN Multimedia

    2003-01-01

    Network Physics, provider of business-level, traffic flow-based network management solutions, today announced the introduction of the Network Physics NP/BizFlow-1000. With the NP/BizFlow-1000, Fortune 1000 companies with complex and dynamic networks can analyze the flows that link business groups, critical applications, and network software and hardware (1 page).

  6. Contemplating future energy options

    International Nuclear Information System (INIS)

    Pooley, D.

    2005-01-01

    All political parties in the UK accept that we should move away from our reliance on fossil fuels towards a much greater use of alternative energy technologies. Nuclear power is one of these but finds minimal support in the political spectrum. The article reviews the European Commission's Advisory Group on Energy submission to the EC's report entitled 'Key Tasks for European Energy R and D'. The 'strength and weaknesses' of the various 'alternative energy' systems (including nuclear power) are summarised and then the key R and D tasks which, if they are carried out successfully, should make the eight selected technologies significantly more attractive. However, the message here is clear enough: there are no easy options, only a range of very imperfect possibilities, despite what enthusiastic proponents of each may say. Nuclear fission is certainly one of the most attractive options available, but the industry needs to continue to strive to eliminate the possibility of significant off-site releases, whether caused by plant failure or by human error or intention, and to prove beyond reasonable doubt the safety of high-level radioactive waste disposal. (author)

  7. Achalasia: Treatment Options Revisited

    Directory of Open Access Journals (Sweden)

    Willemijntje A Hoogerwerf

    2000-01-01

    Full Text Available The aim of all current forms of treatment of achalasia is to enable the patient to eat without disabling symptoms such as dysphagia, regurgitation, coughing or choking. Historically, this has been accomplished by mechanical disruption of the lower esophageal sphincter fibres, either by means of pneumatic dilation (PD or by open surgical myotomy. The addition of laparoscopic myotomy and botulinum toxin (BTX injection to the therapeutic armamentarium has triggered a recent series of reviews to determine the optimal therapeutic approach. Both PD and BTX have excellent short term (less than three months efficacy in the majority of patients. New data have been published that suggest that PD and BTX (with repeat injections can potentially obtain long term efficacy. PD is still considered the first-line treatment by most physicians; its main disadvantage is risk of perforation. BTX injection is evolving as an excellent, safe option for patients who are considered high risk for more invasive procedures. Laparoscopic myotomy with combined antireflux surgery is an increasingly attractive option in younger patients with achalasia, but long term follow-up studies are required to establish its efficacy and the potential for reflux-related sequelae.

  8. Retrieval options study

    Energy Technology Data Exchange (ETDEWEB)

    1980-03-01

    This Retrieval Options Study is part of the systems analysis activities of the Office of Nuclear Waste Isolation to develop the scientific and technological bases for radioactive waste repositories in various geologic media. The study considers two waste forms, high level waste and spent fuel, and defines various classes of waste retrieval and recovery. A methodology and data base are developed which allow the relative evaluation of retrieval and recovery costs and the following technical criteria: safety; technical feasibility; ease of retrieval; probable intact retrieval time; safeguards; monitoring; criticality; and licensability. A total of 505 repository options are defined and the cost and technical criteria evaluated utilizing a combination of facts and engineering judgments. The repositories evaluated are selected combinations of the following parameters: Geologic Media (salt, granite, basalt, shale); Retrieval Time after Emplacement (5 and 25 years); Emplacement Design (nominal hole, large hole, carbon steel canister, corrosion resistant canister, backfill in hole, nominal sleeves, thick wall sleeves); Emplacement Configuration (single vertical, multiple vertical, single horizontal, multiple horizontal, vaults; Thermal Considerations; (normal design, reduced density, once-through ventilation, recirculated ventilation); Room Backfill; (none, run-of-mine, early, 5 year delay, 25 year delay, decommissioned); and Rate of Retrieval; (same as emplacement, variably slower depending on repository/canister condition).

  9. Retrieval options study

    International Nuclear Information System (INIS)

    1980-03-01

    This Retrieval Options Study is part of the systems analysis activities of the Office of Nuclear Waste Isolation to develop the scientific and technological bases for radioactive waste repositories in various geologic media. The study considers two waste forms, high level waste and spent fuel, and defines various classes of waste retrieval and recovery. A methodology and data base are developed which allow the relative evaluation of retrieval and recovery costs and the following technical criteria: safety; technical feasibility; ease of retrieval; probable intact retrieval time; safeguards; monitoring; criticality; and licensability. A total of 505 repository options are defined and the cost and technical criteria evaluated utilizing a combination of facts and engineering judgments. The repositories evaluated are selected combinations of the following parameters: Geologic Media (salt, granite, basalt, shale); Retrieval Time after Emplacement (5 and 25 years); Emplacement Design (nominal hole, large hole, carbon steel canister, corrosion resistant canister, backfill in hole, nominal sleeves, thick wall sleeves); Emplacement Configuration (single vertical, multiple vertical, single horizontal, multiple horizontal, vaults; Thermal Considerations; (normal design, reduced density, once-through ventilation, recirculated ventilation); Room Backfill; (none, run-of-mine, early, 5 year delay, 25 year delay, decommissioned); and Rate of Retrieval;

  10. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  11. The Texas Solution to the Nation's Disposal Needs for Irradiated Hardware - 13337

    International Nuclear Information System (INIS)

    Britten, Jay M.

    2013-01-01

    The closure of the disposal facility in Barnwell, South Carolina, to out-of-compact states in 2008 left commercial nuclear power plants without a disposal option for Class B and C irradiated hardware. In 2012, Waste Control Specialists LLC (WCS) opened a highly engineered facility specifically designed and built for the disposal of Class B and C waste. The WCS facility is the first Interstate Compact low-level radioactive waste disposal facility to be licensed and operated under the Low-level Waste Policy Act of 1980, as amended in 1985. Due to design requirements of a modern Low Level Radioactive Waste (LLRW) facility, traditional methods for disposal were not achievable at the WCS site. Earlier methods primarily utilized the As Low as Reasonably Achievable (ALARA) concept of distance to accomplish worker safety. The WCS method required the use of all three ALARA concepts of time, distance, and shielding to ensure the safe disposal of this highly hazardous waste stream. (authors)

  12. Real time hardware implementation of power converters for grid integration of distributed generation and STATCOM systems

    Science.gov (United States)

    Jaithwa, Ishan

    Deployment of smart grid technologies is accelerating. Smart grid enables bidirectional flows of energy and energy-related communications. The future electricity grid will look very different from today's power system. Large variable renewable energy sources will provide a greater portion of electricity, small DERs and energy storage systems will become more common, and utilities will operate many different kinds of energy efficiency. All of these changes will add complexity to the grid and require operators to be able to respond to fast dynamic changes to maintain system stability and security. This thesis investigates advanced control technology for grid integration of renewable energy sources and STATCOM systems by verifying them on real time hardware experiments using two different systems: d SPACE and OPAL RT. Three controls: conventional, direct vector control and the intelligent Neural network control were first simulated using Matlab to check the stability and safety of the system and were then implemented on real time hardware using the d SPACE and OPAL RT systems. The thesis then shows how dynamic-programming (DP) methods employed to train the neural networks are better than any other controllers where, an optimal control strategy is developed to ensure effective power delivery and to improve system stability. Through real time hardware implementation it is proved that the neural vector control approach produces the fastest response time, low overshoot, and, the best performance compared to the conventional standard vector control method and DCC vector control technique. Finally the entrepreneurial approach taken to drive the technologies from the lab to market via ORANGE ELECTRIC is discussed in brief.

  13. Flight Hardware Virtualization for On-Board Science Data Processing Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Utilize Hardware Virtualization technology to benefit on-board science data processing by investigating new real time embedded Hardware Virtualization solutions and...

  14. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  15. Power Hardware-in-the-Loop Evaluation of PV Inverter Grid Support on Hawaiian Electric Feeders

    Energy Technology Data Exchange (ETDEWEB)

    Nelson, Austin A [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Prabakar, Kumaraguru [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Nagarajan, Adarsh [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Nepal, Shaili [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Hoke, Anderson F [National Renewable Energy Laboratory (NREL), Golden, CO (United States); Asano, Marc [Hawaiian Electric Company; Ueda, Reid [Hawaiian Electric Company; Ifuku, Earle [Hawaiian Electric Company

    2017-10-03

    As more grid-connected photovoltaic (PV) inverters become compliant with evolving interconnections requirements, there is increased interest from utilities in understanding how to best deploy advanced grid-support functions (GSF) in the field. One efficient and cost-effective method to examine such deployment options is to leverage power hardware-in-the-loop (PHIL) testing methods, which combine the fidelity of hardware tests with the flexibility of computer simulation. This paper summarizes a study wherein two Hawaiian Electric feeder models were converted to real-time models using an OPAL-RT real-time digital testing platform, and integrated with models of GSF capable PV inverters based on characterization test data. The integrated model was subsequently used in PHIL testing to evaluate the effects of different fixed power factor and volt-watt control settings on voltage regulation of the selected feeders using physical inverters. Selected results are presented in this paper, and complete results of this study were provided as inputs for field deployment and technical interconnection requirements for grid-connected PV inverters on the Hawaiian Islands.

  16. Evaluating the Governance Model of Hardware-Dependent Software Ecosystems – A Case Study of the Axis Ecosystem

    OpenAIRE

    Wnuk, Krzysztof; Manikas, Konstantinos; Runeson, Per; Matilda, Lantz; Oskar, Weijden; Munir, Hussan

    2014-01-01

    Ecosystem governance becomes gradually more relevant for a set of companies or actors characterized by symbiotic relations evolved on the top of a technological platform, i.e. a software ecosystem. In this study, we focus on the governance of a hardware-dependent software ecosystem. More specifically, we evaluate the governance model applied by Axis, a network video and surveillance camera producer, that is the platform owner and orchestrator of the Application Development Partner (ADP) softw...

  17. Optical packet switched design with relaxed maximum hardware parameters and high service-class granularity for flexible switch node dimensioning

    DEFF Research Database (Denmark)

    Nord, Martin

    2004-01-01

    This work proposes a quality of service differentiation algorithm, improving the service class granularity and isolation of our recently presented waveband plane based design. The design aims at overcoming potential hardware limitations and increasing the switch node dimensioning flexibility...... in core networks. Exploiting the wavelength dimension for contention resolution, using partially shared wavelength converter pools, avoids optical buffers and reduces wavelength converter count. These benefits are illustrated by numerical simulations, and are highlighted in a dimensioning study with three...

  18. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  19. Fast DRR splat rendering using common consumer graphics hardware

    International Nuclear Information System (INIS)

    Spoerk, Jakob; Bergmann, Helmar; Wanschitz, Felix; Dong, Shuo; Birkfellner, Wolfgang

    2007-01-01

    Digitally rendered radiographs (DRR) are a vital part of various medical image processing applications such as 2D/3D registration for patient pose determination in image-guided radiotherapy procedures. This paper presents a technique to accelerate DRR creation by using conventional graphics hardware for the rendering process. DRR computation itself is done by an efficient volume rendering method named wobbled splatting. For programming the graphics hardware, NVIDIAs C for Graphics (Cg) is used. The description of an algorithm used for rendering DRRs on the graphics hardware is presented, together with a benchmark comparing this technique to a CPU-based wobbled splatting program. Results show a reduction of rendering time by about 70%-90% depending on the amount of data. For instance, rendering a volume of 2x10 6 voxels is feasible at an update rate of 38 Hz compared to 6 Hz on a common Intel-based PC using the graphics processing unit (GPU) of a conventional graphics adapter. In addition, wobbled splatting using graphics hardware for DRR computation provides higher resolution DRRs with comparable image quality due to special processing characteristics of the GPU. We conclude that DRR generation on common graphics hardware using the freely available Cg environment is a major step toward 2D/3D registration in clinical routine

  20. Optional Defaultable Markets

    Directory of Open Access Journals (Sweden)

    Mohamed N. Abdelghani

    2017-10-01

    Full Text Available The paper deals with defaultable markets, one of the main research areas of mathematical finance. It proposes a new approach to the theory of such markets using techniques from the calculus of optional stochastic processes on unusual probability spaces, which was not presented before. The paper is a foundation paper and contains a number of fundamental results on modeling of defaultable markets, pricing and hedging of defaultable claims and results on the probability of default under such conditions. Moreover, several important examples are presented: a new pricing formula for a defaultable bond and a new pricing formula for credit default swap. Furthermore, some results on the absence of arbitrage for markets on unusual probability spaces and markets with default are also provided.

  1. Automotive turbogenerator design options

    Energy Technology Data Exchange (ETDEWEB)

    Rodgers, C. [ITC, San Diego, CA (United States); McDonald, C. [McDonald Thermal Engineering, La Jolla, CA (United States)

    1998-12-31

    For the small turbogenerator to find reception in the hybrid electric automotive market its major features must be dominated by the following considerations, low cost, high performance, low emissions, compact size and high reliability. Not meeting the first two criteria has been the nemesis of earlier attempts to introduce the small gas turbine for automotive service. With emphasis on the design for low cost and high performance, this paper presents several turbogenerator design flowpath configuration options for the major engine components. The projected evolution from today`s state-of-the-art all metallic engines, to advanced technology ceramic units for service in the early decade of the 21st century, is the major topic of this paper. (author)

  2. Hardware and software concept of the remote monitoring system for nuclear reactors in Bavaria

    International Nuclear Information System (INIS)

    Gietl, G.

    1981-01-01

    The remote monitoring system for nuclear reactors (KFUe) is a fully automatic system for the measuring and registration of radioactive releases and of operation parameters of the nuclear power plants in Bavaria. It has also to measure the meteorological parameters on the site of a power plant for the purpose of dispersion calculations. The system consists of the network centre and the subsystems with their satellite stations at the nuclear power plants. Process computers in the network centre and in the subsystems perform the automatic operation and they handle the data transmission via data lines. The hardware of the entire system is so conceived that the mesured data can be processed, stored and displayed in an optimal way for the user. The software of the KFUe centre and the subsystems is structured strictly modular. Redunancies are implied in the hardware and software. The automatic remote air quality monitoring system of Bavaria (LUeB) can be operated as a stand-by system for the KFUe and vice versa in case of an emergency. (orig./HP) [de

  3. The Gel Generator option

    International Nuclear Information System (INIS)

    Boyd, R.E.

    1999-01-01

    The development of a national policy for guaranteeing an ample supply of 99m Tc to nuclear medicine, involves issues which go beyond the means by which radioactivation is achieved. Indeed, in such an exercise the pragmatic dictates of business and the sensitivities of politics must also be taken into account. Furthermore where a preference towards the nuclear reactor or the potential of cyclotrons is being questioned, the debate is incomplete if the only options that are considered are the fission-based 99 Mo generator versus the direct cyclotron production of 99m Tc. There is a third option (also neutron γ-based), an alternative to the fission 99 Mo generator, which ought not be overlooked. The application of low specific activity (n,γ) 99 Mo to a new type of generator, the Gel Generator, has been the focus of much research, particularly in Australia and more recently in China. After the initial concept had been established in the laboratory, the Australian researchers then undertook a comprehensive program of tests on the Gel Generator to assess its potential, either in the clinical laboratory or the centralised radiopharmacy, for supplying 99m Tc suitable for nuclear medicine. The outcome of this program was a clear indication that the Gel Generator innovation had the capability to provide both technical and economic advantages to the nuclear medicine industry. These advantages are described. Since that time the Gel Generator has been selected for routine use in China where it now satisfies more than 30% of the 99m Tc demand. (author)

  4. The $2000 Electric Powertrain Option-1 Program. Final technical report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1999-06-01

    This report describes the tasks accomplished as part of Northrop Grumman's TRP $2000 Electric Powertrain Option-1 program. Northrop Grumman has strived to achieve technology advances and development considered as high priority to the success of future electric vehicles. Northrop Grumman has achieved the intent of the program by taking several steps toward reducing the cost of the electric vehicle powertrain, demonstrating technologies in the form of hardware and introducing enhancements into production that are consistent with the needs of the market.

  5. Mars ascent propulsion options for small sample return vehicles

    International Nuclear Information System (INIS)

    Whitehead, J. C.

    1997-01-01

    An unprecedented combination of high propellant fraction and small size is required for affordable-scale Mars return, regardless of the number of stages, or whether Mars orbit rendezvous or in-situ propellant options are used. Conventional space propulsion technology is too heavy, even without structure or other stage subsystems. The application of launch vehicle design principles to the development of new hardware on a tiny scale is therefore suggested. Miniature pump-fed rocket engines fed by low pressure tanks can help to meet this challenge. New concepts for engine cycles using piston pumps are described, and development issues are outlined

  6. Space Network Devices Developed

    Science.gov (United States)

    Jones, Robert E.

    2004-01-01

    The NASA Glenn Research Center through a contract with Spectrum Astro, Inc., has been developing space network hardware as an enabling technology using open systems interconnect (OSI) standards for space-based communications applications. The OSI standard is a well-recognized layered reference model that specifies how data should be sent node to node in a communications network. Because of this research and technology development, a space-qualifiable Ethernet-based network interface card (similar to the type found in a networked personal computer) and the associated four-port hub were designed and developed to flight specifications. During this research and development, there also have been many lessons learned for determining approaches for migrating existing spacecraft architectures to an OSI-network-based platform. Industry has recognized the benefits of targeting hardware developed around OSI standards such as Transmission Control Protocol/Internet Protocol (TCP/IP) or similar protocols for use in future generations of space communication systems. Some of these tangible benefits include overall reductions in mission schedule and cost and in system complexity. This development also brings us a step closer to the realization of a principal investigator on a terrestrial Internet site being able to interact with space platform assets in near real time. To develop this hardware, Spectrum Astro first conducted a technology analysis of alternatives study. For this analysis, they looked at the features of three protocol specifications: Ethernet (IEEE 802.3), Firewire (IEEE 1394), and Spacewire (IEEE 1355). A thorough analysis was performed on the basis of criteria such as current protocol performance and suitability for future space applications. Spectrum Astro also projected future influences such as cost, hardware and software availability, throughput performance, and integration procedures for current and transitive space architectures. After a thorough analysis

  7. Hello! Kids Network around the World.

    Science.gov (United States)

    Lynes, Kristine

    1996-01-01

    Describes Kids Network, an educational network available from the National Geographic Society that allows students in grades four through six to become part of research teams that include students from around the world. Computer hardware requirements and a list of Kids Network research questions are listed in a sidebar. (JMV)

  8. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  9. Hardware and software maintenance strategies for upgrading vintage computers

    International Nuclear Information System (INIS)

    Wang, B.C.; Buijs, W.J.; Banting, R.D.

    1992-01-01

    The paper focuses on the maintenance of the computer hardware and software for digital control computers (DCC). Specific design and problems related to various maintenance strategies are reviewed. A foundation was required for a reliable computer maintenance and upgrading program to provide operation of the DCC with high availability and reliability for 40 years. This involved a carefully planned and executed maintenance and upgrading program, involving complementary hardware and software strategies. The computer system was designed on a modular basis, with large sections easily replaceable, to facilitate maintenance and improve availability of the system. Advances in computer hardware have made it possible to replace DCC peripheral devices with reliable, inexpensive, and widely available components from PC-based systems (PC = personal computer). By providing a high speed link from the DCC to a PC, it is now possible to use many commercial software packages to process data from the plant. 1 fig

  10. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah; Amin, Osama; Ikki, Salama S.; Alouini, Mohamed-Slim

    2017-01-01

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  11. Hardware controls for the STAR experiment at RHIC

    International Nuclear Information System (INIS)

    Reichhold, D.; Bieser, F.; Bordua, M.; Cherney, M.; Chrin, J.; Dunlop, J.C.; Ferguson, M.I.; Ghazikhanian, V.; Gross, J.; Harper, G.; Howe, M.; Jacobson, S.; Klein, S.R.; Kravtsov, P.; Lewis, S.; Lin, J.; Lionberger, C.; LoCurto, G.; McParland, C.; McShane, T.; Meier, J.; Sakrejda, I.; Sandler, Z.; Schambach, J.; Shi, Y.; Willson, R.; Yamamoto, E.; Zhang, W.

    2003-01-01

    The STAR detector sits in a high radiation area when operating normally; therefore it was necessary to develop a robust system to remotely control all hardware. The STAR hardware controls system monitors and controls approximately 14,000 parameters in the STAR detector. Voltages, currents, temperatures, and other parameters are monitored. Effort has been minimized by the adoption of experiment-wide standards and the use of pre-packaged software tools. The system is based on the Experimental Physics and Industrial Control System (EPICS) . VME processors communicate with subsystem-based sensors over a variety of field busses, with High-level Data Link Control (HDLC) being the most prevalent. Other features of the system include interfaces to accelerator and magnet control systems, a web-based archiver, and C++-based communication between STAR online, run control and hardware controls and their associated databases. The system has been designed for easy expansion as new detector elements are installed in STAR

  12. Plutonium Protection System (PPS). Volume 2. Hardware description. Final report

    International Nuclear Information System (INIS)

    Miyoshi, D.S.

    1979-05-01

    The Plutonium Protection System (PPS) is an integrated safeguards system developed by Sandia Laboratories for the Department of Energy, Office of Safeguards and Security. The system is designed to demonstrate and test concepts for the improved safeguarding of plutonium. Volume 2 of the PPS final report describes the hardware elements of the system. The major areas containing hardware elements are the vault, where plutonium is stored, the packaging room, where plutonium is packaged into Container Modules, the Security Operations Center, which controls movement of personnel, the Material Accountability Center, which maintains the system data base, and the Material Operations Center, which monitors the operating procedures in the system. References are made to documents in which details of the hardware items can be found

  13. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah

    2017-02-22

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  14. Transportation Options | Climate Neutral Research Campuses | NREL

    Science.gov (United States)

    Transportation Options Transportation Options Transportation to, from, and within a research campus from business travel often enlarge the footprint more than expected. To understand options for climate

  15. Optimized hardware design for the divertor remote handling control system

    Energy Technology Data Exchange (ETDEWEB)

    Saarinen, Hannu [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland)], E-mail: hannu.saarinen@tut.fi; Tiitinen, Juha; Aha, Liisa; Muhammad, Ali; Mattila, Jouni; Siuko, Mikko; Vilenius, Matti [Tampere University of Technology, Korkeakoulunkatu 6, 33720 Tampere (Finland); Jaervenpaeae, Jorma [VTT Systems Engineering, Tekniikankatu 1, 33720 Tampere (Finland); Irving, Mike; Damiani, Carlo; Semeraro, Luigi [Fusion for Energy, Josep Pla 2, Torres Diagonal Litoral B3, 08019 Barcelona (Spain)

    2009-06-15

    A key ITER maintenance activity is the exchange of the divertor cassettes. One of the major focuses of the EU Remote Handling (RH) programme has been the study and development of the remote handling equipment necessary for divertor exchange. The current major step in this programme involves the construction of a full scale physical test facility, namely DTP2 (Divertor Test Platform 2), in which to demonstrate and refine the RH equipment designs for ITER using prototypes. The major objective of the DTP2 project is the proof of concept studies of various RH devices, but is also important to define principles for standardizing control hardware and methods around the ITER maintenance equipment. This paper focuses on describing the control system hardware design optimization that is taking place at DTP2. Here there will be two RH movers, namely the Cassette Multifuctional Mover (CMM), Cassette Toroidal Mover (CTM) and assisting water hydraulic force feedback manipulators (WHMAN) located aboard each Mover. The idea here is to use common Real Time Operating Systems (RTOS), measurement and control IO-cards etc. for all maintenance devices and to standardize sensors and control components as much as possible. In this paper, new optimized DTP2 control system hardware design and some initial experimentation with the new DTP2 RH control system platform are presented. The proposed new approach is able to fulfil the functional requirements for both Mover and Manipulator control systems. Since the new control system hardware design has reduced architecture there are a number of benefits compared to the old approach. The simplified hardware solution enables the use of a single software development environment and a single communication protocol. This will result in easier maintainability of the software and hardware, less dependence on trained personnel, easier training of operators and hence reduced the development costs of ITER RH.

  16. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  17. Automating an EXAFS facility: hardware and software considerations

    International Nuclear Information System (INIS)

    Georgopoulos, P.; Sayers, D.E.; Bunker, B.; Elam, T.; Grote, W.A.

    1981-01-01

    The basic design considerations for computer hardware and software, applicable not only to laboratory EXAFS facilities, but also to synchrotron installations, are reviewed. Uniformity and standardization of both hardware configurations and program packages for data collection and analysis are heavily emphasized. Specific recommendations are made with respect to choice of computers, peripherals, and interfaces, and guidelines for the development of software packages are set forth. A description of two working computer-interfaced EXAFS facilities is presented which can serve as prototypes for future developments. 3 figures

  18. Surface moisture measurement system hardware acceptance test report

    Energy Technology Data Exchange (ETDEWEB)

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  19. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  20. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  1. Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

    Energy Technology Data Exchange (ETDEWEB)

    Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

    1993-01-01

    Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

  2. Carbonate fuel cell endurance: Hardware corrosion and electrolyte management status

    Energy Technology Data Exchange (ETDEWEB)

    Yuh, C.; Johnsen, R.; Farooque, M.; Maru, H.

    1993-05-01

    Endurance tests of carbonate fuel cell stacks (up to 10,000 hours) have shown that hardware corrosion and electrolyte losses can be reasonably controlled by proper material selection and cell design. Corrosion of stainless steel current collector hardware, nickel clad bipolar plate and aluminized wet seal show rates within acceptable limits. Electrolyte loss rate to current collector surface has been minimized by reducing exposed current collector surface area. Electrolyte evaporation loss appears tolerable. Electrolyte redistribution has been restrained by proper design of manifold seals.

  3. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  4. Hardware-assisted software clock synchronization for homogeneous distributed systems

    Science.gov (United States)

    Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

    1990-01-01

    A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

  5. The Security Research of Digital Library Network

    Science.gov (United States)

    Zhang, Xin; Song, Ding-Li; Yan, Shu

    Digital library is a self-development needs for the modern library to meet the development requirements of the times, changing the way services and so on. digital library from the hardware, technology, management and other aspects to objective analysis of the factors of threats to digital library network security. We should face up the problems of digital library network security: digital library network hardware are "not hard", the technology of digital library is relatively lag, digital library management system is imperfect and other problems; the government should take active measures to ensure that the library funding, to enhance the level of network hardware, to upgrade LAN and prevention technology, to improve network control technology, network monitoring technology; to strengthen safety management concepts, to prefect the safety management system; and to improve the level of security management modernization for digital library.

  6. [Network Design of the Spaceport Command and Control System

    Science.gov (United States)

    Teijeiro, Antonio

    2017-01-01

    I helped the Launch Control System (LCS) hardware team sustain the network design of the Spaceport Command and Control System. I wrote the procedure that will be used to satisfy an official hardware test for the hardware carrying data from the Launch Vehicle. I installed hardware and updated design documents in support of the ongoing development of the Spaceport Command and Control System and applied firewall experience I gained during my spring 2017 semester to inspect and create firewall security policies as requested. Finally, I completed several online courses concerning networking fundamentals and Unix operating systems.

  7. Option-implied term structures

    OpenAIRE

    Vogt, Erik

    2014-01-01

    The illiquidity of long-maturity options has made it difficult to study the term structures of option spanning portfolios. This paper proposes a new estimation and inference framework for these option-implied term structures that addresses long-maturity illiquidity. By building a sieve estimator around the risk-neutral valuation equation, the framework theoretically justifies (fat-tailed) extrapolations beyond truncated strikes and between observed maturities while remaining nonparametric. Ne...

  8. Portfolio insurance using traded options

    OpenAIRE

    Machado-Santos, Carlos

    2001-01-01

    Literature concerning the institutional use of options indicates that the main purpose of option trading is to provide investors with the opportunity to create return distributions previously unavailable, considering that options provide the means to manipulate portfolio returns. In such a context, this study intends to analyse the returns of insured portfolios generated by hedging strategies on underlying stock portfolios. Because dynamic hedging is too expensive, we have hedged the stock po...

  9. Synroc processing options

    International Nuclear Information System (INIS)

    Rozsa, R.B.; Hoenig, C.L.

    1981-01-01

    Synroc is a titanate-based ceramic material currently being developed for immobilizing high-level nuclear reactor wastes in solid form. Synroc D is a unique variation of Synroc. It can contain the high-level defense wastes, particularly those in storage at the Savannah River Plant. In this report, we review the early development of the initial Synroc process, discuss modification and other options that simplify it overall, and recommend the future direction of research and development in the processing area. A reference Synroc process is described briefly and contrasted with the Savannah River Laboratory glass-based reference case. Preliminary engineering layouts show Synroc to be a more complex processing operation and, thus, more expensive than the glass-based process. However, we believe that simplifications, which will significantly reduce the cost difference, are possible. Further research and development will continue in the areas of slurry processing, fluidized bed calcination, and mineralization. This last will use sintering, hot uniaxial pressing, or hot isostatic pressing

  10. Nuclear technology options

    International Nuclear Information System (INIS)

    Salvatores, Massimo

    2013-01-01

    Different strategies and motivations in different countries have led to diverse options. In Europe the SNETP (Sustainable Nuclear Energy Technology Platform) has the objective of developing R&D supporting GEN-II (present) and GEN-III nuclear systems under development; allowing sustainability and minimisation of waste burden, promoting advanced Gen-IV Fast Reactors; and accounting for a Nuclear Cogeneration Industrial Initiative. A remarkable initiative in the USA has been the promotion of small modular reactors (SMRs) – at less than 300 MWe in capacity, much smaller than typical reactors – which can be an ideal choice for (remote) areas which cannot support a larger reactor. Compact scalable design offers a host of potential safety, construction and economic benefits. More “upbeat” strategies are expected in other areas of the world where significant increase in nuclear energy demand is predicted in the next decades. If this growth materialises, future fuel cycles characteristics, feasibility and acceptability will be crucial. This paper will discuss different scenarios for future fuel cycles, resources optimisation and/or waste minimization, the range from full fast reactor deployment to phase-out, management of spent nuclear fuel and the significant potential benefits of advanced cycles. The next 45 years will be dominated by deployment of standard large or medium size plants operating for 60 years. Available resources do allow it. However, fuel cycle will be a growing and most challenging issue and early assessments will be needed for public acceptance and policy decisions.

  11. Optional carbon capture

    Energy Technology Data Exchange (ETDEWEB)

    Alderson, T.; Scott, S.; Griffiths, J. [Jacobs Engineering, London (United Kingdom)

    2007-07-01

    In the case of IGCC power plants, carbon capture can be carried out before combustion. The carbon monoxide in the syngas is catalytically shifted to carbon dioxide and then captured in a standard gas absorption system. However, the insertion of a shift converter into an existing IGCC plant with no shift would mean a near total rebuild of the gasification waste heat recovery, gas treatment system and HRSG, with only the gasifier and gas turbine retaining most of their original features. To reduce the extent, cost and time taken for the revamping, the original plant could incorporate the shift, and the plant would then be operated without capture to advantage, and converted to capture mode of operation when commercially appropriate. This paper examines this concept of placing a shift converter into an IGCC plant before capture is required, and operating the same plant first without and then later with CO{sub 2} capture in a European context. The advantages and disadvantages of this 'capture ready' option are discussed. 6 refs., 2 figs., 4 tabs.

  12. Treatment Options for Narcolepsy.

    Science.gov (United States)

    Barateau, Lucie; Lopez, Régis; Dauvilliers, Yves

    2016-05-01

    Narcolepsy type 1 and narcolepsy type 2 are central disorders of hypersomnolence. Narcolepsy type 1 is characterized by excessive daytime sleepiness and cataplexy and is associated with hypocretin-1 deficiency. On the other hand, in narcolepsy type 2, cerebrospinal fluid hypocretin-1 levels are normal and cataplexy absent. Despite major advances in our understanding of narcolepsy mechanisms, its current management is only symptomatic. Treatment options may vary from a single drug that targets several symptoms, or multiple medications that each treats a specific symptom. In recent years, narcolepsy treatment has changed with the widespread use of modafinil/armodafinil for daytime sleepiness, antidepressants (selective serotonin and dual serotonin and noradrenalin reuptake inhibitors) for cataplexy, and sodium oxybate for both symptoms. Other psychostimulants can also be used, such as methylphenidate, pitolisant and rarely amphetamines, as third-line therapy. Importantly, clinically relevant subjective and objective measures of daytime sleepiness are required to monitor the treatment efficacy and to provide guidance on whether the treatment goals are met. Associated symptoms and comorbid conditions, such as hypnagogic/hypnopompic hallucinations, sleep paralysis, disturbed nighttime sleep, unpleasant dreams, REM- and non REM-related parasomnias, depressive symptoms, overweight/obesity, and obstructive sleep apnea, should also be taken into account and managed, if required. In the near future, the efficacy of new wake-promoting drugs, anticataplectic agents, hypocretin replacement therapy and immunotherapy at the early stages of the disease should also be evaluated.

  13. Perpetual Cancellable American Call Option

    OpenAIRE

    Emmerling, Thomas J.

    2010-01-01

    This paper examines the valuation of a generalized American-style option known as a Game-style call option in an infinite time horizon setting. The specifications of this contract allow the writer to terminate the call option at any point in time for a fixed penalty amount paid directly to the holder. Valuation of a perpetual Game-style put option was addressed by Kyprianou (2004) in a Black-Scholes setting on a non-dividend paying asset. Here, we undertake a similar analysis for the perpetua...

  14. Option price and market instability

    Science.gov (United States)

    Baaquie, Belal E.; Yu, Miao

    2017-04-01

    An option pricing formula, for which the price of an option depends on both the value of the underlying security as well as the velocity of the security, has been proposed in Baaquie and Yang (2014). The FX (foreign exchange) options price was empirically studied in Baaquie et al., (2014), and it was found that the model in general provides an excellent fit for all strike prices with a fixed model parameters-unlike the Black-Scholes option price Hull and White (1987) that requires the empirically determined implied volatility surface to fit the option data. The option price proposed in Baaquie and Cao Yang (2014) did not fit the data during the crisis of 2007-2008. We make a hypothesis that the failure of the option price to fit data is an indication of the market's large deviation from its near equilibrium behavior due to the market's instability. Furthermore, our indicator of market's instability is shown to be more accurate than the option's observed volatility. The market prices of the FX option for various currencies are studied in the light of our hypothesis.

  15. Treatment Option Overview (Myelodysplastic/Myeloproliferative Neoplasms)

    Science.gov (United States)

    ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ... factors affect prognosis (chance of recovery) and treatment options. The prognosis (chance of recovery ) and treatment options ...

  16. Probabilistic methods in exotic option pricing

    NARCIS (Netherlands)

    Anderluh, J.H.M.

    2007-01-01

    The thesis presents three ways of calculating the Parisian option price as an illustration of probabilistic methods in exotic option pricing. Moreover options on commidities are considered and double-sided barrier options in a compound Poisson framework.

  17. Software Defined Network Monitoring Scheme Using Spectral Graph Theory and Phantom Nodes

    Science.gov (United States)

    2014-09-01

    networks is the emergence of software - defined networking ( SDN ) [1]. SDN has existed for the...Chapter III for network monitoring. A. SOFTWARE DEFINED NETWORKS SDNs provide a new and innovative method to simplify network hardware by logically...and R. Giladi, “Performance analysis of software - defined networking ( SDN ),” in Proc. of IEEE 21st International Symposium on Modeling, Analysis

  18. TreeBASIS Feature Descriptor and Its Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Spencer Fowers

    2014-01-01

    Full Text Available This paper presents a novel feature descriptor called TreeBASIS that provides improvements in descriptor size, computation time, matching speed, and accuracy. This new descriptor uses a binary vocabulary tree that is computed using basis dictionary images and a test set of feature region images. To facilitate real-time implementation, a feature region image is binary quantized and the resulting quantized vector is passed into the BASIS vocabulary tree. A Hamming distance is then computed between the feature region image and the effectively descriptive basis dictionary image at a node to determine the branch taken and the path the feature region image takes is saved as a descriptor. The TreeBASIS feature descriptor is an excellent candidate for hardware implementation because of its reduced descriptor size and the fact that descriptors can be created and features matched without the use of floating point operations. The TreeBASIS descriptor is more computationally and space efficient than other descriptors such as BASIS, SIFT, and SURF. Moreover, it can be computed entirely in hardware without the support of a CPU for additional software-based computations. Experimental results and a hardware implementation show that the TreeBASIS descriptor compares well with other descriptors for frame-to-frame homography computation while requiring fewer hardware resources.

  19. Hardware Algorithms For Tile-Based Real-Time Rendering

    NARCIS (Netherlands)

    Crisu, D.

    2012-01-01

    In this dissertation, we present the GRAphics AcceLerator (GRAAL) framework for developing embedded tile-based rasterization hardware for mobile devices, meant to accelerate real-time 3-D graphics (OpenGL compliant) applications. The goal of the framework is a low-cost, low-power, high-performance

  20. Hardware and software techniques for boiler operation and management

    Energy Technology Data Exchange (ETDEWEB)

    Kobayashi, Hiroshi (Hirakawa Iron Works, Ltd., Osaka (Japan))

    1989-04-01

    A study was conducted on the requirements for easy-operable boiler from the view points of hardware and software technologies. Relation among efficiency, energy-saving, and economics, and control of total emission regarding low NOx operation, were explained, with suggestion of orientation to developed necessary hard- and soft- ware for the realization. 8 figs.