WorldWideScience

Sample records for n-type silicon wafers

  1. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    International Nuclear Information System (INIS)

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  2. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  3. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  4. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  5. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  6. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  7. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  8. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  9. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  10. Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

    Science.gov (United States)

    ur Rehman, Atteq; Lee, Soo Hong

    2013-01-01

    The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

  11. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  12. Morphological and optical properties of n-type porous silicon

    Indian Academy of Sciences (India)

    type silicon wafer have been reported in the present article. Method of PS fabrication is by photo-assisted electrochemical etching with different etching current densities ( J ). Porosity and PS layer thickness, obtained by the gravimetric method, ...

  13. Silicon heterojunction solar cells with novel fluorinated n-type nanocrystalline silicon oxide emitters on p-type crystalline silicon

    Science.gov (United States)

    Dhar, Sukanta; Mandal, Sourav; Das, Gourab; Mukhopadhyay, Sumita; Pratim Ray, Partha; Banerjee, Chandan; Barua, Asok Kumar

    2015-08-01

    A novel fluorinated phosphorus doped silicon oxide based nanocrystalline material have been used to prepare heterojunction solar cells on flat p-type crystalline silicon (c-Si) Czochralski (CZ) wafers. The n-type nc-SiO:F:H material were deposited by radio frequency plasma enhanced chemical vapor deposition. Deposited films were characterized in detail by using atomic force microscopy (AFM), high resolution transmission electron microscopy (HRTEM), Raman, fourier transform infrared spectroscopy (FTIR) and optoelectronics properties have been studied using temperature dependent conductivity measurement, Ellipsometry, UV-vis spectrum analysis etc. It is observed that the cell fabricated with fluorinated silicon oxide emitter showing higher initial efficiency (η = 15.64%, Jsc = 32.10 mA/cm2, Voc = 0.630 V, FF = 0.77) for 1 cm2 cell area compare to conventional n-a-Si:H emitter (14.73%) on flat c-Si wafer. These results indicate that n type nc-SiO:F:H material is a promising candidate for heterojunction solar cell on p-type crystalline wafers. The high Jsc value is associated with excellent quantum efficiencies at short wavelengths (<500 nm).

  14. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  15. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  16. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  17. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  18. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  19. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  20. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  1. Profiling N-Type Dopants in Silicon

    Czech Academy of Sciences Publication Activity Database

    Hovorka, Miloš; Mika, Filip; Mikulík, P.; Frank, Luděk

    2010-01-01

    Roč. 51, č. 2 (2010), s. 237-242 ISSN 1345-9678 R&D Projects: GA ČR GP102/09/P543; GA AV ČR IAA100650803 Institutional research plan: CEZ:AV0Z20650511 Keywords : silicon * dopant contrast * photoemission electron microscopy * scanning electron microscopy Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering Impact factor: 0.779, year: 2010 http://www.jim.or.jp/journal/e/51/02/237.html

  2. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  3. Selective etching of n-type silicon in pn junction structure in hydrofluoric acid and its application in silicon nanowire fabrication

    International Nuclear Information System (INIS)

    Wang Huiquan; Jin Zhonghe; Zheng Yangming; Ma Huilian; Wang Yuelin; Li Tie

    2008-01-01

    Boron is selectively implanted on the surface of an n-type silicon wafer to form a p-type area surrounded by an n-type area. The wafer is then put into a buffered oxide etch solution. It is found that the n-type area can be selectively etched without illumination, with an etching rate lower than 1 nm min -1 , while the p-type area can be selectively etched under illumination with a much higher etching rate. The possible mechanism of the etching phenomenon is discussed. A simple fabrication process of silicon nanowires is proposed according to the above phenomenon. In this process only traditional micro-electromechanical system technology is used. Dimensions of the fabricated nanowire can be controlled well. A 50 nm wide and 50 nm thick silicon nanowire has been formed using this method

  4. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  5. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  6. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  7. The Impact of Metallic Impurities on Minority Carrier Lifetime in High Purity N-type Silicon

    Science.gov (United States)

    Yoon, Yohan

    photovoltaics. The detrimental effects and electrical properties of transition-metal impurities, e.g., iron, and its complexes, such as FeB, in p-type silicon are well-known. However, in n-type silicon wafers, although there is evidence of greater tolerance, the impact of specific metallic impurities on minority lifetimes is not as well established. The major contribution of this dissertation is to provide new electrical data relating to metallic impurities in n-type silicon, e.g. activation energy, capture cross sections. The injection-dependent lifetimes of intentionally metal contaminated n-type CZ silicon wafers were investigated using resonant-coupled photoconductance decay (RCPCD) and the quasi-steady-state photoconductance technique (QSSPC). Finally, a direct correlation between minority carrier lifetime and the concentration of specific electrically active metallic impurities was established using DLTS.

  8. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  9. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  10. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  11. Lifetime degradation of n-type Czochralski silicon after hydrogenation

    Science.gov (United States)

    Vaqueiro-Contreras, M.; Markevich, V. P.; Mullins, J.; Halsall, M. P.; Murin, L. I.; Falster, R.; Binns, J.; Coutinho, J.; Peaker, A. R.

    2018-04-01

    Hydrogen plays an important role in the passivation of interface states in silicon-based metal-oxide semiconductor technologies and passivation of surface and interface states in solar silicon. We have shown recently [Vaqueiro-Contreras et al., Phys. Status Solidi RRL 11, 1700133 (2017)] that hydrogenation of n-type silicon slices containing relatively large concentrations of carbon and oxygen impurity atoms {[Cs] ≥ 1 × 1016 cm-3 and [Oi] ≥ 1017 cm-3} can produce a family of C-O-H defects, which act as powerful recombination centres reducing the minority carrier lifetime. In this work, evidence of the silicon's lifetime deterioration after hydrogen injection from SiNx coating, which is widely used in solar cell manufacturing, has been obtained from microwave photoconductance decay measurements. We have characterised the hydrogenation induced deep level defects in n-type Czochralski-grown Si samples through a series of deep level transient spectroscopy (DLTS), minority carrier transient spectroscopy (MCTS), and high-resolution Laplace DLTS/MCTS measurements. It has been found that along with the hydrogen-related hole traps, H1 and H2, in the lower half of the gap reported by us previously, hydrogenation gives rise to two electron traps, E1 and E2, in the upper half of the gap. The activation energies for electron emission from the E1 and E2 trap levels have been determined as 0.12, and 0.14 eV, respectively. We argue that the E1/H1 and E2/H2 pairs of electron/hole traps are related to two energy levels of two complexes, each incorporating carbon, oxygen, and hydrogen atoms. Our results show that the detrimental effect of the C-O-H defects on the minority carrier lifetime in n-type Si:O + C materials can be very significant, and the carbon concentration in Czochralski-grown silicon is a key parameter in the formation of the recombination centers.

  12. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  13. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  14. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  15. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  16. N-type nano-silicon powders with ultra-low electrical resistivity as anode materials in lithium ion batteries

    Science.gov (United States)

    Yue, Zhihao; Zhou, Lang; Jin, Chenxin; Xu, Guojun; Liu, Liekai; Tang, Hao; Li, Xiaomin; Sun, Fugen; Huang, Haibin; Yuan, Jiren

    2017-06-01

    N-type silicon wafers with electrical resistivity of 0.001 Ω cm were ball-milled to powders and part of them was further mechanically crushed by sand-milling to smaller particles of nano-size. Both the sand-milled and ball-milled silicon powders were, respectively, mixed with graphite powder (silicon:graphite = 5:95, weight ratio) as anode materials for lithium ion batteries. Electrochemical measurements, including cycle and rate tests, present that anode using sand-milled silicon powder performed much better. The first discharge capacity of sand-milled silicon anode is 549.7 mAh/g and it is still up to 420.4 mAh/g after 100 cycles. Besides, the D50 of sand-milled silicon powder shows ten times smaller in particle size than that of ball-milled silicon powder, and they are 276 nm and 2.6 μm, respectively. In addition, there exist some amorphous silicon components in the sand-milled silicon powder excepting the multi-crystalline silicon, which is very different from the ball-milled silicon powder made up of multi-crystalline silicon only.

  17. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  18. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  19. Surface Passivation and Antireflection Behavior of ALD on n-Type Silicon for Solar Cells

    Directory of Open Access Journals (Sweden)

    Ing-Song Yu

    2013-01-01

    Full Text Available Atomic layer deposition, a method of excellent step coverage and conformal deposition, was used to deposit TiO2 thin films for the surface passivation and antireflection coating of silicon solar cells. TiO2 thin films deposited at different temperatures (200°C, 300°C, 400°C, and 500°C on FZ n-type silicon wafers are in the thickness of 66.4 nm ± 1.1 nm and in the form of self-limiting growth. For the properties of surface passivation, Si surface is effectively passivated by the 200°C deposition TiO2 thin film. Its effective minority carrier lifetime, measured by the photoconductance decay method, is improved 133% at the injection level of  cm−3. Depending on different deposition parameters and annealing processes, we can control the crystallinity of TiO2 and find low-temperature TiO2 phase (anatase better passivation performance than the high-temperature one (rutile, which is consistent with the results of work function measured by Kelvin probe. In addition, TiO2 thin films on polished Si wafer serve as good ARC layers with refractive index between 2.13 and 2.44 at 632.8 nm. Weighted average reflectance at AM1.5G reduces more than half after the deposition of TiO2. Finally, surface passivation and antireflection properties of TiO2 are stable after the cofire process of conventional crystalline Si solar cells.

  20. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  1. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  2. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  3. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  4. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  5. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  6. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  7. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  8. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  9. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  10. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  11. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  12. Predictable quantum efficient detector based on n-type silicon photodiodes

    Science.gov (United States)

    Dönsberg, Timo; Manoocheri, Farshid; Sildoja, Meelis; Juntunen, Mikko; Savin, Hele; Tuovinen, Esa; Ronkainen, Hannu; Prunnila, Mika; Merimaa, Mikko; Tang, Chi Kwong; Gran, Jarle; Müller, Ingmar; Werner, Lutz; Rougié, Bernard; Pons, Alicia; Smîd, Marek; Gál, Péter; Lolli, Lapo; Brida, Giorgio; Rastello, Maria Luisa; Ikonen, Erkki

    2017-12-01

    The predictable quantum efficient detector (PQED) consists of two custom-made induced junction photodiodes that are mounted in a wedged trap configuration for the reduction of reflectance losses. Until now, all manufactured PQED photodiodes have been based on a structure where a SiO2 layer is thermally grown on top of p-type silicon substrate. In this paper, we present the design, manufacturing, modelling and characterization of a new type of PQED, where the photodiodes have an Al2O3 layer on top of n-type silicon substrate. Atomic layer deposition is used to deposit the layer to the desired thickness. Two sets of photodiodes with varying oxide thicknesses and substrate doping concentrations were fabricated. In order to predict recombination losses of charge carriers, a 3D model of the photodiode was built into Cogenda Genius semiconductor simulation software. It is important to note that a novel experimental method was developed to obtain values for the 3D model parameters. This makes the prediction of the PQED responsivity a completely autonomous process. Detectors were characterized for temperature dependence of dark current, spatial uniformity of responsivity, reflectance, linearity and absolute responsivity at the wavelengths of 488 nm and 532 nm. For both sets of photodiodes, the modelled and measured responsivities were generally in agreement within the measurement and modelling uncertainties of around 100 parts per million (ppm). There is, however, an indication that the modelled internal quantum deficiency may be underestimated by a similar amount. Moreover, the responsivities of the detectors were spatially uniform within 30 ppm peak-to-peak variation. The results obtained in this research indicate that the n-type induced junction photodiode is a very promising alternative to the existing p-type detectors, and thus give additional credibility to the concept of modelled quantum detector serving as a primary standard. Furthermore, the manufacturing of

  13. Study of an Amorphous Silicon Oxide Buffer Layer for p-Type Microcrystalline Silicon Oxide/n-Type Crystalline Silicon Heterojunction Solar Cells and Their Temperature Dependence

    Directory of Open Access Journals (Sweden)

    Taweewat Krajangsang

    2014-01-01

    Full Text Available Intrinsic hydrogenated amorphous silicon oxide (i-a-SiO:H films were used as front and rear buffer layers in crystalline silicon heterojunction (c-Si-HJ solar cells. The surface passivity and effective lifetime of these i-a-SiO:H films on an n-type silicon wafer were improved by increasing the CO2/SiH4 ratios in the films. Using i-a-SiO:H as the front and rear buffer layers in c-Si-HJ solar cells was investigated. The front i-a-SiO:H buffer layer thickness and the CO2/SiH4 ratio influenced the open-circuit voltage (Voc, fill factor (FF, and temperature coefficient (TC of the c-Si-HJ solar cells. The highest total area efficiency obtained was 18.5% (Voc=700 mV, Jsc=33.5 mA/cm2, and FF=0.79. The TC normalized for this c-Si-HJ solar cell efficiency was −0.301%/°C.

  14. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  15. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  16. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Science.gov (United States)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  17. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    International Nuclear Information System (INIS)

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  18. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  19. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Science.gov (United States)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  20. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    International Nuclear Information System (INIS)

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  1. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  2. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  3. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  4. Low-temperature radiation damage in silicon - 1: Annealing studies on N-type material

    International Nuclear Information System (INIS)

    Awadelkarim, O.O.

    1986-07-01

    The presence of electrically active defects in electron-irradiated P-doped n-type silicon was monitored using capacitance and loss factor measurements. Irradiations were performed at temperatures c - 0.14) eV and (E c - 0.24) eV in the gap are ascribed to the carbon interstitial and the divacancy, respectively. (author)

  5. Effects of thermal budget in n-type bifacial solar cell fabrication processes on effective lifetime of crystalline silicon

    Directory of Open Access Journals (Sweden)

    Tomihisa Tachibana

    2017-04-01

    Full Text Available The effects of residual C on cell properties are investigated from the view point of thermal budget in the n-type bifacial cell processes. Implied Voc obtained from wafers with same Oi concentration depend on the thermal budgets decreases as the Cs concentration increases. The Voc values vary depending on the wafer with different growth cooling rate. To analyze the effect of thermal budget correspond to solar cell fabrication process, CZ wafers with almost the same Oi concentrations are prepared. One of the wafers with relatively high residual Cs concentration shows the longer lifetime than the initial value after the 950 oC annealing step. On the other hand, the lifetime of a wafer with relatively low Cs concentration dramatically decreased by the same process due to the O segregation. These results suggest that it is important to choose appropriate wafer specification, starting with feedstock material, for increasing the solar cell efficiency.

  6. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  7. Formation of photoluminescent n-type macroporous silicon: Effect of magnetic field and lateral electric potential

    Energy Technology Data Exchange (ETDEWEB)

    Antunez, E.E. [Centro de Investigación en Ingeniería y Ciencias Aplicadas, UAEM, Av. Universidad 1001, Col. Chamilpa, Cuernavaca, Morelos, CP 62210 (Mexico); Estevez, J.O. [Instituto de Física, B. Universidad Autónoma de Puebla, A.P. J-48, Puebla 72570 (Mexico); Campos, J. [Instituto de Energías Renovables, UNAM, Priv. Xochicalco S/N, Temixco, Morelos, CP 62580 (Mexico); Basurto-Pensado, M.A. [Centro de Investigación en Ingeniería y Ciencias Aplicadas, UAEM, Av. Universidad 1001, Col. Chamilpa, Cuernavaca, Morelos, CP 62210 (Mexico); Agarwal, V., E-mail: vagarwal@uaem.mx [Centro de Investigación en Ingeniería y Ciencias Aplicadas, UAEM, Av. Universidad 1001, Col. Chamilpa, Cuernavaca, Morelos, CP 62210 (Mexico)

    2014-11-15

    Metal electrode-free electrochemical etching of low doped n-type silicon substrates, under the combined effect of magnetic and lateral electric field, is used to fabricate photoluminescent n-type porous silicon structures in dark conditions. A lateral gradient in terms of structural characteristics (i.e. thickness and pore dimensions) along the electric field direction is formed. Enhancement of electric and magnetic field resulted in the increase of pore density and a change in the shape of the macropore structure, from circular to square morphology. Broad photoluminescence (PL) emission from 500 to 800 nm, with a PL peak wavelength ranging from 571 to 642 nm, is attributed to the wide range of microporous features present on the porous silicon layer.

  8. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  9. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Science.gov (United States)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  10. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  11. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  12. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  13. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  14. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Directory of Open Access Journals (Sweden)

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  15. N-type polycrystalline silicon films formed on alumina by aluminium induced crystallization and overdoping

    Energy Technology Data Exchange (ETDEWEB)

    Tuezuen, O. [InESS, UMR 7163 CNRS-ULP, 23 rue du Loess, F-67037 Strasbourg (France)], E-mail: Ozge.Tuzun@iness.c-strasbourg.fr; Slaoui, A. [InESS, UMR 7163 CNRS-ULP, 23 rue du Loess, F-67037 Strasbourg (France); Gordon, I. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Focsa, A. [InESS, UMR 7163 CNRS-ULP, 23 rue du Loess, F-67037 Strasbourg (France); Ballutaud, D. [GEMaC-UMR 8635 CNRS, 1 place Aristide Briand, F-92195 Meudon (France); Beaucarne, G.; Poortmans, J. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium)

    2008-08-30

    In this work, we investigated the formation of n-type polysilicon films on alumina substrates by overdoping a p-type silicon layer obtained by aluminium induced crystallization of amorphous silicon (AIC), and subsequent epitaxy. The phosphorus doping of the AIC was carried out by thermal diffusion from a solid source. The structural quality of the n-type Si film was monitored by optical microscope and scanning electron microscope (SEM). The doping efficiency was determined by resistivity measurements and secondary ion mass spectroscopy (SIMS). The sheet resitivity changed from 2700{omega}/sq to 19.6{omega}/sq after thermal diffusion at 950 deg. C for 1h, indicating the overdoping effect. The SIMS profile carried out after the high temperature epitaxy exhibits a two steps phosphorus distribution, indicating the formation of an n{sup +}n structure.

  16. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  17. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  18. N-Type delta Doping of High-Purity Silicon Imaging Arrays

    Science.gov (United States)

    Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

    2005-01-01

    A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including

  19. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  20. Embedding and electropolymerization of terthiophene derivatives in porous n-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Badeva, Diyana, E-mail: diyana.badeva@cnrs-imn.fr [Equipe Physique des Materiaux et Nanostructures, IMN, B.P. 32229, 44322 Nantes cedex 3 (France); Tran-Van, Francois, E-mail: francois.tran@univ-tours.fr [Laboratoire de Physico-Chimie des Materiaux et des Electrolytes pour l' Energie (PCM2E), E.A 6299, Universite de Tours, Faculte des Sciences et Techniques, Parc de Grandmont, 37200 Tours (France); Beouch, Layla, E-mail: layla.beouch@u-cergy.fr [Laboratoire de Physicochimie des Polymeres et des Interfaces, 5, mail Gay-Lussac, F-95031 Cergy-Pontoise Cedex (France); Chevrot, Claude, E-mail: claude.chevrot@u-cergy.fr [Laboratoire de Physicochimie des Polymeres et des Interfaces, 5, mail Gay-Lussac, F-95031 Cergy-Pontoise Cedex (France); Markova, Ivania, E-mail: vania@uctm.edu [Laboratory of Nanomaterials and Nanotechnologies, University of Chemical Technology and Metallurgy, 8 St. Kliment Ohridski blvd., 1756 Sofia (Bulgaria); Racheva, Todora, E-mail: todora@uctm.edu [Laboratory of Nanomaterials and Nanotechnologies, University of Chemical Technology and Metallurgy, 8 St. Kliment Ohridski blvd., 1756 Sofia (Bulgaria); Froyer, Gerard, E-mail: gerard.froyer@cnrs-imn.fr [Equipe Physique des Materiaux et Nanostructures, IMN, B.P. 32229, 44322 Nantes cedex 3 (France)

    2012-04-16

    Highlights: Black-Right-Pointing-Pointer Development of a mesoporous silicon with special morphological and chemical properties. Black-Right-Pointing-Pointer Successful embedding of carboxylic-acid terthiophenic monomer in porous silicon. Black-Right-Pointing-Pointer In situ electrochemical polymerization. Black-Right-Pointing-Pointer Polarized IRTF scattering provides the tendency to preferential organization. - Abstract: A mesoporous n-type silicon/poly (3 Prime -acetic acid-2,2 Prime -5 Prime ,2 Prime Prime terthiophene)-(Poly (3TAA) nanocomposite was elaborated in order to realize new components for optoelectronics. Non-oxidized and oxidized porous silicon substrates is used and their physical and chemical properties have been studied by different techniques such as transmission electron microscopy (TEM), scanning electron microscopy (SEM) and Fourier transformed infrared spectroscopy (FTIR). Terthiophene based conjugated structure has been successfully incorporated inside the pores by capillarity at the melting temperature of the monomer. The filling of the monomer into the porous volume was probed by energy dispersive X-ray spectroscopy (EDX). Polarized infrared absorption spectroscopy results indicated that the monomer molecules show preferential orientation along the pore axis, due to hydrogen bonding, in particular that of the carboxylic groups with silanol-rich oxidized porous silicon surface. The 3TAA monomer molecules embedded in porous silicon matrix were electrochemically polymerized in situ and resonance Raman scattering spectroscopy proved the above-mentioned polymerization.

  1. DEPTH MEASUREMENT OF DISRUPTED LAYER ON SILICON WAFER SURFACE USING AUGER SPECTROSCOPY METHOD

    Directory of Open Access Journals (Sweden)

    V. A. Solodukha

    2016-01-01

    Full Text Available The paper proposes a method for depth measurement of a disrupted layer on silicon wafer surface which is based on application of Auger spectroscopy with the precision sputtering of surface silicon layers and registration of the Auger electron yield intensity. In order to measure the disrupted layer with the help of Auger spectroscopy it is necessary to determine dependence of the released Auger electron amount on sputtering time (profile and then the dependence is analyzed. Silicon amount in the disrupted layer is less than in the volume. While going deeper the disruptive layer is decreasing that corresponds to an increase of atom density in a single layer. The essence of the method lies in the fact the disruptive layer is removed by ion beam sputtering and detection of interface region is carried out with the help of registration of the Auger electron yield intensity from the sputtered surface up to the moment when it reaches the value which is equal to the Auger electron yield intensity for single-crystal silicon. While removing surface silicon layers the registration of the Auger electron yield intensity from silicon surface makes it possible to control efficiently a presence of the disrupted layer on the silicon wafer surface. In this case depth control locality is about 1.0 nm due to some peculiarities of Auger spectroscopy method. The Auger electron yield intensity is determined automatically while using Auger spectrometer and while removing the disrupted layer the intensity is gradually increasing. Depth of the disrupted layer is determined by measuring height of the step which has been formed as a result of removal of the disrupted layer from the silicon wafer surface. Auger spectroscopy methods ensures an efficient depth control surface disruptions at the manufacturing stages of silicon wafers and integrated circuits. The depth measurement range of disruptions constitutes 0.001–1.000 um.

  2. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  3. Progress in low-cost n-type silicon solar cell technology

    Energy Technology Data Exchange (ETDEWEB)

    Geerligs, L.J.; Romijn, G.; Burgers, A.R.; Guillevin, N.; Weeber, A.W.; Bultman, J.H. [ECN Solar Energy, Petten (Netherlands); Wang, Hongfang; Lang, Fang; Zhao, Wenchao; Li, Gaofei; Hu, Zhiyan; Xiong, Jingfeng [Yingli Green Energy Holding Co., LTD, Baoding (China); Vlooswijk, A. [Tempress Systems, Vaassen (Netherlands)

    2012-06-15

    This article will review our recent progress in development of high-efficiency cells on n-type monocrystalline Si wafers. With boron-doped front emitter, phosphorous BSF, and screen-printed metallisation, at this moment such cells reach an efficiency of over 19%. We describe recent results of processing with reduced front contact area, and improved BSF and improved rear surface passivation, which are key parameters that limit the cell efficiency. The improved processing leads to an efficiency of 20%. The cell process has also been adopted for fabrication of metal-wrap-through back-contact cells. Without the improved contact recombination and BSF, an MWT cell efficiency of 19.7% is reached, 0.3% higher than the corresponding 'standard' (non-back-contact) cells.

  4. Radiation Effects of n-type, Low Resistivity, Spiral Silicon Drift Detector Hybrid Systems

    International Nuclear Information System (INIS)

    Chen, W.; De Geronimo, G.; Carini, G.A.; Gaskin, J.A.; Keister, J.W.; Li, S.; Li, Z.; Ramsey, B.D.; Siddons, D.P.; Smith, G.C.; Verbitskaya, E.

    2011-01-01

    We have developed a new thin-window, n-type, low-resistivity, spiral silicon drift detector (SDD) array - to be used as an extraterrestrial X-ray spectrometer (in varying environments) for NASA. To achieve low-energy response, a thin SDD entrance window was produced using a previously developed method. These thin-window devices were also produced on lower resistivity, thinner, n-type, silicon material, effectively ensuring their radiation hardness in anticipation of operation in potentially harsh radiation environments (such as found around the Jupiter system). Using the Indiana University Cyclotron Facility beam line RERS1, we irradiated a set of suitable diodes up to 5 Mrad and the latest iteration of our ASICs up to 12 Mrad. Then we irradiated two hybrid detectors consisting of newly, such-produced in-house (BNL) SDD chips bonded with ASICs with doses of 0.25 Mrad and 1 Mrad. Also we irradiated another hybrid detector consisting of previously produced (by KETEK) on n-type, high-resistivity SDD chip bonded with BNL's ASICs with a dose of 1 Mrad. The measurement results of radiated diodes (up to 5 Mrad), ASICs (up to 12 Mrad) and hybrid detectors (up to 1 Mrad) are presented here.

  5. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Science.gov (United States)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  6. Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

    Science.gov (United States)

    Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

    2018-05-01

    Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

  7. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  8. Growth of misfit dislocation-free p/p+ thick epitaxial silicon wafers on Ge-B-codoped substrates

    International Nuclear Information System (INIS)

    Jiang Huihua; Yang Deren; Ma Xiangyang; Tian Daxi; Li Liben; Que Duanlin

    2006-01-01

    The growth of p/p + silicon epitaxial silicon wafers (epi-wafers) without misfit dislocations has been successfully achieved by using heavily boron-doped Czochralski (CZ) silicon wafers codoped with desirable level of germanium as the substrates. The lattice compensation by codoping of germanium and boron into the silicon matrix to reduce the lattice mismatch between the substrate (heavily boron-doped) and epi-layer (lightly boron-doped) is the basic idea underlying in the present achievement. In principle, the codoping of germanium and boron in the CZ silicon can be tailored to achieve misfit dislocation-free epi-layer with required thickness. It is reasonably expected that the presented solution to elimination of misfit dislocations in the p/p + silicon wafers can be applied in the volume production

  9. Porosity dependence of positive magnetoconductance in n-type porous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Chouaibi, Bassem; Radaoui, Moufid; Benfredj, Amel; Bouchriha, Habib [Laboratoire Materiaux Avances et Phenomenes Quantiques, Faculte des Sciences de Tunis, Universite El Manar, 2092 Campus universitaire, Tunis (Tunisia); Romdhane, Samir [Laboratoire Materiaux Avances et Phenomenes Quantiques, Faculte des Sciences de Tunis, Universite El Manar, 2092 Campus universitaire, Tunis (Tunisia); Faculte des Sciences de Bizerte, 7021 Zarzouna, Bizerte, Universite de Carthage (Tunisia); Bouaicha, Mongi [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, BP 95, Hammam-Lif 2050 (Tunisia)

    2012-10-15

    Positive magnetoconductance (MC) on n-type porous silicon (PS) based devices was observed at room temperature for low static magnetic field (under 6000 G). We found that the measured MC decreases when the film porosity is increased. Obtained results were analyzed by means of the quasi-1D weak localization (WL) theory. From the dependence of the MC vs. applied magnetic field, we determine the phase coherence length L{sup {phi}}. Good agreement between theoretical and experimental results was found (copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  10. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  11. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  12. Fabrication of silicon condenser microphones using single wafer technology

    NARCIS (Netherlands)

    Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

    1992-01-01

    A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

  13. Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

    Science.gov (United States)

    Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

    1986-01-01

    The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

  14. Micro-spectroscopy on silicon wafers and solar cells

    Directory of Open Access Journals (Sweden)

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  15. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  16. External self-gettering of nickel in float zone silicon wafers

    Science.gov (United States)

    Gay, N.; Martinuzzi, S.

    1997-05-01

    During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

  17. Spin relaxation through lateral spin transport in heavily doped n -type silicon

    Science.gov (United States)

    Ishikawa, M.; Oka, T.; Fujita, Y.; Sugiyama, H.; Saito, Y.; Hamaya, K.

    2017-03-01

    We experimentally study temperature-dependent spin relaxation including lateral spin diffusion in heavily doped n -type silicon (n+-Si ) layers by measuring nonlocal magnetoresistance in small-sized CoFe/MgO/Si lateral spin-valve (LSV) devices. Even at room temperature, we observe large spin signals, 50-fold the magnitude of those in previous works on n+-Si . By measuring spin signals in LSVs with various center-to-center distances between contacts, we reliably evaluate the temperature-dependent spin diffusion length (λSi) and spin lifetime (τSi). We find that the temperature dependence of τSi is affected by that of the diffusion constant in the n+-Si layers, meaning that it is important to understand the temperature dependence of the channel mobility. A possible origin of the temperature dependence of τSi is discussed in terms of the recent theories by Dery and co-workers.

  18. Terahertz optical-Hall effect for multiple valley band materials: n-type silicon

    International Nuclear Information System (INIS)

    Kuehne, P.; Hofmann, T.; Herzinger, C.M.; Schubert, M.

    2011-01-01

    The optical-Hall effect comprises generalized ellipsometry at long wavelengths on samples with free-charge carriers placed within external magnetic fields. Measurement of the anisotropic magneto-optic response allows for the determination of the free-charge carrier properties including spatial anisotropy. In this work we employ the optical-Hall effect at terahertz frequencies for analysis of free-charge carrier properties in multiple valley band materials, for which the optical free-charge carrier contributions originate from multiple Brillouin-zone conduction or valence band minima or maxima, respectively. We investigate exemplarily the room temperature optical-Hall effect in low phosphorous-doped n-type silicon where free electrons are located in six equivalent conduction-band minima near the X-point. We simultaneously determine their free-charge carrier concentration, mobility, and longitudinal and transverse effective mass parameters.

  19. Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

    Science.gov (United States)

    Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

    2018-06-01

    Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

  20. An attempt to specify thermal history in CZ silicon wafers and possibilities for its modification

    International Nuclear Information System (INIS)

    Kissinger, G.; Sattler, A.; Mueller, T.; Ammon, W. von

    2007-01-01

    The term thermal history of silicon wafers represents the whole variety of process parameters of crystal growth. The aim of this contribution is an attempt to specify thermal history by one parameter that is directly correlated to the bulk microdefect density. The parameter that reflects thermal history and correlates it with nucleation of oxide precipitates is the concentration of VO 2 complexes. The VO 2 concentration in silicon wafers is too low to be measured by FTIR but it can be obtained from the loss of interstitial oxygen during a standardized thermal treatment. Based on this, the vacancy concentration frozen during crystal cooling in the ingot can be calculated. RTA treatments above 1150 deg. C create a well defined level of the VO 2 concentration in silicon wafers. This means that a well controlled modification of the thermal history is possible. We also investigated the kinetics of reduction of the as-grown excess VO 2 concentration during RTA treatments at 950 deg. C and 1050 deg. C and the effectiveness of this attempt to totally delete the thermal history

  1. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Science.gov (United States)

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  2. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  3. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  4. Non-axisymmetric flexural vibrations of free-edge circular silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Dmitriev, A.V., E-mail: dmitriev@hbar.phys.msu.ru; Gritsenko, D.S.; Mitrofanov, V.P., E-mail: mitr@hbar.phys.msu.ru

    2014-02-07

    Non-axisymmetric flexural vibrations of circular silicon (111) wafers are investigated. The modes with azimuthal index 2⩽k⩽30 are electrostatically excited and monitored by a capacitive sensor. The splitting of the mode frequencies associated with imperfection of the wafer is observed. The measured loss factors for the modes with 6≲k≲26 are close to those calculated according to the thermoelastic damping theory, while clamping losses likely dominate for k≲6, and surface losses at the level of inverse Q-factor Q{sup −1}≈4×10{sup −6} prevail for the modes with large k. The modes demonstrate nonlinear behavior of mainly geometrical origin at large amplitudes.

  5. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Directory of Open Access Journals (Sweden)

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  6. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    International Nuclear Information System (INIS)

    Vega, M; Lasorsa, C; Lerner, B; Perez, M; Granell, P

    2016-01-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production. (paper)

  7. Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

    Science.gov (United States)

    Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

    2016-02-01

    In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

  8. Eutectic and solid-state wafer bonding of silicon with gold

    International Nuclear Information System (INIS)

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  9. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    International Nuclear Information System (INIS)

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  10. Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications

    International Nuclear Information System (INIS)

    Ngo, H-D; Hiess, Andre; Seidemann, Volker; Studzinski, Daniel; Lange, Martin; Leib, Juergen; Shariff, Dzafir; Ashraf, Huma; Steel, Mike; Atabo, Lilian; Reast, Jon

    2006-01-01

    This paper is a brief report of plasma etching as applied to pattern transfer in silicon. It will focus more on concept overview and strategies for etching of tapered features of interest for MEMS and Wafer Level Packaging (WLP). The basis of plasma etching, the dry etching technique, is explained and plasma configurations are described elsewhere. An important feature of plasma etching is the possibility to achieve etch anisotropy. The plasma etch process is extremely sensitive to many variables such as mask material, mask openings and more important the plasma parameters

  11. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  12. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Directory of Open Access Journals (Sweden)

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  13. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  14. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  15. Electronic properties and morphology of copper oxide/n-type silicon heterostructures

    Science.gov (United States)

    Lindberg, P. F.; Gorantla, S. M.; Gunnæs, A. E.; Svensson, B. G.; Monakhov, E. V.

    2017-08-01

    Silicon-based tandem heterojunction solar cells utilizing cuprous oxide (Cu2O) as the top absorber layer show promise for high-efficiency conversion and low production cost. In the present study, single phase Cu2O films have been realized on n-type Si substrates by reactive magnetron sputtering at 400 °C. The obtained Cu2O/Si heterostructures have subsequently been heat treated at temperatures in the 400-700 °C range in Ar flow and extensively characterized by x-ray diffraction (XRD) measurements, transmission electron microscopy (TEM) imaging and electrical techniques. The Cu2O/Si heterojunction exhibits a current rectification of ~5 orders of magnitude between forward and reverse bias voltages. High resolution cross-sectional TEM-images show the presence of a ~2 nm thick interfacial SiO2 layer between Cu2O and the Si substrate. Heat treatments below 550 °C result in gradual improvement of crystallinity, indicated by XRD. At and above 550 °C, partial phase transition to cupric oxide (CuO) occurs followed by a complete transition at 700 °C. No increase or decrease of the SiO2 layer is observed after the heat treatment at 550 °C. Finally, a thin Cu-silicide layer (Cu3Si) emerges below the SiO2 layer upon annealing at 550 °C. This silicide layer influences the lateral current and voltage distributions, as evidenced by an increasing effective area of the heterojunction diodes.

  16. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  17. Process induced sub-surface damage in mechanically ground silicon wafers

    International Nuclear Information System (INIS)

    Yang Yu; De Munck, Koen; Teixeira, Ricardo Cotrin; Swinnen, Bart; De Wolf, Ingrid; Verlinden, Bert

    2008-01-01

    Micro-Raman spectroscopy, scanning electron microcopy, atomic force microscopy and preferential etching were used to characterize the sub-surface damage induced by the rough and fine grinding steps used to make ultra-thin silicon wafers. The roughly and ultra-finely ground silicon wafers were examined on both the machined (1 0 0) planes and the cross-sectional (1 1 0) planes. They reveal similar multi-layer damage structures, consisting of amorphous, plastically deformed and elastically stressed layers. However, the thickness of each layer in the roughly ground sample is much higher than its counterpart layers in the ultra-finely ground sample. The residual stress after rough and ultra-fine grinding is in the range of several hundreds MPa and 30 MPa, respectively. In each case, the top amorphous layer is believed to be the result of sequential phase transformations (Si-I to Si-II to amorphous Si). These phase transformations correspond to a ductile grinding mechanism, which is dominating in ultra-fine grinding. On the other hand, in rough grinding, a mixed mechanism of ductile and brittle grinding causes multi-layer damage and sub-surface cracks

  18. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  19. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.; Kutbee, Arwa T.; Khan, Sherjeel M.; Sepulveda, Adrian C.; Wicaksono, Irmandy; Nour, Maha A.; Wehbe, Nimer; Almislem, Amani Saleh Saad; Ghoneim, Mohamed T.; Sevilla, Galo T.; Syed, Ahad; Shaikh, Sohail F.; Hussain, Muhammad Mustafa

    2018-01-01

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  20. Formation of hydrogen-related traps in electron-irradiated n-type silicon by wet chemical etching

    International Nuclear Information System (INIS)

    Tokuda, Yutaka; Shimada, Hitoshi

    1998-01-01

    Interaction of hydrogen atoms and vacancy-related defects in 10 MeV electron-irradiated n-type silicon has been studied by deep-level transient spectroscopy. Hydrogen has been incorporated into electron-irradiated n-type silicon by wet chemical etching. The reduction of the concentration of the vacancy-oxygen pair and divacancy occurs by the incorporation of hydrogen, while the formation of the NH1 electron trap (E c - 0.31 eV) is observed. Further decrease of the concentration of the vacancy-oxygen pair and further increase of the concentration of the NH1 trap are observed upon subsequent below-band-gap light illumination. It is suggested that the trap NH1 is tentatively ascribed to the vacancy-oxygen pair which is partly saturated with hydrogen

  1. A kinetic formulation of piezoresistance in N-type silicon: Application to non-linear effects

    Science.gov (United States)

    Charbonnieras, A. R.; Tellier, C. R.

    1999-07-01

    This paper is devoted to the theoretical study of the influence of the temperature and of the doping on the piezoresistance of N-type silicon. In the first step the fractional change in the resistivity caused by stresses is calculated in the framework of a multivalley model using a kinetic transport formulation based on the Boltzmann transport equation. In the second step shifts in the minima of the conduction band and the resulting shift of the Fermi level are expressed in terms of deformation potentials and of stresses. General expressions for the fundamental linear, π_{11} and π_{12}, and non-linear, π_{111}, π_{112}, π_{122} and π_{123}, piezoresistance coefficients are then derived. Plots of the non-linear piezoresistance coefficients against the reduced shift of the Fermi level or against temperature allow us to characterize the influence of doping and temperature. Finally some attempts are made to estimate the non-linearity for heavily doped semiconductor gauges. Cette publication est consacrée à l'étude théorique de l'influence de la température et du dopage sur la piezorésistivité du silicium type N. Dans une première étape nous adoptons le modèle de vallées et nous utilisons une formulation cinétique du transport électronique faisant appel à l'équation de transport de Boltzmann pour calculer la variation de la résistivité du semiconducteur sous contrainte. Dans la deuxième étape nous exprimons les déplacements des minima de la bande de conduction et du niveau de Fermi en termes de potentiels de déformation et de contraintes. Nous proposons ensuite des expressions générales pour les coefficients piezorésistifs fondamentaux linéaires, π_{11} et π_{12}, et non-linéaires, π_{111}, π_{112}, π_{122} et π_{123}. Des représentations graphiques des variations des coefficients non-linéaires permettent de caractériser l'influence du dopage et de la température. Enfin nous fournissons une première pré-estimation des effets

  2. Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

    Science.gov (United States)

    Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

    This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

  3. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  4. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    CERN Document Server

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  5. Effect of Processing Parameters on Thickness of Columnar Structured Silicon Wafers Directly Grown from Silicon Melts

    Directory of Open Access Journals (Sweden)

    Jin-Seok Lee

    2012-01-01

    Full Text Available In order to obtain optimum growth conditions for desired thickness and more effective silicon feedstock usage, effects of processing parameters such as preheated substrate temperatures, time intervals, moving velocity of substrates, and Ar gas blowing rates on silicon ribbon thickness were investigated in the horizontal growth process. Most of the parameters strongly affected in the control of ribbon thickness with columnar grain structure depended on the solidification rate. The thickness of the silicon ribbon decreased with an increasing substrate temperature, decreasing time interval, and increasing moving velocity of the substrate. However, the blowing of Ar gas onto a liquid layer existing on the surface of solidified ribbon contributed to achieving smooth surface roughness but did not closely affect the change of ribbon thickness in the case of a blowing rate of ≥0.65 Nm3/h because the thickness of the solidified layer was already determined by the exit height of the reservoir.

  6. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    International Nuclear Information System (INIS)

    Mou, Chun-Yueh; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-01-01

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate

  7. Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

    Science.gov (United States)

    Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

    2014-07-21

    Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

  8. Preparation and characterization of ultra-thin amphiphobic coatings on silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mou, Chun-Yueh, E-mail: cymou165@gmail.com; Yuan, Wei-Li; Shih, Chih-Hsin

    2013-06-30

    Fluorine-based amphiphobic coatings have been widely used in commercial domestic utensils and textiles to repel water and oil contaminants. However, few reports from the literature survey have discussed the effects on amphiphobicity of the nano- to micro-scale surface features of such a coating. In this research thin amphiphobic epoxy coatings based on a mixture of bisphenol A diglycidyl ether, tetraethylorthosilicate (TEOS), and a particular alkoxy silane with fluorinated side chains (F-silane) are deposited on silicon wafers. Film amphiphobicity is characterized by the measurement of water and oil contact angles of the coating. Film morphology is revealed in the scanned images using atomic force microscopy. The deposited films free of F-silane are about 10 nm thick. When a small amount of F-silane was firstly added, the water and oil contact angles of the deposited films jumped up to 107° and 69° respectively and then flattened out with increased F-silane. Water droplets gave an average plateau contact angle about 110°, while vegetable oil ones, 40°. It was noted that there is a dramatic decrease in the lyophobicity causing a reduction in contact angles. However, surface lyophobicity also depends on sub-microscopic surface structures. In addition, by increasing TEOS, it was shown that the formed silica sols or granules were helpful in enhancing the mechanical strength along with retaining the lyophobicity of the film. - Highlights: • Epoxy ultrathin films about 10 nm thick deposited on silicon wafer. • Nominal fluorinated silane added to epoxy coatings for amphiphobicity. • Surface lyophobicity retained by sub-micrometer granules in ultrathin coatings. • Film hardness improved by adding tetraethylorthosilicate.

  9. Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

    Science.gov (United States)

    Wang, Shing-Dar; Chen, Ting-Wei

    2018-06-01

    In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

  10. Analysis of borophosphosilicate glass layers on silicon wafers by X-ray emission from photon and electron excitation

    International Nuclear Information System (INIS)

    Elgersma, O.; Borstrok, J.J.M.

    1989-01-01

    Phosphorus and oxygen concentrations in the homogeneous layer of borosilicate glass (BPSG) deposited on Si-integrated circuits are determined by X-ray fluorescence from photon excitation. The X-ray emission from electron excitation in an open X-ray tube instrument yields a sufficiently precise determination of the boron content. The thickness of the layer can be derived from silicon Kα-fluorescence. A calibration model is proposed for photon as well as for electron excitation. The experimentally determined parameters in this model well agree with those derived from fundamental parameters for X-ray absorption and emission. The chemical surrounding of silicon affects strongly the peak profile of the silicon Kβ-emission. This enables to distinguish emission from the silicon atoms in the wafer and from the silicon atoms in the silicon oxide complexes of the BPSG-layer. (author)

  11. Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

    International Nuclear Information System (INIS)

    Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

    2016-01-01

    It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

  12. Electrodeposition of cadmium on n-type silicon single crystals of ...

    African Journals Online (AJOL)

    sea

    type silicon have been studied as a function of different potential steps. Within appropriate potential ... including progressive nucleation on active sites and diffusion controlled cluster growth. ..... al CdSe nanocrystals on {111} gold. Surf. Sci.

  13. Photon-Enhanced Thermionic Emission in Cesiated p-Type and n-Type Silicon

    DEFF Research Database (Denmark)

    Reck, Kasper; Dionigi, Fabio; Hansen, Ole

    2014-01-01

    electrons. Efficiencies above 60% have been predicted theoretically for high solar concentration systems. Silicon is an interesting absorber material for high efficiency PETE solar cells, partly due to its mechanical and thermal properties and partly due to its electrical properties, including a close......Photon-enhanced thermionic emission (PETE) is a relatively new concept for high efficiency solar cells that utilize not only the energy of electrons excited across the band gap by photons, as in conventional photovoltaic solar cells, but also the energy usual lost to thermalization of the excited...... to ideal band gap. The work function of silicon is, however, too high for practical PETE implementations. A well-known method for lowering the work function of silicon (and other materials) is to apply approximately a monolayer of cesium to the silicon surface. We present the first measurements of PETE...

  14. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  15. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    International Nuclear Information System (INIS)

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  16. Reliability assessment of ultra-thin HfO{sub 2} films deposited on silicon wafer

    Energy Technology Data Exchange (ETDEWEB)

    Fu, Wei-En [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Chang, Chia-Wei [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Chang, Yong-Qing [Center for Measurement Standards, Industrial Technology Research Institute, Room 216, Building 8, 321 Kuang Fu Road Sec. 2, Hsinchu, Taiwan (China); Yao, Chih-Kai [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China); Liao, Jiunn-Der, E-mail: jdliao@mail.ncku.edu.tw [Department of Materials Science and Engineering, National Cheng Kung University, 1 University Road, Tainan 70101, Taiwan (China)

    2012-09-01

    Highlights: Black-Right-Pointing-Pointer Nano-mechanical properties on annealed ultra-thin HfO{sub 2} film are studied. Black-Right-Pointing-Pointer By AFM analysis, hardness of the crystallized HfO{sub 2} film significantly increases. Black-Right-Pointing-Pointer By nano-indention, the film hardness increases with less contact stiffness. Black-Right-Pointing-Pointer Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO{sub 2}) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO{sub 2} films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO{sub 2} films deposited on silicon wafers (HfO{sub 2}/SiO{sub 2}/Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO{sub 2} (nominal thickness Almost-Equal-To 10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO{sub 2} phases for the atomic layer deposited HfO{sub 2}. The HfSi{sub x}O{sub y} complex formed at the interface between HfO{sub 2} and SiO{sub 2}/Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO{sub 2} film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically

  17. Nanostructure Size Determination in N+-Type Porous Silicon by X-Ray diffractometry and Raman Spectroscopy

    International Nuclear Information System (INIS)

    Ramirez Porras, A.

    1997-01-01

    A series of porous silicon surfaces were obtained after different exposition times of electrochemical etching on cristalline n+- type silicon in presence of hydrofluoric acid. These kind of surfaces show photoluminescence when illuminated by UV light. One possible explanation for this is that the treated surface is made up of small crystallites the nanometer scale that split away the semiconductor band edges up to optical photon energies for the band- to -band recombination processes. In this study, a nanometer size determination of such proposed structures was performed by the use of X-Ray Diffractometry and Raman Spectroscopy. The result suggest the consistency between the so called Quantum Confined Model and the experimental results. (Author) [es

  18. Nanostructure Size Determination in N+-Type Porous Silicon by X-Ray diffractometry and Raman Spectroscopy

    CERN Document Server

    Ramirez-Porras, A

    1997-01-01

    A series of porous silicon surfaces were obtained after different exposition times of electrochemical etching on cristalline n+- type silicon in presence of hydrofluoric acid. These kind of surfaces show photoluminescence when illuminated by UV light. One possible explanation for this is that the treated surface is made up of small crystallites the nanometer scale that split away the semiconductor band edges up to optical photon energies for the band- to -band recombination processes. In this study, a nanometer size determination of such proposed structures was performed by the use of X-Ray Diffractometry and Raman Spectroscopy. The result suggest the consistency between the so called Quantum Confined Model and the experimental results. (Author)

  19. Capacity spectroscopy of minority-carrier radiation traps in n-type silicon

    International Nuclear Information System (INIS)

    Kuchinskij, P.V.; Lomako, V.M.; Shakhlevich, L.N.

    1987-01-01

    Minority charge-carrier radiation traps in n-silicon, produced by neutron transmutation doping (NTD) and zone melting method, were studied using unsteady capacity spectroscopy method. Studying the parameters of defects, formed in the lower half of the restricted zone, was performed using minority carrier injection by forward current pulses. Samples were p + -n-structures, produced on the basis of silicon with different oxygen content. It is shown, that a trap with activation energy ≅E v +0.34 eV appears to be the main defect in oxygen p-silicon. Investigation into thermal stability has shown, that centers with E v +0.34 eV and E v +0.27 eV activation energies are annealed within the same temperature interval (300-400 deg C)

  20. Comparison of slowness profiles of lamb wave with elastic moduli and crystal structure in single crystalline silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Min, Young Jae; Yun, Gyeong Won; Kim, Kyung Min; Roh, Yuji; Kim, Young H. [Applied Acoustics Lab, Korea Science Academy of KAIST, Busan (Korea, Republic of)

    2016-02-15

    Single crystalline silicon wafers having (100), (110), and (111) directions are employed as specimens for obtaining slowness profiles. Leaky Lamb waves (LLW) from immersed wafers were detected by varying the incident angles of the specimens and rotating the specimens. From an analysis of LLW signals for different propagation directions and phase velocities of each specimen, slowness profiles were obtained, which showed a unique symmetry with different symmetric axes. Slowness profiles were compared with elastic moduli of each wafer. They showed the same symmetries as crystal structures. In addition, slowness profiles showed expected patterns and values that can be inferred from elastic moduli. This implies that slowness profiles can be used to examine crystal structures of anisotropic solids.

  1. The effect of hydrogen on the morphology of n-type silicon electrodes under electrochemical conditions

    DEFF Research Database (Denmark)

    Goldar, A.; Roser, S.J.; Caruana, D.

    2001-01-01

    the changes in the shape of the total reflection feature. We assume that the change in the morphology of the surface is due to the diffusion of hydrogen in the silicon electrode. This assumption allow us to model the changes in the reflected intensity at two different angles and find the diffusion exponent...

  2. Morphological and optical properties of n-type porous silicon: effect ...

    Indian Academy of Sciences (India)

    Method of PS fabrication is by photo-assisted electrochemical etching with different etching current densities ... Observation of room temperature visible photoluminescence (PL) [4,5] in PS has ... are pre-treated with HF and ethanol in an ultrasonic bath for 5 min to remove any native oxide present on the silicon surface [16].

  3. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  4. Quantitative analysis of phosphosilicate glass films on silicon wafers for calibration of x-ray fluorescence spectrometry standards

    International Nuclear Information System (INIS)

    Weissman, S.H.

    1983-01-01

    The phosphorus and silicon contents of phosphosilicate glass films deposited by chemical vapor deposition (CVD) on silicon wafers were determined. These films were prepared for use as x-ray fluorescence (XRF) spectrometry standards. The thin films were removed from the wafer by etching with dilute hydrofluoric acid, and the P and Si concentrations in solution were determined by inductively coupled plasma atomic emission spectroscopy (ICP). The calculated phosphorus concentration ranged from 2.2 to 12 wt %, with an uncertainty of 2.73 to 10.1 relative percent. Variation between the calculated weight loss (summation of P 2 O 5 and SiO 2 amounts as determined by ICP) and the measured weight loss (determined gravimetrically) averaged 4.9%. Results from the ICP method, Fourier transform-infrared spectroscopy (FT-IR), dispersive infrared spectroscopy, electron microprobe, and x-ray fluorescence spectroscopy for the same samples are compared

  5. Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

    Science.gov (United States)

    Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

    2013-05-06

    Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

  6. Femtosecond versus nanosecond laser machining: comparison of induced stresses and structural changes in silicon wafers

    International Nuclear Information System (INIS)

    Amer, M.S.; El-Ashry, M.A.; Dosser, L.R.; Hix, K.E.; Maguire, J.F.; Irwin, Bryan

    2005-01-01

    Laser micromachining has proven to be a very successful tool for precision machining and microfabrication with applications in microelectronics, MEMS, medical device, aerospace, biomedical, and defense applications. Femtosecond (FS) laser micromachining is usually thought to be of minimal heat-affected zone (HAZ) local to the micromachined feature. The assumption of reduced HAZ is attributed to the absence of direct coupling of the laser energy into the thermal modes of the material during irradiation. However, a substantial HAZ is thought to exist when machining with lasers having pulse durations in the nanosecond (NS) regime. In this paper, we compare the results of micromachining a single crystal silicon wafer using a 150-femtosecond and a 30-nanosecond lasers. Induced stress and amorphization of the silicon single crystal were monitored using micro-Raman spectroscopy as a function of the fluence and pulse duration of the incident laser. The onset of average induced stress occurs at lower fluence when machining with the femtosecond pulse laser. Induced stresses were found to maximize at fluence of 44 J cm -2 and 8 J cm -2 for nanosecond and femtosecond pulsed lasers, respectively. In both laser pulse regimes, a maximum induced stress is observed at which point the induced stress begins to decrease as the fluence is increased. The maximum induced stress was comparable at 2.0 GPa and 1.5 GPa for the two lasers. For the nanosecond pulse laser, the induced amorphization reached a plateau of approximately 20% for fluence exceeding 22 J cm -2 . For the femtosecond pulse laser, however, induced amorphization was approximately 17% independent of the laser fluence within the experimental range. These two values can be considered nominally the same within experimental error. For femtosecond laser machining, some effect of the laser polarization on the amount of induced stress and amorphization was also observed

  7. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  8. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  9. Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

    Science.gov (United States)

    Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

    2017-09-01

    SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

  10. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  11. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  12. Tin-vacancy acceptor levels in electron-irradiated n-type silicon

    DEFF Research Database (Denmark)

    Larsen, A. Nylandsted; Goubet, J. J.; Mejlholm, P.

    2000-01-01

    Si crystals (n-type, fz) with doping levels between 1.5x10(14) and 2x10(16)cm(-3) containing in addition similar to 10(18) Sn/cm(3) were irradiated with 2-MeV electrons to different doses and subsequently studied by deep level transient spectroscopy, Mossbauer spectroscopy, and positron...... annihilation. Two tin-vacancy (Sn-V) levels at E-c - 0.214 eV and E-c - 0.501 eV have been identified (E-c denotes the conduction band edge). Based on investigations of the temperature dependence of the electron-capture cross sections, the electric-field dependence of the electron emissivity, the anneal...... temperature, and the defect-introduction rate, it is concluded that these levels are the double and single acceptor levels, respectively, of the Sn-V pair. These conclusions are in agreement with electronic structure calculations carried out using a local spin-density functional theory, incorporating...

  13. The annealing of interstitial carbon atoms in high-resistivity n-type silicon after proton irradiation

    CERN Document Server

    Kuhnke, M; Lindström, G

    2002-01-01

    The annealing of interstitial carbon C sub i after 7-10 MeV and 23 GeV proton irradiations at room temperature in high-resistivity n-type silicon is investigated. Deep level transient spectroscopy is used to determine the defect parameters. The annealing characteristics of the impurity defects C sub i , C sub i C sub s , C sub i O sub i and VO sub i suggest that the mobile C sub i atoms are also captured at divacancy VV sites at the cluster peripheries and not only at C sub s and O sub i sites in the silicon bulk. The deviation of the electrical filling characteristic of C sub i from the characteristic of a homogeneously distributed defect can be explained by an aggregation of C sub i atoms in the environment of the clusters. The capture rate of electrons into defects located in the cluster environment is reduced due to a positive space charge region surrounding the negatively charged cluster core. The optical filling characteristic of C sub i suggests that the change of the triangle-shaped electric field dis...

  14. Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

    Science.gov (United States)

    Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

    2013-01-02

    Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

  15. Detection of protein kinases P38 based on reflectance spectroscopy with n-type porous silicon microcavities for diagnosing hydatidosis hydatid disease

    Science.gov (United States)

    Lv, Xiaoyi; Lv, Guodong; Jia, Zhenhong; Wang, Jiajia; Mo, Jiaqing

    2014-11-01

    Detection of protein kinases P38 of Echinococcus granulosus and its homologous antibody have great value for early diagnosis and treatment of hydatidosis hydatid disease. In this experiment, n-type mesoporous silicon microcavities have been successfully fabricated without KOH etching or oxidants treatment that reported in other literature. We observed the changes of the reflectivity spectrum before and after the antigen-antibody reaction by n-type mesoporous silicon microcavities. The binding of protein kinases P38 and its homologous antibody causes red shifts in the reflection spectrum of the sensor, and the red shift was proportional to the protein kinases P38 concentration with linear relationship.

  16. Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

    Science.gov (United States)

    Norris, D J; Myronov, M; Leadley, D R; Walther, T

    2017-12-01

    We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

  17. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  18. Synthesis of thermoresponsive poly(N-isopropylacrylamide) brush on silicon wafer surface via atom transfer radical polymerization

    Energy Technology Data Exchange (ETDEWEB)

    Turan, Eylem; Demirci, Serkan [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey); Caykara, Tuncer, E-mail: caykara@gazi.edu.t [Department of Chemistry, Faculty of Art and Science, Gazi University, 06500 Besevler, Ankara (Turkey)

    2010-08-31

    Thermoresponsive poly(N-isopropylacrylamide) [poly(NIPAM)] brush on silicon wafer surface was prepared by combining the self-assembled monolayer of initiator and atom transfer radical polymerization (ATRP). The resulting polymer brush was characterized by in situ reflectance Fourier transform infrared spectroscopy, atomic force microscopy and ellipsometry techniques. Gel permeation chromatography determination of the number-average molecular weight and polydispersity index of the brush detached from the silicon wafer surface suggested that the surface-initiated ATRP method can provide relatively homogeneous polymer brush. Contact angle measurements exhibited a two-stage increase upon heating over the board temperature range 25-45 {sup o}C, which is in contrast to the fact that free poly(NIPAM) homopolymer in aqueous solution exhibits a phase transition at ca. 34 {sup o}C within a narrow temperature range. The first de-wetting transition takes place at 27 {sup o}C, which can be tentatively attributed to the n-cluster induced collapse of the inner region of poly(NIPAM) brush close to the silicon surface; the second de-wetting transition occurs at 38 {sup o}C, which can be attributed to the outer region of poly(NIPAM) brush, possessing much lower chain density compared to that of the inner part.

  19. Deep level transient spectroscopic analysis of p/n junction implanted with boron in n-type silicon substrate

    Science.gov (United States)

    Wakimoto, Hiroki; Nakazawa, Haruo; Matsumoto, Takashi; Nabetani, Yoichi

    2018-04-01

    For P-i-N diodes implanted and activated with boron ions into a highly-resistive n-type Si substrate, it is found that there is a large difference in the leakage current between relatively low temperature furnace annealing (FA) and high temperature laser annealing (LA) for activation of the p-layer. Since electron trap levels in the n-type Si substrate is supposed to be affected, we report on Deep Level Transient Spectroscopy (DLTS) measurement results investigating what kinds of trap levels are formed. As a result, three kinds of electron trap levels are confirmed in the region of 1-4 μm from the p-n junction. Each DLTS peak intensity of the LA sample is smaller than that of the FA sample. In particular, with respect to the trap level which is the closest to the silicon band gap center most affecting the reverse leakage current, it was not detected in LA. It is considered that the electron trap levels are decreased due to the thermal energy of LA. On the other hand, four kinds of trap levels are confirmed in the region of 38-44 μm from the p-n junction and the DLTS peak intensities of FA and LA are almost the same, considering that the thermal energy of LA has not reached this area. The large difference between the reverse leakage current of FA and LA is considered to be affected by the deep trap level estimated to be the interstitial boron.

  20. Harnessing light energy with a planar transparent hybrid of graphene/single wall carbon nanotube/n-type silicon heterojunction solar cell

    DEFF Research Database (Denmark)

    Chen, Leifeng; Yu, Hua; Zhong, Jiasong

    2015-01-01

    The photovoltaic conversion efficiency of a solar cell fabricated by a simple electrophoretic method with a planar transparent hybrid of graphenes (GPs) and single wall carbon nanotubes (SCNTs)/n-type silicon heterojunction was significantly increased compared to GPs/n-Si and SCNTs/n-Si solar cells...

  1. Tunnel oxide passivated rear contact for large area n-type front junction silicon solar cells providing excellent carrier selectivity

    Directory of Open Access Journals (Sweden)

    Yuguo Tao

    2016-01-01

    Full Text Available Carrier-selective contact with low minority carrier recombination and efficient majority carrier transport is mandatory to eliminate metal-induced recombination for higher energy conversion efficiency for silicon (Si solar cells. In the present study, the carrier-selective contact consists of an ultra-thin tunnel oxide and a phosphorus-doped polycrystalline Si (poly-Si thin film formed by plasma enhanced chemical vapor deposition (PECVD and subsequent thermal crystallization. It is shown that the poly-Si film properties (doping level, crystallization and dopant activation anneal temperature are crucial for achieving excellent contact passivation quality. It is also demonstrated quantitatively that the tunnel oxide plays a critical role in this tunnel oxide passivated contact (TOPCON scheme to realize desired carrier selectivity. Presence of tunnel oxide increases the implied Voc (iVoc by ~ 125 mV. The iVoc value as high as 728 mV is achieved on symmetric structure with TOPCON on both sides. Large area (239 cm2 n-type Czochralski (Cz Si solar cells are fabricated with homogeneous implanted boron emitter and screen-printed contact on the front and TOPCON on the back, achieving 21.2% cell efficiency. Detailed analysis shows that the performance of these cells is mainly limited by boron emitter recombination on the front side.

  2. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  3. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Science.gov (United States)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  4. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  5. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  6. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Science.gov (United States)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  7. Interfacial Characteristics of TiN Coatings on SUS304 and Silicon Wafer Substrates with Pulsed Laser Thermal Shock

    International Nuclear Information System (INIS)

    Seo, Nokun; Jeon, Seol; Choi, Youngkue; Shin, Hyun-Gyoo; Lee, Heesoo; Jeon, Min-Seok

    2014-01-01

    TiN coatings prepared on different substrates that had different coefficients of thermal expansion were subjected to pulsed laser thermal shock and observed by using FIB milling to compare the deterioration behaviors. TiN coating on SUS304, which had a larger CTE (⁓17.3 × 10 - 6 /℃) than the coating was degraded with pores and cracks on the surface and showed significant spalling of the coating layer over a certain laser pulses. TiN coating on silicon wafer with a smaller CTE value, ⁓4.2 × 10‒6 /℃, than the coating exhibited less degradation of the coating layer at the same ablation condition. Cracks propagated at the interface were observed in the coating on the silicon wafer, which induced a compressive stress to the coating. The coating on the SUS304 showed less interface cracks while the tensile stress was applied to the coating. Delamination of the coating layer related to the intercolumnar cracks at the interface was observed in both coatings through bright-field TEM analysis.

  8. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    International Nuclear Information System (INIS)

    Takahara, Hikari; Mori, Yoshihiro; Shibata, Harumi; Shimazaki, Ayako; Shabani, Mohammad B.; Yamagami, Motoyuki; Yabumoto, Norikuni; Nishihagi, Kazuo; Gohshi, Yohichi

    2013-01-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10 9 and 5 × 10 10 atoms/cm 2 Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO 2 , silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10 10 atoms/cm 2 . • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies

  9. Development of low cost silicon solar cells by reusing the silicon saw dust collected during wafering process

    International Nuclear Information System (INIS)

    Zaidi, Z.I.; Raza, B.; Ahmed, M.; Sheikh, H.; Qazi, I.A.

    2002-01-01

    Silicon material due to its abundance in nature and maximum conversion efficiency has been successfully being used for the fabrication of electronic and photovoltaic devices such as ICs, diodes, transistors and solar cells. The 80% of the semiconductor industry is ruled by silicon material. Single crystal silicon solar cells are in use for both space and terrestrial application, due to the well developed technology and better efficiency than polycrystalline and amorphous silicon solar cells. The current research work is an attempt to reduce the cost of single crystal silicon solar cells by reusing the silicon saw dust obtained during the watering process. During the watering process about 45% Si material is wasted in the form of Si powder dust. Various waste powder silicon samples were analyzed using inductively Coupled Plasma (ICP) technique, for metallic impurities critical for solar grade silicon material. The results were evaluated from impurity and cost point of view. (author)

  10. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Science.gov (United States)

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

  11. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    NARCIS (Netherlands)

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  12. Positron annihilation lifetime in float-zone n-type silicon irradiated by fast electrons: a thermally stable vacancy defect

    International Nuclear Information System (INIS)

    Arutyunov, Nikolay; Emtsev, Vadim; Oganesyan, Gagik; Krause-Rehberg, Reinhard; Elsayed, Mohamed; Kozlovskii, Vitalii

    2016-01-01

    Temperature dependency of the average positron lifetime has been investigated for n-type float-zone silicon, n-FZ-Si(P), subjected to irradiation with 0.9 MeV electrons at RT. In the course of the isochronal annealing a new defect-related temperature-dependent pattern of the positron lifetime spectra has been revealed. Beyond the well known intervals of isochronal annealing of acceptor-like defects such as E-centers, divacancies and A-centers, the positron annihilation at the vacancy defects has been observed in the course of the isochronal annealing from ∝ 320 C up to the limit of reliable detecting of the defect-related positron annihilation lifetime at ≥ 500 C. These data correlate with the ones of recovery of the concentration of the charge carriers and their mobility which is found to continue in the course of annealing to ∝ 570 C; the annealing is accomplished at ∝650 C. A thermally stable complex consisting of the open vacancy volume and the phosphorus impurity atom, V_o_p-P, is suggested as a possible candidate for interpreting the data obtained by the positron annihilation lifetime spectroscopy. An extended couple of semi-vacancies, 2V_s_-_e_x_t, as well as a relaxed inwards a couple of vacancies, 2V_i_n_w, are suggested as the open vacancy volume V_o_p to be probed with the positron. It is argued that a high thermal stability of the V_s_-_e_x_t PV_s_-_e_x_t (or V_i_n_wPV_i_n_w_.) configuration is contributed by the efficiency of PSi_5 bonding. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  13. Solid phase epitaxy on N-type polysilicon films formed by aluminium induced crystallization of amorphous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Tuezuen, O., E-mail: Ozge.Tuzun@iness.c-strasbourg.f [InESS, UMR 7163 CNRS-UdS, 23 rue du Loess, F-67037 Strasbourg Cedex 2 (France); Slaoui, A.; Roques, S.; Focsa, A. [InESS, UMR 7163 CNRS-UdS, 23 rue du Loess, F-67037 Strasbourg Cedex 2 (France); Jomard, F.; Ballutaud, D. [GEMaC-UMR 8635 CNRS, 1 place Aristide Briand, F-92195 Meudon (France)

    2009-10-01

    In this work, undoped amorphous silicon layers were deposited on n-type AIC seed films and then annealed at different temperatures for epitaxial growth. The epitaxy was carried out using halogen lamps (rapid thermal process or RTP) or a tube conventional furnace (CTP). We investigated the morphology of the resulting 2 {mu}m thick epi-layers by means of optical microscopy. An average grain size of about 40 {mu}m is formed after 90 s annealing at 1000 {sup o}C in RTP. The stress and degree of crystallinity of the epi-layers were studied by micro-Raman Spectroscopy and UV-visible spectrometer as a function of annealing time. The presence of compressive stress is observed from the peak position which shifts from 520.0 cm{sup -1} to 521.0 cm{sup -1} and 522.3 cm{sup -1} after CTP annealing for 10 min and 90 min, respectively. It is shown that the full width at half maximum (FWHM) varies from 9.8 cm{sup -1} to 15.6 cm{sup -1}, and the magnitude of stress is changing from 325 MPa to 650 MPa. Finally, the highest crystallinity is achieved after annealing at 1000 {sup o}C for 90 min in a tube furnace exhibiting a crystalline fraction of 81.5%. X-ray diffraction technique was used to determine the preferential orientation of the poly-Si thin films formed by SPE technique on n{sup +} type AIC layer. The preferential orientation is <100> for all annealing times at 1000 {sup o}C.

  14. Proposal of a neutron transmutation doping facility for n-type spherical silicon solar cell at high-temperature engineering test reactor.

    Science.gov (United States)

    Ho, Hai Quan; Honda, Yuki; Motoyama, Mizuki; Hamamoto, Shimpei; Ishii, Toshiaki; Ishitsuka, Etsuo

    2018-05-01

    The p-type spherical silicon solar cell is a candidate for future solar energy with low fabrication cost, however, its conversion efficiency is only about 10%. The conversion efficiency of a silicon solar cell can be increased by using n-type silicon semiconductor as a substrate. This study proposed a new method of neutron transmutation doping silicon (NTD-Si) for producing the n-type spherical solar cell, in which the Si-particles are irradiated directly instead of the cylinder Si-ingot as in the conventional NTD-Si. By using a 'screw', an identical resistivity could be achieved for the Si-particles without a complicated procedure as in the NTD with Si-ingot. Also, the reactivity and neutron flux swing could be kept to a minimum because of the continuous irradiation of the Si-particles. A high temperature engineering test reactor (HTTR), which is located in Japan, was used as a reference reactor in this study. Neutronic calculations showed that the HTTR has a capability to produce about 40t/EFPY of 10Ωcm resistivity Si-particles for fabrication of the n-type spherical solar cell. Copyright © 2018 Elsevier Ltd. All rights reserved.

  15. Minimizing guard ring dead space in silicon detectors with an n-type guard ring at the edge of the detector

    International Nuclear Information System (INIS)

    Palviainen, Tanja; Tuuva, Tuure; Leinonen, Kari

    2007-01-01

    Detectors with n-type silicon with an n + -type guard ring were investigated. In the present work, a new p + /n/n + detector structure with an n + guard ring is described. The guard ring is placed at the edge of the detector. The detector depletion region extends also sideways, allowing for signal collection very close to the n-guard ring. In this kind of detector structure, the dead space of the detector is minimized to be only below the guard ring. This is proved by simulations done using Silvaco/ATLAS software

  16. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Energy Technology Data Exchange (ETDEWEB)

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  17. Influence of the transition region between p- and n-type polycrystalline silicon passivating contacts on the performance of interdigitated back contact silicon solar cells

    Science.gov (United States)

    Reichel, Christian; Müller, Ralph; Feldmann, Frank; Richter, Armin; Hermle, Martin; Glunz, Stefan W.

    2017-11-01

    Passivating contacts based on thin tunneling oxides (SiOx) and n- and p-type semi-crystalline or polycrystalline silicon (poly-Si) enable high passivation quality and low contact resistivity, but the integration of these p+/n emitter and n+/n back surface field junctions into interdigitated back contact silicon solar cells poses a challenge due to high recombination at the transition region from p-type to n-type poly-Si. Here, the transition region was created in different configurations—(a) p+ and n+ poly-Si regions are in direct contact with each other ("pn-junction"), using a local overcompensation (counterdoping) as a self-aligning process, (b) undoped (intrinsic) poly-Si remains between the p+ and n+ poly-Si regions ("pin-junction"), and (c) etched trenches separate the p+ and n+ poly-Si regions ("trench")—in order to investigate the recombination characteristics and the reverse breakdown behavior of these solar cells. Illumination- and injection-dependent quasi-steady state photoluminescence (suns-PL) and open-circuit voltage (suns-Voc) measurements revealed that non-ideal recombination in the space charge regions with high local ideality factors as well as recombination in shunted regions strongly limited the performance of solar cells without a trench. In contrast, solar cells with a trench allowed for open-circuit voltage (Voc) of 720 mV, fill factor of 79.6%, short-circuit current (Jsc) of 41.3 mA/cm2, and a conversion efficiencies (η) of 23.7%, showing that a lowly conducting and highly passivating intermediate layer between the p+ and n+ poly-Si regions is mandatory. Independent of the configuration, no hysteresis was observed upon multiple stresses in reverse direction, indicating a controlled and homogeneously distributed breakdown, but with different breakdown characteristics.

  18. A Reuse Evaluation for Solar-Cell Silicon Wafers via Shift Revolution and Tool Rotation Using Magnetic Assistance in Ultrasonic Electrochemical Micromachining

    Directory of Open Access Journals (Sweden)

    P. S. Pa

    2013-01-01

    Full Text Available A new reuse fabrication using a tool module with rotation and revolution through a process of magnetic assistance in ultrasonic electrochemical micromachining (UEMM for removal of the surface layers from silicon wafers of solar cells is demonstrated. The target of the proposed reuse fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach to removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. The high revolution speed of the shift with the high rotation speed of the designed tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. High frequency and high power of ultrasonic with large electrolyte flow rate and high magnetic strengths with a small distance between the two magnets provide a large discharge effect and good removal; only a short period of time is required to remove the epoxy film and Si3N4 layer easily and cleanly.

  19. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  20. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  1. Ion-implanted capacitively coupled silicon strip detectors with integrated polysilicon bias resistors processed on a 100 mm wafer

    International Nuclear Information System (INIS)

    Hietanen, I.; Lindgren, J.; Orava, R.; Tuuva, T.; Voutilainen, M.; Brenner, R.; Andersson, M.; Leinonen, K.; Ronkainen, H.

    1991-01-01

    Double-sided silicon strip detectors with integrated coupling capacitors and polysilicon resistors have been processed on a 100 mm wafer. A detector with an active area of 19x19 mm 2 was connected to LSI readout electronics and tested. The strip pitch of the detector is 25 μm on the p-side and 50 μm on the n-side. The readout pitch is 50 μm on both sides. The number of readout strips is 774 and the total number of strips is 1161. On the p-side a signal-to-noise of 35 has been measured using a 90 Sr β-source. The n-side has been studied using a laser. (orig.)

  2. Surface passivation of n-type doped black silicon by atomic-layer-deposited SiO2/Al2O3 stacks

    Science.gov (United States)

    van de Loo, B. W. H.; Ingenito, A.; Verheijen, M. A.; Isabella, O.; Zeman, M.; Kessels, W. M. M.

    2017-06-01

    Black silicon (b-Si) nanotextures can significantly enhance the light absorption of crystalline silicon solar cells. Nevertheless, for a successful application of b-Si textures in industrially relevant solar cell architectures, it is imperative that charge-carrier recombination at particularly highly n-type doped black Si surfaces is further suppressed. In this work, this issue is addressed through systematically studying lowly and highly doped b-Si surfaces, which are passivated by atomic-layer-deposited Al2O3 films or SiO2/Al2O3 stacks. In lowly doped b-Si textures, a very low surface recombination prefactor of 16 fA/cm2 was found after surface passivation by Al2O3. The excellent passivation was achieved after a dedicated wet-chemical treatment prior to surface passivation, which removed structural defects which resided below the b-Si surface. On highly n-type doped b-Si, the SiO2/Al2O3 stacks result in a considerable improvement in surface passivation compared to the Al2O3 single layers. The atomic-layer-deposited SiO2/Al2O3 stacks therefore provide a low-temperature, industrially viable passivation method, enabling the application of highly n- type doped b-Si nanotextures in industrial silicon solar cells.

  3. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    International Nuclear Information System (INIS)

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  4. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Energy Technology Data Exchange (ETDEWEB)

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  5. Preliminary reduction of chromium ore using Si sludge generated in silicon wafer manufacturing process

    Directory of Open Access Journals (Sweden)

    Jung W.-G.

    2018-01-01

    Full Text Available In order to promote the recycling of by-product from Si wafer manufacturing process and to develop environment-friend and low cost process for ferrochrome alloy production, a basic study was performed on the preliminary reduction reaction between chromium ore and the Si sludge, comprised of SiC and Si particles, which is recovered from the Si wafer manufacturing process for the semiconductor and solar cell industries. Pellets were first made by mixing chromium ore, Si sludge, and some binders in the designed mixing ratios and were then treated at different temperatures in the 1116°C–1388°C range in an ambient atmosphere. Cordierite and SiO2 were confirmed to be formed in the products after the reduction. Additionally, metal particles were observed in the product with Fe, Cr, and Si components. It is found that temperatures above 1300°C are necessary for the reduction of the chromium ore by the Si sludge. The reduction ratio for Fe was evaluated quantitatively for our experimental conditions, and the proper mixing ratio was suggested for the pre-reduction of the chromium ore by the Si sludge. This study provides basic information for the production of ferrochrome alloys on the pre-reduction of chromium ore using Si sludge.

  6. Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

    Science.gov (United States)

    Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

    2016-11-01

    The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

  7. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  8. The ALU+ concept: n-type silicon solar cells with surface passivated screen-printed aluminum-alloyed rear emitter

    NARCIS (Netherlands)

    Bock, R.; Schmidt, J.; Mau, S.; Hoex, B.; Kessels, W.M.M.; Brendel, R.

    2009-01-01

    Aluminum-doped p-type (Al-p+) silicon emitters fabricated by means of screen-printing and firing are effectively passivated by plasma-enhanced chemicalvapor deposited (PECVD) amorphous silicon (a-Si) and atomic-layer-deposited (ALD) aluminum oxide (Al2O3) as well as Al2O3/SiNx stacks, where the

  9. Possibility of whole-surface analysis of a silicon wafer with ordinary straight TXRF

    International Nuclear Information System (INIS)

    Mori, Y.; Uemura, K.; Iizuka, Y.

    2000-01-01

    For the analysis of average metal concentration on a semiconductor surface, we customarily use the wet techniques (AAS, typically), that require skilled operators or expensive automated machines for sample pretreatment. The straight TXRF require no pretreatment, on the other hand. However, its detection area is too small (1-2 cm 2 ) to conduct a whole-surface analysis. In fact, it takes more than one day per one wafer (500 s/point x 100-300 points) for a complete mapping. Therefore it has been believed that the whole-surface analysis with straight TXRF is impracticable. It should be noted that the absolute lower limit of detection (LLD) of the straight TXRF is superior to AAS. As an example, the absolute LLD of TXRF for Fe is 0.2 pg (500 s integration), while that of AAS is l0 pg. The required integration time for TXRF to obtain the same LLD of AAS is calculated to be only 0.2 s. This means, in principle, that the whole-surface contamination can be measured in some ten seconds by accumulating 0.2 s mapping. But actually, the adjustment of glancing angle requires several ten seconds per one point, so the above mapping still takes several hours. That is why such a measurement has not been applied to daily analysis so far. However, the influence of glancing angle errors is expected to be reduced through the multi-point measurement. Figure 1 shows an accumulated spectrum of 20 s x 25 points mapping for an IAP wafer doped with Ni. In this measurement, glancing angles were not precisely controlled (the error of glancing angle is ±15 %). A spectrum of 500 s x 1 point measurement for the same wafer is shown in Figure 2. Figures 1 and 2 are almost identical. This suggests that the reduction of glancing angle errors actually works well through multi-points measurement. This method is expected to give better results by increasing the number of measuring points. The overall variation for the final measurement value obtained by multi-point measurement can be assessed by the

  10. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  11. Radiation hardness of silicon detectors manufactured on wafers from various sources

    International Nuclear Information System (INIS)

    Dezillie, B.; Bates, S.; Glaser, M.; Lemeilleur, F.; Leroy, C.

    1997-01-01

    Impurity concentrations in the initial silicon material are expected to play an important role for the radiation hardness of silicon detectors, during their irradiation and for their evolution with time after irradiation. This work reports on the experimental results obtained with detectors manufactured using various float-zone (FZ) and epitaxial-grown material. Preliminary results comparing the changes in leakage current and full depletion voltage of FZ and epitaxial detectors as a function of fluence and of time after 10 14 cm -2 proton irradiation are given. The measurement of charge collection efficiency for epitaxial detectors is also presented. (orig.)

  12. Damage-free polishing of monocrystalline silicon wafers without chemical additives

    International Nuclear Information System (INIS)

    Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

    2008-01-01

    This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

  13. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Science.gov (United States)

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  14. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  15. Wet chemical treatment of boron doped emitters on n-type (100) c-Si prior to amorphous silicon passivation

    OpenAIRE

    Meddeb, H.; Bearda, Twan; Payo, M. Recaman; Abdelwahab, I.; Abdulraheem, Yaser; Ezzaouia, H.; Gordon, I.; Szlufcik, J.; POORTMANS, Jef

    2015-01-01

    The influence of the cleaning process on the amorphous silicon passivation of homojunction emitters is investigated. A significant variation in the passivation quality following different cleaning sequences is not observed, even though differences in cleaning performance are evident. These results point out the effectiveness of our cleaning treatment and provide a hydrogen termination for intrinsic amorphous silicon passivation. A post-deposition treatment improves the passivation level yield...

  16. Minimizing guard ring dead space in silicon detectors with an n-type guard ring at the edge of the detector

    Energy Technology Data Exchange (ETDEWEB)

    Palviainen, Tanja [Lappeenranta University of Technology, P.O. Box 20, FIN-53851 Lappeenranta (Finland)]. E-mail: tanja.palviainen@lut.fi; Tuuva, Tuure [Lappeenranta University of Technology, P.O. Box 20, FIN-53851 Lappeenranta (Finland); Leinonen, Kari [Lappeenranta University of Technology, P.O. Box 20, FIN-53851 Lappeenranta (Finland)

    2007-04-01

    Detectors with n-type silicon with an n{sup +}-type guard ring were investigated. In the present work, a new p{sup +}/n/n{sup +} detector structure with an n{sup +} guard ring is described. The guard ring is placed at the edge of the detector. The detector depletion region extends also sideways, allowing for signal collection very close to the n-guard ring. In this kind of detector structure, the dead space of the detector is minimized to be only below the guard ring. This is proved by simulations done using Silvaco/ATLAS software.

  17. Internal Friction and Young's Modulus Measurements on SiO2 and Ta2O5 Films Done with an Ultra-High Q Silicon-Wafer Suspension

    Directory of Open Access Journals (Sweden)

    Granata M.

    2015-04-01

    Full Text Available In order to study the internal friction of thin films a nodal suspension system called GeNS (Gentle Nodal Suspension has been developed. The key features of this system are: i the possibility to use substrates easily available like silicon wafers; ii extremely low excess losses coming from the suspension system which allows to measure Q factors in excess of 2×108 on 3” diameter wafers; iii reproducibility of measurements within few percent on mechanical losses and 0.01% on resonant frequencies; iv absence of clamping; v the capability to operate at cryogenic temperatures. Measurements at cryogenic temperatures on SiO2 and at room temperature only on Ta2O5 films deposited on silicon are presented.

  18. Neutron activation analysis of low-level element contents in silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Goerner, W [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  19. Laser-fired contact formation on metallized and passivated silicon wafers under short pulse durations

    Science.gov (United States)

    Raghavan, Ashwin S.

    The objective of this work is to develop a comprehensive understanding of the physical processes governing laser-fired contact (LFC) formation under microsecond pulse durations. Primary emphasis is placed on understanding how processing parameters influence contact morphology, passivation layer quality, alloying of Al and Si, and contact resistance. In addition, the research seeks to develop a quantitative method to accurately predict the contact geometry, thermal cycles, heat and mass transfer phenomena, and the influence of contact pitch distance on substrate temperatures in order to improve the physical understanding of the underlying processes. Finally, the work seeks to predict how geometry for LFCs produced with microsecond pulses will influence fabrication and performance factors, such as the rear side contacting scheme, rear surface series resistance and effective rear surface recombination rates. The characterization of LFC cross-sections reveals that the use of microsecond pulse durations results in the formation of three-dimensional hemispherical or half-ellipsoidal contact geometries. The LFC is heavily alloyed with Al and Si and is composed of a two-phase Al-Si microstructure that grows from the Si wafer during resolidification. As a result of forming a large three-dimensional contact geometry, the total contact resistance is governed by the interfacial contact area between the LFC and the wafer rather than the planar contact area at the original Al-Si interface within an opening in the passivation layer. By forming three-dimensional LFCs, the total contact resistance is significantly reduced in comparison to that predicted for planar contacts. In addition, despite the high energy densities associated with microsecond pulse durations, the passivation layer is well preserved outside of the immediate contact region. Therefore, the use of microsecond pulse durations can be used to improve device performance by leading to lower total contact resistances

  20. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Science.gov (United States)

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  1. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    International Nuclear Information System (INIS)

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  2. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Directory of Open Access Journals (Sweden)

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  3. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  4. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    KAUST Repository

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  5. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  6. Rectification properties of n-type nanocrystalline diamond heterojunctions to p-type silicon carbide at high temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Goto, Masaki; Amano, Ryo; Shimoda, Naotaka [Graduate School of Automotive Science, Kyushu University, Nishiku, Fukuoka 819-0395 (Japan); Kato, Yoshimine, E-mail: yoshimine.kato@zaiko.kyushu-u.ac.jp [Department of Materials Science and Engineering, Kyushu University, Nishiku, Fukuoka 819-0395 (Japan); Teii, Kungen [Department of Applied Science for Electronics and Materials, Kyushu University, Kasuga, Fukuoka 816-8580 (Japan)

    2014-04-14

    Highly rectifying heterojunctions of n-type nanocrystalline diamond (NCD) films to p-type 4H-SiC substrates are fabricated to develop p-n junction diodes operable at high temperatures. In reverse bias condition, a potential barrier for holes at the interface prevents the injection of reverse leakage current from the NCD into the SiC and achieves the high rectification ratios of the order of 10{sup 7} at room temperature and 10{sup 4} even at 570 K. The mechanism of the forward current injection is described with the upward shift of the defect energy levels in the NCD to the conduction band of the SiC by forward biasing. The forward current shows different behavior from typical SiC Schottky diodes at high temperatures.

  7. Microstructure and mechanical properties of thermoelectric nanostructured n-type silicon-germanium alloys synthesized employing spark plasma sintering

    Energy Technology Data Exchange (ETDEWEB)

    Bathula, Sivaiah [CSIR-Network of Institutes for Solar Energy, CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Department of Applied Physics, Delhi Technological University, Delhi (India); Gahtori, Bhasker; Tripathy, S. K.; Tyagi, Kriti; Srivastava, A. K.; Dhar, Ajay, E-mail: adhar@nplindia.org [CSIR-Network of Institutes for Solar Energy, CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Jayasimhadri, M. [Department of Applied Physics, Delhi Technological University, Delhi (India)

    2014-08-11

    Owing to their high thermoelectric (TE) figure-of-merit, nanostructured Si{sub 80}Ge{sub 20} alloys are evolving as a potential replacement for their bulk counterparts in designing efficient radio-isotope TE generators. However, as the mechanical properties of these alloys are equally important in order to avoid in-service catastrophic failure of their TE modules, we report the strength, hardness, fracture toughness, and thermal shock resistance of nanostructured n-type Si{sub 80}Ge{sub 20} alloys synthesized employing spark plasma sintering of mechanically alloyed nanopowders of its constituent elements. These mechanical properties show a significant enhancement, which has been correlated with the microstructural features at nano-scale, delineated by transmission electron microscopy.

  8. Low-field microwave absorption and magnetoresistance in iron nanostructures grown by electrodeposition on n-type lightly doped silicon substrates

    Energy Technology Data Exchange (ETDEWEB)

    Felix, J.F. [Universidade Federal de Viçosa-UFV, Departamento de Física, 36570-900 Viçosa, MG (Brazil); Universidade de Brasília-UnB, Instituto de Física, Núcleo de Física Aplicada, 70910-900 Brasília, DF (Brazil); Figueiredo, L.C. [Universidade de Brasília-UnB, Instituto de Física, Núcleo de Física Aplicada, 70910-900 Brasília, DF (Brazil); Mendes, J.B.S. [Universidade Federal de Viçosa-UFV, Departamento de Física, 36570-900 Viçosa, MG (Brazil); Morais, P.C. [Universidade de Brasília-UnB, Instituto de Física, Núcleo de Física Aplicada, 70910-900 Brasília, DF (Brazil); Huazhong University of Science and Technology, School of Automation, 430074 Wuhan (China); Araujo, C.I.L. de., E-mail: dearaujo@ufv.br [Universidade de Brasília-UnB, Instituto de Física, Núcleo de Física Aplicada, 70910-900 Brasília, DF (Brazil)

    2015-12-01

    In this study we investigate magnetic properties, surface morphology and crystal structure in iron nanoclusters electrodeposited on lightly doped (100) n-type silicon substrates. Our goal is to investigate the spin injection and detection in the Fe/Si lateral structures. The samples obtained under electric percolation were characterized by magnetoresistive and magnetic resonance measurements with cycling the sweeping applied field in order to understand the spin dynamics in the as-produced samples. The observed hysteresis in the magnetic resonance spectra, plus the presence of a broad peak in the non-saturated regime confirming the low field microwave absorption (LFMA), were correlated to the peaks and slopes found in the magnetoresistance curves. The results suggest long range spin injection and detection in low resistive silicon and the magnetic resonance technique is herein introduced as a promising tool for analysis of electric contactless magnetoresistive samples. - Highlights: • Electrodeposition of Fe nanostructures on high resistive silicon substrates. • Spin polarized current among clusters through Si suggested by isotropic magnetoresistance. • Low field microwave absorption arising from the sample shape anisotropy. • Contactless magnetoresistive device characterization by resonance measurements.

  9. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  10. Single and double acceptor-levels of a carbon-hydrogen defect in n-type silicon

    Energy Technology Data Exchange (ETDEWEB)

    Stübner, R.; Scheffler, L.; Kolkovsky, Vl., E-mail: kolkov@ifpan.edu.pl; Weber, J. [Technische Universität Dresden, 01062 Dresden (Germany)

    2016-05-28

    In the present study, we discuss the origin of two dominant deep levels (E42 and E262) observed in n-type Si, which is subjected to hydrogenation by wet chemical etching or a dc H-plasma treatment. Their activation enthalpies determined from Laplace deep level transient spectroscopy measurements are E{sub C}-0.06 eV (E42) and E{sub C}-0.51 eV (E262). The similar annealing behavior and identical depth profiles of E42 and E262 correlate them with two different charge states of the same defect. E262 is attributed to a single acceptor state due to the absence of the Poole-Frenkel effect and the lack of a capture barrier for electrons. The emission rate of E42 shows a characteristic enhancement with the electric field, which is consistent with the assignment to a double acceptor state. In samples with different carbon and hydrogen content, the depth profiles of E262 can be explained by a defect with one H-atom and one C-atom. From a comparison with earlier calculations [Andersen et al., Phys. Rev. B 66, 235205 (2002)], we attribute E42 to the double acceptor and E262 to the single acceptor state of the CH{sub 1AB} configuration, where one H atom is directly bound to carbon in the anti-bonding position.

  11. A-centres build-up kinetics in the conductive matrix of pulled n-type silicon with calculation of their recharges at defect clusters

    International Nuclear Information System (INIS)

    Dolgolenko, A.P.; Fishchuk, I.I.

    1981-01-01

    Pulled n-Si samples with rho approximately 40 Ωcm are investigated after irradiation with different doses of fast-pile neutrons. It is known that the simple defects are created not only in the conductive matrix but also in the region of the space charge of defect clusters. Then the charge state, for example, of A-centres in the region of the space charge is defined by both, the temperature and the value of the electrostatical potential. If this circumstance is not taken into account the calculation of the conductive volume is not precise enough. In the present paper the temperature dependence of the volume fraction is calculated, in which the space charge of defect clusters occurs, taking into account the recharges of A-centres in the region of the space charge. Using the expression obtained the A-centres build-up kinetics in the conductive matrix of pulled n-type silicon is calculated. (author)

  12. High Sensitivity Detection of CdSe/ZnS Quantum Dot-Labeled DNA Based on N-type Porous Silicon Microcavities.

    Science.gov (United States)

    Lv, Changwu; Jia, Zhenhong; Lv, Jie; Zhang, Hongyan; Li, Yanyu

    2017-01-01

    N-type macroporous silicon microcavity structures were prepared using electrochemical etching in an HF solution in the absence of light and oxidants. The CdSe/ZnS water-soluble quantum dot-labeled DNA target molecules were detected by monitoring the microcavity reflectance spectrum, which was characterized by the reflectance spectrum defect state position shift resulting from changes to the structures' refractive index. Quantum dots with a high refractive index and DNA coupling can improve the detection sensitivity by amplifying the optical response signals of the target DNA. The experimental results show that DNA combined with a quantum dot can improve the sensitivity of DNA detection by more than five times.

  13. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  14. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  15. Porous Silicon Nanowires

    Science.gov (United States)

    Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

    2011-01-01

    In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

  16. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    International Nuclear Information System (INIS)

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  17. Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

    Science.gov (United States)

    Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

    2018-01-01

    Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

  18. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    Energy Technology Data Exchange (ETDEWEB)

    Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

    2017-05-08

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

  19. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Science.gov (United States)

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  20. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  1. An experimental and theoretical study of pendellösung fringes in synchrotron section topographs of silicon wafers.

    Science.gov (United States)

    Partanen, J; Tuomi, T

    1990-01-01

    X-ray section topographs of nearly perfect Czochralski-grown wafers were made with synchrotron radiation having a continuous spectrum. An intensity curve measured from the x-ray film is compared to the calculated curve obtained using the dynamical theory of x-ray diffraction. A computer simulation of the topograph is also presented. A good agreement between theory and experiment is found except in the middle part of the topograph.

  2. Manipulation of polystyrene nanoparticles on a silicon wafer in the peak force tapping mode in water: pH-dependent friction and adhesion force

    Energy Technology Data Exchange (ETDEWEB)

    Schiwek, Simon; Stark, Robert W., E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de; Dietz, Christian, E-mail: stark@csi.tu-darmstadt.de, E-mail: dietz@csi.tu-darmstadt.de [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany); Physics of Surfaces, Institute of Materials Science, Technische Universität Darmstadt, Alarich-Weiss-Str. 16, 64287 Darmstadt (Germany); Heim, Lars-Oliver [Center of Smart Interfaces, Technische Universität Darmstadt, Alarich-Weiss-Str. 10, 64287 Darmstadt (Germany)

    2015-03-14

    The friction force between nanoparticles and a silicon wafer is a crucial parameter for cleaning processes in the semiconductor industry. However, little is known about the pH-dependency of the friction forces and the shear strength at the interface. Here, we push polystyrene nanoparticles, 100 nm in diameter, with the tip of an atomic force microscope and measure the pH-dependency of the friction, adhesion, and normal forces on a silicon substrate covered with a native silicon dioxide layer. The peak force tapping mode was applied to control the vertical force on these particles. We successively increased the applied load until the particles started to move. The main advantage of this technique over single manipulation processes is the achievement of a large number of manipulation events in short time and in a straightforward manner. Geometrical considerations of the interaction forces at the tip-particle interface allowed us to calculate the friction force and shear strength from the applied normal force depending on the pH of an aqueous solution. The results clearly demonstrated that particle removal should be performed with a basic solution at pH 9 because of the low interaction forces between particle and substrate.

  3. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    NARCIS (Netherlands)

    Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  4. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Science.gov (United States)

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  5. Serial section scanning electron microscopy (S3EM) on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Science.gov (United States)

    Horstmann, Heinz; Körber, Christoph; Sätzler, Kurt; Aydin, Daniel; Kuner, Thomas

    2012-01-01

    High resolution, three-dimensional (3D) representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM), complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM) using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3)EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3) volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3)EM), for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3)EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  6. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  7. A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

    International Nuclear Information System (INIS)

    Wagler, H.; Flachowsky, J.

    1986-01-01

    Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

  8. Crystallization behavior of polyethylene on silicon wafers in solution casting processes traced by time-resolved measurements of synchrotron grazing-incidence small-angle and wide-angle X-ray scattering

    International Nuclear Information System (INIS)

    Sasaki, S; Masunaga, H; Takata, M; Itou, K; Tashiro, K; Okuda, H; Takahara, A

    2009-01-01

    Crystallization behavior of polyethylene (PE) on silicon wafers in solution casting processes has been successfully traced by time-resolved grazing-incidence small-angle and wide-angle X-ray scattering (GISWAXS) measurements utilizing synchrotron radiation. A p-xylene solution of PE kept at ca. 343 K was dropped on a silicon wafer at ca. 298 K. While the p-xylene evaporated naturally from the dropped solution sample, PE chains crystallized to be a thin film. Raman spectral measurements were performed simultaneously with the GISWAXS measurements to evaluate quantitatively the p-xylene the dropped solution contained. Grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns indicated nucleation and crystal growth in the dropped solution and the following as-cast film. GIWAXS and Raman spectral data revealed that crystallization of PE was enhanced after complete evaporation of the p-xylene from the dropped solution. The [110] and [200] directions of the orthorhombic PE crystal became relatively parallel to the wafer surface with time, which implied that the flat-on lamellae with respect to the wafer surface were mainly formed in the as-cast film. On the other hand, grazing-incidence small-angle X-ray scattering (GISAXS) patterns implied formation of isolated lamellae in the dropped solution. The lamellae and amorphous might alternatively be stacked in the preferred direction perpendicular to the wafer surface. The synchrotron GISWAXS experimental method could be applied for kinetic study on hierarchical structure of polymer thin films.

  9. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  10. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  11. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers.

    Science.gov (United States)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K(alpha)0.28 keV and Al K(alpha)1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K(alpha) (approximately 6 nm rms) is significantly larger than approximately 1 nm at Al K(alpha). This can be explained by different coherent lengths at two energies.

  12. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K{alpha}0.28 keV and Al K{alpha}1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K{alpha} ({approx}6 nm rms) is significantly larger than {approx}1 nm at Al K{alpha}. This can be explained by different coherent lengths at two energies.

  13. Characterization of the first double-sided 3D radiation sensors fabricated at FBK on 6-inch silicon wafers

    International Nuclear Information System (INIS)

    Sultan, D.M.S.; Mendicino, R.; Betta, G.-F. Dalla; Boscardin, M.; Ronchin, S.; Zorzi, N.

    2015-01-01

    Following 3D pixel sensor production for the ATLAS Insertable B-Layer, Fondazione Bruno Kessler (FBK) fabrication facility has recently been upgraded to process 6-inch wafers. In 2014, a test batch was fabricated to check for possible issues relevant to this upgrade. While maintaining a double-sided fabrication technology, some process modifications have been investigated. We report here on the technology and the design of this batch, and present selected results from the electrical characterization of sensors and test structures. Notably, the breakdown voltage is shown to exceed 200 V before irradiation, much higher than in earlier productions, demonstrating robustness in terms of radiation hardness for forthcoming productions aimed at High Luminosity LHC upgrades

  14. Surface passivation of n-type doped black silicon by atomic-layer-deposited SiO2/Al2O3 stacks

    NARCIS (Netherlands)

    van de Loo, B.W.H.; Ingenito, A.; Verheijen, M.A.; Isabella, O.; Zeman, M.; Kessels, W.M.M.

    2017-01-01

    Black silicon (b-Si) nanotextures can significantly enhance the light absorption of crystalline silicon solar cells. Nevertheless, for a successful application of b-Si textures in industrially relevant solar cell architectures, it is imperative that charge-carrier recombination at particularly

  15. a Study of Oxygen Precipitation in Heavily Doped Silicon.

    Science.gov (United States)

    Graupner, Robert Kurt

    processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

  16. Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2018-03-01

    We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

  17. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  18. Electrodeposition of three-dimensionally assembled platinum spheres on a gold-coated silicon wafer, and its application to nonenzymatic sensing of glucose

    International Nuclear Information System (INIS)

    Roh, Seongjin; Kim, Jongwon

    2015-01-01

    We report on a method of single-step electrodeposition of three-dimensionally (3-D) assembled Pt spheres on a gold-coated silicon wafer. The 3-D interconnected Pt spheres could be electrodeposited by applying a negative potential (−0.8 V, vs. Ag/AgCl) in neutral electrolytes containing KClO 4 . The application of such a negative potential is not possible in acidic solutions because of the formation of hydrogen. Scanning electron microscopy revealed that the seed Pt particles first grew to a certain size, and then form Pt spheres interconnected in multiple layers. The resulting 3-D assembled Pt sphere structures warrants a high surface area, and this property was utilized for the selective and sensitive amperometric determination of glucose at a working potential of 0.4 V (vs. Ag/AgCl), at near neutral pH values and in the presence of 0.1 M chloride. This straightforward method for the fabrication of 3-D assembled Pt sphere structures offers new opportunities for electroanalytical and electrocatalytic sensing based on porous Pt surfaces (author)

  19. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-12-16

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  20. The study of 1 MeV electron irradiation induced defects in N-type and P-type monocrystalline silicon

    Science.gov (United States)

    Babaee, S.; Ghozati, S. B.

    2017-12-01

    Despite extensive use of GaAs cells in space, silicon cells are still being used. The reason is that not only they provide a good compromise between efficiency and cost, but also some countries do not have the required technology for manufacturing GaAs. Behavior of a silicon cell under any levels of charged particle irradiation could be deducted from the results of a damage equivalent 1 MeV electron irradiation using the NASA EQflux open source software package. In this paper for the first time, we have studied the behavior of a silicon cell before and after 1 MeV electron irradiation with 1014, 1015 and 1016 electrons-cm-2 fluences, using SILVACO TCAD simulation software package. Simulation was carried out at room temperature under AM0 condition. Results reveal that open circuit voltage and efficiency decrease after irradiation while short circuit current shows a slight increase in the trend around 5 × 1016 electrons-cm-2, and short circuit current loss plays an important role on efficiency changes rather than open circuit voltage.

  1. Wet chemical treatment of boron doped emitters on n-type (1 0 0) c-Si prior to amorphous silicon passivation

    Energy Technology Data Exchange (ETDEWEB)

    Meddeb, H., E-mail: hosny.meddeb@gmail.com [KACST-Intel Consortium Center of Excellence in Nano-manufacturing Applications (CENA), Riyadh (Saudi Arabia); IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Research and Technology Center of Energy, Photovoltaic Department, Borj-Cedria Science and Technology Park, BP 95, 2050 (Tunisia); University of Carthage, Faculty of Sciences of Bizerta (Tunisia); Bearda, T.; Recaman Payo, M.; Abdelwahab, I. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Abdulraheem, Y. [Electrical Engineering Department, College of Engineering & Petroleum, Kuwait University, P.O. Box 5969, 13060 Safat (Kuwait); Ezzaouia, H. [Research and Technology Center of Energy, Photovoltaic Department, Borj-Cedria Science and Technology Park, BP 95, 2050 (Tunisia); Gordon, I.; Szlufcik, J. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Poortmans, J. [IMEC, Kapeldreef 75, B-3001 Leuven (Belgium); Department of Electrical Engineering (ESAT), K.U. Leuven, 3001 Leuven (Belgium); Faculty of Sciences, University of Hasselt, Martelarenlaan 42, 3500 Hasselt (Belgium)

    2015-02-15

    Highlights: • The influence of the cleaning process using different HF-based cleaning on the amorphous silicon passivation of homojunction boron doped emitters is analyzed. • The effect of boron doping level on surface characteristics after wet chemical cleaning: For heavily doped surfaces, the reduction in contact angle was less pronounced, which proves that such surfaces are more resistant to oxide formation and remain hydrophobic for a longer time. In the case of low HF concentration, XPS measurements show higher oxygen concentrations for samples with higher doping level, probably due to the incomplete removal of the native oxide. • Higher effective lifetime is achieved at lower doping for all considered different chemical pre-treatments. • A post-deposition annealing improves the passivation level yielding emitter saturation currents determined by Auger recombination in the order of 70 fA/cm{sup 2} and below. • The dominance of Auger recombination over other type of B-induced defects on lifetime quality in the case of our p+ emitter. - Abstract: The influence of the cleaning process on the amorphous silicon passivation of homojunction emitters is investigated. A significant variation in the passivation quality following different cleaning sequences is not observed, even though differences in cleaning performance are evident. These results point out the effectiveness of our cleaning treatment and provide a hydrogen termination for intrinsic amorphous silicon passivation. A post-deposition treatment improves the passivation level yielding emitter saturation currents determined by Auger recombination in the order of 70 fA/cm{sup 2} and below.

  2. Investigation the effect of porosity on corrosion of macroporous silicon in 1.0 M sodium hydroxide solution using weight loss measurements, electrochemical methods and scanning electron microscope

    International Nuclear Information System (INIS)

    Lai, Chuan; Xiang, Zhen

    2015-01-01

    Highlights: • The dissolution of silicon wafers conforms Faraday’s laws of electrolysis. • The porosity effect on macroporous silicon corrosion was investigated. • The corrosion rate increase linearly with porosity increasing. • The porosity effect on activation parameters was obtained. - Abstract: In this study, the macroporous silicon has been fabricated by electrochemical anodization. The dissolution of n-type silicon wafers in etching solution conforms Faraday’s laws of electrolysis. The fabricated macroporous silicon with different porosity corrosion in 1.0 M NaOH was systemically investigated by weight loss measurements, electrochemical methods and scanning electron microscope. Results show that with the porosity increasing, the corrosion rate of macroporous silicon in 1.0 M NaOH increases linearly. In addition, the increase of corrosion rate of macroporous silicon with relative higher porosity was determined by the pre-exponential factor.

  3. Junction Transport in Epitaxial Film Silicon Heterojunction Solar Cells: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Young, D. L.; Li, J. V.; Teplin, C. W.; Stradins, P.; Branz, H. M.

    2011-07-01

    We report our progress toward low-temperature HWCVD epitaxial film silicon solar cells on inexpensive seed layers, with a focus on the junction transport physics exhibited by our devices. Heterojunctions of i/p hydrogenated amorphous Si (a-Si) on our n-type epitaxial crystal Si on n++ Si wafers show space-charge-region recombination, tunneling or diffusive transport depending on both epitaxial Si quality and the applied forward voltage.

  4. Nanopatterned Silicon Substrate Use in Heterojunction Thin Film Solar Cells Made by Magnetron Sputtering

    Directory of Open Access Journals (Sweden)

    Shao-Ze Tseng

    2014-01-01

    Full Text Available This paper describes a method for fabricating silicon heterojunction thin film solar cells with an ITO/p-type a-Si : H/n-type c-Si structure by radiofrequency magnetron sputtering. A short-circuit current density and efficiency of 28.80 mA/cm2 and 8.67% were achieved. Novel nanopatterned silicon wafers for use in cells are presented. Improved heterojunction cells are formed on a nanopatterned silicon substrate that is prepared with a self-assembled monolayer of SiO2 nanospheres with a diameter of 550 nm used as an etching mask. The efficiency of the nanopattern silicon substrate heterojunction cells was 31.49% greater than that of heterojunction cells on a flat silicon wafer.

  5. Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

    Science.gov (United States)

    Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

    2009-09-01

    The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

  6. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  7. Positron probing of open vacancy volume of phosphorus-vacancy complexes in float-zone n-type silicon irradiated by 0.9-MeV electrons and by 15-MeV protons

    Energy Technology Data Exchange (ETDEWEB)

    Arutyunov, Nikolay [Department of Physics, Martin Luther University Halle (Germany); Ioffe Physico-Technical Institute, St. Petersburg (Russian Federation); Institute of Ion-Plasma and Laser Technologies (Institute of Electronics), Tashkent (Uzbekistan); Emtsev, Vadim; Oganesyan, Gagik [Ioffe Physico-Technical Institute, St. Petersburg (Russian Federation); Elsayed, Mohamed [Department of Physics, Martin Luther University Halle (Germany); Faculty of Science, Department of Physics, Minia University (Egypt); Krause-Rehberg, Reinhard [Department of Physics, Martin Luther University Halle (Germany); Abrosimov, Nikolay [Leibniz Institute for Crystal Growth, Berlin (Germany); Kozlovski, Vitalii [St. Petersburg State Polytechnical University (Russian Federation)

    2017-07-15

    For the first time the samples, cut from the same wafer of crystals of float-zone silicon, n-FZ-Si(P) and n-FZ-Si(Bi), were subjected to irradiation with 0.9-MeV electrons and 15-MeV protons at RT for studying them by low-temperature positron annihilation lifetime spectroscopy. Measurements of Hall effect have been used for the materials characterization. The discussion is focused on the open vacancy volume (V{sub op}) of the thermally stable group-V-impurity-vacancy complexes comprising the phosphorus atoms; the bismuth-related vacancy complexes are briefly considered. The data of positron probing of PV pairs (E-centers), divacancies, and the thermally stable defects in the irradiated n-FZ-Si(P) materials are compared. Beyond a reliable detecting of the defect-related positron annihilation lifetime in the course of isochronal annealing at ∝ 500 C, the recovery of concentration of phosphorus-related shallow donor states continues up to ∝650-700 C. The open vacancy volumes V{sub op} to be characterized by long positron lifetimes Δτ{sub 2} ∝271-289 ps in (gr.-V-atom)-V{sub op} complexes are compared with theoretical data available for the vacancies, τ(V{sub 1}), and divacancies, τ(V{sub 2}). The extended semi-vacancies, 2V{sub s-ext}, and relaxed vacancies, 2V{sub inw}, are proposed as the open volume V{sub op} in (gr.-V-atom)-V{sub op} complexes. It is argued that at high annealing temperature the defect P{sub s}-V{sub op}-P{sub s} is decomposed. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  8. Characterization of thermal, optical and carrier transport properties of porous silicon using the photoacoustic technique

    International Nuclear Information System (INIS)

    Sheng, Chan Kok; Mahmood Mat Yunus, W.; Yunus, Wan Md. Zin Wan; Abidin Talib, Zainal; Kassim, Anuar

    2008-01-01

    In this work, the porous silicon layer was prepared by the electrochemical anodization etching process on n-type and p-type silicon wafers. The formation of the porous layer has been identified by photoluminescence and SEM measurements. The optical absorption, energy gap, carrier transport and thermal properties of n-type and p-type porous silicon layers were investigated by analyzing the experimental data from photoacoustic measurements. The values of thermal diffusivity, energy gap and carrier transport properties have been found to be porosity-dependent. The energy band gap of n-type and p-type porous silicon layers was higher than the energy band gap obtained for silicon substrate (1.11 eV). In the range of porosity (50-76%) of the studies, our results found that the optical band-gap energy of p-type porous silicon (1.80-2.00 eV) was higher than that of the n-type porous silicon layer (1.70-1.86 eV). The thermal diffusivity value of the n-type porous layer was found to be higher than that of the p-type and both were observed to increase linearly with increasing layer porosity

  9. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  10. High power n-type metal-wrap-through cells and modules using industrial processes

    Energy Technology Data Exchange (ETDEWEB)

    Guillevin, N.; Heurtault, B.J.B.; Geerligs, L.J.; Van Aken, B.B.; Bennett, I.J.; Jansen, M.J.; Weeber, A.W.; Bultman, J.H. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG Petten (Netherlands); Jianming, Wang; Ziqian, Wang; Jinye, Zhai; Zhiliang, Wan; Shuquan, Tian; Wenchao, Zhao; Zhiyan, Hu; Gaofei, Li; Bo, Yu; Jingfeng, Xiong [Yingli Green Energy Holding Co.,Ltd. 3399 North Chaoyang Avenue, Baoding (China)

    2013-10-15

    This paper reviews our recent progress in the development of metal wrap through (MWT) cells and modules, produced from n-type Czochralski silicon wafers. The use of n-type silicon as base material allows for high efficiencies: for front emitter-contacted industrial cells, efficiencies above 20% have been reported. N-type MWT (nMWT) cells produced by industrial process technologies allow even higher efficiency due to reduced front metal coverage. Based on the same industrial technology, the efficiency of the bifacial n-MWT cells exceeds the efficiency of the n-type front-and-rear contact and bifacial 'Pasha' technology (n-Pasha) by 0.1-0.2% absolute, with a maximum nMWT efficiency of 20.1% so far. Additionally, full back-contacting of the MWT cells in a module results in reduced cell to module (CTM) fill factor losses. In a direct 60-cell module performance comparison, the n-MWT module, based on integrated backfoil, produced 3% higher power output than the comparable tabbed front emitter-contacted n-Pasha module. Thanks to reduced resistive losses in copper circuitry on the backfoil compared to traditional tabs, the CTM FF loss of the MWT module was reduced by about 2.2%abs. compared to the tabbed front emitter contact module. A full-size module made using MWT cells of 19.6% average efficiency resulted in a power output close to 280W. Latest results of the development of the n-MWT technology at cell and module level are discussed in this paper, including a recent direct comparison run between n-MWT and n-Pasha cells and results of n-MWT cells from 140{mu}m thin mono-crystalline wafers, with only very slight loss (1% of Isc) for the thin cells. Also reverse characteristics and effects of reverse bias for extended time at cell and module level are reported, where we find a higher tolerance of MWT modules than tabbed front contact modules for hotspots.

  11. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  12. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-01-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  13. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-06-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  14. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  15. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  16. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  17. Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

    Directory of Open Access Journals (Sweden)

    Jia Ge

    2014-01-01

    Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

  18. MOS structures containing silicon nanoparticles for memory device applications

    International Nuclear Information System (INIS)

    Nedev, N; Zlatev, R; Nesheva, D; Manolov, E; Levi, Z; Brueggemann, R; Meier, S

    2008-01-01

    Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO x (x = 1.15) and RF sputtering of SiO 2 on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability

  19. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  20. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  1. Porous silicon formation by hole injection from a back side p+/n junction for electrical insulation applications

    International Nuclear Information System (INIS)

    Fèvre, A; Menard, S; Defforge, T; Gautier, G

    2016-01-01

    In this paper, we propose to study the formation of porous silicon (PS) in low doped (1 × 10 14 cm −3 ) n-type silicon through hole injection from a back side p + /n junction in the dark. This technique is investigated within the framework of electrical insulation. Three different types of junctions are investigated. The first one is an epitaxial n-type layer grown on p + doped silicon wafer. The two other junctions are carried out by boron diffusion leading to p + regions with junction depths of 20 and 115 μm. The resulting PS morphology is a double layer with a nucleation layer (NL) and macropores fully filled with mesoporous material. This result is unusual for low doped n-type silicon. Morphology variations are described depending on the junction formation process, the electrolyte composition, the anodization current density and duration. In order to validate the more interesting industrial potentialities of the p + /n injection technique, a comparison is achieved with back side illumination in terms of resulting morphology and experiments confirm comparable results. Electrical characterizations of the double layer, including NL and fully filled macropores, are then performed. To our knowledge, this is the first electrical investigation in low doped n type silicon with this morphology. Compared to the bulk silicon, the measured electrical resistivities are 6–7 orders of magnitude higher at 373 K. (paper)

  2. Modification of the properties of porous silicon on adsorption of iodine molecules

    International Nuclear Information System (INIS)

    Vorontsov, A. S.; Osminkina, L. A.; Tkachenko, A. E.; Konstantinova, E. A.; Elenskii, V. G.; Timoshenko, V. Yu.; Kashkarov, P. K.

    2007-01-01

    Infrared spectroscopy and electron spin resonance measurements are used to study the properties of porous silicon layers on adsorption of the I 2 iodine molecules. The layers are formed on the p-an n-Si single-crystal wafers. It is established that, in the atmosphere of I 2 molecules, the charge-carrier concentration in the layers produced on the p-type wafers can be noticeably increased: the concentration of holes can attain values on the order of ∼10 18 -10 19 cm -3 . In porous silicon layers formed on the n-type wafers, the adsorption-induced inversion of the type of charge carriers and the partial substitution of silicon-hydrogen bonds by silicon-iodine bonds are observed. A decrease in the concentration of surface paramagnetic defects, P b centers, is observed in the samples with adsorbed iodine. The experimental data are interpreted in the context of the model in which it is assumed that both deep and shallow acceptor states are formed at the surface of silicon nanocrystals upon the adsorption of I 2 molecules

  3. The doping concentration and physical properties measurement of silicon water using tera hertz wave

    International Nuclear Information System (INIS)

    Park, Sung Hyeon; Oh, Gyung Hwan; Kim, Hak Sung

    2017-01-01

    In this study, a tera hertz time domain spectroscopy (THz-TDS) imaging technique was used to measure doping concentration and physical properties (such as refractive index and permittivity) of the doped silicon (Si) wafers. The transmission and reflection modes with an incidence angle of 30° were employed to determine the physical properties of the doped Si wafers. The doping concentrations of the prepared Si wafers were varied from 10"1"4 to 10"1"8 in both N-type and P-type cases. Finally, the correlation between the doping concentration and the power of the THz wave was determined by measuring the powers of the transmitted and reflected THz waves of the doped Si wafers. Additionally, the doped thickness, the refractive index, and permittivity of each doped Si wafer were calculated using the THz time domain waveform. The results indicate that the THz-TDS imaging technique is potentially a promising technique to measure the doping concentration as well as other optical properties (such as the refractive index and permittivity) of the doped Si wafer

  4. The doping concentration and physical properties measurement of silicon water using tera hertz wave

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sung Hyeon; Oh, Gyung Hwan; Kim, Hak Sung [Dept. of Mechanical Convergence Engineering, Hanyang University, Seoul(Korea, Republic of)

    2017-02-15

    In this study, a tera hertz time domain spectroscopy (THz-TDS) imaging technique was used to measure doping concentration and physical properties (such as refractive index and permittivity) of the doped silicon (Si) wafers. The transmission and reflection modes with an incidence angle of 30° were employed to determine the physical properties of the doped Si wafers. The doping concentrations of the prepared Si wafers were varied from 10{sup 14} to 10{sup 18} in both N-type and P-type cases. Finally, the correlation between the doping concentration and the power of the THz wave was determined by measuring the powers of the transmitted and reflected THz waves of the doped Si wafers. Additionally, the doped thickness, the refractive index, and permittivity of each doped Si wafer were calculated using the THz time domain waveform. The results indicate that the THz-TDS imaging technique is potentially a promising technique to measure the doping concentration as well as other optical properties (such as the refractive index and permittivity) of the doped Si wafer.

  5. Effects of indium concentration on the properties of In-doped ZnO films: Applications to silicon wafer solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Djessas, K. [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Bouchama, I., E-mail: bouchama.idris@yahoo.fr [Université de Perpignan Via Domitia (UPVD), Laboratoire Procédés, Matériaux et Energie Solaire (PROMES—CNRS), TECNOSUD, Rambla de la thermodynamique, 66100 Perpignan (France); Département d' Electronique, Faculté de Technologie, Université de Msila, 28000 (Algeria); Gauffier, J.L. [Département de Physique, INSA de Toulouse, 135 Avenue de Rangueil, 31077 Toulouse Cedex 4 (France); Ayadi, Z. Ben [Laboratoire de Physique des Matériaux et des Nanomatériaux appliquée à l' Environnement (LaPhyMNE), Université de Gabès, Faculté des Sciences de Gabès, Cité Erriadh Manara Zrig, 6072 Gabès (Tunisia)

    2014-03-31

    In the present paper, high-quality In-doped ZnO (ZnO:In) thin films have been prepared by rf-magnetron sputtering on glass and p-type monocrystalline silicon substrates from an aerogel nanopowder target material. The nanoparticles with the [In]/[Zn] ratio varying between 0.01 and 0.05 were synthesized by the sol–gel method and the structural properties have been analyzed. The effect of different dopant concentrations on the electrical, optical, structural and morphological properties of the films has been investigated. The obtained ZnO:In films at room temperature are polycrystalline with a hexagonal structure and a highly preferred orientation with the c-axis perpendicular to the substrate. Scanning electron microscopy and atomic force microscopy have been applied for a morphology characterization of the films' cross-section and surface. The results revealed a typical columnar structure and very smooth surface. Films with good optical transmittance, around 85%, within the visible wavelength region, and low resistivity in the range of 10{sup −3} Ω·cm and high mobility of 4 cm{sup 2}/Vs, were produced at low substrate temperature. On the other hand, we have studied the position of the p–n junction involved in an Au/In{sub 2}O{sub 3}:SnO{sub 2}/ZnO:In(n)/c-Si(p)/Al structure by electron beam induced current. Current density–voltage characterizations in the dark and under illumination were also performed. The cell exhibits an efficiency of 6%. - Highlights: • ZnO:In thin films were prepared by rf-magnetron sputtering. • No significant changes were observed in the ZnO:In properties. • In-doped ZnO shows superior electric properties compared with pure ZnO. • Interesting photovoltaic effect observed in ITO/ZnO:In(n)/c-Si(p) heterostructure • Good quality of p–n junction in the ZnO:In(n)/c-Si(p) solar cell.

  6. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    Science.gov (United States)

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic.

  7. A silicon pixel detector with routing for external VLSI read-out

    International Nuclear Information System (INIS)

    Thomas, S.L.; Seller, P.

    1988-07-01

    A silicon pixel detector with an array of 32 by 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector. The detailed design of the pixels, their layout and method of read-out are discussed. A number of test structures have been incorporated onto the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future. (author)

  8. Luminescence and optical absorption determination in porous silicon

    International Nuclear Information System (INIS)

    Nogal, U.; Calderon, A.; Marin, E.; Rojas T, J. B.; Juarez, A. G.

    2012-10-01

    We applied the photoacoustic spectroscopy technique in order to obtain the optical absorption spectrum in porous silicon samples prepared by electrochemical anodic etching on n-type, phosphorous doped, (100)-oriented crystal-line silicon wafer with thickness of 300 μm and 1-5 ωcm resistivity. The porous layers were prepared with etching times of 13, 20, 30, 40 and 60 minutes. Also, we realized a comparison among the optical absorption spectrum with the photoluminescence and photo reflectance ones, both obtained at room temperature. Our results show that the absorption spectrum of the samples of porous silicon depends notably of the etching time an it consist of two distinguishable absorption bands, one in the Vis region and the other one in the UV region. (Author)

  9. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  10. Development of AC-coupled, poly-silicon biased, p-on-n silicon strip detectors in India for HEP experiments

    Science.gov (United States)

    Jain, Geetika; Dalal, Ranjeet; Bhardwaj, Ashutosh; Ranjan, Kirti; Dierlamm, Alexander; Hartmann, Frank; Eber, Robert; Demarteau, Marcel

    2018-02-01

    P-on-n silicon strip sensors having multiple guard-ring structures have been developed for High Energy Physics applications. The study constitutes the optimization of the sensor design, and fabrication of AC-coupled, poly-silicon biased sensors of strip width of 30 μm and strip pitch of 55 μm. The silicon wafers used for the fabrication are of 4 inch n-type, having an average resistivity of 2-5 k Ω cm, with a thickness of 300 μm. The electrical characterization of these detectors comprises of: (a) global measurements of total leakage current, and backplane capacitance; (b) strip and voltage scans of strip leakage current, poly-silicon resistance, interstrip capacitance, interstrip resistance, coupling capacitance, and dielectric current; and (c) charge collection measurements using ALiBaVa setup. The results of the same are reported here.

  11. Formation of a silicon micropore array of a two-dimension electron multiplier by photo electrochemical etching

    International Nuclear Information System (INIS)

    Gao Yanjun; Duanmu Qingduo; Wang Guozheng; Li Ye; Tian Jingquan

    2009-01-01

    A semiconductor PEC etching method is applied to fabricate the n-type silicon deep micropore channel array. In this method, it is important to arrange the direction of the micropore array along the crystal orientation of the Si substrate. Otherwise, serious lateral erosion will happen. The etching process is also relative to the light intensity and HF concentration. 5% HF concentration and 10-15 cm distance between the light source and the silicon wafer are demonstrated to be the best in our experiments. The n-type silicon deep micropore channel array with aperture of 3 μm and aspect ratio of 40-60, whose inner walls are smooth, is finally obtained.

  12. Study of araldite in edge protection of n-type and p-type surface barrier detectors

    International Nuclear Information System (INIS)

    Alencar, M.A.V.; Jesus, E.F.O.; Lopes, R.T.

    1995-01-01

    The aim of this work is the realization of a comparative study between the surface barrier detectors performance n and type using the epoxy resin Araldite as edge protection material with the purpose of determining which type of detector (n or p) the use of Araldite is more indicated. The surface barrier detectors were constructed using n and p type silicon wafer with resistivity of 3350Ω.cm and 5850 Ω.cm respectively. In the n type detectors, the metals used as ohmic and rectifier contacts were the Al and Au respectively, while in the p type detectors, the ohmic and rectifier contacts were Au and Al. All metallic contacts were done by evaporation in high vacuum (∼10 -4 Torr) and with deposit of 40 μm/cm 2 . The obtained results for the detectors (reverse current of -350nA and resolution from 21 to 26 keV for p type detectors and reserve current of 1μA and resolution from 44 to 49 keV for n type detectors) tend to demonstrate that use of epoxy resin Araldite in the edge protection is more indicated to p type surface barrier detectors. (author). 3 refs., 4 figs., 1 tab

  13. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  14. Passivation mechanism in silicon heterojunction solar cells with intrinsic hydrogenated amorphous silicon oxide layers

    Science.gov (United States)

    Deligiannis, Dimitrios; van Vliet, Jeroen; Vasudevan, Ravi; van Swaaij, René A. C. M. M.; Zeman, Miro

    2017-02-01

    In this work, we use intrinsic hydrogenated amorphous silicon oxide layers (a-SiOx:H) with varying oxygen content (cO) but similar hydrogen content to passivate the crystalline silicon wafers. Using our deposition conditions, we obtain an effective lifetime (τeff) above 5 ms for cO ≤ 6 at. % for passivation layers with a thickness of 36 ± 2 nm. We subsequently reduce the thickness of the layers using an accurate wet etching method to ˜7 nm and deposit p- and n-type doped layers fabricating a device structure. After the deposition of the doped layers, τeff appears to be predominantly determined by the doped layers themselves and is less dependent on the cO of the a-SiOx:H layers. The results suggest that τeff is determined by the field-effect rather than by chemical passivation.

  15. Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

    Science.gov (United States)

    Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

    2015-10-01

    We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

  16. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  17. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    International Nuclear Information System (INIS)

    Heib, F.; Hempelmann, R.; Munief, W.M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-01-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ a and the receding θ r contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis

  18. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    Energy Technology Data Exchange (ETDEWEB)

    Heib, F., E-mail: f.heib@mx.uni-saarland.de [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Hempelmann, R. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany); Munief, W.M.; Ingebrandt, S. [Department of Informatics and Microsystem Technology, University of Applied Sciences, Kaiserslautern, 66482 Zweibrücken (Germany); Fug, F.; Possart, W. [Department of Adhesion and Interphases in Polymers, Saarland University, 66123 Saarbrücken (Germany); Groß, K.; Schmitt, M. [Department of Physical Chemistry, Saarland University, 66123 Saarbrücken (Germany)

    2015-07-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ{sub a} and the receding θ{sub r} contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple

  19. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  20. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  1. Silicon Wafer X-ray Mirror

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  2. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  3. Study of the semiconductor properties by irradiation, 8. Study of trapping center by. gamma. -ray on Si wafer

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Koji; Shioya, Hitoshi; Nagamatsu, Yasuhiko; Ogura, Shoji [Miyazaki Univ. (Japan). Faculty of Engineering

    1983-08-01

    In order to know the effects of ..gamma..-ray irradiation on n-type Si-wafers, the author did ..gamma..-ray irradiation experiments on n-type Si-wafers. They then observed the trapping center by using DLTS and ICTS equipments. The trapping center level, which is produced by ..gamma..-ray, is about 0.49 eV. In addition, the authors discuss the recombination rate.

  4. Ultra-thin silicon oxide layers on crystalline silicon wafers: Comparison of advanced oxidation techniques with respect to chemically abrupt SiO{sub 2}/Si interfaces with low defect densities

    Energy Technology Data Exchange (ETDEWEB)

    Stegemann, Bert, E-mail: bert.stegemann@htw-berlin.de [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Gad, Karim M. [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Balamou, Patrice [HTW Berlin - University of Applied Sciences, 12459 Berlin (Germany); Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Sixtensson, Daniel [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany); Vössing, Daniel; Kasemann, Martin [University of Freiburg, Department of Microsystems Engineering - IMTEK, 79110 Freiburg (Germany); Angermann, Heike [Helmholtz Center Berlin for Materials and Energy (HZB), 12489 Berlin (Germany)

    2017-02-15

    Highlights: • Fabrication of ultrathin SiO{sub 2} tunnel layers on c-Si. • Correlation of electronic and chemical SiO{sub 2}/Si interface properties revealed by XPS/SPV. • Chemically abrupt SiO{sub 2}/Si interfaces generate less interface defect states considerable. - Abstract: Six advanced oxidation techniques were analyzed, evaluated and compared with respect to the preparation of high-quality ultra-thin oxide layers on crystalline silicon. The resulting electronic and chemical SiO{sub 2}/Si interface properties were determined by a combined x-ray photoemission (XPS) and surface photovoltage (SPV) investigation. Depending on the oxidation technique, chemically abrupt SiO{sub 2}/Si interfaces with low densities of interface states were fabricated on c-Si either at low temperatures, at short times, or in wet-chemical environment, resulting in each case in excellent interface passivation. Moreover, the beneficial effect of a subsequent forming gas annealing (FGA) step for the passivation of the SiO{sub 2}/Si interface of ultra-thin oxide layers has been proven. Chemically abrupt SiO{sub 2}/Si interfaces have been shown to generate less interface defect states.

  5. Fabrication of novel AFM probe with high-aspect-ratio ultra-sharp three-face silicon nitride tips

    NARCIS (Netherlands)

    Vermeer, Rolf; Berenschot, Johan W.; Sarajlic, Edin; Tas, Niels Roelof; Jansen, Henricus V.

    In this paper we present the wafer-scale fabrication of molded AFM probes with high aspect ratio ultra-sharp three-plane silicon nitride tips. Using $\\langle$111$\\rangle$ silicon wafers a dedicated process is developed to fabricate molds in the silicon wafer that have a flat triangular bottom

  6. Low surface damage dry etched black silicon

    Science.gov (United States)

    Plakhotnyuk, Maksym M.; Gaudig, Maria; Davidsen, Rasmus Schmidt; Lindhard, Jonas Michael; Hirsch, Jens; Lausch, Dominik; Schmidt, Michael Stenbæk; Stamate, Eugen; Hansen, Ole

    2017-10-01

    Black silicon (bSi) is promising for integration into silicon solar cell fabrication flow due to its excellent light trapping and low reflectance, and a continuously improving passivation. However, intensive ion bombardment during the reactive ion etching used to fabricate bSi induces surface damage that causes significant recombination. Here, we present a process optimization strategy for bSi, where surface damage is reduced and surface passivation is improved while excellent light trapping and low reflectance are maintained. We demonstrate that reduction of the capacitively coupled plasma power, during reactive ion etching at non-cryogenic temperature (-20 °C), preserves the reflectivity below 1% and improves the effective minority carrier lifetime due to reduced ion energy. We investigate the effect of the etching process on the surface morphology, light trapping, reflectance, transmittance, and effective lifetime of bSi. Additional surface passivation using atomic layer deposition of Al2O3 significantly improves the effective lifetime. For n-type wafers, the lifetime reaches 12 ms for polished and 7.5 ms for bSi surfaces. For p-type wafers, the lifetime reaches 800 μs for both polished and bSi surfaces.

  7. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  8. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  9. Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

    Science.gov (United States)

    Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

    2018-03-01

    Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

  10. Comparison of pad detectors produced on different silicon materials after irradiation with neutrons, protons and pions

    International Nuclear Information System (INIS)

    Kramberger, G.; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M.

    2010-01-01

    A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of Φ eq =3x10 15 cm -2 . The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.

  11. Comparison of pad detectors produced on different silicon materials after irradiation with neutrons, protons and pions

    Energy Technology Data Exchange (ETDEWEB)

    Kramberger, G., E-mail: Gregor.Kramberger@ijs.s [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia); Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M. [Jozef Stefan Institute and Department of Physics, University of Ljubljana, SI-1000 Ljubljana (Slovenia)

    2010-01-01

    A set of 44 pad detectors produced on p- and n-type MCz and Fz wafers was irradiated with 23 GeV protons, 200 MeV pions and reactor neutrons up to the equivalent fluences of PHI{sub eq}=3x10{sup 15}cm{sup -2}. The evolution of the full depletion voltage and the leakage current were monitored during short- and long-term annealing. At selected representative annealing steps, charge collection measurements were performed for all samples with LHC speed electronics. Measurements of full depletion voltage, leakage current and charge collection efficiency were compared for different irradiation particles and silicon materials.

  12. Performance Test Results of a Single-sided Silicon Strip Detector with a Radioactive Source and a Proton Beam

    International Nuclear Information System (INIS)

    Ki, Y. I.; Kah, D. H.; Son, D. H.; Kang, H. D.; Kim, H. J.; Kim, H. O.; Bae, J. B.; Ryu, S.; Park, H.; Kim, K. R.

    2007-01-01

    Due to high intrinsic precision and high speed properties of a silicon material, the silicon detector has been used in various applications such as medical imaging detector, radiation detector, positioning detectors in space science and experimental particle physics. High technology, modern equipment, and deep expertise are required to design and fabricate good quality of silicon sensors. Only few facilities in the world can develop silicon sensors which meet requirements of sensor performances. That is one of main reasons that the silicon sensor is so expensive and it takes time to purchase the silicon sensor once it is ordered. We designed and fabricated AC-coupled single-sided silicon strip sensors and developed front-end electronics and DAQ system to read out sensor signals. The silicon strip sensors were fabricated on a 5-in. n-type silicon wafer which has an orientation, high resistivity (>5 kΩ · cm) and a thickness of 380 μm. We measured the signal-to-noise ratio (SNR) of each channel by using a radioactive source and a 45 MeV proton beam from the MC-50 cyclotron at the Korea Institute of Radiological and Medical Science (KIRAMS) in Seoul. We present the measurement results of the SNRs of the silicon strip sensor with a proton beam and radioactive sources

  13. Graphene electrodes for n-type organic field-effect transistors

    DEFF Research Database (Denmark)

    Henrichsen, Henrik Hartmann; Boggild, P.

    2010-01-01

    This work presents a convenient and contamination safe E-beam lithography process for microstructuring of graphene flakes. Exfoliated graphene flakes were deposited on oxidized silicon wafers and subsequently patterned by E-beam lithography, to be used as source and drain electrodes in an organic...

  14. Seedless electroplating on patterned silicon

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2006-01-01

    Nickel thin films have been electrodeposited without the use of an additional seed layer, on highly doped silicon wafers. These substrates conduct sufficiently well to allow deposition using a peripherical electrical contact on the wafer. Films 2 μm thick have been deposited using a nickel sulfamate

  15. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Science.gov (United States)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  16. Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells. [using p-n junctions on light receiving surface of base crystal

    Science.gov (United States)

    Chen, L. Y.; Loferski, J. J.

    1975-01-01

    Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

  17. Upgraded metallurgical-grade silicon solar cells with efficiency above 20%

    Energy Technology Data Exchange (ETDEWEB)

    Zheng, P.; Rougieux, F. E.; Samundsett, C.; Yang, Xinbo; Wan, Yimao; Macdonald, D. [Research School of Engineering, College of Engineering and Computer Science, The Australian National University, Canberra, Australian Capital Terrritory 2601 (Australia); Degoulange, J.; Einhaus, R. [Apollon Solar, 66 Cours Charlemagne, Lyon 69002 (France); Rivat, P. [FerroPem, 517 Avenue de la Boisse, Chambery Cedex 73025 (France)

    2016-03-21

    We present solar cells fabricated with n-type Czochralski–silicon wafers grown with strongly compensated 100% upgraded metallurgical-grade feedstock, with efficiencies above 20%. The cells have a passivated boron-diffused front surface, and a rear locally phosphorus-diffused structure fabricated using an etch-back process. The local heavy phosphorus diffusion on the rear helps to maintain a high bulk lifetime in the substrates via phosphorus gettering, whilst also reducing recombination under the rear-side metal contacts. The independently measured results yield a peak efficiency of 20.9% for the best upgraded metallurgical-grade silicon cell and 21.9% for a control device made with electronic-grade float-zone silicon. The presence of boron-oxygen related defects in the cells is also investigated, and we confirm that these defects can be partially deactivated permanently by annealing under illumination.

  18. Hydrogen diffusion at moderate temperatures in p-type Czochralski silicon

    International Nuclear Information System (INIS)

    Huang, Y.L.; Ma, Y.; Job, R.; Ulyashin, A.G.

    2004-01-01

    In plasma-hydrogenated p-type Czochralski silicon, rapid thermal donor (TD) formation is achieved, resulting from the catalytic support of hydrogen. The n-type counter doping by TD leads to a p-n junction formation. A simple method for the indirect determination of the diffusivity of hydrogen via applying the spreading resistance probe measurements is presented. Hydrogen diffusion in silicon during both plasma hydrogenation and post-hydrogenation annealing is investigated. The impact of the hydrogenation duration, annealing temperature, and resistivity of the silicon wafers on the hydrogen diffusion is discussed. Diffusivities of hydrogen are determined in the temperature range 270-450 deg. C. The activation energy for the hydrogen diffusion is deduced to be 1.23 eV. The diffusion of hydrogen is interpreted within the framework of a trap-limited diffusion mechanism. Oxygen and hydrogen are found to be the main traps

  19. Proton irradiation effects in silicon devices

    Energy Technology Data Exchange (ETDEWEB)

    Simoen, E; Vanhellemont, J; Alaerts, A [IMEC, Leuven (Belgium); and others

    1997-03-01

    Proton irradiation effects in silicon devices are studied for components fabricated in various substrates in order to reveal possible hardening effects. The degradation of p-n junction diodes increases in first order proportionally with the fluence, when submitted to 10 MeV proton irradiations in the range 5x10{sup 9} cm{sup -2} to 5x10{sup 11} cm{sup -2}. The damage coefficients for both p- and n-type Czochralski, Float-Zone and epitaxial wafers are reported. Charge-Coupled Devices fabricated in a 1.2 {mu}m CCD-CMOS technology are shown to be quite resistant to 59 MeV H{sup +} irradiations, irrespective of the substrate type. (author)

  20. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  1. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  2. Quasimetallic silicon micromachined photonic crystals

    International Nuclear Information System (INIS)

    Temelkuran, B.; Bayindir, Mehmet; Ozbay, E.; Kavanaugh, J. P.; Sigalas, M. M.; Tuttle, G.

    2001-01-01

    We report on fabrication of a layer-by-layer photonic crystal using highly doped silicon wafers processed by semiconductor micromachining techniques. The crystals, built using (100) silicon wafers, resulted in an upper stop band edge at 100 GHz. The transmission and defect characteristics of these structures were found to be analogous to metallic photonic crystals. We also investigated the effect of doping concentration on the defect characteristics. The experimental results agree well with predictions of the transfer matrix method simulations

  3. Proposed method of assembly for the BCD silicon strip vertex detector modules

    International Nuclear Information System (INIS)

    Lindenmeyer, C.

    1989-01-01

    The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

  4. Increasing the efficiency of silicon heterojunction solar cells and modules by light soaking

    KAUST Repository

    Kobayashi, Eiji; De Wolf, Stefaan; Levrat, Jacques; Descoeudres, Antoine; Despeisse, Matthieu; Haug, Franz-Josef; Ballif, Christophe

    2017-01-01

    Silicon heterojunction solar cells use crystalline silicon (c-Si) wafers as optical absorbers and employ bilayers of doped/intrinsic hydrogenated amorphous silicon (a-Si:H) to form passivating contacts. Recently, we demonstrated that such solar

  5. Optimization of the Surface Structure on Black Silicon for Surface Passivation.

    Science.gov (United States)

    Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

    2017-12-01

    Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

  6. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  7. Industrial n-type solar cells with >20% cell efficiency

    Energy Technology Data Exchange (ETDEWEB)

    Romijn, I.G.; Anker, J.; Burgers, A.R.; Gutjahr, A.; Koppes, M.; Kossen, E.J.; Lamers, M.W.P.E.; Heurtault, Benoit; Saynova-Oosterling, D.S.; Tool, C.J.J. [ECN Solar Energy, Petten (Netherlands)

    2013-03-15

    To realize high efficiencies at low costs, ECN has developed the n-Pasha solar cell concept. The n-Pasha cell concept is a bifacial solar cell concept on n-Cz base material, with which average efficiencies of above 20% have been demonstrated. In this paper recent developments at ECN to improve the cost of ownership (lower Euro/Wp) of the n-Pasha cell concept are discussed. Two main drivers for the manufacturing costs of n-type solar cells are addressed: the n-type Cz silicon material and the silver consumption. We show that a large resistivity range between 2 and 8 cm can be tolerated for high cell efficiency, and that the costs due to the silver metallization can be significantly reduced while increasing the solar cell efficiency. Combining the improved efficiency and cost reduction makes the n-Pasha cell concept a very cost effective solution to manufacture high efficient solar cells and modules.

  8. Silicon hybrid integration

    International Nuclear Information System (INIS)

    Li Xianyao; Yuan Taonu; Shao Shiqian; Shi Zujun; Wang Yi; Yu Yude; Yu Jinzhong

    2011-01-01

    Recently,much attention has concentrated on silicon based photonic integrated circuits (PICs), which provide a cost-effective solution for high speed, wide bandwidth optical interconnection and optical communication.To integrate III-V compounds and germanium semiconductors on silicon substrates,at present there are two kinds of manufacturing methods, i.e., heteroepitaxy and bonding. Low-temperature wafer bonding which can overcome the high growth temperature, lattice mismatch,and incompatibility of thermal expansion coefficients during heteroepitaxy, has offered the possibility for large-scale heterogeneous integration. In this paper, several commonly used bonding methods are reviewed, and the future trends of low temperature wafer bonding envisaged. (authors)

  9. Performance of silicon pad detectors after mixed irradiations with neutrons and fast charged hadrons

    Energy Technology Data Exchange (ETDEWEB)

    Kramberger, G. [Jozef Stefan Institute, Department of Physics, University of Ljubljana, Jamova 39, SI-1000 Ljubljana (Slovenia)], E-mail: Gregor.Kramberger@ijs.si; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M. [Jozef Stefan Institute, Department of Physics, University of Ljubljana, Jamova 39, SI-1000 Ljubljana (Slovenia)

    2009-10-11

    A large set of silicon pad detectors produced on MCz and FZ wafer of p- and n-type was irradiated in two steps, first by fast charged hadrons followed by reactor neutrons. In this way the irradiations resemble the real irradiation fields at LHC. After irradiations controlled annealing started in steps during which the evolution of full depletion voltage, leakage current and charge collection efficiency was monitored. The damage introduced by different irradiation particles was found to be additive. The most striking consequence of that is a decrease of the full depletion voltage for n-type MCz detectors after additional neutron irradiation. This confirms that effective donors introduced by charged hadron irradiation are compensated by acceptors from neutron irradiation.

  10. Performance of silicon pad detectors after mixed irradiations with neutrons and fast charged hadrons

    International Nuclear Information System (INIS)

    Kramberger, G.; Cindro, V.; Dolenc, I.; Mandic, I.; Mikuz, M.; Zavrtanik, M.

    2009-01-01

    A large set of silicon pad detectors produced on MCz and FZ wafer of p- and n-type was irradiated in two steps, first by fast charged hadrons followed by reactor neutrons. In this way the irradiations resemble the real irradiation fields at LHC. After irradiations controlled annealing started in steps during which the evolution of full depletion voltage, leakage current and charge collection efficiency was monitored. The damage introduced by different irradiation particles was found to be additive. The most striking consequence of that is a decrease of the full depletion voltage for n-type MCz detectors after additional neutron irradiation. This confirms that effective donors introduced by charged hadron irradiation are compensated by acceptors from neutron irradiation.

  11. Hybrid Integrated Platforms for Silicon Photonics

    Science.gov (United States)

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  12. Hybrid Integrated Platforms for Silicon Photonics

    Directory of Open Access Journals (Sweden)

    John E. Bowers

    2010-03-01

    Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  13. Field oxide radiation damage measurements in silicon strip detectors

    Energy Technology Data Exchange (ETDEWEB)

    Laakso, M [Particle Detector Group, Fermilab, Batavia, IL (United States) Research Inst. for High Energy Physics (SEFT), Helsinki (Finland); Singh, P; Shepard, P F [Dept. of Physics and Astronomy, Univ. Pittsburgh, PA (United States)

    1993-04-01

    Surface radiation damage in planar processed silicon detectors is caused by radiation generated holes being trapped in the silicon dioxide layers on the detector wafer. We have studied charge trapping in thick (field) oxide layers on detector wafers by irradiating FOXFET biased strip detectors and MOS test capacitors. Special emphasis was put on studying how a negative bias voltage across the oxide during irradiation affects hole trapping. In addition to FOXFET biased detectors, negatively biased field oxide layers may exist on the n-side of double-sided strip detectors with field plate based n-strip separation. The results indicate that charge trapping occurred both close to the Si-SiO[sub 2] interface and in the bulk of the oxide. The charge trapped in the bulk was found to modify the electric field in the oxide in a way that leads to saturation in the amount of charge trapped in the bulk when the flatband/threshold voltage shift equals the voltage applied over the oxide during irradiation. After irradiation only charge trapped close to the interface is annealed by electrons tunneling to the oxide from the n-type bulk. (orig.).

  14. Surface Passivation for Silicon Heterojunction Solar Cells

    NARCIS (Netherlands)

    Deligiannis, D.

    2017-01-01

    Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

  15. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  16. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    OpenAIRE

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  17. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  18. Electron drift time in silicon drift detectors: A technique for high precision measurement of electron drift mobility

    International Nuclear Information System (INIS)

    Castoldi, A.; Rehak, P.

    1995-01-01

    This paper presents a precise absolute measurement of the drift velocity and mobility of electrons in high resistivity silicon at room temperature. The electron velocity is obtained from the differential measurement of the drift time of an electron cloud in a silicon drift detector. The main features of the transport scheme of this class of detectors are: the high uniformity of the electron motion, the transport of the signal electrons entirely contained in the high-purity bulk, the low noise timing due to the very small anode capacitance (typical value 100 fF), and the possibility to measure different drift distances, up to the wafer diameter, in the same semiconductor sample. These features make the silicon drift detector an optimal device for high precision measurements of carrier drift properties. The electron drift velocity and mobility in a 10 kΩ cm NTD n-type silicon wafer have been measured as a function of the electric field in the range of possible operation of a typical drift detector (167--633 V/cm). The electron ohmic mobility is found to be 1394 cm 2 /V s. The measurement precision is better than 1%. copyright 1995 American Institute of Physics

  19. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  20. Indium tin oxide thin-films prepared by vapor phase pyrolysis for efficient silicon based solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Simashkevich, Alexei, E-mail: alexeisimashkevich@hotmail.com [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Serban, Dormidont; Bruc, Leonid; Curmei, Nicolai [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Hinrichs, Volker [Institut für Heterogene Materialsysteme, Helmholtz-Zentrum Berlin für Materialien und Energie GmbH, Lise-Meitner Campus, Hahn-Meitner-Platz 1, 14109 Berlin (Germany); Rusu, Marin [Institute of Applied Physics, 5 Academiei str., Chisinau, MD-2028, Republic of Moldova (Moldova, Republic of); Institut für Heterogene Materialsysteme, Helmholtz-Zentrum Berlin für Materialien und Energie GmbH, Lise-Meitner Campus, Hahn-Meitner-Platz 1, 14109 Berlin (Germany)

    2016-07-01

    The vapor phase pyrolysis deposition method was developed for the preparation of indium tin oxide (ITO) thin films with thicknesses ranging between 300 and 400 nm with the sheet resistance of 10–15 Ω/sq. and the transparency in the visible region of the spectrum over 80%. The layers were deposited on the (100) surface of the n-type silicon wafers with the charge carriers concentration of ~ 10{sup 15} cm{sup −3}. The morphology of the ITO layers deposited on Si wafers with different surface morphologies, e.g., smooth (polished), rough (irregularly structured) and textured (by inversed pyramids) was investigated. The as-deposited ITO thin films consist of crystalline columns with the height of 300–400 nm and the width of 50–100 nm. Photovoltaic parameters of mono- and bifacial solar cells of Cu/ITO/SiO{sub 2}/n–n{sup +} Si/Cu prepared on Si (100) wafers with different surface structures were studied and compared. A maximum efficiency of 15.8% was achieved on monofacial solar cell devices with the textured Si surface. Bifacial photovoltaic devices from 100 μm thick Si wafers with the smooth surface have demonstrated efficiencies of 13.0% at frontal illumination and 10% at rear illumination. - Highlights: • ITO thin films prepared by vapor phase pyrolysis on Si (100) wafers with a smooth (polished), rough (irregularly structured) and textured (by inversed pyramids) surface. • Monofacial ITO/SiO2/n-n+Si solar cells with an efficiency of 15.8% prepared and bifacial PV devices with front- and rear-side efficiencies up to 13% demonstrated. • Comparative studies of photovoltaic properties of solar cells with different morphologies of the Si wafer surface presented.

  1. Microscopic mapping of specific contact resistances and long-term reliability tests on 4H-silicon carbide using sputtered titanium tungsten contacts for high temperature device applications

    Science.gov (United States)

    Lee, S.-K.; Zetterling, C.-M.; Ostling, M.

    2002-07-01

    We report on the microscopic mapping of specific contact resistances (rhoc) and long-term reliability tests using sputtered titanium tungsten (TiW) ohmic contacts to highly doped n-type epilayers of 4H-silicon carbide. The TiW ohmic contacts showed good uniformity with low contact resistivity of 3.3 x10-5 Omega cm2. Microscopic mapping of the rhoc showed that the rhoc had a distribution that decreased from the center to the edge of the wafer. This distribution of the rhoc is caused by variation of the doping concentration of the wafer. Sacrificial oxidation at high temperature partially recovered inductively coupled plasma etch damage. TiW contacts with platinum and gold capping layers have stable specific contact resistance at 500 and 600 degC in a vacuum chamber for 308 h.

  2. Liquid phase epitaxial growth of silicon on porous silicon for photovoltaic applications

    International Nuclear Information System (INIS)

    Berger, S.; Quoizola, S.; Fave, A.; Kaminski, A.; Perichon, S.; Barbier, D.; Laugier, A.

    2001-01-01

    The aim of this experiment is to grow a thin silicon layer ( 2 atmosphere, and finally LPE silicon growth with different temperature profiles in order to obtain a silicon layer on the sacrificial porous silicon (p-Si). We observed a pyramidal growth on the surface of the (100) porous silicon but the coalescence was difficult to obtain. However, on a p-Si (111) oriented wafer, homogeneous layers were obtained. (orig.)

  3. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  4. Nano-ridge fabrication by local oxidation of silicon edges with silicon nitride as a mask

    NARCIS (Netherlands)

    Haneveld, J.; Berenschot, Johan W.; Maury, P.A.; Jansen, Henricus V.

    2005-01-01

    A method to fabricate nano-ridges over a full wafer is presented. The fabrication method uses local oxidation of silicon, with silicon nitride as a mask, and wet anisotropic etching of silicon. The realized structures are 7-20 nm wide, 40-100 nm high and centimeters long. All dimensions are easily

  5. Silicon nanowire-based solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S [Institute of Photonic Technology, Albert-Einstein-Strasse 9, D-07745 Jena (Germany)], E-mail: thomas.stelzner@ipht-jena.de

    2008-07-23

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm{sup 2} open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm{sup -2} were obtained.

  6. Silicon nanowire-based solar cells

    International Nuclear Information System (INIS)

    Stelzner, Th; Pietsch, M; Andrae, G; Falk, F; Ose, E; Christiansen, S

    2008-01-01

    The fabrication of silicon nanowire-based solar cells on silicon wafers and on multicrystalline silicon thin films on glass is described. The nanowires show a strong broadband optical absorption, which makes them an interesting candidate to serve as an absorber in solar cells. The operation of a solar cell is demonstrated with n-doped nanowires grown on a p-doped silicon wafer. From a partially illuminated area of 0.6 cm 2 open-circuit voltages in the range of 230-280 mV and a short-circuit current density of 2 mA cm -2 were obtained

  7. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  8. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  9. Luminescence of porous silicon doped by erbium

    International Nuclear Information System (INIS)

    Bondarenko, V.P.; Vorozov, N.N.; Dolgij, L.N.; Dorofeev, A.M.; Kazyuchits, N.M.; Leshok, A.A.; Troyanova, G.N.

    1996-01-01

    The possibility of the 1.54 μm intensive luminescence in the silicon dense porous layers, doped by erbium, with various structures is shown. Low-porous materials of both porous type on the p-type silicon and porous silicon with wood-like structure on the n + type silicon may be used for formation of light-emitting structures

  10. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  11. Technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE)

    Science.gov (United States)

    Wegrzecka, Iwona; Panas, Andrzej; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kozłowski, Roman; Sarnecki, Jerzy; Słysz, Wojciech; Szmigiel, Dariusz; Wegrzecki, Maciej; Zaborowski, Michał

    2013-07-01

    The paper discusses the technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE). The developed technology enables the fabrication of both planar and epiplanar p+-ν-n+ detector structures with an active area of up to 50 cm2. The starting material for epiplanar structures are silicon wafers with a high-resistivity n-type epitaxial layer ( ν layer - ρ < 3 kΩcm) deposited on a highly doped n+-type substrate (ρ< 0,02Ωcm) developed and fabricated at the Institute of Electronic Materials Technology. Active layer thickness of the epiplanar detectors (νlayer) may range from 10 μm to 150 μm. Imported silicon with min. 5 kΩcm resistivity is used to fabricate planar detectors. Active layer thickness of the planar detectors (ν) layer) may range from 200 μm to 1 mm. This technology enables the fabrication of both discrete and multi-junction detectors (monolithic detector arrays), such as single-sided strip detectors (epiplanar and planar) and double-sided strip detectors (planar). Examples of process diagrams for fabrication of the epiplanar and planar detectors are presented in the paper, and selected technological processes are discussed.

  12. Optical and microstructural characterization of porous silicon using photoluminescence, SEM and positron annihilation spectroscopy

    International Nuclear Information System (INIS)

    Cheung, C K; Nahid, F; Cheng, C C; Beling, C D; Fung, S; Ling, C C; Djurisic, A B; Pramanik, C; Saha, H; Sarkar, C K

    2007-01-01

    We have studied the dependence of porous silicon morphology and porosity on fabrication conditions. N-type (100) silicon wafers with resistivity of 2-5 Ω cm were electrochemically etched at various current densities and anodization times. Surface morphology and the thickness of the samples were examined by scanning electron microscopy (SEM). Detailed information of the porous silicon layer morphology with variation of preparation conditions was obtained by positron annihilation spectroscopy (PAS): the depth-defect profile and open pore interconnectivity on the sample surface has been studied using a slow positron beam. Coincidence Doppler broadening spectroscopy (CDBS) was used to study the chemical environment of the samples. The presence of silicon micropores with diameter varying from 1.37 to 1.51 nm was determined by positron lifetime spectroscopy (PALS). Visible luminescence from the samples was observed, which is considered to be a combination effect of quantum confinement and the effect of Si = O double bond formation near the SiO 2 /Si interface according to the results from photoluminescence (PL) and positron annihilation spectroscopy measurements. The work shows that the study of the positronium formed when a positron is implanted into the porous surface provides valuable information on the pore distribution and open pore interconnectivity, which suggests that positron annihilation spectroscopy is a useful tool in the porous silicon micropores' characterization

  13. Plasma immersion ion implantation of boron for ribbon silicon solar cells

    Directory of Open Access Journals (Sweden)

    Derbouz K.

    2013-09-01

    Full Text Available In this work, we report for the first time on the solar cell fabrication on n-type silicon RST (for Ribbon on Sacrificial Template using plasma immersion ion implantation. The experiments were also carried out on FZ silicon as a reference. Boron was implanted at energies from 10 to 15 kV and doses from 1015 to 1016 cm-2, then activated by a thermal annealing in a conventional furnace at 900 and 950 °C for 30 min. The n+ region acting as a back surface field was achieved by phosphorus spin-coating. The frontside boron emitter was passivated either by applying a 10 nm deposited SiOX plasma-enhanced chemical vapor deposition (PECVD or with a 10 nm grown thermal oxide. The anti-reflection coating layer formed a 60 nm thick SiNX layer. We show that energies less than 15 kV and doses around 5 × 1015 cm-2 are appropriate to achieve open circuit voltage higher than 590 mV and efficiency around 16.7% on FZ-Si. The photovoltaic performances on ribbon silicon are so far limited by the bulk quality of the material and by the quality of the junction through the presence of silicon carbide precipitates at the surface. Nevertheless, we demonstrate that plasma immersion ion implantation is very promising for solar cell fabrication on ultrathin silicon wafers such as ribbons.

  14. Potassium-doped n-type bilayer graphene

    Science.gov (United States)

    Yamada, Takatoshi; Okigawa, Yuki; Hasegawa, Masataka

    2018-01-01

    Potassium-doped n-type bilayer graphene was obtained. Chemical vapor deposited bilayer and single layer graphene on copper (Cu) foils were used. After etching of Cu foils, graphene was dipped in potassium hydroxide aqueous solutions to dope potassium. Graphene on silicon oxide was characterized by X-ray photoelectron spectroscopy (XPS), energy dispersive X-ray spectroscopy (EDX), and Raman spectroscopy. Both XPS and EDX spectra indicated potassium incorporation into the bilayer graphene via intercalation between the graphene sheets. The downward shift of the 2D peak position of bilayer graphene after the potassium hydroxide (KOH) treatment was confirmed in Raman spectra, indicating that the KOH-treated bilayer graphene was doped with electrons. Electrical properties were measured using Hall bar structures. The Dirac points of bilayer graphene were shifted from positive to negative by the KOH treatment, indicating that the KOH-treated bilayer graphene was n-type conduction. For single layer graphene after the KOH treatment, although electron doping was confirmed from Raman spectra, the peak of potassium in the X-ray photoelectron spectroscopy (XPS) spectrum was not detected. The Dirac points of single layer graphene with and without the KOH treatment showed positive.

  15. Progress in N-type Si Solar Cell and Module Technology for High Efficiency and Low Cost

    Energy Technology Data Exchange (ETDEWEB)

    Song, Dengyuan; Xiong, Jingfeng; Hu, Zhiyan; Li, Gaofei; Wang, Hongfang; An, Haijiao; Yu, Bo; Grenko, Brian; Borden, Kevin; Sauer, Kenneth; Cui, Jianhua; Wang, Haitao [Yingli Green Energy Holding Co., LTD, 071051 Boading (China); Roessler, T. [Yingli Green Energy Europe GmbH, Heimeranstr. 37, 80339 Munich (Germany); Bultman, J. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG Petten (Netherlands); Vlooswijk, A.H.G.; Venema, P.R. [Tempress Systems BV, Radeweg 31, 8171 Vaassen (Netherlands)

    2012-06-15

    A novel high efficiency solar cell and module technology, named PANDA, using crystalline n-type CZ Si wafers has moved into large-scale production at Yingli. The first commercial sales of the PANDA modules commenced in mid 2010. Up to 600MW of mass production capacity from crystal-Si growth, wafer slicing, cell processing and module assembly have been implemented by the end of 2011. The PANDA technology was developed specifically for high efficiency and low cost. In contrast to the existing n-type Si solar cell manufacturing methods in mass production, this new technology is largely compatible with a traditional p-type Si solar cell production line by conventional diffusion, SiNx coating and screen-printing technology. With optimizing all technologies, Yingli's PANDA solar cells on semi-square 6-inch n-type CZ wafers (cell size 239cm{sup 2}) have been improved to currently have an average efficiency on commercial production lines exceeding 19.0% and up to 20.0% in pilot production. The PANDA modules have been produced and were certified according to UL1703, IEC 61215 and IEC 61730 standards. Nearly two years of full production on scale-up lines show that the PANDA modules have a high efficiency and power density, superior high temperature performance, near zero initial light induced degradation, and excellent efficiency at low irradiance.

  16. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Directory of Open Access Journals (Sweden)

    Kae Dal Kwack

    2011-01-01

    Full Text Available A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  17. Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

    Science.gov (United States)

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

  18. Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

    Science.gov (United States)

    Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

    2011-01-01

    A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

  19. Laser plasma generation of hydrogen-free diamond-like carbon thin films on Zr-2.5Nb CANDU pressure tube materials and silicon wafers with a pulsed high-power CO2 laser

    International Nuclear Information System (INIS)

    Ebrahim, N.A.; Mouris, J.F.; Hoffmann, C.R.J.; Davis, R.W.

    1995-06-01

    We report the first experiments on the laser plasma deposition of hydrogen-free, diamond-like carbon (DLC) films on Zr-2.5Nb CANDU pressure-tube materials and silicon substrates, using the short-pulse, high-power, CO 2 laser in the High-Power Laser Laboratory at Chalk River Laboratories. The films were (AFM). The thin films show the characteristic signature of DLC films in the Raman spectra obtained using a krypton-ion (Kr + ) laser. The Vickers ultra-low-load microhardness tests show hardness of the coated surface of approximately 7000 Kg force mm -2 , which is consistent with the hardness associated with DLC films. AFM examination of the film morphology shows diamond-like crystals distributed throughout the film, with film thicknesses of up to 0.5 μm generated with 50 laser pulses. With significantly more laser pulses, it is expected that very uniform diamond-like films would be produced. These experiments suggest that it should be possible to deposit hydrogen-free, diamond-like films of relevance to nuclear reactor components with a high-power and high-repetition-rate laser facility. (author). 7 refs., 2 tabs., 15 figs

  20. Nuclear radiation detectors using high resistivity neutron transmutation doped silicon

    International Nuclear Information System (INIS)

    Gessner, T.; Irmer, K.

    1983-01-01

    A method for the production of semiconductor detectors based on high resistivity n-type silicon is described. The n-type silicon is produced by neutron irradiation of p-type silicon. The detectors are produced by planar technique. They are suitable for the spectrometry of alpha particles and for the pulse count measurement of beta particles at room temperature. (author)

  1. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  2. Silicon epitaxy on textured double layer porous silicon by LPCVD

    International Nuclear Information System (INIS)

    Cai Hong; Shen Honglie; Zhang Lei; Huang Haibin; Lu Linfeng; Tang Zhengxia; Shen Jiancang

    2010-01-01

    Epitaxial silicon thin film on textured double layer porous silicon (DLPS) was demonstrated. The textured DLPS was formed by electrochemical etching using two different current densities on the silicon wafer that are randomly textured with upright pyramids. Silicon thin films were then grown on the annealed DLPS, using low-pressure chemical vapor deposition (LPCVD). The reflectance of the DLPS and the grown silicon thin films were studied by a spectrophotometer. The crystallinity and topography of the grown silicon thin films were studied by Raman spectroscopy and SEM. The reflectance results show that the reflectance of the silicon wafer decreases from 24.7% to 11.7% after texturing, and after the deposition of silicon thin film the surface reflectance is about 13.8%. SEM images show that the epitaxial silicon film on textured DLPS exhibits random pyramids. The Raman spectrum peaks near 521 cm -1 have a width of 7.8 cm -1 , which reveals the high crystalline quality of the silicon epitaxy.

  3. SiC epitaxial layer growth in a novel multi-wafer VPE reactor

    Energy Technology Data Exchange (ETDEWEB)

    Burk, A.A. Jr.; O`Loughlin, M.J. [Northrop Grumman Advanced Technology Lab., Baltimore, MD (United States); Mani, S.S. [Northrop Grumman Science and Technology Center, Pittsburgh, PA (United States)

    1998-06-01

    Preliminary results are presented for SiC epitaxial layer growth employing a unique planetary SiC-VPE reactor. The high-throughput, multi-wafer (7 x 2-inch) reactor, was designed for atmospheric and reduced pressure operation at temperatures up to and exceeding 1600 C. Specular epitaxial layers have been grown in the reactor at growth rates from 3-5 {mu}m/hr. The thickest layer grown to data was 42 {mu}m. The layers exhibit minimum unintentional n-type doping of {proportional_to}1 x 10{sup 15} cm{sup -3}, room temperature mobilities of {proportional_to}1000 cm{sup 2}/Vs, and intentional n-type doping from {proportional_to}5 x 10{sup 15} cm{sup -3} to >1 x 10{sup 19} cm{sup -3}. Intrawafer thickness and doping uniformities of 4% and 7% (standard deviation/mean) have been obtained, respectively, on 35 mm diameter substrates. Recently, 3% thickness uniformity has been demonstrated on a 50 mm substrate. Within a run, wafer-to-wafer thickness deviation is {proportional_to}4-14%. Doping variation is currently larger, ranging as much as a factor of two from the highest to the lowest doped wafer. Continuing efforts to improve the susceptor temperature uniformity and reduce unintentional hydrocarbon generation to improve layer uniformity and reproducibility, are presented. (orig.) 18 refs.

  4. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  5. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  6. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  7. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  8. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  9. Reassessment of the recombination parameters of chromium in n- and p-type crystalline silicon and chromium-boron pairs in p-type crystalline silicon

    International Nuclear Information System (INIS)

    Sun, Chang; Rougieux, Fiacre E.; Macdonald, Daniel

    2014-01-01

    Injection-dependent lifetime spectroscopy of both n- and p-type, Cr-doped silicon wafers with different doping levels is used to determine the defect parameters of Cr i and CrB pairs, by simultaneously fitting the measured lifetimes with the Shockley-Read-Hall model. A combined analysis of the two defects with the lifetime data measured on both n- and p-type samples enables a significant tightening of the uncertainty ranges of the parameters. The capture cross section ratios k = σ n /σ p of Cr i and CrB are determined as 3.2 (−0.6, +0) and 5.8 (−3.4, +0.6), respectively. Courtesy of a direct experimental comparison of the recombination activity of chromium in n- and p-type silicon, and as also suggested by modelling results, we conclude that chromium has a greater negative impact on carrier lifetimes in p-type silicon than n-type silicon with similar doping levels.

  10. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  11. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  12. Polycrystalline Silicon Gettered by Porous Silicon and Heavy Phosphorous Diffusion

    Institute of Scientific and Technical Information of China (English)

    LIU Zuming(刘祖明); Souleymane K Traore; ZHANG Zhongwen(张忠文); LUO Yi(罗毅)

    2004-01-01

    The biggest barrier for photovoltaic (PV) utilization is its high cost, so the key for scale PV utilization is to further decrease the cost of solar cells. One way to improve the efficiency, and therefore lower the cost, is to increase the minority carrier lifetime by controlling the material defects. The main defects in grain boundaries of polycrystalline silicon gettered by porous silicon and heavy phosphorous diffusion have been studied. The porous silicon was formed on the two surfaces of wafers by chemical etching. Phosphorous was then diffused into the wafers at high temperature (900℃). After the porous silicon and diffusion layers were removed, the minority carrier lifetime was measured by photo-conductor decay. The results show that the lifetime's minority carriers are increased greatly after such treatment.

  13. Reduction of absorption loss in multicrystalline silicon via combination of mechanical grooving and porous silicon

    Energy Technology Data Exchange (ETDEWEB)

    Ben Rabha, Mohamed; Mohamed, Seifeddine Belhadj; Dimassi, Wissem; Gaidi, Mounir; Ezzaouia, Hatem; Bessais, Brahim [Laboratoire de Photovoltaique, Centre de Recherches et des Technologies de l' Energie, Technopole de Borj-Cedria, BP 95, 2050 Hammam-Lif (Tunisia)

    2011-03-15

    Surface texturing of silicon wafer is a key step to enhance light absorption and to improve the solar cell performances. While alkaline-texturing of single crystalline silicon wafers was well established, no efficient chemical solution has been successfully developed for multicrystalline silicon wafers. Thus, the use of alternative new methods for effective texturization of multicrystalline silicon is worth to be investigated. One of the promising texturing techniques of multicrystalline silicon wafers is the use of mechanical grooves. However, most often, physical damages occur during mechanical grooves of the wafer surface, which in turn require an additional step of wet processing-removal damage. Electrochemical surface treatment seems to be an adequate solution for removing mechanical damage throughout porous silicon formation. The topography of untreated and porous silicon-treated mechanically textured surface was investigated using scanning electron microscopy (SEM). As a result of the electrochemical surface treatment, the total reflectivity drops to about 5% in the 400-1000 nm wavelength range and the effective minority carrier diffusion length enhances from 190 {mu}m to about 230 {mu}m (copyright 2011 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  14. Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

    Science.gov (United States)

    Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

    2017-09-01

    The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

  15. Mass removal modes in the laser ablation of silicon by a Q-switched diode-pumped solid-state laser (DPSSL)

    International Nuclear Information System (INIS)

    Lim, Daniel J; Ki, Hyungson; Mazumder, Jyoti

    2006-01-01

    A fundamental study on the Q-switched diode-pumped solid-state laser interaction with silicon was performed both experimentally and numerically. Single pulse drilling experiments were conducted on N-type silicon wafers by varying the laser intensity from 10 8 -10 9 W cm -2 to investigate how the mass removal mechanism changes depending on the laser intensity. Hole width and depth were measured and surface morphology was studied using scanning electron microscopy. For the numerical model study, Ki et al's self-consistent continuous-wave laser drilling model (2001 J. Phys. D: Appl. Phys. 34 364-72) was modified to treat the solidification phenomenon between successive laser pulses. The model has the capabilities of simulating major interaction physics, such as melt flow, heat transfer, evaporation, homogeneous boiling, multiple reflections and surface evolution. This study presents some interesting results on how the mass removal mode changes as the laser intensity increases

  16. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  17. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  18. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  19. Silicon Nanowire Fabrication Using Edge and Corner Lithography

    NARCIS (Netherlands)

    Yagubizade, H.; Berenschot, Johan W.; Jansen, Henricus V.; Elwenspoek, Michael Curt; Tas, Niels Roelof

    2010-01-01

    This paper presents a wafer scale fabrication method of single-crystalline silicon nanowires (SiNWs) bound by <111> planes using a combination of edge and corner lithography. These are methods of unconventional nanolithography for wafer scale nano-patterning which determine the size of nano-features

  20. Extrinsic doping in silicon revisited

    KAUST Repository

    Schwingenschlögl, Udo

    2010-06-17

    Both n-type and p-type doping of silicon is at odds with the charge transfer predicted by Pauling electronegativities and can only be reconciled if we no longer regarding dopant species as isolated atoms but rather consider them as clusters consisting of the dopant and its four nearest neighbor silicon atoms. The process that gives rise to n-type and p-type effects is the charge redistribution that occurs between the dopant and its neighbors, as we illustrate here using electronic structure calculations. This view point is able to explain why conventional substitutional n-type doping of carbon has been so difficult.

  1. Extrinsic doping in silicon revisited

    KAUST Repository

    Schwingenschlö gl, Udo; Chroneos, Alexander; Grimes, R. W.; Schuster, Cosima

    2010-01-01

    Both n-type and p-type doping of silicon is at odds with the charge transfer predicted by Pauling electronegativities and can only be reconciled if we no longer regarding dopant species as isolated atoms but rather consider them as clusters consisting of the dopant and its four nearest neighbor silicon atoms. The process that gives rise to n-type and p-type effects is the charge redistribution that occurs between the dopant and its neighbors, as we illustrate here using electronic structure calculations. This view point is able to explain why conventional substitutional n-type doping of carbon has been so difficult.

  2. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  3. Industrially feasible, dopant-free, carrier-selective contacts for high-efficiency silicon solar cells

    KAUST Repository

    Yang, Xinbo

    2017-05-31

    Dopant-free, carrier-selective contacts (CSCs) on high efficiency silicon solar cells combine ease of deposition with potential optical benefits. Electron-selective titanium dioxide (TiO) contacts, one of the most promising dopant-free CSC technologies, have been successfully implemented into silicon solar cells with an efficiency over 21%. Here, we report further progress of TiO contacts for silicon solar cells and present an assessment of their industrial feasibility. With improved TiO contact quality and cell processing, a remarkable efficiency of 22.1% has been achieved using an n-type silicon solar cell featuring a full-area TiO contact. Next, we demonstrate the compatibility of TiO contacts with an industrial contact-firing process, its low performance sensitivity to the wafer resistivity, its applicability to ultrathin substrates as well as its long-term stability. Our findings underscore the great appeal of TiO contacts for industrial implementation with their combination of high efficiency with robust fabrication at low cost.

  4. Simulation optimizing of n-type HIT solar cells with AFORS-HET

    Science.gov (United States)

    Yao, Yao; Xiao, Shaoqing; Zhang, Xiumei; Gu, Xiaofeng

    2017-07-01

    This paper presents a study of heterojunction with intrinsic thin layer (HIT) solar cells based on n-type silicon substrates by a simulation software AFORS-HET. We have studied the influence of thickness, band gap of intrinsic layer and defect densities of every interface. Details in mechanisms are elaborated as well. The results show that the optimized efficiency reaches more than 23% which may give proper suggestions to practical preparation for HIT solar cells industry.

  5. First experimental results on active and slim-edge silicon sensors for XFEL

    International Nuclear Information System (INIS)

    Pancheri, L.; Benkechcache, M. E. A.; Betta, G.-F. Dalla; Xu, H.; Verzellesi, G.; Ronchin, S.; Boscardin, M.; Ratti, L.; Grassi, M.; Lodola, L.; Malcovati, P.; Vacchi, C.; Manghisoni, M.; Re, V.; Traversi, G.; Batignani, G.; Bettarini, S.; Casarosa, G.; Giorgi, M.; Forti, F.

    2016-01-01

    This work presents the first characterization results obtained on a pilot fabrication run of planar sensors, tailored for X-ray imaging applications at FELs, developed in the framework of INFN project PixFEL. Active and slim-edge p-on-n sensors are fabricated on n-type high-resistivity silicon with 450 μm thickness, bonded to a support wafer. Both diodes and pixelated sensors with a pitch of 110 μm are included in the design. Edge structures with different number of guard rings are designed to comply with the large bias voltage required by the application after accumulating an ionizing radiation dose as large as 1GGy. Preliminary results from the electrical characterization of the produced sensors, providing a first assessment of the proposed approach, are discussed. A functional characterization of the sensors with a pulsed infrared laser is also presented, demonstrating the validity of slim-edge configurations.

  6. Effect of Current Density on Optical Properties of Anisotropic Photoelectrochemical Etched Silicon (110)

    Science.gov (United States)

    Amirhoseiny, M.; Hassan, Z.; Ng, S. S.

    2012-08-01

    Photoelectrochemical etched Si layers were prepared on n-type (110) oriented silicon wafer. The photoluminescence (PL), Fourier transformed infrared (FTIR) absorption and Raman spectroscopies of etched Si (110) at two different current densities were studied. Both samples showed PL peak in the visible spectral range situated from 650 nm to 750 nm. The corresponding changes in Raman spectra at different current density are discussed. The blue shift in the PL and Raman peaks is consequent of the quantum confinement effect and defect states of surface Si nanocrystallites complexes and hydrogen atoms of the photoelectrochemical etched Si (110) samples. The attenuated total reflection (ATR) results show both hydrogen and oxygen related IR modes in the samples which can be used to explain the PL effect.

  7. Use of porous silicon to minimize oxidation induced stacking fault defects in silicon

    International Nuclear Information System (INIS)

    Shieh, S.Y.; Evans, J.W.

    1992-01-01

    This paper presents methods for minimizing stacking fault defects, generated during oxidation of silicon, include damaging the back of the wafer or depositing poly-silicon on the back. In either case a highly defective structure is created and this is capable of gettering either self-interstitials or impurities which promote nucleation of stacking fault defects. A novel method of minimizing these defects is to form a patch of porous silicon on the back of the wafer by electrochemical etching. Annealing under inert gas prior to oxidation may then result in the necessary gettering. Experiments were carried out in which wafers were subjected to this treatment. Subsequent to oxidation, the wafers were etched to remove oxide and reveal defects. The regions of the wafer adjacent to the porous silicon patch were defect-free, whereas remote regions had defects. Deep level transient spectroscopy has been used to examine the gettering capability of porous silicon, and the paper discusses the mechanism by which the porous silicon getters

  8. Fabrication of a silicon oxide stamp by edge lithography reinforced with silicon nitride for nanoimprint lithography

    NARCIS (Netherlands)

    Zhao, Yiping; Berenschot, Johan W.; de Boer, M.; de Boer, Meint J.; Jansen, Henricus V.; Tas, Niels Roelof; Huskens, Jurriaan; Elwenspoek, Michael Curt

    2008-01-01

    The fabrication of a stamp reinforced with silicon nitride is presented for its use in nanoimprint lithography. The fabrication process is based on edge lithography using conventional optical lithography and wet anisotropic etching of 110 silicon wafers. SiO2 nano-ridges of 20 nm in width were

  9. Characterization of 150μm thick epitaxial silicon detectors from different producers after proton irradiation

    International Nuclear Information System (INIS)

    Hoedlmoser, H.; Moll, M.; Haerkoenen, J.; Kronberger, M.; Trummer, J.; Rodeghiero, P.

    2007-01-01

    Epitaxial (EPI) silicon has recently been investigated for the development of radiation tolerant detectors for future high-luminosity HEP experiments. A study of 150μm thick EPI silicon diodes irradiated with 24GeV/c protons up to a fluence of 3x10 15 p/cm 2 has been performed by means of Charge Collection Efficiency (CCE) measurements, investigations with the Transient Current Technique (TCT) and standard CV/IV characterizations. The aim of the work was to investigate the impact of radiation damage as well as the influence of the wafer processing on the material performance by comparing diodes from different manufacturers. The changes of CCE, full depletion voltage and leakage current as a function of fluence are reported. While the generation of leakage current due to irradiation is similar in all investigated series of detectors, a difference in the effective doping concentration can be observed after irradiation. In the CCE measurements an anomalous drop in performance was found even for diodes exposed to very low fluences (5x10 13 p/cm 2 ) in all measured series. This result was confirmed for one series of diodes in TCT measurements with an infrared laser. TCT measurements with a red laser showed no type inversion up to fluences of 3x10 15 p/cm 2 for n-type devices whereas p-type diodes undergo type inversion from p- to n-type for fluences higher than ∼2x10 14 p/cm 2

  10. Effect of illumination on photoluminescence properties of porous silicon

    International Nuclear Information System (INIS)

    Naddaf, M.; Hamadeh, H.

    2008-11-01

    Porous silicon (PS) layers were formed by photo-electrochemical etching of both p-type and n-type single crystal wafers in HF based solution. During the etching process, the silicon wafer was illuminated by a halogen lamp light guided by an optical fiber through a monochromator or diode lasers at different power density and wavelengths (480,533,580 and 635 nm). The optical and structural properties of the prepared PS samples have been investigated by using temperature dependent photoluminescence (PL) spectroscopy, Fourier Transform Infrared (FTIR) spectroscopy, contact angle (CA) measurements, optical microscope and atomic force microscope (AFM). Beside the strong red-yellow PL band, a blue PL band has been observed only in the PS samples formed under the illumination with low power and short wavelengths (480-580 nm) light. In the near infrared (IR) spectral range, a new PL band at 850 nm was observed in p-type PS samples, which prepared under darkness or illumination with 635 nm of low power light. Temperature dependent PL measurements showed that, in contrast to the main IR PL band at around 1100 nm, the intensity of this new band increases on increasing the temperature. These changes in the PL properties was correlated with the illumination induced-structural and morphological modifications in the PS skeleton. In particular, the FTIR analysis showed that the chemical groups and bonds constituting the PS skeleton, such as, SiH, SiO bonds and silanol SiOH group play key role in deciding the PL emission intensity and blue shift. The study proved that the illumination parameters during the photo-electrochemical etching process can be utilized for tailoring a porous layer with novel optical and structural properties. (Authors)

  11. Effect of illumination on photoluminescence properties of porous silicon

    International Nuclear Information System (INIS)

    Naddaf, M.; Hamadeh, H.

    2009-01-01

    Porous silicon (PS) layers were formed by photo-electrochemical etching of both p-type and n-type single crystal wafers in HF based solution. During the etching process, the silicon wafer was illuminated by a halogen lamp light guided by an optical fiber through a monochromator or diode lasers at different power density and wavelengths (480,533,580 and 635 nm). The optical and structural properties of the prepared PS samples have been investigated by using temperature dependent photoluminescence (PL) spectroscopy, Fourier Transform Infrared (FTIR) spectroscopy, contact angle (CA) measurements, optical microscope and atomic force microscope (AFM). Beside the strong red-yellow PL band, a blue PL band has been observed only in the PS samples formed under the illumination with low power and short wavelengths (480-580 nm) light. In the near infrared (IR) spectral range, a new PL band at 850 nm was observed in p-type PS samples, which prepared under darkness or illumination with 635 nm of low power light. Temperature dependent PL measurements showed that, in contrast to the main IR PL band at around 1100 nm, the intensity of this new band increases on increasing the temperature. These changes in the PL properties was correlated with the illumination induced-structural and morphological modifications in the PS skeleton. In particular, the FTIR analysis showed that the chemical groups and bonds constituting the PS skeleton, such as, SiH, SiO bonds and silanol SiOH group play key role in deciding the PL emission intensity and blue shift. The study proved that the illumination parameters during the photo-electrochemical etching process can be utilized for tailoring a porous layer with novel optical and structural properties. (Authors)

  12. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  13. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  14. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  15. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  16. Study of irradiation induced defects in silicon

    International Nuclear Information System (INIS)

    Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

    2000-01-01

    Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

  17. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  18. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Silicon nanowire hybrid photovoltaics

    KAUST Repository

    Garnett, Erik C.; Peters, Craig; Brongersma, Mark; Cui, Yi; McGehee, Mike

    2010-01-01

    Silicon nanowire Schottky junction solar cells have been fabricated using n-type silicon nanowire arrays and a spin-coated conductive polymer (PEDOT). The polymer Schottky junction cells show superior surface passivation and open-circuit voltages compared to standard diffused junction cells with native oxide surfaces. External quantum efficiencies up to 88% were measured for these silicon nanowire/PEDOT solar cells further demonstrating excellent surface passivation. This process avoids high temperature processes which allows for low-cost substrates to be used. © 2010 IEEE.

  20. Silicon nanowire hybrid photovoltaics

    KAUST Repository

    Garnett, Erik C.

    2010-06-01

    Silicon nanowire Schottky junction solar cells have been fabricated using n-type silicon nanowire arrays and a spin-coated conductive polymer (PEDOT). The polymer Schottky junction cells show superior surface passivation and open-circuit voltages compared to standard diffused junction cells with native oxide surfaces. External quantum efficiencies up to 88% were measured for these silicon nanowire/PEDOT solar cells further demonstrating excellent surface passivation. This process avoids high temperature processes which allows for low-cost substrates to be used. © 2010 IEEE.

  1. Switchable static friction of piezoelectric composite-silicon wafer contacts

    NARCIS (Netherlands)

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  2. Switchable static friction of piezoelectric composite—silicon wafer contacts

    NARCIS (Netherlands)

    Van den Ende, D.A.; Fischer, H.R.; Groen, W.A.; Van der Zwaag, S.

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  3. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    post-fabrication wet-chemical etching in phosphoric acid. A MEFOUED1,2,*, M FATHI1, ... and RCA decontamination stages by putting them in a bath made of ... found to be decreasing after chemical attack as shown in figure 2. In order to ...

  4. Influence for high intensity irradiation on characteristics of silicon strip-detectors

    International Nuclear Information System (INIS)

    Anokhin, I.E.; Pugatch, V.M.; Zinets, O.S.

    1995-01-01

    Full text: Silicon strip detectors (SSD) are widely used for the coordinate determination of short-range as well as minimum ionizing particles with high spatial resolution. Submicron position sensitivity of strip-detectors for short-range particles has been studied by means of two dimensional analyses of charges collected by neighboring strips as well as by measurement of charge collection times [1]. Silicon strip detectors was also used for testing high energy electron beam [2]. Under large fluences the radiation defects are stored and such characteristics of strip-detectors as an accuracy of the coordinate determination and the registration efficiency are significantly changed. Radiation defects lead to a decrease of the lifetime and mobility of charge carriers and therefore to changes of conditions for the charge collection in detectors. The inhomogeneity in spatial distribution if defects and electrical field plays an important role in the charge collection. In this report the role of the diffusion and drift in the charge collection in silicon strip-detectors under irradiation up to 10 Mrad has been studied. The electric field distribution and its dependence on the radiation dose in the detector have been calculated. It is shown that for particles incident between adjacent strips the coordinate determination precision depends strongly on the detector geometry and the electric field distribution, particularly in the vicinity of strips. Measuring simultaneously the collected charges and collection times on adjacent strips one can essentially improve reliability of the coordinate determination for short-range particles. Usually SSD are fabricated on n-type wafers. It is well known that under high intensity irradiation n-Si material converts into p-Si as far as p-type silicon is more radiative hard than n-type silicon [3] it is reasonable to fabricate SSD using high resistivity p-Si. Characteristics of SSD in basis n-and P-Si have been compared and higher

  5. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  6. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  7. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  8. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  9. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  10. Compton recoil electron tracking with silicon strip detectors

    International Nuclear Information System (INIS)

    O'Neill, T.J.; Ait-Ouamer, F.; Schwartz, I.; Tumer, O.T.; White, R.S.; Zych, A.D.

    1992-01-01

    The application of silicon strip detectors to Compton gamma ray astronomy telescopes is described in this paper. The Silicon Compton Recoil Telescope (SCRT) tracks Compton recoil electrons in silicon strip converters to provide a unique direction for Compton scattered gamma rays above 1 MeV. With strip detectors of modest positional and energy resolutions of 1 mm FWHM and 3% at 662 keV, respectively, 'true imaging' can be achieved to provide an order of magnitude improvement in sensitivity to 1.6 x 10 - 6 γ/cm 2 -s at 2 MeV. The results of extensive Monte Carlo calculations of recoil electrons traversing multiple layers of 200 micron silicon wafers are presented. Multiple Coulomb scattering of the recoil electron in the silicon wafer of the Compton interaction and the next adjacent wafer is the basic limitation to determining the electron's initial direction

  11. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  12. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  13. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  14. Flexible Thermoelectric Generators on Silicon Fabric

    KAUST Repository

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  15. Low temperature spalling of silicon: A crack propagation study

    Energy Technology Data Exchange (ETDEWEB)

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

  16. LASER ABLATION OF MONOCRYSTALLINE SILICON UNDER PULSED-FREQUENCY FIBER LASER

    Directory of Open Access Journals (Sweden)

    V. P. Veiko

    2015-05-01

    Full Text Available Subject of research. The paper deals with research of the surface ablation for single-crystal silicon wafers and properties of materials obtained in response to silicon ablation while scanning beam radiation of pulse fiber ytterbium laser with a wavelenght λ = 1062 nm in view of variation of radiation power and scanning modes. Method. Wafers of commercial p-type conductivity silicon doped with boron (111, n-type conductivity silicon doped with phosphorus (100 have been under research with a layer of intrinsical silicon oxide having the thickness equal to several 10 s of nanometers and SiO2 layer thickness from 120 to 300 nm grown by thermal oxidation method. The learning system comprises pulse fiber ytterbium laser with a wavelenght λ = 1062 nm. The laser rated-power output is equal to 20 W, pulse length is 100 ns. Pulses frequency is in the range from 20 kHz to 100 kHz. Rated energy in the pulse is equal to 1.0 mJ. Scanning has been carried out by means of two axial scanning device driven by VM2500+ and controlled by personal computer with «SinMarkТМ» software package. Scanning velocity is in the range from 10 mm/s to 4000 mm/s, the covering varies from 100 lines per mm to 3000 lines per mm. Control of samples has been carried out by means of Axio Imager A1m optical microscope Carl Zeiss production with a high definition digital video camera. All experiments have been carried out in the mode of focused laser beam with a radiation spot diameter at the substrate equal to 50 μm. The change of temperature and its distribution along the surface have been evaluated by FLIR IR imager of SC7000 series. Main results. It is shown that ablation occurs without silicon melting and with plasma torch origination. The particles of ejected silicon take part in formation of silicon ions plasma and atmosphere gases supporting the plasmo-chemical growth of SiO2. The range of beam scanning modes is determined where the growth of SiO2 layer is observed

  17. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  18. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  19. Porous silicon carbide (SIC) semiconductor device

    Science.gov (United States)

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1996-01-01

    Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

  20. Fabrication of heterojunction solar cells by using microcrystalline hydrogenated silicon oxide film as an emitter

    International Nuclear Information System (INIS)

    Banerjee, Chandan; Sritharathikhun, Jaran; Konagai, Makoto; Yamada, Akira

    2008-01-01

    Wide gap, highly conducting n-type hydrogenated microcrystalline silicon oxide (μc-SiO : H) films were prepared by very high frequency plasma enhanced chemical vapour deposition at a very low substrate temperature (170 deg. C) as an alternative to amorphous silicon (a-Si : H) for use as an emitter layer of heterojunction solar cells. The optoelectronic properties of n-μc-SiO : H films prepared for the emitter layer are dark conductivity = 0.51 S cm -1 at 20 nm thin film, activation energy = 23 meV and E 04 = 2.3 eV. Czochralski-grown 380 μm thick p-type (1 0 0) oriented polished silicon wafers with a resistivity of 1-10 Ω cm were used for the fabrication of heterojunction solar cells. Photovoltaic parameters of the device were found to be V oc = 620 mV, J sc = 32.1 mA cm -2 , FF = 0.77, η = 15.32% (active area efficiency)

  1. Floating Silicon Method

    Energy Technology Data Exchange (ETDEWEB)

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  2. Hydrogen-induced structural changes in polycrystalline silicon as revealed by positron lifetime spectroscopy

    International Nuclear Information System (INIS)

    Arole, V.M.; Takwale, M.G.; Bhide, V.G.

    1989-01-01

    Hydrogen passivation of polycrystalline silicon wafer is carried out in order to reduce the deleterious effects of grain boundaries. A systematic variation is made in the process parameters implemented during hydrogen passivation and the results of room temperature resistivity measurements are reported. As an efficient tool to study the structure change, positron lifetime spectroscopic measurements are performed on original and hydrogenated polycrystalline silicon wafers and a systematic correlation is sought between the changes that take place in the electrical and structural properties of polycrystalline silicon wafer, brought about by hydrogen passivation. (author)

  3. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Directory of Open Access Journals (Sweden)

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  4. Silicon-micromachined microchannel plates

    CERN Document Server

    Beetz, C P; Steinbeck, J; Lemieux, B; Winn, D R

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of approx 0.5 to approx 25 mu m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposite...

  5. Organic n-type materials for charge transport and charge storage applications.

    Science.gov (United States)

    Stolar, Monika; Baumgartner, Thomas

    2013-06-21

    Conjugated materials have attracted much attention toward applications in organic electronics in recent years. These organic species offer many advantages as potential replacement for conventional materials (i.e., silicon and metals) in terms of cheap fabrication and environmentally benign devices. While p-type (electron-donating or hole-conducting) materials have been extensively reviewed and researched, their counterpart n-type (electron-accepting or electron-conducting) materials have seen much less popularity despite the greater need for improvement. In addition to developing efficient charge transport materials, it is equally important to provide a means of charge storage, where energy can be used on an on-demand basis. This perspective is focused on discussing a selection of representative n-type materials and the efforts toward improving their charge-transport efficiencies. Additionally, this perspective will also highlight recent organic materials for battery components and the efforts that have been made to improve their environmental appeal.

  6. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  7. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  8. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  9. The impact of silicon feedstock on the PV module cost

    NARCIS (Netherlands)

    del Coso, G.; del Cañizo, C.; Sinke, W.C.

    2010-01-01

    The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

  10. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  11. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  12. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  13. Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

    Science.gov (United States)

    Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

    2018-01-01

    Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

  14. Silicon microphotonic waveguides

    International Nuclear Information System (INIS)

    Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

    2004-01-01

    Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

  15. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  16. Xe{sup +} ion beam induced rippled structures on Si miscut wafers

    Energy Technology Data Exchange (ETDEWEB)

    Hanisch, Antje; Grenzer, Joerg [Forschungszentrum Dresden-Rossendorf, Dresden (Germany); Biermanns, Andreas; Pietsch, Ullrich [Institute of Physics, University of Siegen (Germany)

    2009-07-01

    We report on the influence of the initial roughness and crystallography of the substrate on the formation of self-organized ripple structures on semiconductors surfaces by noble gas ion bombardment. The Bradley-Harper theory predicts that an initial roughness is most important for starting the sputtering process which in the ends leads to the evolution of regular patterns. We produced periodic structures with intermediate Xe{sup +} ion energies (5-70 keV) at different incidence and azimuthal angles which lead to the assumption that also crystallography plays a role at the beginning of ripple evolution. Most of the previous investigations started from the original roughness of a polished silicon wafer. We used (001) silicon wafers with a miscut angle of 1 , 5 and 10 towards[110]. We studied the ripple formation keeping the ion beam parallel to the[111],[-1-11] or[-111] direction, i.e. parallel, antiparallel or perpendicular to the miscut direction[110]. The parallel and antiparallel case implies a variation of the incidence angle with increased roughness over the surface step terraces. The perpendicular orientation means almost no roughness. The results were compared to normal Si(001) and Si(111) wafers.

  17. Study on structural properties of epitaxial silicon films on annealed double layer porous silicon

    International Nuclear Information System (INIS)

    Yue Zhihao; Shen Honglie; Cai Hong; Lv Hongjie; Liu Bin

    2012-01-01

    In this paper, epitaxial silicon films were grown on annealed double layer porous silicon by LPCVD. The evolvement of the double layer porous silicon before and after thermal annealing was investigated by scanning electron microscope. X-ray diffraction and Raman spectroscopy were used to investigate the structural properties of the epitaxial silicon thin films grown at different temperature and different pressure. The results show that the surface of the low-porosity layer becomes smooth and there are just few silicon-bridges connecting the porous layer and the substrate wafer. The qualities of the epitaxial silicon thin films become better along with increasing deposition temperature. All of the Raman peaks of silicon films with different deposition pressure are situated at 521 cm -1 under the deposition temperature of 1100 °C, and the Raman intensity of the silicon film deposited at 100 Pa is much closer to that of the monocrystalline silicon wafer. The epitaxial silicon films are all (4 0 0)-oriented and (4 0 0) peak of silicon film deposited at 100 Pa is more symmetric.

  18. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  19. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  20. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  1. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  2. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  3. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  4. Covalent biofunctionalization of silicon nitride surfaces

    NARCIS (Netherlands)

    Arafat, A.; Giesbers, M.; Rosso, M.; Sudhölter, E.J.R.; Schroën, C.G.P.H.; White, R.G.; Li Yang,; Linford, M.R.; Zuilhof, H.

    2007-01-01

    Covalently attached organic monolayers on etched silicon nitride (SixN4; x 3) surfaces were prepared by reaction of SixN4-coated wafers with neat or solutions of 1-alkenes and 1-alkynes in refluxing mesitylene. The surface modification was monitored by measurement of the static water contact angle,

  5. Micromachining of buried micro channels in silicon

    NARCIS (Netherlands)

    de Boer, Meint J.; Tjerkstra, R.W.; Berenschot, Johan W.; Jansen, Henricus V.; Burger, G.J.; Burger, G.J.; Gardeniers, Johannes G.E.; Elwenspoek, Michael Curt; van den Berg, Albert

    A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the

  6. Low-temperature magnetotransport in Si/SiGe heterostructures on 300 mm Si wafers

    Science.gov (United States)

    Scappucci, Giordano; Yeoh, L.; Sabbagh, D.; Sammak, A.; Boter, J.; Droulers, G.; Kalhor, N.; Brousse, D.; Veldhorst, M.; Vandersypen, L. M. K.; Thomas, N.; Roberts, J.; Pillarisetty, R.; Amin, P.; George, H. C.; Singh, K. J.; Clarke, J. S.

    Undoped Si/SiGe heterostructures are a promising material stack for the development of spin qubits in silicon. To deploy a qubit into high volume manufacturing in a quantum computer requires stringent control over substrate uniformity and quality. Electron mobility and valley splitting are two key electrical metrics of substrate quality relevant for qubits. Here we present low-temperature magnetotransport measurements of strained Si quantum wells with mobilities in excess of 100000 cm2/Vs fabricated on 300 mm wafers within the framework of advanced semiconductor manufacturing. These results are benchmarked against the results obtained in Si quantum wells deposited on 100 mm Si wafers in an academic research environment. To ensure rapid progress in quantum wells quality we have implemented fast feedback loops from materials growth, to heterostructure FET fabrication, and low temperature characterisation. On this topic we will present recent progress in developing a cryogenic platform for high-throughput magnetotransport measurements.

  7. Fluorescence and thermoluminescence in silicon oxide films rich in silicon

    International Nuclear Information System (INIS)

    Berman M, D.; Piters, T. M.; Aceves M, M.; Berriel V, L. R.; Luna L, J. A.

    2009-10-01

    In this work we determined the fluorescence and thermoluminescence (TL) creation spectra of silicon rich oxide films (SRO) with three different silicon excesses. To study the TL of SRO, 550 nm of SRO film were deposited by Low Pressure Chemical Vapor Deposition technique on N-type silicon substrates with resistivity in the order of 3 to 5 Ω-cm with silicon excess controlled by the ratio of the gases used in the process, SRO films with Ro= 10, 20 and 30 (12-6% silicon excess) were obtained. Then, they were thermally treated in N 2 at high temperatures to diffuse and homogenize the silicon excess. In the fluorescence spectra two main emission regions are observed, one around 400 nm and one around 800 nm. TL creation spectra were determined by plotting the integrated TL intensity as function of the excitation wavelength. (Author)

  8. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  9. Electroless porous silicon formation applied to fabrication of boron-silica-glass cantilevers

    DEFF Research Database (Denmark)

    Teva, Jordi; Davis, Zachary James; Hansen, Ole

    2010-01-01

    This work describes the characterization and optimization of anisotropic formation of porous silicon in large volumes (0.5-1 mm3) of silicon by an electroless wet etching technique. The main goal is to use porous silicon as a sacrificial volume for bulk micromachining processes, especially in cases...... where etching of the full wafer thickness is needed. The porous silicon volume is formed by a metal-assisted etching in a wet chemical solution composed of hydrogen peroxide (30%), hydrofluoric acid (40%) and ethanol. This paper focuses on optimizing the etching conditions in terms of maximizing...... for bio-chemical sensors. The porous silicon volume is formed in an early step of the fabrication process, allowing easy handling of the wafer during all of the micromachining processes in the process flow. In the final process step, the porous silicon is quickly etched by immersing the wafer in a KOH...

  10. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2013-01-01

    (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

  11. Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

    Science.gov (United States)

    Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

    2018-05-01

    An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

  12. Roadmap for integration of InP based photonics and silicon electronics

    NARCIS (Netherlands)

    Williams, K.A.

    2015-01-01

    We identify the synergies and a roadmap for the intimate integration of InP photonic integrated circuits and Silicon electronic ICs using wafer-scale processes. Advantages are foreseen in terms of bandwidth, energy savings and package simplification.

  13. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    International Nuclear Information System (INIS)

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  14. Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

    Institute of Scientific and Technical Information of China (English)

    潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

    2011-01-01

    Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95% active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

  15. Effect of annealing on silicon heterojunction solar cells with textured ZnO:Al as transparent conductive oxide

    Directory of Open Access Journals (Sweden)

    Roca i Cabarrocas P.

    2012-07-01

    Full Text Available We report on silicon heterojunction solar cells using textured aluminum doped zinc oxide (ZnO:Al as a transparent conductive oxide (TCO instead of flat indium tin oxide. Double side silicon heterojunction solar cell were fabricated by radio frequency plasma enhanced chemical vapor deposition on high life time N-type float zone crystalline silicon wafers. On both sides of these cells we have deposited by radio frequency magnetron sputtering ZnO:Al layers of thickness ranging from 800 nm to 1400 nm. These TCO layers were then textured by dipping the samples in a 0.5% hydrochloric acid. External quantum efficiency as well as I-V under 1 sun illumination measurements showed an increase of the current for the cells using textured ZnO:Al. The cells were then annealed at 150 °C, 175 °C and 200 °C during 30 min in ambient atmosphere and characterized at each annealing step. The results show that annealing has no impact on the open circuit voltage of the devices but that up to a 175 °C it enhances their short circuit current, consistent with an overall enhancement of their spectral response. Our results suggest that ZnO:Al is a promising material to increase the short circuit current (Jsc while avoiding texturing the c-Si substrate.

  16. Impurity Precipitation, Dissolution, Gettering and Passivation in PV Silicon: Final Technical Report, 30 January 1998--29 August 2001

    Energy Technology Data Exchange (ETDEWEB)

    Weber, E. R.

    2002-02-01

    This report describes the major progress in understanding the physics of transition metals in silicon and their possible impact on the efficiency of solar cells that was achieved during the three-year span of this subcontract. We found that metal-silicide precipitates and dissolved 3d transition metals can be relatively easily gettered. Gettering and passivating treatments must take into account the individuality of each transition metal. Our studies demonstrated how significant is the difference between defect reactions of copper and iron. Copper does not significantly affect the minority-carrier diffusion length in p-type silicon, at least as long as its concentration is low, but readily precipitates in n-type silicon. Therefore, copper precipitates may form in the area of p-n junctions and cause shunts in solar cells. Fortunately, copper precipitates are present mostly in the chemical state of copper-silicide and can relatively easily be dissolved. In contrast, iron was found to form clusters of iron-oxides and iron-silicates in the wafers. These clusters are thermodynamically stable even in high temperatures and are extremely difficult to remove. The formation of iron-silicates was observed at temperatures over 900C.

  17. Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

    Science.gov (United States)

    Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

    2017-11-30

    Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

  18. Organization of silicon nanocrystals by localized electrochemical etching

    International Nuclear Information System (INIS)

    Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

    2009-01-01

    An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

  19. Selfsupported epitaxial silicon films

    International Nuclear Information System (INIS)

    Lazarovici, D.; Popescu, A.

    1975-01-01

    The methods of removing the p or p + support of an n-type epitaxial silicon layer using electrochemical etching are described. So far, only n + -n junctions have been processed. The condition of anodic dissolution for some values of the support and layer resistivity are given. By this method very thin single crystal selfsupported targets of convenient areas can be obtained for channeling - blocking experiments

  20. Methods and mechanisms of gettering of silicon structures in the production of integrated circuits

    Directory of Open Access Journals (Sweden)

    Pilipenko V. A.

    2013-05-01

    Full Text Available Increasing the degree of integration of hardware components imposes more stringent requirements for the reduction of the concentration of contaminants and oxidation stacking faults in the original silicon wafers with its preservation in the IC manufacturing process cycle. This causes high relevance of the application of gettering in modern microelectronic technology. The existing methods of silicon wafers gettering and the mechanisms of their occurrence are considered.

  1. Efficiency improvements by Metal Wrap Through technology for n-type Si solar cells and modules

    Energy Technology Data Exchange (ETDEWEB)

    Wenchao, Zhao; Jianming, Wang; Yanlong, Shen; Ziqian, Wang; Yingle, Chen; Shuquan, Tian; Zhiliang, Wan; Bo, Yu; Gaofei, Li; Zhiyan, Hu; Jingfeng, Xiong [Yingli Green Energy Holding Co., Ltd, 3399 North Chaoyang Avenue, Baoding (China); Guillevin, N.; Heurtault, B.; Aken, B.B. van; Bennett, I.J.; Geerligs, L.J.; Weeber, A.W.; Bultman, J.H. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    N-type Metal Wrap Through (n-MWT) is presented as an industrially promising back-contact technology to reach high performance of silicon solar cells and modules. It can combine benefits from both n-type base and MWT metallization. In this paper, the efficiency improvements of commercial industrial n-type bifacial Si solar cells (239 cm{sup 2}) and modules (60 cells) by the integration of the MWT technique are described. For the cell, after the optimization of integration, over 0.3% absolute efficiency gain was achieved over the similar non-MWT technology, and Voc gain and Isc gain up to 0.9% and 3.5%, respectively. These gains are mainly attributed to reduced shading loss and surface recombination. Besides the front pattern optimization, a 0.1m{Omega} reduction of Rs in via part will induce further 0.06% absolute efficiency improvement. For the module part, a power output of n-MWT module up to 279W was achieved, corresponding to a module efficiency of about 17.7%.

  2. Complementary p- and n-type polymer doping for ambient stable graphene inverter.

    Science.gov (United States)

    Yun, Je Moon; Park, Seokhan; Hwang, Young Hwan; Lee, Eui-Sup; Maiti, Uday; Moon, Hanul; Kim, Bo-Hyun; Bae, Byeong-Soo; Kim, Yong-Hyun; Kim, Sang Ouk

    2014-01-28

    Graphene offers great promise to complement the inherent limitations of silicon electronics. To date, considerable research efforts have been devoted to complementary p- and n-type doping of graphene as a fundamental requirement for graphene-based electronics. Unfortunately, previous efforts suffer from undesired defect formation, poor controllability of doping level, and subtle environmental sensitivity. Here we present that graphene can be complementary p- and n-doped by simple polymer coating with different dipolar characteristics. Significantly, spontaneous vertical ordering of dipolar pyridine side groups of poly(4-vinylpyridine) at graphene surface can stabilize n-type doping at room-temperature ambient condition. The dipole field also enhances and balances the charge mobility by screening the impurity charge effect from the bottom substrate. We successfully demonstrate ambient stable inverters by integrating p- and n-type graphene transistors, which demonstrated clear voltage inversion with a gain of 0.17 at a 3.3 V input voltage. This straightforward polymer doping offers diverse opportunities for graphene-based electronics, including logic circuits, particularly in mechanically flexible form.

  3. TXRF analysis of trace metals in thin silicon nitride films

    International Nuclear Information System (INIS)

    Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

    2000-01-01

    As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

  4. Drastic reduction in the surface recombination velocity of crystalline silicon passivated with catalytic chemical vapor deposited SiNx films by introducing phosphorous catalytic-doped layer

    International Nuclear Information System (INIS)

    Thi, Trinh Cham; Koyama, Koichi; Ohdaira, Keisuke; Matsumura, Hideki

    2014-01-01

    We improve the passivation property of n-type crystalline silicon (c-Si) surface passivated with a catalytic chemical vapor deposited (Cat-CVD) Si nitride (SiN x ) film by inserting a phosphorous (P)-doped layer formed by exposing c-Si surface to P radicals generated by the catalytic cracking of PH 3 molecules (Cat-doping). An extremely low surface recombination velocity (SRV) of 2 cm/s can be achieved for 2.5 Ω cm n-type (100) floating-zone Si wafers passivated with SiN x /P Cat-doped layers, both prepared in Cat-CVD systems. Compared with the case of only SiN x passivated layers, SRV decreases from 5 cm/s to 2 cm/s. The decrease in SRV is the result of field effect created by activated P atoms (donors) in a shallow P Cat-doped layer. Annealing process plays an important role in improving the passivation quality of SiN x films. The outstanding results obtained imply that SiN x /P Cat-doped layers can be used as promising passivation layers in high-efficiency n-type c-Si solar cells.

  5. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  6. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  7. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  8. Characterization of poly-aniline/silicon heterojunction for gamma dosimetry

    International Nuclear Information System (INIS)

    Laranjeira, Jane M.G.; Khoury, Helen J.; Azevedo, Walter M.; Silva Junior, Eronides F. da; Vasconcelos, Elder A.

    2000-01-01

    In this work, we have developed and characterized poly-aniline/silicon heterojunction diodes for dosimetry applications. The poly-aniline thin film (thickness in order of microns) was deposited on n-type Si (1 Ωcm) by spin-coating technique from soluble poly-aniline. Al electrode was evaporated on the back side of Si wafer and a circular gold electrode with an area of 0,0036 cm 2 was evaporated on the poly-aniline film. The UV-visible and infrared characterization of the poly-aniline solution and the poly-aniline film has also been done. The heterojunction presents good rectifying behavior at room temperature and the rectification ratio were found to be 51664 ±1,0 V under ambient conditions. The saturation current densities are of the order of 1,4 μA/cm 2 at -1,0 V. The forward current correspond to the negative polarity on the aluminum electrode side and the ideality factor of diodes was approximately 2. The rectifying characteristics of diodes was changed after interaction with gamma radiation ( 60 Co) and the results shows that this devices has potential for applications in dosimetry for doses in range of 0 to 4000 Gy. (author)

  9. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  10. Electron-selective contacts via ultra-thin organic interface dipoles for silicon organic heterojunction solar cells

    Science.gov (United States)

    Reichel, Christian; Würfel, Uli; Winkler, Kristina; Schleiermacher, Hans-Frieder; Kohlstädt, Markus; Unmüssig, Moritz; Messmer, Christoph A.; Hermle, Martin; Glunz, Stefan W.

    2018-01-01

    In the last years, novel materials for the formation of electron-selective contacts on n-type crystalline silicon (c-Si) heterojunction solar cells were explored as an interfacial layer between the metal electrode and the c-Si wafer. Besides inorganic materials like transition metal oxides or alkali metal fluorides, also interfacial layers based on organic molecules with a permanent dipole moment are promising candidates to improve the contact properties. Here, the dipole effect plays an essential role in the modification of the interface and effective work function of the contact. The amino acids L-histidine, L-tryptophan, L-phenylalanine, glycine, and sarcosine, the nucleobase adenine, and the heterocycle 4-hydroxypyridine were investigated as dipole materials for an electron-selective contact on the back of p- and n-type c-Si with a metal electrode based on aluminum (Al). Furthermore, the effect of an added fluorosurfactant on the resulting contact properties was examined. The performance of n-type c-Si solar cells with a boron diffusion on the front was significantly increased when L-histidine and/or the fluorosurfactant was applied as a full-area back surface field. This improvement was attributed to the modification of the interface and the effective work function of the contact by the dipole material which was corroborated by numerical device simulations. For these solar cells, conversion efficiencies of 17.5% were obtained with open-circuit voltages (Voc) of 625 mV and fill factors of 76.3%, showing the potential of organic interface dipoles for silicon organic heterojunction solar cells due to their simple formation by solution processing and their low thermal budget requirements.

  11. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    International Nuclear Information System (INIS)

    Hansen, M. G.; Bjorling, C. F.

    2013-01-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

  12. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    Energy Technology Data Exchange (ETDEWEB)

    Hansen, M. G.; Bjorling, C. F. [Topsil Semiconductor Materials A/S, Odense (Denmark)

    2013-07-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain.

  13. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  14. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  15. Signal development in irradiated silicon detectors

    CERN Document Server

    Kramberger, Gregor; Mikuz, Marko

    2001-01-01

    This work provides a detailed study of signal formation in silicon detectors, with the emphasis on detectors with high concentration of irradiation induced defects in the lattice. These defects give rise to deep energy levels in the band gap. As a consequence, the current induced by charge motion in silicon detectors is signifcantly altered. Within the framework of the study a new experimental method, Charge correction method, based on transient current technique (TCT) was proposed for determination of effective electron and hole trapping times in irradiated silicon detectors. Effective carrier trapping times were determined in numerous silicon pad detectors irradiated with neutrons, pions and protons. Studied detectors were fabricated on oxygenated and non-oxygenated silicon wafers with different bulk resistivities. Measured effective carrier trapping times were found to be inversely proportional to fuence and increase with temperature. No dependence on silicon resistivity and oxygen concentration was observ...

  16. CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

    Science.gov (United States)

    Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

    2016-01-13

    One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

  17. High-Efficiency Silicon/Organic Heterojunction Solar Cells with Improved Junction Quality and Interface Passivation.

    Science.gov (United States)

    He, Jian; Gao, Pingqi; Ling, Zhaoheng; Ding, Li; Yang, Zhenhai; Ye, Jichun; Cui, Yi

    2016-12-27

    Silicon/organic heterojunction solar cells (HSCs) based on conjugated polymers, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), and n-type silicon (n-Si) have attracted wide attention due to their potential advantages of high efficiency and low cost. However, the state-of-the-art efficiencies are still far from satisfactory due to the inferior junction quality. Here, facile treatments were applied by pretreating the n-Si wafer in tetramethylammonium hydroxide (TMAH) solution and using a capping copper iodide (CuI) layer on the PEDOT:PSS layer to achieve a high-quality Schottky junction. Detailed photoelectric characteristics indicated that the surface recombination was greatly suppressed after TMAH pretreatment, which increased the thickness of the interfacial oxide layer. Furthermore, the CuI capping layer induced a strong inversion layer near the n-Si surface, resulting in an excellent field effect passivation. With the collaborative improvements in the interface chemical and electrical passivation, a competitive open-circuit voltage of 0.656 V and a high fill factor of 78.1% were achieved, leading to a stable efficiency of over 14.3% for the planar n-Si/PEDOT:PSS HSCs. Our findings suggest promising strategies to further exploit the full voltage as well as efficiency potentials for Si/organic solar cells.

  18. Development of thin pixel detectors on epitaxial silicon for HEP experiments

    International Nuclear Information System (INIS)

    Boscardin, Maurizio; Calvo, Daniela; Giacomini, Gabriele; Wheadon, Richard; Ronchin, Sabina; Zorzi, Nicola

    2013-01-01

    The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10 16 n eq /cm 2 . Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics

  19. Development of thin pixel detectors on epitaxial silicon for HEP experiments

    Energy Technology Data Exchange (ETDEWEB)

    Boscardin, Maurizio, E-mail: boscardi@fbk.eu [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Calvo, Daniela [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Giacomini, Gabriele [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy); Wheadon, Richard [INFN and Dipartimento di Fisica, Università di Torino, Via Pietro Giuria, I-10125 Torino (Italy); Ronchin, Sabina; Zorzi, Nicola [FBK, CMM, Via Sommarive 18, I-38123 Povo, Trento (Italy)

    2013-08-01

    The foreseen luminosity of the new experiments in High Energy Physics will require that the innermost layer of vertex detectors will be able to sustain fluencies up to 10{sup 16} n{sub eq}/cm{sup 2}. Moreover, in many experiments there is a demand for the minimization of the material budget of the detectors. Therefore, thin pixel devices fabricated on n-type silicon are a natural choice to fulfill these requirements due to their rad-hard performances and low active volume. We present an R and D activity aimed at developing a new thin hybrid pixel device in the framework of PANDA experiments. The detector of this new device is a p-on-n pixel sensor realized starting from epitaxial silicon wafers and back thinned up to 50–100 μm after process completion. We present the main technological steps and some electrical characterization on the fabricated devices before and after back thinning and after bump bonding to the front-end electronics.

  20. Characterization of silicon sensor materials and designs for the CMS Tracker Upgrade

    CERN Document Server

    Dierlamm, Alexander Hermann

    2012-01-01

    During the high luminosity phase of the LHC (HL-LHC, starting around 2020) the inner tracking system of CMS will be exposed to harsher conditions than the current system was designed for. Therefore a new tracker is planned to cope with higher radiation levels and higher occupancies. Within the strip sensor developments of CMS a comparative survey of silicon materials and technologies is being performed in order to identify the baseline material for the future tracker. Hence, a variety of materials (float-zone, magnetic Czochralski and epitaxially grown silicon with thicknesses from 50$\\mu$m to 320$\\mu$m as p- and n-type) has been processed at one company (Hamamatsu Photonics K.K.), irradiated (proton, neutron and mixed irradiations up to 1.5e15n$_{eq}$/cm$^2$ and beyond) and tested under identical conditions. The wafer layout includes a variety of devices to investigate different aspects of sensor properties like simple diodes, test-structures, small strip sensors and a strip sensor array with varying strip p...

  1. Two-dimensional numerical simulation of boron diffusion for pyramidally textured silicon

    International Nuclear Information System (INIS)

    Ma, Fa-Jun; Duttagupta, Shubham; Shetty, Kishan Devappa; Meng, Lei; Hoex, Bram; Peters, Ian Marius; Samudra, Ganesh S.

    2014-01-01

    Multidimensional numerical simulation of boron diffusion is of great relevance for the improvement of industrial n-type crystalline silicon wafer solar cells. However, surface passivation of boron diffused area is typically studied in one dimension on planar lifetime samples. This approach neglects the effects of the solar cell pyramidal texture on the boron doping process and resulting doping profile. In this work, we present a theoretical study using a two-dimensional surface morphology for pyramidally textured samples. The boron diffusivity and segregation coefficient between oxide and silicon in simulation are determined by reproducing measured one-dimensional boron depth profiles prepared using different boron diffusion recipes on planar samples. The established parameters are subsequently used to simulate the boron diffusion process on textured samples. The simulated junction depth is found to agree quantitatively well with electron beam induced current measurements. Finally, chemical passivation on planar and textured samples is compared in device simulation. Particularly, a two-dimensional approach is adopted for textured samples to evaluate chemical passivation. The intrinsic emitter saturation current density, which is only related to Auger and radiative recombination, is also simulated for both planar and textured samples. The differences between planar and textured samples are discussed

  2. Low-temperature Au/a-Si wafer bonding

    International Nuclear Information System (INIS)

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  3. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  4. Silicon heterojunction solar cell passivation in combination with nanocrystalline silicon oxide emitters

    NARCIS (Netherlands)

    Gatz, H.A.; Rath, J.K.; Verheijen, M.A.; Kessels, W.M.M.; Schropp, R.E.I.

    2016-01-01

    Silicon heterojunction solar cells (SHJ) are well known for their high efficiencies, enabled by their remarkably high open-circuit voltages (VOC). A key factor in achieving these values is a good passivation of the crystalline wafer interface. One of the restrictions during SHJ solar cell production

  5. Mechanically flexible optically transparent porous mono-crystalline silicon substrate

    KAUST Repository

    Rojas, Jhonathan Prieto; Syed, Ahad A.; Hussain, Muhammad Mustafa

    2012-01-01

    For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

  6. Superacid Passivation of Crystalline Silicon Surfaces.

    Science.gov (United States)

    Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

    2016-09-14

    The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

  7. Transistors using crystalline silicon devices on glass

    Science.gov (United States)

    McCarthy, Anthony M.

    1995-01-01

    A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

  8. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  9. Silicon (100)/SiO2 by XPS

    Energy Technology Data Exchange (ETDEWEB)

    Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh; Vail, Michael A.; Dadson, Andrew; Engelhard, Mark H.; Linford, Matthew R.

    2013-09-25

    Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the base material for subsequent growth of templated carbon nanotubes.

  10. Bias-assisted KOH etching of macroporous silicon membranes

    International Nuclear Information System (INIS)

    Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

    2011-01-01

    This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

  11. Silicon Nanowire Field-effect Chemical Sensor

    OpenAIRE

    Chen, S.

    2011-01-01

    This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

  12. Air-stable n-type colloidal quantum dot solids

    KAUST Repository

    Ning, Zhijun; Voznyy, Oleksandr; Pan, Jun; Hoogland, Sjoerd H.; Adinolfi, Valerio; Xu, Jixian; Li, Min; Kirmani, Ahmad R.; Sun, Jonpaul; Minor, James C.; Kemp, Kyle W.; Dong, Haopeng; Rollny, Lisa R.; Labelle, André J.; Carey, Graham H.; Sutherland, Brandon R.; Hill, Ian G.; Amassian, Aram; Liu, Huan; Tang, Jiang; Bakr, Osman; Sargent, E. H.

    2014-01-01

    Colloidal quantum dots (CQDs) offer promise in flexible electronics, light sensing and energy conversion. These applications rely on rectifying junctions that require the creation of high-quality CQD solids that are controllably n-type (electron-rich) or p-type (hole-rich). Unfortunately, n-type semiconductors made using soft matter are notoriously prone to oxidation within minutes of air exposure. Here we report high-performance, air-stable n-type CQD solids. Using density functional theory we identify inorganic passivants that bind strongly to the CQD surface and repel oxidative attack. A materials processing strategy that wards off strong protic attack by polar solvents enabled the synthesis of an air-stable n-type PbS CQD solid. This material was used to build an air-processed inverted quantum junction device, which shows the highest current density from any CQD solar cell and a solar power conversion efficiency as high as 8%. We also feature the n-type CQD solid in the rapid, sensitive, and specific detection of atmospheric NO2. This work paves the way for new families of electronic devices that leverage air-stable quantum-tuned materials. © 2014 Macmillan Publishers Limited. All rights reserved.

  13. Air-stable n-type colloidal quantum dot solids

    KAUST Repository

    Ning, Zhijun

    2014-06-08

    Colloidal quantum dots (CQDs) offer promise in flexible electronics, light sensing and energy conversion. These applications rely on rectifying junctions that require the creation of high-quality CQD solids that are controllably n-type (electron-rich) or p-type (hole-rich). Unfortunately, n-type semiconductors made using soft matter are notoriously prone to oxidation within minutes of air exposure. Here we report high-performance, air-stable n-type CQD solids. Using density functional theory we identify inorganic passivants that bind strongly to the CQD surface and repel oxidative attack. A materials processing strategy that wards off strong protic attack by polar solvents enabled the synthesis of an air-stable n-type PbS CQD solid. This material was used to build an air-processed inverted quantum junction device, which shows the highest current density from any CQD solar cell and a solar power conversion efficiency as high as 8%. We also feature the n-type CQD solid in the rapid, sensitive, and specific detection of atmospheric NO2. This work paves the way for new families of electronic devices that leverage air-stable quantum-tuned materials. © 2014 Macmillan Publishers Limited. All rights reserved.

  14. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  15. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  16. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  17. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  18. n-Type Azaacenes Containing B←N Units.

    Science.gov (United States)

    Min, Yang; Dou, Chuandong; Tian, Hongkun; Geng, Yanhou; Liu, Jun; Wang, Lixiang

    2018-02-12

    We disclose a novel strategy to design n-type acenes through the introduction of boron-nitrogen coordination bonds (B←N). We synthesized two azaacenes composed of two B←N units and six/eight linearly annelated rings. The B←N unit significantly perturbed the electronic structures of the azaacenes: Unique LUMOs delocalized over the entire acene skeletons and decreased aromaticity of the B←N-adjacent rings. Most importantly, these B←N-containing azaacenes exhibited low-lying LUMO energy levels and high electron affinities, thus leading to n-type character. The solution-processed organic field-effect transistor based on one such azaacene exhibited unipolar n-type characteristics with an electron mobility of 0.21 cm 2  V -1  s -1 . © 2018 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Method of fabricating porous silicon carbide (SiC)

    Science.gov (United States)

    Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

    1995-01-01

    Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

  20. Silicone metalization

    Energy Technology Data Exchange (ETDEWEB)

    Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

    2008-12-09

    A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

  1. n-Type organic semiconductors in organic electronics.

    Science.gov (United States)

    Anthony, John E; Facchetti, Antonio; Heeney, Martin; Marder, Seth R; Zhan, Xiaowei

    2010-09-08

    Organic semiconductors have been the subject of intensive academic and commercial interest over the past two decades, and successful commercial devices incorporating them are slowly beginning to enter the market. Much of the focus has been on the development of hole transporting, or p-type, semiconductors that have seen a dramatic rise in performance over the last decade. Much less attention has been devoted to electron transporting, or so called n-type, materials, and in this paper we focus upon recent developments in several classes of n-type materials and the design guidelines used to develop them.

  2. Waveguide silicon nitride grating coupler

    Science.gov (United States)

    Litvik, Jan; Dolnak, Ivan; Dado, Milan

    2016-12-01

    Grating couplers are one of the most used elements for coupling of light between optical fibers and photonic integrated components. Silicon-on-insulator platform provides strong confinement of light and allows high integration. In this work, using simulations we have designed a broadband silicon nitride surface grating coupler. The Fourier-eigenmode expansion and finite difference time domain methods are utilized in design optimization of grating coupler structure. The fully, single etch step grating coupler is based on a standard silicon-on-insulator wafer with 0.55 μm waveguide Si3N4 layer. The optimized structure at 1550 nm wavelength yields a peak coupling efficiency -2.6635 dB (54.16%) with a 1-dB bandwidth up to 80 nm. It is promising way for low-cost fabrication using complementary metal-oxide- semiconductor fabrication process.

  3. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  4. A continuous Czochralski silicon crystal growth system

    Science.gov (United States)

    Wang, C.; Zhang, H.; Wang, T. H.; Ciszek, T. F.

    2003-03-01

    Demand for large silicon wafers has driven the growth of silicon crystals from 200 to 300 mm in diameter. With the increasing silicon ingot sizes, melt volume has grown dramatically. Melt flow becomes more turbulent as melt height and volume increase. To suppress turbulent flow in a large silicon melt, a new Czochralski (CZ) growth furnace has been designed that has a shallow melt. In this new design, a crucible consists of a shallow growth compartment in the center and a deep feeding compartment around the periphery. Two compartments are connected with a narrow annular channel. A long crystal may be continuously grown by feeding silicon pellets into the dedicated feeding compartment. We use our numerical model to simulate temperature distribution and velocity field in a conventional 200-mm CZ crystal growth system and also in the new shallow crucible CZ system. By comparison, advantages and disadvantages of the proposed system are observed, operating conditions are determined, and the new system is improved.

  5. Micro benchtop optics by bulk silicon micromachining

    Science.gov (United States)

    Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

    2000-01-01

    Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

  6. Study on 150μm thick n- and p-type epitaxial silicon sensors irradiated with 24 GeV/c protons and 1 MeV neutrons

    International Nuclear Information System (INIS)

    Kaska, Katharina; Moll, Michael; Fahrer, Manuel

    2010-01-01

    A study on 150μm epitaxial (EPI) n- and p-type silicon diodes irradiated with neutrons up to 8x10 15 n/cm 2 and protons up to 1.7x10 15 p/cm 2 has been performed by means of CV/IV, charge collection efficiency (CCE) and transient current technique (TCT) measurements. It is found that the effective space charge density increases three times faster after proton than after neutron irradiation with a slightly higher effective space charge generation rate for n-type material compared to p-type material. A drop in charge collection efficiency already at fluences of 1x10 12 n eq /cm 2 can be seen in n-type material, but is absent in p-type material. TCT measurements show space charge sign inversion from positive to negative charge in n-type material after neutron irradiation and from negative to positive space charge in p-type material after proton irradiation. No difference was found in the response of diodes manufactured by different producers out of the same wafer material.

  7. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  8. Electric transport in N-type Fe2O3

    NARCIS (Netherlands)

    Acket, G.A.; Volger, J.

    Resistivity, Seebeck-coefficient, Hall-coefficient and magneto-resistance of n-type single crystal ferric oxide (hematite), containing Sn4+ as an impurity, are reported. The resistivity does not show important anisotropy. The Hall- and magneto-resistance effects are probably related to the parasitic

  9. Study on the graphene/silicon Schottky diodes by transferring graphene transparent electrodes on silicon

    International Nuclear Information System (INIS)

    Wang, Xiaojuan; Li, Dong; Zhang, Qichong; Zou, Liping; Wang, Fengli; Zhou, Jun; Zhang, Zengxing

    2015-01-01

    Graphene/silicon heterostructures present a Schottky characteristic and have potential applications for solar cells and photodetectors. Here, we fabricated graphene/silicon heterostructures by using chemical vapor deposition derived graphene and n-type silicon, and studied the electronic and optoelectronic properties through varying their interface and silicon resistivity. The results exhibit that the properties of the fabricated configurations can be effectively modulated. The graphene/silicon heterostructures with a Si (111) interface and high resistivity show a better photovoltaic behavior and should be applied for high-performance photodetectors. With the combined atomic force microscopy and theoretical analysis, the possible origination is discussed. The work here should be helpful on exploring high-performance graphene/silicon photoelectronics. - Highlights: • Different graphene/silicon heterostructures were fabricated. • Electronic and optoelectronic properties of the heterostructures were studied. • Graphene/silicon heterostructures were further explored for photodetectors.

  10. Study on the graphene/silicon Schottky diodes by transferring graphene transparent electrodes on silicon

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Xiaojuan [MOE Key Laboratory of Advanced Micro-structured Materials & Shanghai Key Laboratory of Special Artificial Microstructure Materials and Technology, School of Physics Science and Engineering, Tongji University, Shanghai 200092 (China); School of Physics and Electronics, Henan University, Kaifeng 475004 (China); Li, Dong; Zhang, Qichong; Zou, Liping; Wang, Fengli [MOE Key Laboratory of Advanced Micro-structured Materials & Shanghai Key Laboratory of Special Artificial Microstructure Materials and Technology, School of Physics Science and Engineering, Tongji University, Shanghai 200092 (China); Zhou, Jun, E-mail: zhoujunzhou@tongji.edu.cn [Center for Phononics and Thermal Energy Science, School of Physics Science and Engineering, Tongji University, Shanghai 200092 (China); Zhang, Zengxing, E-mail: zhangzx@tongji.edu.cn [MOE Key Laboratory of Advanced Micro-structured Materials & Shanghai Key Laboratory of Special Artificial Microstructure Materials and Technology, School of Physics Science and Engineering, Tongji University, Shanghai 200092 (China)

    2015-10-01

    Graphene/silicon heterostructures present a Schottky characteristic and have potential applications for solar cells and photodetectors. Here, we fabricated graphene/silicon heterostructures by using chemical vapor deposition derived graphene and n-type silicon, and studied the electronic and optoelectronic properties through varying their interface and silicon resistivity. The results exhibit that the properties of the fabricated configurations can be effectively modulated. The graphene/silicon heterostructures with a Si (111) interface and high resistivity show a better photovoltaic behavior and should be applied for high-performance photodetectors. With the combined atomic force microscopy and theoretical analysis, the possible origination is discussed. The work here should be helpful on exploring high-performance graphene/silicon photoelectronics. - Highlights: • Different graphene/silicon heterostructures were fabricated. • Electronic and optoelectronic properties of the heterostructures were studied. • Graphene/silicon heterostructures were further explored for photodetectors.

  11. Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

    Directory of Open Access Journals (Sweden)

    Xiao Li

    2018-03-01

    Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

  12. Analysis of the silicon market: Will thin films profit?

    International Nuclear Information System (INIS)

    Sark, W.G.J.H.M. van; Brandsen, G.W.; Fleuster, M.; Hekkert, M.P.

    2007-01-01

    The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010

  13. Analysis of the silicon market: Will thin films profit?

    Energy Technology Data Exchange (ETDEWEB)

    Sark, W.G.J.H.M. van; Brandsen, G.W. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Science, Technology and Society; Fleuster, M. [Solland Solar Energy, Heerlen (Netherlands); Hekkert, M.P. [Copernicus Institute for Sustainable Development and Innovation, Utrecht University, Utrecht (Netherlands). Department of Innovation Studies

    2007-06-15

    The photovoltaic industry has been growing with astonishing rates over the past years. The supply of silicon to the wafer-based industry has recently become a problem. This paper presents a thorough analysis of the PV industry and quantifies the silicon shortage. It is expected that this leads to a decrease in production in 2006 rather than the usual increase. Due to a mismatch in expansion plans of silicon feedstock manufacturers and solar cell manufacturers, a large cell overcapacity will persist up to 2010. The thin-film PV market is expected to profit from the silicon shortage problem; its market share may substantially increase to about 25% in 2010. (author)

  14. Micro filtration membrane sieve with silicon micro machining for industrial and biomedical applications

    NARCIS (Netherlands)

    van Rijn, C.J.M.; Elwenspoek, Michael Curt

    1995-01-01

    With the use of silicon micromachining an inorganic membrane sieve for microfiltration is constructed, having a siliconnitride membrane layer with thickness typically 1 pm and perforations typically between 0.5 pm and 10 pm in diameter. As a support a -silicon wafer with openings of loo0 pm in

  15. Laser direct writing of oxide structures on hydrogen-passivated silicon surfaces

    DEFF Research Database (Denmark)

    Müllenborn, Matthias; Birkelund, Karen; Grey, Francois

    1996-01-01

    on amorphous and crystalline silicon surfaces in order to determine the depassivation mechanism. The minimum linewidth achieved is about 450 nm using writing speeds of up to 100 mm/s. The process is fully compatible with local oxidation of silicon by scanning probe lithography. Wafer-scale patterns can...

  16. Silicon-photonics light source realized by III-V/Si grating-mirror laser

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2010-01-01

    waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

  17. Porous silicon in solar cell structures : a review of achievements and modern directions of further use

    NARCIS (Netherlands)

    Yerokhov, VY; Melnyk, [No Value

    1999-01-01

    Porous silicon, which is being obtained by electrochemical etching of silicon wafers in electrolytes on the base of hydrofluoric acid, recently attracted the attention of specialists in photovoltaics even more due to a number of its unique properties. However, at present, acceptable results are

  18. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  19. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  20. Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

    Science.gov (United States)

    Pradeepkumar, Aiswarya; Zielinski, Marcin; Bosi, Matteo; Verzellesi, Giovanni; Gaskill, D. Kurt; Iacopi, Francesca

    2018-06-01

    Heteroepitaxial 3C-SiC films on silicon substrates are of technological interest as enablers to integrate the excellent electrical, electronic, mechanical, thermal, and epitaxial properties of bulk silicon carbide into well-established silicon technologies. One critical bottleneck of this integration is the establishment of a stable and reliable electronic junction at the heteroepitaxial interface of the n-type SiC with the silicon substrate. We have thus investigated in detail the electrical and transport properties of heteroepitaxial cubic silicon carbide films grown via different methods on low-doped and high-resistivity silicon substrates by using van der Pauw Hall and transfer length measurements as test vehicles. We have found that Si and C intermixing upon or after growth, particularly by the diffusion of carbon into the silicon matrix, creates extensive interstitial carbon traps and hampers the formation of a stable rectifying or insulating junction at the SiC/Si interface. Although a reliable p-n junction may not be realistic in the SiC/Si system, we can achieve, from a point of view of the electrical isolation of in-plane SiC structures, leakage suppression through the substrate by using a high-resistivity silicon substrate coupled with deep recess etching in between the SiC structures.