Sample records for CIRCUITOS DIGITALES (digital circuits)
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1

Diseño de Circuitos Digitales a Nivel de Registro empleando Diagramas ASM++/ Digital Circuit Design at Register Transfer Level using ASM++ Charts

de Pablo, Santiago; Cáceres, Santiago; Cebrián, Jesús A; Sanz, Francisco
2010-01-01

Resumen en español Este artículo muestra la estrecha relación que existe entre los diagramas de estado algorítmicos (ASM charts) y los modernos lenguajes de descripción de circuitos, ambos empleados en el diseño de circuitos digitales. Se proponen sustanciales mejoras sobre la notación actual con el objetivo de desarrollar un compilador capaz de procesar automáticamente estos diagramas y generar el código VHDL o Verilog correspondiente. El uso de esta metodología facilita el aprend (mas) izaje del diseño de circuitos digitales a nivel de transferencia entre registros (RTL). El lenguaje gráfico propuesto es fácil de aprender y es entendido sin dificultad por estudiantes universitarios, quienes lo emplean como parte de la metodología de diseño para producir circuitos digitales sobre dispositivos reconfigurables tipo FPGA y CPLD Resumen en inglés This article shows the close relationship between Algorithmic State Machines (ASM charts) and modern hardware description languages, both applied to digital electronic design. Important improvements on current notation have been proposed in order to develop a compiler capable of processing these charts and generating VHDL or Verilog code automatically, The use of this methodology facilitates the learning of electronic design at the register transfer level (RTL). The langu (mas) age proposed is easy to learn and comprehend with no much difficulty by university students who used it as part of design methodology to produce digital circuits on reconfigurable devices of the type FPGA and CPLD

Scientific Electronic Library Online (Spanish)

3

Usando el PSPICE orientado al analisis de los circuitos del controlador booster instalado en CVG Venalum/ USING THE PSPICE ORIENTED TO CIRCUITS ANALYSIS OF THE BOOSTER CONTROLLER INSTALLED IN CVG VENALUM

Fernández, Herman; Franco, Zulay Egilda
2009-06-01

Resumen en español El artículo muestra la utilidad del simulador de circuitos Pspice para comprender la operación del controlador de la Celda Booster instalado en CVG Venalum. El proceso de reducción de aluminio requiere de una fuente de corriente DC de gran potencia. El equipo de la celda Booster es capaz de alimentar la celda de reducción usando un rectificador de tiristores. El sistema tiene incorporado varias etapas de circuitos analógicos y digitales: las unidades de seguimiento, (mas) un integrador de voltaje, un regulador de corriente, un módulo de disparo, un atenuador de voltaje, un acondicionador de corriente y otros circuitos. Actualmente, la información técnica no es suficiente para comprender los circuitos en estado transitorio. Los ejemplos suministrados de Pspice representan un laboratorio virtual del sistema. Probando las simulaciones, observando las formas de ondas del voltaje, y determinando los componentes de estas señales, el equipo de técnicos tiene una mejor apreciación de los circuitos de la Celda Booster. Cuando es posible, los resultados de las simulaciones son comparados con las ecuaciones desarrolladas. Los resultados de las simulaciones pueden ser usados como soporte técnico durante las operaciones de mantenimiento. Resumen en inglés This paper shows the usefulness of the Pspice circuit simulator to understand the operation of the Booster-Cell controller installed in CVG Venalum. The aluminum reduction process requires of a high power DC current source. The Booster-Cell equipment is able to feed the reduction cell using a thyristor-rectifier. This system has incorporated several stages of analog and digital circuits: the buffer units, a voltage integrator, a current regulator, the gating module, an at (mas) tenuator voltage, a conditioner current amplifier and others circuits. Actually, the technical information not is enough to understand the transient-state response of these circuits. The considered Pspice examples represent a virtual laboratory of the system. Performing the simulations, observing the voltage waveforms, and determining waveforms components, the technical staffs have a better appreciation of Booster-Cell circuits. Whenever is possible, the simulation results are compared with theoretical ones gives by equations developed. The simulation results can be used as technical support during maintenance operations.

Scientific Electronic Library Online (Spanish)

4

Nuevas Tendencias del Cine Chileno tras la llegada del Cine Digital/ New Tendencies in Chilean Contemporary Cinema After the Implosion Of Digital Video

Larraín Pulido, Carolina
2010-07-01

Resumen en español La llegada de tecnologías digitales al país en pocos años transforma la escena de producción cinematográfica, no sólo modificando los costos y procesos implicados en la cadena de producción y exhibición cinematográfica, sino también posibilitando la gestación de una escena de producción de largometrajes digitales de bajo costo, que permite el surgimiento de una serie de nuevos realizadores, temáticas, estilos, formas de producción y circuitos de exhibición. (mas) El artículo Nuevas Tendencias del cine chileno tras la llegada del cine digital explora e intenta dar cuenta de este fenómeno reciente en el medio chileno, dando cuenta de cómo la inserción de la tecnología digital ha impactado sobre estas nuevas cinematografías, revisando nuevos usos, prácticas, representaciones y tendencias presentes en estas realizaciones Resumen en inglés Abstract During the past years, the insertion of digital technologies in Chile has greatly affected the nation's film scenario, not only modifying the chain of film production and exhibition, but also generating a production scene of low-budget digital feature film that has allowed the development of new directors, themes, styles and modes of production and exhibition. The present article analyzes this recent phenomenon in Chilean film industry, revising how the insertion (mas) of digital technologies has affected these new forms of cinema in terms of style, production practices, exhibition, purposes and main tendencies

Scientific Electronic Library Online (Spanish)

5

Circuito de recuperación de reloj CMOS completamente integrable, diferencial, de alta velocidad y bajo consumo de potencia/ A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

Pacheco Bautista, Daniel; Castillo Soria, Francisco Rubén; Linares Aranda, Mónico; Salim Maza, Manuel
2007-12-01

Resumen en español En los sistemas electrónicos de recuperación de información (discos duros, unidades de lectura y escritura de DVD y CD, etc.), así como en las comunicaciones digitales en banda base, los circuitos de recuperación de reloj (CRC) juegan un papel fundamental, extrayendo la señal de reloj implícita en los datos recibidos, dicha señal es necesaria para sincronizar el procesamiento posterior de la información. En la actualidad esta tarea es difícil de lograr, no solo (mas) por la naturaleza aleatoria de los datos, sino por su alta velocidad de transferencia. En este artículo se presenta el diseño de un circuito de recuperación de reloj integrable en tecnología CMOS de alto desempeño, que opera a 1.2Gbps y consume únicamente 17.4mW de una fuente de 3.3V. Las altas prestaciones se logran al realizar un diseño completamente diferencial, utilizando arquitectura PLL convencional, lógica en modo corriente, así como un novedoso oscilador controlado por voltaje (VCO) de anillo de solo dos etapas. El diseño fue realizado con parámetros de proceso CMOS AMS de 0.35µm. Los resultados de la simulación en Hspice comprueban el buen desempeño del circuito, logrando la adquisición en menos de 300ns. Resumen en inglés The clock recovery circuit (CRC) plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units) and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a (mas) high-performance integral CMOS technology clock recovery circuit (CRC) working at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL), current mode logic (MCML) and a novel two stage ring-based voltage controlled oscillator (VCO). The design used 0.35 µm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

Scientific Electronic Library Online (Spanish)

6

LAS CONCAVIDADES DE PRIMER ORDEN: EXPRESIÓN DEL MECANISMO ACTIVO DE MODELADO EN EL ALTIPLANO DE SANTA ROSA DE OSOS/ FIRST ORDER CONCAVITLES: EXPRESSION OF THE ACTIVE MECHANISM OF MODELING IN THE HIGHLAND OF SANTA ROSA DE OSOS

ARIAS L, LUIS ALBERTO
2007-06-01

Resumen en español El principio axiomático de considerar al relieve de la superficie terrestre como un sistema dinámico complejo con la cualidad de dejar testimonios de sus comportamientos pasados plantea el reto de la reconstrucción histórica de la evolución geomorfológica en las diferentes regiones. Un aspecto fundamental de la complejidad de los sistemas geomórficos es la existencia de historias muy diversas en regiones diferentes. En estudios previos se han delineado las directri (mas) ces generales del proceso evolutivo del relieve en el altiplano de Santa Rosa de Osos y se han identificado y descrito las generaciones de relieve asociadas a cada fase (Arias et al, 2000, 2002, 2006). Si el relieve de una región es en lo fundamental un producto histórico, es pertinente la pregunta acerca de los tipos de relieve que están siendo modelados actualmente. En otros términos más específicos: ¿Cuales son los mecanismos activos de modelado del relieve y las geoformas resultantes en el altiplano de Santa Rosa de Osos? Intentar responder satisfactoriamente este interrogante constituye el objetivo central del ensayo. Las concavidades semicirculares encajadas en los flancos de las colinas del ASRO constituyen la generación de relieve en proceso activo de modelado en esta unidad de relieve mayor de la cordillera Central. Inicialmente se presenta una descripción de estas geoformas con base en las características morfométricas de sus elementos constitutivos (flancos, fondo plano y cierre terminal). La configuración mórfica de las concavidades expresa un proceso de evolución convergente; su diversidad mórfica se interpreta como estados de desarrollo mórfico distintos. La diversidad mórfica de las concavidades se despliega en las fases embrionarias y tempranas de su desarrollo expresando así una trayectoria de evolución divergente, mientras en las fases avanzadas se hace explícito un proceso de convergencia mórfica, acorde con una evolución convergente. Las hipótesis cualitativas postuladas en este ensayo acerca del modelado de las concavidades de primer orden emplea parámetros morfométricos factibles de cuantificar (pendientes, longitud y perfil de los flancos; área, gradiente y forma de la línea perimetral de los fondos planos; grado de encajamiento del fondo plano). Las hipótesis cualitativas podrán someterse al análisis cuantitativo en el momento que los modelos digitales de elevación (MDE) disponibles tengan la resolución espacial adecuada. El ensayo aborda igualmente la investigación del mecanismo de modelado. Este mecanismo opera como una sucesión de circuitos de retroalimentación positiva, inestables por su naturaleza, los cuales al “romperse” (cruzar su umbral de estabilidad) generan un conjunto de procesos y geoformas transitorias, tales como: · La transformación de un flujo hídrico interno de carácter intergranular en un flujo concentrado. · La transformación de una “erosión química” interna, eficiente para evacuar materiales iónicos, especialmente sílice, en una “erosión física” interna que evacua material particulado (arcillas, limos y arenas), en franjas alargadas del perfil de meteorización. · Procesos de tubificación que generan túneles y chimeneas al interior de los perfiles de meteorización. · Finalmente, el colapso de los sobretechos de estas geoformas internas, con lo cual, el proceso morfogenético pasa de una fase subterránea a otra con expresión superficial. Los procesos identificados en este estudio involucran la disolución iónica de arcillas caoliníticas presentes en perfiles de meteorización de la cuarzodiorita del batolito Antioqueño. Las tasas de los procesos de disolución de arcillas y de formación de túneles y chimeneas se desconocen; ahondar en estos tópicos es una necesidad apremiante por sus consecuencias negativas en los proyectos infraestructurales (presas hidráulicas, carreteras) y en las actividades agropecuarias. Resumen en inglés To consider the relief of the terrestrial surface as a complex dynamic system with the quality of leaving testimonies of its last behaviors is the axiomatic principle that presents the challenge of historical reconstruction of landforms in different regions. A fundamental aspect of the complexity of geomorphic systems is the existence of diverse histories in different regions. In previous studies they have been delineated the general guidelines of the evolutionary process (mas) of the relief in the uplifted erosion surface of Santa Rosa de Osos “altiplano”; the relief generations associated to each phase have been previously identified and described (Arias et al, 2000, 2002, 2006). If the relief of a region is fundamentally a historical product, it has relevance the question about the relief types that are being actively modeled. In more specific terms, which the active mechanisms of modeling are? and which the resulting geomorphic structures in Santa Rosa de Osos highlands are? Trying to respond this query satisfactorily constitutes the central objective of this essay. Semicircular fitted concavities in the flanks of the hills of the ASRO constitute the active relief generation. A description of morphometric characteristics of its constituent elements (flanks, plane bottom and terminal closing) is presented initially. The geomorphic configuration of these structures expresses a process of convergent evolution; the diversity of them is interpreted as different states of morphic development. Geomorphic diversity operates in the embryonic and early phases of modeling of first order concavities and express a divergent evolution while in the advanced phases it becomes explicit a process of convergent evolution. Postulated qualitative hypotheses about the modeling of first order concavities use quantifiable parameters (slopes, longitude and profile type of the flanks; area, gradient and its forms of perimeter line of the plane bottom; degree of fit of the plane bottom). The qualitative hypotheses could be undergone quantitative analysis in the moment that digital models of elevation (MDE) available have the appropriate spatial resolution. The essay approaches the investigation of the mechanisms of modeling of these geomorphic structures. These mechanisms operate like a succession of positive feedback circuits, unstable for its nature, which when are broken (to cross its threshold of stability) generates a process group and transient landforms, such as: · The transformation of an intergranular internal flow in a concentrated flow. · The transformation of an efficient internal chemical erosion to evacuate ionic materials -especially sílica - in internal physical erosion that evacuates particle material (clays, silts and sands). · Piping process generates tunnels and chimneys into weathering profiles. · Collapses of recovering materials of tunnels and chimneys generate a systematic cluster of hollows along axial concavities. As a consequence, morphogenetic processes shift from underground to superficial conditions. Identified processes in this study involve dissolution of kaolinitic clays in weathering profiles derived from granitic rocks. The rates of kaolinitic dissolution and formation of tunnels and chimneys are ignored; however, to deepen in this topic is an urgent necessity for their negative consequences in the infrastructural projects (dams, highways) and agricultural activities.

Scientific Electronic Library Online (Spanish)

7

Tunable dual-band printed tab monopole antennas for wireless communications

Valenzuela Valdés, Juan; García Fernández, Miguel Ángel; Martínez González, Antonio Manuel; Sánchez Hernández, David

The advance of communication systems requires new antenna designs to comply with the ever-increasing demands of the wireless market. The antenna designs are being conditioned by miniaturization and migration to new frequencies (IEEE 802.11a/g), while keeping compatibility with other systems poses ye...

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8

Tunable dual-band printed tab monopole antennas for wireless communications

García Fernández, Miguel Ángel; Martínez González, Antonio Manuel; Sánchez Hernández, David; Valenzuela Valdés, Juan Francisco

The advance of communication systems requires new antenna designs to comply with the ever-increasing demands of the wireless market. The antenna designs are being conditioned by miniaturization and migration to new frequencies (IEEE 802.11a/g), while keeping compatibility with other systems poses ye...

DRIVER (Spanish)

9

Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Angel

Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips gives a systematic methodology for designing ΣΔ Modulators (ΣΔMs), specially those of the bandpass type, realized in digital CMOS technologies by using switched-current (SI) circuits. For this ...

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10

Switched-Current Bandpass Sigma-Delta Modulators for AM Digital Radio Receivers

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Medeiro, Fernando; Río Fernández, Rocío del; Rodríguez Vázquez, Angel

This paper discusses the use of switched-current (SI) circuits to design Band-Pass ΣΔ Modulators (BP-ΣΔMs) suitable for AM digital radio receivers. First of all, the paper briefly outlines the concept and principles of BP-ΣΔMs, and introduces two modulator architectures which are obtained by applyin...

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11

Sistema de control automático del enfriamiento de frutos

Olías Jiménez, José Manuel; Sanz Martínez, Luis Carlos; Pérez Rubio, Ana Gracia; Sánchez López, M.ª Carmen
2000-12-01

Digital.CSIC (Spain)

12

Simulation-based High-level Synthesis of Pipeline Analog-to-Digital Converters

Ruiz Amaya, Jesús; Rosa Utrera, José Manuel de la; Delgado Restituto, Manuel

This paper presents a toolbox for thetime-domain simulation and optimization-basedhigh-level synthesis of pipeline analog-to-digital converters in MATLAB®. Behavioral models of building blocks, including their critical error mechanisms, are described and incorporated into SIMULINK® as C-compiled S...

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13

Serial architecture for fuzzy controllers: hardware implementation using analog/digital VLSI techniques

Huertas, José Luis; Sánchez-Solano, Santiago; Barriga, Angel; Baturone, M.ª Iluminada

A new architecture is presented for the implementation of fuzzy systems using analog-digital techniques. This architectureis directed towards allowing the implementation of many rules on the same chip, including the fuzzy inference engine and the defuzzifier. This approach is based on a total or pa...

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14

Practical implementation of the spatial images technique for the analysis of shielded multilayered printed circuits

Gómez Díaz, Juan Sebastián; Martínez Mendoza, Mónica; Pérez Soler, Francisco Javier; Quesada Pereira, Fernando Daniel

In this paper, a practical implementation of the spatialimages technique for the analysis of shielded multilayered printedcircuits inside convex cavities is proposed. A new method is introducedin order to automatically locate the images surrounding thestructure in order to impose the appropriate...

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15

Practical implementation of the spatial images technique for the analysis of shielded multilayered printed circuits

Gómez Díaz, Juan Sebastián; Martínez Mendoza, Mónica; Pérez Soler, Francisco Javier; Quesada Pereira, Fernando Daniel

In this paper, a practical implementation of the spatialimages technique for the analysis of shielded multilayered printedcircuits inside convex cavities is proposed. A new method is introducedin order to automatically locate the images surrounding thestructure in order to impose the appropriate...

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16

Numerical evaluation of the green’s functions for cylindrical enclosures by a new spatial images method.

Quesada Pereira, Fernando Daniel; Vera Castejón, Pedro; Cañete Rebenaque, David; Pascual García, Juan; Álvarez Melcón, Alejandro

In this paper, a spatial images technique is usedto efficiently calculate the mixed potential Green’s functionsassociated to magnetic sources when they are placed inside acircular cylindrical cavity. The technique places magnetic dipoleimages and charges outside the cylindrical region. Their str...

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17

Numerical evaluation of the green’s functions for cylindrical enclosures by a new spatial images method.

Quesada Pereira, Fernando Daniel; Vera Castejón, Pedro; Cañete Rebenaque, David; Pascual García, Juan; Álvarez Melcón, Alejandro

In this paper, a spatial images technique is usedto efficiently calculate the mixed potential Green’s functionsassociated to magnetic sources when they are placed inside acircular cylindrical cavity. The technique places magnetic dipoleimages and charges outside the cylindrical region. Their str...

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18

Neuropatología de la epilepsia del lóbulo temporal. Alteraciones primarias y secundarias de los circuitos corticales y epileptogenicidad | The neuropathology of temporal lobe epilepsy: primary and secondary changes in the cortical circuits and epileptogenicity

De Felipe-Oroquieta, Javier; Arellano, Jon I.; Alonso, L; Muñoz, A

Presentado en el I Congreso de la Liga Española contra la Epilepsia, celebradoen Bilbao del 14 al 17 de noviembre de 2001.Simposio I: Avances en la Fisiopatología de la EpileptogénesisModeradores: J.L. Herranz, P. Madoz | Temporal lobe epilepsy is associated to many disorders localized to the neo...

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19

Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+

Río Fernández, Rocío del; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Delgado Restituto, Manuel

We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS proc...

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20

High-Order Cascade Multi-bit ΣΔ Modulators for High-Speed A/D Conversion

Río Fernández, Rocío del; Medeiro, Fernando; Pérez Verdú, Belén; Rodríguez Vázquez, Angel

The use of Sigma-Delta (ΣΔ) modulation for analog-to-digital conversion (ADC) in thecommunication frequency range is evaluated. Two high-order multi-bit architectures are proposed to achieve +12-bit dynamic range at 4Msample/s Nyquist rate using very low oversampling ratio. They show very low sensi...

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21

High-Level Synthesis of Switched-Capacitor, Switched-Current and Continuous-Time ΣΔ Modulators Using SIMULINK-Based Time-Domain Behavioral Models

Ruiz Amaya, Jesús; Rosa Utrera, José Manuel de la; Fernández, Francisco V.; Medeiro, Fernando; Río Fernández, Rocío del

This paper presents a high-level synthesis tool for ΣΔ Modulators (ΣΔMs) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for themodulator implementation are considered: switched-capacitor, switched-cu...

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22

Digital read-out integrated circuit for the digital reading of high-speed image sensors

Serra Graells, Francisco; Margarit Taule, Josep M.; Teres Teres, Lluis
2009-11-19

Digital.CSIC (Spain)

23

Device and method for measuring parameters of periodic oscillatory signals.

Vazquez García de la Vega, Diego; Leger, Gildas; Huertas Sanchez, Gloria; Huertas, José Luis
2003-05-30

Digital.CSIC (Spain)

24

Design of tapered leaky-wave antennas in hybrid waveguide-planar technology for millimeter waveband applications

Gómez Tornero, José Luis; Torre Martínez, Alejandro de la; Cañete Rebenaque, David; Álvarez Melcón, Alejandro

Different types of waveguide leaky-wave antennas,asymmetrically perturbed with printed-circuits, are studied inthis paper. The capability to modify the leakage constant of theexcited leaky-wave mode, while maintaining unchanged its phaseconstant, is studied in detail for each design. Several slo...

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25

Design of tapered leaky-wave antennas in hybrid waveguide-planar technology for millimeter waveband applications

Gómez Tornero, José Luis; Torre Martínez, Alejandro de la; Cañete Rebenaque, David; Álvarez Melcón, Alejandro

Different types of waveguide leaky-wave antennas,asymmetrically perturbed with printed-circuits, are studied inthis paper. The capability to modify the leakage constant of theexcited leaky-wave mode, while maintaining unchanged its phaseconstant, is studied in detail for each design. Several slo...

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26

Design Considerations for an Automotive Sensor Interface Sigma-Delta Modulator

Medeiro, Fernando; Rosa Utrera, José Manuel de la; Río Fernández, Rocío del; Pérez Verdú, Belén; Rodríguez Vázquez, Angel

EU IST Project 2001-34283/TAMES-2Spanish MCyT Project TIC2001-0929/ADAVERE. | The Sigma-Delta Modulator presented in this paper contains a programmable-gain input inferface to accommodate the output signal level of a variety of automotive sensors. We show that this characteristic can be efficiently...

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27

CMOS Sigma-Delta Converters - From Basics to State of the Art: Session 2

Río Fernández, Rocío del; Pérez Verdú, Belén; Rosa Utrera, José Manuel de la

The RaMSiS Group (Radio And Mixed Signal Integrated Systems) of the Royal Institute of Technology Stockholm (KTH) and the Institute of Microelectronics of Seville (IMSE-CNM) of the Spanish Microelectronics Centre (CSIC).

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28

CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom: Error Analysis and Practical Design.

Río Fernández, Rocío del; Medeiro, Fernando; Pérez Verdú, Belén; Rosa Utrera, José Manuel de la; Rodríguez Vázquez, Angel

Peer reviewed

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29

Behavioral Modeling, Simulation and High-Level Synthesis of Pipeline A/D Converters

Ruiz Amaya, Jesús; Rosa Utrera, José Manuel de la; Delgado Restituto, Manuel; Rodríguez Vázquez, Angel

This paper presents a MATLAB® toolbox for the time-domain simulation and high-level sizing of pipeline analog-to-digital converters. SIMULINK® C-coded S-functions are used to describe the behavioral models of all building blocks, including their main circuit errors. This approach significantly speed...

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30

Bandpass Sigma-Delta Modulators: Principles, Architecture and Circuits

Rodríguez Vázquez, Angel; Rosa Utrera, José Manuel de la

Peer reviewed

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31

BandPass Sigma-Delta Analog-to-Digital Converters

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Medeiro, Fernando; Río Fernández, Rocío del; Rodríguez Vázquez, Angel

The principle of ΣΔ Modulation (ΣΔM) is extended in BPΣΔMs to bandpass signals, especially but not only, with a narrow bandwidth. Thus, BPΣΔMshave much in common with their lowpass counterparts - whose properties have been covered in previous Chapters of this book. However, there are some issues wh...

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32

Analysis of Error Mechanisms in Switched-Current Sigma-Delta Modulators

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Medeiro, Fernando; Río Fernández, Rocío del; Rodríguez Vázquez, Angel

This paper presents a systematic analysis of the major switched-current (SI) errors and their influence on the performance degradation of ΣΔ Modulators (ΣΔMs). The study is presented in a hierarchical systematic way. First, the physical mechanisms behind SI errors are explained and a precise mode...

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33

An interpolated spatial images method for the analysis of multilayered shielded microwave circuits

Gómez Díaz, Juan Sebastián; Martínez Mendoza, Mónica; Pérez Soler, Francisco Javier; Álvarez Melcón, Alejandro

In this paper, an efficient interpolation method is presented in order to compute the Green’s functionassociated to electrical sources, when they are placed inside cylindrical cavities. The interpolation schemeis formulated in the frame of the spatial images technique recently developed. The origi...

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34

An Embedded 12-bit 80MS/s A/D/A Interface for Power-Line Communications in 0.13μm Pure Digital CMOS Technology

Delgado Restituto, Manuel; Ruiz Amaya, Jesús; Rosa Utrera, José Manuel de la; Fernández-Bootello, Juan Francisco

This paper presents an embedded interface, comprising both A/D and D/A converters, which has been implemented in a 0.13μm pure digital CMOS technology. The interface is integratedin a system for high-performance broad-band power-line communications. The A/D converter uses a pipelined structure, whe...

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35

ATLAS TileCal read out driver production

Valero, José Alberto; Abdallah, J.; Castillo, M.ª Victoria; Cuenca Almenar, Cristóbal; Ferrer, Antonio

13 pages, 11 figures.-- ISI Article Identifier: 000253651500004.-- Paper available Open Access at: http://ific.uv.es/tical/doc/2007_05_14_JINST_2_P05003.pdf | The production tests of the 38 ATLAS TileCal Read Out Drivers (RODs) are presented in this paper. The hardware specifications and firmware fu...

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36

A simulation study on the health concerns derived from GSM base station placement

Muñoz Gea, Juan Pedro; Vales Alonso, Javier; García Haro, Joan; García Castaño, Francisco Javier

In the last years a great concern has raised among population due to the placement of the base stations (BS) of cellular systems in urban areas. In some cases, it has been addressed with the (re)installation of BSs in far suburban areas. However, in these cases, mobile stations (MS) must raise trans...

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37

A mixed-signal architecture for high complexity CMOS fuzzy controlers | Arquitectura de señal mixta para controladores difusos de CMOS de alta complejidad

Navas-González, Rafael; Vidal Verdú, Fernando; Rodríguez Vázquez, Angel

Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision, as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually or...

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38

A New High-Level Synthesis Methodology of Cascaded Continuous-Time ΣΔ Modulators

Tortosa, Ramón; Rosa Utrera, José Manuel de la; Fernández, Francisco V.; Rodríguez Vázquez, Angel

This brief presents an efficient method for synthesizing cascaded sigma–delta modulators implemented with continuous-time circuits. It is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as ha...

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A High-Performance Sigma-Delta ADC for ADSL Applications in 0.35μm CMOS Digital Technology

Río Fernández, Rocío del; Rosa Utrera, José Manuel de la; Medeiro, Fernando; Pérez Verdú, Belén; Rodríguez Vázquez, Angel

We present a Sigma-Delta modulator designed for ADSL applications in a 0.3Sμm CMOS pure digital technology. It employs a 4th-order 3-stage cascade architecture including both single-bit and multi-bit quantizers with programmable resolution, which allows us to use only 16 oversampling ratio. Especial...

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A Fourth-Order BandPass Sigma-Delta Modulator Using Current-Mode Analog/Digital Circuits

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Medeiro, Fernando; Rodríguez Vázquez, Angel

We present a fourth-order bandpass Sigma-Delta switched current modulator in 0.8 um CMOS single-poly technology.Its architecture is obtained by applying a lowpass to BandPass transformation to a second-order lowpass modulator. It has been realized using fully-differential circuitrywith common-mod...

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A CMOS 110-dB@40-kS/s Programmable-Gain, Chopper-Stabilized Third-Order 2-1 Cascade Sigma-Delta Modulator for Low-Power, High-Linearity Automotive Sensor ASICs

Rosa Utrera, José Manuel de la; Escalera, Sara; Pérez Verdú, Belén; Medeiro, Fernando; Guerra, Oscar

This paper describes a 0.35-μm CMOS chopper-stabilized switched-capacitor 2-1 cascade ΣΔ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed andpower dissipation. To obtain a b...

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A CMOS 0.8μm Transistor-Only 1.63MHz Switched-Current Bandpass ΣΔ Modulator for AM Signal A/D Conversion

Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Río Fernández, Rocío del; Rodríguez Vázquez, Angel

This paper presents a CMOS 0.8um SwItched-current (SI) fourth-order Band-Pass ΣΔ Modulator (BP-ΣΔM) IC capable of handling signals up to 1.63MHz with 10.5-bit resolution and 60mW power consumption from a 5V supply voltage. This modulator is intended for direct A/D conversion of narrowband signals wi...

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A 14-bit 4-MS/s Multi-bit Cascade Sigma-Delta Modulator in CMOS 0.35-um Digital Technology

Río Fernández, Rocío del; Medeiro, Fernando; Rosa Utrera, José Manuel de la; Pérez Verdú, Belén; Rodríguez Vázquez, Angel

This paper presents a 4th-order 3-stage cascade SD modulator that achieves 14-bit dynamic range at 4MS/s using low oversampling ratio. It includes a programmable multi-bit quantizer in the last stage, providing 2-, 3-, or 4-bit internal resolution. The modulator is implemented with fully-differentia...

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A 12-bit CMOS Current Steering D/A Converter for Embedded Systems

Ruiz Amaya, Jesús; Delgado Restituto, Manuel; Fernández-Bootello, Juan Francisco; Brandano, Davide; Castro López, Rafael

This paper describes the design of a 12-bit digital-to-analog converter for a wireline modem chip implemented in a 0.13μm digital CMOS technology. Transistor-level simulations from extracted layout at the nominal modem data rate of 8OMS/s show an Spurious-Free Dynamic-Range (SFDR) better than 62dB a...

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A 0.35μm CMOS 17-bit@40kS/s Sensor A/D Interface Based on a Programmable-Gain Cascade 2-1 ΣΔ Modulator

García-González, José Manuel; Escalera, Sara; Rosa Utrera, José Manuel de la; Guerra, Oscar; Medeiro, Fernando

This paper describes the design and electrical implementation of an A/D interface for sensor applications realized in a 0.35μm standardCMOS technology. The circuit is composed of a low-noise instrumentation preamplifier and a SC cascade (2-1) ΣΔ modulator. The preamplifier, based on hybrid Nested-M...

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A 0.13μm CMOS Current Steering D/A Converter for PLC and VDSL Applications

Ruiz Amaya, Jesús; Fernández-Bootello, Juan Francisco; Rosa Utrera, José Manuel de la; Delgado Restituto, Manuel

This paper describes the design of a 12-bit80MS/s Digital-to-Analog converter implemented in a 0.13μm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. Th...

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4th-Order Cascade SC ΣΔ modulators: A Comparative Study

Medeiro, Fernando; Pérez Verdú, Belén; Rosa Utrera, José Manuel de la; Rodríguez Vázquez, Angel

Fourth-order cascade ΣΔ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires c...

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