Sample records for LOGISCHE SCHALTUNGEN (logic circuits)
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6

Signed-Digit CMOS (SD-CMOS) Logic Circuits with Dynamic Operation

Fukuda, H.; IEEE Computer Society Technical Committee on Multiple-Valued Logic
2005-01-01

German National Library of Science and Technology (GetInfo) (German)

7

Set-Valued Logic Circuits for Next Generation VLSI Architectures

Aoki, T.; Higuchi, T.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

8

Semi-Dynamic and Dynamic Flip-FLops with Embedded Logic

Klass, F.; IEEE; Solid State Circuits Society; Japan Society of Applied Physics
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

13

Residue Arithmetic Circuits Based on the Signed-Digit Multiple-Valued Arithmetic Circuits

Wei, S.; Shimizu, K.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

14

Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits

Shimabukuro, K.; Zukeran, C.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

15

Quaternary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits

Herrfeld, A.; Hentschke, S.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1997-01-01

German National Library of Science and Technology (GetInfo) (German)

24

Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits

Baba, T.; Uemura, T.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1997-01-01

German National Library of Science and Technology (GetInfo) (German)

27

Merged DRAM and Logic

Furuyama, T.; Lu, N.; IEEE; Solid State Circuits Council
1996-01-01

German National Library of Science and Technology (GetInfo) (German)

32

Logic synthesis and optimization

International Symposium on Logic Synthesis and Microprocessor Architecture < 1992, Iizuka>
1993-01-01

German National Library of Science and Technology (GetInfo) (German)

37

Implementing Logic in FPGA Embedded Memory Arrays: Architectural Implications

Wilton, S. J. E.; IEEE; Solid State Circuits Society; IEEE; Electron Devices Society
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

40
41

Future High Performance Logic Circuits

Kuroda, T.; Borkar, S.; Japan Society of Applied Physics
1995-01-01

German National Library of Science and Technology (GetInfo) (German)

46

Evolutionary Methods in the Design of Quaternery Digital Circuits

Moraga, C.; Wang, W.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1998-01-01

German National Library of Science and Technology (GetInfo) (German)

50

Efficient Charge Recovery Logic

Moon, Y.; Jeong, D.-K.; Japan Society of Applied Physics
1995-01-01

German National Library of Science and Technology (GetInfo) (German)

53

Dynamic Logic Synthesis

Yee, G.; Sechen, C.; IEEE; Solid State Circuits Council
1997-01-01

German National Library of Science and Technology (GetInfo) (German)

54
57

Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits

Wu, X.; Pedram, M.; IEEE; Computer Society; Technical Committee on Multiple-Valued Logic
1997-01-01

German National Library of Science and Technology (GetInfo) (German)

60

DESIGN OF MOS CURRENT MODE LOGIC GATES - COMPUTING THE LIMITS OF VOLTAGE SWING AND BIAS CURRENT

Caruso, G.; Institute of Electrical and Electronics Engineers; IEEE Circuits and Systems Society
2005-01-01

German National Library of Science and Technology (GetInfo) (German)

62

Colloquium on Gigabit Logic Circuits

Colloquium on Gigabit Logic Circuits < 1992, London>; Institution of Electrical Engineers / Electronics Division
1992-01-01

German National Library of Science and Technology (GetInfo) (German)

66

CPU Controller Optimization in HDL Logic Synthesis

Yeap, G.; IEEE; Solid State Circuits Council; IEEE; Electron Devices Society
1997-01-01

German National Library of Science and Technology (GetInfo) (German)

67

CONCENTRATOR ACCESS NETWORKS FOR PROGRAMMABLE LOGIC CORES ON SOCS

Quinton, B.; Wilton, S.; Institute of Electrical and Electronics Engineers
2005-01-01

German National Library of Science and Technology (GetInfo) (German)

68

CMOS TSPC Latch Circuits for Pass-Transistor Logic

Smith, J. C.; University of Southwestern Louisiana; Center for Advanced Computer Studies; IEEE; Circuits and Systems Society
1994-01-01

German National Library of Science and Technology (GetInfo) (German)