Utilization of multi-band OFDM modulation to increase traffic rate of phosphor-LED wireless VLC.

Science.gov (United States)

Yeh, Chien-Hung; Chen, Hsing-Yu; Chow, Chi-Wai; Liu, Yen-Liang

2015-01-26

To increase the traffic rate in phosphor-LED visible light communication (VLC), a multi-band orthogonal frequency division multiplexed (OFDM) modulation is first proposed and demonstrated. In the measurement, we do not utilize optical blue filter to increase modulation bandwidth of phosphor-LED in the VLC system. In this proposed scheme, different bands of OFDM signals are applied to different LED chips in a LED lamp, this can avoid the power fading and nonlinearity issue by applying the same OFDM signal to all the LED chips in a LED lamp. Here, the maximum increase percentages of traffic rates are 41.1%, 17.8% and 17.8% under received illuminations of 200, 500 and 1000 Lux, respectively, when the proposed three-band OFDM modulation is used in the VLC system. In addition, the analysis and verification by experiments are also performed.

A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

International Nuclear Information System (INIS)

Tang, Jiajie; Sun, Xiaowei; Luo, Le

2011-01-01

A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon

A multi-chip module for physics experiments

CERN Document Server

Benso, A; Giovannetti, S; Mariani, R; Motto, S; Prinetto, P

1999-01-01

MCMs are widely adopted as assembly solutions for multi-die based systems, where area, performance, and costs are critical constraints. This paper describes both the project strategies and production flow that are to be adopted to realize an MCM-D for data acquisition in high-energy physics experiments. The activity starts from the results of RD/16 CERN project, and is part of the LAP Esprit project. The paper details the most critical issues faced in the production phase, and analyzes how they influenced system partitioning and component design. Moreover, it presents the design-for-testability methodologies adopted at both chip and MCM levels to achieve low defect levels and high production yields, minimizing the overhead in terms of system performance and area occupation. This work should demonstrate the feasibility of the MCM technology in such high speed data processing systems, where both size and cost constraints are important. (10 refs).

Application of quantum-dot multi-wavelength lasers and silicon photonic ring resonators to data-center optical interconnects

Science.gov (United States)

Beckett, Douglas J. S.; Hickey, Ryan; Logan, Dylan F.; Knights, Andrew P.; Chen, Rong; Cao, Bin; Wheeldon, Jeffery F.

2018-02-01

Quantum dot comb sources integrated with silicon photonic ring-resonator filters and modulators enable the realization of optical sub-components and modules for both inter- and intra-data-center applications. Low-noise, multi-wavelength, single-chip, laser sources, PAM4 modulation and direct detection allow a practical, scalable, architecture for applications beyond 400 Gb/s. Multi-wavelength, single-chip light sources are essential for reducing power dissipation, space and cost, while silicon photonic ring resonators offer high-performance with space and power efficiency.

Embedded memory design for multi-core and systems on chip

CERN Document Server

Mohammad, Baker

2014-01-01

This book describes the various tradeoffs systems designers face when designing embedded memory.  Readers designing multi-core systems and systems on chip will benefit from the discussion of different topics from memory architecture, array organization, circuit design techniques and design for test.  The presentation enables a multi-disciplinary approach to chip design, which bridges the gap between the architecture level and circuit level, in order to address yield, reliability and power-related issues for embedded memory.  ·         Provides a comprehensive overview of embedded memory design and associated challenges and choices; ·         Explains tradeoffs and dependencies across different disciplines involved with multi-core and system on chip memory design; ·         Includes detailed discussion of memory hierarchy and its impact on energy and performance; ·         Uses real product examples to demonstrate embedded memory design flow from architecture, to circuit ...

A 60-GHz energy harvesting module with on-chip antenna and switch for co-integration with ULP radios in 65-nm CMOS with fully wireless mm-wave power transfer measurement

NARCIS (Netherlands)

Gao, H.; Matters - Kammerer, M.; Harpe, P.J.A.; Milosevic, D.; Roermund, van A.H.M.; Linnartz, J.P.M.G.; Baltus, P.G.M.

2014-01-01

In this paper the architecture and performance of a co-integrated 60 GHz on-chip wireless energy harvester and ultra-low power (ULP) radio in 65-nm CMOS are discussed. Integration of an on-chip antenna with wireless power receiver and wireless data transfer module is the crucial next step to achieve

Vce-based methods for temperature estimation of high power IGBT modules during power cycling - A comparison

DEFF Research Database (Denmark)

Amoiridis, Anastasios; Anurag, Anup; Ghimire, Pramod

2015-01-01

. This experimental work evaluates the validity and accuracy of two Vce based methods applied on high power IGBT modules during power cycling tests. The first method estimates the chip temperature when low sense current is applied and the second method when normal load current is present. Finally, a correction factor......Temperature estimation is of great importance for performance and reliability of IGBT power modules in converter operation as well as in active power cycling tests. It is common to be estimated through Thermo-Sensitive Electrical Parameters such as the forward voltage drop (Vce) of the chip...

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

Directory of Open Access Journals (Sweden)

Junning Chen

2013-07-01

Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

Serial powering of pixel modules

CERN Document Server

Stockmanns, Tobias; Hügging, Fabian Georg; Peric, I; Runólfsson, O; Wermes, Norbert

2003-01-01

Modern pixel detectors for the next generation of high-energy collider experiments like LHC use readout electronics in deep sub- micron technology. Chips in this technology need a low supply voltage of 2-2.5 V alongside high current consumption to achieve the desired performance. The high supply current leads to significant voltage drops in the long and low mass supply cables so that voltage fluctuations at the chips are induced, when the supply current changes. This problem scales with the number of modules when connected in parallel to the power supplies. An alternative powering scheme connects several modules in series resulting in a higher supply voltage but a lower current consumption of the chain and therefore a much lower voltage drop in the cables. In addition the amount of cables needed to supply the detector is vastly reduced. The concept and features of serial powering are presented and studies of the implementation of this technology as an alternative for the ATLAS pixel detector are shown. In par...

Serial powering of pixel modules

International Nuclear Information System (INIS)

Stockmanns, Tobias; Fischer, Peter; Huegging, Fabian; Peric, Ivan; Runolfsson, O.; Wermes, Norbert

2003-01-01

Modern pixel detectors for the next generation of high-energy collider experiments like LHC use readout electronics in deep sub-micron technology. Chips in this technology need a low supply voltage of 2-2.5 V alongside high current consumption to achieve the desired performance. The high supply current leads to significant voltage drops in the long and low mass supply cables so that voltage fluctuations at the chips are induced, when the supply current changes. This problem scales with the number of modules when connected in parallel to the power supplies. An alternative powering scheme connects several modules in series resulting in a higher supply voltage but a lower current consumption of the chain and therefore a much lower voltage drop in the cables. In addition the amount of cables needed to supply the detector is vastly reduced. The concept and features of serial powering are presented and studies of the implementation of this technology as an alternative for the ATLAS pixel detector are shown. In particular, it is shown that the potential risk of powering in series can be addressed and eliminated

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

International Nuclear Information System (INIS)

Li, Huanlu; Strain, Michael J.; Meriggi, Laura; Sorel, Marc; Chen, Lifeng; Zhu, Jiangbo; Cicek, Kenan; Wang, Jianwei; Thompson, Mark G.; Cai, Xinlun; Yu, Siyuan

2015-01-01

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications. It can be intentionally implemented with other modulation elements to achieve more complicated applications

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

Energy Technology Data Exchange (ETDEWEB)

Li, Huanlu [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Strain, Michael J. [School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Wolfson Centre, Institute of Photonics, University of Strathclyde, 106 Rottenrow East, Glasgow G4 0NW (United Kingdom); Meriggi, Laura; Sorel, Marc [School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP (United Kingdom); Chen, Lifeng; Zhu, Jiangbo; Cicek, Kenan [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); Wang, Jianwei; Thompson, Mark G. [Centre for Quantum Photonics, H. H. Wills Physics Laboratory and Department of Electrical and Electronic Engineering, University of Bristol, Bristol BS8 1UB (United Kingdom); Cai, Xinlun, E-mail: caixlun5@mail.sysu.edu.cn [Centre for Quantum Photonics, H. H. Wills Physics Laboratory and Department of Electrical and Electronic Engineering, University of Bristol, Bristol BS8 1UB (United Kingdom); State Key Laboratory of Optoelectronic Materials and Technologies and School of Physics and Engineering, Sun Yat-sen University, Guangzhou 510275 (China); Yu, Siyuan, E-mail: s.yu@bristol.ac.uk [Department of Electrical and Electronic Engineering, University of Bristol, University Walk, Bristol BS8 1TR (United Kingdom); State Key Laboratory of Optoelectronic Materials and Technologies and School of Physics and Engineering, Sun Yat-sen University, Guangzhou 510275 (China)

2015-08-03

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications. It can be intentionally implemented with other modulation elements to achieve more complicated applications.

A scalable single-chip multi-processor architecture with on-chip RTOS kernel

NARCIS (Netherlands)

Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

2003-01-01

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

Module Integrated GaN Power Stage for High Switching Frequency Operation

DEFF Research Database (Denmark)

Nour, Yasser; Knott, Arnold

2017-01-01

is integrated on a high glass transition temperature 0.4 mmthick FR4 substrate configured as a 70 pin ball grid arraypackage. The power stage is tested up to switching frequency of12 MHz. The power stage achieved 88.5 % peak efficiency whenconfigured as a soft switching buck converter operating at 7MHz......An increased attention has been detected todevelop smaller and lighter high voltage power converters in therange of 50 V to 400 V domains. The applications for theseconverters are mainly focused for Power over Ethernet (PoE),LED lighting and ac adapters. Design for high power density isone...... of the targets for next generation power converters. Thispaper presents an 80 V input capable multi-chip moduleintegration of enhancement mode gallium nitride (GaN) fieldeffect transistors (FETs) based power stage. The module design ispresented and validated through experimental results. The powerstage...

FE-I4 pixel chip characterization with USBpix3 test system

Energy Technology Data Exchange (ETDEWEB)

Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

2015-07-01

The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

Exploring performance and power properties of modern multicore chips via simple machine models

OpenAIRE

Hager, Georg; Treibig, Jan; Habich, Johannes; Wellein, Gerhard

2012-01-01

Modern multicore chips show complex behavior with respect to performance and power. Starting with the Intel Sandy Bridge processor, it has become possible to directly measure the power dissipation of a CPU chip and correlate this data with the performance properties of the running code. Going beyond a simple bottleneck analysis, we employ the recently published Execution-Cache-Memory (ECM) model to describe the single- and multi-core performance of streaming kernels. The model refines the wel...

Advanced Nanofabrication Process Development for Self-Powered System-on-Chip

KAUST Repository

Rojas, Jhonathan Prieto

2010-01-01

In summary, by using a novel sustainable energy component and scalable nano-patterning for logic and computing module, this work has successfully collected the essential base knowledge and joined two different elements that synergistically will contribute for the future implementation of a Self-Powered System-on-Chip.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

Science.gov (United States)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Study of multi-channel readout ASIC and its discrete module for particle detector

International Nuclear Information System (INIS)

Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

2013-01-01

Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

Directory of Open Access Journals (Sweden)

Chang-Hung Lee

2014-05-01

Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

Science.gov (United States)

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

Development of the MCM-D technique for pixel detector modules

CERN Document Server

Grah, Christian

2005-01-01

This thesis treats a copper--polymer based thin film technology, the MCM-D technique and its application when building hybrid pixel detector modules. The ATLAS experiment at the LHC will be equipped with a pixel detector system. The basic mechanical units of the pixel detector are multi chip modules. The main components of these modules are: 16 electronic chips, a controller chip and a large sensor tile, featuring more than 46000 sensor cells. MCM-D is a superior technique to build the necessary signal bus system and the power distribution system directly on the active sensor tile. In collaboration with the Fraunhofer Institute for Reliability and Microintegration, IZM, the thin film process is reviewed and enhanced. The multi layer system was designed and optimized for the interconnection system as well as for the 46000 pixel contacts. Laboratory measurements on prototypes prove that complex routing schemes for geometrically optimized single chips are suitable and have negligible influence on the front--end ...

On-chip digital power supply control for system-on-chip applications

NARCIS (Netherlands)

Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

2005-01-01

The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

Variable-Width Datapath for On-Chip Network Static Power Reduction

Energy Technology Data Exchange (ETDEWEB)

Michelogiannakis, George; Shalf, John

2013-11-13

With the tight power budgets in modern large-scale chips and the unpredictability of application traffic, on-chip network designers are faced with the dilemma of designing for worst- case bandwidth demands and incurring high static power overheads, or designing for an average traffic pattern and risk degrading performance. This paper proposes adaptive bandwidth networks (ABNs) which divide channels and switches into lanes such that the network provides just the bandwidth necessary in each hop. ABNs also activate input virtual channels (VCs) individually and take advantage of drowsy SRAM cells to eliminate false VC activations. In addition, ABNs readily apply to silicon defect tolerance with just the extra cost for detecting faults. For application traffic, ABNs reduce total power consumption by an average of 45percent with comparable performance compared to single-lane power-gated networks, and 33percent compared to multi-network designs.

Multidisciplinary Modelling Tools for Power Electronic Circuits

DEFF Research Database (Denmark)

Bahman, Amir Sajjad

in reliability assessment of power modules, a three-dimensional lumped thermal network is proposed to be used for fast, accurate and detailed temperature estimation of power module in dynamic operation and different boundary conditions. Since an important issue in the reliability of power electronics...... environment to be used for optimization of cooling system layout with respect to thermal resistance and pressure drop reductions. Finally extraction of electrical parasitics in the multi-chip power modules will be investigated. As the switching frequency of power devices increases, the size of passive...... components are reduced considerably that leads to increase of power density and cost reduction. However, electrical parasitics become more challenging with increasing the switching frequency and paralleled chips in the integrated and denser packages. Therefore, electrical parasitic models are analyzed based...

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

Science.gov (United States)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

DEFF Research Database (Denmark)

Sparsø, Jens

2012-01-01

This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

Development of the MCM-D technique for pixel detector modules

International Nuclear Information System (INIS)

Grah, C.

2005-03-01

This thesis treats a copper--polymer based thin film technology, the MCM-D technique and its application when building hybrid pixel detector modules. The ATLAS experiment at the LHC will be equipped with a pixel detector system. The basic mechanical units of the pixel detector are multi chip modules. The main components of these modules are: 16 electronic chips, a controller chip and a large sensor tile, featuring more than 46000 sensor cells. MCM-D is a superior technique to build the necessary signal bus system and the power distribution system directly on the active sensor tile. In collaboration with the Fraunhofer Institute for Reliability and Microintegration, IZM, the thin film process is reviewed and enhanced. The multi layer system was designed and optimized for the interconnection system as well as for the 46000 pixel contacts. Laboratory measurements on prototypes prove that complex routing schemes for geometrically optimized single chips are suitable and have negligible influence on the front--end chips performance. A full scale MCM-D module has been built and it is shown that the technology is suitable to build pixel detector modules. Further tests include the investigation of the impact of hadronic irradiation on the thin film layers. Single chip assemblies have been operated in a test beam environment and the feasibility of the optimization of the sensors could be shown. A review on the potential as well as the perspective for the MCM-D technique in future experiments is given

Self-powered integrated systems-on-chip (energy chip)

KAUST Repository

Hussain, Muhammad Mustafa

2010-04-23

In today\\'s world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

Self-powered integrated systems-on-chip (energy chip)

Science.gov (United States)

Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

2010-04-01

In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

Fuzzy logic based power-efficient real-time multi-core system

CERN Document Server

Ahmed, Jameel; Najam, Shaheryar; Najam, Zohaib

2017-01-01

This book focuses on identifying the performance challenges involved in computer architectures, optimal configuration settings and analysing their impact on the performance of multi-core architectures. Proposing a power and throughput-aware fuzzy-logic-based reconfiguration for Multi-Processor Systems on Chip (MPSoCs) in both simulation and real-time environments, it is divided into two major parts. The first part deals with the simulation-based power and throughput-aware fuzzy logic reconfiguration for multi-core architectures, presenting the results of a detailed analysis on the factors impacting the power consumption and performance of MPSoCs. In turn, the second part highlights the real-time implementation of fuzzy-logic-based power-efficient reconfigurable multi-core architectures for Intel and Leone3 processors. .

Application of CPLD in CSR power supply control module

International Nuclear Information System (INIS)

Liu Caihong; Guo Yuhui; Chinese Academy of Sciences, Beijing; Jing Lan; Qiao Weimin

2005-01-01

A realization of Single Chip Microcomputer peripheral interface in HIRFL-CSR power supply control module based on CPLD is presented in the paper. It integrates flip-latch, coding unit, data bus, frequency division unit, logical compare unit, counter and logic circuit into a single CPLD chip, and dramatically decreases the area of PCB and increase system reliability, at the same time the whole system's flexibility has been evidently improved because of the CPLD's in-system programmable characteristics. (authors)

Quasi-periodic synchronisation of self-modulation oscillations in a ring chip laser by an external periodic signal

International Nuclear Information System (INIS)

Aulova, T V; Kravtsov, Nikolai V; Lariontsev, E G; Chekina, S N

2011-01-01

The synchronisation of periodic self-modulation oscillations in a ring Nd:YAG chip laser under an external periodic signal modulating the pump power has been experimentally investigated. A new quasi-periodic regime of synchronisation of self-modulation oscillations is found. The characteristic features of the behaviour of spectral and temporal structures of synchronised quasi-periodic oscillations with a change in the external signal frequency are studied. (control of laser radiation parameters)

In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

CERN Multimedia

Saba, A

2006-01-01

2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints

Science.gov (United States)

Yu, Thomas Edison; Yoneda, Tomokazu; Zhao, Danella; Fujiwara, Hideo

The rapid advancement of VLSI technology has made it possible for chip designers and manufacturers to embed the components of a whole system onto a single chip, called System-on-Chip or SoC. SoCs make use of pre-designed modules, called IP-cores, which provide faster design time and quicker time-to-market. Furthermore, SoCs that operate at multiple clock domains and very low power requirements are being utilized in the latest communications, networking and signal processing devices. As a result, the testing of SoCs and multi-clock domain embedded cores under power constraints has been rapidly gaining importance. In this research, a novel method for designing power-aware test wrappers for embedded cores with multiple clock domains is presented. By effectively partitioning the various clock domains, we are able to increase the solution space of possible test schedules for the core. Since previous methods were limited to concurrently testing all the clock domains, we effectively remove this limitation by making use of bandwidth conversion, multiple shift frequencies and properly gating the clock signals to control the shift activity of various core logic elements. The combination of the above techniques gains us greater flexibility when determining an optimal test schedule under very tight power constraints. Furthermore, since it is computationally intensive to search the entire expanded solution space for the possible test schedules, we propose a heuristic 3-D bin packing algorithm to determine the optimal wrapper architecture and test schedule while minimizing the test time under power and bandwidth constraints.

On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

International Nuclear Information System (INIS)

Ren Zhixiong; Zhang Kefeng; Liu Lanqi; Li Cong; Chen Xiaofei; Liu Dongsheng; Liu Zhenglin; Zou Xuecheng

2015-01-01

Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE. (paper)

Portable low-power thermal cycler with dual thin-film Pt heaters for a polymeric PCR chip.

Science.gov (United States)

Jeong, Sangdo; Lim, Juhun; Kim, Mi-Young; Yeom, JiHye; Cho, Hyunmin; Lee, Hyunjung; Shin, Yong-Beom; Lee, Jong-Hyun

2018-01-29

Polymerase chain reaction (PCR) has been widely used for major definite diagnostic tool, but very limited its place used only indoor such as hospital or diagnosis lab. For the rapid on-site detection of pathogen in an outdoor environment, a low-power cordless polymerase chain reaction (PCR) thermal cycler is crucial module. At this point of view, we proposed a low-power PCR thermal cycler that could be operated in an outdoor anywhere. The disposable PCR chip was made of a polymeric (PI/PET) film to reduce the thermal mass. A dual arrangement of the Pt heaters, which were positioned on the top and bottom of the PCR chip, improved the temperature uniformity. The temperature sensor, which was made of the same material as the heater, utilized the temperature dependence of the Pt resistor to ensure simple fabrication of the temperature sensor. Cooling the PCR chip using dual blower fans enabled thermal cycling to operate with a lower power than that of a Peltier element with a high power consumption. The PCR components were electrically connected to a control module that could be operated with a Li-ion battery (12 V), and the PCR conditions (temperature, time, cycle, etc.) were inputted on a touch screen. For 30 PCR cycles, the accumulated power consumption of heating and cooling was 7.3 Wh, which is easily available from a compact battery. Escherichia coli genomic DNA (510 bp) was amplified using the proposed PCR thermal cycler and the disposable PCR chip. A similar DNA amplification capability was confirmed using the proposed portable and low-power thermal cycler compared with a conventional thermal cycler.

Silicon nanowire networks for multi-stage thermoelectric modules

International Nuclear Information System (INIS)

Norris, Kate J.; Garrett, Matthew P.; Zhang, Junce; Coleman, Elane; Tompa, Gary S.; Kobayashi, Nobuhiko P.

2015-01-01

Highlights: • Fabricated flexible single, double, and quadruple stacked Si thermoelectric modules. • Measured an enhanced power production of 27%, showing vertical stacking is scalable. • Vertically scalable thermoelectric module design of semiconducting nanowires. • Design can utilize either p or n-type semiconductors, both types are not required. • ΔT increases with thickness therefore power/area can increase as modules are stacked. - Abstract: We present the fabrication and characterization of single, double, and quadruple stacked flexible silicon nanowire network based thermoelectric modules. From double to quadruple stacked modules, power production increased 27%, demonstrating that stacking multiple nanowire thermoelectric devices in series is a scalable method to generate power by supplying larger temperature gradient. We present a vertically scalable multi-stage thermoelectric module design using semiconducting nanowires, eliminating the need for both n-type and p-type semiconductors for modules

1 GHz GaAs Buck Converter for High Power Amplifier Modulation Applications

NARCIS (Netherlands)

Busking, E.B.; Hek, A.P. de; Vliet, F.E. van

2012-01-01

A fully integrated 1 GHz buck converter output stage, including on-chip inductor and DC output filtering has been realized, in a standard high-voltage breakdown GaAs MMIC technology. This is a significant step forward in designing highspeed power control of supply-modulated HPAs (high power

A Comprehensive Investigation on the Short Circuit Performance of MW-level IGBT Power Modules

DEFF Research Database (Denmark)

Wu, Rui; Reigosa, Paula Diaz; Iannuzzo, Francesco

2015-01-01

This paper investigates the short circuit performance of commercial 1.7 kV / 1 kA IGBT power modules by means of a 6 kA Non-Destructive-Tester. A mismatched current distribution among the parallel chips has been observed, which can reduce the short circuit capability of the IGBT power module unde...... short circuit conditions. Further Spice simulations reveal that the stray parameters inside the module play an important role in contributing to such a phenomenon....

A multi-channel isolated power supply in non-equipotential circuit

Science.gov (United States)

Li, Xiang; Zhao, Bo-Wen; Zhang, Yan-Chi; Xie, Da

2018-04-01

A multi-channel isolation power supply is designed for the problems of different MOSFET or IGBT in the non-equipotential circuit in this paper. It mainly includes the square wave generation circuit, the high-frequency transformer and the three-terminal stabilized circuit. The first part is used to generate the 24V square wave, and as the input of the magnetic ring transformer. In the second part, the magnetic ring transformer consists of one input and three outputs to realize multi-channel isolation output. The third part can output different potential and realize non-equal potential function through the three-terminal stabilized chip. In addition, the multi-channel isolation power source proposed in this paper is Small size, high reliability and low price, and it is convenient for power electronic switches that operate on multiple different potentials. Therefore, the research on power supply of power electronic circuit has practical significance.

A Multi-Cycle Q-Modulation for Dynamic Optimization of Inductive Links.

Science.gov (United States)

Lee, Byunghun; Yeon, Pyungwoo; Ghovanloo, Maysam

2016-08-01

This paper presents a new method, called multi-cycle Q-modulation, which can be used in wireless power transmission (WPT) to modulate the quality factor (Q) of the receiver (Rx) coil and dynamically optimize the load impedance to maximize the power transfer efficiency (PTE) in two-coil links. A key advantage of the proposed method is that it can be easily implemented using off-the-shelf components without requiring fast switching at or above the carrier frequency, which is more suitable for integrated circuit design. Moreover, the proposed technique does not need any sophisticated synchronization between the power carrier and Q-modulation switching pulses. The multi-cycle Q-modulation is analyzed theoretically by a lumped circuit model, and verified in simulation and measurement using an off-the-shelf prototype. Automatic resonance tuning (ART) in the Rx, combined with multi-cycle Q-modulation helped maximizing PTE of the inductive link dynamically in the presence of environmental and loading variations, which can otherwise significantly degrade the PTE in multi-coil settings. In the prototype conventional 2-coil link, the proposed method increased the power amplifier (PA) plus inductive link efficiency from 4.8% to 16.5% at ( R L = 1 kΩ, d 23 = 3 cm), and from 23% to 28.2% at ( R L = 100 Ω, d 23 = 3 cm) after 11% change in the resonance capacitance, while delivering 168.1 mW to the load (PDL).

High-Temperature, Wirebondless, Ultracompact Wide Bandgap Power Semiconductor Modules

Science.gov (United States)

Elmes, John

2015-01-01

Silicon carbide (SiC) and other wide bandgap semiconductors offer great promise of high power rating, high operating temperature, simple thermal management, and ultrahigh power density for both space and commercial power electronic systems. However, this great potential is seriously limited by the lack of reliable high-temperature device packaging technology. This Phase II project developed an ultracompact hybrid power module packaging technology based on the use of double lead frames and direct lead frame-to-chip transient liquid phase (TLP) bonding that allows device operation up to 450 degC. The new power module will have a very small form factor with 3-5X reduction in size and weight from the prior art, and it will be capable of operating from 450 degC to -125 degC. This technology will have a profound impact on power electronics and energy conversion technologies and help to conserve energy and the environment as well as reduce the nation's dependence on fossil fuels.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An FPGA design flow for reconfigurable network-based multi-processor systems on chip

NARCIS (Netherlands)

Kumar, A.; Hansson, M.A; Huisken, J.; Corporaal, H.

2007-01-01

Multi-processor systems on chip (MPSoC) platforms are becoming increasingly more heterogeneous and are shifting towards a more communication-centric methodology. Networks on chip (NoC) have emerged as the design paradigm for scalable on-chip communication architectures. As the system complexity

Importance of the multi-modules study in PSA

International Nuclear Information System (INIS)

Gonzalez R, V. J.; Nelson E, P. F.

2015-09-01

The current approach that has taken the Probabilistic Safety Analysis (PSA) consists of doing all the APS analysis including the existence of multi-units in the nuclear power plants (NPP), this new approach seeks to analyze the risk of site, evaluating all reactors together. The main reasons for this trend are: the accident occurred on March 2011 in Fukushima Daiichi in Japan, with serious consequences in more than one reactor of the NPP and the current planning and construction of new Small Modular Reactors, which host more than one module on the same NPP and are connected to a single control room. This study analyzes how to model the risk of a multi-module NPP. In 2013, the ASME/ANS standard for advanced reactors that are not light-water reactors was published, in which the requirements to realize a PSA including multi-units or modules are shown; however, does not describe the methodology to do that. This article presents a methodology to calculate the risk of the site in a PBMR plant with two modules. This methodology consists of two models of trees of different events, one that evaluates to a single PBMR module and another that evaluates the two modules together. Both models are responsible to show their differences and compare results to finally demonstrate the need for new methodologies for risk analysis site in multi-modules and units. (Author)

End user reliability assessment of 1.2-1.7 kV commercial SiC MOSFET power modules

DEFF Research Database (Denmark)

Ionita, Claudiu; Nawaz, Muhammad

2017-01-01

This paper is a first attempt to offer reliability evaluation of full SiC power modules where several dies are connected in parallel to increase power rating capability. Here, five different power modules with voltage rating from 1.2-1.7 kV and current rating from 120-800 A from three vendors hav......, which is connected in parallel with the MOSFET chip. For another module, there has also been recorded a failure of the gate oxide during H3TRB....

Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

CERN Document Server

Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

2014-01-01

In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects

International Nuclear Information System (INIS)

Sangirov Jamshid; Ukaegbu Ikechi Augustine; Lee Tae-Woo; Park Hyo-Hoon; Sangirov Gulomjon

2013-01-01

A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm 2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. (semiconductor integrated circuits)

A new multi-purpose NIM module

International Nuclear Information System (INIS)

Dong Binjiang; Wang Congrong; Du Chunxiang.

1992-01-01

The authors briefly state the function, character and main technique performance of a new multi-purpose NIM interposition (NI01) developed recently. This interposition uses 8031 single-chip microprocessors as the kernel and is multi-purpose, reliable and convenient. Especially, it is suitable for training teaching and scientific researching

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

DEFF Research Database (Denmark)

Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

2002-01-01

is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more......This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

Rearrangeable and exchangeable optical module with system-on-chip for wearable functional near-infrared spectroscopy system.

Science.gov (United States)

Funane, Tsukasa; Numata, Takashi; Sato, Hiroki; Hiraizumi, Shinsuke; Hasegawa, Yuichi; Kuwabara, Hidenobu; Hasegawa, Kiyoshi; Kiguchi, Masashi

2018-01-01

We developed a system-on-chip (SoC)-incorporated light-emitting diode (LED) and avalanche photodiode (APD) modules to improve the usability and flexibility of a fiberless wearable functional near-infrared spectroscopy (fNIRS) system. The SoC has a microprocessing unit and programmable circuits. The time division method and the lock-in method were used for separately detecting signals from different positions and signals of different wavelengths, respectively. Each module autonomously works for this time-divided-lock-in measurement with a high sensitivity for haired regions. By supplying [Formula: see text] of power and base and data clocks, the LED module emits both 730- and 855-nm wavelengths of light, amplitudes of which are modulated in each lock-in frequency generated from the base clock, and the APD module provides the lock-in detected signals synchronizing with the data clock. The SoC provided many functions, including automatic-power-control of the LED, automatic judgment of detected power level, and automatic-gain-control of the programmable gain amplifier. The number and the arrangement of modules can be adaptively changed by connecting this exchangeable modules in a daisy chain and setting the parameters dependent on the probing position. Therefore, users can configure a variety of arrangements (single- or multidistance combinations) of them with this module-based system.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

Energy Technology Data Exchange (ETDEWEB)

Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

2011-08-11

The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

Ring resonator-based on-chip modulation transformer for high-performance phase-modulated microwave photonic links.

Science.gov (United States)

Zhuang, Leimeng; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Heideman, René; van Dijk, Paulus; Roeloffzen, Chris

2013-11-04

In this paper, we propose and experimentally demonstrate a novel wideband on-chip photonic modulation transformer for phase-modulated microwave photonic links. The proposed device is able to transform phase-modulated optical signals into intensity-modulated versions (or vice versa) with nearly zero conversion of laser phase noise to intensity noise. It is constructed using waveguide-based ring resonators, which features simple architecture, stable operation, and easy reconfigurability. Beyond the stand-alone functionality, the proposed device can also be integrated with other functional building blocks of photonic integrated circuits (PICs) to create on-chip complex microwave photonic signal processors. As an application example, a PIC consisting of two such modulation transformers and a notch filter has been designed and realized in TriPleX(TM) waveguide technology. The realized device uses a 2 × 2 splitting circuit and 3 ring resonators with a free spectral range of 25 GHz, which are all equipped with continuous tuning elements. The device can perform phase-to-intensity modulation transform and carrier suppression simultaneously, which enables high-performance phase-modulated microwave photonics links (PM-MPLs). Associated with the bias-free and low-complexity advantages of the phase modulators, a single-fiber-span PM-MPL with a RF bandwidth of 12 GHz (3 dB-suppression band 6 to 18 GHz) has been demonstrated comprising the proposed PIC, where the achieved spurious-free dynamic range performance is comparable to that of Class-AB MPLs using low-biased Mach-Zehnder modulators.

Compact silicon photonics-based multi laser module for sensing

Science.gov (United States)

Ayotte, S.; Costin, F.; Babin, A.; Paré-Olivier, G.; Morin, M.; Filion, B.; Bédard, K.; Chrétien, P.; Bilodeau, G.; Girard-Deschênes, E.; Perron, L.-P.; Davidson, C.-A.; D'Amato, D.; Laplante, M.; Blanchet-Létourneau, J.

2018-02-01

A compact three-laser source for optical sensing is presented. It is based on a low-noise implementation of the Pound Drever-Hall method and comprises high-bandwidth optical phase-locked loops. The outputs from three semiconductor distributed feedback lasers, mounted on thermo-electric coolers (TEC), are coupled with micro-lenses into a silicon photonics (SiP) chip that performs beat note detection and several other functions. The chip comprises phase modulators, variable optical attenuators, multi-mode-interference couplers, variable ratio tap couplers, integrated photodiodes and optical fiber butt-couplers. Electrical connections between a metallized ceramic and the TECs, lasers and SiP chip are achieved by wirebonds. All these components stand within a 35 mm by 35 mm package which is interfaced with 90 electrical pins and two fiber pigtails. One pigtail carries the signals from a master and slave lasers, while another carries that from a second slave laser. The pins are soldered to a printed circuit board featuring a micro-processor that controls and monitors the system to ensure stable operation over fluctuating environmental conditions. This highly adaptable multi-laser source can address various sensing applications requiring the tracking of up to three narrow spectral features with a high bandwidth. It is used to sense a fiber-based ring resonator emulating a resonant fiber optics gyroscope. The master laser is locked to the resonator with a loop bandwidth greater than 1 MHz. The slave lasers are offset frequency locked to the master laser with loop bandwidths greater than 100 MHz. This high performance source is compact, automated, robust, and remains locked for days.

Fracture mechanics in new designed power module under thermo-mechanical loads

Directory of Open Access Journals (Sweden)

Durand Camille

2014-06-01

Full Text Available Thermo-mechanically induced failure is a major reliability issue in the microelectronic industry. On this account, a new type of Assembly Interconnected Technology used to connect MOSFETs in power modules has been developed. The reliability is increased by using a copper clip soldered on the top side of the chip, avoiding the use of aluminium wire bonds, often responsible for the failure of the device. Thus the new designed MOSFET package does not follow the same failure mechanisms as standard modules. Thermal and power cycling tests were performed on these new packages and resulting failures were analyzed. Thermo-mechanical simulations including cracks in the aluminium metallization and intermetallics (IMC were performed using Finite Element Analysis in order to better understand crack propagation and module behaviour.

Multi-stage decoding of multi-level modulation codes

Science.gov (United States)

Lin, Shu; Kasami, Tadao; Costello, Daniel J., Jr.

1991-01-01

Various types of multi-stage decoding for multi-level modulation codes are investigated. It is shown that if the component codes of a multi-level modulation code and types of decoding at various stages are chosen properly, high spectral efficiency and large coding gain can be achieved with reduced decoding complexity. Particularly, it is shown that the difference in performance between the suboptimum multi-stage soft-decision maximum likelihood decoding of a modulation code and the single-stage optimum soft-decision decoding of the code is very small, only a fraction of dB loss in signal to noise ratio at a bit error rate (BER) of 10(exp -6).

Power and Thermal Management of System-on-Chip

DEFF Research Database (Denmark)

Liu, Wei

, are necessary at the chip design level. In this work, we investigate the power and thermal management of System-on- Chips (SoCs). Thermal analysis is performed in a SPICE simulation approach based on the electrical-thermal analogy. We investigate the impact of inter- connects on heat distribution...

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

Science.gov (United States)

Lee, Dasheng

2008-12-02

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Science.gov (United States)

Lee, Dasheng

2008-01-01

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Directory of Open Access Journals (Sweden)

Dasheng Lee

2008-12-01

Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

Multi-Gigahertz radar range processing of baseband and RF carrier modulated signals in Tm:YAG

International Nuclear Information System (INIS)

Merkel, K.D.; Krishna Mohan, R.; Cole, Z.; Chang, T.; Olson, A.; Babbitt, W.R.

2004-01-01

An optical device is described and demonstrated that uses a spatial-spectral holographic material to perform coherent signal processing operations on analog, high-bandwidth optical signals with large time-bandwidth-products. Signal processing is performed as the material records the coherent spectral interference (or cross-power spectrum) of modulated optical signals as a spatial-spectral population grating between electronic transition states. Multiple exposures of processing pulse sequences are integrated with increasing grating strength. The device, coined as the Spatial-Spectral Coherent Holographic Integrating Processor (or S 2 -CHIP), is described as currently envisioned for a broadband, mid-to-high pulse repetition frequency range-Doppler radar signal processing system. Experiments were performed in Tm:YAG (0.1 at% at 5 K) to demonstrate time delay variation, integration dynamics, and effects of coding as applied to a radar range processor. These demonstrations used baseband modulation with a 1 gigabit per second (GPBS) bit rate and code length of 512 bits (512 ns), where delays up to 1.0 μs were resolved with greater than a 40 dB peak to RMS sidelobe ratio after 800 processing shots. Multi-GHz processing was demonstrated using a bit rate of 2.5 GBPS (baseband modulation) and code length of 2048 bits (819.2 ns). Processing of double-sideband modulated signals on a radio frequency (RF) carrier was demonstrated, where 512 bit, 1.0 GBPS codes were modulated on a 1.75 GHz carrier and then modulated on the optical carrier

60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

KAUST Repository

Ghaffar, Farhan A.

2014-04-01

A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

60 GHz system-on-chip (SoC) with built-in memory and an on-chip antenna

KAUST Repository

Ghaffar, Farhan A.; Arsalan, Muhammad; Cheema, Hammad; Salama, Khaled N.; Shamim, Atif

2014-01-01

A novel 60 GHz transmitter SoC with an on-chip antenna and integrated memory in CMOS 65 nm technology is presented in this paper. This highly integrated transmitter design can support a data rate of 2 GBPS with a transmission range of 1 m. The transmitter consists of a fundamental frequency 60 GHz PLL which covers the complete ISM band. The modulator following the PLL can support both BPSK and OOK modulation schemes. Both stored data on the integrated memory or directly from an external source can be transmitted. A tapered slot on chip antenna is integrated with the power amplifier to complete the front end of the transmitter design. Size of the complete transmitter with on-chip antenna is only 1.96 mm × 1.96 mm. The core circuits consume less than 100 mW of power. The high data rate capability of the design makes it extremely suitable for bandwidth hungry applications such as unencrypted HD video streaming and transmission.

Multi-target electrochemical biosensing enabled by integrated CMOS electronics

International Nuclear Information System (INIS)

Rothe, J; Lewandowska, M K; Heer, F; Frey, O; Hierlemann, A

2011-01-01

An integrated electrochemical measurement system, based on CMOS technology, is presented, which allows the detection of several analytes in parallel (multi-analyte) and enables simultaneous monitoring at different locations (multi-site). The system comprises a 576-electrode CMOS sensor chip, an FPGA module for chip control and data processing, and the measurement laptop. The advantages of the highly versatile system are demonstrated by two applications. First, a label-free, hybridization-based DNA sensor is enabled by the possibility of large-scale integration in CMOS technology. Second, the detection of the neurotransmitter choline is presented by assembling the chip with biosensor microprobe arrays. The low noise level enables a limit of detection of, e.g., 0.3 µM choline. The fully integrated system is self-contained: it features cleaning, functionalization and measurement functions without the need for additional electrical equipment. With the power supplied by the laptop, the system is very suitable for on-site measurements

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips.

Directory of Open Access Journals (Sweden)

Peter Loskill

Full Text Available Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates.

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips.

Science.gov (United States)

Loskill, Peter; Marcus, Sivan G; Mathur, Anurag; Reese, Willie Mae; Healy, Kevin E

2015-01-01

Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

Science.gov (United States)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

A multi-staining chip using hydrophobic valves for exfoliative cytology in cancer

Science.gov (United States)

Lee, Tae Hee; Bu, Jiyoon; Moon, Jung Eun; Kim, Young Jun; Kang, Yoon-Tae; Cho, Young-Ho; Kim, In Sik

2017-07-01

Exfoliative cytology is a highly established technique for the diagnosis of tumors. Various microfluidic devices have been developed to minimize the sample numbers by conjugating multiple antibodies in a single sample. However, the previous multi-staining devices require complex control lines and valves operated by external power sources, to deliver multiple antibodies separately for a single sample. In addition, most of these devices are composed of hydrophobic materials, causing unreliable results due to the non-specific binding of antibodies. Here, we present a multi-staining chip using hydrophobic valves, which is formed by the partial treatment of 2-hydroxyethyl methacrylate (HEMA). Our chip consists of a circular chamber, divided into six equal fan-shaped regions. Switchable injection ports are located at the center of the chamber and at the middle of the arc of each fan-shaped zone. Thus, our device is beneficial for minimizing the control lines, since pre-treatment solutions flow from the center to outer ports, while six different antibodies are introduced oppositely from the outer ports. Furthermore, hydrophobic narrow channels, connecting the central region and each of the six fan-shaped zones, are closed by capillary effect, thus preventing the fluidic mixing without external power sources. Meanwhile, HEMA treatment on the exterior region results in hydrophobic-to-hydrophilic transition and prevents the non-specific binding of antibodies. For the application, we measured the expression of six different antibodies in a single sample using our device. The expression levels of each antibody highly matched the conventional immunocytochemistry results. Our device enables cancer screening with a small number of antibodies for a single sample.

A multi-staining chip using hydrophobic valves for exfoliative cytology in cancer

International Nuclear Information System (INIS)

Lee, Tae Hee; Bu, Jiyoon; Kim, Young Jun; Kang, Yoon-Tae; Cho, Young-Ho; Moon, Jung Eun; Kim, In Sik

2017-01-01

Exfoliative cytology is a highly established technique for the diagnosis of tumors. Various microfluidic devices have been developed to minimize the sample numbers by conjugating multiple antibodies in a single sample. However, the previous multi-staining devices require complex control lines and valves operated by external power sources, to deliver multiple antibodies separately for a single sample. In addition, most of these devices are composed of hydrophobic materials, causing unreliable results due to the non-specific binding of antibodies. Here, we present a multi-staining chip using hydrophobic valves, which is formed by the partial treatment of 2-hydroxyethyl methacrylate (HEMA). Our chip consists of a circular chamber, divided into six equal fan-shaped regions. Switchable injection ports are located at the center of the chamber and at the middle of the arc of each fan-shaped zone. Thus, our device is beneficial for minimizing the control lines, since pre-treatment solutions flow from the center to outer ports, while six different antibodies are introduced oppositely from the outer ports. Furthermore, hydrophobic narrow channels, connecting the central region and each of the six fan-shaped zones, are closed by capillary effect, thus preventing the fluidic mixing without external power sources. Meanwhile, HEMA treatment on the exterior region results in hydrophobic-to-hydrophilic transition and prevents the non-specific binding of antibodies. For the application, we measured the expression of six different antibodies in a single sample using our device. The expression levels of each antibody highly matched the conventional immunocytochemistry results. Our device enables cancer screening with a small number of antibodies for a single sample. (paper)

Importance of the multi-modules study in PSA; Importancia del estudio de multi-modulos en APS

Energy Technology Data Exchange (ETDEWEB)

Gonzalez R, V. J.; Nelson E, P. F., E-mail: judith_gonzalez_rodriguez@outlook.es [UNAM, Facultad de Ingenieria, Departamento de Sistemas Energeticos, Paseo Cuauhnahuac 8532, 62550 Jiutepec, Morelos (Mexico)

2015-09-15

The current approach that has taken the Probabilistic Safety Analysis (PSA) consists of doing all the APS analysis including the existence of multi-units in the nuclear power plants (NPP), this new approach seeks to analyze the risk of site, evaluating all reactors together. The main reasons for this trend are: the accident occurred on March 2011 in Fukushima Daiichi in Japan, with serious consequences in more than one reactor of the NPP and the current planning and construction of new Small Modular Reactors, which host more than one module on the same NPP and are connected to a single control room. This study analyzes how to model the risk of a multi-module NPP. In 2013, the ASME/ANS standard for advanced reactors that are not light-water reactors was published, in which the requirements to realize a PSA including multi-units or modules are shown; however, does not describe the methodology to do that. This article presents a methodology to calculate the risk of the site in a PBMR plant with two modules. This methodology consists of two models of trees of different events, one that evaluates to a single PBMR module and another that evaluates the two modules together. Both models are responsible to show their differences and compare results to finally demonstrate the need for new methodologies for risk analysis site in multi-modules and units. (Author)

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

Science.gov (United States)

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

DEFF Research Database (Denmark)

Beczkowski, Szymon; Jørgensen, Asger Bjørn; Li, Helong

2017-01-01

Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries....... Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed...... in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on....

Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3

International Nuclear Information System (INIS)

Loecker, M.

2007-04-01

Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 μm 2 pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e - ). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed

A deterministic guide for material and mode dependence of on-chip electro-optic modulator performance

Science.gov (United States)

Amin, Rubab; Suer, Can; Ma, Zhizhen; Sarpkaya, Ibrahim; Khurgin, Jacob B.; Agarwal, Ritesh; Sorger, Volker J.

2017-10-01

Electro-optic modulation is a key function in optical data communication and possible future optical computing engines. The performance of modulators intricately depends on the interaction between the actively modulated material and the propagating waveguide mode. While high-performing modulators were demonstrated before, the approaches were taken as ad-hoc. Here we show the first systematic investigation to incorporate a holistic analysis for high-performance and ultra-compact electro-optic modulators on-chip. We show that intricate interplay between active modulation material and optical mode plays a key role in the device operation. Based on physical tradeoffs such as index modulation, loss, optical confinement factors and slow-light effects, we find that bias-material-mode regions exist where high phase modulation and high loss (absorption) modulation is found. This work paves the way for a holistic design rule of electro-optic modulators for on-chip integration.

Optimizing Energy and Modulation Selection in Multi-Resolution Modulation For Wireless Video Broadcast/Multicast

KAUST Repository

She, James

2009-11-01

Emerging technologies in Broadband Wireless Access (BWA) networks and video coding have enabled high-quality wireless video broadcast/multicast services in metropolitan areas. Joint source-channel coded wireless transmission, especially using hierarchical/superposition coded modulation at the channel, is recognized as an effective and scalable approach to increase the system scalability while tackling the multi-user channel diversity problem. The power allocation and modulation selection problem, however, is subject to a high computational complexity due to the nonlinear formulation and huge solution space. This paper introduces a dynamic programming framework with conditioned parsing, which significantly reduces the search space. The optimized result is further verified with experiments using real video content. The proposed approach effectively serves as a generalized and practical optimization framework that can gauge and optimize a scalable wireless video broadcast/multicast based on multi-resolution modulation in any BWA network.

Optimizing Energy and Modulation Selection in Multi-Resolution Modulation For Wireless Video Broadcast/Multicast

KAUST Repository

She, James; Ho, Pin-Han; Shihada, Basem

2009-01-01

Emerging technologies in Broadband Wireless Access (BWA) networks and video coding have enabled high-quality wireless video broadcast/multicast services in metropolitan areas. Joint source-channel coded wireless transmission, especially using hierarchical/superposition coded modulation at the channel, is recognized as an effective and scalable approach to increase the system scalability while tackling the multi-user channel diversity problem. The power allocation and modulation selection problem, however, is subject to a high computational complexity due to the nonlinear formulation and huge solution space. This paper introduces a dynamic programming framework with conditioned parsing, which significantly reduces the search space. The optimized result is further verified with experiments using real video content. The proposed approach effectively serves as a generalized and practical optimization framework that can gauge and optimize a scalable wireless video broadcast/multicast based on multi-resolution modulation in any BWA network.

A Low Power, Parallel Wearable Multi-Sensor System for Human Activity Evaluation.

Science.gov (United States)

Li, Yuecheng; Jia, Wenyan; Yu, Tianjian; Luan, Bo; Mao, Zhi-Hong; Zhang, Hong; Sun, Mingui

2015-04-01

In this paper, the design of a low power heterogeneous wearable multi-sensor system, built with Zynq System-on-Chip (SoC), for human activity evaluation is presented. The powerful data processing capability and flexibility of this SoC represent significant improvements over our previous ARM based system designs. The new system captures and compresses multiple color images and sensor data simultaneously. Several strategies are adopted to minimize power consumption. Our wearable system provides a new tool for the evaluation of human activity, including diet, physical activity and lifestyle.

MCC: the Module Controller Chip for the ATLAS Pixel Detector

International Nuclear Information System (INIS)

Beccherle, R.; Darbo, G.; Gagliardi, G.; Gemme, C.; Morettini, P.; Musico, P.; Osculati, B.; Oppizzi, P.; Pratolongo, F.; Ruscino, E.; Schiavi, C.; Vernocchi, F.; Blanquart, L.; Einsweiler, K.; Meddeler, G.; Richardson, J.; Comes, G.; Fischer, P.; Calvet, D.; Boyd, R.; Sicho, P.

2002-01-01

In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate

Selective attention in multi-chip address-event systems.

Science.gov (United States)

Bartolozzi, Chiara; Indiveri, Giacomo

2009-01-01

Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the "Selective Attention Chip" (SAC), which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

Directory of Open Access Journals (Sweden)

Ismail Cevik

2015-03-01

Full Text Available An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT-based power management system (PMS is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

A 5.2GHz, 0.5mW RF powered wireless sensor with dual on-chip antennas for implantable intraocular pressure monitoring

KAUST Repository

Arsalan, Muhammad; Ouda, Mahmoud H.; Marnat, Loic; Ahmad, Talha Jamal; Shamim, Atif; Salama, Khaled N.

2013-01-01

For the first time a single chip implantable wireless sensor system for Intraocular Pressure Monitoring (IOPM) is presented. This system-on-chip (SoC) is battery-free and harvests energy from incoming RF signals. The chip is self-contained and does not require external components or bond wires to function. This 1.4mm3 SoC has separate 2.4GHz-transmit and 5.2GHz-receive antennas, an energy harvesting module, a temperature sensor, a 7-bit TIQ Flash ADC, a 4-bit RFID, a power management and control unit, and a VCO transmitter. The chip is fabricated in a standard 6-metal 0.18μm CMOS process and is designed to work with a post-processed MEMS pressure sensor. It consumes 513μW of peak power and when implanted inside the eye, it is designed to communicate with an external reader using on-off keying (OOK). © 2013 IEEE.

A 5.2GHz, 0.5mW RF powered wireless sensor with dual on-chip antennas for implantable intraocular pressure monitoring

KAUST Repository

Arsalan, Muhammad

2013-06-01

For the first time a single chip implantable wireless sensor system for Intraocular Pressure Monitoring (IOPM) is presented. This system-on-chip (SoC) is battery-free and harvests energy from incoming RF signals. The chip is self-contained and does not require external components or bond wires to function. This 1.4mm3 SoC has separate 2.4GHz-transmit and 5.2GHz-receive antennas, an energy harvesting module, a temperature sensor, a 7-bit TIQ Flash ADC, a 4-bit RFID, a power management and control unit, and a VCO transmitter. The chip is fabricated in a standard 6-metal 0.18μm CMOS process and is designed to work with a post-processed MEMS pressure sensor. It consumes 513μW of peak power and when implanted inside the eye, it is designed to communicate with an external reader using on-off keying (OOK). © 2013 IEEE.

System on chip module configured for event-driven architecture

Science.gov (United States)

Robbins, Kevin; Brady, Charles E.; Ashlock, Tad A.

2017-10-17

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

Multi-stage decoding for multi-level block modulation codes

Science.gov (United States)

Lin, Shu

1991-01-01

In this paper, we investigate various types of multi-stage decoding for multi-level block modulation codes, in which the decoding of a component code at each stage can be either soft-decision or hard-decision, maximum likelihood or bounded-distance. Error performance of codes is analyzed for a memoryless additive channel based on various types of multi-stage decoding, and upper bounds on the probability of an incorrect decoding are derived. Based on our study and computation results, we find that, if component codes of a multi-level modulation code and types of decoding at various stages are chosen properly, high spectral efficiency and large coding gain can be achieved with reduced decoding complexity. In particular, we find that the difference in performance between the suboptimum multi-stage soft-decision maximum likelihood decoding of a modulation code and the single-stage optimum decoding of the overall code is very small: only a fraction of dB loss in SNR at the probability of an incorrect decoding for a block of 10(exp -6). Multi-stage decoding of multi-level modulation codes really offers a way to achieve the best of three worlds, bandwidth efficiency, coding gain, and decoding complexity.

Modeling and Simulation of the Multi-module High Temperature Gas-cooled Reactor

International Nuclear Information System (INIS)

Liu Dan; Sun Jun; Sui Zhe; Xu Xiaolin; Ma Yuanle; Sun Yuliang

2014-01-01

The modular high temperature gas-cooled reactor (MHTGR) is characterized with the inherent safety. To enhance its economic benefit, the capital cost of MHTGR can be decreased by combining more reactor modules into one unit and realize the batch constructions in the concept of modularization. In the research and design of the multi-module reactors, one difficulty is to clarify the coupling effects of different modules in operating the reactors due to the shared feed water and main steam systems in the secondary loop. In the advantages of real-time simulation and coupling calculations of different modules and sub-systems, the operation of multi-module reactors can be studied and analyzed to understand the range and extent of the coupling effects. In the current paper; the engineering simulator for the multi-module reactors was realized and able to run in high performance computers, based on the research experience of the HTR-PM engineering simulator. The models were detailed introduced including the primary and secondary loops. The steady state of full power operation was demonstrated to show the good performance of six-module reactors. Typical dynamic processes, such as adjusting feed water flow rates and shutting down one reactor; were also tested to study the coupling effects in multi-module reactors. (author)

A multi-resolution envelope-power based model for speech intelligibility

DEFF Research Database (Denmark)

Jørgensen, Søren; Ewert, Stephan D.; Dau, Torsten

2013-01-01

The speech-based envelope power spectrum model (sEPSM) presented by Jørgensen and Dau [(2011). J. Acoust. Soc. Am. 130, 1475-1487] estimates the envelope power signal-to-noise ratio (SNRenv) after modulation-frequency selective processing. Changes in this metric were shown to account well...... to conditions with stationary interferers, due to the long-term integration of the envelope power, and cannot account for increased intelligibility typically obtained with fluctuating maskers. Here, a multi-resolution version of the sEPSM is presented where the SNRenv is estimated in temporal segments...... with a modulation-filter dependent duration. The multi-resolution sEPSM is demonstrated to account for intelligibility obtained in conditions with stationary and fluctuating interferers, and noisy speech distorted by reverberation or spectral subtraction. The results support the hypothesis that the SNRenv...

Troubleshooting of Modulator DC power supply at KOMAC

Energy Technology Data Exchange (ETDEWEB)

Jeong, Hae Seong; Kim, Han Sung; Kwon, Hyeok Jung; Kim, Seong Gu; Kim, Dae Il; Lee, Seok Geun; Kim, Jae Ha; Seol, Kyeong Tae; Cho, Yong Sub [KAERI, Daejeon (Korea, Republic of)

2016-05-15

The process of solving problems to operate the 2nd converter modulator will be introduced. Also, the PSpice simulation result about the 12-pulse rectifier will be compared with the measurement result. KOMAC (KOrea Multi-purpose Accelerator Complex) has four HVCMs (High Voltage Converter Modulator) which are the power source of nine klystrons. Four HVCMs are already operated since 2013 for operating the 100 MeV linear proton accelerator at KOMAC. This HVCM system includes the 12-pulse rectifier (ac-dc), capacitors bank (dc-link, Pos, Neg) and converter modulator (dc-dc). Especially, the 12-pulse rectifier system receives the power from the utility and converts 3,300 ac voltage to 2,200 dc voltage for supplying the dc power to the capacitors bank. This rectifier system used twelve thyristors for the rectification and applied RC snubber networks to protect the semiconductor switches (thyristors). Since the 2nd modulator dc power supply has troubled, the troubleshooting process conducted by the staves of KOMAC. It takes 3 months to solve the problems because it is not easy to find the faulty wiring. Nevertheless, our staves found the faulty point with a hope to operate the modulator system and the PSpice simulation helps to solve the problems. Using PSpice which is tool for simulating the circuit, the dc power supply abnormal phenomenon was simulated exactly. After corrected the faulty wiring, the modulator dc power supply operated.

Multi-angle lensless digital holography for depth resolved imaging on a chip

Science.gov (United States)

Su, Ting-Wei; Isikman, Serhan O.; Bishara, Waheb; Tseng, Derek; Erlinger, Anthony; Ozcan, Aydogan

2010-01-01

A multi-angle lensfree holographic imaging platform that can accurately characterize both the axial and lateral positions of cells located within multi-layered micro-channels is introduced. In this platform, lensfree digital holograms of the micro-objects on the chip are recorded at different illumination angles using partially coherent illumination. These digital holograms start to shift laterally on the sensor plane as the illumination angle of the source is tilted. Since the exact amount of this lateral shift of each object hologram can be calculated with an accuracy that beats the diffraction limit of light, the height of each cell from the substrate can be determined over a large field of view without the use of any lenses. We demonstrate the proof of concept of this multi-angle lensless imaging platform by using light emitting diodes to characterize various sized microparticles located on a chip with sub-micron axial and lateral localization over ~60 mm2 field of view. Furthermore, we successfully apply this lensless imaging approach to simultaneously characterize blood samples located at multi-layered micro-channels in terms of the counts, individual thicknesses and the volumes of the cells at each layer. Because this platform does not require any lenses, lasers or other bulky optical/mechanical components, it provides a compact and high-throughput alternative to conventional approaches for cytometry and diagnostics applications involving lab on a chip systems. PMID:20588819

Radiation effect characterization and test methods of single-chip and multi-chip stacked 16Mbit DRAMs

International Nuclear Information System (INIS)

LaBel, K.A.; Gates, M.M.; Moran, A.K.; Kim, H.S.; Seidleck, C.M.; Marshall, P.; Kinnison, J.; Carkhuff, B.

1996-01-01

This paper presents radiation effects characterization performed by the NASA Goddard Space Flight Center (GSFC) on spaceflight candidate 16Mbit DRAMs. This includes heavy ion, proton, and Co60 irradiations on single-chip devices as well as proton irradiation of a stacked DRAM module. Lastly, a discussion of test methodology is undertaken

Design of a 2.5MW(e) biomass gasification power generation module

Energy Technology Data Exchange (ETDEWEB)

McLellan, R.

2000-07-01

The purpose of this contract was to produce a detailed process and mechanical design of a gasification and gas clean up system for a 2.5MW(e) power generation module based on the generation of electrical power from a wood chip feed stock. The design is to enable the detailed economic evaluation of the process and to verify the technical performance data provided by the pilot plant programme. Detailed process and equipment design also assists in the speed at which the technology can be implemented into a demonstration project. (author)

Studies on the coordinated operation and autonomous control for multi-modular nuclear power plants

International Nuclear Information System (INIS)

Hui Chao; Huang Xiaojin; Wang Jie

2011-01-01

The tendency has always been to build ever larger single-modular reactor plants with the objective of benefiting from economies of scale. These plants have compiled admirable safety records. Nevertheless, there is concern that conventional large single reactors have become too complex by reason of placing too much reliance on engineered safeguards. The multi-modular approach offers a solution in that its use of many small reactors in conjunction with several shared turbines permits a simpler core design while, at the same time, at least partially retaining economies of scale by increasing the number of modules. Specific advantages to the multi-modular approach are as follows. First, the small-sized of the reactor core may allow the incorporation of passive safety features such as natural circulation cooling on loss of off-site electricity. Second, the individual modules are to be sized so that components related to nuclear safety can be factory-fabricated. Moreover, once the major components are made, they are to be transported to the site for rapid installation. This construction method is expected to reduce the licensing effort because the modules will be pre-licensed, and only site-specific issues will have to be considered in the final licensing process. At present, related studies show that the multi-modular approach for Generation IV can retain both the inherent safety and good economies of scale. However, the unbalanced load operation of the multi-modular power plant in which each module operates at a different power level and strong coupling between multi modules creates a complex control challenge to safe operation and control. Firstly, this paper summarizes the unbalanced load operation characteristics and challenges faced by operation and control of multi-modular power plant in the dynamic operational characteristics and requirements of coordinated control between multi modules. Secondly, detailed analysis and comparison are given in the integral

Multi-reactor power system configurations for multimegawatt nuclear electric propulsion

Science.gov (United States)

George, Jeffrey A.

1991-01-01

A modular, multi-reactor power system and vehicle configuration for piloted nuclear electric propulsion (NEP) missions to Mars is presented. Such a design could provide enhanced system and mission reliability, allowing a comfortable safety margin for early manned flights, and would allow a range of piloted and cargo missions to be performed with a single power system design. Early use of common power modules for cargo missions would also provide progressive flight experience and validation of standardized systems for use in later piloted applications. System and mission analysis are presented to compare single and multi-reactor configurations for piloted Mars missions. A conceptual design for the Hydra modular multi-reactor NEP vehicle is presented.

Interference control by best-effort process duty-cycling in chip multi-processor systems for real-time medical image processing

NARCIS (Netherlands)

Westmijze, M.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria

2013-01-01

Systems with chip multi-processors are currently used for several applications that have real-time requirements. In chip multi-processor architectures, many hardware resources such as parts of the cache hierarchy are shared between cores and by using such resources, applications can significantly

Development of a new lower hybrid antenna module using a poloidal power divider

International Nuclear Information System (INIS)

Maebara, Sunao; Seki, Masami; Suganuma, Kazuaki

1996-07-01

The antenna using poloidal power divider is an effective method for simplification of Lower Hybrid Current Drive (LHCD) antenna system. This method should allow to reduce the power density in the antenna while maintaining a good flexibility of N parallel spectrum of waves. For this purpose, three types of poloidal power divider which split the power in three, and the 3 x 6 multi-junction module were developed. r.f. properties and outgassing of these components were evaluated using the CEA Cadarache RF Test Facility. A good power dividing ratio of 33 ± 4% was obtained for each of these poloidal dividers, and the reflection coefficient was lower value than 1.5%. For the 3 x 6 multi-junction, reflection coefficient was less than 1.3% and r.f. losses lower than 1.0% were measured. On the other hand, it was found in the scattering matrix analysis that reflection coefficient at plasma has to be less than a few % in order to operate these components under available conditions. In combination with two poloidal power dividers connected to the 3 x 6 multi-junction module, quasi stationary operation for r.f. injection time of 1000 sec at 300 kW was demonstrated under water cooling. In this case, it was found that the outgassing rate is in the lower range of 10 -7 Pam 3 s -1 m -2 within the maximum module temperature of ∼100degC. This report describes the experimental and analytical results of a new lower hybrid (LH) antenna module using the poloidal power divider. (author)

Low-cost low-power UHF RFID tag with on-chip antenna

Energy Technology Data Exchange (ETDEWEB)

Xi Jingtian; Yan Na; Che Wenyi; Xu Conghui; Wang Xiao; Yang Yuqing; Jian Hongyan; Min Hao, E-mail: jtxi@fudan.edu.c [State Key Laboratory of ASIC and System, Auto-ID Laboratory, Fudan University, Shanghai 201203 (China)

2009-07-15

This paper presents an EPC Class 1 Generation 2 compatible tag with on-chip antenna implemented in the SMIC 0.18 {mu}m standard CMOS process. The UHF tag chip includes an RF/analog front-end, a digital baseband, and a 640-bit EEPROM memory. The on-chip antenna is optimized based on a novel parasitic-aware model. The rectifier is optimized to achieve a power conversion efficiency up to 40% by applying a self-bias feedback and threshold compensation techniques. A good match between the tag circuits and the on-chip antenna is realized by adjusting the rectifier input impedance. Measurements show that the presented tag can achieve a communication range of 1 cm with 1 W reader output power using a 1 x 1 cm{sup 2} single-turn loop reader antenna.

Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

Energy Technology Data Exchange (ETDEWEB)

Kaipainen, H; Seppaenen, V

1997-12-31

The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

Wood harvesting as chunkwood chips and multi-stage chipping; Puun korjuu palahakkeena ja monivaiheinen lastuaminen

Energy Technology Data Exchange (ETDEWEB)

Kaipainen, H.; Seppaenen, V.

1996-12-31

The task for the year 1995 was to define the preliminary results of the previous years, to measure the productivity of a harvester, designed for production of chunkwood, and the properties of the chunks. The costs of the PALAPUU method from the felling site to pulpwood chips were to be examined on this basis. Because the prototype of the harvester was not yet available for field tests, the costs were partially calculated on the basis of previous measurements, completed by productivity data obtained from the time-consumption measurements of a multi-tree harvester, applied with minor alteration for this purpose. According to the calculations the PALAPUU method cannot compete with partial-tree or shortwood methods. The profitability of the method could be improved by adding the transportation density and the productivity of the harvester. It is also possible to procure timber to the mill as partial-trees and to chunk it while feeding it into the drum. Chipping tests were made using the steel-frame-chipper owned by VTT Construction Technology. The blade construction of the chipper was changed so, that it was possible to adjust the cutting thickness of the chips to 4 mm, while in the previous mill-tests it had been 6 mm. The chips were used for cooking tests in the Department of Chemistry of the University of Jyvaeskylae. The results showed that the thinner chips were cooked further under the same cooking conditions. By using the chunkwood method it is possible to harvest 10-70 more biomass for the mills, than it is possible in the pulpwood harvesting

Multi-level trellis coded modulation and multi-stage decoding

Science.gov (United States)

Costello, Daniel J., Jr.; Wu, Jiantian; Lin, Shu

1990-01-01

Several constructions for multi-level trellis codes are presented and many codes with better performance than previously known codes are found. These codes provide a flexible trade-off between coding gain, decoding complexity, and decoding delay. New multi-level trellis coded modulation schemes using generalized set partitioning methods are developed for Quadrature Amplitude Modulation (QAM) and Phase Shift Keying (PSK) signal sets. New rotationally invariant multi-level trellis codes which can be combined with differential encoding to resolve phase ambiguity are presented.

Investigation of the thermal and optical performance of a spatial light modulator with high average power picosecond laser exposure for materials processing applications

Science.gov (United States)

Zhu, G.; Whitehead, D.; Perrie, W.; Allegre, O. J.; Olle, V.; Li, Q.; Tang, Y.; Dawson, K.; Jin, Y.; Edwardson, S. P.; Li, L.; Dearden, G.

2018-03-01

Spatial light modulators (SLMs) addressed with computer generated holograms (CGHs) can create structured light fields on demand when an incident laser beam is diffracted by a phase CGH. The power handling limitations of these devices based on a liquid crystal layer has always been of some concern. With careful engineering of chip thermal management, we report the detailed optical phase and temperature response of a liquid cooled SLM exposed to picosecond laser powers up to 〈P〉  =  220 W at 1064 nm. This information is critical for determining device performance at high laser powers. SLM chip temperature rose linearly with incident laser exposure, increasing by only 5 °C at 〈P〉  =  220 W incident power, measured with a thermal imaging camera. Thermal response time with continuous exposure was 1-2 s. The optical phase response with incident power approaches 2π radians with average power up to 〈P〉  =  130 W, hence the operational limit, while above this power, liquid crystal thickness variations limit phase response to just over π radians. Modelling of the thermal and phase response with exposure is also presented, supporting experimental observations well. These remarkable performance characteristics show that liquid crystal based SLM technology is highly robust when efficiently cooled. High speed, multi-beam plasmonic surface micro-structuring at a rate R  =  8 cm2 s-1 is achieved on polished metal surfaces at 〈P〉  =  25 W exposure while diffractive, multi-beam surface ablation with average power 〈P〉  =100 W on stainless steel is demonstrated with ablation rate of ~4 mm3 min-1. However, above 130 W, first order diffraction efficiency drops significantly in accord with the observed operational limit. Continuous exposure for a period of 45 min at a laser power of 〈P〉  =  160 W did not result in any detectable drop in diffraction efficiency, confirmed afterwards by the efficient

Multi-kilowatt modularized spacecraft power processing system development

International Nuclear Information System (INIS)

Andrews, R.E.; Hayden, J.H.; Hedges, R.T.; Rehmann, D.W.

1975-07-01

A review of existing information pertaining to spacecraft power processing systems and equipment was accomplished with a view towards applicability to the modularization of multi-kilowatt power processors. Power requirements for future spacecraft were determined from the NASA mission model-shuttle systems payload data study which provided the limits for modular power equipment capabilities. Three power processing systems were compared to evaluation criteria to select the system best suited for modularity. The shunt regulated direct energy transfer system was selected by this analysis for a conceptual design effort which produced equipment specifications, schematics, envelope drawings, and power module configurations

Advanced Nanofabrication Process Development for Self-Powered System-on-Chip

KAUST Repository

Rojas, Jhonathan Prieto

2010-11-01

In this work the development of a Self-Powered System-On-Chip is explored by examining two components of process development in different perspectives. On one side, an energy component is approached from a biochemical standpoint where a Microbial Fuel Cell (MFC) is built with standard microfabrication techniques, displaying a novel electrode based on Carbon Nanotubes (CNTs). The fabrication process involves the formation of a micrometric chamber that hosts an enhanced CNT-based anode. Preliminary results are promising, showing a high current density (113.6mA/m2) compared with other similar cells. Nevertheless many improvements can be done to the main design and further characterization of the anode will give a more complete understanding and bring the device closer to a practical implementation. On a second point of view, nano-patterning through silicon nitride spacer width control is developed, aimed at producing alternative sub-100nm device fabrication with the potential of further scaling thanks to nanowire based structures. These nanostructures are formed from a nano-pattern template, by using a bottom-up fabrication scheme. Uniformity and scalability of the process are demonstrated and its potential described. An estimated area of 0.120μm2 for a 6T-SRAM (Static Random Access Memory) bitcell (6 devices) can be achieved. In summary, by using a novel sustainable energy component and scalable nano-patterning for logic and computing module, this work has successfully collected the essential base knowledge and joined two different elements that synergistically will contribute for the future implementation of a Self-Powered System-on-Chip.

On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

Directory of Open Access Journals (Sweden)

Jian Lu

2008-01-01

Full Text Available A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC. We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

Multi-Cluster Network on a Chip Reconfigurable Radiation Hardened Radio, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The objective of the Phase-I research is to architect, model and simulate a multi-cluster Network on a Chip (NoC) reconfigurable Radio in SystemC RTL, with...

Advanced Technology for Ultra-Low Power System-on-Chip (SoC)

Science.gov (United States)

2017-06-01

was proposed for lower power applications with Ioff=10pA/μm and VDD=0.5V. In this project, the optimized structure shows great potential in both Lg...AFRL-RY-WP-TR-2017-0115 ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON-CHIP (SoC) Jason Woo, Weicong Li, and Peng Lu University of California...September 2015 – 31 March 2017 4. TITLE AND SUBTITLE ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON- CHIP (SoC) 5a. CONTRACT NUMBER FA8650-15-1-7574 5b

Data transmission optical link for LLRF TESLA project part I: hardware structure of OPT0 module

Science.gov (United States)

Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Jalmuzna, Wojciech; Olowski, Krzysztof; Perkuszewski, Karol; Zielinski, Jerzy; Kierzkowski, Krzysztof

2006-03-01

It may be predicted now, even assuming a very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals. The paper presents the idea and realization of a gigabit synchronous data distributor designed to work in the LLRF control system of TESLA technology based X-ray FEL. The design bases on a relatively simple and cheap FPGA chip Cyclone. Commercially available SERDES (serializer/deserializer) and optical transceiver chips were applied. The optoelectronic module is embedded on the main LLRF BMB (backbone mother board). The MB provides communication with the outside computer control system, programmable chip configuration, integration with other functional modules and power supply. The hardware implementation is here described and the used software for BER (bit-error-rate) testing of the multi-gigabit optical link. The measurement results are presented. The appendix contains a comparison between the available protocols of serial data transmission for FPGA technology. This paper is a partial contribution to the next version of the SIMCON system which is expected to be released this year. The SIMCON, ver 3.0 will contain 8 channels and multi-gigabit optical transmission capability. It will be a fully modular construction.

Realisation of serial powering of ATLAS pixel modules

CERN Document Server

Stockmanns, Tobias; Fischer, P; Hügging, Fabian Georg; Peric, Ivan; Runólfsson, Ogmundur; Wermes, Norbert

2004-01-01

Modern hybrid pixel detectors as they will be used for the next generation of high energy collider experiments like LHC avail deep sub micron technology for the readout electronics. To operate chips in this technology low supply voltages of 2.0 V to 2.5 V and high currents to achieve the desired performance are needed. Due to the long and low mass supply cables this high current leads to a significant voltage drop so that voltage fluctuations at the chip result, when the supply current changes. Therefore the parallel connection of the readout electronics with the power supplies imposes severe constraints on a detector with respect to voltage fluctuations and cable mass. To bypass this problem a new concept of serially connecting modules in a supply chain was developed. The basic idea of the concept, the potential risk and ways to minimize these risks are presented. In addition, studies of the implementation of this technology as an alternative for a possible upgrade of the ATLAS pixel detector are shown. In p...

Analysis and design of power efficient semi-passive RFID tag

Energy Technology Data Exchange (ETDEWEB)

Che Wenyi; Guan Shuo; Wang Xiao; Xiong Tingwen; Xi Jingtian; Tan Xi; Yan Na; Min Hao, E-mail: yanna@fudan.edu.c [State Key Laboratory of ASIC and System, Auto-ID Laboratory, Fudan University, Shanghai 201203 (China)

2010-07-15

The analysis and design of a semi-passive radio frequency identification (RFID) tag is presented. By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump, the calculation method for semi-passive tag's read range is proposed. According to different read range limitation factors, an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given. A test chip is implemented in SMIC 0.18 {mu}m standard CMOS technology under the guidance of theoretical analysis. The main building blocks are the threshold compensated charge pump and low power wake-up circuit using the power triggering wake-up mode. The proposed semi-passive tag is fully compatible to EPC C1G2 standard. It has a compact chip size of 0.54 mm{sup 2}, and is adaptable to batteries with a 1.2 to 2.4 V output voltage.

Analysis and design of power efficient semi-passive RFID tag

International Nuclear Information System (INIS)

Che Wenyi; Guan Shuo; Wang Xiao; Xiong Tingwen; Xi Jingtian; Tan Xi; Yan Na; Min Hao

2010-01-01

The analysis and design of a semi-passive radio frequency identification (RFID) tag is presented. By studying the power transmission link of the backscatter RFID system and exploiting a power conversion efficiency model for a multi-stage AC-DC charge pump, the calculation method for semi-passive tag's read range is proposed. According to different read range limitation factors, an intuitive way to define the specifications of tag's power budget and backscatter modulation index is given. A test chip is implemented in SMIC 0.18 μm standard CMOS technology under the guidance of theoretical analysis. The main building blocks are the threshold compensated charge pump and low power wake-up circuit using the power triggering wake-up mode. The proposed semi-passive tag is fully compatible to EPC C1G2 standard. It has a compact chip size of 0.54 mm 2 , and is adaptable to batteries with a 1.2 to 2.4 V output voltage.

Mastering multi-depth bio-chip patterns with DVD LBRs

Science.gov (United States)

Carson, Doug

2017-08-01

Bio chip and bio disc are rapidly growing technologies used in medical, health and other industries. While there are numerous unique designs and features, these products all rely on precise three-dimensional micro-fluidic channels or arrays to move, separate and combine samples under test. These bio chip and bio disc consumables are typically manufactured by molding these parts to a precise three-dimensional pattern on a negative metal stamper, or they can be made in smaller quantities using an appropriate curable resin and a negative mold/stamper. Stampers required for bio chips have been traditionally made using either micro machining or XY stepping lithography. Both of these technologies have their advantages as well as limitations when it comes to creating micro-fluidic patterns. Significant breakthroughs in continuous maskless lithography have enabled accurate and efficient manufacturing of micro-fluidic masters using LBRs (Laser Beam Recorders) and DRIE (Deep Reactive Ion Etching). The important advantages of LBR continuous lithography vs. XY stepping lithography and micro machining are speed and cost. LBR based continuous lithography is >100x faster than XY stepping lithography and more accurate than micro machining. Several innovations were required in order to create multi-depth patterns with sub micron accuracy. By combining proven industrial LBRs with DCA's G3-VIA pattern generator and DRIE, three-dimensional bio chip masters and stampers are being manufactured efficiently and accurately.

PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation

DEFF Research Database (Denmark)

Ceccarelli, Lorenzo; Iannuzzo, Francesco; Nawaz, Muhammad

2016-01-01

to simulate the performance of high current rating (above 100 A), multi-chip SiC MOSFET modules both for static and switching behavior. Therefore, the simulation results have been validated experimentally in a wide range of operating conditions, including high temperatures, gate resistance and stray elements....... The whole process has been repeated for three different modules with voltage rating of 1.2 kV and 1.7 kV, manufactured by three different companies. Lastly, a parallel connection of two modules of the same type has been performed in order to observe the unbalancing and mismatches experimentally......The aim of this work is to present a PSpice implementation for a well-established and compact physics-based SiC MOSFET model, including a fast, experimental-based parameter extraction procedure in a MATLAB GUI environment. The model, originally meant for single-die devices, has been used...

Scalability of multi-junction organic solar cells for large area organic solar modules

Science.gov (United States)

Xiao, Xin; Lee, Kyusang; Forrest, Stephen R.

2015-05-01

We investigate the scalability of multi-junction organic photovoltaic cells (OPV) with device areas ranging from 1 mm2 to 1 cm2, as well as 25 cm2 active area solar modules. We find that the series resistance losses in 1 cm2 vs. 1 mm2 OPV cell efficiencies are significantly higher in single junction cells than tandem, triple, and four junction cells due to the lower operating voltage and higher current of the former. Using sub-electrodes to reduce series resistance, the power conversion efficiency (PCE) of multi-junction cells is almost independent of area from 1 mm2 to 1 cm2. Twenty-five, 1 cm2 multi-junction cell arrays are integrated in a module and connected in a series-parallel circuit configuration. A yield of 100% with a deviation of PCE from cell to cell of <10% is achieved. The module generates an output power of 162 ± 9 mW under simulated AM1.5G illumination at one sun intensity, corresponding to PCE = 6.5 ± 0.1%, slightly lower than PCE of discrete cells ranging from 6.7% to 7.2%.

Pulse power modulators - an overview

International Nuclear Information System (INIS)

Venkatramani, N.

2006-01-01

Pulse power modulators are electronic devices to provide, high voltage, high current, power bursts. Ideally, a modulator, with the means to shape and control the pulses, acts as a switch between a high voltage power supply and its load. This article gives an overview of the pulse power modulators: starting with the basics of pulse and modulation, it covers modulation topologies, different types of modulators, major subsystems and pulse measurement techniques. The various applications of pulse power modulators and the recent trends have been included at the end. (author)

PFGA based, full-duplex, multi-channel, optical gigabit, synchronous data transceiver for TESLA technology LLRF control system

Energy Technology Data Exchange (ETDEWEB)

Pozniak, K.T.; Romaniuk, R.S.; Jalmuzna, W.; Olowski, K.; Perkuszewski, K.; Zielinski, J. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems; Kierzkowski, K. [Warsaw Univ. (Poland). Inst. of Experimental Physics

2005-07-01

It may be predicted now, even assuming very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals. The paper presents the idea and realization of a gigabit synchronous data distributor designed to work in the LLRF control system of TESLA technology based X-ray FEL. The design bases on a relatively simple and cheap FPGA chip Cyclone. Commercially available SERDES (serializer/deserializer) and optical transceiver chips were applied. The optoelectronic module is embedded on the main LLRF BMB (backbone mother board). The MB provides communication with the outside computer control system, programmable chip configuration, integration with other functional modules and power supply. The hardware implementation is here described and the used software for BER (bit-error-rate) testing of the multi-gigabit optical link. The measurement results are presented. The appendix contains a comparison between the available protocols of serial data transmission for FPGA technology. This TESLA Technology Report is a partial contribution to the next version of the SIMCON system which is expected to be released this year. The SIMCON, ver 3. will contain 8 channels and multi-gigabit optical transmission capability. (orig.)

The Chip-Scale Atomic Clock - Low-Power Physics Package

Science.gov (United States)

2004-12-01

36th Annual Precise Time and Time Interval (PTTI) Meeting 339 THE CHIP-SCALE ATOMIC CLOCK – LOW-POWER PHYSICS PACKAGE R. Lutwak ...pdf/documents/ds-x72.pdf [2] R. Lutwak , D. Emmons, W. Riley, and R. M. Garvey, 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs...2002, Reston, Virginia, USA (U.S. Naval Observatory, Washington, D.C.), pp. 539-550. [3] R. Lutwak , D. Emmons, T. English, and W. Riley, 2004

Electric Power Self-Supply Module for WSN Sensor Node Based on MEMS Vibration Energy Harvester

Directory of Open Access Journals (Sweden)

Wenyang Zhang

2018-04-01

Full Text Available This paper proposes an electric power self-supply module for the wireless sensor network (WSN sensor node. The module includes an electromagnetic vibration energy harvester based on micro-electro-mechanical system (MEMS technology and a processing circuit. The vibration energy harvester presented in this paper is fabricated by an integrated microfabrication process and consists of four similar and relatively independent beam vibration elements. The main functions of the processing circuit are to convert the output of the harvester from unstable alternating current (AC to stable direct current (DC, charge the super capacitor, and ensure the stable output of the super capacitor. The preliminary test results of the harvester chip show that the chip can output discontinuous pulse voltage, and the range of the voltage value is from tens to hundreds of millivolts in the vibration frequency range of 10–90 Hz. The maximum value that can be reached is 563 mV (at the vibration frequency of 18 Hz. The results of the test show that the harvester can output a relatively high voltage, which can meet the general electric power demand of a WSN sensor node.

Power-Energy Simulation for Multi-Core Processors in Bench-marking

Directory of Open Access Journals (Sweden)

Mona A. Abou-Of

2017-01-01

Full Text Available At Microarchitectural level, multi-core processor, as a complex System on Chip, has sophisticated on-chip components including cores, shared caches, interconnects and system controllers such as memory and ethernet controllers. At technological level, architects should consider the device types forecast in the International Technology Roadmap for Semiconductors (ITRS. Energy simulation enables architects to study two important metrics simultaneously. Timing is a key element of the CPU performance that imposes constraints on the CPU target clock frequency. Power and the resulting heat impose more severe design constraints, such as core clustering, while semiconductor industry is providing more transistors in the die area in pace with Moore’s law. Energy simulators provide a solution for such serious challenge. Energy is modelled either by combining performance benchmarking tool with a power simulator or by an integrated framework of both performance simulator and power profiling system. This article presents and asses trade-offs between different architectures using four cores battery-powered mobile systems by running a custom-made and a standard benchmark tools. The experimental results assure the Energy/ Frequency convexity rule over a range of frequency settings on different number of enabled cores. The reported results show that increasing the number of cores has a great effect on increasing the power consumption. However, a minimum energy dissipation will occur at a lower frequency which reduces the power consumption. Despite that, increasing the number of cores will also increase the effective cores value which will reflect a better processor performance.

Automatic extraction and processing of small RNAs on a multi-well/multi-channel (M&M) chip.

Science.gov (United States)

Zhong, Runtao; Flack, Kenneth; Zhong, Wenwan

2012-12-07

The study of the regulatory roles in small RNAs can be accelerated by techniques that permit simple, low-cost, and rapid extraction of small RNAs from a small number of cells. In order to ensure highly specific and sensitive detection, the extracted RNAs should be free of the background nucleic acids and present stably in a small volume. To meet these criteria, we designed a multi-well/multi-channel (M&M) chip to carry out automatic and selective isolation of small RNAs via solid-phase extraction (SPE), followed by reverse-transcription (RT) to convert them to the more stable cDNAs in a final volume of 2 μL. Droplets containing buffers for RNA binding, washing, and elution were trapped in microwells, which were connected by one channel, and suspended in mineral oil. The silica magnetic particles (SMPs) for SPE were moved along the channel from well to well, i.e. in between droplets, by a fixed magnet and a translation stage, allowing the nucleic acid fragments to bind to the SMPs, be washed, and then be eluted for RT reaction within 15 minutes. RNAs shorter than 63 nt were selectively enriched from cell lysates, with recovery comparable to that of a commercial kit. Physical separation of the droplets on our M&M chip allowed the usage of multiple channels for parallel processing of multiple samples. It also permitted smooth integration with on-chip RT-PCR, which simultaneously detected the target microRNA, mir-191, expressed in fewer than 10 cancer cells. Our results have demonstrated that the M&M chip device is a valuable and cost-saving platform for studying small RNA expression patterns in a limited number of cells with reasonable sample throughput.

Collective Memory Transfers for Multi-Core Chips

Energy Technology Data Exchange (ETDEWEB)

Michelogiannakis, George; Williams, Alexander; Shalf, John

2013-11-13

Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled layout for on-chip L1 data caches and scratchpads. How- ever, DRAM performance suffers under the non-streaming access patterns generated by many independent cores. We propose collective memory scheduling (CMS) that actively takes control of collective memory transfers such that requests arrive in a sequential and predictable fashion to the memory controller. CMS uses the hierarchically tiled arrays formal- ism to compactly express collective operations, which greatly improves programmability over conventional prefetch or list- DMA approaches. CMS reduces application execution time by up to 32% and DRAM read power by 2.2×, compared to a baseline DMA architecture such as STI Cell.

Performance comparison of binary modulation schemes for visible light communication

KAUST Repository

Park, Kihong

2015-09-11

In this paper, we investigate the power spectral density of several binary modulation schemes including variable on-off keying, variable pulse position modulation, and pulse dual slope modulation which were previously proposed for visible light communication with dimming control. We also propose a novel slope-based modulation called differential chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input bit sequence. We show that the DCSM scheme can exploit spectrum density more efficiently than the reference schemes while providing an error rate performance comparable to them. © 2015 IEEE.

A multi-modal stereo microscope based on a spatial light modulator.

Science.gov (United States)

Lee, M P; Gibson, G M; Bowman, R; Bernet, S; Ritsch-Marte, M; Phillips, D B; Padgett, M J

2013-07-15

Spatial Light Modulators (SLMs) can emulate the classic microscopy techniques, including differential interference (DIC) contrast and (spiral) phase contrast. Their programmability entails the benefit of flexibility or the option to multiplex images, for single-shot quantitative imaging or for simultaneous multi-plane imaging (depth-of-field multiplexing). We report the development of a microscope sharing many of the previously demonstrated capabilities, within a holographic implementation of a stereo microscope. Furthermore, we use the SLM to combine stereo microscopy with a refocusing filter and with a darkfield filter. The instrument is built around a custom inverted microscope and equipped with an SLM which gives various imaging modes laterally displaced on the same camera chip. In addition, there is a wide angle camera for visualisation of a larger region of the sample.

Dry-film polymer waveguide for silicon photonics chip packaging.

Science.gov (United States)

Hsu, Hsiang-Han; Nakagawa, Shigeru

2014-09-22

Polymer waveguide made by dry film process is demonstrated for silicon photonics chip packaging. With 8 μm × 11.5 μm core waveguide, little penalty is observed up to 25 Gbps before or after the light propagate through a 10-km long single-mode fiber (SMF). Coupling loss to SMF is 0.24 dB and 1.31 dB at the polymer waveguide input and output ends, respectively. Alignment tolerance for 0.5 dB loss increase is +/- 1.0 μm along both vertical and horizontal directions for the coupling from the polymer waveguide to SMF. The dry-film polymer waveguide demonstrates promising performance for silicon photonics chip packaging used in next generation optical multi-chip module.

Power module assembly

Science.gov (United States)

Campbell, Jeremy B [Torrance, CA; Newson, Steve [Redondo Beach, CA

2011-11-15

A power module assembly of the type suitable for deployment in a vehicular power inverter, wherein the power inverter has a grounded chassis, is provided. The power module assembly comprises a conductive base layer electrically coupled to the chassis, an insulating layer disposed on the conductive base layer, a first conductive node disposed on the insulating layer, a second conductive node disposed on the insulating layer, wherein the first and second conductive nodes are electrically isolated from each other. The power module assembly also comprises a first capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the first conductive node, and further comprises a second capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the second conductive node.

A Low-Power and Low-Voltage Power Management Strategy for On-Chip Micro Solar Cells

Directory of Open Access Journals (Sweden)

Ismail Cevik

2015-01-01

Full Text Available Fundamental characteristics of on-chip micro solar cell (MSC structures were investigated in this study. Several MSC structures using different layers in three different CMOS processes were designed and fabricated. Effects of PN junction structure and process technology on solar cell performance were measured. Parameters for low-power and low-voltage implementation of power management strategy and boost converter based circuits utilizing fractional voltage maximum power point tracking (FVMPPT algorithm were determined. The FVMPPT algorithm works based on the fraction between the maximum power point operation voltage and the open circuit voltage of the solar cell structure. This ratio is typically between 0.72 and 0.78 for commercially available poly crystalline silicon solar cells that produce several watts of power under typical daylight illumination. Measurements showed that the fractional voltage ratio is much higher and fairly constant between 0.82 and 0.85 for on-chip mono crystalline silicon micro solar cell structures that produce micro watts of power. Mono crystalline silicon solar cell structures were observed to result in better power fill factor (PFF that is higher than 74% indicating a higher energy harvesting efficiency.

Variation Tolerant On-Chip Interconnects

CERN Document Server

Nigussie, Ethiopia Enideg

2012-01-01

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

Simulation research of acousto optic modulator drive based on Multisim

Science.gov (United States)

Wang, Shiqian; Guo, Yangkuan; Zhu, Lianqing; Na, Yunxiao; Zhang, Yinmin; Liu, Qianzhe

2013-10-01

The acousto optic modulator drive is mainly made with 2 amplitude shift keying (2ASK)circuit, pre-amplifier circuit and power operational amplifier circuit, and the simulation of the acousto optic modulator drive is realized. Firstly, the acousto optic modulator drive works as follows.The modulation function is realized by the analoged switch circuit, and the on-off of the analoged switch chip (CD4066) are controlled by the pulse signal generated by the electronic conversion circuit. The voltage amplification of the modulated signal is achieved by two reverse proportional operation implements voltage amplifier circuit, and the circuit is mainly made with the AD8001 chip. Then the amplified signal is transfered into a two-stage power operational amplifier circuit of class C which is mainly made with the chip of MRF158. Secondly, both of the simulating structures and the union debugging based on the designed system are realized by Multisim. Finally, obtaining the modulation signal of 150(MHz) frequency and 5(μs) pulse width illustrates that a 2ASk modulation of the 150 (MHz)carrier signal and the 20(kHz) modulation signal is achieved. Besides, as the frequency of input signal and amplitude of voltage change, the output power of the power operational amplifier circuit also changes, and the conclusion is drawn that the output power increases when the frequency of input signal decreases and the amplitude of voltage increases. The component selection of the drive's PCB design, the performance parameter and of the actual circuit and the debugging of the actual circuit are based on the simulation results.

Power-Efficient Design Challenges

Science.gov (United States)

Pangrle, Barry

Design teams find themselves facing decreasing power budgets while simultaneously the products that they design continue to require the integration of increasingly complex levels of functionality. The market place (driven by consumer preferences) and new regulations and guidelines on energy efficiency and environmental impact are the key drivers. This in turn has generated new approaches in all IC and electronic system design domains from the architecture to the physical layout of ICs, to design-for-test, as well as for design verification to insure that the design implementation actually meets the intended requirements and specifications. This chapter covers key aspects of these forces from a technological and market perspective that are driving designers to produce more energy-efficient products. Observations by significant industry leaders from AMD, ARM, IBM, Intel, nVidia and TSMC are cited, and the emerging techniques and technologies used to address these issues now and into the future are explored. Topic areas include: System level: Architectural analysis and transaction-level modeling. How architectural decisions can dramatically reduce the design power and the importance of modeling hardware and software together. IC (Chip) level: The impact of creating on-chip power domains for selectively turning power off and/or multi-voltage operation on: (1) chip verification, (2) multi-corner multi-mode analysis during placement and routing of logic cells and (3) changes to design-for-test, all in order to accommodate for power-gating and multi-voltage control logic, retention registers, isolation cells and level shifters needed to implement these power saving techniques. Process level: The disappearing impact of body-bias techniques on leakage control and why new approaches like High-K Metal Gate (HKMG) technology help but don't eliminate power issues. Power-efficient design is impacting the way chip designers work today, and this chapter focuses on where the most

Low modulation index RF signal detection for a passive UHF RFID transponder

International Nuclear Information System (INIS)

Liu Zhongqi; Zhang Chun; Li Yongming; Wang Zhihua

2009-01-01

In a typical RFID system the reader transmits modulated RF power to provide both data and energy for the passive transponder. Low modulation index RF energy is preferable for an adequate tag power supply and increase in communication range but gives rise to difficulties for near-field conventional demodulation. Therefore, a novel ASK demodulator for minimum 20% modulation index RF signal detection over a range of 23 dB is presented. Thanks to the proposed innovative divisional linear conversion from the power into voltage signal, the detection sensitivity is ensured over a wide power range with low power consumption of 8.6 μW. The chip is implemented in UMC 0.18 μm mix-mode CMOS technology, and the chip area is 0.06 mm 2 .

Cost-effective, compact and high-speed integrable multi-mode interference modulator

NARCIS (Netherlands)

Lenstra, Daan; Yao, Weiming; Cardarelli, Simone; Mink, Jan

2017-01-01

Theoretical analysis of the modulation performance of this wave-guide device shows great potential when combined with a single-mode laser on a monolithic optical chip. On the basis of the reversed-bias electro-optic effect, modulation speeds surmounting 25 Gbit/s with 10 dB extinction ratio are

Power penalties for multi-level PAM modulation formats at arbitrary bit error rates

Science.gov (United States)

Kaliteevskiy, Nikolay A.; Wood, William A.; Downie, John D.; Hurley, Jason; Sterlingov, Petr

2016-03-01

There is considerable interest in combining multi-level pulsed amplitude modulation formats (PAM-L) and forward error correction (FEC) in next-generation, short-range optical communications links for increased capacity. In this paper we derive new formulas for the optical power penalties due to modulation format complexity relative to PAM-2 and due to inter-symbol interference (ISI). We show that these penalties depend on the required system bit-error rate (BER) and that the conventional formulas overestimate link penalties. Our corrections to the standard formulas are very small at conventional BER levels (typically 1×10-12) but become significant at the higher BER levels enabled by FEC technology, especially for signal distortions due to ISI. The standard formula for format complexity, P = 10log(L-1), is shown to overestimate the actual penalty for PAM-4 and PAM-8 by approximately 0.1 and 0.25 dB respectively at 1×10-3 BER. Then we extend the well-known PAM-2 ISI penalty estimation formula from the IEEE 802.3 standard 10G link modeling spreadsheet to the large BER case and generalize it for arbitrary PAM-L formats. To demonstrate and verify the BER dependence of the ISI penalty, a set of PAM-2 experiments and Monte-Carlo modeling simulations are reported. The experimental results and simulations confirm that the conventional formulas can significantly overestimate ISI penalties at relatively high BER levels. In the experiments, overestimates up to 2 dB are observed at 1×10-3 BER.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems.

Science.gov (United States)

Indiveri, Giacomo

2008-09-03

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2008-09-01

Full Text Available Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

Directory of Open Access Journals (Sweden)

M. Jamal Deen

2013-08-01

Full Text Available Ultra-low power radio frequency (RF transceivers used in short-range application such as wireless sensor networks (WSNs require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs in addition to a 2.0 GHz phase-locked loop (PLL based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of −122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of −120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3; Charakterisierung von bildgebenden Pixeldetektoren aus Si und CdTe ausgelesen mit dem zaehlenden Roentgenchip MPEC 2.3

Energy Technology Data Exchange (ETDEWEB)

Loecker, M.

2007-04-15

Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 {mu}m{sup 2} pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e{sup -}). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed.

Solid state isotopic power source for computer chips

International Nuclear Information System (INIS)

Brown, P.M.

1992-01-01

This paper reports that recent developments in materials technology now make it possible to fabricate nonthermal thin-film isotopic energy converters (REC) with a specific power of 24 W/kg and 5 to 10 year working life at 5 to 10 Watts. This creates applications never before possible, such as placing the power supply directly on integrated circuit chips. The efficiency of the REC is about 25% which is two to three times greater than the 6 to 8% capabilities of current thermoelectric systems

Photovoltaic Array Space Power flight experiment plus diagnostics (PASP+) modules

International Nuclear Information System (INIS)

Cooley, W.T.; Adams, S.F.; Reinhardt, K.C.; Piszczor, M.F.

1992-01-01

The Photovoltaic Array Space Power Plus Diagnostics flight experiment (PASP+) subsumes twelve solar array modules which represent the state of the art in the space photovoltaic array industry. Each of the twelve modules individually feature specific photovoltaic technologies such as advanced semiconductor materials, multi-bandgap structures, lightweight array designs, advanced interconnect technologies, or concentrator array designs. This paper will describe each module in detail including the configuration, components, materials, anticipated on orbit performance, and some of the aspects of each array technology. The layout of each module and the photovoltaic cell or array cross section will be presented graphically. A discussion on the environmental constraints and materials selection will be included as well as a delineation of the differences between the modules and the baseline array configuration in its intended application

Low modulation index RF signal detection for a passive UHF RFID transponder

Energy Technology Data Exchange (ETDEWEB)

Liu Zhongqi [Department of Electronic Engineering, Tsinghua University, Beijing 100084 (China); Zhang Chun; Li Yongming; Wang Zhihua, E-mail: liu-zq04@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

2009-09-15

In a typical RFID system the reader transmits modulated RF power to provide both data and energy for the passive transponder. Low modulation index RF energy is preferable for an adequate tag power supply and increase in communication range but gives rise to difficulties for near-field conventional demodulation. Therefore, a novel ASK demodulator for minimum 20% modulation index RF signal detection over a range of 23 dB is presented. Thanks to the proposed innovative divisional linear conversion from the power into voltage signal, the detection sensitivity is ensured over a wide power range with low power consumption of 8.6 {mu}W. The chip is implemented in UMC 0.18 {mu}m mix-mode CMOS technology, and the chip area is 0.06 mm{sup 2}.

Multi-LED parallel transmission for long distance underwater VLC system with one SPAD receiver

Science.gov (United States)

Wang, Chao; Yu, Hong-Yi; Zhu, Yi-Jun; Wang, Tao; Ji, Ya-Wei

2018-03-01

In this paper, a multiple light emitting diode (LED) chips parallel transmission (Multi-LED-PT) scheme for underwater visible light communication system with one photon-counting single photon avalanche diode (SPAD) receiver is proposed. As the lamp always consists of multi-LED chips, the data rate could be improved when we drive these multi-LED chips parallel by using the interleaver-division-multiplexing technique. For each chip, the on-off-keying modulation is used to reduce the influence of clipping. Then a serial successive interference cancellation detection algorithm based on ideal Poisson photon-counting channel by the SPAD is proposed. Finally, compared to the SPAD-based direct current-biased optical orthogonal frequency division multiplexing system, the proposed Multi-LED-PT system could improve the error-rate performance and anti-nonlinearity performance significantly under the effects of absorption, scattering and weak turbulence-induced channel fading together.

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

Science.gov (United States)

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Fabricating and Characterizing the Microfluidic Solid Phase Extraction Module Coupling with Integrated ESI Emitters

Directory of Open Access Journals (Sweden)

Hangbin Tang

2018-05-01

Full Text Available Microfluidic chips coupling with mass spectrometry (MS will be of great significance to the development of relevant instruments involving chemical and bio-chemical analysis, drug detection, food and environmental applications and so on. In our previous works, we proposed two types of microfluidic electrospray ionization (ESI chip coupling with MS: the two-phase flow focusing (FF ESI microfluidic chip and the corner-integrated ESI emitter, respectively. However the pretreatment module integrated with these ESI emitters is still a challenging problem. In this paper, we concentrated on integrating the solid phase micro-extraction (SPME module with our previous proposed on-chip ESI emitters; the fabrication processes of such SPME module are fully compatible with our previous proposed ESI emitters based on the multi-layer soft lithography. We optimized the structure of the integrated chip and characterized its performance using standard samples. Furthermore, we verified its abilities of salt removal, extraction of multiple analytes and separation through on-chip elution using mimic biological urine spiked with different drugs. The results indicated that our proposed integrated module with ESI emitters is practical and effective for real biological sample pretreatment and MS detection.

Design and characterization of a 200 V, 45 A all-GaN HEMT-based power module

International Nuclear Information System (INIS)

Chou, Po-Chien; Cheng, Stone

2013-01-01

Emerging gallium nitride (GaN)-based high electron mobility transistor (HEMT) technology has the potential to make lower loss and higher power switching characteristics than those made using traditional silicon (Si) components. This work designed, developed, and tested an all-GaN-based power module. In a 200 V, 45 A module, each switching element comprises three GaN chips in parallel, each of which includes six 2.1 A AlGaN/GaN-on-Si HEMT cells. The cells are wire-bonded in parallel to scale up the power rating. Static I D -V DS characteristics of the module are experimentally obtained over widely varying base plate temperatures, and a low on-state resistance is obtained at an elevated temperature of 125 °C. The fabricated module has a blocking voltage exceeding 200 V at a reverse-leakage current density below 1 mA/mm. Two standard temperature measurements are made to provide a simple means of determining mean cell temperature in the module. Self-heating in AlGaN/GaN HEMTs is studied by electrical analysis and infrared thermography. Electrical analysis provides fast temperature overviews while infrared thermography reveals temperature behavior in selected active regions. The current distribution among cells was acceptable over the measured operating temperature range. The characterization of electrical performance and mechanical performance confirm the potential use of the packaged module for high-power applications. -- Highlights: • This work proposes the design, development, and testing of all-GaN power module. • We develop module package and determine their thermal and electrical properties. • ID-VDS characteristics are obtained over a wide range of base plate temperatures. • Self-heating in GaN HEMTs is studied by electrical analysis and IR thermography

Development of control system for multi-converter High voltage Power supply using programmable SoC

Science.gov (United States)

Dave, Rasesh; Dharangutti, Jagruti; Singh, N. P.; Thakar, Aruna; Dhola, Hitesh; Gajjar, Sandip; Parmar, Darshan; Zaveri, Tanish; Baruah, Ujjwal

2017-04-01

Multi-converter based High Voltage Power Supplies (HVPSs) find application in multi-megawatt accelerators, RF systems. Control system for HVPS must be a combination of superior parallel processing, real time performance, fast computation and versatile connectivity. The hardware platform is expected to be robust, easily scalable for future developments with minimal overheads. This paper describes development of control system on Zynq All Programmable SoC (System on Chip) for HVPS. Typical HVPS control mechanism involves communication, generation of precise control signals/pulses for few hundred numbers of chopper and closed loop control in microsecond range for regulated output. Such kind of requirements can be met with Zynq All Programmable SoC, which is a combination of Dual core ARM Cortex A-9 Processing System (PS) and Xilinx 7 series FPGA based Programmable Logic (PL). Deterministic functions of power supply control system such as generation of control signals with precise inter-channel delay of nanosecond range and communication with individual chopper at 100kbps can be implemented on PL. PS should implement corrective tasks based on field feedback received from individual chopper, user interface and OS management that allows to take full advantage of system capabilities. PS and PL are connected with on-chip AXI-4 interface with low latency and higher bandwidth through 9 AXI ports. Typically PS boots first, this ensures secure booting and prevents external environment from tampering PL.

Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

International Nuclear Information System (INIS)

Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

2012-01-01

A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

A System-on-Chip Solution for Point-of-Care Ultrasound Imaging Systems: Architecture and ASIC Implementation.

Science.gov (United States)

Kang, Jeeun; Yoon, Changhan; Lee, Jaejin; Kye, Sang-Bum; Lee, Yongbae; Chang, Jin Ho; Kim, Gi-Duck; Yoo, Yangmo; Song, Tai-kyong

2016-04-01

In this paper, we present a novel system-on-chip (SOC) solution for a portable ultrasound imaging system (PUS) for point-of-care applications. The PUS-SOC includes all of the signal processing modules (i.e., the transmit and dynamic receive beamformer modules, mid- and back-end processors, and color Doppler processors) as well as an efficient architecture for hardware-based imaging methods (e.g., dynamic delay calculation, multi-beamforming, and coded excitation and compression). The PUS-SOC was fabricated using a UMC 130-nm NAND process and has 16.8 GFLOPS of computing power with a total equivalent gate count of 12.1 million, which is comparable to a Pentium-4 CPU. The size and power consumption of the PUS-SOC are 27×27 mm(2) and 1.2 W, respectively. Based on the PUS-SOC, a prototype hand-held US imaging system was implemented. Phantom experiments demonstrated that the PUS-SOC can provide appropriate image quality for point-of-care applications with a compact PDA size ( 200×120×45 mm(3)) and 3 hours of battery life.

Scalable multi-segment phase mask for spatial power splitting and mode division demultiplexing

NARCIS (Netherlands)

Chen, H.; Koonen, A.M.J.

2013-01-01

Multi-segment Phase Mask (MSPM) designs for spatial power splitting and mode division demultiplexing are verified through simulation and experiments. Coupler insertion loss and mode dependent loss are calculated. A spatial light modulator is used to emulate the proposed MSPMs.

In-Situ Measurement of Power Loss for Crystalline Silicon Modules Undergoing Thermal Cycling and Mechanical Loading Stress Testing

DEFF Research Database (Denmark)

Spataru, Sergiu; Hacke, Peter; Sera, Dezso

We analyze the degradation of multi-crystalline silicon photovoltaic modules undergoing simultaneous thermal, mechanical, and humidity-freeze stress testing to develop a dark environmental chamber in-situ measurement procedure for determining module power loss. We analyze dark I-V curves measured...

Selective Attention in Multi-Chip Address-Event Systems

Directory of Open Access Journals (Sweden)

Giacomo Indiveri

2009-06-01

Full Text Available Selective attention is the strategy used by biological systems to cope with the inherent limits in their available computational resources, in order to efficiently process sensory information. The same strategy can be used in artificial systems that have to process vast amounts of sensory data with limited resources. In this paper we present a neuromorphic VLSI device, the “Selective Attention Chip” (SAC, which can be used to implement these models in multi-chip address-event systems. We also describe a real-time sensory-motor system, which integrates the SAC with a dynamic vision sensor and a robotic actuator. We present experimental results from each component in the system, and demonstrate how the complete system implements a real-time stimulus-driven selective attention model.

Development of a Multi-Channel Ultrasonic Testing System for Automated Ultrasonic Pipe Inspection of Nuclear Power Plant

International Nuclear Information System (INIS)

Lee, Hee Jong; Cho, Chan Hee; Cho, Hyun Joon

2009-01-01

Currently almost all in-service-inspection techniques, applied in domestic nuclear power plants, are partial to field inspection technique. These kinds of techniques are related to managing nuclear power plants by the operation of foreign-produced inspection devices. There have been so many needs for development of native in-service-inspection device because there is no native diagnosis device for nuclear power plant inspection yet in Korea. In this research, we developed several core techniques to make an automated ultrasonic pipe inspection system for nuclear power plants. A high performance multi-channel ultrasonic pulser/receiver module, an A/D converter module and a digital main CPU module were developed and the performance of the developed modules was verified. The S/N ratio, noise level and signal acquisition performance of the developed modules showed proper level as we designed in the beginning.

OM4 bend insensitive multi-mode fibers’ usefulness for MCM integration

International Nuclear Information System (INIS)

Guzowski, Bartłomiej; Lisik, Zbigniew; Tosik, Grzegorz; Ciupa, Emilia

2012-01-01

Highlights: ► The influence of high temperature exposure on OM4 fibers’ mechanical properties. ► Researching OM4 class fibers for use in innovative Optical Multi Chip Module. ► The influence of bending at a very small radius, up to 2 mm, on MM fibers. - Abstract: For future generations of electronic systems, a severe bottleneck is expected on the interconnection level and the use of optical interconnection is considered as one of the most promising solutions in this matter. Recent progress in fiber development resulted in new generation of optical fibers that are bend insensitive. This makes them ideal for Multi Chip Module (MCM) application. This paper focuses on OM4 bend insensitive multi-mode fibers’ usefulness for MCM integration, particularly the investigation of MM fiber loss is presented, which is influenced by bend diameter and the fiber's mechanical performance under influence of high temperature (400 °C–1000 °C adequate to MCM production process).

Au–Sn bonding material for the assembly of power integrated circuit module

Energy Technology Data Exchange (ETDEWEB)

Zhu, Z.X.; Li, C.C. [Department of Materials Science & Engineering, National Taiwan University, Taipei, Taiwan (China); Liao, L.L.; Liu, C.K. [Electronic and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan (China); Kao, C.R., E-mail: crkao@ntu.edu.tw [Department of Materials Science & Engineering, National Taiwan University, Taipei, Taiwan (China)

2016-06-25

Insulated gate bipolar transistor (IGBT) chips are the key components in high-temperature power electronic modules, which have to efficiently convert electricity between direct and alternating current. In this study, the eutectic Au–Sn (20 wt.% Sn) is successfully used to assemble IGBT chips and direct-bond-copper substrates by using solid liquid interdiffusion (SLID) bonding. During subsequent isothermal aging at 150, 200, and 240 °C, the microstructure evolution and growth kinetics of intermetallic compounds are investigated. Excellent thermal stability and mechanical strength are observed. It is concluded that the eutectic Au–Sn solder is ideal to assemble high-temperature IGBT by using the SLID process. - Highlights: • Au–20Sn serves as a promising bonding material for IGBT operating at T < 519 °C. • The Au–20Sn reacted with Ni to form (Ni,Au){sub 3}Sn{sub 2}/(Au{sub 5}Sn + AuSn)/(Ni,Au){sub 3}Sn{sub 2}. • Once the AuSn was nearly exhausted, the whole joint could withstand higher temperatures. • A cost-effective way for long-term operations at high temperature.

Scaling vectors of attoJoule per bit modulators

Science.gov (United States)

Sorger, Volker J.; Amin, Rubab; Khurgin, Jacob B.; Ma, Zhizhen; Dalir, Hamed; Khan, Sikandar

2018-01-01

Electro-optic modulation performs the conversion between the electrical and optical domain with applications in data communication for optical interconnects, but also for novel optical computing algorithms such as providing nonlinearity at the output stage of optical perceptrons in neuromorphic analog optical computing. While resembling an optical transistor, the weak light-matter-interaction makes modulators 105 times larger compared to their electronic counterparts. Since the clock frequency for photonics on-chip has a power-overhead sweet-spot around tens of GHz, ultrafast modulation may only be required in long-distance communication, not for short on-chip links. Hence, the search is open for power-efficient on-chip modulators beyond the solutions offered by foundries to date. Here, we show scaling vectors towards atto-Joule per bit efficient modulators on-chip as well as some experimental demonstrations of novel plasmonic modulators with sub-fJ/bit efficiencies. Our parametric study of placing different actively modulated materials into plasmonic versus photonic optical modes shows that 2D materials overcompensate their miniscule modal overlap by their unity-high index change. Furthermore, we reveal that the metal used in plasmonic-based modulators not only serves as an electrical contact, but also enables low electrical series resistances leading to near-ideal capacitors. We then discuss the first experimental demonstration of a photon-plasmon-hybrid graphene-based electro-absorption modulator on silicon. The device shows a sub-1 V steep switching enabled by near-ideal electrostatics delivering a high 0.05 dB V-1 μm-1 performance requiring only 110 aJ/bit. Improving on this demonstration, we discuss a plasmonic slot-based graphene modulator design, where the polarization of the plasmonic mode aligns with graphene’s in-plane dimension; where a push-pull dual-gating scheme enables 2 dB V-1 μm-1 efficient modulation allowing the device to be just 770 nm

Identifying EGFR-Expressed Cells and Detecting EGFR Multi-Mutations at Single-Cell Level by Microfluidic Chip

Science.gov (United States)

Li, Ren; Zhou, Mingxing; Li, Jine; Wang, Zihua; Zhang, Weikai; Yue, Chunyan; Ma, Yan; Peng, Hailin; Wei, Zewen; Hu, Zhiyuan

2018-03-01

EGFR mutations companion diagnostics have been proved to be crucial for the efficacy of tyrosine kinase inhibitor targeted cancer therapies. To uncover multiple mutations occurred in minority of EGFR-mutated cells, which may be covered by the noises from majority of un-mutated cells, is currently becoming an urgent clinical requirement. Here we present the validation of a microfluidic-chip-based method for detecting EGFR multi-mutations at single-cell level. By trapping and immunofluorescently imaging single cells in specifically designed silicon microwells, the EGFR-expressed cells were easily identified. By in situ lysing single cells, the cell lysates of EGFR-expressed cells were retrieved without cross-contamination. Benefited from excluding the noise from cells without EGFR expression, the simple and cost-effective Sanger's sequencing, but not the expensive deep sequencing of the whole cell population, was used to discover multi-mutations. We verified the new method with precisely discovering three most important EGFR drug-related mutations from a sample in which EGFR-mutated cells only account for a small percentage of whole cell population. The microfluidic chip is capable of discovering not only the existence of specific EGFR multi-mutations, but also other valuable single-cell-level information: on which specific cells the mutations occurred, or whether different mutations coexist on the same cells. This microfluidic chip constitutes a promising method to promote simple and cost-effective Sanger's sequencing to be a routine test before performing targeted cancer therapy.[Figure not available: see fulltext.

On-Chip Laser-Power Delivery System for Dielectric Laser Accelerators

Science.gov (United States)

Hughes, Tyler W.; Tan, Si; Zhao, Zhexin; Sapra, Neil V.; Leedle, Kenneth J.; Deng, Huiyang; Miao, Yu; Black, Dylan S.; Solgaard, Olav; Harris, James S.; Vuckovic, Jelena; Byer, Robert L.; Fan, Shanhui; England, R. Joel; Lee, Yun Jo; Qi, Minghao

2018-05-01

We propose an on-chip optical-power delivery system for dielectric laser accelerators based on a fractal "tree-network" dielectric waveguide geometry. This system replaces experimentally demanding free-space manipulations of the driving laser beam with chip-integrated techniques based on precise nanofabrication, enabling access to orders-of-magnitude increases in the interaction length and total energy gain for these miniature accelerators. Based on computational modeling, in the relativistic regime, our laser delivery system is estimated to provide 21 keV of energy gain over an acceleration length of 192 μ m with a single laser input, corresponding to a 108-MV/m acceleration gradient. The system may achieve 1 MeV of energy gain over a distance of less than 1 cm by sequentially illuminating 49 identical structures. These findings are verified by detailed numerical simulation and modeling of the subcomponents, and we provide a discussion of the main constraints, challenges, and relevant parameters with regard to on-chip laser coupling for dielectric laser accelerators.

Digital Power Consumption Estimations for CHIPIX65 Pixel Readout Chip

CERN Document Server

Marcotulli, Andrea

2016-01-01

New hybrid pixel detectors with improved resolution capable of dealing with hit rates up to 3 GHz/cm2 will be required for future High Energy Physics experiments in the Large Hadron Collider (LHC) at CERN. Given this, the RD53 collaboration works on the design of the next generation pixel readout chip needed for both the ATLAS and CMS detector phase 2 pixel upgrades. For the RD53 demonstrator chip in 65nm CMOS technology, different architectures are considered. In particular the purpose of this work is estimating the power consumption of the digital architecture of the readout ASIC developed by CHIPIX65 project of the INFN National Scientific Committee. This has been done with modern chip design tools integrated with the VEPIX53 simulation framework that has been developed within the RD53 collaboration in order to assess the performance of the system in very high rate, high energy physics experiments.

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

Science.gov (United States)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

Online Chip Temperature Monitoring Using υce-Load Current and IR Thermography

DEFF Research Database (Denmark)

Ghimire, Pramod; Pedersen, Kristian Bonderup; Trintis, Ionut

2015-01-01

This paper presents on-state collector-emitter voltage (υce, on)-load current (Ic) method to monitor chip temperature on power insulated gate bipolar transistor (IGBT) modules in converter operation. The measurement method is also evaluated using infrared (IR) thermography. Temperature dependencies...

Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

Energy Technology Data Exchange (ETDEWEB)

Harb, Ali, E-mail: ali.harb@desy.de; Mussgiller, Andreas; Hauk, Johannes

2017-02-11

The CMS Binary Chip (CBC) is a prototype version of the front-end read-out ASIC to be used in the silicon strip modules of the CMS outer tracking detector during the high luminosity phase of the LHC. The CBC is produced in 130 nm CMOS technology and bump-bonded to the hybrid of a double layer silicon strip module, the so-called 2S-p{sub T} module. It has 254 input channels and is designed to provide on-board trigger information to the first level trigger system of CMS, with the capability of cluster-width discrimination and high-p{sub T} track identification. In November 2013 the first 2S-p{sub T} module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2 to 4 GeV. In this paper the test setup and the results are presented.

Multi-equilibrium property of metabolic networks: SSI module

Directory of Open Access Journals (Sweden)

Chen Luonan

2011-06-01

Full Text Available Abstract Background Revealing the multi-equilibrium property of a metabolic network is a fundamental and important topic in systems biology. Due to the complexity of the metabolic network, it is generally a difficult task to study the problem as a whole from both analytical and numerical viewpoint. On the other hand, the structure-oriented modularization idea is a good choice to overcome such a difficulty, i.e. decomposing the network into several basic building blocks and then studying the whole network through investigating the dynamical characteristics of the basic building blocks and their interactions. Single substrate and single product with inhibition (SSI metabolic module is one type of the basic building blocks of metabolic networks, and its multi-equilibrium property has important influence on that of the whole metabolic networks. Results In this paper, we describe what the SSI metabolic module is, characterize the rates of the metabolic reactions by Hill kinetics and give a unified model for SSI modules by using a set of nonlinear ordinary differential equations with multi-variables. Specifically, a sufficient and necessary condition is first given to describe the injectivity of a class of nonlinear systems, and then, the sufficient condition is used to study the multi-equilibrium property of SSI modules. As a main theoretical result, for the SSI modules in which each reaction has no more than one inhibitor, a sufficient condition is derived to rule out multiple equilibria, i.e. the Jacobian matrix of its rate function is nonsingular everywhere. Conclusions In summary, we describe SSI modules and give a general modeling framework based on Hill kinetics, and provide a sufficient condition for ruling out multiple equilibria of a key type of SSI module.

Modulating wind power plant output using different frequency modulation components for damping grid oscillations

DEFF Research Database (Denmark)

2017-01-01

A method, controller, wind power plant, and computer program product are disclosed for operating a wind power plant comprising a plurality of wind turbines, the wind power plant producing a plant power output. The method comprises receiving a modulation request signal indicating a requested...... modulation of the plant power output, the requested modulation specifying a modulation frequency. The method further comprises generating a respective power reference signal for each of at least two wind turbines of the plurality of wind turbines selected to fulfill the requested modulation, Each generated...... power reference signal includes a respective modulation component corresponding to a portion of the requested modulation and having a frequency different than the modulation frequency....

On decoding of multi-level MPSK modulation codes

Science.gov (United States)

Lin, Shu; Gupta, Alok Kumar

1990-01-01

The decoding problem of multi-level block modulation codes is investigated. The hardware design of soft-decision Viterbi decoder for some short length 8-PSK block modulation codes is presented. An effective way to reduce the hardware complexity of the decoder by reducing the branch metric and path metric, using a non-uniform floating-point to integer mapping scheme, is proposed and discussed. The simulation results of the design are presented. The multi-stage decoding (MSD) of multi-level modulation codes is also investigated. The cases of soft-decision and hard-decision MSD are considered and their performance are evaluated for several codes of different lengths and different minimum squared Euclidean distances. It is shown that the soft-decision MSD reduces the decoding complexity drastically and it is suboptimum. The hard-decision MSD further simplifies the decoding while still maintaining a reasonable coding gain over the uncoded system, if the component codes are chosen properly. Finally, some basic 3-level 8-PSK modulation codes using BCH codes as component codes are constructed and their coding gains are found for hard decision multistage decoding.

Development of a 64-channel 100 ps TDC module

International Nuclear Information System (INIS)

Liu Xiaohua; An Qi; Liu Shubin; Su Hong; Zhan Wenlong

2009-01-01

Multi-wire drift chamber at external target experiment in HIRFL-CSR measures drift time of charged particles to obtain the track information. A 64-channel TDC module hosting high density connectors and high performance TDC chips (HPTDC) are used to perform the time digitization. Data of the module is transferred to computer through PXI bus. The test results show that a 100 ps resolution has been achieved. (authors)

Powering embedded electronics for wind turbine monitoring using multi-source energy harvesting techniques

Science.gov (United States)

Anton, S. R.; Taylor, S. G.; Raby, E. Y.; Farinholt, K. M.

2013-03-01

With a global interest in the development of clean, renewable energy, wind energy has seen steady growth over the past several years. Advances in wind turbine technology bring larger, more complex turbines and wind farms. An important issue in the development of these complex systems is the ability to monitor the state of each turbine in an effort to improve the efficiency and power generation. Wireless sensor nodes can be used to interrogate the current state and health of wind turbine structures; however, a drawback of most current wireless sensor technology is their reliance on batteries for power. Energy harvesting solutions present the ability to create autonomous power sources for small, low-power electronics through the scavenging of ambient energy; however, most conventional energy harvesting systems employ a single mode of energy conversion, and thus are highly susceptible to variations in the ambient energy. In this work, a multi-source energy harvesting system is developed to power embedded electronics for wind turbine applications in which energy can be scavenged simultaneously from several ambient energy sources. Field testing is performed on a full-size, residential scale wind turbine where both vibration and solar energy harvesting systems are utilized to power wireless sensing systems. Two wireless sensors are investigated, including the wireless impedance device (WID) sensor node, developed at Los Alamos National Laboratory (LANL), and an ultra-low power RF system-on-chip board that is the basis for an embedded wireless accelerometer node currently under development at LANL. Results indicate the ability of the multi-source harvester to successfully power both sensors.

Power module assemblies with staggered coolant channels

Science.gov (United States)

Herron, Nicholas Hayden; Mann, Brooks S; Korich, Mark D

2013-07-16

A manifold is provided for supporting a power module assembly with a plurality of power modules. The manifold includes a first manifold section. The first face of the first manifold section is configured to receive the first power module, and the second face of the first manifold section defines a first cavity with a first baseplate thermally coupled to the first power module. The first face of the second manifold section is configured to receive the second power module, and the second face of the second manifold section defines a second cavity with a second baseplate thermally coupled to the second power module. The second face of the first manifold section and the second face of the second manifold section are coupled together such that the first cavity and the second cavity form a coolant channel. The first cavity is at least partially staggered with respect to second cavity.

Optimization of Reliability and Power Consumption in Systems on a Chip

OpenAIRE

Simunic, Tajana; Mihic, Kresimir; De Micheli, Giovanni

2005-01-01

Aggressive transistor scaling, decreased voltage margins and increased processor power and temperature, have made reliability assessment a much more significant issue in design. Although reliability of devices and interconnect has been broadly studied, here we characterize reliability at the system level. Thus we consider component-based System on Chip designs. Reliability is strongly affected by system temperature, which is in turn driven by power consumption. Thus, component reliability and...

Ultracompact on-chip photothermal power monitor based on silicon hybrid plasmonic waveguides

Directory of Open Access Journals (Sweden)

Wu Hao

2017-01-01

Full Text Available We propose and demonstrate an ultracompact on-chip photothermal power monitor based on a silicon hybrid plasmonic waveguide (HPWG, which consists of a metal strip, a silicon core, and a silicon oxide (SiO2 insulator layer between them. When light injected to an HPWG is absorbed by the metal strip, the temperature increases and the resistance of the metal strip changes accordingly due to the photothermal and thermal resistance effects of the metal. Therefore, the optical power variation can be monitored by measuring the resistance of the metal strip on the HPWG. To obtain the electrical signal for the resistance measurement conveniently, a Wheatstone bridge circuit is monolithically integrated with the HPWG on the same chip. As the HPWG has nanoscale light confinement, the present power monitor is as short as ~3 μm, which is the smallest photothermal power monitor reported until now. The compactness helps to improve the thermal efficiency and the response speed. For the present power monitor fabricated with simple fabrication processes, the measured responsivity is as high as about 17.7 mV/mW at a bias voltage of 2 V and the power dynamic range is as large as 35 dB.

arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

CERN Document Server

Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

2018-02-02

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

Triple Pulse Tester - Efficient Power Loss Characterization of Power Modules

DEFF Research Database (Denmark)

Trintis, Ionut; Poulsen, Thomas; Beczkowski, Szymon

2015-01-01

In this paper the triple pulse testing method and circuit for power loss characterization of power modules is introduced. The proposed test platform is able to accurately characterize both the switching and conduction losses of power modules in a single automated process. A configuration of a half...

Chips 2020

CERN Document Server

2016-01-01

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

First MCM-D modules for the b-physics layer of the ATLAS Pixel Detector

CERN Document Server

Basken, O; Ehrmann, O; Gerlach, P; Grah, C; Gregor, I M; Linder, C; Meuser, S; Richardson, J; Topper, M; Wolf, J

2000-01-01

The innermost layer (b-physics layer) of the ATLAS Pixel Detector will consist of modules based on MCM-D technology. Such a module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out ICs, each serving 24* 160 pixel unit cells, a module controller chip (MCC), an optical transceiver and the local signal interconnection and power distribution busses. We show a prototype of such a module with additional test pads on both sides. The outer dimensions of the final module will be 21.4 mm*67.8 mm. The extremely high wiring density, which is necessary to interconnect the read-out chips, was achieved using a thin film copper/photo-BCB process on the pixel array. The bumping of the read out chips was done using electroplating PbSn. All dice are then attached by flip-chip assembly to the sensor diodes and the local busses. The focus of this paper is the description of the first results of such MCM-D-type modules. (11 refs).

10Gb/s Ultra-Wideband Wireless Transmission Based on Multi-Band Carrierless Amplitude Phase Modulation

DEFF Research Database (Denmark)

Puerta Ramírez, Rafael; Rommel, Simon; Vegas Olmos, Juan José

2016-01-01

In this paper, for the first time, a record UWB transmission of 10Gb/s is experimentally demonstrated employing a multi-band approach of carrierless amplitude phase modulation (MultiCAP). The proposed solution complies with the restrictions on the effective radiated power established by both...... the United States Federal Communications Commission and the European Electronic Communications Committee, achieving a BER below the limit for a 7% overhead FEC of 3.8 · 10−3 up to respective wireless distances of 3.5m and 2m....

CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

Directory of Open Access Journals (Sweden)

Arun Ravindran

2012-02-01

Full Text Available Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs. While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9

Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

Science.gov (United States)

Zargham, Meysam; Gulak, P Glenn

2015-04-01

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Science.gov (United States)

Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

2005-06-01

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

Chip-carrier thermal barrier and its impact on lateral thermal lens profile and beam parameter product in high power broad area lasers

Science.gov (United States)

Rieprich, J.; Winterfeldt, M.; Kernke, R.; Tomm, J. W.; Crump, P.

2018-03-01

High power broad area diode lasers with high optical power density in a small focus spot are in strong commercial demand. For this purpose, the beam quality, quantified via the beam parameter product (BPP), has to be improved. Previous studies have shown that the BPP is strongly affected by current-induced heating and the associated thermal lens formed within the laser stripe. However, the chip structure and module-assembly related factors that regulate the size and the shape of the thermal lens are not well known. An experimental infrared thermographic technique is used to quantify the thermal lens profile in diode lasers operating at an emission wavelength of 910 nm, and the results are compared with finite element method simulations. The analysis indicates that the measured thermal profiles can best be explained when a thermal barrier is introduced between the chip and the carrier, which is shown to have a substantial impact on the BPP and the thermal resistance. Comparable results are observed in further measurements of samples from multiple vendors, and the barrier is only observed for junction-down (p-down) mounting, consistent with the barrier being associated with the GaAs-metal transition.

A MCM-D-type module for the ATLAS pixel detector

CERN Document Server

Becks, K H; Ehrmann, O; Gerlach, P; Gregor, I M; Pieters, P; Topper, M; Truzzi, C; Wolf, J

1999-01-01

For the ATLAS experiment at the planned Large Hadron Collider LHC at CERN hybrid pixel detectors are being built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the ATLAS pixel $9 detector. A module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out IC's, each serving 24*160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and $9 power distribution busses. The dies are attached by flip-chip assembly to the sensor diodes and the local busses. In the following a module based on MCM-D technology will be discussed and prototype results will be presented.

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

Science.gov (United States)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Innovative use of power integrated modules for DC power supplies

DEFF Research Database (Denmark)

Ørndrup Nielsen, Rasmus; Elkiær, Alexander; Munk-Nielsen, Stig

2013-01-01

In this article several innovative ways of utilizing Power Integrated Modules (PIM) as switching device in a DC power supply are presented. PIM have advantages in compactness of design, cost and fast prototype due to easier PCB layout. A PIM converter topology is chosen and designed resulting...... in an experimental setup. Results from the setup are presented showing the feasibility of using a PIM module as almost all power semiconductors in a DC power supply....

On the use of OSL of chip card modules with molding for retrospective and accident dosimetry

International Nuclear Information System (INIS)

Woda, Clemens; Fiedler, Irene; Spöttl, Thomas

2012-01-01

The potential of optically stimulated luminescence of wire-bond chip card modules with molded encapsulations for retrospective and accident dosimetry is investigated. Contact-based and contactless modules were studied, the latter finding potential use in electronic documents (e.g. electronic passports, electronic identity cards). Investigations were carried out on intact as well as chemically prepared modules, extracting the filler material. Contact-based modules are characterized according to zero dose signal, correlation between OSL and TL, dose response and long-term signal stability. For prepared modules, the minimum detectable dose immediately after irradiation is 3 mGy and between 20 and 200 mGy for contact-based and contactless modules, respectively. Dose recovery tests on contact-based modules indicate that the developed methodology yields results with sufficient accuracy for measurements promptly after irradiation, whereas a systematic underestimation is observed for longer delay times. The reasons for this behaviour are as yet not fully understood.

Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Engel, G.L., E-mail: gengel@siue.ed [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Hall, M.J.; Proctor, J.M. [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J. [Departments of Chemistry and Physics, Washington University, Saint Louis, MO 63130 (United States)

2009-12-21

This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-mum process (C5N).

Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

International Nuclear Information System (INIS)

Engel, G.L.; Hall, M.J.; Proctor, J.M.; Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J.

2009-01-01

This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-μm process (C5N).

InP MMIC Chip Set for Power Sources Covering 80-170 GHz

Science.gov (United States)

Ngo, Catherine

2001-01-01

We will present a Monolithic Millimeter-wave Integrated Circuit (MMIC) chip set which provides high output-power sources for driving diode frequency multipliers into the terahertz range. The chip set was fabricated at HRL Laboratories using a 0.1-micrometer gate-length InAlAs/InGaAs/InP high electron mobility transistor (HEMT) process, and features transistors with an f(sub max) above 600 GHz. The HRL InP HEMT process has already demonstrated amplifiers in the 60-200 GHz range. In this paper, these high frequency HEMTs form the basis for power sources up to 170 GHz. A number of state-of-the-art InP HEMT MMICs will be presented. These include voltage-controlled and fixed-tuned oscillators, power amplifiers, and an active doubler. We will first discuss an 80 GHz voltage-controlled oscillator with 5 GHz of tunability and at least 17 mW of output power, as well as a 120 GHz oscillator providing 7 mW of output power. In addition, we will present results of a power amplifier which covers the full WRIO waveguide band (75-110 GHz), and provides 40-50 mW of output power. Furthermore, we will present an active doubler at 164 GHz providing 8% bandwidth, 3 mW of output power, and an unprecedented 2 dB of conversion loss for an InP HEMT MMIC at this frequency. Finally, we will demonstrate a power amplifier to cover 140-170 GHz with 15-25 mW of output power and 8 dB gain. These components can form a power source in the 155-165 GHz range by cascading the 80 GHz oscillator, W-band power amplifier, 164 GHz active doubler and final 140-170 GHz power amplifier for a stable, compact local oscillator subsystem, which could be used for atmospheric science or astrophysics radiometers.

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

Science.gov (United States)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

ALICE chip processor

CERN Multimedia

Maximilien Brice

2003-01-01

This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

Parametric resonance and cooling on an atom chip

International Nuclear Information System (INIS)

Yan Bo; Li Xiaolin; Ke Min; Wang Yuzhu

2008-01-01

This paper observes the parametric excitation on atom chip by measuring the trap loss when applying a parametric modulation. By modulating the current in chip wires, it modulates not only the trap frequency but also the trap position. It shows that the strongest resonance occurs when the modulation frequency equals to the trap frequency. The resonance amplitude increases exponentially with modulation depth. Because the Z-trap is an anharmonic trap, there exists energy selective excitation which would cause parametric cooling. We confirm this effect by observing the temperature of atom cloud dropping

Demonstration of a Submillimeter-Wave HEMT Oscillator Module at 330 GHz

Science.gov (United States)

Radisic, Vesna; Deal, W. R.; Mei, X. B.; Yoshida, Wayne; Liu, P. H.; Uyeda, Jansen; Lai, Richard; Samoska, Lorene; Fung, King Man; Gaier, Todd;

Module-Integrated Power Converters Based on Universal Dock

Energy Technology Data Exchange (ETDEWEB)

Chapman, Patrick; Rodriguez, Fernando

2015-03-13

Solar power installations using alternating current photovoltaic (ACPV) modules have significant cost and performance advantages over systems using conventional solar modules and string inverters. ACPV modules have improved energy harvest due to module-level power point tracking and redundancy. More importantly, ACPV modules are easier and cheaper to install, lowering the total installed cost, indirect costs, and barriers to market entry. Furthermore, ACPV modules have communications and data logging capability, yielding module-level telemetry data that is useful in site diagnostics and other data applications. The products of these efforts were threefold. First, an advanced microinverter power topology was developed, modeled, simulated, and tested. Second, new microinverter enclosure concepts were developed and tested. Third, a new ACPV module prototype was constructed, combining the power topology and the enclosure concepts. SolarBridge filed for patents in each of these areas and is transitioning the project from a concept phase to full development.

Universal and inductorless DC/DC converter for multi-output power supplies in sensor and actuator networks

Science.gov (United States)

Saponara, Sergio; Ciarpi, Gabriele

2017-05-01

This work proposes a universal and inductorless DC/DC converter that can be used for a wide input range, from few V to 60 V, to regulate output voltages from 5 V down to 1 V in Sensor and Actuator Network nodes. The proposed converter has been developed within the Athenis3D European project. It is composed by a cascade of multiple switching capacitor stages, with a proper skip-mode control to implement both step-down and step-up converting ratios, thus regulating all input sources to a voltage of about 6 V. These switching stages are further cascaded with linear regulators, which can provide stable output voltages down to 1 V. The multi-output regulator has been realized as a single-chip in a low-cost 0.35 μm CMOS technology. It is available as a naked die or in a ceramic package. The only needed external components are surface mount capacitors, which can be integrated on top of the naked chip die, creating a 3D structure, using trench capacitors embedded in a passive interposing layer. This way the size of the power management unit is further minimized. An advantage of the proposed converter is that it isn't optimized for a particular input voltage, therefore it can be used with no constant input power, like power harvesting systems (e.g. solar cells, wind and water turbines) and very disturbed power supplies.

The overvoltage protection module for the power supply system for the pixel detector at Belle II experiment at KEK

International Nuclear Information System (INIS)

Kapusta, P.; Kisielewski, B.

2015-01-01

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experiment as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)

The overvoltage protection module for the power supply system for the pixel detector at Belle II experiment at KEK

Energy Technology Data Exchange (ETDEWEB)

Kapusta, P.; Kisielewski, B. [Institute of Nuclear Physics PAN, ul.Radzikowskiego 152, 31-875 Krakow, (Poland)

2015-07-01

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experiment as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)

Analysis of Harmonic Injection to the Modulation of Multi-Level ...

African Journals Online (AJOL)

This paper explores the analysis of third and ninth harmonic injection to the modulation of a multilevel diode clamped converter (DCC) at a varying modulation index. The spectral distributions of the various multi-level waveforms obtained under normal modulation index of 0.8 and over modulation index of 1.15 were ...

A 2.4GHz ULP OOK single-chip transceiver for healthcare applications

NARCIS (Netherlands)

Vidojkovic, M.; Huang, X.; Harpe, P.J.A.; Rampu, S.; Zhou, C.; Huang, Li; Molengraft, van de J.; Imamura, K.; Büsze, B.; Bouwens, F.; Konijnenburg, M.; Santana, J.; Breeschoten, A.; Huisken, J.; Philips, K.; Dolmans, G.; Groot, de H.W.H.

2011-01-01

This paper describes an ultra-low power (ULP) single chip transceiver for wireless body area network (WBAN) applications. It supports on-off keying (OOK) modulation, and it operates in the 2.36–2.4 GHz medical BAN and 2.4–2.485 GHz ISM bands. It is implemented in 90 nm CMOS technology. The direct

Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

Directory of Open Access Journals (Sweden)

Ching-Hwa Cheng

2011-09-01

Full Text Available The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Semipolar III–nitride quantum well waveguide photodetector integrated with laser diode for on-chip photonic system

KAUST Repository

Shen, Chao

2017-02-28

A high-performance waveguide photodetector (WPD) integrated with a laser diode (LD) sharing the single InGaN/GaN quantum well active region is demonstrated on a semipolar GaN substrate. The photocurrent of the integrated WPD is effectively tuned by the emitted optical power from the LD. The responsivity ranges from 0.018 to 0.051 A/W with increasing reverse bias from 0 to 10 V. The WPD shows a large 3 dB modulation bandwidth of 230 MHz. The integrated device, being used for power monitoring and on-chip communication, paves the way towards the eventual realization of a III–nitride on-chip photonic system.

Semipolar III–nitride quantum well waveguide photodetector integrated with laser diode for on-chip photonic system

KAUST Repository

Shen, Chao; Lee, Changmin; Stegenburgs, Edgars; Lerma, Jorge Holguin; Ng, Tien Khee; Nakamura, Shuji; DenBaars, Steven P.; Alyamani, Ahmed Y.; El-Desouki, Munir M.; Ooi, Boon S.

2017-01-01

A high-performance waveguide photodetector (WPD) integrated with a laser diode (LD) sharing the single InGaN/GaN quantum well active region is demonstrated on a semipolar GaN substrate. The photocurrent of the integrated WPD is effectively tuned by the emitted optical power from the LD. The responsivity ranges from 0.018 to 0.051 A/W with increasing reverse bias from 0 to 10 V. The WPD shows a large 3 dB modulation bandwidth of 230 MHz. The integrated device, being used for power monitoring and on-chip communication, paves the way towards the eventual realization of a III–nitride on-chip photonic system.

Integrated sample-to-detection chip for nucleic acid test assays.

Science.gov (United States)

Prakash, R; Pabbaraju, K; Wong, S; Tellier, R; Kaler, K V I S

2016-06-01

Nucleic acid based diagnostic techniques are routinely used for the detection of infectious agents. Most of these assays rely on nucleic acid extraction platforms for the extraction and purification of nucleic acids and a separate real-time PCR platform for quantitative nucleic acid amplification tests (NATs). Several microfluidic lab on chip (LOC) technologies have been developed, where mechanical and chemical methods are used for the extraction and purification of nucleic acids. Microfluidic technologies have also been effectively utilized for chip based real-time PCR assays. However, there are few examples of microfluidic systems which have successfully integrated these two key processes. In this study, we have implemented an electro-actuation based LOC micro-device that leverages multi-frequency actuation of samples and reagents droplets for chip based nucleic acid extraction and real-time, reverse transcription (RT) PCR (qRT-PCR) amplification from clinical samples. Our prototype micro-device combines chemical lysis with electric field assisted isolation of nucleic acid in a four channel parallel processing scheme. Furthermore, a four channel parallel qRT-PCR amplification and detection assay is integrated to deliver the sample-to-detection NAT chip. The NAT chip combines dielectrophoresis and electrostatic/electrowetting actuation methods with resistive micro-heaters and temperature sensors to perform chip based integrated NATs. The two chip modules have been validated using different panels of clinical samples and their performance compared with standard platforms. This study has established that our integrated NAT chip system has a sensitivity and specificity comparable to that of the standard platforms while providing up to 10 fold reduction in sample/reagent volumes.

Sensory and Quality Evaluation of Traditional Compared with Power Ultrasound Processed Corn (Zea Mays) Tortilla Chips.

Science.gov (United States)

Janve, Bhaskar; Yang, Wade; Sims, Charles

2015-06-01

Power ultrasound reduces the traditional corn steeping time from 18 to 1.5 h during tortilla chips dough (masa) processing. This study sought to examine consumer (n = 99) acceptability and quality of tortilla chips made from the masa by traditional compared with ultrasonic methods. Overall appearance, flavor, and texture acceptability scores were evaluated using a 9-point hedonic scale. The baked chips (process intermediate) before and after frying (finished product) were analyzed using a texture analyzer and machine vision. The texture values were determined using the 3-point bend test using breaking force gradient (BFG), peak breaking force (PBF), and breaking distance (BD). The fracturing properties determined by the crisp fracture support rig using fracture force gradient (FFG), peak fracture force (PFF), and fracture distance (FD). The machine vision evaluated the total surface area, lightness (L), color difference (ΔE), Hue (°h), and Chroma (C*). The results were evaluated by analysis of variance and means were separated using Tukey's test. Machine vision values of L, °h, were higher (P power ultrasound as potential tortilla chips processing aid. © 2015 Institute of Food Technologists®

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

CERN Document Server

Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

2012-01-01

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

Multi-Port High Voltage Gain Modular Power Converter for Offshore Wind Farms

Directory of Open Access Journals (Sweden)

Sen Song

2018-06-01

Full Text Available In high voltage direct current (HVDC power transmission of offshore wind power systems, DC/DC converters are applied to transfer power from wind generators to HVDC terminals, and they play a crucial role in providing a high voltage gain, high efficiency, and high fault tolerance. This paper introduces an innovative multi-port DC/DC converter with multiple modules connected in a scalable matrix configuration, presenting an ultra-high voltage step-up ratio and low voltage/current rating of components simultaneously. Additionally, thanks to the adoption of active clamping current-fed push–pull (CFPP converters as sub-modules (SMs, soft-switching is obtained for all power switches, and the currents of series-connected CFPP converters are auto-balanced, which significantly reduce switching losses and control complexity. Furthermore, owing to the expandable matrix structure, the output voltage and power of a modular converter can be controlled by those of a single SM, or by adjusting the column and row numbers of the matrix. High control flexibility improves fault tolerance. Moreover, due to the flexible control, the proposed converter can transfer power directly from multiple ports to HVDC terminals without bus cable. In this paper, the design of the proposed converter is introduced, and its functions are illustrated by simulation results.

New Technology for Microfabrication and Testing of a Thermoelectric Device for Generating Mobile Electrical Power

Science.gov (United States)

Prasad, Narashimha S.; Taylor, Patrick J.; Trivedi, Sudhir B.; Kutcher, Susan

2010-01-01

We report the results of fabrication and testing of a thermoelectric power generation module. The module was fabricated using a new "flip-chip" module assembly technique that is scalable and modular. This technique results in a low value of contact resistivity ( surfaces. Under mild testing, a power of 22 mW/sq cm was obtained from small (electrical power of practical and usable magnitude for remote applications using thermoelectric power generation technologies.

Simulating the Effect of Modulated Tool-Path Chip Breaking On Surface Texture and Chip Length

Energy Technology Data Exchange (ETDEWEB)

Smith, K.S.; McFarland, J.T.; Tursky, D. A.; Assaid, T. S.; Barkman, W. E.; Babelay, Jr., E. F.

2010-04-30

One method for creating broken chips in turning processes involves oscillating the cutting tool in the feed direction utilizing the CNC machine axes. The University of North Carolina at Charlotte and the Y-12 National Security Complex have developed and are refining a method to reliably control surface finish and chip length based on a particular machine's dynamic performance. Using computer simulations it is possible to combine the motion of the machine axes with the geometry of the cutting tool to predict the surface characteristics and map the surface texture for a wide range of oscillation parameters. These data allow the selection of oscillation parameters to simultaneously ensure broken chips and acceptable surface characteristics. This paper describes the machine dynamic testing and characterization activities as well as the computational method used for evaluating and predicting chip length and surface texture.

Simultaneous detection of multiple HPV DNA via bottom-well microfluidic chip within an infra-red PCR platform.

Science.gov (United States)

Liu, Wenjia; Warden, Antony; Sun, Jiahui; Shen, Guangxia; Ding, Xianting

2018-03-01

Portable Polymerase Chain Reaction (PCR) devices combined with microfluidic chips or lateral flow stripes have shown great potential in the field of point-of-need testing (PoNT) as they only require a small volume of patient sample and are capable of presenting results in a short time. However, the detection for multiple targets in this field leaves much to be desired. Herein, we introduce a novel PCR platform by integrating a bottom-well microfluidic chip with an infra-red (IR) excited temperature control method and fluorescence co-detection of three PCR products. Microfluidic chips are utilized to partition different samples into individual bottom-wells. The oil phase in the main channel contains multi-walled carbon nanotubes which were used as a heat transfer medium that absorbs energy from the IR-light-emitting diode (LED) and transfers heat to the water phase below. Cyclical rapid heating and cooling necessary for PCR are achieved by alternative power switching of the IR-LED and Universal Serial Bus (USB) mini-fan with a pulse width modulation scheme. This design of the IR-LED PCR platform is economic, compact, and fully portable, making it a promising application in the field of PoNT. The bottom-well microfluidic chip and IR-LED PCR platform were combined to fulfill a three-stage thermal cycling PCR for 40 cycles within 90 min for Human Papilloma Virus (HPV) detection. The PCR fluorescent signal was successfully captured at the end of each cycle. The technique introduced here has broad applications in nucleic acid amplification and PoNT devices.

Optimization of Modulation Waveforms for Improved EMI Attenuation in Switching Frequency Modulated Power Converters

Directory of Open Access Journals (Sweden)

Deniss Stepins

2015-01-01

Full Text Available Electromagnetic interference (EMI is one of the major problems of switching power converters. This paper is devoted to switching frequency modulation used for conducted EMI suppression in switching power converters. Comprehensive theoretical analysis of switching power converter conducted EMI spectrum and EMI attenuation due the use of traditional ramp and multislope ramp modulation waveforms is presented. Expressions to calculate EMI spectrum and attenuation are derived. Optimization procedure of the multislope ramp modulation waveform is proposed to get maximum benefits from switching frequency modulation for EMI reduction. Experimental verification is also performed to prove that the optimized multislope ramp modulation waveform is very useful solution for effective EMI reduction in switching power converters.

One-chip Integrated Module of MEMS Shock Sensor and Sensing Amplifier LSI using Pseudo-SOC Technology

Science.gov (United States)

Iida, Atsuko; Onozuka, Yutaka; Nishigaki, Michihiko; Yamada, Hiroshi; Funaki, Hideyuki; Itaya, Kazuhiko

We have been developing the pseudo-SOC technology for one-chip module integration of heterogeneous devices that realizes high electrical performance and high density of devices embodying the advantages of both SOC technology and SIP technology. Especially, this technology is available for MEMS-LSI integration. We developed a 0.2mm-thickness one-chip module integrating a MEMS shock sensor and a sensing amplifier LSI by applying this technology. The MEMS shock sensor and the sensing amplifier LSI were connected by high-rigidity epoxy resin optimized the material constants to reduce the stress and the warpage resulting from resin shrinkage due to curing. Then the planar insulating layer and the redistributed conducting layer were formed on it for the global layer. The MEMS shock sensor was preformed to be modularized with a glass cap. Electrical contacts were achieved by bonding of Au bumps on the MEMS fixed electrodes and via holes filled with Ag paste of the glass cap. Functional performance was confirmed by obtaining signal corresponding to the reference signal of the pick-up sensor. Furthermore, stress analysis was performed using the FEM model simulation considering the resin shrinkage.

A Novel 3D Thermal Impedance Model for High Power Modules Considering Multi-layer Thermal Coupling and Different Heating/Cooling Conditions

DEFF Research Database (Denmark)

Bahman, Amir Sajjad; Ma, Ke; Blaabjerg, Frede

2015-01-01

accurate temperature estimation either vertically or horizontally inside the power devices is still hard to identify. This paper investigates the thermal behavior of high power module in various operating conditions by means of Finite Element Method (FEM). A novel 3D thermal impedance network considering......Thermal management of power electronic devices is essential for reliable performance especially at high power levels. One of the most important activities in the thermal management and reliability improvement is acquiring the temperature information in critical points of the power module. However...

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Combined heat and power unit using renewable raw materials. A cogeneration power plant with wood chips and pellets; BHKW auf Basis nachwachsender Rohstoffe. KWK mit Holzhackschnitzeln und Pellets

Energy Technology Data Exchange (ETDEWEB)

Lennartz, Marc Wilhelm

2013-07-15

The combined heat and power units of the next generation operate with renewable resources. The plants working with wood chips or pellets now are ready for mass production. So, farmers and foresters, trade and municipalities may pile in the decentralized, energetic self-sufficiency. Two companies have developed procedures with which combined heat and power plants based can be operated on wood chips or pellets.

Generalised Multi-sequence Shift-Register Synthesis using Module Minimisation

DEFF Research Database (Denmark)

Nielsen, Johan Sebastian Rosenkilde

2013-01-01

We show how to solve a generalised version of the Multi-sequence Linear Feedback Shift-Register (MLFSR) problem using minimisation of free modules over F[x]. We show how two existing algorithms for minimising such modules run particularly fast on these instances. Furthermore, we show how one...

Runtime adaptive multi-processor system-on-chip: RAMPSoC

OpenAIRE

Göhringer, D.; Hübner, M.; Schatz, V.; Becker, J.

2008-01-01

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elemen...

Increasing security in inter-chip communication

Science.gov (United States)

Edwards, Nathan J; Hamlet, Jason; Bauer, Todd; Helinski, Ryan

2014-10-28

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Fiscal 2000 achievement report on the venture business assisting type regional consortium - Minor business creation base type. Development of 1-chip multifunctional motion sensor and its application to intelligent module; 2000 nendo chiiki consortium kenkyu kaihatsu jigyo seika hokokusho. 1 chip gata takino undo sensor no kaihatsu to intelligent module eno tekiyo

Energy Technology Data Exchange (ETDEWEB)

NONE

2001-03-01

The aim is to embody an intelligent micromodule for sensing bodily motions. For this purpose, technologies were established for high accuracy/high aspect ratio etching of crystals and for detecting angular velocity and acceleration, and a 1-chip multifunctional motion sensor was developed. The results of the efforts are briefly described below. A 1-chip multifunctional motion sensor (device size: 16 times 6 times 0.3mm) was developed, capable of simultaneously detecting uniaxial acceleration and uniaxial angular velocity, and an operating circuit was established for the detection. Using the 1-chip multifunctional motion sensor, a wrist watch type intelligent module was developed, capable of discriminating between various patterns of human behavior (walking, jogging, desk work, etc.). An intelligent module and the host computer were connected by wire or radio enabling the real-time observation of a patient's kinetic behavior, and this helped develop an application program allowing the quantification of the rate of recovery of patients undergoing rehabilitation. Using an intelligent module, an application program was developed enabling a laryngeal patient to establish communication by a physical action in case of emergency. (NEDO)

Optimization of high frequency flip-chip interconnects for digital superconducting circuits

International Nuclear Information System (INIS)

Rafique, M R; Engseth, H; Kidiyarova-Shevchenko, A

2006-01-01

This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than -20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s -1 speedand can operate above 100 Gbit s -1 speed. Wide bandwidth transmission requires the realization of an advanced flip-chip process with a small dimension of the MCM contact (less than 30 μm diameter of the contact pad) and small height of the flip-chip contact bumps of the order of 2 μm. Current processes with about 7 μm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s -1 ; however, the maximum speed of operation is 61 Gbit s -1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link

Direct cooled power electronics substrate

Science.gov (United States)

Wiles, Randy H [Powell, TN; Wereszczak, Andrew A [Oak Ridge, TN; Ayers, Curtis W [Kingston, TN; Lowe, Kirk T [Knoxville, TN

2010-09-14

The disclosure describes directly cooling a three-dimensional, direct metallization (DM) layer in a power electronics device. To enable sufficient cooling, coolant flow channels are formed within the ceramic substrate. The direct metallization layer (typically copper) may be bonded to the ceramic substrate, and semiconductor chips (such as IGBT and diodes) may be soldered or sintered onto the direct metallization layer to form a power electronics module. Multiple modules may be attached to cooling headers that provide in-flow and out-flow of coolant through the channels in the ceramic substrate. The modules and cooling header assembly are preferably sized to fit inside the core of a toroidal shaped capacitor.

Next Generation Space Telescope Integrated Science Module Data System

Science.gov (United States)

Schnurr, Richard G.; Greenhouse, Matthew A.; Jurotich, Matthew M.; Whitley, Raymond; Kalinowski, Keith J.; Love, Bruce W.; Travis, Jeffrey W.; Long, Knox S.

1999-01-01

The Data system for the Next Generation Space Telescope (NGST) Integrated Science Module (ISIM) is the primary data interface between the spacecraft, telescope, and science instrument systems. This poster includes block diagrams of the ISIM data system and its components derived during the pre-phase A Yardstick feasibility study. The poster details the hardware and software components used to acquire and process science data for the Yardstick instrument compliment, and depicts the baseline external interfaces to science instruments and other systems. This baseline data system is a fully redundant, high performance computing system. Each redundant computer contains three 150 MHz power PC processors. All processors execute a commercially available real time multi-tasking operating system supporting, preemptive multi-tasking, file management and network interfaces. These six processors in the system are networked together. The spacecraft interface baseline is an extension of the network, which links the six processors. The final selection for Processor busses, processor chips, network interfaces, and high-speed data interfaces will be made during mid 2002.

Autonomous transmission power adaptation for multi-radio multi-channel wireless mesh networks

CSIR Research Space (South Africa)

Olwal, TO

2009-09-01

Full Text Available Multi-Radio Multi-Channel (MRMC) systems are key to power control problems in WMNs. Previous studies have emphasized through- put maximization in such systems as the main design challenge and transmission power control treated as a secondary issue...

Autonomous transmission power adaptation for multi-radio multi-channel wireless mesh networks

CSIR Research Space (South Africa)

Olwal, TO

2008-09-01

Full Text Available Multi-Radio Multi-Channel (MRMC) systems are key to power control problems in WMNs. Previous studies have emphasized throughput maximization in such systems as the main design challenge and transmission power control treated as a secondary issue...

An inherently safe power reactor module

International Nuclear Information System (INIS)

Salerno, L.N.

1985-01-01

General Electric's long participation in liquid metal reactor technology has led to a Power Reactor Inherently Safe Module (PRISM) concept supported by DOE contract DE-AC06-85NE37937. The reactor module is sized to maximize inherent safety features. The small size allows factory fabrication, reducing field construction and field QA/QC labor, and allows safety to be demonstrated in full scale, to support a pre-licensed standard commercial product. The module is small enough to be placed underground, and can be combined with steam and electrical generating equipment to provide a complete electrical power producing plant in the range of 400-1200 MWe. Initial assessments are that the concept has the potential to be economically competitive with existing methods of power production used by the utility industry

Asymmetric power device rating selection for even temperature distribution in NPC inverter

DEFF Research Database (Denmark)

Choi, Uimin; Blaabjerg, Frede

2017-01-01

the power rating and lifetime of the NPC inverter are limited by the most stressed devices. In this paper, an asymmetric power device rating selection method for the NPC inverter is proposed in order to balance the lifetimes of the power devices. The thermal distribution of the power devices is analyzed......A major drawback of the NPC inverter is an unequal power loss distribution among the power devices which leads to unequal temperature stress among them. Therefore, certain power devices experience higher temperature stress, which is the main cause of power device module failure and thus both...... based on 30 kW NPC inverter as a case study. Analytical power loss and thermal impedance models depending on the chip size are derived. Finally, using these models, the junction temperatures of the power devices depending on the chip size is discussed and a proper chip size for an even temperature...

Molecular detection of harmful cyanobacteria and expression of their toxin genes in Dutch lakes using multi-probe RNA chips

NARCIS (Netherlands)

Van de Waal, Dedmer B.; Guillebault, Delphine; Alfonso, Amparo; Rodríguez, Inés; Botana, Luis M.; Bijkerk, Ronald; Medlin, Linda K.

Abstract Harmful cyanobacterial blooms are a major threat to water quality and human health. Adequate risk assessment is thus required, which relies strongly on comprehensive monitoring. Here, we tested novel multi-probe RNA chips developed in the European project, μAqua, to determine the abundance

Space Vector Pulse Width Modulation of a Multi-Level Diode ...

African Journals Online (AJOL)

Space Vector Pulse Width Modulation of a Multi-Level Diode Clamped ... of MATLAB /SIMULINK modeling of the space vector pulse-width modulation and the ... two adjacent active vectors in determining the switching process of the multilevel ...

A novel on-chip high to low voltage power conversion circuit

International Nuclear Information System (INIS)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong; Lai Xinquan; Ye Qiang; Li Xianrui

2009-01-01

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 μm BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm 2 area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

A novel on-chip high to low voltage power conversion circuit

Energy Technology Data Exchange (ETDEWEB)

Wang Hui; Wang Songlin; Mou Zaixin; Guo Baolong [Institute of Mechano-electronic Engineering, Xidian University, Xi' an 71007 (China); Lai Xinquan; Ye Qiang; Li Xianrui, E-mail: whui94@126.co [Institute of Electronic CAD, Xidian University, Xi' an 710071 (China)

2009-03-15

A novel power supply transform technique for high voltage IC based on the TSMC 0.6 mum BCD process is achieved. An adjustable bandgap voltage reference is presented which is different from the traditional power supply transform technique. It can be used as an internal power supply for high voltage IC by using the push-pull output stage to enhance its load capability. High-order temperature compensated circuit is designed to ensure the precision of the reference. Only 0.01 mm{sup 2} area is occupied using this novel power supply technique. Compared with traditional technique, 50% of the area is saved, 40% quiescent power loss is decreased, and the temperature coefficient of the reference is only 4.48 ppm/deg. C. Compared with the traditional LDO (low dropout) regulator, this power conversion architecture does not need external output capacitance and decreases the chip-pin and external components, so the PCB area and design cost are also decreased. The testing results show that this circuit works well.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

Science.gov (United States)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

Range based power control for multi-radio multi-channel wireless mesh networks

CSIR Research Space (South Africa)

Olwal, TO

2009-08-01

Full Text Available Multi-Radio Multi-Channel (MRMC) systems are key to power control problems in Wireless Mesh Networks (WMNs). In this paper, researchers present a range based dynamic power control for MRMC WMNs. First, WMN is represented as a set of disjoint Unified...

Power Generator with Thermo-Differential Modules

Science.gov (United States)

Saiz, John R.; Nguyen, James

2010-01-01

A thermoelectric power generator consists of an oven box and a solar cooker/solar reflector unit. The solar reflector concentrates sunlight into heat and transfers the heat into the oven box via a heat pipe. The oven box unit is surrounded by five thermoelectric modules and is located at the bottom end of the solar reflector. When the heat is pumped into one side of the thermoelectric module and ejected from the opposite side at ambient temperatures, an electrical current is produced. Typical temperature accumulation in the solar reflector is approximately 200 C (392 F). The heat pipe then transfers heat into the oven box with a loss of about 40 percent. At the ambient temperature of about 20 C (68 F), the temperature differential is about 100 C (180 F) apart. Each thermoelectric module, generates about 6 watts of power. One oven box with five thermoelectric modules produces about 30 watts. The system provides power for unattended instruments in remote areas, such as space colonies and space vehicles, and in polar and other remote regions on Earth.

Development of a multi-purpose logic module with the FPGA

International Nuclear Information System (INIS)

Nanbu, K.; Ishikawa, T.; Shimizu, H.

2008-01-01

We have developed a multi-purpose logic module (MPLM) with an FPGA. The internal circuit of this module can be modified easily with the FPGA. This kind of module enables trigger pulse processing for nuclear science. As a first step, the MPLM is used as an event tag generator in experiments with the FOREST detector system. (author)

Cache-aware network-on-chip for chip multiprocessors

Science.gov (United States)

Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

2009-05-01

This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

Ultrasensitive NO2 gas sensors using hybrid heterojunctions of multi-walled carbon nanotubes and on-chip grown SnO2 nanowires

Science.gov (United States)

Nguyet, Quan Thi Minh; Van Duy, Nguyen; Manh Hung, Chu; Hoa, Nguyen Duc; Van Hieu, Nguyen

2018-04-01

Hybrid heterojunction devices are designed for ultrahigh response to NO2 toxic gas. The devices were constructed by assembling multi-walled carbon nanotubes (MWCNTs) on a microelectrode chip bridged bare Pt-electrode and a Pt-electrode with pre-grown SnO2 nanowires (NWs). All heterojunction devices were realized using different types of MWCNTs, which exhibit ultrahigh response to sub-ppm NO2 gas at 50 °C operated in the reverse bias mode. The response to 1 ppm NO2 gas reaches 11300, which is about 100 times higher than that of a back-to-back heterojunction device fabricated from SnO2 NWs and MWCNTs. In addition, the present device exhibits an ultralow detection limit of about 0.68 ppt. The modulation of trap-assisted tunneling current under reverse bias is the main gas-sensing mechanism. This principle device presents a concept for developing gas sensors made of a hybrid between semiconductor metal oxide NWs and CNTs.

SIMULASI TEKNIK POWER CONTROL DAN MULTI USER DETECTION PADA SISTEM KOMUNIKASI DS-CDMA

Directory of Open Access Journals (Sweden)

Yuli Christyono

2012-02-01

Full Text Available CDMA is interference limited multiple access system. Because all users transmit on the same frequency,internal interference generated by the system is the most significant factor in determining system capacity andcall quality. The transmit power for each user must be reduced to limit interference, however, the power shouldbe enough to maintain the required Eb/No (signal to noise ratio for a satisfactory call quality. Maximumcapacity is achieved when Eb/No of every user is at the minimum level needed for the acceptable channelperformance. As the MS moves around, the RF environment continuously changes due to fast and slow fading,external interference, shadowing , and other factors. The aim of the dynamic power control is to limittransmitted power on both the links while maintaining link quality under all conditions. Additional advantagesare longer mobile battery life and longer life span of BTS power amplifiers.In this research will be made a sumulation of power control and multi user detection to avoid the interferencebetween MS.Observations show that the increasing number of users will decrease the value of Signal to Interfrence Ratio(SIR / SIR below the target. To cope the growing number of users increases can be done by iteration / updatingpower transmit so the convergence computation can be reached and target value SIR can be achieved. Inaddition, to reduce interference can also be done by extending the number of chips.

A Performance Improvement of Power Supply Module for Safety-related Controller

International Nuclear Information System (INIS)

Kim, Jong-Kyun; Yun, Dong-Hwa; Hwang, Sung-Jae; Lee, Myeong-Kyun; Yoo, Kwan-Woo

2015-01-01

In this paper, in relation to voltage shortage state when power supply module is a slave mode, the performance improvement by modifying a PFC(Power Factor Correction) circuit is presented. With the modification of the PFC circuit, the performance improvement in respect of the voltage shortage state when the power supply module is a slave mode is checked. As a result, POSAFE-Q PLC can ensure the stability with the redundant power supply module. The purpose of this paper is to improve the redundant performance of power supply module(NSPS-2Q). It is one of components in POSAFE-Q which is a PLC(Programmable Logic Controller) that has been developed for the evaluation of safety-related. Power supply module provides a stable power in order that POSAFE-Q can be operated normally. It is possible to be mounted two power supply modules in POSAFE-Q for a redundant(Master/Slave) function. So that even if a problem occurs in one power supply module, another power supply module will provide a power to POSAFE-Q stably

A Performance Improvement of Power Supply Module for Safety-related Controller

Energy Technology Data Exchange (ETDEWEB)

Kim, Jong-Kyun; Yun, Dong-Hwa; Hwang, Sung-Jae; Lee, Myeong-Kyun; Yoo, Kwan-Woo [PONUTech Co., Seoul (Korea, Republic of)

2015-10-15

In this paper, in relation to voltage shortage state when power supply module is a slave mode, the performance improvement by modifying a PFC(Power Factor Correction) circuit is presented. With the modification of the PFC circuit, the performance improvement in respect of the voltage shortage state when the power supply module is a slave mode is checked. As a result, POSAFE-Q PLC can ensure the stability with the redundant power supply module. The purpose of this paper is to improve the redundant performance of power supply module(NSPS-2Q). It is one of components in POSAFE-Q which is a PLC(Programmable Logic Controller) that has been developed for the evaluation of safety-related. Power supply module provides a stable power in order that POSAFE-Q can be operated normally. It is possible to be mounted two power supply modules in POSAFE-Q for a redundant(Master/Slave) function. So that even if a problem occurs in one power supply module, another power supply module will provide a power to POSAFE-Q stably.

37 GHz Direct-Modulation Bandwidth of Multi-Section InGaAsP/InP DBR-Laser with weakly coupled active grating section

DEFF Research Database (Denmark)

Kaiser, W.; Bach, L.; Reithmaier, J. P.

2003-01-01

37 GHz direct-modulation bandwidth could be obtained by a multi-section design with an integrated weakly coupled DBR grating. The laser shows side mode suppression ratios of 45 dB and output powers exceeding 20 mW....

Cobalt hexacyanoferrate modified multi-walled carbon nanotubes/graphite composite electrode as electrochemical sensor on microfluidic chip

International Nuclear Information System (INIS)

Li Xinchun; Chen Zuanguang; Zhong Yuwen; Yang Fan; Pan Jianbin; Liang Yajing

2012-01-01

Highlights: ► CoHCF nanoparticles modified MWCNTs/graphite electrode use for electrochemistry on electrophoresis microchip for the first time. ► Simultaneous, rapid, and sensitive electrochemical detection of hydrazine and isoniazid in real samples. ► An exemplary work of CME sensor assembly onto microchip for determination of analytes with environmental significance. ► Manifestation of the applicability and flexibility of CME sensor for electroanalysis on microfluidic chip. - Abstract: Nanomaterial-based electrochemical sensor has received significant interest. In this work, cobalt hexacyanoferrate modified multi-walled carbon nanotubes/graphite composite electrode was electrochemically prepared and exploited as an amperometric detector for microchip electrophoresis. The prepared sensor displayed rapid and sensitive response towards hydrazine and isoniazid oxidation, which was attributed to synergetic electrocatalytic effect of cobalt hexacyanoferrate and multi-walled carbon nanotubes. The sensitivity enhancement with nearly two orders of magnitude was gained, compared with the bare carbon paste electrode, with the detection limit of 0.91 μM (S/N = 3) for hydrazine. Acceptable repeatability of the microanalysis system was verified by consecutive eleven injections of hydrazine without chip and electrode treatments, the RSDs for peak current and migration time were 3.4% and 2.1%, respectively. Meanwhile, well-shaped electrophoretic peaks were observed, mainly due to fast electron transfer of electroactive species on the modified electrode. The developed microchip-electrochemistry setup was successfully applied to the determination of hydrazine and isoniazid in river water and pharmaceutical preparation, respectively. Several merits of the novel electrochemical sensor coupled with microfluidic platform, such as comparative stability, easy fabrication and high sensitivity, hold great potential for hydrazine compounds assay in the lab-on-a-chip system.

Multi-functional Electric Module for a Vehicle

Science.gov (United States)

Bluethmann, William J. (Inventor); Waligora, Thomas M. (Inventor); Fraser-Chanpong, Nathan (Inventor); Reed, Ryan (Inventor); Akinyode, Akinjide Akinniyi (Inventor); Spain, Ivan (Inventor); Dawson, Andrew D. (Inventor); Figuered, Joshua M. (Inventor); Herrera, Eduardo (Inventor); Markee, Mason M. (Inventor)

2015-01-01

A multi-functional electric module (eModule) is provided for a vehicle having a chassis, a master controller, and a drive wheel having a propulsion-braking module. The eModule includes a steering control assembly, mounting bracket, propulsion control assembly, brake controller, housing, and control arm. The steering control assembly includes a steering motor controlled by steering controllers in response to control signals from the master controller. A mounting feature of the bracket connects to the chassis. The propulsion control assembly and brake controller are in communication with the propulsion-braking module. The control arm connects to the lower portion and contains elements of a suspension system, with the control arm being connectable to the drive wheel via a wheel input/output block. The controllers are responsive to the master controller to control a respective steering, propulsion, and braking function. The steering motor may have a dual-wound stator with windings controlled via the respective steering controllers.

Low-cost and versatile thermal test chip for power assemblies assessment and thermometric calibration purposes

International Nuclear Information System (INIS)

Jorda, X.; Perpina, X.; Vellvehi, M.; Madrid, F.; Flores, D.; Hidalgo, S.; Millan, J.

2011-01-01

Chips specifically designed for thermal tests such as the assessment of packages, are of main interest in Microelectronics. Nevertheless, these test dies are required in relatively low quantities and their price is a limiting factor. This work describes a low-cost thermal test chip, specifically developed for the needs of power electronics. It is based on a poly-silicon heating resistor and a decoupled Pt temperature sensing resistor on the top, allowing to dissipate more than 60 W (170 W/cm 2 ) and reaching temperatures up to 200 o C. Its simple structure allows an easy simulation and modeling. These features have been taken in profit for packaging materials assessment, calibration of temperature measurement apparatus and methods, and validation of thermal models and simulations. - Highlights: → We describe a low-cost thermal test chip developed for power electronics applications. → It integrates a poly-silicon heating resistor and a Pt temperature sensing resistor on the top. → It can dissipate up to 200 W/cm 2 and work up to 200 o C. → It has been used for thermal resistance and conductivity measurement of substrates. → It allowed also the calibration of advanced thermometric equipments.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

Science.gov (United States)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

NARCIS (Netherlands)

Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Rauwerda, G.K.; Smit, L.T.

Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as

Energy Model of Networks-on-Chip and a Bus

NARCIS (Netherlands)

Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Kavaldjiev, N.K.; Becker, Jens E.; Becker, Jürgen; Nurmi, J.; Takala, J.; Hamalainen, T.D.

2005-01-01

A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both

Cross-flow filtration of yeast extract with multi-tubular membrane module and rotating-disk membrane module; Makukaitengata heibanmaku module to tankanjomaku module ni yoru kobo hasaieki no cross flow roka

Energy Technology Data Exchange (ETDEWEB)

Matsushita, K.; Shimizu, Y.; Watanabe, a. [Toto Ltd., Kitakyushu (Japan)

1994-09-15

A membrane separation experiment was made with multi-tubular membrane module and rotating-disk membrane module to study the cross-flow filtration of yeast extract. The membrane was an alumina precision filtration membrane with 0.15 micron m diameter pores. A multi-tubular membrane which was 19 in number of channels and 0.113{sup 2} in effective membrane area was fitted to the multi-tubular membrane module. A rotating-disk membrane which was 0.071m{sup 2} in effective membrane area was fitted to the rotating-disk membrane module. Judging from the concentration speed and factor, the rotating-disk type is more advantageous in concentrating the suspension than the multi-tubular type. The soluble high-molecular component was more easily filtrated through the rotating-disk type, which is judged attributable to its possible operation at a high flow rate on the membrane surface without necessitating a high-flow rate circulation pump. As compared with the conventional cross-filtration type, the rotating-disk type gives a high permeate flux even at a high concentration factor. 11 refs., 5 figs.

Flow-cytometric identification of vinegars using a multi-parameter analysis optical detection module

Science.gov (United States)

Verschooten, T.; Ottevaere, H.; Vervaeke, M.; Van Erps, J.; Callewaert, M.; De Malsche, W.; Thienpont, H.

2015-09-01

We show a proof-of-concept demonstration of a multi-parameter analysis low-cost optical detection system for the flowcytometric identification of vinegars. This multi-parameter analysis system can simultaneously measure laser induced fluorescence, absorption and scattering excited by two time-multiplexed lasers of different wavelengths. To our knowledge no other polymer optofluidic chip based system offers more simultaneous measurements. The design of the optofluidic channels is aimed at countering the effects that viscous fingering, air bubbles, and emulsion samples can have on the correct operation of such a detection system. Unpredictable variations in viscosity and refractive index of the channel content can be turned into a source of information. The sample is excited by two laser diodes that are driven by custom made low-cost laser drivers. The optofluidic chip is built to be robust and easy to handle and is reproducible using hot embossing. We show a custom optomechanical holder for the optofluidic chip that ensures correct alignment and automatic connection to the external fluidic system. We show an experiment in which 92 samples of vinegar are measured. We are able to identify 9 different kinds of vinegar with an accuracy of 94%. Thus we show an alternative approach to the classic optical spectroscopy solution at a lowered. Furthermore, we have shown the possibility of predicting the viscosity and turbidity of vinegars with a goodness-of-fit R2 over 0.947.

Power transistor module for high current applications

International Nuclear Information System (INIS)

Cilyo, F.F.

1975-01-01

One of the parts needed for the control system of the 400-GeV accelerator at Fermilab was a power transistor with a safe operating area of 1800A at 50V, dc current gain of 100,000 and 20 kHz bandwidth. Since the commercially available discrete devices and power hybrid packages did not meet these requirements, a power transistor module was developed which performed satisfactorily. By connecting 13 power transistors in parallel, with due consideration for network and heat dissipation problems, and by driving these 13 with another power transistor, a super power transistor is made, having an equivalent current, power, and safe operating area capability of 13 transistors. For higher capabilities, additional modules can be conveniently added. (auth)

Multi-crystalline II-VI based multijunction solar cells and modules

Science.gov (United States)

Hardin, Brian E.; Connor, Stephen T.; Groves, James R.; Peters, Craig H.

2015-06-30

Multi-crystalline group II-VI solar cells and methods for fabrication of same are disclosed herein. A multi-crystalline group II-VI solar cell includes a first photovoltaic sub-cell comprising silicon, a tunnel junction, and a multi-crystalline second photovoltaic sub-cell. A plurality of the multi-crystalline group II-VI solar cells can be interconnected to form low cost, high throughput flat panel, low light concentration, and/or medium light concentration photovoltaic modules or devices.

Scalable Multi-core Architectures Design Methodologies and Tools

CERN Document Server

Jantsch, Axel

2012-01-01

As Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures. This book provides a current snapshot of industrial and academic research, conducted as part of the European FP7 MOSART project, addressing urgent challenges in many-core architectures and application mapping.  It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies. Describes trends towards distributed memory architectures and distributed power management; Integrates Network on Chip with distributed, shared memory architectures; Demonstrates novel design methodologies and frameworks for multi-core design space exploration; Shows how midll...

Comparison of single-/few-/multi-mode 850 nm VCSELs for optical OFDM transmission.

Science.gov (United States)

Kao, Hsuan-Yun; Tsai, Cheng-Ting; Leong, Shan-Fong; Peng, Chun-Yen; Chi, Yu-Chieh; Huang, Jian Jang; Kuo, Hao-Chung; Shih, Tien-Tsorng; Jou, Jau-Ji; Cheng, Wood-Hi; Wu, Chao-Hsin; Lin, Gong-Ru

2017-07-10

For high-speed optical OFDM transmission applications, a comprehensive comparison of the homemade multi-/few-/single-transverse mode (MM/FM/SM) vertical cavity surface emitting laser (VCSEL) chips is performed. With microwave probe, the direct encoding of pre-leveled 16-QAM OFDM data and transmission over 100-m-long OM4 multi-mode-fiber (MMF) are demonstrated for intra-datacenter applications. The MM VCSEL chip with the largest emission aperture of 11 μm reveals the highest differential quantum efficiency which provides the highest optical power of 8.67 mW but exhibits the lowest encodable bandwidth of 21 GHz. In contrast, the SM VCSEL chip fabricated with the smallest emission aperture of only 3 μm provides the highest 3-dB encoding bandwidth up to 23 GHz at a cost of slight heat accumulation. After optimization, with the trade-off set between the receiving signal-to-noise ratio (SNR) and bandwidth, the FM VCSEL chip guarantees the highest optical OFDM transmission bit rate of 96 Gbit/s under back-to-back case with its strongest throughput. Among three VCSEL chips, the SM VCSEL chip with nearly modal-dispersion free feature is treated as the best candidate for carrying the pre-leveled 16-QAM OFDM data over 100-m OM4-MMF with same material structure but exhibits different oxide-layer confined gain cross-sections with one another at 80-Gbit/s with the smallest receiving power penalty of 1.77 dB.

Development of a multi-physic, multi-time virtual proto-typing module. Application to power converters; Developpement d'un module de prototypage virtuel multiphysique, multidomaine et multitemps. Application aux convertisseurs de puissance

Energy Technology Data Exchange (ETDEWEB)

Menanteau, L.

2004-10-15

This works concerns the development of a virtual proto-typing tool for electro-thermo-mechanical simulation of power converters. The programming of this code, written in an object-oriented language, includes a dual Schur Domain Decomposition Method. The solving of problems including floating sub-domains can be performed in steady-state whereas man can couple implicit and explicit integration schemes. These integration schemes can have different time steps. Moreover, the code includes parts of programme which permit the parallelization of calculus and so the optimisation of the times of resolution. The benchmarks which are presented validate the method and show its substantial gains in time of calculus. The last part of this work concerns the study of an industrial benchmark concerning the power converters used in railway transport: it concerns the electro-thermal simulation of a semiconductor chip in steady state and in transient. This sample allows to compare different strategies of tearing in sub-domains and to couple different time steps on the same structure. (author)

Multiple-state based power control for multi-radio multi-channel wireless mesh networks

CSIR Research Space (South Africa)

Olwal, TO

2009-01-01

Full Text Available Multi-Radio Multi-Channel (MRMC) systems are key to power control problems in wireless mesh networks (WMNs). In this paper, we present asynchronous multiple-state based power control for MRMC WMNs. First, WMN is represented as a set of disjoint...

A polymer chip-integrable piezoelectric micropump with low backpressure dependence

DEFF Research Database (Denmark)

Conde, A. J.; Bianchetti, A.; Veiras, F. E.

2015-01-01

We describe a piezoelectric micropump constructed in polymers with conventional machining methods. The micropump is self-contained and can be built as an independent device or as an on-chip module within laminated microfluidic chips. We demonstrate on-chip integrability by the fabrication and tes...

A simple method for fabricating multi-layer PDMS structures for 3D microfluidic chips

KAUST Repository

Zhang, Mengying

2010-01-01

We report a simple methodology to fabricate PDMS multi-layer microfluidic chips. A PDMS slab was surface-treated by trichloro (1H,1H,2H,2H-perfluorooctyl) silane, and acts as a reusable transferring layer. Uniformity of the thickness of the patterned PDMS layer and the well-alignment could be achieved due to the transparency and proper flexibility of this transferring layer. Surface treatment results are confirmed by XPS and contact angle testing, while bonding forces between different layers were measured for better understanding of the transferring process. We have also designed and fabricated a few simple types of 3D PDMS chip, especially one consisting of 6 thin layers (each with thickness of 50 μm), to demonstrate the potential utilization of this technique. 3D fluorescence images were taken by a confocal microscope to illustrate the spatial characters of essential parts. This fabrication method is confirmed to be fast, simple, repeatable, low cost and possible to be mechanized for mass production. © The Royal Society of Chemistry 2010.

Module-based Hybrid Uncertainty Quantification for Multi-physics Applications: Theory and Software

Energy Technology Data Exchange (ETDEWEB)

Tong, Charles [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Chen, Xiao [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Iaccarino, Gianluca [Stanford Univ., CA (United States); Mittal, Akshay [Stanford Univ., CA (United States)

2013-10-08

In this project we proposed to develop an innovative uncertainty quantification methodology that captures the best of the two competing approaches in UQ, namely, intrusive and non-intrusive approaches. The idea is to develop the mathematics and the associated computational framework and algorithms to facilitate the use of intrusive or non-intrusive UQ methods in different modules of a multi-physics multi-module simulation model in a way that physics code developers for different modules are shielded (as much as possible) from the chores of accounting for the uncertain ties introduced by the other modules. As the result of our research and development, we have produced a number of publications, conference presentations, and a software product.

Power magnetic devices a multi-objective design approach

CERN Document Server

Sudhoff, Scott D

2014-01-01

Presents a multi-objective design approach to the many power magnetic devices in use today Power Magnetic Devices: A Multi-Objective Design Approach addresses the design of power magnetic devices-including inductors, transformers, electromagnets, and rotating electric machinery-using a structured design approach based on formal single- and multi-objective optimization. The book opens with a discussion of evolutionary-computing-based optimization. Magnetic analysis techniques useful to the design of all the devices considered in the book are then set forth. This material is then used for ind

Cobalt hexacyanoferrate modified multi-walled carbon nanotubes/graphite composite electrode as electrochemical sensor on microfluidic chip

Energy Technology Data Exchange (ETDEWEB)

Li Xinchun [School of Pharmaceutical Sciences, Sun Yat-sen University, 132 Waihuan East Road of Higher Education Mega Centre, Guangzhou 510006 (China); Chen Zuanguang, E-mail: chenzg@mail.sysu.edu.cn [School of Pharmaceutical Sciences, Sun Yat-sen University, 132 Waihuan East Road of Higher Education Mega Centre, Guangzhou 510006 (China); Zhong Yuwen, E-mail: yu0106@163.com [Center for Disease Control and Prevention of Guangdong Province, 176 Xingangxi, Guangzhou 510300 (China); Yang Fan; Pan Jianbin; Liang Yajing [School of Pharmaceutical Sciences, Sun Yat-sen University, 132 Waihuan East Road of Higher Education Mega Centre, Guangzhou 510006 (China)

2012-01-13

Highlights: Black-Right-Pointing-Pointer CoHCF nanoparticles modified MWCNTs/graphite electrode use for electrochemistry on electrophoresis microchip for the first time. Black-Right-Pointing-Pointer Simultaneous, rapid, and sensitive electrochemical detection of hydrazine and isoniazid in real samples. Black-Right-Pointing-Pointer An exemplary work of CME sensor assembly onto microchip for determination of analytes with environmental significance. Black-Right-Pointing-Pointer Manifestation of the applicability and flexibility of CME sensor for electroanalysis on microfluidic chip. - Abstract: Nanomaterial-based electrochemical sensor has received significant interest. In this work, cobalt hexacyanoferrate modified multi-walled carbon nanotubes/graphite composite electrode was electrochemically prepared and exploited as an amperometric detector for microchip electrophoresis. The prepared sensor displayed rapid and sensitive response towards hydrazine and isoniazid oxidation, which was attributed to synergetic electrocatalytic effect of cobalt hexacyanoferrate and multi-walled carbon nanotubes. The sensitivity enhancement with nearly two orders of magnitude was gained, compared with the bare carbon paste electrode, with the detection limit of 0.91 {mu}M (S/N = 3) for hydrazine. Acceptable repeatability of the microanalysis system was verified by consecutive eleven injections of hydrazine without chip and electrode treatments, the RSDs for peak current and migration time were 3.4% and 2.1%, respectively. Meanwhile, well-shaped electrophoretic peaks were observed, mainly due to fast electron transfer of electroactive species on the modified electrode. The developed microchip-electrochemistry setup was successfully applied to the determination of hydrazine and isoniazid in river water and pharmaceutical preparation, respectively. Several merits of the novel electrochemical sensor coupled with microfluidic platform, such as comparative stability, easy fabrication and

Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

CERN Document Server

Poikela, Tuomas; Paakkulainen, J

2010-01-01

The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

Energy Technology Data Exchange (ETDEWEB)

Puellen, Lukas

2015-02-10

In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

International Nuclear Information System (INIS)

Puellen, Lukas

2015-01-01

In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

A novel microfluidic chip electrophoresis strategy for simultaneous, label-free, multi-protein detection based on a graphene energy transfer biosensor.

Science.gov (United States)

Lin, Fengming; Zhao, Xiaochao; Wang, Jianshe; Yu, Shiyong; Deng, Yulin; Geng, Lina; Li, HuanJun

2014-06-07

A new type of high-throughput and parallel optical sensing platform with a single-color probe based on microfluidic chip electrophoresis combined with aptamer-carboxyfluorescein/graphene oxide energy transfer is reported here. Label-free protein multi-targets were detected, even in challenging complex samples without any pre-treatment.

Pixel detector modules using MCM-D technology

CERN Document Server

Grah, C

2001-01-01

For the upcoming ATLAS-experiment at CERN it is planned to build a large area pixel detector, providing more than 100*10/sup 6/ sensor cells. For the innermost layer, the B-physics layer, it is planned to use MCM-D technology to perform the signal interconnections and power distribution on the modules. Focus of this paper is to give an introduction to this technology and present measurements on single chip MCM-D assemblies and a full scale MCM-D module prototype. (10 refs).

On the use of OSL of wire-bond chip card modules for retrospective and accident dosimetry

Energy Technology Data Exchange (ETDEWEB)

Woda, Clemens [Helmholtz Zentrum Muenchen - German Research Centre for Environmental Health, Institute of Radiation Protection, Ingolstaedter Landstrasse 1, D-85764 Neuherberg (Germany)], E-mail: clemens.woda@helmholtz-muenchen.de; Spoettl, Thomas [Infineon Technologies AG, Wernerwerkstrasse 1, D-93049 Regensburg (Germany)

2009-05-15

The potential of optically stimulated luminescence of wire-bond chip card modules, used in health insurance, ID, cash and credit cards for retrospective and accident dosimetry is investigated. Chip card modules obtained directly from the producer, using a widely spread UV-cured epoxy product for encapsulation, are used as basis for the study. The radiation sensitivity is due to silica grains added to the epoxy for controlling the thixotropic properties. Luminescence properties are complex due to the presumed thermo-optical release of electrons from the epoxy and transfer into the silica. Best results and highest sensitivity are obtained by using no or only low preheat treatments. A high degree of fading of the OSL signal during storage at room temperature is observed, which is tentatively explained by the superposition of thermal decay of shallow OSL traps and athermal (anomalous) decay of deeper OSL traps. The dose response of the OSL signal shows exponentially saturating behaviour, with saturation doses of 77 Gy or 9.6 Gy, depending on pretreatment. Dose recovery tests show that given doses can be recovered within a deviation of {+-}14%, if measured signals are corrected for fading. The minimum detectable dose is estimated at {approx}3 mGy, {approx}10 mGy and {approx}20 mGy for readouts immediately, 1 day and 10 days after exposure, respectively.

On the use of OSL of wire-bond chip card modules for retrospective and accident dosimetry

International Nuclear Information System (INIS)

Woda, Clemens; Spoettl, Thomas

2009-01-01

The potential of optically stimulated luminescence of wire-bond chip card modules, used in health insurance, ID, cash and credit cards for retrospective and accident dosimetry is investigated. Chip card modules obtained directly from the producer, using a widely spread UV-cured epoxy product for encapsulation, are used as basis for the study. The radiation sensitivity is due to silica grains added to the epoxy for controlling the thixotropic properties. Luminescence properties are complex due to the presumed thermo-optical release of electrons from the epoxy and transfer into the silica. Best results and highest sensitivity are obtained by using no or only low preheat treatments. A high degree of fading of the OSL signal during storage at room temperature is observed, which is tentatively explained by the superposition of thermal decay of shallow OSL traps and athermal (anomalous) decay of deeper OSL traps. The dose response of the OSL signal shows exponentially saturating behaviour, with saturation doses of 77 Gy or 9.6 Gy, depending on pretreatment. Dose recovery tests show that given doses can be recovered within a deviation of ±14%, if measured signals are corrected for fading. The minimum detectable dose is estimated at ∼3 mGy, ∼10 mGy and ∼20 mGy for readouts immediately, 1 day and 10 days after exposure, respectively.

Hemispherical power asymmetry from scale-dependent modulated reheating

International Nuclear Information System (INIS)

McDonald, John

2013-01-01

We propose a new model for the hemispherical power asymmetry of the CMB based on modulated reheating. Non-Gaussianity from modulated reheating can be small enough to satisfy the bound from Planck if the dominant modulation of the inflaton decay rate is linear in the modulating field σ. σ must then acquire a spatially-modulated power spectrum with a red scale-dependence. This can be achieved if the primordial perturbation of σ is generated via tachyonic growth of a complex scalar field. Modulated reheating due to σ then produces a spatially modulated and scale-dependent sub-dominant contribution to the adiabatic density perturbation. We show that it is possible to account for the observed asymmetry while remaining consistent with bounds from quasar number counts, non-Gaussianity and the CMB temperature quadupole. The model predicts that the adiabatic perturbation spectral index and its running will be modified by the modulated reheating component

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

Science.gov (United States)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Narrow linewidth diode laser modules for quantum optical sensor applications in the field and in space

Science.gov (United States)

Wicht, A.; Bawamia, A.; Krüger, M.; Kürbis, Ch.; Schiemangk, M.; Smol, R.; Peters, A.; Tränkle, G.

2017-02-01

We present the status of our efforts to develop very compact and robust diode laser modules specifically suited for quantum optics experiments in the field and in space. The paper describes why hybrid micro-integration and GaAs-diode laser technology is best suited to meet the needs of such applications. The electro-optical performance achieved with hybrid micro-integrated, medium linewidth, high power distributed-feedback master-oscillator-power-amplifier modules and with medium power, narrow linewidth extended cavity diode lasers emitting at 767 nm and 780 nm are briefly described and the status of space relevant stress tests and space heritage is summarized. We also describe the performance of an ECDL operating at 1070 nm. Further, a novel and versatile technology platform is introduced that allows for integration of any type of laser system or electro-optical module that can be constructed from two GaAs chips. This facilitates, for the first time, hybrid micro-integration, e.g. of extended cavity diode laser master-oscillator-poweramplifier modules, of dual-stage optical amplifiers, or of lasers with integrated, chip-based phase modulator. As an example we describe the implementation of an ECDL-MOPA designed for experiments on ultra-cold rubidium and potassium atoms on board a sounding rocket and give basic performance parameters.

The ALICE Silicon Pixel Detector System (SPD)

CERN Document Server

Kluge, A; Antinori, Federico; Burns, M; Cali, I A; Campbell, M; Caselle, M; Ceresa, S; Dima, R; Elias, D; Fabris, D; Krivda, Marian; Librizzi, F; Manzari, Vito; Morel, M; Moretto, Sandra; Osmic, F; Pappalardo, G S; Pepato, Adriano; Pulvirenti, A; Riedler, P; Riggi, F; Santoro, R; Stefanini, G; Torcato De Matos, C; Turrisi, R; Tydesjo, H; Viesti, G; PH-EP

2007-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 detector modules (half-staves) each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8192 active cells, so that the total number of pixel cells in the SPD is ≈ 107. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget and detector module dimensions are very demanding.

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

Energy Technology Data Exchange (ETDEWEB)

Aglieri Rinella, Gianluca, E-mail: gianluca.aglieri.rinella@cern.ch

2017-02-11

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10{sup −5} and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm{sup 2} for the application in the Inner Barrel Layers and below 20 mW/cm{sup 2} for the Outer Barrel Layers, where the occupancy is lower. This contribution describes the architecture and the main features of the final ALPIDE chip, planned for submission at the beginning of 2016. Early results from the experimental qualification of full scale prototype predecessors are also reported. - Highlights: • The ALPIDE chip, an innovative CMOS pixel particle detector is described. • It achieves excellent detection performance figures and very low power consumption. • The characterization of prototypes confirms the achievement of the specifications.

Automating dChip: toward reproducible sharing of microarray data analysis

Directory of Open Access Journals (Sweden)

Li Cheng

2008-05-01

Full Text Available Abstract Background During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the widely used dChip as a microarray analysis software package accessible to both biologist and data analysts. However, challenges arise when dChip users want to analyze large number of arrays automatically and share data analysis procedures and parameters. Improvement is also needed when the dChip user support team tries to identify the causes of reported analysis errors or bugs from users. Results We report here implementation and application of the dChip automation module. Through this module, dChip automation files can be created to include menu steps, parameters, and data viewpoints to run automatically. A data-packaging function allows convenient transfer from one user to another of the dChip software, microarray data, and analysis procedures, so that the second user can reproduce the entire analysis session of the first user. An analysis report file can also be generated during an automated run, including analysis logs, user comments, and viewpoint screenshots. Conclusion The dChip automation module is a step toward reproducible research, and it can prompt a more convenient and reproducible mechanism for sharing microarray software, data, and analysis procedures and results. Automation data packages can also be used as publication supplements. Similar automation mechanisms could be valuable to the research community if implemented in other genomics and bioinformatics software packages.

Driving the SID chip: Assembly language, composition, and sound design for the C64

Directory of Open Access Journals (Sweden)

James Newman

2017-12-01

Full Text Available The MOS6581, more commonly known as the Sound Interface Device, or SID chip, was the sonic heart of the Commodore 64 home computer. By considering the chip’s development, specification, uses and creative abuses by composers and programmers, alongside its continuing legacy, this paper argues that, more than any other device, the SID chip is responsible for shaping the sound of videogame music. Compared with the brutal atonality of chips such as Atari’s TIA, the SID chip offers a complex 3-channel synthesizer with dynamic waveform selection, per-channel ADSR envelopes, multi-mode filter, ring and cross modulation. However, while the specification is sophisticated, the exploitation of the vagaries and imperfections of the chip are just as significant to its sonic character. As such, the compositional, sound design and programming techniques developed by 1980s composer-coders like Rob Hubbard and Martin Galway are central in defining the distinctive sound of C64 gameplay. Exploring the affordances of the chip and the distinctive ways they were harnessed, the argument of this paper centers on the inexorable link between the technological and the musical. Crucially, composers like Hubbard et al. developed their own bespoke low-level drivers to interface with the SID chip to create pseudo-polyphony through rapid arpeggiation and channel sharing, drum synthesis through waveform manipulation, portamento, and even sample playback. This paper analyses the indivisibility of sound design, synthesis and composition in the birth of these musical forms and aesthetics, and assesses their impact on what would go on to be defined as chiptunes.

SUPPORT CARD FOR THE FORWARD SCT MODULE

CERN Document Server

Greenall, A

2002-01-01

Previously in the development and testing stage of ATLAS SCT Forward modules support cards have been used which interface the module to the DAQ by using only the Redundant inputs for the module configuration and the 'spying' of the ABCD Master chip(s) data. As module development has matured there is now a necessity to be able to test modules in the laboratory using also their Primary input/output data routes i.e. using the optical chips DORIC [1] and VDC [2] but without the need of optical fibres. A Forward Kapton Support Card, FKSC, has been developed so that both Primary and Redundant data routes can be used for module testing.

Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

International Nuclear Information System (INIS)

Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

2011-01-01

Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

The FE-I4 Pixel Readout Chip and the IBL Module

Energy Technology Data Exchange (ETDEWEB)

Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

2012-05-01

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

Multi-chamber and multi-layer thiol-ene microchip for cell culture

DEFF Research Database (Denmark)

Tan, H. Y.; Hemmingsen, Mette; Lafleur, Josiane P.

2014-01-01

We present a multi-layer and multi-chamber microfluidic chip fabricated using two different thiol-ene mixtures. Sandwiched between the thiol-ene chip layers is a commercially available membrane whose morphology has been altered with coatings of thiol-ene mixtures. Experiments have been conducted ...... with the microchip and shown that the fabricated microchip is suitable for long term cell culture....

Variable self-powered light detection CMOS chip with real-time adaptive tracking digital output based on a novel on-chip sensor.

Science.gov (United States)

Wang, HongYi; Fan, Youyou; Lu, Zhijian; Luo, Tao; Fu, Houqiang; Song, Hongjiang; Zhao, Yuji; Christen, Jennifer Blain

2017-10-02

This paper provides a solution for a self-powered light direction detection with digitized output. Light direction sensors, energy harvesting photodiodes, real-time adaptive tracking digital output unit and other necessary circuits are integrated on a single chip based on a standard 0.18 µm CMOS process. Light direction sensors proposed have an accuracy of 1.8 degree over a 120 degree range. In order to improve the accuracy, a compensation circuit is presented for photodiodes' forward currents. The actual measurement precision of output is approximately 7 ENOB. Besides that, an adaptive under voltage protection circuit is designed for variable supply power which may undulate with temperature and process.

A Low-Cost Production Method of FeSi2 Power Generation Thermoelectric Modules

Science.gov (United States)

Inoue, Hiroyuki; Kobayashi, Takahide; Kato, Masahiko; Yoneda, Seiji

2016-03-01

A method is proposed to reduce the production cost of power generation thermoelectric modules. FeSi2 is employed as the thermoelectric material because of its low cost, low environmental load, and oxidation resistance. The raw materials were prepared in the composition of Fe0.96Si2.1Co0.04 for n-type and Fe0.92Si2.1Mn0.08 for p-type, which were added with 0.5 wt.% Cu as the starting materials. They were sintered without pressure at 1446 K to be formed into elements. The Seebeck coefficient and resistivity at room temperature were determined to be -182 μV/K and 0.13 mΩm for n-type, and 338 μV/K and 1.13 mΩm for p-type, respectively. The brazing conditions of the direct joining between the element and the solder were examined. Pastes of BNi-6, BNi-7 or TB-608T were tried as the solder. TB-608T was useable for metallizing of insulation substrates and joining of thermoelectric elements in order to manufacture thermoelectric modules. The joining strength was determined to be 50 MPa between the alumina plate and the elements. No mechanical failure was observed in the modules after repetition of 10 or more exposures to a heat source of 670 K. No change was found in the internal resistance. The present production method will provide modules with high durability and low production cost, which will enable high-power multi-stage cascade modules at a reasonable cost.

Antiseptic solutions modulate the paracrine-like activity of bone chips: differential impact of chlorhexidine and sodium hypochlorite.

Science.gov (United States)

Sawada, Kosaku; Caballé-Serrano, Jordi; Bosshardt, Dieter D; Schaller, Benoit; Miron, Richard J; Buser, Daniel; Gruber, Reinhard

2015-09-01

Chemical decontamination increases the availability of bone grafts; however, it remains unclear whether antiseptic processing changes the biological activity of bone. Bone chips were incubated with four different antiseptic solutions including (1) povidone-iodine (0.5%), (2) chlorhexidine diguluconate (0.2%), (3) hydrogen peroxide (1%) and (4) sodium hypochlorite (0.25%). After 10 min. of incubation, changes in the capacity of the bone-conditioned medium (BCM) to modulate gene expression of gingival fibroblasts was investigated. Conditioned medium obtained from freshly prepared bone chips increased the expression of TGF-β target genes interleukin 11 (IL11), proteoglycan4 (PRG4), NADPH oxidase 4 (NOX4), and decreased the expression of adrenomedullin (ADM), and pentraxin 3 (PTX3) in gingival fibroblasts. Incubation of bone chips with 0.2% chlorhexidine, followed by vigorously washing resulted in a BCM with even higher expression of IL11, PRG4 and NOX4. These findings were also detected with a decrease in cell viability and an activation of apoptosis signalling. Chlorhexidine alone, at low concentrations, increased IL11, PRG4 and NOX4 expression, independent of the TGF-β receptor I kinase activity. In contrast, 0.25% sodium hypochlorite almost entirely abolished the activity of BCM, whereas the other two antiseptic solutions, 1% hydrogen peroxide and 0.5% povidone-iodine, had relatively no impact respectively. These in vitro findings demonstrate that incubation of bone chips with chlorhexidine differentially affects the activity of the respective BCM compared to the other antiseptic solutions. The data further suggest that the main effects are caused by chlorhexidine remaining in the BCM after repeated washing of the bone chips. © 2015 John Wiley & Sons A/S. Published by John Wiley & Sons Ltd.

Dimmable electronic ballasts by variable power density modulation technique

Science.gov (United States)

Borekci, Selim; Kesler, Selami

2014-11-01

Dimming can be accomplished commonly by switching frequency and pulse density modulation techniques and a variable inductor. In this study, a variable power density modulation (VPDM) control technique is proposed for dimming applications. A fluorescent lamp is operated in several states to meet the desired lamp power in a modulation period. The proposed technique has the same advantages of magnetic dimming topologies have. In addition, a unique and flexible control technique can be achieved. A prototype dimmable electronic ballast is built and experiments related to it have been conducted. As a result, a 36WT8 fluorescent lamp can be driven for a desired lamp power from several alternatives without modulating the switching frequency.

Development of control system for multi-converter high voltage power supply using programmable SoC

International Nuclear Information System (INIS)

Dave, Rasesh; Singh, N.P.; Thakar, Aruna; Dhola, Hitesh; Gajjar, Sandip; Parmar, Darshan Kumar; Baruah, Ujjwal Kumar; Dharangutti, Jagruti; Zaveri, Tanish

2015-01-01

Multi-converter based High Voltage Power Supplies (HVPSs) find application in multi-megawatt accelerators, RF systems. Control system for HVPS must be a combination of superior parallel processing, real time performance, fast computation and versatile connectivity. The hardware platform is expected to be robust, easily scalable for future developments without any cost overhead. Typical HVPS control mechanism involves communication, generation of precise control signals/pulses for few hundred Nos of chopper and closed loop control in microsecond range for regulated output. Such kind of requirements can be met with Zynq All Programmable SoC, which is a combination of Dual core ARM Cortex A-9 Processing System (PS) and Xilinx 7 series FPGA based Programmable Logic (PL). Deterministic functions of power supply control system such as generation of control signals with precise inter-channel delay of nanosecond range and communication with individual chopper at 100kbps can be implemented on PL. PS should implement corrective tasks based on field feedback received from individual chopper, user interface and OS management that allows to take full advantage of system capabilities. PS and PL are connected with on-chip AXI-4 interface with low latency and higher bandwidth through 9 AXI ports. Typically PS boots first, this ensures secure booting and prevents external environment from tampering PL. This paper describes development of control system on Zynq All Programmable SoC for HVPS. (author)

Differential pulse amplitude modulation for multiple-input single-output OWVLC

Science.gov (United States)

Yang, S. H.; Kwon, D. H.; Kim, S. J.; Son, Y. H.; Han, S. K.

2015-01-01

White light-emitting diodes (LEDs) are widely used for lighting due to their energy efficiency, eco-friendly, and small size than previously light sources such as incandescent, fluorescent bulbs and so on. Optical wireless visible light communication (OWVLC) based on LED merges lighting and communications in applications such as indoor lighting, traffic signals, vehicles, and underwater communications because LED can be easily modulated. However, physical bandwidth of LED is limited about several MHz by slow time constant of the phosphor and characteristics of device. Therefore, using the simplest modulation format which is non-return-zero on-off-keying (NRZ-OOK), the data rate reaches only to dozens Mbit/s. Thus, to improve the transmission capacity, optical filtering and pre-, post-equalizer are adapted. Also, high-speed wireless connectivity is implemented using spectrally efficient modulation methods: orthogonal frequency division multiplexing (OFDM) or discrete multi-tone (DMT). However, these modulation methods need additional digital signal processing such as FFT and IFFT, thus complexity of transmitter and receiver is increasing. To reduce the complexity of transmitter and receiver, we proposed a novel modulation scheme which is named differential pulse amplitude modulation. The proposed modulation scheme transmits different NRZ-OOK signals with same amplitude and unit time delay using each LED chip, respectively. The `N' parallel signals from LEDs are overlapped and directly detected at optical receiver. Received signal is demodulated by power difference between unit time slots. The proposed scheme can overcome the bandwidth limitation of LEDs and data rate can be improved according to number of LEDs without complex digital signal processing.

Scalable fabrication of high-power graphene micro-supercapacitors for flexible and on-chip energy storage

Science.gov (United States)

El-Kady, Maher F.; Kaner, Richard B.

2013-02-01

The rapid development of miniaturized electronic devices has increased the demand for compact on-chip energy storage. Microscale supercapacitors have great potential to complement or replace batteries and electrolytic capacitors in a variety of applications. However, conventional micro-fabrication techniques have proven to be cumbersome in building cost-effective micro-devices, thus limiting their widespread application. Here we demonstrate a scalable fabrication of graphene micro-supercapacitors over large areas by direct laser writing on graphite oxide films using a standard LightScribe DVD burner. More than 100 micro-supercapacitors can be produced on a single disc in 30 min or less. The devices are built on flexible substrates for flexible electronics and on-chip uses that can be integrated with MEMS or CMOS in a single chip. Remarkably, miniaturizing the devices to the microscale results in enhanced charge-storage capacity and rate capability. These micro-supercapacitors demonstrate a power density of ~200 W cm-3, which is among the highest values achieved for any supercapacitor.

Optical lattice on an atom chip

DEFF Research Database (Denmark)

Gallego, D.; Hofferberth, S.; Schumm, Thorsten

2009-01-01

Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

Power-law modulation of the scalar power spectrum from a heavy field with a monomial potential

Science.gov (United States)

Huang, Qing-Guo; Pi, Shi

2018-04-01

The effects of heavy fields modulate the scalar power spectrum during inflation. We analytically calculate the modulations of the scalar power spectrum from a heavy field with a separable monomial potential, i.e. V(phi)~ phin. In general the modulation is characterized by a power-law oscillation which is reduced to the logarithmic oscillation in the case of n=2.

The ALPIDE pixel sensor chip for the upgrade of the ALICE Inner Tracking System

CERN Document Server

Aglieri Rinella, Gianluca

2017-01-01

The ALPIDE chip is a CMOS Monolithic Active Pixel Sensor being developed for the Upgrade of the ITS of the ALICE experiment at the CERN Large Hadron Collider. The ALPIDE chip is implemented with a 180 nm CMOS Imaging Process and fabricated on substrates with a high-resistivity epitaxial layer. It measures 15 mm×30 mm and contains a matrix of 512×1024 pixels with in-pixel amplification, shaping, discrimination and multi-event buffering. The readout of the sensitive matrix is hit driven. There is no signaling activity over the matrix if there are no hits to read out and power consumption is proportional to the occupancy. The sensor meets the experimental requirements of detection efficiency above 99%, fake-hit probability below 10−5 and a spatial resolution of 5 μm. The capability to read out Pb–Pb interactions at 100 kHz is provided. The power density of the ALPIDE chip is projected to be less than 35 mW/cm2 for the application in the Inner Barrel Layers and below 20 mW/cm2 for the Outer Barrel Layers, ...

160 Gbit/s optical packet switching using a silicon chip

DEFF Research Database (Denmark)

Hu, Hao; Ji, Hua; Galili, Michael

2012-01-01

We have successfully demonstrated 160 Gbit/s all-optical packet switching based on cross-phase modulation using a silicon chip. Error free performance is achieved for the 4-to-1 switched 160 Gbit/s packet.......We have successfully demonstrated 160 Gbit/s all-optical packet switching based on cross-phase modulation using a silicon chip. Error free performance is achieved for the 4-to-1 switched 160 Gbit/s packet....

Pulse Power Modulator development for the CLIC Damping Ring Kickers

CERN Document Server

Holma, Janne

2012-01-01

The Compact Linear Collider (CLIC) study is exploring the scheme for an electron-positron collider with high luminosity (10-34 – 10-35 cm-2s-1) and a nominal centre-of-mass energy of 3 TeV: CLIC would complement LHC physics in the multi-TeV range. The CLIC design relies on Pre-Damping Rings (PDR) and Damping Rings (DR) to achieve the very low emittance, through synchrotron radiation, needed for the luminosity requirements of CLIC. To limit the beam emittance blow-up due to oscillations, the pulse power modulators for the DR kickers must provide extremely flat, high-voltage pulses: the 2 GHz specification called for a 160 ns duration flat-top of 12.5 kV, 250 A, with a combined ripple and droop of not more than ±0.02 %. In order to meet these demanding specifications, a combination of broadband impedance matching, optimized electrical circuit layout and advanced control techniques is required. A solid-state modulator, the inductive adder, is the most promising approach to meeting the demanding specifications...

Modeling of a Stacked Power Module for Parasitic Inductance Extraction

Science.gov (United States)

2017-09-15

ARL-TR-8138 ● SEP 2017 US Army Research Laboratory Modeling of a Stacked Power Module for Parasitic Inductance Extraction by...not return it to the originator. ARL-TR-8138 ● SEP 2017 US Army Research Laboratory Modeling of a Stacked Power Module for... Power Module for Parasitic Inductance Extraction 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) Steven Kaplan

Resonator-Based Silicon Electro-Optic Modulator with Low Power Consumption

Science.gov (United States)

Xin, Maoqing; Danner, Aaron J.; Eng Png, Ching; Thor Lim, Soon

2009-04-01

This paper demonstrates, via simulation, an electro-optic modulator based on a subwavelength Fabry-Perot resonator cavity with low power consumption of 86 µW/µm. This is, to the best of our knowledge, the lowest power reported for silicon photonic bandgap modulators. The device is modulated at a doped p-i-n junction overlapping the cavity in a silicon waveguide perforated with etched holes, with the doping area optimized for minimum power consumption. The surface area of the entire device is only 2.1 µm2, which compares favorably to other silicon-based modulators. A modulation speed of at least 300 MHz is detected from the electrical simulator after sidewall doping is introduced which is suitable for sensing or fiber to the home (FTTH) technologies, where speed can be traded for low cost and power consumption. The device does not rely on ultra-high Q, and could serve as a sensor, modulator, or passive filter with built-in calibration.

Radio frequency powering of microelectronic sensor modules

Energy Technology Data Exchange (ETDEWEB)

Boegel, Gerd vom; Meyer, Frederic; Kemmerling, Martin [Fraunhofer-Institut fuer Mikroelektronische Schaltungen und Systeme, Duisburg (Germany)

2013-03-01

In RFID applications the power supply of transponders via electromagnetic field is state-of-the-art. In this presentation the use of electromagnetic energy will be discussed for the operation of sensor modules. Starting with the question, whether the omnipresent radiation from power supply networks, radio transmitters, and mobile phone base stations is useable (energy harvesting), the feasibility of the operation of self-sufficient sensor modules is explained. Ancillary conditions of typical applications (e.g. operating range) and technology are considered. (orig.)

Multi-band microwave photonic satellite repeater scheme employing intensity Mach-Zehnder modulators

Institute of Scientific and Technical Information of China (English)

Yin Jie; Dong Tao; Zhang Bin; Hao Yan; Cao Guixing; Cheng Zijing; Xu Kun; Zhou Yue; Dai Jian

2017-01-01

To solve the satellite repeater's flexible and wideband frequency conversion problem,we propose a novel microwave photonic repeater system,which can convert the upload signal's carrier to six different frequencies.The scheme employs one 20 GHz bandwidth dual-drive Mach-Zehnder modulator (MZM) and two 10 GHz bandwidth MZMs.The basic principle of this scheme is filtering out two optical sidebands after the optical carrier suppression (OCS) modulation and combining two sidebands modulated by the input radio frequency (RF) signal.This structure can realize simultaneous multi-band frequency conversion with only one frequency-fixed microwave source and prevent generating harmful interference sidebands by using two corresponding optical filters after optical modulation.In the simulation,one C-band signal of 6 GHz carrier can be successfully converted to 12 GHz (Ku-band),28 GHz,34 GHz,40 GHz,46 GHz (Ka-band) and 52 GHz (V-band),which can be an attractive method to realize multi-band microwave photonic satellite repeater.Alternatively,the scheme can be configured to generate multi-band local oscillators (LOs) for widely satellite onboard clock distribution when the input RF signal is replaced by the internal clock source.

Staves and Petals: Multi-module Local Support Structures of the ATLAS ITk Strips Upgrade

CERN Document Server

Rodriguez Rodriguez, Daniel; The ATLAS collaboration

2017-01-01

The ATLAS Inner Tracker (ITk) is an all-silicon tracker that will replace the existing inner detector at the Phase-II Upgrade of ATLAS. The outermost part of the tracker consists of the strips tracker, in which the sensor elements consist of silicon micro-strip sensors with strip lengths varying from 1.7 to up to 10 cm. The current design is part of the ATLAS ITk Strip Detector Technical Design Report (TDR) and envisions a four-layer barrel and two six-disk end-cap regions. The sensor and readout units (``modules'') are directly glued onto multi-module, low-mass, high thermal performance carbon fibre structures, called “staves” for the barrel and ``petals'' for the end-cap. They provide cooling, power, data and control lines to the modules with a minimal amount of external services. An extensive prototyping program was put in place over the last years to fully characterise these structures mechanically, thermally, and electrically. Thermo-mechanical stave and petal prototypes have recently been built and ...

Multi Carrier Modulation Audio Power Amplifier with Programmable Logic

DEFF Research Database (Denmark)

Christiansen, Theis; Andersen, Toke Meyer; Knott, Arnold

2009-01-01

While switch-mode audio power amplifiers allow compact implementations and high output power levels due to their high power efficiency, they are very well known for creating electromagnetic interference (EMI) with other electronic equipment. To lower the EMI of switch-mode (class D) audio power a...

Optical continuum generation on a silicon chip

Science.gov (United States)

Jalali, Bahram; Boyraz, Ozdal; Koonath, Prakash; Raghunathan, Varun; Indukuri, Tejaswi; Dimitropoulos, Dimitri

2005-08-01

Although the Raman effect is nearly two orders of magnitude stronger than the electronic Kerr nonlinearity in silicon, under pulsed operation regime where the pulse width is shorter than the phonon response time, Raman effect is suppressed and Kerr nonlinearity dominates. Continuum generation, made possible by the non-resonant Kerr nonlinearity, offers a technologically and economically appealing path to WDM communication at the inter-chip or intra-chip levels. We have studied this phenomenon experimentally and theoretically. Experimentally, a 2 fold spectral broadening is obtained by launching ~4ps optical pulses with 2.2GW/cm2 peak power into a conventional silicon waveguide. Theoretical calculations, that include the effect of two-photon-absorption, free carrier absorption and refractive index change indicate that up to >30 times spectral broadening is achievable in an optimized device. The broadening is due to self phase modulation and saturates due to two photon absorption. Additionally, we find that free carrier dynamics also contributes to the spectral broadening and cause the overall spectrum to be asymmetric with respect to the pump wavelength.

Universal lab-on-a-chip platform for complex, perfused 3D cell cultures

Science.gov (United States)

Sonntag, F.; Schmieder, F.; Ströbel, J.; Grünzner, S.; Busek, M.; Günther, K.; Steege, T.; Polk, C.; Klotzbach, U.

2016-03-01

The miniaturization, rapid prototyping and automation of lab-on-a-chip technology play nowadays a very important role. Lab-on-a-chip technology is successfully implemented not only for environmental analysis and medical diagnostics, but also as replacement of animals used for the testing of substances in the pharmaceutical and cosmetics industries. For that purpose the Fraunhofer IWS and partners developed a lab-on-a-chip platform for perfused cell-based assays in the last years, which includes different micropumps, valves, channels, reservoirs and customized cell culture modules. This technology is already implemented for the characterization of different human cell cultures and organoids, like skin, liver, endothelium, hair follicle and nephron. The advanced universal lab-on-a-chip platform for complex, perfused 3D cell cultures is divided into a multilayer basic chip with integrated micropump and application-specific 3D printed cell culture modules. Moreover a technology for surface modification of the printed cell culture modules by laser micro structuring and a complex and flexibly programmable controlling device based on an embedded Linux system was developed. A universal lab-on-a-chip platform with an optional oxygenator and a cell culture module for cubic scaffolds as well as first cell culture experiments within the cell culture device will be presented. The module is designed for direct interaction with robotic dispenser systems. This offers the opportunity to combine direct organ printing of cells and scaffolds with the microfluidic cell culture module. The characterization of the developed system was done by means of Micro-Particle Image Velocimetry (μPIV) and an optical oxygen measuring system.

Power adaptive multi-filter carrierless amplitude and phase access scheme for visible light communication network

Science.gov (United States)

Li, Wei; Huang, Zhitong; Li, Haoyue; Ji, Yuefeng

2018-04-01

Visible light communication (VLC) is a promising candidate for short-range broadband access due to its integration of advantages for both optical communication and wireless communication, whereas multi-user access is a key problem because of the intra-cell and inter-cell interferences. In addition, the non-flat channel effect results in higher losses for users in high frequency bands, which leads to unfair qualities. To solve those issues, we propose a power adaptive multi-filter carrierless amplitude and phase access (PA-MF-CAPA) scheme, and in the first step of this scheme, the MF-CAPA scheme utilizing multiple filters as different CAP dimensions is used to realize multi-user access. The character of orthogonality among the filters in different dimensions can mitigate the effect of intra-cell and inter-cell interferences. Moreover, the MF-CAPA scheme provides different channels modulated on the same frequency bands, which further increases the transmission rate. Then, the power adaptive procedure based on MF-CAPA scheme is presented to realize quality fairness. As demonstrated in our experiments, the MF-CAPA scheme yields an improved throughput compared with multi-band CAP access scheme, and the PA-MF-CAPA scheme enhances the quality fairness and further improves the throughput compared with the MF-CAPA scheme.

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

Directory of Open Access Journals (Sweden)

Tingyou Lin

2017-06-01

Full Text Available This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs. An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm2. The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.

PS-Modules over Ore Extensions and Skew Generalized Power Series Rings

Directory of Open Access Journals (Sweden)

Refaat M. Salem

2015-01-01

Full Text Available A right R-module MR is called a PS-module if its socle, SocMR, is projective. We investigate PS-modules over Ore extension and skew generalized power series extension. Let R be an associative ring with identity, MR a unitary right R-module, O=Rx;α,δ Ore extension, MxO a right O-module, S,≤ a strictly ordered additive monoid, ω:S→EndR a monoid homomorphism, A=RS,≤,ω the skew generalized power series ring, and BA=MS,≤RS,≤, ω the skew generalized power series module. Then, under some certain conditions, we prove the following: (1 If MR is a right PS-module, then MxO is a right PS-module. (2 If MR is a right PS-module, then BA is a right PS-module.

Performance comparison of binary modulation schemes for visible light communication

KAUST Repository

Park, Kihong; Li, Changping; Alouini, Mohamed-Slim

2015-01-01

communication with dimming control. We also propose a novel slope-based modulation called differential chip slope modulation (DCSM) and develop a chip-based hard-decision receiver to demodulate the resulting signal, detect the chip sequence, and decode the input

Power electronic modules design and manufacture

CERN Document Server

Sheng, William W

2004-01-01

IntroductionSelection ProcedureMaterialsInsulating Substrate and MetallizationBase PlateBonding MaterialPower Interconnection and TerminalEncapsulantPlastic Case and Cover Manufacturing of Power IGBT ModulesManufacturing Process Process Control/Long-Term ReliabilityManufacturing FacilitiesManufacturing Flow Charts DesignThermal ManagementCircuit PartitioningDesign Guidelines and ConsiderationsThermal Results of Different Samples

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

Directory of Open Access Journals (Sweden)

Diwei He

2015-07-01

Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

Science.gov (United States)

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

Network module detection: Affinity search technique with the multi-node topological overlap measure.

Science.gov (United States)

Li, Ai; Horvath, Steve

2009-07-20

Many clustering procedures only allow the user to input a pairwise dissimilarity or distance measure between objects. We propose a clustering method that can input a multi-point dissimilarity measure d(i1, i2, ..., iP) where the number of points P can be larger than 2. The work is motivated by gene network analysis where clusters correspond to modules of highly interconnected nodes. Here, we define modules as clusters of network nodes with high multi-node topological overlap. The topological overlap measure is a robust measure of interconnectedness which is based on shared network neighbors. In previous work, we have shown that the multi-node topological overlap measure yields biologically meaningful results when used as input of network neighborhood analysis. We adapt network neighborhood analysis for the use of module detection. We propose the Module Affinity Search Technique (MAST), which is a generalized version of the Cluster Affinity Search Technique (CAST). MAST can accommodate a multi-node dissimilarity measure. Clusters grow around user-defined or automatically chosen seeds (e.g. hub nodes). We propose both local and global cluster growth stopping rules. We use several simulations and a gene co-expression network application to argue that the MAST approach leads to biologically meaningful results. We compare MAST with hierarchical clustering and partitioning around medoid clustering. Our flexible module detection method is implemented in the MTOM software which can be downloaded from the following webpage: http://www.genetics.ucla.edu/labs/horvath/MTOM/

Multi-hit time-to-amplitude CAMAC module (MTAC)

International Nuclear Information System (INIS)

Kang, H.

1980-10-01

A Multi-Hit Time-to-Amplitude Module (MTAC) for the SLAC Mark III drift chamber system has been designed to measure drift time by converting time-proportional chamber signals into analog levels, and converting the analog data by slow readout via a semi-autonomous controller in a CAMAC crate. The single width CAMAC module has 16 wire channels, each with a 4-hit capacity. An externally generated common start initiates an internal precision ramp voltage which is then sampled using a novel shift register gating scheme and CMOS sampling switches. The detailed design and performance specifications are described

The NutriChip project--translating technology into nutritional knowledge.

Science.gov (United States)

Vergères, Guy; Bogicevic, Biljana; Buri, Caroline; Carrara, Sandro; Chollet, Magali; Corbino-Giunta, Linda; Egger, Lotti; Gille, Doreen; Kopf-Bolanz, Katrin; Laederach, Kurt; Portmann, Reto; Ramadan, Qasem; Ramsden, Jeremy; Schwander, Flurina; Silacci, Paolo; Walther, Barbara; Gijs, Martin

2012-09-01

Advances in food transformation have dramatically increased the diversity of products on the market and, consequently, exposed consumers to a complex spectrum of bioactive nutrients whose potential risks and benefits have mostly not been confidently demonstrated. Therefore, tools are needed to efficiently screen products for selected physiological properties before they enter the market. NutriChip is an interdisciplinary modular project funded by the Swiss programme Nano-Tera, which groups scientists from several areas of research with the aim of developing analytical strategies that will enable functional screening of foods. The project focuses on postprandial inflammatory stress, which potentially contributes to the development of chronic inflammatory diseases. The first module of the NutriChip project is composed of three in vitro biochemical steps that mimic the digestion process, intestinal absorption, and subsequent modulation of immune cells by the bioavailable nutrients. The second module is a miniaturised form of the first module (gut-on-a-chip) that integrates a microfluidic-based cell co-culture system and super-resolution imaging technologies to provide a physiologically relevant fluid flow environment and allows sensitive real-time analysis of the products screened in vitro. The third module aims at validating the in vitro screening model by assessing the nutritional properties of selected food products in humans. Because of the immunomodulatory properties of milk as well as its amenability to technological transformation, dairy products have been selected as model foods. The NutriChip project reflects the opening of food and nutrition sciences to state-of-the-art technologies, a key step in the translation of transdisciplinary knowledge into nutritional advice.

Power module for an experimental picosatellite Cubesat type

Directory of Open Access Journals (Sweden)

Javier Castro Avellaneda

2016-06-01

Full Text Available This article describes a power module for picosatellite following CubeSat standard requirements [1,2,3,13]. The Power Module project is developed in four phases: study, design, implementation and testing. In the study phase of the theoretical framework and preliminary designs made in the Universidad Distrital [4,5] and other CubeSat developed in the world is reviewed, also investigates existing technologies and components in the market and its affordability. The design phase involves analysis of the system and using a computer program designed to generate the necessary hardware. The ultimate goal is to obtain a functional power module and work in space environment conditions in which the picosatellite keep his focus on an application in telemedicine, with a payload that would become the telecommunications system mission.

Power Inverter Topologies for Photovoltaic Modules - A Review

DEFF Research Database (Denmark)

Kjær, Søren Bækhøj; Pedersen, John Kim; Blaabjerg, Frede

2002-01-01

This review-paper focuses on the latest development of inverters for photovoltaic AC-Modules. The power range for these inverters is usually within 90 Watt to 500 Watt, which covers the most commercial photovoltaic-modules. Self-commutated inverters have replaced the grid-commutated ones. The same...... is true for the bulky low-frequency transformers versus the high-frequency transformers, which are used to adapt the voltage level. The AC-Module provides a modular design and a flexible behaviour in various grid conditions. It hereby opens the market for photovoltaic-power for everyone at a low cost due...

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

Science.gov (United States)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

FISH & CHIPS: Four Electrode Conductivity / Salinity Sensor on a Silicon Multi-sensor chip for Fisheries Research

DEFF Research Database (Denmark)

Hyldgård, Anders; Olafsdottir, Iris; Olesen, M.

2005-01-01

The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given......The design and fabrication of a single chip silicon salinity, temperature, pressure and light multisensor is presented. The behavior 2- and 4-electrode conductivity microsensors are described and methods for precise determination of water conductivity are given...

Origami chip-on-sensor design: progress and new developments

International Nuclear Information System (INIS)

Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

2013-01-01

The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

InP on SOI devices for optical communication and optical network on chip

Science.gov (United States)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Study and Handling Methods of Power IGBT Module Failures in Power Electronic Converter Systems

DEFF Research Database (Denmark)

Choi, Uimin; Blaabjerg, Frede; Lee, Kyo-Beum

2015-01-01

Power electronics plays an important role in a wide range of applications in order to achieve high efficiency and performance. Increasing efforts are being made to improve the reliability of power electronics systems to ensure compliance with more stringent constraints on cost, safety......, and availability in different applications. This paper presents an overview of the major failure mechanisms of IGBT modules and their handling methods in power converter systems improving reliability. The major failure mechanisms of IGBT modules are presented first, and methods for predicting lifetime...... and estimating the junction temperature of IGBT modules are then discussed. Subsequently, different methods for detecting open- and short-circuit faults are presented. Finally, fault-tolerant strategies for improving the reliability of power electronic systems under field operation are explained and compared...

Optogenetic Modulation and Multi-Electrode Analysis of Cerebellar Networks In Vivo

Science.gov (United States)

Kruse, Wolfgang; Krause, Martin; Aarse, Janna; Mark, Melanie D.; Manahan-Vaughan, Denise; Herlitze, Stefan

2014-01-01

The firing patterns of cerebellar Purkinje cells (PCs), as the sole output of the cerebellar cortex, determine and tune motor behavior. PC firing is modulated by various inputs from different brain regions and by cell-types including granule cells (GCs), climbing fibers and inhibitory interneurons. To understand how signal integration in PCs occurs and how subtle changes in the modulation of PC firing lead to adjustment of motor behaviors, it is important to precisely record PC firing in vivo and to control modulatory pathways in a spatio-temporal manner. Combining optogenetic and multi-electrode approaches, we established a new method to integrate light-guides into a multi-electrode system. With this method we are able to variably position the light-guide in defined regions relative to the recording electrode with micrometer precision. We show that PC firing can be precisely monitored and modulated by light-activation of channelrhodopsin-2 (ChR2) expressed in PCs, GCs and interneurons. Thus, this method is ideally suited to investigate the spatio/temporal modulation of PCs in anesthetized and in behaving mice. PMID:25144735

Optogenetic modulation and multi-electrode analysis of cerebellar networks in vivo.

Directory of Open Access Journals (Sweden)

Wolfgang Kruse

Full Text Available The firing patterns of cerebellar Purkinje cells (PCs, as the sole output of the cerebellar cortex, determine and tune motor behavior. PC firing is modulated by various inputs from different brain regions and by cell-types including granule cells (GCs, climbing fibers and inhibitory interneurons. To understand how signal integration in PCs occurs and how subtle changes in the modulation of PC firing lead to adjustment of motor behaviors, it is important to precisely record PC firing in vivo and to control modulatory pathways in a spatio-temporal manner. Combining optogenetic and multi-electrode approaches, we established a new method to integrate light-guides into a multi-electrode system. With this method we are able to variably position the light-guide in defined regions relative to the recording electrode with micrometer precision. We show that PC firing can be precisely monitored and modulated by light-activation of channelrhodopsin-2 (ChR2 expressed in PCs, GCs and interneurons. Thus, this method is ideally suited to investigate the spatio/temporal modulation of PCs in anesthetized and in behaving mice.

Prototype detection unit for the CHIPS experiment

Science.gov (United States)

Pfützner, Maciej M.

2017-09-01

CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

Research on channel characteristics of differential multi pulse position modulation without background noise

Science.gov (United States)

Gao, Zhuo; Zhan, Weida; Sun, Quan; Hao, Ziqiang

2018-04-01

Differential multi-pulse position modulation (DMPPM) is a new type of modulation technology. There is a fast transmission rate, high bandwidth utilization, high modulation rate characteristics. The study of DMPPM modulation has important scientific value and practical significance. Channel capacity is one of the important indexes to measure the communication capability of communication system, and studying the channel capacity of DMPPM without background noise is the key to analyze the characteristics of DMPPM. The DMPPM theoretical model is established. The symbol structure of DMPPM with guard time slot is analyzed, and the channel capacity expression of DMPPM is deduced. Simulation analysis by MATLAB. The curves of unit channel capacity and capacity efficiency at different pulse and photon counting rates are analyzed. The results show that DMPPM is more advantageous than multi-pulse position modulation (MPPM), and is more suitable for future wireless optical communication system.

Mission profile based multi-disciplinary analysis of power modules in single-phase transformerless photovoltaic inverters

DEFF Research Database (Denmark)

Yang, Yongheng; Wang, Huai; Blaabjerg, Frede

2013-01-01

years) has been set as a main target and an emerging demand from the customers, which imposes a new challenge on grid-connected transformerless inverters. In order to reduce maintenance cost, it is essential to predict the lifetime of the transformerless PV inverter and its components based......The popularity of transformerless photovoltaic (PV) inverters in Europe proves that these topologies can achieve higher efficiency (e.g., ≥ 98% has been reported). Along with the advanced power electronics technology and the booming development of PV power systems, a long service time (e.g. 25...... on the mission profiles — solar irradiance and ambient temperature. In this paper, a mission profile based analysis approach is proposed and it is demonstrated by three main single-phase transformerless PV inverters — Full-Bridge (FB) with bipolar modulation scheme, the FB inverter with DC bypass (FB...

Multi Carrier Modulator for Switch-Mode Audio Power Amplifiers

DEFF Research Database (Denmark)

Knott, Arnold; Pfaffinger, Gerhard; Andersen, Michael Andreas E.

2008-01-01

While switch-mode audio power amplifiers allow compact implementations and high output power levels due to their high power efficiency, they are very well known for creating electromagnetic interference (EMI) with other electronic equipment, in particular radio receivers. Lowering the EMI of swit...

Study of silicon chip soldering in high-power transistor housing

Directory of Open Access Journals (Sweden)

Vasily S. Anosov

2017-09-01

We experimentally assessed the effect of outer housing layer materials and back side chip metallization. For lead-silver soldering of silicon chips, the best housing is that with a nickel outer layer rather than with a gold-plated one, because the resultant thermal resistance is lower and the absence of gold makes the technology cheaper. We obtained a 0.6 K/W thermal resistance for a 24 mm2 chip area.

Compositionally modulated multilayer diamond-like carbon coatings with AlTiSi multi-doping by reactive high power impulse magnetron sputtering

Science.gov (United States)

Dai, Wei; Gao, Xiang; Liu, Jingmao; Kwon, Se-Hun; Wang, Qimin

2017-12-01

Diamond-like carbon (DLC) coatings with AlTiSi multi-doping were prepared by a reactive high power impulse magnetron sputtering with using a gas mixture of Ar and C2H2 as precursor. The composition, microstructure, compressive stress, and mechanical property of the as-deposited DLC coatings were studied systemically by using SEM, XPS, TEM, Raman spectrum, stress-tester, and nanoindentation as a function of the Ar fraction. The results show that the doping concentrations of the Al, Ti and Si atoms increased as the Ar fraction increased. The doped Ti and Si preferred to bond with C while the doped Al mainly existed in oxidation state without bonding with C. As the doping concentrations increased, TiC carbide nanocrystals were formed in the DLC matrix. The microstructure of coatings changed from an amorphous feature dominant AlTiSi-DLC to a carbide nanocomposite AlTiSi-DLC with TiC nanoparticles embedding. In addition, the coatings exhibited the compositionally modulated multilayer consisting of alternate Al-rich layer and Al-poor layer due to the rotation of the substrate holder and the diffusion behavior of the doped Al which tended to separate from C and diffuse towards the DLC matrix surface owing to its weak interactions with C. The periodic Al-rich layer can effectively release the compressive stress of the coatings. On the other hand, the hard TiC nanoparticles were conducive to the hardness of the coatings. Consequently, the DLC coatings with relatively low residual stress and high hardness could be acquired successfully through AlTiSi multi-doping. It is believed that the AlCrSi multi-doping may be a good way for improving the comprehensive properties of the DLC coatings. In addition, we believe that the DLC coatings with Al-rich multilayered structure have a high oxidation resistance, which allows the DLC coatings application in high temperature environment.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

Science.gov (United States)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

Directory of Open Access Journals (Sweden)

Oluwole John Famoriji

2017-01-01

Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

Effects of spectral variation on the device performance of copper indium diselenide and multi-crystalline silicon photovoltaic modules

Energy Technology Data Exchange (ETDEWEB)

Okullo, W.; Munji, M.K.; Vorster, F.J.; van Dyk, E.E. [Department of Physics, Nelson Mandela Metropolitan University, Box 77000, Port Elizabeth (South Africa)

2011-02-15

We present results of an experimental investigation of the effects of the daily spectral variation on the device performance of copper indium diselenide and multi-crystalline silicon photovoltaic modules. Such investigations are of importance in characterization of photovoltaic devices. The investigation centres on the analysis of outdoor solar spectral measurements carried out at 10 min intervals on clear-sky days. We have shown that the shift in the solar spectrum towards infrared has a negative impact on the device performance of both modules. The spectral bands in the visible region contribute more to the short circuit current than the bands in the infrared region while the ultraviolet region contributes least. The quantitative effects of the spectral variation on the performance of the two photovoltaic modules are reflected on their respective device performance parameters. The decrease in the visible and the increase in infrared of the late afternoon spectra in each case account for the decreased current collection and hence power and efficiency of both modules. (author)

Packaging Aspects of Photodetector Modules for 100 Gbit/s Ethernet Applications

DEFF Research Database (Denmark)

Jiang, Chenhui; Mekonnen, G.G.; Krozer, Viktor

2008-01-01

Packaging is a major problem at millimetre-wave frequencies approaching 100 GHz. In this paper we present that insertion losses in a multi-chip module (MCM) can be less IL ...-backed coplanar waveguides (CBCPWs) with vias is accurately analyzed using 3D electromagnetic (EM) simulation over a wide frequency range. Patch antenna mode resonances are identified as a major origin of resonances in simulated and measured transmission characteristics of the CBCPW with vias. Based on EM...

Multi-core System Architecture for Safety-critical Control Applications

DEFF Research Database (Denmark)

Li, Gang

and size, and high power consumption. Increasing the frequency of a processor is becoming painful now due to the explosive power consumption. Furthermore, components integrated into a single-core processor have to be certified to the highest SIL, due to that no isolation is provided in a traditional single...... certification cost. Meanwhile, hardware platforms with improved processing power are required to execute the applications of larger size. To tackle the two issues mentioned above, the state of the art approaches are using more Electronic Control Units (ECU) in a federated architecture or increasing......-core processor. A promising alternative to improve processing power and provide isolation is to adopt a multi-core architecture with on-chip isolation. In general, a specific multi-core architecture can facilitate the development and certification of safety-related systems, due to its physical isolation between...

Performance evaluation of CPPM modulation in multi-path environments

International Nuclear Information System (INIS)

Tasev, Zarko; Kocarev, Ljupco

2003-01-01

Chaotic pulse position modulation (CPPM) is a novel technique to communicate with chaotic signals based upon pulse trains in which the intervals between two pulses are determined by chaotic dynamics of a pulse generator. Using numerical simulations we show that CPPM offers excellent multi-path performance. We simulated the CPPM radio system, which is designed for a WLAN application and operates in the 2.4 GHz ISM frequency band with IEEE 802.11 compliant channel spacing. In this case, the average performance loss due the multi-path for CPPM is less than 5 dB

Performance evaluation of CPPM modulation in multi-path environments

Energy Technology Data Exchange (ETDEWEB)

Tasev, Zarko E-mail: ztasev@ucsd.edu; Kocarev, Ljupco E-mail: lkocarev@ucsd.edu

2003-01-01

Chaotic pulse position modulation (CPPM) is a novel technique to communicate with chaotic signals based upon pulse trains in which the intervals between two pulses are determined by chaotic dynamics of a pulse generator. Using numerical simulations we show that CPPM offers excellent multi-path performance. We simulated the CPPM radio system, which is designed for a WLAN application and operates in the 2.4 GHz ISM frequency band with IEEE 802.11 compliant channel spacing. In this case, the average performance loss due the multi-path for CPPM is less than 5 dB.

Nuclear Power Plant Module, NPP-1: Nuclear Power Cost Analysis.

Science.gov (United States)

Whitelaw, Robert L.

The purpose of the Nuclear Power Plant Modules, NPP-1, is to determine the total cost of electricity from a nuclear power plant in terms of all the components contributing to cost. The plan of analysis is in five parts: (1) general formulation of the cost equation; (2) capital cost and fixed charges thereon; (3) operational cost for labor,…

Sensitivity of a multi-photomultiplier optical module for KM3NeT

NARCIS (Netherlands)

Löhner, H.; Mjos, A.

2009-01-01

For the KM3NeT neutrino telescope an optical module with a number of small photomultiplier tubes (multi-PMT optical module) will be advantageous for various reasons, e.g. reduced background rate, a larger number of coincidence hits, and sensitivity to ultra-high energy neutrinos. The properties of

Multi-fuel multi-product operation of IGCC power plants with carbon capture and storage (CCS)

International Nuclear Information System (INIS)

Cormos, Ana-Maria; Dinca, Cristian; Cormos, Calin-Cristian

2015-01-01

This paper investigates multi-fuel multi-product operation of IGCC plants with carbon capture and storage (CCS). The investigated plant designs co-process coal with different sorts of biomass (e.g. sawdust) and solid wastes, through gasification, leading to different decarbonised energy vectors (power, hydrogen, heat, substitute natural gas etc.) simultaneous with carbon capture. Co-gasification of coal with different renewable energy sources coupled with carbon capture will pave the way towards zero emissions power plants. The energy conversions investigated in the paper were simulated using commercial process flow modelling package (ChemCAD) in order to produce mass and energy balances necessary for the proposed evaluation. As illustrative cases, hydrogen and power co-generation and Fischer–Tropsch fuel synthesis (both with carbon capture), were presented. The case studies investigated in the paper produce a flexible ratio between power and hydrogen (in the range of 400–600 MW net electricity and 0–200 MW th hydrogen considering the lower heating value) with at least 90% carbon capture rate. Special emphasis were given to fuel selection criteria for optimisation of gasification performances (fuel blending), to the selection criteria for gasification reactor in a multi-fuel multi-product operation scenario, modelling and simulation of whole process, to thermal and power integration of processes, flexibility analysis of the energy conversion processes, in-depth techno-economic and environmental assessment etc. - Highlights: • Assessment of IGCC-based energy vectors poly-generation systems with CCS. • Optimisation of gasification performances and CO 2 emissions by fuel blending. • Multi-fuel multi-product operation of gasification plants

On-chip micro-power: three-dimensional structures for micro-batteries and micro-supercapacitors

Science.gov (United States)

Beidaghi, Majid; Wang, Chunlei

2010-04-01

With the miniaturization of portable electronic devices, there is a demand for micro-power source which can be integrated on the semiconductor chips. Various micro-batteries have been developed in recent years to generate or store the energy that is needed by microsystems. Micro-supercapacitors are also developed recently to couple with microbatteries and energy harvesting microsystems and provide the peak power. Increasing the capacity per footprint area of micro-batteries and micro-supercapacitors is a great challenge. One promising route is the manufacturing of three dimensional (3D) structures for these micro-devices. In this paper, the recent advances in fabrication of 3D structure for micro-batteries and micro-supercapacitors are briefly reviewed.

Lunar Module Electrical Power System Design Considerations and Failure Modes

Science.gov (United States)

Interbartolo, Michael

2009-01-01

This slide presentation reviews the design and redesign considerations of the Apollo lunar module electrical power system. Included in the work are graphics showing the lunar module power system. It describes the in-flight failures, and the lessons learned from these failures.

Multilevel photonic modules for millimeter-wave phased-array antennas

Science.gov (United States)

Paolella, Arthur C.; Bauerle, Athena; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

2000-09-01

Millimeter wave phased array systems have antenna element sizes and spacings similar to MMIC chip dimensions by virtue of the operating wavelength. Designing modules in traditional planar packaing techniques are therefore difficult to implement. An advantageous way to maintain a small module footprint compatible with Ka-Band and high frequency systems is to take advantage of two leading edge technologies, opto- electronic integrated circuits (OEICs) and multilevel packaging technology. Under a Phase II SBIR these technologies are combined to form photonic modules for optically controlled millimeter wave phased array antennas. The proposed module, consisting of an OEIC integrated with a planar antenna array will operate on the 40GHz region. The OEIC consists of an InP based dual-depletion PIN photodetector and distributed amplifier. The multi-level module will be fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated, using standard commercial processes, it has the potential to be low cost while maintaining high performance, impacting both military and commercial communications systems.

Wood chip production technology and costs for fuel in Namibia

Energy Technology Data Exchange (ETDEWEB)

Leinonen, A.

2007-12-15

This work has been done in the project where the main target is to evaluate the technology and economy to use bush biomass for power production in Namibia. The project has been financed by the Ministry for Foreign Affairs of Finland and the Ministry of Agriculture, Water and Forestry of the Republic of Namibia. The target of this study is to calculate the production costs of bush chips at the power plant using the current production technology and to look possibilities to develop production technology in order to mechanize production technology and to decrease the production costs. The wood production costs are used in feasibility studies, in which the technology and economy of utilization of wood chips for power generation in 5, 10 and 20 MW electric power plants and for power generation in Van Eck coal fired power plant in Windhoek are evaluated. Field tests were made at Cheetah Conservation Farm (CCF) in Otjiwarongo region. CCF is producing wood chips for briquette factory in Otjiwarongo. In the field tests it has been gathered information about this CCF semi-mechanized wood chip production technology. Also new machines for bush biomass chip production have been tested. A new mechanized production chain has been designed on the basis of this information. The production costs for the CCF semi-mechanized and the new production chain have been calculated. The target in the moisture content to produce wood chips for energy is 20 w-%. In the semi-mechanized wood chip production chain the work is done partly manually, and the supply chain is organized into crews of 4.8 men. The production chain consists of manual felling and compiling, drying, chipping with mobile chipper and manual feeding and road transport by a tractor with two trailers. The CCF production chain works well. The chipping and road transport productivity in the semimechanized production chain is low. New production machines, such as chainsaw, brush cutter, lawn mover type cutter, rotator saw in skid

Photonic packaging sourcebook fiber-chip coupling for optical components, basic calculations, modules

CERN Document Server

Fischer-Hirchert, Ulrich H P

2015-01-01

This book serves as a guide on photonic assembly techniques. It provides an overview of today's state-of-the-art technologies for photonic packaging experts and professionals in the field. The text guides the readers to the practical use of optical connectors. It also assists engineers to find a way to an effective and inexpensive set-up for their own needs. In addition, many types of current industrial modules and state-of-the-art applications from single fiber to multi fiber are described in detail. Simulation techniques such as FEM, BPM and ray tracing are explained in depth. Finally, all recent reliability test procedures for datacom and telecom modules are illustrated in combination with related standardization aspects.

Apollo 11 Command Service Module

Science.gov (United States)

1969-01-01

A close-up view of the Apollo 11 command service module ready to be mated with the spacecraft LEM adapter of the third stage. The towering 363-foot Saturn V was a multi-stage, multi-engine launch vehicle standing taller than the Statue of Liberty. Altogether, the Saturn V engines produced as much power as 85 Hoover Dams.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

Science.gov (United States)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

Advanced power cycling test for power module with on-line on-state VCE measurement

DEFF Research Database (Denmark)

Choi, Ui-min; Trintis, Ionut; Blaabjerg, Frede

2015-01-01

module. The proposed concept can perform various stress conditions which is valid in a real mission profile and it is using a real power converter application with small loss. The concept of the proposed test setup is first presented. Then, the on-line on-state collector-emitter voltage VCE measurement......Recent research has made an effort to improve the reliability of power electronic systems to comply with more stringent constraints on cost, safety, predicted lifetime and availability in many applications. For this, studies about failure mechanisms of power electronic components and lifetime...... estimation of power semiconductor devices and capacitors have been done. Accelerated power cycling test is one of the common tests to assess the power device module and develop the lifetime model considering the physics of failure. In this paper, a new advanced power cycling test setup is proposed for power...

Reliability-cost models for the power switching devices of wind power converters

DEFF Research Database (Denmark)

Ma, Ke; Blaabjerg, Frede

2012-01-01

In order to satisfy the growing reliability requirements for the wind power converters with more cost-effective solution, the target of this paper is to establish a new reliability-cost model which can connect the relationship between reliability performances and corresponding semiconductor cost...... temperature mean value Tm and fluctuation amplitude ΔTj of power devices, are presented. With the proposed reliability-cost model, it is possible to enable future reliability-oriented design of the power switching devices for wind power converters, and also an evaluation benchmark for different wind power...... for power switching devices. First the conduction loss, switching loss as well as thermal impedance models of power switching devices (IGBT module) are related to the semiconductor chip number information respectively. Afterwards simplified analytical solutions, which can directly extract the junction...

Flattened optical frequency-locked multi-carrier generation by cascading one DML and one phase modulator driven by different RF frequency clocks

International Nuclear Information System (INIS)

Li, Xinying; Yu, Jianjun; Zhang, Junwen; Chi, Nan

2013-01-01

We propose a novel scheme for flattened optical frequency-locked multi-carrier generation based on one directly modulated laser (DML) and one phase modulator (PM) in cascade driven by different sinusoidal radio-frequency (RF) clocks. We experimentally demonstrate that when the clock frequencies for the cascaded DML and the PM are respectively 12.5 GHz and 25 GHz, over 24 optical subcarriers can be generated with 12.5-GHz frequency spacing and amplitude fluctuation less than 3 dB. Furthermore, the number of generated optical subcarriers can be further increased when we increase the driving power for the DML. (letter)

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

Science.gov (United States)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Six-port optical switch for cluster-mesh photonic network-on-chip

Science.gov (United States)

Jia, Hao; Zhou, Ting; Zhao, Yunchou; Xia, Yuhao; Dai, Jincheng; Zhang, Lei; Ding, Jianfeng; Fu, Xin; Yang, Lin

2018-05-01

Photonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

Science.gov (United States)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Multi-variable systems in nuclear power plant

International Nuclear Information System (INIS)

Collins, G.B.; Howell, J.

1982-01-01

Nuclear power plant are complex multi-variable dynamically interactive systems which employ many facets of systems and control theory in their analysis and design. Whole plant mathematical models must be developed and validated and in addition to their obvious role in control system synthesis and design, they are also widely used for operational constraint and plant malfunction analysis. The need for and scope of an integrated power plant control system is discussed and, as a specific example, the design of an integrated feedwater regulator is reviewed. The multi-variable frequency response analysis employed in the design is described in detail. (author)

Globally Stable Microresonator Turing Pattern Formation for Coherent High-Power THz Radiation On-Chip

Science.gov (United States)

Huang, Shu-Wei; Yang, Jinghui; Yang, Shang-Hua; Yu, Mingbin; Kwong, Dim-Lee; Zelevinsky, T.; Jarrahi, Mona; Wong, Chee Wei

2017-10-01

In nonlinear microresonators driven by continuous-wave (cw) lasers, Turing patterns have been studied in the formalism of the Lugiato-Lefever equation with emphasis on their high coherence and exceptional robustness against perturbations. Destabilization of Turing patterns and the transition to spatiotemporal chaos, however, limit the available energy carried in the Turing rolls and prevent further harvest of their high coherence and robustness to noise. Here, we report a novel scheme to circumvent such destabilization, by incorporating the effect of local mode hybridizations, and we attain globally stable Turing pattern formation in chip-scale nonlinear oscillators with significantly enlarged parameter space, achieving a record-high power-conversion efficiency of 45% and an elevated peak-to-valley contrast of 100. The stationary Turing pattern is discretely tunable across 430 GHz on a THz carrier, with a fractional frequency sideband nonuniformity measured at 7.3 ×10-14 . We demonstrate the simultaneous microwave and optical coherence of the Turing rolls at different evolution stages through ultrafast optical correlation techniques. The free-running Turing-roll coherence, 9 kHz in 200 ms and 160 kHz in 20 minutes, is transferred onto a plasmonic photomixer for one of the highest-power THz coherent generations at room temperature, with 1.1% optical-to-THz power conversion. Its long-term stability can be further improved by more than 2 orders of magnitude, reaching an Allan deviation of 6 ×10-10 at 100 s, with a simple computer-aided slow feedback control. The demonstrated on-chip coherent high-power Turing-THz system is promising to find applications in astrophysics, medical imaging, and wireless communications.

Modulation Schemes of Multi-phase Three-Level Z-Source Inverters

DEFF Research Database (Denmark)

Gao, F.; Loh, P.C.; Blaabjerg, Frede

2007-01-01

different modulation requirement and output performance. For clearly illustrating the detailed modulation process, time domain analysis instead of the traditional multi-dimensional space vector demonstration is assumed which reveals the right way to insert shoot-through durations in the switching sequence...... with minimal commutation count. Lastly, the theoretical findings are verified in Matlab/PLECS simulation and experimentally using constructed laboratory prototypes.......This paper investigates the modulation schemes of three-level multiphase Z-source inverters with either two Z-source networks or single Z-source network connected between the dc sources and inverter circuitry. With the proper offset added for achieving both desired four-leg operation and optimized...

Feasibility study of a green energy powered thermoelectric chip based air conditioner for electric vehicles

International Nuclear Information System (INIS)

Miranda, Á.G.; Chen, T.S.; Hong, C.W.

2013-01-01

Traditional compressed-refrigerant air conditioning systems consume substantial energy that may reduce the driving performance and cruising mileage of electric vehicles considerably. It is crucial to design a new climate control system, using a direct energy conversion principle, to further aid in the commercialization of modern electric vehicles. A solid state air conditioner model consisting on TECs (thermoelectric chips) as the load, DSSCs (dye sensitized solar cells) as the renewable energy source and high power LiBs (lithium-ion batteries) as an energy storage device are considered for a personal mobility vehicle. The power management between the main power net and the solid state air conditioner interface is designed with an outer proportional-integral controller and an inner passivity based current controller with a loss included model for perfect tracking. This model is intended to comprise thermal and electrical elements which can be tunable for performance benchmarking and optimization of a solid state air conditioning system. Dynamic performance simulations of the solid-state air conditioner are performed, alongside guidelines for feasibility. - Highlights: • Alternative model extraction for dye sensitized solar cells. • Improved and computationally fast model for the cabin air temperature dynamics. • Euler–Lagrange loss included modeling of a buck converter. • Loss-included passivity based inner loop current control. • The thermoelectric chip air conditioner is tested in simulated cooling/heating scenarios

Inverter power module with distributed support for direct substrate cooling

Science.gov (United States)

Miller, David Harold [San Pedro, CA; Korich, Mark D [Chino Hills, CA; Ward, Terence G [Redondo Beach, CA; Mann, Brooks S [Redondo Beach, CA

2012-08-21

Systems and/or methods are provided for an inverter power module with distributed support for direct substrate cooling. An inverter module comprises a power electronic substrate. A first support frame is adapted to house the power electronic substrate and has a first region adapted to allow direct cooling of the power electronic substrate. A gasket is interposed between the power electronic substrate and the first support frame. The gasket is configured to provide a seal between the first region and the power electronic substrate. A second support frame is adapted to house the power electronic substrate and joined to the first support frame to form the seal.

White LEDs and modules in chip-on-board technology for general lighting

Science.gov (United States)

Hartmann, Paul; Wenzl, Franz P.; Sommer, Christian; Pachler, Peter; Hoschopf, Hans; Schweighart, Marko; Hartmann, Martin; Kuna, Ladislav; Jakopic, Georg; Leising, Guenther; Tasch, Stefan

2006-08-01

At present, light-emitting diode (LED) modules in various shapes are developed and designed for the general lighting, advertisement, emergency lighting, design and architectural markets. To compete with and to surpass the performance of traditional lighting systems, enhancement of Lumen output and the white light quality as well as the thermal management and the luminary integration are key factors for success. Regarding these issues, white LEDs based on the chip-on-board (COB) technology show pronounced advantages. State-of-the-art LEDs exploiting this technology are now ready to enter the general lighting segments. We introduce and discuss the specific properties of the Tridonic COB technology dedicated for general lighting. This technology, in combination with a comprehensive set of tools to improve and to enhance the Lumen output and the white light quality, including optical simulation, is the scaffolding for the application of white LEDs in emerging areas, for which an outlook will be given.

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

NARCIS (Netherlands)

Hansson, A.; Goossens, K.; Rãdulescu, A.

2007-01-01

Networks on chip (NoCs) are an essential component of systems on chip (SoCs) and much research is devoted to deadlock avoidance in NoCs. Prior work focuses on the router network while protocol interactions between NoC and intellectual property (IP) modules are not considered. These interactions

A primary battery-on-a-chip using monolayer graphene

Science.gov (United States)

Iost, Rodrigo M.; Crespilho, Frank N.; Kern, Klaus; Balasubramanian, Kannan

2016-07-01

We present here a bottom-up approach for realizing on-chip on-demand batteries starting out with chemical vapor deposition-grown graphene. Single graphene monolayers contacted by electrode lines on a silicon chip serve as electrodes. The anode and cathode are realized by electrodeposition of zinc and copper respectively onto graphene, leading to the realization of a miniature graphene-based Daniell cell on a chip. The electrolyte is housed partly in a gel and partly in liquid form in an on-chip enclosure molded using a 3d printer or made out of poly(dimethylsiloxane). The realized batteries provide a stable voltage (∼1.1 V) for many hours and exhibit capacities as high as 15 μAh, providing enough power to operate a pocket calculator. The realized batteries show promise for deployment as on-chip power sources for autonomous systems in lab-on-a-chip or biomedical applications.

Quantitative Prediction of Power Loss for Damaged Photovoltaic Modules Using Electroluminescence

Directory of Open Access Journals (Sweden)

Timo Kropp

2018-05-01

Full Text Available Electroluminescence (EL is a powerful tool for the qualitative mapping of the electronic properties of solar modules, where electronic and electrical defects are easily detected. However, a direct quantitative prediction of electrical module performance purely based on electroluminescence images has yet to be accomplished. Our novel approach, called “EL power prediction of modules” (ELMO as presented here, used just two electroluminescence images to predict the electrical loss of mechanically damaged modules when compared to their original (data sheet power. First, using this method, two EL images taken at different excitation currents were converted into locally resolved (relative series resistance images. From the known, total applied voltage to the module, we were then able to calculate absolute series resistance values and the real distribution of voltages and currents. Then, we reconstructed the complete current/voltage curve of the damaged module. We experimentally validated and confirmed the simulation model via the characterization of a commercially available photovoltaic module containing 60 multicrystalline silicon cells, which were mechanically damaged by hail. Deviation between the directly measured and predicted current/voltage curve was less than 4.3% at the maximum power point. For multiple modules of the same type, the level of error dropped below 1% by calibrating the simulation. We approximated the ideality factor from a module with a known current/voltage curve and then expand the application to modules of the same type. In addition to yielding series resistance mapping, our new ELMO method was also capable of yielding parallel resistance mapping. We analyzed the electrical properties of a commercially available module, containing 72 monocrystalline high-efficiency back contact solar cells, which suffered from potential induced degradation. For this module, we predicted electrical performance with an accuracy of better

Multi-objective optimal power flow with FACTS devices

International Nuclear Information System (INIS)

Basu, M.

2011-01-01

This paper presents multi-objective differential evolution to optimize cost of generation, emission and active power transmission loss of flexible ac transmission systems (FACTS) device-equipped power systems. In the proposed approach, optimal power flow problem is formulated as a multi-objective optimization problem. FACTS devices considered include thyristor controlled series capacitor (TCSC) and thyristor controlled phase shifter (TCPS). The proposed approach has been examined and tested on the modified IEEE 30-bus and 57-bus test systems. The results obtained from the proposed approach have been compared with those obtained from nondominated sorting genetic algorithm-II, strength pareto evolutionary algorithm 2 and pareto differential evolution.

On-Chip Implantable Antennas for Wireless Power and Data Transfer in a Glaucoma-Monitoring SoC

KAUST Repository

Marnat, Loic

2013-04-17

For the first time separate transmit and receive onchip antennas have been designed in a eye environment for implantable intraocular pressure monitoring application. The miniaturized antennas fit on a 1.4 mm3 CMOS (0.18 μm) chip with the rest of the circuitry. A 5.2 GHz novel inductive fed and loaded receive monopole antenna is used for wireless powering the chip and is conjugately matched to the rectifier in the energy harvesting and storage unit. The 2.4 GHz transmit antenna is an octagonal loop which also acts as the inductor of the voltage control oscillator resonant tank. To emulate the eye environment in measurements, a custom test setup is developed which comprises plexiglass cavities filled with saline solution. A transition, employing a balun, is also designed which transforms the differential impedance of on-chip antennas immersed in saline solution to a 50 ! single-ended micrsotrip line. The antennas on a lossy Si substrate and eye environment provide sufficient gain to establish wireless communication with an external reader placed few cm away from the eye.

A High Performance Delta-Sigma Modulator for Neurosensing.

Science.gov (United States)

Xu, Jian; Zhao, Menglian; Wu, Xiaobo; Islam, Md Kafiul; Yang, Zhi

2015-08-07

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-µm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 µW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.

Coordinated Multi-Objective Control of Regulating Resources in Multi-Area Power Systems with Large Penetration of Wind Power Generation

DEFF Research Database (Denmark)

Nyeng, Preben; Yang, Bo; Ma, Jian

2008-01-01

This paper describes a control algorithm for a Wide Area Energy Storage and Management System (WAEMS). The WAEMS is designed to meet the demand for fast, accurate and reliable regulation services in multi-area power systems with a significant share of wind power and other intermittent generation...

Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

Directory of Open Access Journals (Sweden)

Shantonu Biswas

2016-03-01

Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

An Integrated Chip High-Voltage Power Receiver for Wireless Biomedical Implants

Directory of Open Access Journals (Sweden)

Vijith Vijayakumaran Nair

2015-06-01

Full Text Available In near-field wireless-powered biomedical implants, the receiver voltage largely overrides the compliance of low-voltage power receiver systems. To limit the induced voltage, generally, low-voltage topologies utilize limiter circuits, voltage clippers or shunt regulators, which are power-inefficient methods. In order to overcome the voltage limitation and improve power efficiency, we propose an integrated chip high-voltage power receiver based on the step down approach. The topology accommodates voltages as high as 30 V and comprises a high-voltage semi-active rectifier, a voltage reference generator and a series regulator. Further, a battery management circuit that enables safe and reliable implant battery charging based on analog control is proposed and realized. The power receiver is fabricated in 0.35-μm high-voltage Bipolar-CMOS-DMOStechnology based on the LOCOS0.35-μm CMOS process. Measurement results indicate 83.5% power conversion efficiency for a rectifier at 2.1 mA load current. The low drop-out regulator based on the current buffer compensation and buffer impedance attenuation scheme operates with low quiescent current, reduces the power consumption and provides good stability. The topology also provides good power supply rejection, which is adequate for the design application. Measurement results indicate regulator output of 4 ± 0.03 V for input from 5 to 30 V and 10 ± 0.05 V output for input from 11 to 30 V with load current 0.01–100 mA. The charger circuit manages the charging of the Li-ion battery through all if the typical stages of the Li-ion battery charging profile.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

Science.gov (United States)

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Modified precision-husky progrind H-3045 for chipping biomass

Science.gov (United States)

Dana Mitchell; Fernando Seixas; John. Klepac

2008-01-01

A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

Analysis of a multi-module split coaxial RFQ

International Nuclear Information System (INIS)

Arai, Shigeaki.

1986-11-01

A split coaxial RFQ linac with modulated vanes is under development for acceleration of very heavy ions. As a first step, a 1/4 scaled model with flat vanes has been constructed. Easy assembling of vanes and good mechanical stability of the structure have been achieved by employing a multi-module cavity arrangement. In this paper, theoretical treatments for the estimation of rf parameters and the interpretation of resonance characteristics are described in detail and their results are compared with the experimental data. The resonant frequency predicted by using the estimated inductance and the measured capacitance agrees with the experimental value within 2 % accuracy. Dispersion characteristics and longitudinal voltage distribution at each resonance mode are qualitatively well explained by an equivalent circuit analysis. (author)

Effects of Auxiliary-Source Connection in Multichip Power Module

DEFF Research Database (Denmark)

Li, Helong; Munk-Nielsen, Stig; Wang, Xiongfei

2017-01-01

the power loop and the gate loop like how the Kelvin-source connection does, owing to their involvement in the loop of the power source current. Three effects of the auxiliary-source connections are then analyzed, which are 1) the common source stray inductance reduction, 2) the transient drain......Auxiliary-source bond wires and connections are widely used in power modules with paralleled MOSFETs or IGBTs. This paper investigates the operation mechanism of the auxiliary-source connections in multichip power modules. It reveals that the auxiliary-source connections cannot fully decouple......-source current imbalance mitigation, and 3) the influence on the steady-state current distribution. Lastly, simulations and experimental results validate the theoretical analysis....

Supply chains of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

2010-07-15

The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

Supply systems of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

2010-07-01

The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

Supply chains of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

2009-07-01

The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

A powerful way of cooling computer chip using liquid metal with low melting point as the cooling fluid

Energy Technology Data Exchange (ETDEWEB)

Li Teng; Lv Yong-Gang [Chinese Academy of Sciences, Beijing (China). Cryogenic Lab.; Chinese Academy of Sciences, Beijing (China). Graduate School; Liu Jing; Zhou Yi-Xin [Chinese Academy of Sciences, Beijing (China). Cryogenic Lab.

2006-12-15

With the improvement of computational speed, thermal management becomes a serious concern in computer system. CPU chips are squeezing into tighter and tighter spaces with no more room for heat to escape. Total power-dissipation levels now reside about 110 W, and peak power densities are reaching 400-500 W/mm{sup 2} and are still steadily climbing. As a result, higher performance and greater reliability are extremely tough to attain. But since the standard conduction and forced-air convection techniques no longer be able to provide adequate cooling for sophisticated electronic systems, new solutions are being looked into liquid cooling, thermoelectric cooling, heat pipes, and vapor chambers. In this paper, we investigated a novel method to significantly lower the chip temperature using liquid metal with low melting point as the cooling fluid. The liquid gallium was particularly adopted to test the feasibility of this cooling approach, due to its low melting point at 29.7 C, high thermal conductivity and heat capacity. A series of experiments with different flow rates and heat dissipation rates were performed. The cooling capacity and reliability of the liquid metal were compared with that of the water-cooling and very attractive results were obtained. Finally, a general criterion was introduced to evaluate the cooling performance difference between the liquid metal cooling and the water-cooling. The results indicate that the temperature of the computer chip can be significantly reduced with the increasing flow rate of liquid gallium, which suggests that an even higher power dissipation density can be achieved with a large flow of liquid gallium and large area of heat dissipation. The concept discussed in this paper is expected to provide a powerful cooling strategy for the notebook PC, desktop PC and large computer. It can also be extended to more wide area involved with thermal management on high heat generation rate. (orig.)

Pulsewidth modulated DC-to-DC power conversion circuits, dynamics, and control designs

CERN Document Server

Choi, Byungcho

2013-01-01

This is the definitive reference for anyone involved in pulsewidth modulated DC-to-DC power conversion Pulsewidth Modulated DC-to-DC Power Conversion: Circuits, Dynamics, and Control Designs provides engineers, researchers, and students in the power electronics field with comprehensive and complete guidance to understanding pulsewidth modulated (PWM) DC-to-DC power converters. Presented in three parts, the book addresses the circuitry and operation of PWM DC-to-DC converters and their dynamic characteristics, along with in-depth discussions of control design of PWM DC-to

High Power Modulator/regulators for neutral beam sources

International Nuclear Information System (INIS)

Lawson, J.Q.; Deitz, A.

1975-01-01

PPPL has recently completed two new Modulator/Regulators for neutral injection sources used on the ATC machine and is constructing four new ones for use with sources on the PLT machine. The ATC modulator uses the well proven 4CX35,000C tetrode as the main switch tube, while the PLT modulators will be using the new but significantly higher powered X-2170 tetrodes. Some interesting circuit and manufacturing techniques are discussed

In situ photo-immobilised pH gradient isoelectric focusing and zone electrophoresis integrated two-dimensional microfluidic chip electrophoresis for protein separation

International Nuclear Information System (INIS)

Lin, Fengmin; Yu, Shiyong; Gu, Le; Zhu, Xuetao; Wang, Jianshe; Zhu, Han; Lu, Yi; Wang, Yihua; Deng, Yulin; Geng, Lina

2015-01-01

A method is introduced for open-column photo-induced site-selective immobilization of pH gradients in a layer of PEG-methacrylate in a multi-dimensional microfluidic chip for use in electrophoresis. It has several attractive features: (a) mixtures of fluorescently labelled proteins carbonic anhydrase, catalase and myoglobin in their native state can be separated by pH-gradient isoelectric focusing (IEF) and zone electrophoresis (CZE) using integrated 2D chip electrophoresis; (b) compared to strip packing or monolithic photo-immobilization, it overcomes the shortcomings of free carrier ampholyte-based 2D chip electrophoresis in an easy way; (c) larger amount of sample can be loaded into the open column-mode electrophoresis (d) immobilized pH gradients can be re-used and the chip can be recycled; (e) a multilayer 3D pH gradient is established by a layer-by-layer assembly technique to further increase the separation capacity. In our perception, this strategy has a large potential in microfluidic chip-based separation schemes because of its simplicity, separation power, re-usability, and separation capacity. (author)

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

Directory of Open Access Journals (Sweden)

Sergio Saponara

2012-01-01

Full Text Available Two multiprocessor system-on-chip (MPSoC architectures are proposed and compared in the paper with reference to audio and video processing applications. One architecture exploits a homogeneous topology; it consists of 8 identical tiles, each made of a 32-bit RISC core enhanced by a 64-bit DSP coprocessor with local memory. The other MPSoC architecture exploits a heterogeneous-tile topology with on-chip distributed memory resources; the tiles act as application specific processors supporting a different class of algorithms. In both architectures, the multiple tiles are interconnected by a network-on-chip (NoC infrastructure, through network interfaces and routers, which allows parallel operations of the multiple tiles. The functional performances and the implementation complexity of the NoC-based MPSoC architectures are assessed by synthesis results in submicron CMOS technology. Among the large set of supported algorithms, two case studies are considered: the real-time implementation of an H.264/MPEG AVC video codec and of a low-distortion digital audio amplifier. The heterogeneous architecture ensures a higher power efficiency and a smaller area occupation and is more suited for low-power multimedia processing, such as in mobile devices. The homogeneous scheme allows for a higher flexibility and easier system scalability and is more suited for general-purpose DSP tasks in power-supplied devices.

A Chip for an Implantable Neural Stimulator

DEFF Research Database (Denmark)

Gudnason, Gunnar; Bruun, Erik; Haugland, Morten

2000-01-01

This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation (FES). The purpose of FES is to restore muscular control in disabled patients. The chip performs all the signal processing required in an implanted neural stimulator. The power and digital data...

Advanced Accelerated Power Cycling Test for Reliability Investigation of Power Device Modules

DEFF Research Database (Denmark)

Choi, Uimin; Jørgensen, Søren; Blaabjerg, Frede

2016-01-01

This paper presents an apparatus and methodology for an advanced accelerated power cycling test of insulated-gate bipolar transistor (IGBT) modules. In this test, the accelerated power cycling test can be performed under more realistic electrical operating conditions with online wear-out monitoring...... of tested power IGBT module. The various realistic electrical operating conditions close to real three-phase converter applications can be achieved by the simple control method. Further, by the proposed concept of applying the temperature stress, it is possible to apply various magnitudes of temperature...... swing in a short cycle period and to change the temperature cycle period easily. Thanks to a short temperature cycle period, test results can be obtained in a reasonable test time. A detailed explanation of apparatus such as configuration and control methods for the different functions of accelerated...

Investigation of solar photovoltaic module power output by various models

International Nuclear Information System (INIS)

Jakhrani, A.Q.; Othman, A.K.; Rigit, A.R.H.; Baini, R.

2012-01-01

This paper aims to investigate the power output of a solar photovoltaic module by various models and to formulate a suitable model for predicting the performance of solar photovoltaic modules. The model was used to correct the configurations of solar photovoltaic systems for sustainable power supply. Different types of models namely the efficiency, power, fill factor and current-voltage characteristic curve models have been reviewed. It was found that the examined models predicted a 40% yield of the rated power in cloudy weather conditions and up to 80% in clear skies. The models performed well in terms of electrical efficiency in cloudy days if the influence of low irradiance were incorporated. Both analytical and numerical methods were employed in the formulation of improved model which gave +- 2% error when compared with the rated power output of solar photovoltaic module. The proposed model is more practical in terms of number of variables used and acceptable performance in humid atmospheres. Therefore, it could be useful for the estimation of power output of the solar photovoltaic systems in Sarawak region. (author)

Reconfigurable Bandpass Sigma-Delta Modulator With Programmable NTF for Low-IF Multi-Mode Receivers

DEFF Research Database (Denmark)

Zhang, Ke; Mikkelsen, Jan H.; Shen, Ming

2012-01-01

transfer function of the loop while still maintaining stability. Compared with conventional multi-mode BPSDM, employing cascade structures and multi-bit sub-ADCs, the proposed modulator features many attractive advantages, such as (1) avoiding coefficient mismatch between analog and digital components...

Solid state modulator for klystron power supply XFEL TDS INJ

Science.gov (United States)

Zavadtsev, A. A.; Zavadtsev, D. A.; Zybin, D. A.; Churanov, D. V.; Shemarykin, P. V.

2016-09-01

The transverse deflecting system XFEL TDS INJ for European X-ray Free Electron Laser includes power supply for the CPI VKS-8262HS klystron. It has been designed for pulse high-voltage, cathode heating, solenoid and klystron ion pump. The klystron power supply includes solid state modulator, pulse transformer, controlled power supply for cathode heating and commercial power supplies for solenoid and ion pump. Main parameters of the modulator are 110 kV of peak voltage, 72 A peak current, and pulse length up to 6 μs. The klystron power supply has been developed, designed, manufactured, tuned, tested and installed in the XFEL building. All designed parameters are satisfied.

Full-scale multi-ejector module for a carbon dioxide supermarket refrigeration system: Numerical study of performance evaluation

International Nuclear Information System (INIS)

Bodys, Jakub; Palacz, Michal; Haida, Michal; Smolka, Jacek; Nowak, Andrzej J.; Banasiak, Krzysztof; Hafner, Armin

2017-01-01

Highlights: • A numerical study of the full-scale multi-ejector module performance was presented. • The module was characterised by stable operation in each considered configuration. • The module showed a high total efficiency for all the operating conditions. - Abstract: The performance of fixed ejectors installed in a multi-ejector module in a carbon dioxide refrigeration system is discussed in this paper. To analyse the module operation, three-dimensional ejector models including the inlet and outlet collecting ducts were considered. The tests were performed for three of four vapour ejectors of different sizes that compose the multi-ejector pack. The testing modes included the serial and parallel operation of the fixed units in operating conditions that are characteristic for the supermarket refrigeration unit working at high ambient temperatures. All numerical simulations were performed using the validated Homogeneous Equilibrium Model implemented on the ejectorPL computational tool for typical transcritical parameters at the motive nozzle port. The detailed analysis was executed separately for the ejectors and the ducts of the module collectors. The results discussion concerned the crucial parameters for such an installation like the pressure and vapour quality distribution. Negligible influence of the motive nozzle collector and a crucial influence of the outlet collector shape was indicated. The global performance analysis showed that the multi-ejector pack provides high and stable performance of all installed ejectors over the entire range of the considered operating conditions for supermarket application. Areas of the possible pressure loss reduction and the uniformity growth in the vapour quality distribution were presented. Finally, according to the multi-ejector pack ducts analysis, the potential areas for module shape optimisation were indicated as well.

Wood chip delivery and research project at Mikkeli region

International Nuclear Information System (INIS)

Saksa, T.; Auvinen, P.

1995-01-01

In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m 3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m 3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m 3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m 3 /a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

Staves and Petals: Multi-module Local Support Structures of the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS Inner Tracker (ITk) is an all-silicon tracker that will replace the existing inner detector at the Phase-II Upgrade of ATLAS. The outermost part of the tracker consists of the strips tracker, in which the sensors elements consist of silicon micro-strip sensors with strip lengths varying from 1.7 to up to 10 cm. The current design, at the moment under internal review in the Strips part of the Technical Design Report (TDR), envisions a four-layer barrel and two six-disk endcap regions. The sensor and readout units (“modules”) are directly glued onto multi-module, low-mass, high thermal performance carbon fiber structures, called “staves” for the barrel and “petals” for the endcap. They provide cooling, power, data and control lines to the modules with a minimal amount of external services. An extensive prototyping program was put in place over the last years to fully characterize these structures mechanically, thermally, and electrically. Thermo-mechanical stave and petal prototypes have r...

Status of sensor qualification for the PS module with on-chip $p_T$ discrimination for the CMS tracker phase 2 upgrade

CERN Document Server

AUTHOR|(CDS)2095782

2016-01-01

The high luminosity upgrade of the LHC is targeted to deliver 3000 fb$^{-1}$ at a luminosity of $5\\times10^{34}$cm$^{-2}$s$^{-1}$. Higher granularity, 140 collisions per bunch crossing and existing bandwidth limitations require a reduction of the amount of data at module level. New modules have binary readout, on-chip $p_{\\mathrm{ T}}$ discrimination and capabilities to provide track finding data at 40 MHz to the L1-trigger. The CMS collaboration has undertaken R&D effort to develop new planar sensors for the pixel-strip (PS) module, which has to withstand $1\\times10^{15}$ cm$^{-2}$ 1 MeV neutron equivalent fluence in the innermost layer of the tracker. The module is composed of a strip sensor and a macro pixel sensor with 100$\\mu$m $\\times$ 1.5 mm pixel size. Sensors were characterized in the laboratory and the effects of different process parameters and sensor concepts were studied. This contribution presents a new sensor prototype with n-pixels in p-bulk material in planar technology for the PS module...

A multi-channel AC power supply controller

International Nuclear Information System (INIS)

Su Hong; Li Xiaogang; Ma Xiaoli; Zhou Bo; Yin Weiwei

2003-01-01

A multi-channel ac power supply controller developed recently by authors is introduced briefly in this paper. This controller is a computer controlled multi-electronic-switch device. This controller was developed for the automatic control and monitoring system of a 220 V ac power supply system, it is a key front-end device of the automatic control and monitoring system. There is an electronic switch in each channel, the rated load power is ≤1 kW/each channel. Another function is to sample the 220 V ac output voltage so that computer can monitor the operation state of each electronic switch. Through these switches, the 220 V ac power supply is applied to some device or apparatus that need to be powered by 220 V ac power supply. In the design, a solid-state relay was employed as an electronic switch. This controller can be connected in cascade mode. There are 8 boxes at most can be connected in cascade mode. The length of control word is 8 bit, which contains addressing information and electronic switch state setting information. The sampling output of the controller is multiplexed. It is only one bit that indicates the operating state of an electronic switch. This controller has been used in an automatic control and monitoring system for 220 V ac power supply system

Integrated thermal control and system assessment in plug-chip spray cooling enclosure

International Nuclear Information System (INIS)

Zhang, Wei-Wei; Cheng, Wen-Long; Shao, Shi-Dong; Jiang, Li-Jia; Hong, Da-Liang

2016-01-01

Highlights: • A novel multi-heat source plug-chip spray cooling enclosure was designed. • Enhanced surfaces with different geometric were analyzed in integrated enclosure. • Overall thermal control with adjustable parameters in enclosure was studied. • Temperature disequilibrium of multi-heat source in enclosure was tested. • A comprehensive assessment system used to evaluate the practicality was proposed. - Abstract: Practical and integrated spray cooling system is urgently needed for the cooling of high-performance electronic chips due to the growth requirements of thermal management in workstation. The integration of multi heat sources and the management of integral system are particularly lacking. In order to fill the vacancies in the study of plug-chip spray cooling, an integrated cooling enclosure was designed in this paper. Multi heat sources were placed in sealed space and the heat was removed by spray. The printed circuit board plug-ins and radio frequency resistors were used as analog motherboards and chips, respectively. The enhanced surfaces with four different geometries and the plain surface were studied under the conditions of different inclination angles. The results were compared and the maximum critical heat flux (CHF) was obtained. Moreover, with the intention of the overall management of multi-heat source in integrated enclosure, the effect of the flow rate and the temperature disequilibrium, and the pulse heating in the process of transient cooling were also analyzed. In addition, a comprehensive assessment system, used to evaluate the practicality of spray cooling experimental devices, was proposed and the performance of enclosure was evaluated.

Chip-integrated optical power limiter based on an all-passive micro-ring resonator

Science.gov (United States)

Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

2014-10-01

Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

Radioactivity changes during burning of peat and chip

International Nuclear Information System (INIS)

Hedvall, R.; Erlandsson, B.; Mattsson, S.

1985-01-01

The increasing use of peat and chip as fuel materials in fossil-fuel power plants has resulted in the need for information about the change in radionuclides concentration in fuel after combustion. The paper describes a study of natural radionuclides from the uranium- and the thorium series and 40 K, as well as fission products from atmospheric nuclear explosions, in ashes from five peat and chip fuelled power plants in Sweden

Integrated packaging of multiple double sided cooling planar bond power modules

Science.gov (United States)

Liang, Zhenxian

2018-04-10

An integrated double sided cooled power module has one or multiple phase legs configuration including one or more planar power packages, each planar power package having an upper power switch unit and a lower power switch unit directly bonded and interconnected between two insulated power substrates, and further sandwiched between two heat exchangers via direct bonds. A segmented coolant manifold is interposed with the one or more planar power packages and creates a sealed enclosure that defines a coolant inlet, a coolant outlet and a coolant flow path between the inlet and the outlet. A coolant circulates along the flow path to remove heat and increase the power density of the power module.

Single-chip serial channel enhances multi-processor systems

Energy Technology Data Exchange (ETDEWEB)

Millar, J.

1982-01-01

In this paper multiprocessor systems are described and explained. The impact that VLSI advancements are having on multiprocessor design is pointed out. The TMS 7041 single-chip microcomputer is described briefly, highlighting its multiprocessor communication capability. And finally, a typical multiprocessor system is shown, implementing the TMS 7041.

POWER ELECTRONIC SYSTEM FOR POWER ELECTRIC VEHICLES WITH ALGORITHMS OF SYNCHRONOUS MODULATION

Directory of Open Access Journals (Sweden)

Oleschuk V.

2014-04-01

Full Text Available Schemes of synchronous space-vector modulation have been adapted for control of split-phase drive for electric vehicle with open-end windings of induction motor, supplied by several voltage source inverters. MATLAB-based simulation of processes in this system has been executed. It has been shown, that the use of algorithms of synchronous modulation provides symmetry of phase voltage waveforms for any ratio between the switching frequency and fundamental frequency, and for any voltage magnitudes of dc-sources. Spectra of the phase voltage of system do not contain even harmonics and subharmonics (of the fundamental frequency, which is especially important for drives for the medium-power and high-power electric vehicles.

FISH & CHIPS: Single Chip Silicon MEMS CTDL Salinity, Temperature, Pressure and Light sensor for use in fisheries research

DEFF Research Database (Denmark)