A high-resolution TDC-based board for a fully digital trigger and data acquisition system in the NA62 experiment at CERN

CERN Document Server

Pedreschi, Elena; Angelucci, Bruno; Avanzini, Carlo; Galeotti, Stefano; Lamanna, Gianluca; Magazzù, Guido; Pinzino, Jacopo; Piandani, Roberto; Sozzi, Marco; Spinella, Franco; Venditti, Stefano

2015-01-01

A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB board developed by the Pisa NA62 group are extensively discussed and performance data is presented in order to show its compliance with the experiment requirements.

Old PCs: Upgrade or Abandon?

Science.gov (United States)

Perez, Ernest

1997-01-01

Examines the practical realities of upgrading Intel personal computers in libraries, considering budgets and technical personnel availability. Highlights include adding RAM; putting in faster processor chips, including clock multipliers; new hard disks; CD-ROM speed; motherboards and interface cards; cost limits and economic factors; and…

Demonstration of Experimental Infrastructure for Studying Cell-to-Cell Failure Propagation in Lithium-Ion Batteries

Science.gov (United States)

2014-09-11

Newegg.com Sabertooth 990 FX BIOS AM3+ Socket Motherboard ASUS Newegg.com GeForce GTX 550 Ti 1 GB 2-Channel Graphics Card Nvidia Newegg.com...Analytical Instruments, Orange, California, USA) and an in-situ Fourier Transform Infrared (FTIR) Spectrometer (I-Series, MIDAC Corporation , Westfield

Temperature studies of the TileCal ROD G-Links for the validation of the air-cooling system

CERN Document Server

Valero, A; Abdallah, J; Castillo, V; Cuenca, C; Ferrer, A; Fullana, E; González, V; Higón, E; Munar, A; Poveda, J; Salvachúa, B; Sanchis, E; Solans, C; Torres, J; Valls, J A

2007-01-01

In this paper we show the results of the temperature studies performed on the TileCal ROD G-Links in order to validate the air-cooling system. In the first part of the note we present results on the characterization tests of the temperature monitor system for the G-Link chips of the TileCal ROD motherboard, performed at IFIC-Valencia. We report on the performance of the temperature behavior system and some cooling studies of a single ROD motherboard. We conclude that the present system can be successfully used to online monitor the temperature of the ROD G-Links. In the second part we show the results of the studies performed with multiple RODs in a standard 9U VME crate in the laboratory at IFIC, and in their final location in the ATLAS cavern. We conclude that the air-cooling provided by the standard VME crate fans is enough to keep the temperature of the G-Links well within specifications.

TRIGGER

CERN Multimedia

Wesley Smith

Level-1 Trigger Hardware and Software The trigger synchronization procedures for running with cosmic muons and operating with the LHC were reviewed during the May electronics week. Firmware maintenance issues were also reviewed. Link tests between the new ECAL endcap trigger concentrator cards (TCC48) and the Regional Calorimeter Trigger have been performed. Firmware for the energy sum triggers and an upgraded tau trigger of the Global Calorimeter Triggers has been developed and is under test. The optical fiber receiver boards for the Track-Finder trigger theta links of the DT chambers are now all installed. The RPC trigger is being made more robust by additional chamber and cable shielding and also by firmware upgrades. For the CSC’s the front-end and trigger motherboard firmware have been updated. New RPC patterns and DT/CSC lookup tables taking into account phi asymmetries in the magnetic field configuration are under study. The motherboard for the new pipeline synchronizer of the Global Trigg...

Streaming Media

Science.gov (United States)

Pulley, John

2009-01-01

At a time when the evolutionary pace of new media resembles the real-time mutation of certain microorganisms, the age-old question of how best to connect with constituents can seem impossibly complex--even for an elite institution plugged into the motherboard of Silicon Valley. Identifying the most effective vehicle for reaching a particular…

Development of the Special Operations Combat Management System

Science.gov (United States)

1999-08-01

Distribution Unlimited Prepared for U. S. Army Soldier and Biological Chemical Command Soldier Systems Center Natick, Massachusetts 01760-5020 19990826 022...Army Soldier and Biological Chemical Command, Soldier Systems Center, ATTN: AMSSB-RSS-D(N) (H. Girolamo), Natick, MA 01760-5020 14. ABSTRACT The...system design, integration and test. American Megatrends Inc. provided the motherboard circuit design, layout and production. Tactical Technologies Inc

Digital beam position monitor for the HAPPEX experiment

International Nuclear Information System (INIS)

Sherlon Kauffman; John Musson; Hai Dong; Lisa Kaufman; Arne Freyberger

2005-01-01

The proposed HAPPEX experiment at CEBAF employs a three cavity monitor system for high precision (1um), high bandwidth (100 kHz) position measurements. This is performed using a cavity triplet consisting of two TM110-mode cavities (one each for X and Y planes) combined with a conventional TM010-mode cavity for a phase and magnitude reference. Traditional systems have used the TM010 cavity output to directly down convert the BPM cavity signals to base band. The multi-channel HAPPEX digital receiver simultaneously I/Q samples each cavity and extracts position using a CORDIC algorithm. The hardware design consists of a RF receiver daughter board and a digital processor motherboard that resides in a VXI crate. The daughter board down converts 1.497 GHz signals from the TM010 cavity and X and Y signals from the TM110 cavities to 3 MHz and extracts the quadrature digital signals. The motherboard processes this data and computes beam intensity and X-Y positions with resolution of 1um, 100 kHz output bandwidth, and overall latency of 1us. The results are available in both the analog and digital format

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

Science.gov (United States)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

Science.gov (United States)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

Development and implementation of quality control strategies for CMS silicon strip tracker modules

International Nuclear Information System (INIS)

Dirkes, G.

2003-01-01

The CMS group in Karlsruhe is involved in the construction of the silicon trackers end-caps and will produce and qualify the 1 600 modules of ring 5. Therefore automatic test systems for module qualification are developed and test strategies are worked out. For the electrical tests a complete readout system is developed, based on readout modules available within the collaboration and extended by home build modules. These are based on a modular approach with less complex functional units attached to a motherboard and includes key functionalities like clock and trigger generation and their distribution, high and low voltage supply and test signal generation usable with lasers or infrared LEDs. The motherboard is connected to a standard PC, hosting a fast ADC, interface cards to the motherboard and the front-end electronics. Already during the R and D phase of this readout system, first prototype tests were performed and some weak points of the design were uncovered, resulting in changes of the electronics design of the front end hybrids. Two test stations are built. The first one focuses on a fast functionality test, which includes an active thermal cycle with readout at -10 C performed for each individual module. The other test station focuses on debugging and repair requirements. It disposes of sufficient space for a flexible use of the system, including the possibility of additional test options with lasers, radioactive sources, probes and LEDs. For quality control measurements at module level it turned out, that LEDs are of good use: Besides external signal generation by running them in a pulsed way, they can be used for constant illumination of sensors, inducing an artificial leakage current. This led to the discovery of gain losses of complete readout chips induced by shorted AC coupling capacitances of several readout channels, which are called pinholes. Therefore pinholes must be unbonded from the front end preamplifier, which requires faultless

Maslow and Motherboards: Taking a Hierarchical View of Technology Planning.

Science.gov (United States)

Johnson, Doug

2003-01-01

Presents a planning model for educational uses of technology that is based on Maslow's hierarchy of needs. Topics include established infrastructure; effective administration; extensive resources; enhanced teaching, including creating distance learning opportunities; empowered students, including evaluation methods and information literacy skills;…

FingerScanner: Embedding a Fingerprint Scanner in a Raspberry Pi

Directory of Open Access Journals (Sweden)

Jordi Sapes

2016-02-01

Full Text Available Nowadays, researchers are paying increasing attention to embedding systems. Cost reduction has lead to an increase in the number of platforms supporting the operating system Linux, jointly with the Raspberry Pi motherboard. Thus, embedding devices on Raspberry-Linux systems is a goal in order to make competitive commercial products. This paper presents a low-cost fingerprint recognition system embedded into a Raspberry Pi with Linux.

WORK SYSTEM ANALYSIS OF POWER SUPPLY IN OPTIMIZING ELECTRICITY ON PERSONAL COMPUTER (PC

Directory of Open Access Journals (Sweden)

Sudarmaji Sudarmaji

2017-12-01

Full Text Available Working Principles DC Power Supply - is an energy source for a computer to operate. The power supply changes the current from AC 110 volts to 60Hz or 220 volts 50Hz to DC + 3.3 volts, +5 volts and + 12 volts. Power Supply must carry a good and stable DC power supply so the system can run well. Tools running on the voltage supplied by the onboard voltage regulator, for example RIMM and RIMM require 2.5 volts while AGP AX and cards require 1.5 volts, both supplied by the onboard regulator of the motherboard. In addition to supplying power, the Power Supply can prevent the computer from starting until a Power Supply voltage exists at a predetermined area. Power Good is a sign of a special test that is sent to the motherboard as an active signal on the computer, usually marked by a green light when the power button is pressed. The current issued by the Power Supply is a direct current (DC, power output is composed of 200 watts, 250 watts, 300 watts, 350 watts, 400 watts to 600 watts. Computers with Intel Pentium 4 processors and above use power of 380 watts to 450 watts. Keywords: Power Supply, Computer, DC, Power Good, and volt

The MOBO City: A Mobile Game Package for Technical Language Learning

OpenAIRE

Faranak Fotouhi-Ghazvini; Rae Earnshaw; David Robison; Peter Excell

2009-01-01

In this research we produced a mobile language learning game that is designed within a technical context. After conceptual analysis of the subject matter i.e. computer’s motherboard, the game was designed. The action within the game is consistent to the theme. There is a story, simplifying and exaggerating real life. Elements of control, feedback and sense of danger are incorporated into our game. By producing an engaging learning experience, vocabularies were learned incidentally. Deliberate...

Changes in the Arctic: Background and Issues for Congress

Science.gov (United States)

2017-01-05

monitored on an ongoing basis.” 237 Canada’s stated priorities for its chairmanship are intended to benefit the 4 million people of the north through...Arctic, and ordered the development by 2014 of a strategic command in the region. However, as noted above, in order to reap the economic benefits of...motherboard.vice.com), June 15, 2016; Gerard O’Dwyer, “9.8% Budget Hike Set for Norwegian Armed Forces,” Defense News, October 9, 2015; Lydia Tomkiw

PC-based digital feedback control for scanning force microscope

International Nuclear Information System (INIS)

Mohd Ashhar Khalid

2002-01-01

In the past, most digital feedback implementation for scanned-probe microscope were based on a digital signal processor (DSP). At present DSP plug-in card with the input-output interface module is still expensive compared to a fast pentium PC motherboard. For a magnetic force microscope (MFM) digital feedback has an advantage where the magnetic signal can be easily separated from the topographic signal. In this paper, a simple low-cost PC-based digital feedback and imaging system for Scanning Force Microscope (SFM) is presented. (Author)

CompTIA A+ certification all-in-one for dummies

CERN Document Server

Clarke, Glen E

2012-01-01

Comprehensive coverage of everything you must know to pass CompTIA's A+ exam A+ is the gateway certification into many IT careers, and interest in certification is exploding. This bestselling A+ certification guide is updated to cover the new A+ exam. It includes the new Windows coverage and reflects the revised emphasis on objectives. Nine minibooks focus individually on specific hardware and OS characteristics including installation and configuration, diagnostics, preventive maintenance, motherboard and processors, printers, networking, and fundamentals. A companion website contains the popu

Opportunist combination of electronic technologies for real time calculations in the Tore Supra Tokamak

International Nuclear Information System (INIS)

Barbuti, A.; Gil, C.; Pastor, P.; Spuig, P.; Vincent, B.; Volpe, D.

2013-06-01

The Tore Supra tokamak real-time plasma control is based on measurements coming from various diagnostics. The complexity of all the events that occur during plasma is at the origin of measurements disturbances which have to be corrected in real time in order to ensure an optimal control. The signal correction does not just mean processing but requires complex algorithms. Electronics does not only need to process and adapt electrical signals, but it has to include corrections by mathematical calculation. The FPGA (field-programmable gate array) technology, with the help of basic adapted electronics, allows integrating the entire real time calculation and digital data transmission on the network. FMC (FPGA Mezzanine Card) coupled with in-house motherboard, which is used both as the interface with Tore Supra specific systems and as the support for other signals processing options, is the perfect answer to this request. The FMC includes a FPGA, memory, Ethernet port and multiple I/O for interfacing with the motherboard and Tore Supra signals. The algorithms are developed in VHDL (Very high speed integrated circuit Hardware Description Language), parallel process management that promotes faster calculation than a common μC (Micro-controller) in one clock pulse. The flexibility, the low cost and the implementation speed allow fitting a large number of various applications in fields where no 'off-theshelf' component can be found. And more specifically, in research and experimentation, algorithms can be continuously improved or modified for new requirements. (authors)

Physical packaging and organization of the drift chamber electronics system for the Stanford Large Detector

International Nuclear Information System (INIS)

Haller, G.M.; Freytag, M.L.; Mazaheri, G.; Olsen, J.; Paffrath, L.

1990-10-01

In this paper the logical organization, physical packaging, and operation of the drift chamber electronics for the SLD at SLAC is described. The system processes signals from approximately 7000 drift wires and is unusual in that most electronic functions are packaged on printed circuit boards within the detector. The circuits reside on signal-processing motherboards, controller boards, signal-transition boards, power-distribution boards, and fiber-optics-to-electrical conversion boards. The interaction and interconnection of these boards with respect to signal and control flow are presented. 11 refs., 7 figs

The MOBO City: A Mobile Game Package for Technical Language Learning

Directory of Open Access Journals (Sweden)

Faranak Fotouhi-Ghazvini

2009-04-01

Full Text Available In this research we produced a mobile language learning game that is designed within a technical context. After conceptual analysis of the subject matter i.e. computer’s motherboard, the game was designed. The action within the game is consistent to the theme. There is a story, simplifying and exaggerating real life. Elements of control, feedback and sense of danger are incorporated into our game. By producing an engaging learning experience, vocabularies were learned incidentally. Deliberate vocabulary learning games were also added to our package to help students solve their common errors.

Packaging of microwave integrated circuits operating beyond 100 GHz

Science.gov (United States)

Samoska, L.; Daniel, E.; Sokolov, V.; Sommerfeldt, S.; Bublitz, J.; Olson, K.; Gilbert, B.; Chow, D.

2002-01-01

Several methods of packaging high speed (75-330 GHz) InP HEMT MMIC devices are discussed. Coplanar wirebonding is presented with measured insertion loss of less than 0.5dB and return loss better than -17 dB from DC to 110 GHz. A motherboard/daughterboard packaging scheme is presented which supports minimum loss chains of MMICs using this coplanar wirebonding method. Split waveguide block packaging approaches are presented in G-band (140-220 GHz) with two types of MMIC-waveguide transitions: E-plane probe andantipodal finline.

Primer printed circuit boards

CERN Document Server

Argyle, Andrew

2009-01-01

Step-by-step instructions for making your own PCBs at home. Making your own printed circuit board (PCB) might seem a daunting task, but once you master the steps, it's easy to attain professional-looking results. Printed circuit boards, which connect chips and other components, are what make almost all modern electronic devices possible. PCBs are made from sheets of fiberglass clad with copper, usually in multiplelayers. Cut a computer motherboard in two, for instance, and you'll often see five or more differently patterned layers. Making boards at home is relatively easy

The fast neutron SEU cross section of a 4 Mb SRAM memory

International Nuclear Information System (INIS)

Pereira Junior, Evaldo C.F.; Goncalez, Odair L.; Cruz, Marco Aurelio da; Prado, Adriane Cristina Mendes; Federico, Claudio Antonio; Gaspar, Felipe de Barros

2013-01-01

The results of a static test of single event upset (SEU) produced by fast neutrons on an ISSI 4Mb SRAM memory are reported in this work. To perform the tests, it was built a platform based on a motherboard which is controlled by microprocessor, whose function is to perform the writing, reading and control of the memories under irradiation. The irradiation was performed with a set of 8 241 Am-Be neutrons source in a quasi-isotropic incidence. The SEU cross was calculated from the accumulated bit flip count. (author)

Reproducing the Motherboard: The Invisible Labor of Discourses That Gender Digital Fields

Science.gov (United States)

Greenhalgh-Spencer, Heather

2017-01-01

Within the digital workforce, women are disappearing. While there are many factors that could be "blamed" for this phenomenon, this article takes issue with the sexist and patriarchal discourses that are deployed within the digital workforce. In many ways, sexist discourses are taken for granted within the digital workplace; and in that…

Experience from design, prototyping and production of a DC–DC conversion powering scheme for the CMS Phase-1 Pixel Upgrade

Energy Technology Data Exchange (ETDEWEB)

Feld, Lutz, E-mail: Lutz.Feld@cern.ch; Karpinski, Waclaw; Klein, Katja; Lipinski, Martin; Preuten, Marius; Rauch, Max; Schmitz, Stefan; Wlochal, Michael

2017-02-11

The CMS pixel detector will be replaced during the technical stop 2016/2017. To allow the new pixel detector to be powered with the legacy cable plant and power supplies, a novel powering scheme based on DC–DC conversion will be employed. After the successful conclusion of an extensive development and prototyping phase, mass production of 1800 DC–DC converters as well as motherboards and other power PCBs has now been completed. This contribution reviews the lessons learned from the development of the power system for the Phase-1 pixel detector, and summarizes the experience gained from the production phase.

New RPC front-end electronics for hades

CERN Document Server

Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

2007-01-01

Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

A compact 16-module camera using 64-pixel CsI(Tl)/Si p-i-n photodiode imaging modules

Science.gov (United States)

Choong, W.-S.; Gruber, G. J.; Moses, W. W.; Derenzo, S. E.; Holland, S. E.; Pedrali-Noy, M.; Krieger, B.; Mandelli, E.; Meddeler, G.; Wang, N. W.; Witt, E. K.

2002-10-01

We present a compact, configurable scintillation camera employing a maximum of 16 individual 64-pixel imaging modules resulting in a 1024-pixel camera covering an area of 9.6 cm/spl times/9.6 cm. The 64-pixel imaging module consists of optically isolated 3 mm/spl times/3 mm/spl times/5 mm CsI(Tl) crystals coupled to a custom array of Si p-i-n photodiodes read out by a custom integrated circuit (IC). Each imaging module plugs into a readout motherboard that controls the modules and interfaces with a data acquisition card inside a computer. For a given event, the motherboard employs a custom winner-take-all IC to identify the module with the largest analog output and to enable the output address bits of the corresponding module's readout IC. These address bits identify the "winner" pixel within the "winner" module. The peak of the largest analog signal is found and held using a peak detect circuit, after which it is acquired by an analog-to-digital converter on the data acquisition card. The camera is currently operated with four imaging modules in order to characterize its performance. At room temperature, the camera demonstrates an average energy resolution of 13.4% full-width at half-maximum (FWHM) for the 140-keV emissions of /sup 99m/Tc. The system spatial resolution is measured using a capillary tube with an inner diameter of 0.7 mm and located 10 cm from the face of the collimator. Images of the line source in air exhibit average system spatial resolutions of 8.7- and 11.2-mm FWHM when using an all-purpose and high-sensitivity parallel hexagonal holes collimator, respectively. These values do not change significantly when an acrylic scattering block is placed between the line source and the camera.

Failure analysis on false call probe pins of microprocessor test equipment

Science.gov (United States)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

Research and development of common DAQ platform

International Nuclear Information System (INIS)

Higuchi, T.; Igarashi, Y.; Nakao, M.; Suzuki, S.Y.; Tanaka, M.; Nagasaka, Y.; Varner, G.

2003-01-01

The upgrade of the KEKB accelerator toward L=10 35 cm -2 s -1 requires an upgrade of the Belle data acquisition system. To match the market trend, we develop a DAQ platform based on the PCI bus that enables fastest DAQ with longer lifetime of the system. The platform is a VME-9U motherboard comprising of four slots for signal digitization modules and three PMC slots to house CPU for data compression. The platform is equipped with event FIFOs for data buffering to minimize the dead-time. A trigger module residing on VME-6U size rear board is connected to the 9U board via PCI-PCI bridge to make an interrupt for the CPU upon the level-1 trigger. (author)

Design of a search and rescue terminal based on the dual-mode satellite and CDMA network

Science.gov (United States)

Zhao, Junping; Zhang, Xuan; Zheng, Bing; Zhou, Yubin; Song, Hao; Song, Wei; Zhang, Meikui; Liu, Tongze; Zhou, Li

2010-12-01

The current goal is to create a set of portable terminals with GPS/BD2 dual-mode satellite positioning, vital signs monitoring and wireless transmission functions. The terminal depends on an ARM processor to collect and combine data related to vital signs and GPS/BD2 location information, and sends the message to headquarters through the military CDMA network. It integrates multiple functions as a whole. The satellite positioning and wireless transmission capabilities are integrated into the motherboard, and the vital signs sensors used in the form of belts communicate with the board through Bluetooth. It can be adjusted according to the headquarters' instructions. This kind of device is of great practical significance for operations during disaster relief, search and rescue of the wounded in wartime, non-war military operations and other special circumstances.

Acquisition system for the CLIC Module

CERN Document Server

Vilalte, Sebastien

2011-01-01

The status of R&D activities for CLIC module acquisition are discussed [1]. LAPP is involved in the design of the local CLIC module acquisition crate, described in the document Study of the CLIC Module Front-End Acquisition and Evaluation Electronics [2]. This acquisition system is a project based on a local crate, assigned to the CLIC module, including several mother boards. These motherboards are foreseen to hold mezzanines dedicated to the different subsystems. This system has to work in radiation environment. LAPP is involved in the development of Drive Beam stripline position monitors read-out, described in the document Drive Beam Stripline BPM Electronics and Acquisition [3]. LAPP also develops a generic acquisition mezzanine that allows to perform all-around acquisition and components tests for drive beam stripline BPM read-out.

Beam Tests of a New Digital Beam Control System for the CERN LEIR Accelerator

CERN Document Server

Angoletta, Maria Elena; Blas, Alfred; De Long, Joseph; Findlay, Alan; Matuszkiewicz, Pawel; Pedersen, Flemming; Salom-Sarasqueta, Angela

2005-01-01

The Low Energy Ion Ring (LEIR) is a major component in the Large Hadron Collider ion injector chain. We have been developing an all-digital beam control and cavity servo system for the RF acceleration in LEIR. The system is housed by VME motherboards that may hold various daughter boards. Fast tasks are executed in Field Programmable Gate Arrays (FPGAs), slower tasks and communication with the software layer above are achieved in Digital Signal Processors (DSPs). We describe a simplified system prototype, which we tested with low intensity beams on the CERN PS Booster (PSB). The aim was to verify the combined DSP+FPGA architecture and the feedback loop dynamics. An additional goal was to deploy and validate novel software concepts, such as reference-functions and timings generation, and user-selectable digital data acquisition.

The Monitor System for the LHCb on-line farm

CERN Document Server

Bonifazi, F; Carbone, A; Galli, D; Gregori, D; Marconi, U; Peco, G; Vagnoni, V

2005-01-01

The aim of the LHCb on-line farm Monitor System is to keep under control all the working indicators which are relevant for the farm operation, and to set the appropriate alarms whenever an error or a critical condition comes up. Since the most stressing tasks of the farm are the data transfer and processing, relevant indicators includes the CPU and the memory load of the system, the network interface and the TCP/IP stack parameters, the rates of the interrupts raised by the network interface card and the detailed status of the running processes. The monitoring of computers’ physical conditions (temperatures, fan speeds and motherboard voltages) are the subject of a separate technical note, since they are accessed in a different way, by using the IPMI protocol.

Advanced Spacesuit Portable Life Support System Packaging Concept Mock-Up Design & Development

Science.gov (United States)

O''Connell, Mary K.; Slade, Howard G.; Stinson, Richard G.

1998-01-01

A concentrated development effort was begun at NASA Johnson Space Center to create an advanced Portable Life Support System (PLSS) packaging concept. Ease of maintenance, technological flexibility, low weight, and minimal volume are targeted in the design of future micro-gravity and planetary PLSS configurations. Three main design concepts emerged from conceptual design techniques and were carried forth into detailed design, then full scale mock-up creation. "Foam", "Motherboard", and "LEGOtm" packaging design concepts are described in detail. Results of the evaluation process targeted maintenance, robustness, mass properties, and flexibility as key aspects to a new PLSS packaging configuration. The various design tools used to evolve concepts into high fidelity mock ups revealed that no single tool was all encompassing, several combinations were complimentary, the devil is in the details, and, despite efforts, many lessons were learned only after working with hardware.

Proof of concept of an imaging system demonstrator for PET applications with SiPM

International Nuclear Information System (INIS)

Morrocchi, Matteo; Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria; Collazuol, Gianmaria; Ambrosi, Giovanni; Santoni, Cristiano; Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito; Sportelli, Giancarlo; Guerra, Pedro; Santos, Andres; Del Guerra, Alberto

2013-01-01

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence

Proof of concept of an imaging system demonstrator for PET applications with SiPM

Energy Technology Data Exchange (ETDEWEB)

Morrocchi, Matteo, E-mail: matteo.morrocchi@pi.infn.it [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Marcatili, Sara; Belcari, Nicola; Giuseppina Bisogni, Maria [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Collazuol, Gianmaria [INFN Sezione di Pisa, Pisa 56127 (Italy); Ambrosi, Giovanni; Santoni, Cristiano [INFN Sezione di Perugia, Perugia 06100 (Italy); Corsi, Francesco; Foresta, Maurizio; Marzocca, Cristoforo; Matarrese, Gianvito [Politecnico di Bari and INFN Sezione di Bari, Bari 70100 (Italy); Sportelli, Giancarlo [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy); Guerra, Pedro; Santos, Andres [Universidad Politecnica de Madrid, E 28040 Madrid (Spain); Centro de Investigación Biomédica en Red en Bioingeniería, Biomateriales y Nanomedicina (CIBER-BBN) (Spain); Del Guerra, Alberto [University of Pisa and INFN Sezione di Pisa, Pisa 56127 (Italy)

2013-08-21

A PET imaging system demonstrator based on LYSO crystal arrays coupled to SiPM matrices is under construction at the University and INFN of Pisa. Two SiPM matrices, composed of 8×8 SiPM pixels, and 1,5 mm pitch, have been coupled one to one to a LYSO crystals array and read out by a custom electronics system. front-end ASICs were used to read 8 channels of each matrix. Data from each front-end were multiplexed and sent to a DAQ board for the digital conversion; a motherboard collects the data and communicates with a host computer through a USB port for the storage and off-line data processing. In this paper we show the first preliminary tomographic image of a point-like radioactive source acquired with part of the two detection heads in time coincidence.

A structure-based approach to evaluation product adaptability in adaptable design

International Nuclear Information System (INIS)

Cheng, Qiang; Liu, Zhifeng; Cai, Ligang; Zhang, Guojun; Gu, Peihua

2011-01-01

Adaptable design, as a new design paradigm, involves creating designs and products that can be easily changed to satisfy different requirements. In this paper, two types of product adaptability are proposed as essential adaptability and behavioral adaptability, and through measuring which respectively a model for product adaptability evaluation is developed. The essential adaptability evaluation proceeds with analyzing the independencies of function requirements and function modules firstly based on axiomatic design, and measuring the adaptability of interfaces secondly with three indices. The behavioral adaptability reflected by the performance of adaptable requirements after adaptation is measured based on Kano model. At last, the effectiveness of the proposed method is demonstrated by an illustrative example of the motherboard of a personal computer. The results show that the method can evaluate and reveal the adaptability of a product in essence, and is of directive significance to improving design and innovative design

Real-time image reconstruction and display system for MRI using a high-speed personal computer.

Science.gov (United States)

Haishi, T; Kose, K

1998-09-01

A real-time NMR image reconstruction and display system was developed using a high-speed personal computer and optimized for the 32-bit multitasking Microsoft Windows 95 operating system. The system was operated at various CPU clock frequencies by changing the motherboard clock frequency and the processor/bus frequency ratio. When the Pentium CPU was used at the 200 MHz clock frequency, the reconstruction time for one 128 x 128 pixel image was 48 ms and that for the image display on the enlarged 256 x 256 pixel window was about 8 ms. NMR imaging experiments were performed with three fast imaging sequences (FLASH, multishot EPI, and one-shot EPI) to demonstrate the ability of the real-time system. It was concluded that in most cases, high-speed PC would be the best choice for the image reconstruction and display system for real-time MRI. Copyright 1998 Academic Press.

The DOe Silicon Track Trigger

International Nuclear Information System (INIS)

Steinbrueck, Georg

2003-01-01

We describe a trigger preprocessor to be used by the DOe experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam

Quicksilver Power Mac G4

CERN Document Server

2001-01-01

A new generation with a reworked motherboard is launched on 2001 with however the same Graphite box. It also included a processor speed-bump, and brought the DVD-R "SuperDrive" to the mid-level model. The Quicksilver PowerMac was available in three configurations: The 733 MHz model, with 128 MB of RAM, a 40 GB hard drive, and a CD-RW drive, was 1,699 dollars, the 867 MHz configuration, with 128 MB of RAM, a 60 GB hard drive and a DVD-R drive, was 2,499 dollars, and the high-end dual-800 MHz model, with 256 MB of RAM, an 80 GB hard drive and a DVD-R drive, was 3,499 dollars. The 733 MHz model is the first personal computer to have a DVD burner, named SuperDrive at Apple. The design was updated on 2002 with 800 MHz, 933 MHz and dual 1 GHz configurations, becoming the first Mac to reach 1 GHz.

Networked Attached Devices at SNS

CERN Document Server

Blokland, W

2003-01-01

The Spallation Neutron Source (SNS) diagnostic instruments at Oak Ridge National Laboratory are based on the Network Attached Device (NAD) concept. Each pickup or sensor has its own resources such as timing, data acquisition and processing. NADs are individually connected to the network, thus reducing the brittleness inherent in tightly coupled systems. This architecture allows an individual device to fail or to be serviced or removed without disrupting other devices. This paper describes our implementation of the nearly 400 NADs to be deployed. The hardware consists of rack-mounted PCs with standard motherboards and PCI data-acquisition boards. The software environment is based on LabVIEW and EPICS. LabVIEW supports the agile development demanded by modern diagnostic systems. EPICS is the control system standard for the entire SNS facility. To achieve high performance, LabVIEW and EPICS communicate through shared memory. SNS diagnostics are developed by a multi-laboratory partnership including ORNL, BNL, LAN...

Pigtailing of integrated optical components

DEFF Research Database (Denmark)

Zenth, Karin

2001-01-01

, but also a silicon motherboard for laser diode pigtailing and a Variable Optical Attenuator have been realized. The pigtailing method consists of three major parts: a waveguide chip with alignment trenches, a fiber array with alignment trenches, and a top plate with alignment rails. The top plate aligns....... The fiber array carrier and the top plate are fabricated by potassium hydroxide (KOH) etching. A method to align the mask pattern to the crystal orientation of the silicon substrate has been implemented. The impact of the etch of the nitride layer, used as an etch mask in KOH, on the line widths...... of the critical structures has been studied. The influence of the process parameters of a RIE etch process has been investigated with respect to the etch rate uniformity. After processing the variation of the line widths of the critical structures on the fiber array carrier and the top plate is determined...

The “Chimera”: An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform

Directory of Open Access Journals (Sweden)

Ra Inta

2012-01-01

Full Text Available The nature of modern astronomy means that a number of interesting problems exhibit a substantial computational bound and this situation is gradually worsening. Scientists, increasingly fighting for valuable resources on conventional high-performance computing (HPC facilities—often with a limited customizable user environment—are increasingly looking to hardware acceleration solutions. We describe here a heterogeneous CPU/GPGPU/FPGA desktop computing system (the “Chimera”, built with commercial-off-the-shelf components. We show that this platform may be a viable alternative solution to many common computationally bound problems found in astronomy, however, not without significant challenges. The most significant bottleneck in pipelines involving real data is most likely to be the interconnect (in this case the PCI Express bus residing on the CPU motherboard. Finally, we speculate on the merits of our Chimera system on the entire landscape of parallel computing, through the analysis of representative problems from UC Berkeley’s “Thirteen Dwarves.”

The Associative Memory Serial Link Processor of the ALTAS Fast TracKer Processing System

CERN Document Server

Sotiropoulou, Calliope Louisa; The ATLAS collaboration

2017-01-01

The upgraded Trigger and Data Acquisition (TDAQ) system of the ATLAS experiment at the LHC will improve the capability of the detector to select the events with the greatest scientific potential. The Fast TracKer (FTK) is one of the ATLAS TDAQ upgrades that is presently under commissioning. FTK is a custom hardware system that feeds the High Level Trigger (HLT) with charged particle tracks reconstructed from hits in silicon detectors at the rate of 105 events per second. The main processing element of FTK is the Associative Memory (AM) system that is used to perform pattern matching with a high degree of parallelism. Its implementation is called the AM Board Serial Link Processor (AMBSLP) and it is a very efficient pattern matching machine that handles in parallel massive data samples. The AMBSLP consists of two types of boards: the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard that hosts four LAMB daughter-boar...

Working with arrays of inexpensive EIDE disk drives

International Nuclear Information System (INIS)

Sanders, D.; Riley, C.; Cremaldi, L.; Summers, D.; Petravick, D.

2000-01-01

In today's marketplace, the cost per Terabyte of disks with EIDE interfaces is about a third that of disks with SCSI. Hence, three times as many particle physics events could be put online with EIDE. The modern EIDE interface includes many of the performance features that appeared earlier in SCSI. EIDE bus speeds approach 33 Megabytes/s and need only be shared between two disks rather than seven disks. The interal I/O rate of very fast (and expensive) SCSI disks is only 50% greater than EIDE disks. Hence, two EIDE disks whose combined cost is much less than one very fast SCSI disk can actually give more data throughput due to the advantage of multiple spindles and head actuators. The authors explore the use of 12 and 16 Gigabyte EIDE disks with motherboard and PCI bus card interfaces on a number of operating systems and CPUs. These include Red Hat Linux and Windows 95/98 on a Pentium, MacOS and Apple's Rhapsody/NeXT/UNIX on a PowerPC, and Sun Solaris on a UltraSparc 10 workstation

Introduction of innovations to Cuban Polarimeters

International Nuclear Information System (INIS)

Mora Mazorra, L. W.; Fajer Avila, V.; Arista Romeu, E.; Fernandez Lechuga, H.; Robaina Martinez, B.; Lizaso Menendez, E.

2012-01-01

It describes the changes made to the various circuits of electronic card system LASERPOL polarimeters. Modifications made to the hardware of the various circuits allowed to increase the accuracy of the instrument to improve the sensitivity and reproducibility of measurements consisted innovations changes in power, ramp generator circuit, low power and high voltage, redesign the motherboard, changes in the converter circuit, modulator circuit rationalization and ramp generator. This coupled with the addition of a new control board allows the use of the instrument in new applications such as use as polarimetric detector in a chromatographic system with data transmission to a PC for further analysis and processing. There were several changes from the mechanical viewpoint to avoid undesirable reflections that occur on the surface of the plates and introduced a device for, improving the fit of the sheet polarizer of the analyzer. These modifications have been performed on multiple computers satisfactory results for the exploitation of them for a period of several years, allowing an increase in the quality and competitiveness of the instrument. (Author)

Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

CERN Document Server

AUTHOR|(CDS)2068589; Rohrich, Dieter

2008-01-01

The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

A Novel Low-Cost Sensor Prototype for Monitoring Temperature during Wine Fermentation in Tanks

Directory of Open Access Journals (Sweden)

Carlos de Castro

2013-02-01

Full Text Available This paper presents a multipurpose and low cost sensor for temperature control over the wine fermentation process, in order to steadily communicate data through wireless modules in real time to a viticulturist’s mobile or fixed device. The advantage of our prototype is due to the fact that it will be used by small winemakers in the “Ribera del Duero” area, and as it is a cheaper sensor and easy to use for the control and monitoring of the grape fermentation process, it will probably be used by other business men with the same necessities in the region. The microcontroller MSP430G2553 is among the components that make up the sensor, that are integrated onto a motherboard. It communicates with the RN-42 Bluetooth module through an UART interface. After verifying that all elements are working correctly, the parts are assembled to form the final prototype. This device has been tested in a winery in the region, fulfilling the initial project specifications.

MANAGEMENT BOARD 11/06/07 (MB106)

CERN Multimedia

Progress and Schedule Three muon DTs had been commissioned underground using cosmics. The EB- insertion was complete. The first global run had taken place as planned. Difficulties had led to a 4 week delay in the installation of YB0 services which was on the critical path. Over 200k cosmic events had been recorded by the Tracker, operating at just below 0 degrees. About 3500 ECAL end-cap crystals had been delivered, and the schedule for the last delivery at the end of March 2008 had been agreed; this meant that the last end-cap Dee could not be installed before the end of June. The concerns with the schedule were the YB0 services installation, the ECAL end-caps schedule which had suffered from manpower being tied up by the Barrel motherboards replacement, the preshower schedule and that of the pixel detecxtor which should be ready for installation in January. There were no significant technical issues. Work must continue as fast and as safely as possible. A message had been received from the CERN Directo...

Highly Parallelized Pattern Matching Execution for the ATLAS Experiment

CERN Document Server

Citraro, Saverio; The ATLAS collaboration

2015-01-01

Abstract– The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using as input the data from the silicon tracker in the ATLAS experiment. The AM is the primary component of the FTK system and is designed using ASIC technology (the AM chip) to execute pattern matching with a high degree of parallelism. The FTK system finds track candidates at low resolution that are seeds for a full resolution track fitting. The AM system implementation is named “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links to sustain a huge traffic of data. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Little Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME motherboard which hosts four LAMB daughterboards. We also report on the performance of the prototypes (both hardware and firmware) produced and ...

Noise measurement on Preshower Si sensors

CERN Document Server

Evangelou, Ioannis; Barney, David; Bloch, Philippe; Elsha, Vladimir; Go, Apollo; Kloukinas, Kostas; Kokkas, Panagiotis; Manthos, Nikolaos; Peisert, Anna; Prouskas, C; Reynaud, Serge; Triantis, Frixos A; Tzoulis, Nikolaos; Zub, E

2002-01-01

Throughout the past couple of years when we were designing the Preshower silicon sensors we have noticed that some of them have strips with a noise higher than the average and not correlated to the leakage current. In order to investigate this effect we have developed a set-up for noise measurement on wafers and diced sensors that does not require bonding. The set-up is based on the DeltaStream chip coupled to a probe card with 32 pins at a pitch of 1.9 mm. All the digital electronics, including the analogue-to-digital converter and a microprocessor, is placed on a motherboard which communicates with a PC via an RS232 line. We have tested 45 sensors and found that some strips which have an above average noise, also have a higher relative current increase as a function of voltage, deltaI/(I deltaV), even though their leakage current is below 50 nA. We also observed that on these strips th e breakdown occurs within about 60 V from the onset of the noise. The source of this noise is not yet clear and the investi...

A methodology for achieving high-speed rates for artificial conductance injection in electrically excitable biological cells.

Science.gov (United States)

Butera, R J; Wilson, C G; Delnegro, C A; Smith, J C

2001-12-01

We present a novel approach to implementing the dynamic-clamp protocol (Sharp et al., 1993), commonly used in neurophysiology and cardiac electrophysiology experiments. Our approach is based on real-time extensions to the Linux operating system. Conventional PC-based approaches have typically utilized single-cycle computational rates of 10 kHz or slower. In thispaper, we demonstrate reliable cycle-to-cycle rates as fast as 50 kHz. Our system, which we call model reference current injection (MRCI); pronounced merci is also capable of episodic logging of internal state variables and interactive manipulation of model parameters. The limiting factor in achieving high speeds was not processor speed or model complexity, but cycle jitter inherent in the CPU/motherboard performance. We demonstrate these high speeds and flexibility with two examples: 1) adding action-potential ionic currents to a mammalian neuron under whole-cell patch-clamp and 2) altering a cell's intrinsic dynamics via MRCI while simultaneously coupling it via artificial synapses to an internal computational model cell. These higher rates greatly extend the applicability of this technique to the study of fast electrophysiological currents such fast a currents and fast excitatory/inhibitory synapses.

Vectronic's Power Macintosh G3 (B & W)

CERN Multimedia

1999-01-01

Apple introduced the Power Macintosh G3 Blue and White (B & W) on January 5, 1999. The Power Macintosh G3 line stayed in production until August 1999, and was replaced by the Power Macintosh G4, which used the same chassis. The Power Macintosh G3 originally cost between $1599 and $2900 depending on options. The three original Power Macintosh G3 models shipped with a 300 MHz, 350 MHz, or 400 MHz PowerPC 750 (G3) processor. Just pull on the small round handle on the side of the tower, and the entire side of the computer opens up. The G3's motherboard is mounted on that surface, giving you easy access for upgrading RAM or installed PCI cards. Apple added new ports (USB and the much-anticipated FireWire) that took the place of historic, and quickly becoming antiquated, Mac serial (printer and modem) ports. The Power Macintosh G3 has two USB (12 Mbps) ports, two FireWire (400 Mbps) ports, one 10/100BaseT Ethernet port, an RJ-11 jack for an optional 56K modem, a sound out and sound in jack, and one ADB (Apple D...

Penetration of High Intensity Radiated Fields (HIRF) Into General Aviation Aircraft

Science.gov (United States)

Balanis, Constantine A.; Birtcher, Craig R.; Georgakopoulos, Stavros V.; Panaretos, Anastasios H.

2004-01-01

The ability to design and achieve electromagnetic compatibility is becoming more challenging with the rapid development of new electronic products and technologies. The importance of electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues stems from the fact that the ambient electromagnetic environment has become very hostile; that is, it increases both in density and intensity, while the current trend in technology suggests the number of electronic devices increases in homes, businesses, factories, and transportation vehicles. Furthermore, the operating frequency of products coming into the market continuously increases. While cell phone technology has exceeded 1 GHz and Bluetooth operates at 2.4 GHz, products involving satellite communications operate near 10 GHz and automobile radar systems involve frequencies above 40 GHz. The concern about higher frequencies is that they correspond to smaller wavelengths, therefore electromagnetic waves are able to penetrate equipment enclosure through apertures or even small cracks more easily. In addition, electronic circuits have become small in size, and they are usually placed on motherboards or housed in boxes in very close proximity. Cosite interference and coupling in all electrical and electronic circuit assemblies are two essential issues that have to be examined in every design.

Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall

Science.gov (United States)

Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.

2010-10-01

A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m2, divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade .

The Front-End Electronics for the HADES RPC Wall (ESTRELA-FEE)

International Nuclear Information System (INIS)

Belver, D.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Lange, S.; Marin, J.; Montes, N.; Skott, P.; Traxler, M.; Zapata, M.

2006-01-01

A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m 2 with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most

PC based manual and safety logic card test setup for 235 MWe PHWRs

International Nuclear Information System (INIS)

Chandgadkar, G.M.; Kohli, A.K.; Agarwal, R.G.; Chandra, Rajesh

1992-01-01

Fuel handling controls for 235 MWe PHWR make use of Manual and Logic cards (MLCs) for providing safety interlocks. These cards consist of various type of logic blocks. By connecting these logic blocks all the safety interlocks required for fuel handling controls have been provided. Previously trouble shooting of these cards was done by means of logic probe. Since the method was manual, it was laborious and time consuming. PC based test setup has overcome this drawback and detects the fault at the component level within few seconds. It also gives printout of status of faulty MLC cards. Here motherboard has been designed having slots for insertion of MLC cards. The input/output connection of these cards are coming to two 50 pin FRC connectors. PC communicates through 144 line digital input/output card with MLC card under test. Software is user friendly and outputs suitable input patterns to the card under test and checks for output pattern. It compares this output pattern with compare pattern and detects the fault and displays the symptoms. This system is currently in use at test facility for fuelling machine for 235 MWe PHWR reactor at Refuelling Technology Division, Hall-7. This test setup has been proposed for use at NAPP and future reactors. (author). 4 figs., 1 annexure

The S-LINK in the data sources for trigger demonstrators in the LHC environment

International Nuclear Information System (INIS)

Hajduk, Z.; Iwanski, W.; Korcyl, K.; Olszowska, J.; Bij, H.C. van der

1998-01-01

The hardware for the data sources to be used in the ATLAS trigger demonstrator program has been designed and built. As a basic element, the SLATE2 module has been used. The S-LINK protocol, as a transferring data standard, has been chosen. A cheap implementation of the S-LINK, the Parallel Electrical S-LINK, has been built. Featuring all the specification laid down in the standard it uses a parallel twisted pair copper cable as a physical layer. A standard SCSI cable has been used. Both the Source and Destination Cards have the same PCB layout. The link may receive 32-bit wide data words at max 40 MHz input rate. Running with 40 MHz link clock, it outputs 32-bit data at a rate of 20 MHz, giving a total a bandwidth of 80 MB/s. The authors report on main characteristics of these implementations. The SLATE2SLINK cad has been built to interface the SLATE motherboard to the S-LINK environment. This daughter card is capable to house and independently control 3 S-LINK sites. Running with the 25 MHz SLATE's clock and 32-bit data, it features a total bandwidth up to 300 MB/s

A simple approach to a vision-guided unmanned vehicle

Science.gov (United States)

Archibald, Christopher; Millar, Evan; Anderson, Jon D.; Archibald, James K.; Lee, Dah-Jye

2005-10-01

This paper describes the design and implementation of a vision-guided autonomous vehicle that represented BYU in the 2005 Intelligent Ground Vehicle Competition (IGVC), in which autonomous vehicles navigate a course marked with white lines while avoiding obstacles consisting of orange construction barrels, white buckets and potholes. Our project began in the context of a senior capstone course in which multi-disciplinary teams of five students were responsible for the design, construction, and programming of their own robots. Each team received a computer motherboard, a camera, and a small budget for the purchase of additional hardware, including a chassis and motors. The resource constraints resulted in a simple vision-based design that processes the sequence of images from the single camera to determine motor controls. Color segmentation separates white and orange from each image, and then the segmented image is examined using a 10x10 grid system, effectively creating a low resolution picture for each of the two colors. Depending on its position, each filled grid square influences the selection of an appropriate turn magnitude. Motor commands determined from the white and orange images are then combined to yield the final motion command for video frame. We describe the complete algorithm and the robot hardware and we present results that show the overall effectiveness of our control approach.

A single-mode data acquisition architecture for PET/MRI

Energy Technology Data Exchange (ETDEWEB)

Sportelli, Giancarlo; Belcari, Nicola; Bisogni, Maria Giuseppina; Camarlinghi, Niccolo; Zaccaro, Emanuele; Del Guerra, Alberto [Department of Physics, University of Pisa and INFN, Pisa (Italy)

2015-05-18

The development of MRI compatible detectors based on compact solid state photomultipliers has recently led to simultaneous fully integrated PET/MRI systems for human imaging. The PET acquisition design for MRI integration is known to have several additional constraints, including smaller space, electromagnetic compatibility issues and thermal management. The current work presents the PET acquisition architecture that has been developed for the TRIMAGE project, whose aim is to provide a cost effective, commercial grade trimodality PET/MRI/EEG scanner. The TRIMAGE PET component consists of 216 modules of 2.5 cm x 2.5 cm, arranged in 18 rectangular detectors of 5 cm x 15 cm, the latter in the axial direction, to form a full ring of 31 cm diameter. Each module consists of a staggered dual layer LYSO matrix read out by two arrays of 4 x 8 SiPMs and an ASIC. The detector board hosts a low-power low-end FPGA that performs pixel identification, energy calibration and handles the communication between the ASICs and the motherboard, which is located in proximity of the scanner. Data is streamed using high-density shielded cables and high-speed LVDS transmission to 9 low-end SoC FPGAs and from there to a central mainboard where coincidences and events statistics are processed. Coincidence data is finally transmitted to a host PC for image reconstruction. The proposed architecture and technological solutions will be presented and discussed.

A compact, discrete CsI(Tl) scintillator/Si photodiode gamma camera for breast cancer imaging

Energy Technology Data Exchange (ETDEWEB)

Gruber, Gregory J. [Univ. of California, Berkeley, CA (United States)

2000-01-01

Recent clinical evaluations of scintimammography (radionuclide breast imaging) are promising and suggest that this modality may prove a valuable complement to X-ray mammography and traditional breast cancer detection and diagnosis techniques. Scintimammography, however, typically has difficulty revealing tumors that are less than 1 cm in diameter, are located in the medial part of the breast, or are located in the axillary nodes. These shortcomings may in part be due to the use of large, conventional Anger cameras not optimized for breast imaging. In this thesis I present compact single photon camera technology designed specifically for scintimammography which strives to alleviate some of these limitations by allowing better and closer access to sites of possible breast tumors. Specific applications are outlined. The design is modular, thus a camera of the desired size and geometry can be constructed from an array (or arrays) of individual modules and a parallel hole lead collimator for directional information. Each module consists of: (1) an array of 64 discrete, optically-isolated CsI(Tl) scintillator crystals 3 x 3 x 5 mm³ in size, (2) an array of 64 low-noise Si PIN photodiodes matched 1-to-1 to the scintillator crystals, (3) an application-specific integrated circuit (ASIC) that amplifies the 64 photodiode signals and selects the signal with the largest amplitude, and (4) connectors and hardware for interfacing the module with a motherboard, thereby allowing straightforward computer control of all individual modules within a camera.

A compact, discrete CsI(Tl) scintillator/Si photodiode gamma camera for breast cancer imaging

International Nuclear Information System (INIS)

Gruber, Gregory J.

2000-01-01

Recent clinical evaluations of scintimammography (radionuclide breast imaging) are promising and suggest that this modality may prove a valuable complement to X-ray mammography and traditional breast cancer detection and diagnosis techniques. Scintimammography, however, typically has difficulty revealing tumors that are less than 1 cm in diameter, are located in the medial part of the breast, or are located in the axillary nodes. These shortcomings may in part be due to the use of large, conventional Anger cameras not optimized for breast imaging. In this thesis I present compact single photon camera technology designed specifically for scintimammography which strives to alleviate some of these limitations by allowing better and closer access to sites of possible breast tumors. Specific applications are outlined. The design is modular, thus a camera of the desired size and geometry can be constructed from an array (or arrays) of individual modules and a parallel hole lead collimator for directional information. Each module consists of: (1) an array of 64 discrete, optically-isolated CsI(Tl) scintillator crystals 3 x 3 x 5 mm 3 in size, (2) an array of 64 low-noise Si PIN photodiodes matched 1-to-1 to the scintillator crystals, (3) an application-specific integrated circuit (ASIC) that amplifies the 64 photodiode signals and selects the signal with the largest amplitude, and (4) connectors and hardware for interfacing the module with a motherboard, thereby allowing straightforward computer control of all individual modules within a camera

A single-mode data acquisition architecture for PET/MRI

International Nuclear Information System (INIS)

Sportelli, Giancarlo; Belcari, Nicola; Bisogni, Maria Giuseppina; Camarlinghi, Niccolo; Zaccaro, Emanuele; Del Guerra, Alberto

2015-01-01

The development of MRI compatible detectors based on compact solid state photomultipliers has recently led to simultaneous fully integrated PET/MRI systems for human imaging. The PET acquisition design for MRI integration is known to have several additional constraints, including smaller space, electromagnetic compatibility issues and thermal management. The current work presents the PET acquisition architecture that has been developed for the TRIMAGE project, whose aim is to provide a cost effective, commercial grade trimodality PET/MRI/EEG scanner. The TRIMAGE PET component consists of 216 modules of 2.5 cm x 2.5 cm, arranged in 18 rectangular detectors of 5 cm x 15 cm, the latter in the axial direction, to form a full ring of 31 cm diameter. Each module consists of a staggered dual layer LYSO matrix read out by two arrays of 4 x 8 SiPMs and an ASIC. The detector board hosts a low-power low-end FPGA that performs pixel identification, energy calibration and handles the communication between the ASICs and the motherboard, which is located in proximity of the scanner. Data is streamed using high-density shielded cables and high-speed LVDS transmission to 9 low-end SoC FPGAs and from there to a central mainboard where coincidences and events statistics are processed. Coincidence data is finally transmitted to a host PC for image reconstruction. The proposed architecture and technological solutions will be presented and discussed.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a {sup 12}C beam

Energy Technology Data Exchange (ETDEWEB)

Belver, D. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)], E-mail: danielbf@usc.es; Cabanelas, P.; Castro, E. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Diaz, J. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Garzon, J.A. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Gil, A. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. [Gesellschaft fuer Schwerionenforschung, GSI, 64291 Darmstadt (Germany); Zapata, M. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m{sup 2} with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a {sup 12}C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

International Nuclear Information System (INIS)

Belver, D.; Cabanelas, P.; Castro, E.; Diaz, J.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-01-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m 2 with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12 C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

Science.gov (United States)

Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Integrated thermal control and system assessment in plug-chip spray cooling enclosure

International Nuclear Information System (INIS)

Zhang, Wei-Wei; Cheng, Wen-Long; Shao, Shi-Dong; Jiang, Li-Jia; Hong, Da-Liang

2016-01-01

Highlights: • A novel multi-heat source plug-chip spray cooling enclosure was designed. • Enhanced surfaces with different geometric were analyzed in integrated enclosure. • Overall thermal control with adjustable parameters in enclosure was studied. • Temperature disequilibrium of multi-heat source in enclosure was tested. • A comprehensive assessment system used to evaluate the practicality was proposed. - Abstract: Practical and integrated spray cooling system is urgently needed for the cooling of high-performance electronic chips due to the growth requirements of thermal management in workstation. The integration of multi heat sources and the management of integral system are particularly lacking. In order to fill the vacancies in the study of plug-chip spray cooling, an integrated cooling enclosure was designed in this paper. Multi heat sources were placed in sealed space and the heat was removed by spray. The printed circuit board plug-ins and radio frequency resistors were used as analog motherboards and chips, respectively. The enhanced surfaces with four different geometries and the plain surface were studied under the conditions of different inclination angles. The results were compared and the maximum critical heat flux (CHF) was obtained. Moreover, with the intention of the overall management of multi-heat source in integrated enclosure, the effect of the flow rate and the temperature disequilibrium, and the pulse heating in the process of transient cooling were also analyzed. In addition, a comprehensive assessment system, used to evaluate the practicality of spray cooling experimental devices, was proposed and the performance of enclosure was evaluated.

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

Science.gov (United States)

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Vacuum packaging of InGaAs focal plane array with four-stage thermoelectric cooler

Science.gov (United States)

Mo, De-feng; Liu, Da-fu; Yang, Li-yi; Xu, Qin-fei; Li, Xue

2013-09-01

The InGaAs focal plane array (FPA) detectors, covering the near-infrared 1~2.4 μm wavelength range, have been developed for application in space-based spectroscopy of the Earth atmosphere. This paper shows an all-metal vacuum package design for area array InGaAs detector of 1024×64 pixels, and its architecture will be given. Four-stage thermoelectric cooler (TEC) is used to cool down the FPA chip. To acquire high heat dissipation for TEC's Joule-heat, tungsten copper (CuW80) and kovar (4J29) is used as motherboard and cavity material respectively which joined by brazing. The heat loss including conduction, convection and radiation is analyzed. Finite element model is established to analyze the temperature uniformity of the chip substrate which is made of aluminum nitride (AlN). The performance of The TEC with and without heat load in vacuum condition is tested. The results show that the heat load has little influence to current-voltage relationship of TEC. The temperature difference (ΔT) increases as the input current increases. A linear relationship exists between heat load and ΔT of the TEC. Theoretical analysis and calculation show that the heat loss of radiation and conduction is about 187 mW and 82 mW respectively. Considering the Joule-heat of readout circuit and the heat loss of radiation and conduction, the FPA for a 220 K operation at room temperature can be achieved. As the thickness of AlN chip substrate is thicker than 1 millimeter, the temperature difference can be less than 0.3 K.

Modular and Reusable Power System Design for the BRRISON Balloon Telescope

Science.gov (United States)

Truesdale, Nicholas A.

High altitude balloons are emerging as low-cost alternatives to orbital satellites in the field of telescopic observation. The near-space environment of balloons allows optics to perform near their diffraction limit. In practice, this implies that a telescope similar to the Hubble Space Telescope could be flown for a cost of tens of millions as opposed to billions. While highly feasible, the design of a balloon telescope to rival Hubble is limited by funding. Until a prototype is proven and more support for balloon science is gained, projects remain limited in both hardware costs and man hours. Thus, to effectively create and support balloon payloads, engineering designs must be efficient, modular, and if possible reusable. This thesis focuses specifically on a modular power system design for the BRRISON comet-observing balloon telescope. Time- and cost-saving techniques are developed that can be used for future missions. A modular design process is achieved through the development of individual circuit elements that span a wide range of capabilities. Circuits for power conversion, switching and sensing are designed to be combined in any configuration. These include DC-DC regulators, MOSFET drivers for switching, isolated switches, current sensors and voltage sensing ADCs. Emphasis is also given to commercially available hardware. Pre-fabricated DC-DC converters and an Arduino microcontroller simplify the design process and offer proven, cost-effective performance. The design of the BRRISON power system is developed from these low-level circuits elements. A board for main power distribution supports the majority of flight electronics, and is extensible to additional hardware in future applications. An ATX computer power supply is developed, allowing the use of a commercial ATX motherboard as the flight computer. The addition of new capabilities is explored in the form of a heater control board. Finally, the power system as a whole is described, and its overall

A custom readout electronics for the BESIII CGEM detector

International Nuclear Information System (INIS)

Rolo, M. Da Rocha; Alexeev, M.; Amoroso, A.; Bianchi, F.; Cossio, F.; Mori, F. De; Destefanis, M.; Ferroli, R. Baldini; Chai, J.Y.; Bertani, M.; Calcaterra, A.; Capodiferro, M.; Cerioni, S.; Bettoni, D.; Canale, N.; Carassiti, V.; Chiozzi, S.; Cibinetto, G.; Ramusino, A. Cotta; Bugalho, R.

2017-01-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM

A custom readout electronics for the BESIII CGEM detector

Science.gov (United States)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

Performance of the ALIBAVA portable readout system with irradiated and non-irradiated microstrip silicon sensors

International Nuclear Information System (INIS)

Marco-Hernadez, R.

2009-01-01

A readout system for microstrip silicon sensors has been developed as a result of collaboration among the University of Liverpool, the CNM of Barcelona and the IFIC of Valencia. The name of this collaboration is ALIBAVA and it is integrated in the RD50 Collaboration. This system is able to measure the collected charge in one or two microstrip silicon sensors by reading out all the channels of the sensor(s), up to 256, as an analogue measurement. The system uses two Beetle chips to read out the detector(s). The Beetle chip is an analogue pipelined readout chip used in the LHCb experiment. The system can operate either with non-irradiated and irradiated sensors as well as with n-type and p-type microstrip silicon sensors. Heavily irradiated sensors will be used at the SLHC, so this system is being to research the performance of microstrip silicon sensors in conditions as similar as possible to the SLHC operating conditions. The system has two main parts: a hardware part and a software part. The hardware part acquires the sensor signals either from external trigger inputs, in case of a radioactive source setup is used, or from a synchronised trigger output generated by the system, if a laser setup is used. This acquired data is sent by USB to be stored in a PC for a further processing. The hardware is a dual board based system. The daughterboard is a small board intended for containing two Beetle readout chips as well as fan-ins and detector support to interface the sensors. The motherboard is intended to process the data, to control the whole hardware and to communicate with the software by USB. The software controls the system and processes the data acquired from the sensors in order to store it in an adequate format file. The main characteristics of the system will be described. Results of measurements acquired with n-type and p-type irradiated and non-irradiated detectors using both the laser and the radioactive source setup will be also presented and discussed

An Offload NIC for NASA, NLR, and Grid Computing

Science.gov (United States)

Awrach, James

2013-01-01

This work addresses distributed data management and access dynamically configurable high-speed access to data distributed and shared over wide-area high-speed network environments. An offload engine NIC (network interface card) is proposed that scales at nX10-Gbps increments through 100-Gbps full duplex. The Globus de facto standard was used in projects requiring secure, robust, high-speed bulk data transport. Novel extension mechanisms were derived that will combine these technologies for use by GridFTP, bandwidth management resources, and host CPU (central processing unit) acceleration. The result will be wire-rate encrypted Globus grid data transactions through offload for splintering, encryption, and compression. As the need for greater network bandwidth increases, there is an inherent need for faster CPUs. The best way to accelerate CPUs is through a network acceleration engine. Grid computing data transfers for the Globus tool set did not have wire-rate encryption or compression. Existing technology cannot keep pace with the greater bandwidths of backplane and network connections. Present offload engines with ports to Ethernet are 32 to 40 Gbps f-d at best. The best of ultra-high-speed offload engines use expensive ASICs (application specific integrated circuits) or NPUs (network processing units). The present state of the art also includes bonding and the use of multiple NICs that are also in the planning stages for future portability to ASICs and software to accommodate data rates at 100 Gbps. The remaining industry solutions are for carrier-grade equipment manufacturers, with costly line cards having multiples of 10-Gbps ports, or 100-Gbps ports such as CFP modules that interface to costly ASICs and related circuitry. All of the existing solutions vary in configuration based on requirements of the host, motherboard, or carriergrade equipment. The purpose of the innovation is to eliminate data bottlenecks within cluster, grid, and cloud computing systems

Storage-Intensive Supercomputing Benchmark Study

Energy Technology Data Exchange (ETDEWEB)

Cohen, J; Dossa, D; Gokhale, M; Hysom, D; May, J; Pearce, R; Yoo, A

2007-10-30

: SuperMicro X7DBE Xeon Dual Socket Blackford Server Motherboard; 2 Intel Xeon Dual-Core 2.66 GHz processors; 1 GB DDR2 PC2-5300 RAM (2 x 512); 80GB Hard Drive (Seagate SATA II Barracuda). The Fusion board is presently capable of 4X in a PCIe slot. The image resampling benchmark was run on a dual Xeon workstation with NVIDIA graphics card (see Chapter 5 for full specification). An XtremeData Opteron+FPGA was used for the language classification application. We observed that these benchmarks are not uniformly I/O intensive. The only benchmark that showed greater that 50% of the time in I/O was the graph algorithm when it accessed data files over NFS. When local disk was used, the graph benchmark spent at most 40% of its time in I/O. The other benchmarks were CPU dominated. The image resampling benchmark and language classification showed order of magnitude speedup over software by using co-processor technology to offload the CPU-intensive kernels. Our experiments to date suggest that emerging hardware technologies offer significant benefit to boosting the performance of data-intensive algorithms. Using GPU and FPGA co-processors, we were able to improve performance by more than an order of magnitude on the benchmark algorithms, eliminating the processor bottleneck of CPU-bound tasks. Experiments with a prototype solid state nonvolative memory available today show 10X better throughput on random reads than disk, with a 2X speedup on a graph processing benchmark when compared to the use of local SATA disk.

OpenMP GNU and Intel Fortran programs for solving the time-dependent Gross-Pitaevskii equation

Science.gov (United States)

Young-S., Luis E.; Muruganandam, Paulsamy; Adhikari, Sadhan K.; Lončar, Vladimir; Vudragović, Dušan; Balaž, Antun

2017-11-01

six different trap symmetries: axially and radially symmetric traps in 3d, circularly symmetric traps in 2d, fully isotropic (spherically symmetric) and fully anisotropic traps in 2d and 3d, as well as 1d traps, where no spatial symmetry is considered. Solution method: We employ the split-step Crank-Nicolson algorithm to discretize the time-dependent GP equation in space and time. The discretized equation is then solved by imaginary- or real-time propagation, employing adequately small space and time steps, to yield the solution of stationary and non-stationary problems, respectively. Reasons for the new version: Previously published Fortran programs [1,2] have now become popular tools [3] for solving the GP equation. These programs have been translated to the C programming language [4] and later extended to the more complex scenario of dipolar atoms [5]. Now virtually all computers have multi-core processors and some have motherboards with more than one physical computer processing unit (CPU), which may increase the number of available CPU cores on a single computer to several tens. The C programs have been adopted to be very fast on such multi-core modern computers using general-purpose graphic processing units (GPGPU) with Nvidia CUDA and computer clusters using Message Passing Interface (MPI) [6]. Nevertheless, previously developed Fortran programs are also commonly used for scientific computation and most of them use a single CPU core at a time in modern multi-core laptops, desktops, and workstations. Unless the Fortran programs are made aware and capable of making efficient use of the available CPU cores, the solution of even a realistic dynamical 1d problem, not to mention the more complicated 2d and 3d problems, could be time consuming using the Fortran programs. Previously, we published auto-parallel Fortran programs [2] suitable for Intel (but not GNU) compiler for solving the GP equation. Hence, a need for the full OpenMP version of the Fortran programs to